1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SPEC_CODE_1_8_3 0x10803
31 #define HWRM_VERSION_1_9_1 0x10901
32 #define HWRM_VERSION_1_9_2 0x10903
34 struct bnxt_plcmodes_cfg {
36 uint16_t jumbo_thresh;
38 uint16_t hds_threshold;
41 static int page_getenum(size_t size)
57 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
58 return sizeof(void *) * 8 - 1;
61 static int page_roundup(size_t size)
63 return 1 << page_getenum(size);
66 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
70 if (rmem->nr_pages > 1) {
72 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
74 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
79 * HWRM Functions (sent to HWRM)
80 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
81 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
82 * command was failed by the ChiMP.
85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
86 uint32_t msg_len, bool use_kong_mb)
89 struct input *req = msg;
90 struct output *resp = bp->hwrm_cmd_resp_addr;
94 uint16_t max_req_len = bp->max_req_len;
95 struct hwrm_short_input short_input = { 0 };
96 uint16_t bar_offset = use_kong_mb ?
97 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
98 uint16_t mb_trigger_offset = use_kong_mb ?
99 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
101 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
102 msg_len > bp->max_req_len) {
103 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
105 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
106 memcpy(short_cmd_req, req, msg_len);
108 short_input.req_type = rte_cpu_to_le_16(req->req_type);
109 short_input.signature = rte_cpu_to_le_16(
110 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
111 short_input.size = rte_cpu_to_le_16(msg_len);
112 short_input.req_addr =
113 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
115 data = (uint32_t *)&short_input;
116 msg_len = sizeof(short_input);
118 /* Sync memory write before updating doorbell */
121 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
124 /* Write request msg to hwrm channel */
125 for (i = 0; i < msg_len; i += 4) {
126 bar = (uint8_t *)bp->bar0 + bar_offset + i;
127 rte_write32(*data, bar);
131 /* Zero the rest of the request space */
132 for (; i < max_req_len; i += 4) {
133 bar = (uint8_t *)bp->bar0 + bar_offset + i;
137 /* Ring channel doorbell */
138 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
141 /* Poll for the valid bit */
142 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
143 /* Sanity check on the resp->resp_len */
145 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
146 /* Last byte of resp contains the valid key */
147 valid = (uint8_t *)resp + resp->resp_len - 1;
148 if (*valid == HWRM_RESP_VALID_KEY)
154 if (i >= HWRM_CMD_TIMEOUT) {
155 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
166 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
167 * spinlock, and does initial processing.
169 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
170 * releases the spinlock only if it returns. If the regular int return codes
171 * are not used by the function, HWRM_CHECK_RESULT() should not be used
172 * directly, rather it should be copied and modified to suit the function.
174 * HWRM_UNLOCK() must be called after all response processing is completed.
176 #define HWRM_PREP(req, type, kong) do { \
177 rte_spinlock_lock(&bp->hwrm_lock); \
178 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
179 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
180 req.cmpl_ring = rte_cpu_to_le_16(-1); \
181 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
182 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
183 req.target_id = rte_cpu_to_le_16(0xffff); \
184 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
187 #define HWRM_CHECK_RESULT_SILENT() do {\
189 rte_spinlock_unlock(&bp->hwrm_lock); \
192 if (resp->error_code) { \
193 rc = rte_le_to_cpu_16(resp->error_code); \
194 rte_spinlock_unlock(&bp->hwrm_lock); \
199 #define HWRM_CHECK_RESULT() do {\
201 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
202 rte_spinlock_unlock(&bp->hwrm_lock); \
203 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
209 if (resp->error_code) { \
210 rc = rte_le_to_cpu_16(resp->error_code); \
211 if (resp->resp_len >= 16) { \
212 struct hwrm_err_output *tmp_hwrm_err_op = \
215 "error %d:%d:%08x:%04x\n", \
216 rc, tmp_hwrm_err_op->cmd_err, \
218 tmp_hwrm_err_op->opaque_0), \
220 tmp_hwrm_err_op->opaque_1)); \
222 PMD_DRV_LOG(ERR, "error %d\n", rc); \
224 rte_spinlock_unlock(&bp->hwrm_lock); \
225 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
233 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
235 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
238 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
239 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
241 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
242 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
245 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
253 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
254 struct bnxt_vnic_info *vnic,
256 struct bnxt_vlan_table_entry *vlan_table)
259 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
260 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
263 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
266 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
267 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
269 /* FIXME add multicast flag, when multicast adding options is supported
272 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
273 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
274 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
275 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
276 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
277 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
278 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
279 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
280 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
281 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
282 if (vnic->mc_addr_cnt) {
283 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
284 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
285 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
288 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
289 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
290 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
291 rte_mem_virt2iova(vlan_table));
292 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
294 req.mask = rte_cpu_to_le_32(mask);
296 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
304 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
306 struct bnxt_vlan_antispoof_table_entry *vlan_table)
309 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
310 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
311 bp->hwrm_cmd_resp_addr;
314 * Older HWRM versions did not support this command, and the set_rx_mask
315 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
316 * removed from set_rx_mask call, and this command was added.
318 * This command is also present from 1.7.8.11 and higher,
321 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
322 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
323 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
328 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
329 req.fid = rte_cpu_to_le_16(fid);
331 req.vlan_tag_mask_tbl_addr =
332 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
333 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
335 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
343 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
344 struct bnxt_filter_info *filter)
347 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
348 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
350 if (filter->fw_l2_filter_id == UINT64_MAX)
353 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
355 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
362 filter->fw_l2_filter_id = UINT64_MAX;
367 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
369 struct bnxt_filter_info *filter)
372 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
373 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
374 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
375 const struct rte_eth_vmdq_rx_conf *conf =
376 &dev_conf->rx_adv_conf.vmdq_rx_conf;
377 uint32_t enables = 0;
378 uint16_t j = dst_id - 1;
380 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
381 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
382 conf->pool_map[j].pools & (1UL << j)) {
384 "Add vlan %u to vmdq pool %u\n",
385 conf->pool_map[j].vlan_id, j);
387 filter->l2_ivlan = conf->pool_map[j].vlan_id;
389 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
390 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
393 if (filter->fw_l2_filter_id != UINT64_MAX)
394 bnxt_hwrm_clear_l2_filter(bp, filter);
396 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
398 req.flags = rte_cpu_to_le_32(filter->flags);
400 rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
402 enables = filter->enables |
403 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
404 req.dst_id = rte_cpu_to_le_16(dst_id);
407 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
408 memcpy(req.l2_addr, filter->l2_addr,
411 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
412 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
415 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
416 req.l2_ovlan = filter->l2_ovlan;
418 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
419 req.l2_ivlan = filter->l2_ivlan;
421 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
422 req.l2_ovlan_mask = filter->l2_ovlan_mask;
424 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
425 req.l2_ivlan_mask = filter->l2_ivlan_mask;
426 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
427 req.src_id = rte_cpu_to_le_32(filter->src_id);
428 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
429 req.src_type = filter->src_type;
431 req.enables = rte_cpu_to_le_32(enables);
433 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
437 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
443 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
445 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
446 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
453 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
456 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
459 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
460 if (ptp->tx_tstamp_en)
461 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
464 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
465 req.flags = rte_cpu_to_le_32(flags);
466 req.enables = rte_cpu_to_le_32
467 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
468 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
470 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
476 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
479 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
480 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
481 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
483 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
487 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
489 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
491 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
495 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
498 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
502 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
503 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
504 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
505 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
506 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
507 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
508 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
509 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
510 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
511 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
512 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
513 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
514 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
515 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
516 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
517 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
518 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
519 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
527 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
530 struct hwrm_func_qcaps_input req = {.req_type = 0 };
531 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
532 uint16_t new_max_vfs;
536 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
538 req.fid = rte_cpu_to_le_16(0xffff);
540 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
544 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
545 flags = rte_le_to_cpu_32(resp->flags);
547 bp->pf.port_id = resp->port_id;
548 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
549 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
550 new_max_vfs = bp->pdev->max_vfs;
551 if (new_max_vfs != bp->pf.max_vfs) {
553 rte_free(bp->pf.vf_info);
554 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
555 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
556 bp->pf.max_vfs = new_max_vfs;
557 for (i = 0; i < new_max_vfs; i++) {
558 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
559 bp->pf.vf_info[i].vlan_table =
560 rte_zmalloc("VF VLAN table",
563 if (bp->pf.vf_info[i].vlan_table == NULL)
565 "Fail to alloc VLAN table for VF %d\n",
569 bp->pf.vf_info[i].vlan_table);
570 bp->pf.vf_info[i].vlan_as_table =
571 rte_zmalloc("VF VLAN AS table",
574 if (bp->pf.vf_info[i].vlan_as_table == NULL)
576 "Alloc VLAN AS table for VF %d fail\n",
580 bp->pf.vf_info[i].vlan_as_table);
581 STAILQ_INIT(&bp->pf.vf_info[i].filter);
586 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
587 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
588 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
589 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
590 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
591 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
592 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
593 /* TODO: For now, do not support VMDq/RFS on VFs. */
598 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
602 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
604 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
605 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
606 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
607 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
609 bnxt_hwrm_ptp_qcfg(bp);
618 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
622 rc = __bnxt_hwrm_func_qcaps(bp);
623 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
624 rc = bnxt_alloc_ctx_mem(bp);
628 rc = bnxt_hwrm_func_resc_qcaps(bp);
630 bp->flags |= BNXT_FLAG_NEW_RM;
636 int bnxt_hwrm_func_reset(struct bnxt *bp)
639 struct hwrm_func_reset_input req = {.req_type = 0 };
640 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
642 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
644 req.enables = rte_cpu_to_le_32(0);
646 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
654 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
657 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
658 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
660 if (bp->flags & BNXT_FLAG_REGISTERED)
663 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
664 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
665 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
666 req.ver_maj = RTE_VER_YEAR;
667 req.ver_min = RTE_VER_MONTH;
668 req.ver_upd = RTE_VER_MINOR;
671 req.enables |= rte_cpu_to_le_32(
672 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
673 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
674 RTE_MIN(sizeof(req.vf_req_fwd),
675 sizeof(bp->pf.vf_req_fwd)));
678 * PF can sniff HWRM API issued by VF. This can be set up by
679 * linux driver and inherited by the DPDK PF driver. Clear
680 * this HWRM sniffer list in FW because DPDK PF driver does
684 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
687 req.async_event_fwd[0] |=
688 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
689 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
690 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
691 req.async_event_fwd[1] |=
692 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
693 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
695 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
700 bp->flags |= BNXT_FLAG_REGISTERED;
705 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
707 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
710 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
713 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
718 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
719 struct hwrm_func_vf_cfg_input req = {0};
721 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
723 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
724 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
725 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
726 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
727 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
729 if (BNXT_HAS_RING_GRPS(bp)) {
730 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
731 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
734 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
735 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
736 AGG_RING_MULTIPLIER);
737 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
738 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
740 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
741 if (bp->vf_resv_strategy ==
742 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
743 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
744 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
745 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
746 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
747 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
748 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
752 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
753 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
754 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
755 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
756 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
757 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
759 if (test && BNXT_HAS_RING_GRPS(bp))
760 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
762 req.flags = rte_cpu_to_le_32(flags);
763 req.enables |= rte_cpu_to_le_32(enables);
765 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
768 HWRM_CHECK_RESULT_SILENT();
776 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
779 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
780 struct hwrm_func_resource_qcaps_input req = {0};
782 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
783 req.fid = rte_cpu_to_le_16(0xffff);
785 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
790 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
791 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
792 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
793 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
794 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
795 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
796 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
797 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
799 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
800 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
801 if (bp->vf_resv_strategy >
802 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
803 bp->vf_resv_strategy =
804 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
810 int bnxt_hwrm_ver_get(struct bnxt *bp)
813 struct hwrm_ver_get_input req = {.req_type = 0 };
814 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
816 uint16_t max_resp_len;
817 char type[RTE_MEMZONE_NAMESIZE];
818 uint32_t dev_caps_cfg;
820 bp->max_req_len = HWRM_MAX_REQ_LEN;
821 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
823 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
824 req.hwrm_intf_min = HWRM_VERSION_MINOR;
825 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
827 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
831 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
832 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
833 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
834 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
835 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
836 (resp->hwrm_fw_min_8b << 16) |
837 (resp->hwrm_fw_bld_8b << 8) |
838 resp->hwrm_fw_rsvd_8b;
839 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
840 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
842 fw_version = resp->hwrm_intf_maj_8b << 16;
843 fw_version |= resp->hwrm_intf_min_8b << 8;
844 fw_version |= resp->hwrm_intf_upd_8b;
845 bp->hwrm_spec_code = fw_version;
847 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
848 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
853 if (bp->max_req_len > resp->max_req_win_len) {
854 PMD_DRV_LOG(ERR, "Unsupported request length\n");
857 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
858 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
859 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
860 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
862 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
863 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
865 if (bp->max_resp_len != max_resp_len) {
866 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
867 bp->pdev->addr.domain, bp->pdev->addr.bus,
868 bp->pdev->addr.devid, bp->pdev->addr.function);
870 rte_free(bp->hwrm_cmd_resp_addr);
872 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
873 if (bp->hwrm_cmd_resp_addr == NULL) {
877 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
878 bp->hwrm_cmd_resp_dma_addr =
879 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
880 if (bp->hwrm_cmd_resp_dma_addr == 0) {
882 "Unable to map response buffer to physical memory.\n");
886 bp->max_resp_len = max_resp_len;
890 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
892 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
893 PMD_DRV_LOG(DEBUG, "Short command supported\n");
894 bp->flags |= BNXT_FLAG_SHORT_CMD;
898 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
900 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
901 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
902 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
903 bp->pdev->addr.domain, bp->pdev->addr.bus,
904 bp->pdev->addr.devid, bp->pdev->addr.function);
906 rte_free(bp->hwrm_short_cmd_req_addr);
908 bp->hwrm_short_cmd_req_addr =
909 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
910 if (bp->hwrm_short_cmd_req_addr == NULL) {
914 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
915 bp->hwrm_short_cmd_req_dma_addr =
916 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
917 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
918 rte_free(bp->hwrm_short_cmd_req_addr);
920 "Unable to map buffer to physical memory.\n");
926 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
927 bp->flags |= BNXT_FLAG_KONG_MB_EN;
928 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
931 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
932 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
939 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
942 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
943 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
945 if (!(bp->flags & BNXT_FLAG_REGISTERED))
948 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
951 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
956 bp->flags &= ~BNXT_FLAG_REGISTERED;
961 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
964 struct hwrm_port_phy_cfg_input req = {0};
965 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
966 uint32_t enables = 0;
968 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
971 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
972 if (bp->link_info.auto_mode && conf->link_speed) {
973 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
974 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
977 req.flags = rte_cpu_to_le_32(conf->phy_flags);
978 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
979 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
981 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
982 * any auto mode, even "none".
984 if (!conf->link_speed) {
985 /* No speeds specified. Enable AutoNeg - all speeds */
987 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
989 /* AutoNeg - Advertise speeds specified. */
990 if (conf->auto_link_speed_mask &&
991 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
993 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
994 req.auto_link_speed_mask =
995 conf->auto_link_speed_mask;
997 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1000 req.auto_duplex = conf->duplex;
1001 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1002 req.auto_pause = conf->auto_pause;
1003 req.force_pause = conf->force_pause;
1004 /* Set force_pause if there is no auto or if there is a force */
1005 if (req.auto_pause && !req.force_pause)
1006 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1008 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1010 req.enables = rte_cpu_to_le_32(enables);
1013 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1014 PMD_DRV_LOG(INFO, "Force Link Down\n");
1017 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1019 HWRM_CHECK_RESULT();
1025 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1026 struct bnxt_link_info *link_info)
1029 struct hwrm_port_phy_qcfg_input req = {0};
1030 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1032 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1034 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1036 HWRM_CHECK_RESULT();
1038 link_info->phy_link_status = resp->link;
1039 link_info->link_up =
1040 (link_info->phy_link_status ==
1041 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1042 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1043 link_info->duplex = resp->duplex_cfg;
1044 link_info->pause = resp->pause;
1045 link_info->auto_pause = resp->auto_pause;
1046 link_info->force_pause = resp->force_pause;
1047 link_info->auto_mode = resp->auto_mode;
1048 link_info->phy_type = resp->phy_type;
1049 link_info->media_type = resp->media_type;
1051 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1052 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1053 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1054 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1055 link_info->phy_ver[0] = resp->phy_maj;
1056 link_info->phy_ver[1] = resp->phy_min;
1057 link_info->phy_ver[2] = resp->phy_bld;
1061 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1062 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1063 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1064 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1065 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1066 link_info->auto_link_speed_mask);
1067 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1068 link_info->force_link_speed);
1073 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1076 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1077 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1080 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1082 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1083 /* HWRM Version >= 1.9.1 */
1084 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1086 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1087 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1089 HWRM_CHECK_RESULT();
1091 #define GET_QUEUE_INFO(x) \
1092 bp->cos_queue[x].id = resp->queue_id##x; \
1093 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1106 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1107 bp->tx_cosq_id = bp->cos_queue[0].id;
1109 /* iterate and find the COSq profile to use for Tx */
1110 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1111 if (bp->cos_queue[i].profile ==
1112 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1113 bp->tx_cosq_id = bp->cos_queue[i].id;
1119 bp->max_tc = resp->max_configurable_queues;
1120 bp->max_lltc = resp->max_configurable_lossless_queues;
1121 if (bp->max_tc > BNXT_MAX_QUEUE)
1122 bp->max_tc = BNXT_MAX_QUEUE;
1123 bp->max_q = bp->max_tc;
1125 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1130 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1131 struct bnxt_ring *ring,
1132 uint32_t ring_type, uint32_t map_index,
1133 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1136 uint32_t enables = 0;
1137 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1138 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1139 struct rte_mempool *mb_pool;
1140 uint16_t rx_buf_size;
1142 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1144 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1145 req.fbo = rte_cpu_to_le_32(0);
1146 /* Association of ring index with doorbell index */
1147 req.logical_id = rte_cpu_to_le_16(map_index);
1148 req.length = rte_cpu_to_le_32(ring->ring_size);
1150 switch (ring_type) {
1151 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1152 req.ring_type = ring_type;
1153 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1154 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1155 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1156 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1158 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1160 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1161 req.ring_type = ring_type;
1162 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1163 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1164 if (BNXT_CHIP_THOR(bp)) {
1165 mb_pool = bp->rx_queues[0]->mb_pool;
1166 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1167 RTE_PKTMBUF_HEADROOM;
1168 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1170 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1172 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1174 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1176 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1177 req.ring_type = ring_type;
1178 if (BNXT_HAS_NQ(bp)) {
1179 /* Association of cp ring with nq */
1180 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1182 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1184 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1186 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1187 req.ring_type = ring_type;
1188 req.page_size = BNXT_PAGE_SHFT;
1189 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1191 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1192 req.ring_type = ring_type;
1193 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1195 mb_pool = bp->rx_queues[0]->mb_pool;
1196 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1197 RTE_PKTMBUF_HEADROOM;
1198 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1200 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1201 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1202 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1203 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1206 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1211 req.enables = rte_cpu_to_le_32(enables);
1213 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1215 if (rc || resp->error_code) {
1216 if (rc == 0 && resp->error_code)
1217 rc = rte_le_to_cpu_16(resp->error_code);
1218 switch (ring_type) {
1219 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1221 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1224 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1226 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1229 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1231 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1235 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1237 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1240 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1242 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1246 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1252 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1257 int bnxt_hwrm_ring_free(struct bnxt *bp,
1258 struct bnxt_ring *ring, uint32_t ring_type)
1261 struct hwrm_ring_free_input req = {.req_type = 0 };
1262 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1264 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1266 req.ring_type = ring_type;
1267 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1269 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1271 if (rc || resp->error_code) {
1272 if (rc == 0 && resp->error_code)
1273 rc = rte_le_to_cpu_16(resp->error_code);
1276 switch (ring_type) {
1277 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1278 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1281 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1282 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1285 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1286 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1289 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1291 "hwrm_ring_free nq failed. rc:%d\n", rc);
1293 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1295 "hwrm_ring_free agg failed. rc:%d\n", rc);
1298 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1306 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1309 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1310 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1312 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1314 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1315 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1316 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1317 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1319 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1321 HWRM_CHECK_RESULT();
1323 bp->grp_info[idx].fw_grp_id =
1324 rte_le_to_cpu_16(resp->ring_group_id);
1331 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1334 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1335 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1337 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1339 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1341 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1343 HWRM_CHECK_RESULT();
1346 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1350 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1353 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1354 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1356 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1359 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1361 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1363 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1365 HWRM_CHECK_RESULT();
1371 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1372 unsigned int idx __rte_unused)
1375 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1376 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1378 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1380 req.update_period_ms = rte_cpu_to_le_32(0);
1382 req.stats_dma_addr =
1383 rte_cpu_to_le_64(cpr->hw_stats_map);
1385 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1387 HWRM_CHECK_RESULT();
1389 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1396 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1397 unsigned int idx __rte_unused)
1400 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1401 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1403 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1405 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1407 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1409 HWRM_CHECK_RESULT();
1415 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1418 struct hwrm_vnic_alloc_input req = { 0 };
1419 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1421 if (!BNXT_HAS_RING_GRPS(bp))
1422 goto skip_ring_grps;
1424 /* map ring groups to this vnic */
1425 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1426 vnic->start_grp_id, vnic->end_grp_id);
1427 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1428 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1430 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1431 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1432 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1433 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1436 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1437 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1438 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1440 if (vnic->func_default)
1442 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1443 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1445 HWRM_CHECK_RESULT();
1447 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1449 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1453 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1454 struct bnxt_vnic_info *vnic,
1455 struct bnxt_plcmodes_cfg *pmode)
1458 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1459 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1461 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1463 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1465 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1467 HWRM_CHECK_RESULT();
1469 pmode->flags = rte_le_to_cpu_32(resp->flags);
1470 /* dflt_vnic bit doesn't exist in the _cfg command */
1471 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1472 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1473 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1474 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1481 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1482 struct bnxt_vnic_info *vnic,
1483 struct bnxt_plcmodes_cfg *pmode)
1486 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1487 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1489 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1491 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1492 req.flags = rte_cpu_to_le_32(pmode->flags);
1493 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1494 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1495 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1496 req.enables = rte_cpu_to_le_32(
1497 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1498 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1499 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1502 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1504 HWRM_CHECK_RESULT();
1510 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1513 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1514 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1515 uint32_t ctx_enable_flag = 0;
1516 struct bnxt_plcmodes_cfg pmodes;
1517 uint32_t enables = 0;
1519 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1520 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1524 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1528 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1530 if (BNXT_CHIP_THOR(bp)) {
1531 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1532 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1533 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1535 req.default_rx_ring_id =
1536 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1537 req.default_cmpl_ring_id =
1538 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1539 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1540 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1544 /* Only RSS support for now TBD: COS & LB */
1545 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1546 if (vnic->lb_rule != 0xffff)
1547 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1548 if (vnic->cos_rule != 0xffff)
1549 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1550 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1551 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1552 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1554 enables |= ctx_enable_flag;
1555 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1556 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1557 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1558 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1561 req.enables = rte_cpu_to_le_32(enables);
1562 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1563 req.mru = rte_cpu_to_le_16(vnic->mru);
1564 /* Configure default VNIC only once. */
1565 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1567 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1568 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1570 if (vnic->vlan_strip)
1572 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1575 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1576 if (vnic->roce_dual)
1577 req.flags |= rte_cpu_to_le_32(
1578 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1579 if (vnic->roce_only)
1580 req.flags |= rte_cpu_to_le_32(
1581 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1582 if (vnic->rss_dflt_cr)
1583 req.flags |= rte_cpu_to_le_32(
1584 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1586 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1588 HWRM_CHECK_RESULT();
1591 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1596 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1600 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1601 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1603 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1604 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1607 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1610 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1611 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1612 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1614 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1616 HWRM_CHECK_RESULT();
1618 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1619 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1620 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1621 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1622 vnic->mru = rte_le_to_cpu_16(resp->mru);
1623 vnic->func_default = rte_le_to_cpu_32(
1624 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1625 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1626 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1627 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1628 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1629 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1630 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1631 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1632 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1633 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1634 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1641 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1642 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1646 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1647 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1648 bp->hwrm_cmd_resp_addr;
1650 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1652 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1653 HWRM_CHECK_RESULT();
1655 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1656 if (!BNXT_HAS_RING_GRPS(bp))
1657 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1658 else if (ctx_idx == 0)
1659 vnic->rss_rule = ctx_id;
1666 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1667 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1670 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1671 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1672 bp->hwrm_cmd_resp_addr;
1674 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1675 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1678 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1680 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1682 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1684 HWRM_CHECK_RESULT();
1690 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1693 struct hwrm_vnic_free_input req = {.req_type = 0 };
1694 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1696 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1697 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1701 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1703 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1705 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1707 HWRM_CHECK_RESULT();
1710 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1711 /* Configure default VNIC again if necessary. */
1712 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1713 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1719 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1723 int nr_ctxs = bp->max_ring_grps;
1724 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1725 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1727 if (!(vnic->rss_table && vnic->hash_type))
1730 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1732 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1733 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1734 req.hash_mode_flags = vnic->hash_mode;
1736 req.hash_key_tbl_addr =
1737 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1739 for (i = 0; i < nr_ctxs; i++) {
1740 req.ring_grp_tbl_addr =
1741 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1742 i * HW_HASH_INDEX_SIZE);
1743 req.ring_table_pair_index = i;
1744 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1746 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1749 HWRM_CHECK_RESULT();
1759 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1760 struct bnxt_vnic_info *vnic)
1763 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1764 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1766 if (BNXT_CHIP_THOR(bp))
1767 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1769 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1771 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1772 req.hash_mode_flags = vnic->hash_mode;
1774 req.ring_grp_tbl_addr =
1775 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1776 req.hash_key_tbl_addr =
1777 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1778 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1779 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1781 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1783 HWRM_CHECK_RESULT();
1789 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1790 struct bnxt_vnic_info *vnic)
1793 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1794 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1797 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1798 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1802 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1804 req.flags = rte_cpu_to_le_32(
1805 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1807 req.enables = rte_cpu_to_le_32(
1808 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1810 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1811 size -= RTE_PKTMBUF_HEADROOM;
1813 req.jumbo_thresh = rte_cpu_to_le_16(size);
1814 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1816 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1818 HWRM_CHECK_RESULT();
1824 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1825 struct bnxt_vnic_info *vnic, bool enable)
1828 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1829 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1831 if (BNXT_CHIP_THOR(bp))
1834 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1837 req.enables = rte_cpu_to_le_32(
1838 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1839 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1840 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1841 req.flags = rte_cpu_to_le_32(
1842 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1843 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1844 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1845 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1846 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1847 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1848 req.max_agg_segs = rte_cpu_to_le_16(5);
1850 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1851 req.min_agg_len = rte_cpu_to_le_32(512);
1853 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1855 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1857 HWRM_CHECK_RESULT();
1863 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1865 struct hwrm_func_cfg_input req = {0};
1866 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1869 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1870 req.enables = rte_cpu_to_le_32(
1871 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1872 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1873 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1875 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1877 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1878 HWRM_CHECK_RESULT();
1881 bp->pf.vf_info[vf].random_mac = false;
1886 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1890 struct hwrm_func_qstats_input req = {.req_type = 0};
1891 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1893 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1895 req.fid = rte_cpu_to_le_16(fid);
1897 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1899 HWRM_CHECK_RESULT();
1902 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1909 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1910 struct rte_eth_stats *stats)
1913 struct hwrm_func_qstats_input req = {.req_type = 0};
1914 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1916 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1918 req.fid = rte_cpu_to_le_16(fid);
1920 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1922 HWRM_CHECK_RESULT();
1924 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1925 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1926 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1927 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1928 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1929 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1931 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1932 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1933 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1934 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1935 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1936 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1938 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1939 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1940 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1947 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1950 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1951 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1953 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1955 req.fid = rte_cpu_to_le_16(fid);
1957 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1959 HWRM_CHECK_RESULT();
1966 * HWRM utility functions
1969 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1974 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1975 struct bnxt_tx_queue *txq;
1976 struct bnxt_rx_queue *rxq;
1977 struct bnxt_cp_ring_info *cpr;
1979 if (i >= bp->rx_cp_nr_rings) {
1980 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1983 rxq = bp->rx_queues[i];
1987 rc = bnxt_hwrm_stat_clear(bp, cpr);
1994 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1998 struct bnxt_cp_ring_info *cpr;
2000 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2002 if (i >= bp->rx_cp_nr_rings) {
2003 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2005 cpr = bp->rx_queues[i]->cp_ring;
2006 bp->grp_info[i].fw_stats_ctx = -1;
2008 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2009 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2010 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2018 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2023 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2024 struct bnxt_tx_queue *txq;
2025 struct bnxt_rx_queue *rxq;
2026 struct bnxt_cp_ring_info *cpr;
2028 if (i >= bp->rx_cp_nr_rings) {
2029 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2032 rxq = bp->rx_queues[i];
2036 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2044 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2049 if (!BNXT_HAS_RING_GRPS(bp))
2052 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2054 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2057 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2065 static void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2067 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2069 bnxt_hwrm_ring_free(bp, cp_ring,
2070 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2071 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2072 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2073 sizeof(*cpr->cp_desc_ring));
2074 cpr->cp_raw_cons = 0;
2077 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2079 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2081 bnxt_hwrm_ring_free(bp, cp_ring,
2082 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2083 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2084 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2085 sizeof(*cpr->cp_desc_ring));
2086 cpr->cp_raw_cons = 0;
2089 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2091 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2092 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2093 struct bnxt_ring *ring = rxr->rx_ring_struct;
2094 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2096 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2097 bnxt_hwrm_ring_free(bp, ring,
2098 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2099 ring->fw_ring_id = INVALID_HW_RING_ID;
2100 bp->grp_info[queue_index].rx_fw_ring_id = INVALID_HW_RING_ID;
2101 memset(rxr->rx_desc_ring, 0,
2102 rxr->rx_ring_struct->ring_size *
2103 sizeof(*rxr->rx_desc_ring));
2104 memset(rxr->rx_buf_ring, 0,
2105 rxr->rx_ring_struct->ring_size *
2106 sizeof(*rxr->rx_buf_ring));
2109 ring = rxr->ag_ring_struct;
2110 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2111 bnxt_hwrm_ring_free(bp, ring,
2112 BNXT_CHIP_THOR(bp) ?
2113 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2114 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2115 ring->fw_ring_id = INVALID_HW_RING_ID;
2116 memset(rxr->ag_buf_ring, 0,
2117 rxr->ag_ring_struct->ring_size *
2118 sizeof(*rxr->ag_buf_ring));
2120 bp->grp_info[queue_index].ag_fw_ring_id = INVALID_HW_RING_ID;
2122 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2123 bnxt_free_cp_ring(bp, cpr);
2125 bnxt_free_nq_ring(bp, rxq->nq_ring);
2128 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2131 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2135 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2136 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2137 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2138 struct bnxt_ring *ring = txr->tx_ring_struct;
2139 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2141 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2142 bnxt_hwrm_ring_free(bp, ring,
2143 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2144 ring->fw_ring_id = INVALID_HW_RING_ID;
2145 memset(txr->tx_desc_ring, 0,
2146 txr->tx_ring_struct->ring_size *
2147 sizeof(*txr->tx_desc_ring));
2148 memset(txr->tx_buf_ring, 0,
2149 txr->tx_ring_struct->ring_size *
2150 sizeof(*txr->tx_buf_ring));
2154 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2155 bnxt_free_cp_ring(bp, cpr);
2156 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2158 bnxt_free_nq_ring(bp, txq->nq_ring);
2162 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2163 bnxt_free_hwrm_rx_ring(bp, i);
2168 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2173 if (!BNXT_HAS_RING_GRPS(bp))
2176 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2177 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2184 void bnxt_free_hwrm_resources(struct bnxt *bp)
2186 /* Release memzone */
2187 rte_free(bp->hwrm_cmd_resp_addr);
2188 rte_free(bp->hwrm_short_cmd_req_addr);
2189 bp->hwrm_cmd_resp_addr = NULL;
2190 bp->hwrm_short_cmd_req_addr = NULL;
2191 bp->hwrm_cmd_resp_dma_addr = 0;
2192 bp->hwrm_short_cmd_req_dma_addr = 0;
2195 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2197 struct rte_pci_device *pdev = bp->pdev;
2198 char type[RTE_MEMZONE_NAMESIZE];
2200 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2201 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2202 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2203 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2204 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2205 if (bp->hwrm_cmd_resp_addr == NULL)
2207 bp->hwrm_cmd_resp_dma_addr =
2208 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2209 if (bp->hwrm_cmd_resp_dma_addr == 0) {
2211 "unable to map response address to physical memory\n");
2214 rte_spinlock_init(&bp->hwrm_lock);
2219 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2221 struct bnxt_filter_info *filter;
2224 STAILQ_FOREACH(filter, &vnic->filter, next) {
2225 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2226 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2227 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2228 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2230 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2231 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2239 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2241 struct bnxt_filter_info *filter;
2242 struct rte_flow *flow;
2245 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2246 filter = flow->filter;
2247 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
2248 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2249 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2250 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2251 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2253 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2255 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2263 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2265 struct bnxt_filter_info *filter;
2268 STAILQ_FOREACH(filter, &vnic->filter, next) {
2269 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2270 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2272 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2273 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2276 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2284 void bnxt_free_tunnel_ports(struct bnxt *bp)
2286 if (bp->vxlan_port_cnt)
2287 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2288 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2290 if (bp->geneve_port_cnt)
2291 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2292 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2293 bp->geneve_port = 0;
2296 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2300 if (bp->vnic_info == NULL)
2304 * Cleanup VNICs in reverse order, to make sure the L2 filter
2305 * from vnic0 is last to be cleaned up.
2307 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2308 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2310 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2312 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2314 if (!BNXT_CHIP_THOR(bp)) {
2315 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2316 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2317 vnic->fw_grp_ids[j]);
2318 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2321 bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2322 vnic->rss_rule = INVALID_HW_RING_ID;
2325 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2327 bnxt_hwrm_vnic_free(bp, vnic);
2329 rte_free(vnic->fw_grp_ids);
2331 /* Ring resources */
2332 bnxt_free_all_hwrm_rings(bp);
2333 bnxt_free_all_hwrm_ring_grps(bp);
2334 bnxt_free_all_hwrm_stat_ctxs(bp);
2335 bnxt_free_tunnel_ports(bp);
2338 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2340 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2342 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2343 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2345 switch (conf_link_speed) {
2346 case ETH_LINK_SPEED_10M_HD:
2347 case ETH_LINK_SPEED_100M_HD:
2349 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2351 return hw_link_duplex;
2354 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2356 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2359 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2361 uint16_t eth_link_speed = 0;
2363 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2364 return ETH_LINK_SPEED_AUTONEG;
2366 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2367 case ETH_LINK_SPEED_100M:
2368 case ETH_LINK_SPEED_100M_HD:
2371 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2373 case ETH_LINK_SPEED_1G:
2375 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2377 case ETH_LINK_SPEED_2_5G:
2379 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2381 case ETH_LINK_SPEED_10G:
2383 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2385 case ETH_LINK_SPEED_20G:
2387 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2389 case ETH_LINK_SPEED_25G:
2391 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2393 case ETH_LINK_SPEED_40G:
2395 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2397 case ETH_LINK_SPEED_50G:
2399 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2401 case ETH_LINK_SPEED_100G:
2403 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2407 "Unsupported link speed %d; default to AUTO\n",
2411 return eth_link_speed;
2414 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2415 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2416 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2417 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2419 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2423 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2426 if (link_speed & ETH_LINK_SPEED_FIXED) {
2427 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2429 if (one_speed & (one_speed - 1)) {
2431 "Invalid advertised speeds (%u) for port %u\n",
2432 link_speed, port_id);
2435 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2437 "Unsupported advertised speed (%u) for port %u\n",
2438 link_speed, port_id);
2442 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2444 "Unsupported advertised speeds (%u) for port %u\n",
2445 link_speed, port_id);
2453 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2457 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2458 if (bp->link_info.support_speeds)
2459 return bp->link_info.support_speeds;
2460 link_speed = BNXT_SUPPORTED_SPEEDS;
2463 if (link_speed & ETH_LINK_SPEED_100M)
2464 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2465 if (link_speed & ETH_LINK_SPEED_100M_HD)
2466 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2467 if (link_speed & ETH_LINK_SPEED_1G)
2468 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2469 if (link_speed & ETH_LINK_SPEED_2_5G)
2470 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2471 if (link_speed & ETH_LINK_SPEED_10G)
2472 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2473 if (link_speed & ETH_LINK_SPEED_20G)
2474 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2475 if (link_speed & ETH_LINK_SPEED_25G)
2476 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2477 if (link_speed & ETH_LINK_SPEED_40G)
2478 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2479 if (link_speed & ETH_LINK_SPEED_50G)
2480 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2481 if (link_speed & ETH_LINK_SPEED_100G)
2482 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2486 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2488 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2490 switch (hw_link_speed) {
2491 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2492 eth_link_speed = ETH_SPEED_NUM_100M;
2494 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2495 eth_link_speed = ETH_SPEED_NUM_1G;
2497 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2498 eth_link_speed = ETH_SPEED_NUM_2_5G;
2500 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2501 eth_link_speed = ETH_SPEED_NUM_10G;
2503 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2504 eth_link_speed = ETH_SPEED_NUM_20G;
2506 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2507 eth_link_speed = ETH_SPEED_NUM_25G;
2509 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2510 eth_link_speed = ETH_SPEED_NUM_40G;
2512 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2513 eth_link_speed = ETH_SPEED_NUM_50G;
2515 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2516 eth_link_speed = ETH_SPEED_NUM_100G;
2518 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2520 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2524 return eth_link_speed;
2527 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2529 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2531 switch (hw_link_duplex) {
2532 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2533 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2535 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2537 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2538 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2541 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2545 return eth_link_duplex;
2548 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2551 struct bnxt_link_info *link_info = &bp->link_info;
2553 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2556 "Get link config failed with rc %d\n", rc);
2559 if (link_info->link_speed)
2561 bnxt_parse_hw_link_speed(link_info->link_speed);
2563 link->link_speed = ETH_SPEED_NUM_NONE;
2564 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2565 link->link_status = link_info->link_up;
2566 link->link_autoneg = link_info->auto_mode ==
2567 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2568 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2573 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2576 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2577 struct bnxt_link_info link_req;
2578 uint16_t speed, autoneg;
2580 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2583 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2584 bp->eth_dev->data->port_id);
2588 memset(&link_req, 0, sizeof(link_req));
2589 link_req.link_up = link_up;
2593 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2594 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2595 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2596 /* Autoneg can be done only when the FW allows */
2597 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2598 bp->link_info.force_link_speed)) {
2599 link_req.phy_flags |=
2600 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2601 link_req.auto_link_speed_mask =
2602 bnxt_parse_eth_link_speed_mask(bp,
2603 dev_conf->link_speeds);
2605 if (bp->link_info.phy_type ==
2606 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2607 bp->link_info.phy_type ==
2608 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2609 bp->link_info.media_type ==
2610 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2611 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2615 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2616 /* If user wants a particular speed try that first. */
2618 link_req.link_speed = speed;
2619 else if (bp->link_info.force_link_speed)
2620 link_req.link_speed = bp->link_info.force_link_speed;
2622 link_req.link_speed = bp->link_info.auto_link_speed;
2624 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2625 link_req.auto_pause = bp->link_info.auto_pause;
2626 link_req.force_pause = bp->link_info.force_pause;
2629 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2632 "Set link config failed with rc %d\n", rc);
2640 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2642 struct hwrm_func_qcfg_input req = {0};
2643 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2647 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2648 req.fid = rte_cpu_to_le_16(0xffff);
2650 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2652 HWRM_CHECK_RESULT();
2654 /* Hard Coded.. 0xfff VLAN ID mask */
2655 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2656 flags = rte_le_to_cpu_16(resp->flags);
2657 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2658 bp->flags |= BNXT_FLAG_MULTI_HOST;
2660 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2661 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2662 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2665 switch (resp->port_partition_type) {
2666 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2667 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2668 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2670 bp->port_partition_type = resp->port_partition_type;
2673 bp->port_partition_type = 0;
2682 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2683 struct hwrm_func_qcaps_output *qcaps)
2685 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2686 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2687 sizeof(qcaps->mac_address));
2688 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2689 qcaps->max_rx_rings = fcfg->num_rx_rings;
2690 qcaps->max_tx_rings = fcfg->num_tx_rings;
2691 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2692 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2694 qcaps->first_vf_id = 0;
2695 qcaps->max_vnics = fcfg->num_vnics;
2696 qcaps->max_decap_records = 0;
2697 qcaps->max_encap_records = 0;
2698 qcaps->max_tx_wm_flows = 0;
2699 qcaps->max_tx_em_flows = 0;
2700 qcaps->max_rx_wm_flows = 0;
2701 qcaps->max_rx_em_flows = 0;
2702 qcaps->max_flow_id = 0;
2703 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2704 qcaps->max_sp_tx_rings = 0;
2705 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2708 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2710 struct hwrm_func_cfg_input req = {0};
2711 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2715 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2716 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2717 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2718 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2719 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2720 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2721 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2722 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2723 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2725 if (BNXT_HAS_RING_GRPS(bp)) {
2726 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2727 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2728 } else if (BNXT_HAS_NQ(bp)) {
2729 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2730 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2733 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2734 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2735 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2736 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2738 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2739 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2740 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2741 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2742 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2743 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2744 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2745 req.fid = rte_cpu_to_le_16(0xffff);
2746 req.enables = rte_cpu_to_le_32(enables);
2748 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2750 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2752 HWRM_CHECK_RESULT();
2758 static void populate_vf_func_cfg_req(struct bnxt *bp,
2759 struct hwrm_func_cfg_input *req,
2762 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2763 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2764 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2765 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2766 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2767 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2768 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2769 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2770 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2771 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2773 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2774 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2776 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2777 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2779 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2781 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2782 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2784 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2785 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2786 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2787 /* TODO: For now, do not support VMDq/RFS on VFs. */
2788 req->num_vnics = rte_cpu_to_le_16(1);
2789 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2793 static void add_random_mac_if_needed(struct bnxt *bp,
2794 struct hwrm_func_cfg_input *cfg_req,
2797 struct rte_ether_addr mac;
2799 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2802 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2804 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2805 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2806 bp->pf.vf_info[vf].random_mac = true;
2808 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2809 RTE_ETHER_ADDR_LEN);
2813 static void reserve_resources_from_vf(struct bnxt *bp,
2814 struct hwrm_func_cfg_input *cfg_req,
2817 struct hwrm_func_qcaps_input req = {0};
2818 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2821 /* Get the actual allocated values now */
2822 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2823 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2824 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2827 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2828 copy_func_cfg_to_qcaps(cfg_req, resp);
2829 } else if (resp->error_code) {
2830 rc = rte_le_to_cpu_16(resp->error_code);
2831 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2832 copy_func_cfg_to_qcaps(cfg_req, resp);
2835 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2836 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2837 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2838 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2839 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2840 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2842 * TODO: While not supporting VMDq with VFs, max_vnics is always
2843 * forced to 1 in this case
2845 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2846 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2851 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2853 struct hwrm_func_qcfg_input req = {0};
2854 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2857 /* Check for zero MAC address */
2858 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2859 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2860 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2862 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2864 } else if (resp->error_code) {
2865 rc = rte_le_to_cpu_16(resp->error_code);
2866 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2869 rc = rte_le_to_cpu_16(resp->vlan);
2876 static int update_pf_resource_max(struct bnxt *bp)
2878 struct hwrm_func_qcfg_input req = {0};
2879 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2882 /* And copy the allocated numbers into the pf struct */
2883 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2884 req.fid = rte_cpu_to_le_16(0xffff);
2885 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2886 HWRM_CHECK_RESULT();
2888 /* Only TX ring value reflects actual allocation? TODO */
2889 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2890 bp->pf.evb_mode = resp->evb_mode;
2897 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2902 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2906 rc = bnxt_hwrm_func_qcaps(bp);
2910 bp->pf.func_cfg_flags &=
2911 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2912 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2913 bp->pf.func_cfg_flags |=
2914 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2915 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2916 rc = __bnxt_hwrm_func_qcaps(bp);
2920 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2922 struct hwrm_func_cfg_input req = {0};
2923 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2930 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2934 rc = bnxt_hwrm_func_qcaps(bp);
2939 bp->pf.active_vfs = num_vfs;
2942 * First, configure the PF to only use one TX ring. This ensures that
2943 * there are enough rings for all VFs.
2945 * If we don't do this, when we call func_alloc() later, we will lock
2946 * extra rings to the PF that won't be available during func_cfg() of
2949 * This has been fixed with firmware versions above 20.6.54
2951 bp->pf.func_cfg_flags &=
2952 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2953 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2954 bp->pf.func_cfg_flags |=
2955 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2956 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2961 * Now, create and register a buffer to hold forwarded VF requests
2963 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2964 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2965 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2966 if (bp->pf.vf_req_buf == NULL) {
2970 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2971 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2972 for (i = 0; i < num_vfs; i++)
2973 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2974 (i * HWRM_MAX_REQ_LEN);
2976 rc = bnxt_hwrm_func_buf_rgtr(bp);
2980 populate_vf_func_cfg_req(bp, &req, num_vfs);
2982 bp->pf.active_vfs = 0;
2983 for (i = 0; i < num_vfs; i++) {
2984 add_random_mac_if_needed(bp, &req, i);
2986 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2987 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2988 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2989 rc = bnxt_hwrm_send_message(bp,
2994 /* Clear enable flag for next pass */
2995 req.enables &= ~rte_cpu_to_le_32(
2996 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2998 if (rc || resp->error_code) {
3000 "Failed to initizlie VF %d\n", i);
3002 "Not all VFs available. (%d, %d)\n",
3003 rc, resp->error_code);
3010 reserve_resources_from_vf(bp, &req, i);
3011 bp->pf.active_vfs++;
3012 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3016 * Now configure the PF to use "the rest" of the resources
3017 * We're using STD_TX_RING_MODE here though which will limit the TX
3018 * rings. This will allow QoS to function properly. Not setting this
3019 * will cause PF rings to break bandwidth settings.
3021 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3025 rc = update_pf_resource_max(bp);
3032 bnxt_hwrm_func_buf_unrgtr(bp);
3036 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3038 struct hwrm_func_cfg_input req = {0};
3039 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3042 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3044 req.fid = rte_cpu_to_le_16(0xffff);
3045 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3046 req.evb_mode = bp->pf.evb_mode;
3048 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3049 HWRM_CHECK_RESULT();
3055 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3056 uint8_t tunnel_type)
3058 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3059 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3062 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3063 req.tunnel_type = tunnel_type;
3064 req.tunnel_dst_port_val = port;
3065 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3066 HWRM_CHECK_RESULT();
3068 switch (tunnel_type) {
3069 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3070 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3071 bp->vxlan_port = port;
3073 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3074 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3075 bp->geneve_port = port;
3086 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3087 uint8_t tunnel_type)
3089 struct hwrm_tunnel_dst_port_free_input req = {0};
3090 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3093 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3095 req.tunnel_type = tunnel_type;
3096 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3097 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3099 HWRM_CHECK_RESULT();
3105 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3108 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3109 struct hwrm_func_cfg_input req = {0};
3112 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3114 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3115 req.flags = rte_cpu_to_le_32(flags);
3116 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3118 HWRM_CHECK_RESULT();
3124 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3126 uint32_t *flag = flagp;
3128 vnic->flags = *flag;
3131 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3133 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3136 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3139 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3140 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3142 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3144 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3145 req.req_buf_page_size = rte_cpu_to_le_16(
3146 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3147 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3148 req.req_buf_page_addr0 =
3149 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3150 if (req.req_buf_page_addr0 == 0) {
3152 "unable to map buffer address to physical memory\n");
3156 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3158 HWRM_CHECK_RESULT();
3164 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3167 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3168 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3170 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3172 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3174 HWRM_CHECK_RESULT();
3180 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3182 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3183 struct hwrm_func_cfg_input req = {0};
3186 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3188 req.fid = rte_cpu_to_le_16(0xffff);
3189 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3190 req.enables = rte_cpu_to_le_32(
3191 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3192 req.async_event_cr = rte_cpu_to_le_16(
3193 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3194 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3196 HWRM_CHECK_RESULT();
3202 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3204 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3205 struct hwrm_func_vf_cfg_input req = {0};
3208 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3210 req.enables = rte_cpu_to_le_32(
3211 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3212 req.async_event_cr = rte_cpu_to_le_16(
3213 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3214 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3216 HWRM_CHECK_RESULT();
3222 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3224 struct hwrm_func_cfg_input req = {0};
3225 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3226 uint16_t dflt_vlan, fid;
3227 uint32_t func_cfg_flags;
3230 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3233 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3234 fid = bp->pf.vf_info[vf].fid;
3235 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3237 fid = rte_cpu_to_le_16(0xffff);
3238 func_cfg_flags = bp->pf.func_cfg_flags;
3239 dflt_vlan = bp->vlan;
3242 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3243 req.fid = rte_cpu_to_le_16(fid);
3244 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3245 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3247 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3249 HWRM_CHECK_RESULT();
3255 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3256 uint16_t max_bw, uint16_t enables)
3258 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3259 struct hwrm_func_cfg_input req = {0};
3262 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3264 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3265 req.enables |= rte_cpu_to_le_32(enables);
3266 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3267 req.max_bw = rte_cpu_to_le_32(max_bw);
3268 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3270 HWRM_CHECK_RESULT();
3276 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3278 struct hwrm_func_cfg_input req = {0};
3279 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3282 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3284 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3285 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3286 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3287 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3289 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3291 HWRM_CHECK_RESULT();
3297 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3302 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3304 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3309 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3310 void *encaped, size_t ec_size)
3313 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3314 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3316 if (ec_size > sizeof(req.encap_request))
3319 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3321 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3322 memcpy(req.encap_request, encaped, ec_size);
3324 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3326 HWRM_CHECK_RESULT();
3332 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3333 struct rte_ether_addr *mac)
3335 struct hwrm_func_qcfg_input req = {0};
3336 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3339 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3341 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3342 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3344 HWRM_CHECK_RESULT();
3346 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3353 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3354 void *encaped, size_t ec_size)
3357 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3358 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3360 if (ec_size > sizeof(req.encap_request))
3363 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3365 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3366 memcpy(req.encap_request, encaped, ec_size);
3368 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3370 HWRM_CHECK_RESULT();
3376 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3377 struct rte_eth_stats *stats, uint8_t rx)
3380 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3381 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3383 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3385 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3387 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3389 HWRM_CHECK_RESULT();
3392 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3393 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3394 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3395 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3396 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3397 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3398 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3399 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3401 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3402 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3403 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3404 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3405 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3406 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3415 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3417 struct hwrm_port_qstats_input req = {0};
3418 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3419 struct bnxt_pf_info *pf = &bp->pf;
3422 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3424 req.port_id = rte_cpu_to_le_16(pf->port_id);
3425 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3426 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3427 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3429 HWRM_CHECK_RESULT();
3435 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3437 struct hwrm_port_clr_stats_input req = {0};
3438 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3439 struct bnxt_pf_info *pf = &bp->pf;
3442 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3443 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3444 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3447 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3449 req.port_id = rte_cpu_to_le_16(pf->port_id);
3450 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3452 HWRM_CHECK_RESULT();
3458 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3460 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3461 struct hwrm_port_led_qcaps_input req = {0};
3467 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3468 req.port_id = bp->pf.port_id;
3469 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3471 HWRM_CHECK_RESULT();
3473 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3476 bp->num_leds = resp->num_leds;
3477 memcpy(bp->leds, &resp->led0_id,
3478 sizeof(bp->leds[0]) * bp->num_leds);
3479 for (i = 0; i < bp->num_leds; i++) {
3480 struct bnxt_led_info *led = &bp->leds[i];
3482 uint16_t caps = led->led_state_caps;
3484 if (!led->led_group_id ||
3485 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3497 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3499 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3500 struct hwrm_port_led_cfg_input req = {0};
3501 struct bnxt_led_cfg *led_cfg;
3502 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3503 uint16_t duration = 0;
3506 if (!bp->num_leds || BNXT_VF(bp))
3509 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3512 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3513 duration = rte_cpu_to_le_16(500);
3515 req.port_id = bp->pf.port_id;
3516 req.num_leds = bp->num_leds;
3517 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3518 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3519 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3520 led_cfg->led_id = bp->leds[i].led_id;
3521 led_cfg->led_state = led_state;
3522 led_cfg->led_blink_on = duration;
3523 led_cfg->led_blink_off = duration;
3524 led_cfg->led_group_id = bp->leds[i].led_group_id;
3527 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3529 HWRM_CHECK_RESULT();
3535 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3539 struct hwrm_nvm_get_dir_info_input req = {0};
3540 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3542 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3544 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3546 HWRM_CHECK_RESULT();
3550 *entries = rte_le_to_cpu_32(resp->entries);
3551 *length = rte_le_to_cpu_32(resp->entry_length);
3556 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3559 uint32_t dir_entries;
3560 uint32_t entry_length;
3563 rte_iova_t dma_handle;
3564 struct hwrm_nvm_get_dir_entries_input req = {0};
3565 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3567 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3571 *data++ = dir_entries;
3572 *data++ = entry_length;
3574 memset(data, 0xff, len);
3576 buflen = dir_entries * entry_length;
3577 buf = rte_malloc("nvm_dir", buflen, 0);
3578 rte_mem_lock_page(buf);
3581 dma_handle = rte_mem_virt2iova(buf);
3582 if (dma_handle == 0) {
3584 "unable to map response address to physical memory\n");
3587 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3588 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3589 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3592 memcpy(data, buf, len > buflen ? buflen : len);
3595 HWRM_CHECK_RESULT();
3601 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3602 uint32_t offset, uint32_t length,
3607 rte_iova_t dma_handle;
3608 struct hwrm_nvm_read_input req = {0};
3609 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3611 buf = rte_malloc("nvm_item", length, 0);
3612 rte_mem_lock_page(buf);
3616 dma_handle = rte_mem_virt2iova(buf);
3617 if (dma_handle == 0) {
3619 "unable to map response address to physical memory\n");
3622 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3623 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3624 req.dir_idx = rte_cpu_to_le_16(index);
3625 req.offset = rte_cpu_to_le_32(offset);
3626 req.len = rte_cpu_to_le_32(length);
3627 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3629 memcpy(data, buf, length);
3632 HWRM_CHECK_RESULT();
3638 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3641 struct hwrm_nvm_erase_dir_entry_input req = {0};
3642 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3644 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3645 req.dir_idx = rte_cpu_to_le_16(index);
3646 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3647 HWRM_CHECK_RESULT();
3654 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3655 uint16_t dir_ordinal, uint16_t dir_ext,
3656 uint16_t dir_attr, const uint8_t *data,
3660 struct hwrm_nvm_write_input req = {0};
3661 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3662 rte_iova_t dma_handle;
3665 buf = rte_malloc("nvm_write", data_len, 0);
3666 rte_mem_lock_page(buf);
3670 dma_handle = rte_mem_virt2iova(buf);
3671 if (dma_handle == 0) {
3673 "unable to map response address to physical memory\n");
3676 memcpy(buf, data, data_len);
3678 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3680 req.dir_type = rte_cpu_to_le_16(dir_type);
3681 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3682 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3683 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3684 req.dir_data_length = rte_cpu_to_le_32(data_len);
3685 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3687 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3690 HWRM_CHECK_RESULT();
3697 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3699 uint32_t *count = cbdata;
3701 *count = *count + 1;
3704 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3705 struct bnxt_vnic_info *vnic __rte_unused)
3710 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3714 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3715 &count, bnxt_vnic_count_hwrm_stub);
3720 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3723 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3724 struct hwrm_func_vf_vnic_ids_query_output *resp =
3725 bp->hwrm_cmd_resp_addr;
3728 /* First query all VNIC ids */
3729 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3731 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3732 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3733 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3735 if (req.vnic_id_tbl_addr == 0) {
3738 "unable to map VNIC ID table address to physical memory\n");
3741 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3744 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3746 } else if (resp->error_code) {
3747 rc = rte_le_to_cpu_16(resp->error_code);
3749 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3752 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3760 * This function queries the VNIC IDs for a specified VF. It then calls
3761 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3762 * Then it calls the hwrm_cb function to program this new vnic configuration.
3764 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3765 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3766 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3768 struct bnxt_vnic_info vnic;
3770 int i, num_vnic_ids;
3775 /* First query all VNIC ids */
3776 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3777 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3778 RTE_CACHE_LINE_SIZE);
3779 if (vnic_ids == NULL) {
3783 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3784 rte_mem_lock_page(((char *)vnic_ids) + sz);
3786 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3788 if (num_vnic_ids < 0)
3789 return num_vnic_ids;
3791 /* Retrieve VNIC, update bd_stall then update */
3793 for (i = 0; i < num_vnic_ids; i++) {
3794 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3795 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3796 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3799 if (vnic.mru <= 4) /* Indicates unallocated */
3802 vnic_cb(&vnic, cbdata);
3804 rc = hwrm_cb(bp, &vnic);
3814 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3817 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3818 struct hwrm_func_cfg_input req = {0};
3821 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3823 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3824 req.enables |= rte_cpu_to_le_32(
3825 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3826 req.vlan_antispoof_mode = on ?
3827 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3828 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3829 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3831 HWRM_CHECK_RESULT();
3837 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3839 struct bnxt_vnic_info vnic;
3842 int num_vnic_ids, i;
3846 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3847 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3848 RTE_CACHE_LINE_SIZE);
3849 if (vnic_ids == NULL) {
3854 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3855 rte_mem_lock_page(((char *)vnic_ids) + sz);
3857 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3863 * Loop through to find the default VNIC ID.
3864 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3865 * by sending the hwrm_func_qcfg command to the firmware.
3867 for (i = 0; i < num_vnic_ids; i++) {
3868 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3869 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3870 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3871 bp->pf.first_vf_id + vf);
3874 if (vnic.func_default) {
3876 return vnic.fw_vnic_id;
3879 /* Could not find a default VNIC. */
3880 PMD_DRV_LOG(ERR, "No default VNIC\n");
3886 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3888 struct bnxt_filter_info *filter)
3891 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3892 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3893 uint32_t enables = 0;
3895 if (filter->fw_em_filter_id != UINT64_MAX)
3896 bnxt_hwrm_clear_em_filter(bp, filter);
3898 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3900 req.flags = rte_cpu_to_le_32(filter->flags);
3902 enables = filter->enables |
3903 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3904 req.dst_id = rte_cpu_to_le_16(dst_id);
3906 if (filter->ip_addr_type) {
3907 req.ip_addr_type = filter->ip_addr_type;
3908 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3911 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3912 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3914 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3915 memcpy(req.src_macaddr, filter->src_macaddr,
3916 RTE_ETHER_ADDR_LEN);
3918 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3919 memcpy(req.dst_macaddr, filter->dst_macaddr,
3920 RTE_ETHER_ADDR_LEN);
3922 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3923 req.ovlan_vid = filter->l2_ovlan;
3925 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3926 req.ivlan_vid = filter->l2_ivlan;
3928 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3929 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3931 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3932 req.ip_protocol = filter->ip_protocol;
3934 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3935 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3937 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3938 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3940 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3941 req.src_port = rte_cpu_to_be_16(filter->src_port);
3943 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3944 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3946 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3947 req.mirror_vnic_id = filter->mirror_vnic_id;
3949 req.enables = rte_cpu_to_le_32(enables);
3951 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3953 HWRM_CHECK_RESULT();
3955 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3961 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3964 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3965 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3967 if (filter->fw_em_filter_id == UINT64_MAX)
3970 PMD_DRV_LOG(ERR, "Clear EM filter\n");
3971 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
3973 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3975 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3977 HWRM_CHECK_RESULT();
3980 filter->fw_em_filter_id = UINT64_MAX;
3981 filter->fw_l2_filter_id = UINT64_MAX;
3986 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3988 struct bnxt_filter_info *filter)
3991 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3992 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3993 bp->hwrm_cmd_resp_addr;
3994 uint32_t enables = 0;
3996 if (filter->fw_ntuple_filter_id != UINT64_MAX)
3997 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3999 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4001 req.flags = rte_cpu_to_le_32(filter->flags);
4003 enables = filter->enables |
4004 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4005 req.dst_id = rte_cpu_to_le_16(dst_id);
4008 if (filter->ip_addr_type) {
4009 req.ip_addr_type = filter->ip_addr_type;
4011 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4014 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4015 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4017 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4018 memcpy(req.src_macaddr, filter->src_macaddr,
4019 RTE_ETHER_ADDR_LEN);
4021 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4022 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4023 //RTE_ETHER_ADDR_LEN);
4025 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4026 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4028 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4029 req.ip_protocol = filter->ip_protocol;
4031 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4032 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4034 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4035 req.src_ipaddr_mask[0] =
4036 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4038 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4039 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4041 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4042 req.dst_ipaddr_mask[0] =
4043 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4045 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4046 req.src_port = rte_cpu_to_le_16(filter->src_port);
4048 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4049 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4051 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4052 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4054 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4055 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4057 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4058 req.mirror_vnic_id = filter->mirror_vnic_id;
4060 req.enables = rte_cpu_to_le_32(enables);
4062 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4064 HWRM_CHECK_RESULT();
4066 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4072 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4073 struct bnxt_filter_info *filter)
4076 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4077 struct hwrm_cfa_ntuple_filter_free_output *resp =
4078 bp->hwrm_cmd_resp_addr;
4080 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4083 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4085 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4087 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4089 HWRM_CHECK_RESULT();
4092 filter->fw_ntuple_filter_id = UINT64_MAX;
4098 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4100 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4101 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4102 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4103 int nr_ctxs = bp->max_ring_grps;
4104 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4105 uint16_t *ring_tbl = vnic->rss_table;
4106 int max_rings = bp->rx_nr_rings;
4110 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4112 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4113 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4114 req.hash_mode_flags = vnic->hash_mode;
4116 req.ring_grp_tbl_addr =
4117 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
4118 req.hash_key_tbl_addr =
4119 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4121 for (i = 0, k = 0; i < nr_ctxs; i++) {
4122 struct bnxt_rx_ring_info *rxr;
4123 struct bnxt_cp_ring_info *cpr;
4125 req.ring_table_pair_index = i;
4126 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4128 for (j = 0; j < 64; j++) {
4131 /* Find next active ring. */
4132 for (cnt = 0; cnt < max_rings; cnt++) {
4133 if (rx_queue_state[k] !=
4134 RTE_ETH_QUEUE_STATE_STOPPED)
4136 if (++k == max_rings)
4140 /* Return if no rings are active. */
4141 if (cnt == max_rings)
4144 /* Add rx/cp ring pair to RSS table. */
4145 rxr = rxqs[k]->rx_ring;
4146 cpr = rxqs[k]->cp_ring;
4148 ring_id = rxr->rx_ring_struct->fw_ring_id;
4149 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4150 ring_id = cpr->cp_ring_struct->fw_ring_id;
4151 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4153 if (++k == max_rings)
4156 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4159 HWRM_CHECK_RESULT();
4169 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4171 unsigned int rss_idx, fw_idx, i;
4173 if (!(vnic->rss_table && vnic->hash_type))
4176 if (BNXT_CHIP_THOR(bp))
4177 return bnxt_vnic_rss_configure_thor(bp, vnic);
4180 * Fill the RSS hash & redirection table with
4181 * ring group ids for all VNICs
4183 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4184 rss_idx++, fw_idx++) {
4185 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4186 fw_idx %= bp->rx_cp_nr_rings;
4187 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4191 if (i == bp->rx_cp_nr_rings)
4193 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4195 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4198 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4199 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4203 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4205 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4206 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4208 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4209 req->num_cmpl_dma_aggr_during_int =
4210 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4212 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4214 /* min timer set to 1/2 of interrupt timer */
4215 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4217 /* buf timer set to 1/4 of interrupt timer */
4218 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4220 req->cmpl_aggr_dma_tmr_during_int =
4221 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4223 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4224 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4225 req->flags = rte_cpu_to_le_16(flags);
4228 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4229 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4231 struct hwrm_ring_aggint_qcaps_input req = {0};
4232 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4237 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4238 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4242 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4243 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4245 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4246 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4247 agg_req->flags = rte_cpu_to_le_16(flags);
4249 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4250 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4251 agg_req->enables = rte_cpu_to_le_32(enables);
4254 HWRM_CHECK_RESULT();
4259 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4260 struct bnxt_coal *coal, uint16_t ring_id)
4262 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4263 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4264 bp->hwrm_cmd_resp_addr;
4267 /* Set ring coalesce parameters only for 100G NICs */
4268 if (BNXT_CHIP_THOR(bp)) {
4269 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4271 } else if (bnxt_stratus_device(bp)) {
4272 bnxt_hwrm_set_coal_params(coal, &req);
4277 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4278 req.ring_id = rte_cpu_to_le_16(ring_id);
4279 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4280 HWRM_CHECK_RESULT();
4285 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4286 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4288 struct hwrm_func_backing_store_qcaps_input req = {0};
4289 struct hwrm_func_backing_store_qcaps_output *resp =
4290 bp->hwrm_cmd_resp_addr;
4293 if (!BNXT_CHIP_THOR(bp) ||
4294 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4299 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4300 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4301 HWRM_CHECK_RESULT_SILENT();
4304 struct bnxt_ctx_pg_info *ctx_pg;
4305 struct bnxt_ctx_mem_info *ctx;
4306 int total_alloc_len;
4309 total_alloc_len = sizeof(*ctx);
4310 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4311 RTE_CACHE_LINE_SIZE);
4316 memset(ctx, 0, total_alloc_len);
4318 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4319 sizeof(*ctx_pg) * BNXT_MAX_Q,
4320 RTE_CACHE_LINE_SIZE);
4325 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4326 ctx->tqm_mem[i] = ctx_pg;
4329 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4330 ctx->qp_min_qp1_entries =
4331 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4332 ctx->qp_max_l2_entries =
4333 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4334 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4335 ctx->srq_max_l2_entries =
4336 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4337 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4338 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4339 ctx->cq_max_l2_entries =
4340 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4341 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4342 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4343 ctx->vnic_max_vnic_entries =
4344 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4345 ctx->vnic_max_ring_table_entries =
4346 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4347 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4348 ctx->stat_max_entries =
4349 rte_le_to_cpu_32(resp->stat_max_entries);
4350 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4351 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4352 ctx->tqm_min_entries_per_ring =
4353 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4354 ctx->tqm_max_entries_per_ring =
4355 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4356 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4357 if (!ctx->tqm_entries_multiple)
4358 ctx->tqm_entries_multiple = 1;
4359 ctx->mrav_max_entries =
4360 rte_le_to_cpu_32(resp->mrav_max_entries);
4361 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4362 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4363 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4372 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4374 struct hwrm_func_backing_store_cfg_input req = {0};
4375 struct hwrm_func_backing_store_cfg_output *resp =
4376 bp->hwrm_cmd_resp_addr;
4377 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4378 struct bnxt_ctx_pg_info *ctx_pg;
4379 uint32_t *num_entries;
4388 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4389 req.enables = rte_cpu_to_le_32(enables);
4391 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4392 ctx_pg = &ctx->qp_mem;
4393 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4394 req.qp_num_qp1_entries =
4395 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4396 req.qp_num_l2_entries =
4397 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4398 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4399 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4400 &req.qpc_pg_size_qpc_lvl,
4404 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4405 ctx_pg = &ctx->srq_mem;
4406 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4407 req.srq_num_l2_entries =
4408 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4409 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4410 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4411 &req.srq_pg_size_srq_lvl,
4415 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4416 ctx_pg = &ctx->cq_mem;
4417 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4418 req.cq_num_l2_entries =
4419 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4420 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4421 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4422 &req.cq_pg_size_cq_lvl,
4426 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4427 ctx_pg = &ctx->vnic_mem;
4428 req.vnic_num_vnic_entries =
4429 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4430 req.vnic_num_ring_table_entries =
4431 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4432 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4433 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4434 &req.vnic_pg_size_vnic_lvl,
4435 &req.vnic_page_dir);
4438 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4439 ctx_pg = &ctx->stat_mem;
4440 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4441 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4442 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4443 &req.stat_pg_size_stat_lvl,
4444 &req.stat_page_dir);
4447 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4448 num_entries = &req.tqm_sp_num_entries;
4449 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4450 pg_dir = &req.tqm_sp_page_dir;
4451 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4452 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4453 if (!(enables & ena))
4456 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4458 ctx_pg = ctx->tqm_mem[i];
4459 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4460 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4463 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4464 HWRM_CHECK_RESULT();
4471 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4473 struct hwrm_port_qstats_ext_input req = {0};
4474 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4475 struct bnxt_pf_info *pf = &bp->pf;
4478 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4479 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4482 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4484 req.port_id = rte_cpu_to_le_16(pf->port_id);
4485 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4486 req.tx_stat_host_addr =
4487 rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4489 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4491 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4492 req.rx_stat_host_addr =
4493 rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4495 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4497 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4500 bp->fw_rx_port_stats_ext_size = 0;
4501 bp->fw_tx_port_stats_ext_size = 0;
4503 bp->fw_rx_port_stats_ext_size =
4504 rte_le_to_cpu_16(resp->rx_stat_size);
4505 bp->fw_tx_port_stats_ext_size =
4506 rte_le_to_cpu_16(resp->tx_stat_size);
4509 HWRM_CHECK_RESULT();