1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SPEC_CODE_1_8_3 0x10803
31 #define HWRM_VERSION_1_9_1 0x10901
32 #define HWRM_VERSION_1_9_2 0x10903
34 struct bnxt_plcmodes_cfg {
36 uint16_t jumbo_thresh;
38 uint16_t hds_threshold;
41 static int page_getenum(size_t size)
57 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
58 return sizeof(void *) * 8 - 1;
61 static int page_roundup(size_t size)
63 return 1 << page_getenum(size);
66 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
70 if (rmem->nr_pages > 1) {
72 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
74 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
79 * HWRM Functions (sent to HWRM)
80 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
81 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
82 * command was failed by the ChiMP.
85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
86 uint32_t msg_len, bool use_kong_mb)
89 struct input *req = msg;
90 struct output *resp = bp->hwrm_cmd_resp_addr;
94 uint16_t max_req_len = bp->max_req_len;
95 struct hwrm_short_input short_input = { 0 };
96 uint16_t bar_offset = use_kong_mb ?
97 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
98 uint16_t mb_trigger_offset = use_kong_mb ?
99 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
101 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
102 msg_len > bp->max_req_len) {
103 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
105 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
106 memcpy(short_cmd_req, req, msg_len);
108 short_input.req_type = rte_cpu_to_le_16(req->req_type);
109 short_input.signature = rte_cpu_to_le_16(
110 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
111 short_input.size = rte_cpu_to_le_16(msg_len);
112 short_input.req_addr =
113 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
115 data = (uint32_t *)&short_input;
116 msg_len = sizeof(short_input);
118 /* Sync memory write before updating doorbell */
121 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
124 /* Write request msg to hwrm channel */
125 for (i = 0; i < msg_len; i += 4) {
126 bar = (uint8_t *)bp->bar0 + bar_offset + i;
127 rte_write32(*data, bar);
131 /* Zero the rest of the request space */
132 for (; i < max_req_len; i += 4) {
133 bar = (uint8_t *)bp->bar0 + bar_offset + i;
137 /* Ring channel doorbell */
138 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
141 /* Poll for the valid bit */
142 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
143 /* Sanity check on the resp->resp_len */
145 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
146 /* Last byte of resp contains the valid key */
147 valid = (uint8_t *)resp + resp->resp_len - 1;
148 if (*valid == HWRM_RESP_VALID_KEY)
154 if (i >= HWRM_CMD_TIMEOUT) {
155 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
166 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
167 * spinlock, and does initial processing.
169 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
170 * releases the spinlock only if it returns. If the regular int return codes
171 * are not used by the function, HWRM_CHECK_RESULT() should not be used
172 * directly, rather it should be copied and modified to suit the function.
174 * HWRM_UNLOCK() must be called after all response processing is completed.
176 #define HWRM_PREP(req, type, kong) do { \
177 rte_spinlock_lock(&bp->hwrm_lock); \
178 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
179 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
180 req.cmpl_ring = rte_cpu_to_le_16(-1); \
181 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
182 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
183 req.target_id = rte_cpu_to_le_16(0xffff); \
184 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
187 #define HWRM_CHECK_RESULT_SILENT() do {\
189 rte_spinlock_unlock(&bp->hwrm_lock); \
192 if (resp->error_code) { \
193 rc = rte_le_to_cpu_16(resp->error_code); \
194 rte_spinlock_unlock(&bp->hwrm_lock); \
199 #define HWRM_CHECK_RESULT() do {\
201 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
202 rte_spinlock_unlock(&bp->hwrm_lock); \
203 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
209 if (resp->error_code) { \
210 rc = rte_le_to_cpu_16(resp->error_code); \
211 if (resp->resp_len >= 16) { \
212 struct hwrm_err_output *tmp_hwrm_err_op = \
215 "error %d:%d:%08x:%04x\n", \
216 rc, tmp_hwrm_err_op->cmd_err, \
218 tmp_hwrm_err_op->opaque_0), \
220 tmp_hwrm_err_op->opaque_1)); \
222 PMD_DRV_LOG(ERR, "error %d\n", rc); \
224 rte_spinlock_unlock(&bp->hwrm_lock); \
225 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
233 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
235 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
238 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
239 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
241 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
242 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
245 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
253 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
254 struct bnxt_vnic_info *vnic,
256 struct bnxt_vlan_table_entry *vlan_table)
259 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
260 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
263 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
266 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
267 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
269 /* FIXME add multicast flag, when multicast adding options is supported
272 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
273 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
274 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
275 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
276 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
277 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
278 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
279 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
280 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
281 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
282 if (vnic->mc_addr_cnt) {
283 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
284 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
285 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
288 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
289 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
290 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
291 rte_mem_virt2iova(vlan_table));
292 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
294 req.mask = rte_cpu_to_le_32(mask);
296 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
304 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
306 struct bnxt_vlan_antispoof_table_entry *vlan_table)
309 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
310 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
311 bp->hwrm_cmd_resp_addr;
314 * Older HWRM versions did not support this command, and the set_rx_mask
315 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
316 * removed from set_rx_mask call, and this command was added.
318 * This command is also present from 1.7.8.11 and higher,
321 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
322 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
323 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
328 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
329 req.fid = rte_cpu_to_le_16(fid);
331 req.vlan_tag_mask_tbl_addr =
332 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
333 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
335 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
343 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
344 struct bnxt_filter_info *filter)
347 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
348 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
350 if (filter->fw_l2_filter_id == UINT64_MAX)
353 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
355 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
362 filter->fw_l2_filter_id = UINT64_MAX;
367 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
369 struct bnxt_filter_info *filter)
372 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
373 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
374 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
375 const struct rte_eth_vmdq_rx_conf *conf =
376 &dev_conf->rx_adv_conf.vmdq_rx_conf;
377 uint32_t enables = 0;
378 uint16_t j = dst_id - 1;
380 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
381 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
382 conf->pool_map[j].pools & (1UL << j)) {
384 "Add vlan %u to vmdq pool %u\n",
385 conf->pool_map[j].vlan_id, j);
387 filter->l2_ivlan = conf->pool_map[j].vlan_id;
389 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
390 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
393 if (filter->fw_l2_filter_id != UINT64_MAX)
394 bnxt_hwrm_clear_l2_filter(bp, filter);
396 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
398 req.flags = rte_cpu_to_le_32(filter->flags);
400 rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
402 enables = filter->enables |
403 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
404 req.dst_id = rte_cpu_to_le_16(dst_id);
407 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
408 memcpy(req.l2_addr, filter->l2_addr,
411 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
412 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
415 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
416 req.l2_ovlan = filter->l2_ovlan;
418 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
419 req.l2_ivlan = filter->l2_ivlan;
421 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
422 req.l2_ovlan_mask = filter->l2_ovlan_mask;
424 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
425 req.l2_ivlan_mask = filter->l2_ivlan_mask;
426 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
427 req.src_id = rte_cpu_to_le_32(filter->src_id);
428 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
429 req.src_type = filter->src_type;
431 req.enables = rte_cpu_to_le_32(enables);
433 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
437 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
443 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
445 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
446 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
453 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
456 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
459 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
460 if (ptp->tx_tstamp_en)
461 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
464 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
465 req.flags = rte_cpu_to_le_32(flags);
466 req.enables = rte_cpu_to_le_32
467 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
468 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
470 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
476 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
479 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
480 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
481 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
483 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
487 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
489 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
491 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
495 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
498 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
502 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
503 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
504 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
505 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
506 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
507 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
508 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
509 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
510 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
511 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
512 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
513 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
514 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
515 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
516 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
517 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
518 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
519 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
527 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
530 struct hwrm_func_qcaps_input req = {.req_type = 0 };
531 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
532 uint16_t new_max_vfs;
536 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
538 req.fid = rte_cpu_to_le_16(0xffff);
540 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
544 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
545 flags = rte_le_to_cpu_32(resp->flags);
547 bp->pf.port_id = resp->port_id;
548 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
549 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
550 new_max_vfs = bp->pdev->max_vfs;
551 if (new_max_vfs != bp->pf.max_vfs) {
553 rte_free(bp->pf.vf_info);
554 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
555 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
556 bp->pf.max_vfs = new_max_vfs;
557 for (i = 0; i < new_max_vfs; i++) {
558 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
559 bp->pf.vf_info[i].vlan_table =
560 rte_zmalloc("VF VLAN table",
563 if (bp->pf.vf_info[i].vlan_table == NULL)
565 "Fail to alloc VLAN table for VF %d\n",
569 bp->pf.vf_info[i].vlan_table);
570 bp->pf.vf_info[i].vlan_as_table =
571 rte_zmalloc("VF VLAN AS table",
574 if (bp->pf.vf_info[i].vlan_as_table == NULL)
576 "Alloc VLAN AS table for VF %d fail\n",
580 bp->pf.vf_info[i].vlan_as_table);
581 STAILQ_INIT(&bp->pf.vf_info[i].filter);
586 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
587 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
588 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
589 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
590 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
591 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
592 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
593 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
595 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
596 /* TODO: For now, do not support VMDq/RFS on VFs. */
601 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
605 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
607 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
608 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
609 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
610 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
612 bnxt_hwrm_ptp_qcfg(bp);
616 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
617 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
624 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
628 rc = __bnxt_hwrm_func_qcaps(bp);
629 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
630 rc = bnxt_alloc_ctx_mem(bp);
634 rc = bnxt_hwrm_func_resc_qcaps(bp);
636 bp->flags |= BNXT_FLAG_NEW_RM;
642 int bnxt_hwrm_func_reset(struct bnxt *bp)
645 struct hwrm_func_reset_input req = {.req_type = 0 };
646 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
648 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
650 req.enables = rte_cpu_to_le_32(0);
652 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
660 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
663 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
664 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
666 if (bp->flags & BNXT_FLAG_REGISTERED)
669 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
670 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
671 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
672 req.ver_maj = RTE_VER_YEAR;
673 req.ver_min = RTE_VER_MONTH;
674 req.ver_upd = RTE_VER_MINOR;
677 req.enables |= rte_cpu_to_le_32(
678 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
679 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
680 RTE_MIN(sizeof(req.vf_req_fwd),
681 sizeof(bp->pf.vf_req_fwd)));
684 * PF can sniff HWRM API issued by VF. This can be set up by
685 * linux driver and inherited by the DPDK PF driver. Clear
686 * this HWRM sniffer list in FW because DPDK PF driver does
690 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
693 req.async_event_fwd[0] |=
694 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
695 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
696 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
697 req.async_event_fwd[1] |=
698 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
699 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
701 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
706 bp->flags |= BNXT_FLAG_REGISTERED;
711 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
713 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
716 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
719 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
724 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
725 struct hwrm_func_vf_cfg_input req = {0};
727 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
729 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
730 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
731 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
732 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
733 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
735 if (BNXT_HAS_RING_GRPS(bp)) {
736 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
737 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
740 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
741 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
742 AGG_RING_MULTIPLIER);
743 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
744 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
746 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
747 if (bp->vf_resv_strategy ==
748 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
749 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
750 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
751 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
752 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
753 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
754 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
758 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
759 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
760 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
761 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
762 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
763 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
765 if (test && BNXT_HAS_RING_GRPS(bp))
766 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
768 req.flags = rte_cpu_to_le_32(flags);
769 req.enables |= rte_cpu_to_le_32(enables);
771 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
774 HWRM_CHECK_RESULT_SILENT();
782 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
785 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
786 struct hwrm_func_resource_qcaps_input req = {0};
788 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
789 req.fid = rte_cpu_to_le_16(0xffff);
791 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
796 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
797 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
798 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
799 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
800 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
801 /* func_resource_qcaps does not return max_rx_em_flows.
802 * So use the value provided by func_qcaps.
805 rte_le_to_cpu_16(resp->max_l2_ctxs) +
807 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
808 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
810 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
811 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
812 if (bp->vf_resv_strategy >
813 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
814 bp->vf_resv_strategy =
815 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
821 int bnxt_hwrm_ver_get(struct bnxt *bp)
824 struct hwrm_ver_get_input req = {.req_type = 0 };
825 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
827 uint16_t max_resp_len;
828 char type[RTE_MEMZONE_NAMESIZE];
829 uint32_t dev_caps_cfg;
831 bp->max_req_len = HWRM_MAX_REQ_LEN;
832 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
834 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
835 req.hwrm_intf_min = HWRM_VERSION_MINOR;
836 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
838 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
842 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
843 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
844 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
845 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
846 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
847 (resp->hwrm_fw_min_8b << 16) |
848 (resp->hwrm_fw_bld_8b << 8) |
849 resp->hwrm_fw_rsvd_8b;
850 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
851 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
853 fw_version = resp->hwrm_intf_maj_8b << 16;
854 fw_version |= resp->hwrm_intf_min_8b << 8;
855 fw_version |= resp->hwrm_intf_upd_8b;
856 bp->hwrm_spec_code = fw_version;
858 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
859 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
864 if (bp->max_req_len > resp->max_req_win_len) {
865 PMD_DRV_LOG(ERR, "Unsupported request length\n");
868 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
869 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
870 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
871 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
873 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
874 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
876 if (bp->max_resp_len != max_resp_len) {
877 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
878 bp->pdev->addr.domain, bp->pdev->addr.bus,
879 bp->pdev->addr.devid, bp->pdev->addr.function);
881 rte_free(bp->hwrm_cmd_resp_addr);
883 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
884 if (bp->hwrm_cmd_resp_addr == NULL) {
888 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
889 bp->hwrm_cmd_resp_dma_addr =
890 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
891 if (bp->hwrm_cmd_resp_dma_addr == 0) {
893 "Unable to map response buffer to physical memory.\n");
897 bp->max_resp_len = max_resp_len;
901 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
903 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
904 PMD_DRV_LOG(DEBUG, "Short command supported\n");
905 bp->flags |= BNXT_FLAG_SHORT_CMD;
909 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
911 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
912 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
913 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
914 bp->pdev->addr.domain, bp->pdev->addr.bus,
915 bp->pdev->addr.devid, bp->pdev->addr.function);
917 rte_free(bp->hwrm_short_cmd_req_addr);
919 bp->hwrm_short_cmd_req_addr =
920 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
921 if (bp->hwrm_short_cmd_req_addr == NULL) {
925 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
926 bp->hwrm_short_cmd_req_dma_addr =
927 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
928 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
929 rte_free(bp->hwrm_short_cmd_req_addr);
931 "Unable to map buffer to physical memory.\n");
937 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
938 bp->flags |= BNXT_FLAG_KONG_MB_EN;
939 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
942 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
943 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
950 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
953 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
954 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
956 if (!(bp->flags & BNXT_FLAG_REGISTERED))
959 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
962 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
967 bp->flags &= ~BNXT_FLAG_REGISTERED;
972 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
975 struct hwrm_port_phy_cfg_input req = {0};
976 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
977 uint32_t enables = 0;
979 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
982 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
983 if (bp->link_info.auto_mode && conf->link_speed) {
984 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
985 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
988 req.flags = rte_cpu_to_le_32(conf->phy_flags);
989 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
990 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
992 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
993 * any auto mode, even "none".
995 if (!conf->link_speed) {
996 /* No speeds specified. Enable AutoNeg - all speeds */
998 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1000 /* AutoNeg - Advertise speeds specified. */
1001 if (conf->auto_link_speed_mask &&
1002 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1004 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1005 req.auto_link_speed_mask =
1006 conf->auto_link_speed_mask;
1008 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1011 req.auto_duplex = conf->duplex;
1012 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1013 req.auto_pause = conf->auto_pause;
1014 req.force_pause = conf->force_pause;
1015 /* Set force_pause if there is no auto or if there is a force */
1016 if (req.auto_pause && !req.force_pause)
1017 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1019 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1021 req.enables = rte_cpu_to_le_32(enables);
1024 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1025 PMD_DRV_LOG(INFO, "Force Link Down\n");
1028 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1030 HWRM_CHECK_RESULT();
1036 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1037 struct bnxt_link_info *link_info)
1040 struct hwrm_port_phy_qcfg_input req = {0};
1041 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1043 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1045 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1047 HWRM_CHECK_RESULT();
1049 link_info->phy_link_status = resp->link;
1050 link_info->link_up =
1051 (link_info->phy_link_status ==
1052 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1053 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1054 link_info->duplex = resp->duplex_cfg;
1055 link_info->pause = resp->pause;
1056 link_info->auto_pause = resp->auto_pause;
1057 link_info->force_pause = resp->force_pause;
1058 link_info->auto_mode = resp->auto_mode;
1059 link_info->phy_type = resp->phy_type;
1060 link_info->media_type = resp->media_type;
1062 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1063 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1064 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1065 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1066 link_info->phy_ver[0] = resp->phy_maj;
1067 link_info->phy_ver[1] = resp->phy_min;
1068 link_info->phy_ver[2] = resp->phy_bld;
1072 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1073 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1074 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1075 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1076 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1077 link_info->auto_link_speed_mask);
1078 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1079 link_info->force_link_speed);
1084 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1087 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1088 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1091 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1093 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1094 /* HWRM Version >= 1.9.1 */
1095 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1097 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1098 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1100 HWRM_CHECK_RESULT();
1102 #define GET_QUEUE_INFO(x) \
1103 bp->cos_queue[x].id = resp->queue_id##x; \
1104 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1117 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1118 bp->tx_cosq_id = bp->cos_queue[0].id;
1120 /* iterate and find the COSq profile to use for Tx */
1121 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1122 if (bp->cos_queue[i].profile ==
1123 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1124 bp->tx_cosq_id = bp->cos_queue[i].id;
1130 bp->max_tc = resp->max_configurable_queues;
1131 bp->max_lltc = resp->max_configurable_lossless_queues;
1132 if (bp->max_tc > BNXT_MAX_QUEUE)
1133 bp->max_tc = BNXT_MAX_QUEUE;
1134 bp->max_q = bp->max_tc;
1136 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1141 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1142 struct bnxt_ring *ring,
1143 uint32_t ring_type, uint32_t map_index,
1144 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1147 uint32_t enables = 0;
1148 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1149 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1150 struct rte_mempool *mb_pool;
1151 uint16_t rx_buf_size;
1153 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1155 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1156 req.fbo = rte_cpu_to_le_32(0);
1157 /* Association of ring index with doorbell index */
1158 req.logical_id = rte_cpu_to_le_16(map_index);
1159 req.length = rte_cpu_to_le_32(ring->ring_size);
1161 switch (ring_type) {
1162 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1163 req.ring_type = ring_type;
1164 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1165 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1166 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1167 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1169 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1171 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1172 req.ring_type = ring_type;
1173 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1174 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1175 if (BNXT_CHIP_THOR(bp)) {
1176 mb_pool = bp->rx_queues[0]->mb_pool;
1177 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1178 RTE_PKTMBUF_HEADROOM;
1179 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1181 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1183 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1185 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1187 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1188 req.ring_type = ring_type;
1189 if (BNXT_HAS_NQ(bp)) {
1190 /* Association of cp ring with nq */
1191 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1193 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1195 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1197 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1198 req.ring_type = ring_type;
1199 req.page_size = BNXT_PAGE_SHFT;
1200 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1202 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1203 req.ring_type = ring_type;
1204 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1206 mb_pool = bp->rx_queues[0]->mb_pool;
1207 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1208 RTE_PKTMBUF_HEADROOM;
1209 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1211 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1212 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1213 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1214 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1217 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1222 req.enables = rte_cpu_to_le_32(enables);
1224 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1226 if (rc || resp->error_code) {
1227 if (rc == 0 && resp->error_code)
1228 rc = rte_le_to_cpu_16(resp->error_code);
1229 switch (ring_type) {
1230 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1232 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1235 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1237 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1240 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1242 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1246 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1248 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1251 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1253 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1257 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1263 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1268 int bnxt_hwrm_ring_free(struct bnxt *bp,
1269 struct bnxt_ring *ring, uint32_t ring_type)
1272 struct hwrm_ring_free_input req = {.req_type = 0 };
1273 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1275 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1277 req.ring_type = ring_type;
1278 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1280 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1282 if (rc || resp->error_code) {
1283 if (rc == 0 && resp->error_code)
1284 rc = rte_le_to_cpu_16(resp->error_code);
1287 switch (ring_type) {
1288 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1289 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1292 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1293 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1296 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1297 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1300 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1302 "hwrm_ring_free nq failed. rc:%d\n", rc);
1304 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1306 "hwrm_ring_free agg failed. rc:%d\n", rc);
1309 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1317 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1320 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1321 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1323 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1325 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1326 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1327 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1328 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1330 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1332 HWRM_CHECK_RESULT();
1334 bp->grp_info[idx].fw_grp_id =
1335 rte_le_to_cpu_16(resp->ring_group_id);
1342 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1345 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1346 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1348 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1350 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1352 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1354 HWRM_CHECK_RESULT();
1357 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1361 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1364 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1365 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1367 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1370 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1372 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1374 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1376 HWRM_CHECK_RESULT();
1382 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1383 unsigned int idx __rte_unused)
1386 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1387 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1389 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1391 req.update_period_ms = rte_cpu_to_le_32(0);
1393 req.stats_dma_addr =
1394 rte_cpu_to_le_64(cpr->hw_stats_map);
1396 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1398 HWRM_CHECK_RESULT();
1400 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1407 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1408 unsigned int idx __rte_unused)
1411 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1412 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1414 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1416 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1418 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1420 HWRM_CHECK_RESULT();
1426 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1429 struct hwrm_vnic_alloc_input req = { 0 };
1430 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1432 if (!BNXT_HAS_RING_GRPS(bp))
1433 goto skip_ring_grps;
1435 /* map ring groups to this vnic */
1436 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1437 vnic->start_grp_id, vnic->end_grp_id);
1438 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1439 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1441 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1442 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1443 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1444 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1447 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1448 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1449 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1451 if (vnic->func_default)
1453 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1454 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1456 HWRM_CHECK_RESULT();
1458 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1460 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1464 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1465 struct bnxt_vnic_info *vnic,
1466 struct bnxt_plcmodes_cfg *pmode)
1469 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1470 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1472 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1474 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1476 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1478 HWRM_CHECK_RESULT();
1480 pmode->flags = rte_le_to_cpu_32(resp->flags);
1481 /* dflt_vnic bit doesn't exist in the _cfg command */
1482 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1483 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1484 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1485 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1492 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1493 struct bnxt_vnic_info *vnic,
1494 struct bnxt_plcmodes_cfg *pmode)
1497 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1498 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1500 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1502 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1503 req.flags = rte_cpu_to_le_32(pmode->flags);
1504 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1505 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1506 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1507 req.enables = rte_cpu_to_le_32(
1508 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1509 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1510 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1513 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1515 HWRM_CHECK_RESULT();
1521 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1524 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1525 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1526 struct bnxt_plcmodes_cfg pmodes = { 0 };
1527 uint32_t ctx_enable_flag = 0;
1528 uint32_t enables = 0;
1530 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1531 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1535 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1539 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1541 if (BNXT_CHIP_THOR(bp)) {
1542 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1543 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1544 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1546 req.default_rx_ring_id =
1547 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1548 req.default_cmpl_ring_id =
1549 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1550 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1551 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1555 /* Only RSS support for now TBD: COS & LB */
1556 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1557 if (vnic->lb_rule != 0xffff)
1558 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1559 if (vnic->cos_rule != 0xffff)
1560 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1561 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1562 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1563 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1565 enables |= ctx_enable_flag;
1566 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1567 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1568 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1569 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1572 req.enables = rte_cpu_to_le_32(enables);
1573 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1574 req.mru = rte_cpu_to_le_16(vnic->mru);
1575 /* Configure default VNIC only once. */
1576 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1578 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1579 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1581 if (vnic->vlan_strip)
1583 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1586 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1587 if (vnic->roce_dual)
1588 req.flags |= rte_cpu_to_le_32(
1589 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1590 if (vnic->roce_only)
1591 req.flags |= rte_cpu_to_le_32(
1592 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1593 if (vnic->rss_dflt_cr)
1594 req.flags |= rte_cpu_to_le_32(
1595 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1597 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1599 HWRM_CHECK_RESULT();
1602 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1607 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1611 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1612 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1614 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1615 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1618 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1621 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1622 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1623 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1625 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1627 HWRM_CHECK_RESULT();
1629 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1630 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1631 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1632 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1633 vnic->mru = rte_le_to_cpu_16(resp->mru);
1634 vnic->func_default = rte_le_to_cpu_32(
1635 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1636 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1637 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1638 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1639 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1640 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1641 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1642 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1643 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1644 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1645 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1652 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1653 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1657 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1658 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1659 bp->hwrm_cmd_resp_addr;
1661 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1663 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1664 HWRM_CHECK_RESULT();
1666 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1667 if (!BNXT_HAS_RING_GRPS(bp))
1668 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1669 else if (ctx_idx == 0)
1670 vnic->rss_rule = ctx_id;
1677 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1678 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1681 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1682 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1683 bp->hwrm_cmd_resp_addr;
1685 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1686 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1689 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1691 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1693 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1695 HWRM_CHECK_RESULT();
1701 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1704 struct hwrm_vnic_free_input req = {.req_type = 0 };
1705 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1707 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1708 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1712 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1714 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1716 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1718 HWRM_CHECK_RESULT();
1721 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1722 /* Configure default VNIC again if necessary. */
1723 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1724 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1730 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1734 int nr_ctxs = bp->max_ring_grps;
1735 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1736 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1738 if (!(vnic->rss_table && vnic->hash_type))
1741 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1743 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1744 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1745 req.hash_mode_flags = vnic->hash_mode;
1747 req.hash_key_tbl_addr =
1748 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1750 for (i = 0; i < nr_ctxs; i++) {
1751 req.ring_grp_tbl_addr =
1752 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1753 i * HW_HASH_INDEX_SIZE);
1754 req.ring_table_pair_index = i;
1755 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1757 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1760 HWRM_CHECK_RESULT();
1770 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1771 struct bnxt_vnic_info *vnic)
1774 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1775 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1777 if (BNXT_CHIP_THOR(bp))
1778 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1780 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1782 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1783 req.hash_mode_flags = vnic->hash_mode;
1785 req.ring_grp_tbl_addr =
1786 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1787 req.hash_key_tbl_addr =
1788 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1789 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1790 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1792 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1794 HWRM_CHECK_RESULT();
1800 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1801 struct bnxt_vnic_info *vnic)
1804 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1805 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1808 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1809 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1813 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1815 req.flags = rte_cpu_to_le_32(
1816 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1818 req.enables = rte_cpu_to_le_32(
1819 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1821 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1822 size -= RTE_PKTMBUF_HEADROOM;
1824 req.jumbo_thresh = rte_cpu_to_le_16(size);
1825 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1827 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1829 HWRM_CHECK_RESULT();
1835 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1836 struct bnxt_vnic_info *vnic, bool enable)
1839 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1840 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1842 if (BNXT_CHIP_THOR(bp))
1845 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1848 req.enables = rte_cpu_to_le_32(
1849 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1850 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1851 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1852 req.flags = rte_cpu_to_le_32(
1853 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1854 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1855 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1856 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1857 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1858 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1859 req.max_agg_segs = rte_cpu_to_le_16(5);
1861 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1862 req.min_agg_len = rte_cpu_to_le_32(512);
1864 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1866 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1868 HWRM_CHECK_RESULT();
1874 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1876 struct hwrm_func_cfg_input req = {0};
1877 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1880 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1881 req.enables = rte_cpu_to_le_32(
1882 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1883 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1884 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1886 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1888 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1889 HWRM_CHECK_RESULT();
1892 bp->pf.vf_info[vf].random_mac = false;
1897 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1901 struct hwrm_func_qstats_input req = {.req_type = 0};
1902 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1904 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1906 req.fid = rte_cpu_to_le_16(fid);
1908 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1910 HWRM_CHECK_RESULT();
1913 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1920 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1921 struct rte_eth_stats *stats)
1924 struct hwrm_func_qstats_input req = {.req_type = 0};
1925 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1927 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1929 req.fid = rte_cpu_to_le_16(fid);
1931 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1933 HWRM_CHECK_RESULT();
1935 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1936 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1937 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1938 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1939 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1940 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1942 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1943 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1944 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1945 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1946 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1947 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1949 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1950 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1951 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1958 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1961 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1962 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1964 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1966 req.fid = rte_cpu_to_le_16(fid);
1968 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1970 HWRM_CHECK_RESULT();
1977 * HWRM utility functions
1980 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1985 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1986 struct bnxt_tx_queue *txq;
1987 struct bnxt_rx_queue *rxq;
1988 struct bnxt_cp_ring_info *cpr;
1990 if (i >= bp->rx_cp_nr_rings) {
1991 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1994 rxq = bp->rx_queues[i];
1998 rc = bnxt_hwrm_stat_clear(bp, cpr);
2005 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2009 struct bnxt_cp_ring_info *cpr;
2011 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2013 if (i >= bp->rx_cp_nr_rings) {
2014 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2016 cpr = bp->rx_queues[i]->cp_ring;
2017 if (BNXT_HAS_RING_GRPS(bp))
2018 bp->grp_info[i].fw_stats_ctx = -1;
2020 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2021 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2022 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2030 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2035 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2036 struct bnxt_tx_queue *txq;
2037 struct bnxt_rx_queue *rxq;
2038 struct bnxt_cp_ring_info *cpr;
2040 if (i >= bp->rx_cp_nr_rings) {
2041 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2044 rxq = bp->rx_queues[i];
2048 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2056 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2061 if (!BNXT_HAS_RING_GRPS(bp))
2064 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2066 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2069 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2077 static void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2079 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2081 bnxt_hwrm_ring_free(bp, cp_ring,
2082 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2083 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2084 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2085 sizeof(*cpr->cp_desc_ring));
2086 cpr->cp_raw_cons = 0;
2089 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2091 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2093 bnxt_hwrm_ring_free(bp, cp_ring,
2094 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2095 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2096 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2097 sizeof(*cpr->cp_desc_ring));
2098 cpr->cp_raw_cons = 0;
2102 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2104 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2105 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2106 struct bnxt_ring *ring = rxr->rx_ring_struct;
2107 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2109 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2110 bnxt_hwrm_ring_free(bp, ring,
2111 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2112 ring->fw_ring_id = INVALID_HW_RING_ID;
2113 if (BNXT_HAS_RING_GRPS(bp))
2114 bp->grp_info[queue_index].rx_fw_ring_id =
2116 memset(rxr->rx_desc_ring, 0,
2117 rxr->rx_ring_struct->ring_size *
2118 sizeof(*rxr->rx_desc_ring));
2119 memset(rxr->rx_buf_ring, 0,
2120 rxr->rx_ring_struct->ring_size *
2121 sizeof(*rxr->rx_buf_ring));
2124 ring = rxr->ag_ring_struct;
2125 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2126 bnxt_hwrm_ring_free(bp, ring,
2127 BNXT_CHIP_THOR(bp) ?
2128 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2129 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2130 ring->fw_ring_id = INVALID_HW_RING_ID;
2131 memset(rxr->ag_buf_ring, 0,
2132 rxr->ag_ring_struct->ring_size *
2133 sizeof(*rxr->ag_buf_ring));
2135 if (BNXT_HAS_RING_GRPS(bp))
2136 bp->grp_info[queue_index].ag_fw_ring_id =
2139 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2140 bnxt_free_cp_ring(bp, cpr);
2142 bnxt_free_nq_ring(bp, rxq->nq_ring);
2145 if (BNXT_HAS_RING_GRPS(bp))
2146 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2149 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2153 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2154 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2155 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2156 struct bnxt_ring *ring = txr->tx_ring_struct;
2157 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2159 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2160 bnxt_hwrm_ring_free(bp, ring,
2161 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2162 ring->fw_ring_id = INVALID_HW_RING_ID;
2163 memset(txr->tx_desc_ring, 0,
2164 txr->tx_ring_struct->ring_size *
2165 sizeof(*txr->tx_desc_ring));
2166 memset(txr->tx_buf_ring, 0,
2167 txr->tx_ring_struct->ring_size *
2168 sizeof(*txr->tx_buf_ring));
2172 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2173 bnxt_free_cp_ring(bp, cpr);
2174 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2176 bnxt_free_nq_ring(bp, txq->nq_ring);
2180 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2181 bnxt_free_hwrm_rx_ring(bp, i);
2186 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2191 if (!BNXT_HAS_RING_GRPS(bp))
2194 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2195 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2202 void bnxt_free_hwrm_resources(struct bnxt *bp)
2204 /* Release memzone */
2205 rte_free(bp->hwrm_cmd_resp_addr);
2206 rte_free(bp->hwrm_short_cmd_req_addr);
2207 bp->hwrm_cmd_resp_addr = NULL;
2208 bp->hwrm_short_cmd_req_addr = NULL;
2209 bp->hwrm_cmd_resp_dma_addr = 0;
2210 bp->hwrm_short_cmd_req_dma_addr = 0;
2213 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2215 struct rte_pci_device *pdev = bp->pdev;
2216 char type[RTE_MEMZONE_NAMESIZE];
2218 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2219 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2220 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2221 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2222 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2223 if (bp->hwrm_cmd_resp_addr == NULL)
2225 bp->hwrm_cmd_resp_dma_addr =
2226 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2227 if (bp->hwrm_cmd_resp_dma_addr == 0) {
2229 "unable to map response address to physical memory\n");
2232 rte_spinlock_init(&bp->hwrm_lock);
2237 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2239 struct bnxt_filter_info *filter;
2242 STAILQ_FOREACH(filter, &vnic->filter, next) {
2243 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2244 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2245 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2246 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2248 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2249 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2257 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2259 struct bnxt_filter_info *filter;
2260 struct rte_flow *flow;
2263 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2264 filter = flow->filter;
2265 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
2266 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2267 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2268 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2269 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2271 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2273 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2281 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2283 struct bnxt_filter_info *filter;
2286 STAILQ_FOREACH(filter, &vnic->filter, next) {
2287 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2288 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2290 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2291 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2294 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2302 void bnxt_free_tunnel_ports(struct bnxt *bp)
2304 if (bp->vxlan_port_cnt)
2305 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2306 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2308 if (bp->geneve_port_cnt)
2309 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2310 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2311 bp->geneve_port = 0;
2314 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2318 if (bp->vnic_info == NULL)
2322 * Cleanup VNICs in reverse order, to make sure the L2 filter
2323 * from vnic0 is last to be cleaned up.
2325 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2326 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2328 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2329 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2333 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2335 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2337 if (BNXT_CHIP_THOR(bp)) {
2338 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2339 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2340 vnic->fw_grp_ids[j]);
2341 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2343 vnic->num_lb_ctxts = 0;
2345 bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2346 vnic->rss_rule = INVALID_HW_RING_ID;
2349 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2351 bnxt_hwrm_vnic_free(bp, vnic);
2353 rte_free(vnic->fw_grp_ids);
2355 /* Ring resources */
2356 bnxt_free_all_hwrm_rings(bp);
2357 bnxt_free_all_hwrm_ring_grps(bp);
2358 bnxt_free_all_hwrm_stat_ctxs(bp);
2359 bnxt_free_tunnel_ports(bp);
2362 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2364 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2366 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2367 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2369 switch (conf_link_speed) {
2370 case ETH_LINK_SPEED_10M_HD:
2371 case ETH_LINK_SPEED_100M_HD:
2373 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2375 return hw_link_duplex;
2378 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2380 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2383 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2385 uint16_t eth_link_speed = 0;
2387 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2388 return ETH_LINK_SPEED_AUTONEG;
2390 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2391 case ETH_LINK_SPEED_100M:
2392 case ETH_LINK_SPEED_100M_HD:
2395 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2397 case ETH_LINK_SPEED_1G:
2399 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2401 case ETH_LINK_SPEED_2_5G:
2403 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2405 case ETH_LINK_SPEED_10G:
2407 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2409 case ETH_LINK_SPEED_20G:
2411 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2413 case ETH_LINK_SPEED_25G:
2415 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2417 case ETH_LINK_SPEED_40G:
2419 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2421 case ETH_LINK_SPEED_50G:
2423 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2425 case ETH_LINK_SPEED_100G:
2427 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2431 "Unsupported link speed %d; default to AUTO\n",
2435 return eth_link_speed;
2438 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2439 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2440 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2441 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2443 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2447 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2450 if (link_speed & ETH_LINK_SPEED_FIXED) {
2451 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2453 if (one_speed & (one_speed - 1)) {
2455 "Invalid advertised speeds (%u) for port %u\n",
2456 link_speed, port_id);
2459 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2461 "Unsupported advertised speed (%u) for port %u\n",
2462 link_speed, port_id);
2466 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2468 "Unsupported advertised speeds (%u) for port %u\n",
2469 link_speed, port_id);
2477 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2481 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2482 if (bp->link_info.support_speeds)
2483 return bp->link_info.support_speeds;
2484 link_speed = BNXT_SUPPORTED_SPEEDS;
2487 if (link_speed & ETH_LINK_SPEED_100M)
2488 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2489 if (link_speed & ETH_LINK_SPEED_100M_HD)
2490 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2491 if (link_speed & ETH_LINK_SPEED_1G)
2492 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2493 if (link_speed & ETH_LINK_SPEED_2_5G)
2494 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2495 if (link_speed & ETH_LINK_SPEED_10G)
2496 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2497 if (link_speed & ETH_LINK_SPEED_20G)
2498 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2499 if (link_speed & ETH_LINK_SPEED_25G)
2500 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2501 if (link_speed & ETH_LINK_SPEED_40G)
2502 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2503 if (link_speed & ETH_LINK_SPEED_50G)
2504 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2505 if (link_speed & ETH_LINK_SPEED_100G)
2506 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2510 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2512 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2514 switch (hw_link_speed) {
2515 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2516 eth_link_speed = ETH_SPEED_NUM_100M;
2518 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2519 eth_link_speed = ETH_SPEED_NUM_1G;
2521 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2522 eth_link_speed = ETH_SPEED_NUM_2_5G;
2524 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2525 eth_link_speed = ETH_SPEED_NUM_10G;
2527 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2528 eth_link_speed = ETH_SPEED_NUM_20G;
2530 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2531 eth_link_speed = ETH_SPEED_NUM_25G;
2533 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2534 eth_link_speed = ETH_SPEED_NUM_40G;
2536 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2537 eth_link_speed = ETH_SPEED_NUM_50G;
2539 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2540 eth_link_speed = ETH_SPEED_NUM_100G;
2542 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2544 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2548 return eth_link_speed;
2551 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2553 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2555 switch (hw_link_duplex) {
2556 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2557 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2559 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2561 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2562 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2565 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2569 return eth_link_duplex;
2572 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2575 struct bnxt_link_info *link_info = &bp->link_info;
2577 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2580 "Get link config failed with rc %d\n", rc);
2583 if (link_info->link_speed)
2585 bnxt_parse_hw_link_speed(link_info->link_speed);
2587 link->link_speed = ETH_SPEED_NUM_NONE;
2588 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2589 link->link_status = link_info->link_up;
2590 link->link_autoneg = link_info->auto_mode ==
2591 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2592 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2597 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2600 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2601 struct bnxt_link_info link_req;
2602 uint16_t speed, autoneg;
2604 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2607 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2608 bp->eth_dev->data->port_id);
2612 memset(&link_req, 0, sizeof(link_req));
2613 link_req.link_up = link_up;
2617 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2618 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2619 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2620 /* Autoneg can be done only when the FW allows */
2621 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2622 bp->link_info.force_link_speed)) {
2623 link_req.phy_flags |=
2624 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2625 link_req.auto_link_speed_mask =
2626 bnxt_parse_eth_link_speed_mask(bp,
2627 dev_conf->link_speeds);
2629 if (bp->link_info.phy_type ==
2630 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2631 bp->link_info.phy_type ==
2632 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2633 bp->link_info.media_type ==
2634 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2635 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2639 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2640 /* If user wants a particular speed try that first. */
2642 link_req.link_speed = speed;
2643 else if (bp->link_info.force_link_speed)
2644 link_req.link_speed = bp->link_info.force_link_speed;
2646 link_req.link_speed = bp->link_info.auto_link_speed;
2648 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2649 link_req.auto_pause = bp->link_info.auto_pause;
2650 link_req.force_pause = bp->link_info.force_pause;
2653 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2656 "Set link config failed with rc %d\n", rc);
2664 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2666 struct hwrm_func_qcfg_input req = {0};
2667 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2671 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2672 req.fid = rte_cpu_to_le_16(0xffff);
2674 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2676 HWRM_CHECK_RESULT();
2678 /* Hard Coded.. 0xfff VLAN ID mask */
2679 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2680 flags = rte_le_to_cpu_16(resp->flags);
2681 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2682 bp->flags |= BNXT_FLAG_MULTI_HOST;
2684 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2685 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2686 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2692 switch (resp->port_partition_type) {
2693 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2694 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2695 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2697 bp->port_partition_type = resp->port_partition_type;
2700 bp->port_partition_type = 0;
2709 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2710 struct hwrm_func_qcaps_output *qcaps)
2712 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2713 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2714 sizeof(qcaps->mac_address));
2715 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2716 qcaps->max_rx_rings = fcfg->num_rx_rings;
2717 qcaps->max_tx_rings = fcfg->num_tx_rings;
2718 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2719 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2721 qcaps->first_vf_id = 0;
2722 qcaps->max_vnics = fcfg->num_vnics;
2723 qcaps->max_decap_records = 0;
2724 qcaps->max_encap_records = 0;
2725 qcaps->max_tx_wm_flows = 0;
2726 qcaps->max_tx_em_flows = 0;
2727 qcaps->max_rx_wm_flows = 0;
2728 qcaps->max_rx_em_flows = 0;
2729 qcaps->max_flow_id = 0;
2730 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2731 qcaps->max_sp_tx_rings = 0;
2732 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2735 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2737 struct hwrm_func_cfg_input req = {0};
2738 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2742 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2743 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2744 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2745 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2746 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2747 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2748 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2749 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2750 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2752 if (BNXT_HAS_RING_GRPS(bp)) {
2753 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2754 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2755 } else if (BNXT_HAS_NQ(bp)) {
2756 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2757 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2760 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2761 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2762 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2763 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2765 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2766 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2767 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2768 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2769 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2770 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2771 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2772 req.fid = rte_cpu_to_le_16(0xffff);
2773 req.enables = rte_cpu_to_le_32(enables);
2775 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2777 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2779 HWRM_CHECK_RESULT();
2785 static void populate_vf_func_cfg_req(struct bnxt *bp,
2786 struct hwrm_func_cfg_input *req,
2789 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2790 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2791 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2792 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2793 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2794 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2795 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2796 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2797 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2798 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2800 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2801 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2803 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2804 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2806 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2808 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2809 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2811 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2812 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2813 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2814 /* TODO: For now, do not support VMDq/RFS on VFs. */
2815 req->num_vnics = rte_cpu_to_le_16(1);
2816 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2820 static void add_random_mac_if_needed(struct bnxt *bp,
2821 struct hwrm_func_cfg_input *cfg_req,
2824 struct rte_ether_addr mac;
2826 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2829 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2831 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2832 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2833 bp->pf.vf_info[vf].random_mac = true;
2835 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2836 RTE_ETHER_ADDR_LEN);
2840 static void reserve_resources_from_vf(struct bnxt *bp,
2841 struct hwrm_func_cfg_input *cfg_req,
2844 struct hwrm_func_qcaps_input req = {0};
2845 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2848 /* Get the actual allocated values now */
2849 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2850 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2851 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2854 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2855 copy_func_cfg_to_qcaps(cfg_req, resp);
2856 } else if (resp->error_code) {
2857 rc = rte_le_to_cpu_16(resp->error_code);
2858 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2859 copy_func_cfg_to_qcaps(cfg_req, resp);
2862 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2863 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2864 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2865 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2866 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2867 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2869 * TODO: While not supporting VMDq with VFs, max_vnics is always
2870 * forced to 1 in this case
2872 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2873 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2878 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2880 struct hwrm_func_qcfg_input req = {0};
2881 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2884 /* Check for zero MAC address */
2885 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2886 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2887 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2889 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2891 } else if (resp->error_code) {
2892 rc = rte_le_to_cpu_16(resp->error_code);
2893 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2896 rc = rte_le_to_cpu_16(resp->vlan);
2903 static int update_pf_resource_max(struct bnxt *bp)
2905 struct hwrm_func_qcfg_input req = {0};
2906 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2909 /* And copy the allocated numbers into the pf struct */
2910 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2911 req.fid = rte_cpu_to_le_16(0xffff);
2912 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2913 HWRM_CHECK_RESULT();
2915 /* Only TX ring value reflects actual allocation? TODO */
2916 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2917 bp->pf.evb_mode = resp->evb_mode;
2924 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2929 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2933 rc = bnxt_hwrm_func_qcaps(bp);
2937 bp->pf.func_cfg_flags &=
2938 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2939 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2940 bp->pf.func_cfg_flags |=
2941 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2942 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2943 rc = __bnxt_hwrm_func_qcaps(bp);
2947 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2949 struct hwrm_func_cfg_input req = {0};
2950 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2957 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2961 rc = bnxt_hwrm_func_qcaps(bp);
2966 bp->pf.active_vfs = num_vfs;
2969 * First, configure the PF to only use one TX ring. This ensures that
2970 * there are enough rings for all VFs.
2972 * If we don't do this, when we call func_alloc() later, we will lock
2973 * extra rings to the PF that won't be available during func_cfg() of
2976 * This has been fixed with firmware versions above 20.6.54
2978 bp->pf.func_cfg_flags &=
2979 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2980 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2981 bp->pf.func_cfg_flags |=
2982 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2983 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2988 * Now, create and register a buffer to hold forwarded VF requests
2990 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2991 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2992 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2993 if (bp->pf.vf_req_buf == NULL) {
2997 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2998 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2999 for (i = 0; i < num_vfs; i++)
3000 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3001 (i * HWRM_MAX_REQ_LEN);
3003 rc = bnxt_hwrm_func_buf_rgtr(bp);
3007 populate_vf_func_cfg_req(bp, &req, num_vfs);
3009 bp->pf.active_vfs = 0;
3010 for (i = 0; i < num_vfs; i++) {
3011 add_random_mac_if_needed(bp, &req, i);
3013 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3014 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3015 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3016 rc = bnxt_hwrm_send_message(bp,
3021 /* Clear enable flag for next pass */
3022 req.enables &= ~rte_cpu_to_le_32(
3023 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3025 if (rc || resp->error_code) {
3027 "Failed to initizlie VF %d\n", i);
3029 "Not all VFs available. (%d, %d)\n",
3030 rc, resp->error_code);
3037 reserve_resources_from_vf(bp, &req, i);
3038 bp->pf.active_vfs++;
3039 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3043 * Now configure the PF to use "the rest" of the resources
3044 * We're using STD_TX_RING_MODE here though which will limit the TX
3045 * rings. This will allow QoS to function properly. Not setting this
3046 * will cause PF rings to break bandwidth settings.
3048 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3052 rc = update_pf_resource_max(bp);
3059 bnxt_hwrm_func_buf_unrgtr(bp);
3063 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3065 struct hwrm_func_cfg_input req = {0};
3066 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3069 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3071 req.fid = rte_cpu_to_le_16(0xffff);
3072 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3073 req.evb_mode = bp->pf.evb_mode;
3075 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3076 HWRM_CHECK_RESULT();
3082 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3083 uint8_t tunnel_type)
3085 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3086 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3089 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3090 req.tunnel_type = tunnel_type;
3091 req.tunnel_dst_port_val = port;
3092 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3093 HWRM_CHECK_RESULT();
3095 switch (tunnel_type) {
3096 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3097 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3098 bp->vxlan_port = port;
3100 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3101 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3102 bp->geneve_port = port;
3113 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3114 uint8_t tunnel_type)
3116 struct hwrm_tunnel_dst_port_free_input req = {0};
3117 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3120 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3122 req.tunnel_type = tunnel_type;
3123 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3124 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3126 HWRM_CHECK_RESULT();
3132 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3135 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3136 struct hwrm_func_cfg_input req = {0};
3139 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3141 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3142 req.flags = rte_cpu_to_le_32(flags);
3143 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3145 HWRM_CHECK_RESULT();
3151 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3153 uint32_t *flag = flagp;
3155 vnic->flags = *flag;
3158 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3160 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3163 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3166 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3167 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3169 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3171 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3172 req.req_buf_page_size = rte_cpu_to_le_16(
3173 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3174 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3175 req.req_buf_page_addr0 =
3176 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3177 if (req.req_buf_page_addr0 == 0) {
3179 "unable to map buffer address to physical memory\n");
3183 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3185 HWRM_CHECK_RESULT();
3191 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3194 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3195 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3197 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3199 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3201 HWRM_CHECK_RESULT();
3207 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3209 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3210 struct hwrm_func_cfg_input req = {0};
3213 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3215 req.fid = rte_cpu_to_le_16(0xffff);
3216 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3217 req.enables = rte_cpu_to_le_32(
3218 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3219 req.async_event_cr = rte_cpu_to_le_16(
3220 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3221 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3223 HWRM_CHECK_RESULT();
3229 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3231 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3232 struct hwrm_func_vf_cfg_input req = {0};
3235 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3237 req.enables = rte_cpu_to_le_32(
3238 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3239 req.async_event_cr = rte_cpu_to_le_16(
3240 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3241 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3243 HWRM_CHECK_RESULT();
3249 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3251 struct hwrm_func_cfg_input req = {0};
3252 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3253 uint16_t dflt_vlan, fid;
3254 uint32_t func_cfg_flags;
3257 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3260 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3261 fid = bp->pf.vf_info[vf].fid;
3262 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3264 fid = rte_cpu_to_le_16(0xffff);
3265 func_cfg_flags = bp->pf.func_cfg_flags;
3266 dflt_vlan = bp->vlan;
3269 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3270 req.fid = rte_cpu_to_le_16(fid);
3271 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3272 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3274 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3276 HWRM_CHECK_RESULT();
3282 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3283 uint16_t max_bw, uint16_t enables)
3285 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3286 struct hwrm_func_cfg_input req = {0};
3289 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3291 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3292 req.enables |= rte_cpu_to_le_32(enables);
3293 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3294 req.max_bw = rte_cpu_to_le_32(max_bw);
3295 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3297 HWRM_CHECK_RESULT();
3303 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3305 struct hwrm_func_cfg_input req = {0};
3306 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3309 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3311 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3312 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3313 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3314 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3316 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3318 HWRM_CHECK_RESULT();
3324 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3329 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3331 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3336 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3337 void *encaped, size_t ec_size)
3340 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3341 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3343 if (ec_size > sizeof(req.encap_request))
3346 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3348 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3349 memcpy(req.encap_request, encaped, ec_size);
3351 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3353 HWRM_CHECK_RESULT();
3359 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3360 struct rte_ether_addr *mac)
3362 struct hwrm_func_qcfg_input req = {0};
3363 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3366 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3368 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3369 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3371 HWRM_CHECK_RESULT();
3373 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3380 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3381 void *encaped, size_t ec_size)
3384 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3385 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3387 if (ec_size > sizeof(req.encap_request))
3390 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3392 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3393 memcpy(req.encap_request, encaped, ec_size);
3395 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3397 HWRM_CHECK_RESULT();
3403 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3404 struct rte_eth_stats *stats, uint8_t rx)
3407 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3408 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3410 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3412 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3414 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3416 HWRM_CHECK_RESULT();
3419 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3420 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3421 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3422 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3423 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3424 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3425 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3426 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3428 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3429 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3430 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3431 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3432 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3433 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3442 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3444 struct hwrm_port_qstats_input req = {0};
3445 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3446 struct bnxt_pf_info *pf = &bp->pf;
3449 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3451 req.port_id = rte_cpu_to_le_16(pf->port_id);
3452 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3453 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3454 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3456 HWRM_CHECK_RESULT();
3462 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3464 struct hwrm_port_clr_stats_input req = {0};
3465 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3466 struct bnxt_pf_info *pf = &bp->pf;
3469 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3470 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3471 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3474 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3476 req.port_id = rte_cpu_to_le_16(pf->port_id);
3477 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3479 HWRM_CHECK_RESULT();
3485 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3487 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3488 struct hwrm_port_led_qcaps_input req = {0};
3494 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3495 req.port_id = bp->pf.port_id;
3496 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3498 HWRM_CHECK_RESULT();
3500 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3503 bp->num_leds = resp->num_leds;
3504 memcpy(bp->leds, &resp->led0_id,
3505 sizeof(bp->leds[0]) * bp->num_leds);
3506 for (i = 0; i < bp->num_leds; i++) {
3507 struct bnxt_led_info *led = &bp->leds[i];
3509 uint16_t caps = led->led_state_caps;
3511 if (!led->led_group_id ||
3512 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3524 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3526 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3527 struct hwrm_port_led_cfg_input req = {0};
3528 struct bnxt_led_cfg *led_cfg;
3529 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3530 uint16_t duration = 0;
3533 if (!bp->num_leds || BNXT_VF(bp))
3536 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3539 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3540 duration = rte_cpu_to_le_16(500);
3542 req.port_id = bp->pf.port_id;
3543 req.num_leds = bp->num_leds;
3544 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3545 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3546 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3547 led_cfg->led_id = bp->leds[i].led_id;
3548 led_cfg->led_state = led_state;
3549 led_cfg->led_blink_on = duration;
3550 led_cfg->led_blink_off = duration;
3551 led_cfg->led_group_id = bp->leds[i].led_group_id;
3554 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3556 HWRM_CHECK_RESULT();
3562 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3566 struct hwrm_nvm_get_dir_info_input req = {0};
3567 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3569 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3571 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3573 HWRM_CHECK_RESULT();
3577 *entries = rte_le_to_cpu_32(resp->entries);
3578 *length = rte_le_to_cpu_32(resp->entry_length);
3583 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3586 uint32_t dir_entries;
3587 uint32_t entry_length;
3590 rte_iova_t dma_handle;
3591 struct hwrm_nvm_get_dir_entries_input req = {0};
3592 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3594 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3598 *data++ = dir_entries;
3599 *data++ = entry_length;
3601 memset(data, 0xff, len);
3603 buflen = dir_entries * entry_length;
3604 buf = rte_malloc("nvm_dir", buflen, 0);
3605 rte_mem_lock_page(buf);
3608 dma_handle = rte_mem_virt2iova(buf);
3609 if (dma_handle == 0) {
3611 "unable to map response address to physical memory\n");
3614 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3615 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3616 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3619 memcpy(data, buf, len > buflen ? buflen : len);
3622 HWRM_CHECK_RESULT();
3628 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3629 uint32_t offset, uint32_t length,
3634 rte_iova_t dma_handle;
3635 struct hwrm_nvm_read_input req = {0};
3636 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3638 buf = rte_malloc("nvm_item", length, 0);
3639 rte_mem_lock_page(buf);
3643 dma_handle = rte_mem_virt2iova(buf);
3644 if (dma_handle == 0) {
3646 "unable to map response address to physical memory\n");
3649 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3650 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3651 req.dir_idx = rte_cpu_to_le_16(index);
3652 req.offset = rte_cpu_to_le_32(offset);
3653 req.len = rte_cpu_to_le_32(length);
3654 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3656 memcpy(data, buf, length);
3659 HWRM_CHECK_RESULT();
3665 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3668 struct hwrm_nvm_erase_dir_entry_input req = {0};
3669 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3671 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3672 req.dir_idx = rte_cpu_to_le_16(index);
3673 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3674 HWRM_CHECK_RESULT();
3681 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3682 uint16_t dir_ordinal, uint16_t dir_ext,
3683 uint16_t dir_attr, const uint8_t *data,
3687 struct hwrm_nvm_write_input req = {0};
3688 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3689 rte_iova_t dma_handle;
3692 buf = rte_malloc("nvm_write", data_len, 0);
3693 rte_mem_lock_page(buf);
3697 dma_handle = rte_mem_virt2iova(buf);
3698 if (dma_handle == 0) {
3700 "unable to map response address to physical memory\n");
3703 memcpy(buf, data, data_len);
3705 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3707 req.dir_type = rte_cpu_to_le_16(dir_type);
3708 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3709 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3710 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3711 req.dir_data_length = rte_cpu_to_le_32(data_len);
3712 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3714 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3717 HWRM_CHECK_RESULT();
3724 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3726 uint32_t *count = cbdata;
3728 *count = *count + 1;
3731 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3732 struct bnxt_vnic_info *vnic __rte_unused)
3737 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3741 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3742 &count, bnxt_vnic_count_hwrm_stub);
3747 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3750 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3751 struct hwrm_func_vf_vnic_ids_query_output *resp =
3752 bp->hwrm_cmd_resp_addr;
3755 /* First query all VNIC ids */
3756 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3758 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3759 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3760 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3762 if (req.vnic_id_tbl_addr == 0) {
3765 "unable to map VNIC ID table address to physical memory\n");
3768 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3771 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3773 } else if (resp->error_code) {
3774 rc = rte_le_to_cpu_16(resp->error_code);
3776 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3779 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3787 * This function queries the VNIC IDs for a specified VF. It then calls
3788 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3789 * Then it calls the hwrm_cb function to program this new vnic configuration.
3791 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3792 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3793 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3795 struct bnxt_vnic_info vnic;
3797 int i, num_vnic_ids;
3802 /* First query all VNIC ids */
3803 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3804 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3805 RTE_CACHE_LINE_SIZE);
3806 if (vnic_ids == NULL) {
3810 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3811 rte_mem_lock_page(((char *)vnic_ids) + sz);
3813 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3815 if (num_vnic_ids < 0)
3816 return num_vnic_ids;
3818 /* Retrieve VNIC, update bd_stall then update */
3820 for (i = 0; i < num_vnic_ids; i++) {
3821 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3822 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3823 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3826 if (vnic.mru <= 4) /* Indicates unallocated */
3829 vnic_cb(&vnic, cbdata);
3831 rc = hwrm_cb(bp, &vnic);
3841 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3844 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3845 struct hwrm_func_cfg_input req = {0};
3848 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3850 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3851 req.enables |= rte_cpu_to_le_32(
3852 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3853 req.vlan_antispoof_mode = on ?
3854 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3855 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3856 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3858 HWRM_CHECK_RESULT();
3864 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3866 struct bnxt_vnic_info vnic;
3869 int num_vnic_ids, i;
3873 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3874 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3875 RTE_CACHE_LINE_SIZE);
3876 if (vnic_ids == NULL) {
3881 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3882 rte_mem_lock_page(((char *)vnic_ids) + sz);
3884 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3890 * Loop through to find the default VNIC ID.
3891 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3892 * by sending the hwrm_func_qcfg command to the firmware.
3894 for (i = 0; i < num_vnic_ids; i++) {
3895 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3896 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3897 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3898 bp->pf.first_vf_id + vf);
3901 if (vnic.func_default) {
3903 return vnic.fw_vnic_id;
3906 /* Could not find a default VNIC. */
3907 PMD_DRV_LOG(ERR, "No default VNIC\n");
3913 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3915 struct bnxt_filter_info *filter)
3918 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3919 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3920 uint32_t enables = 0;
3922 if (filter->fw_em_filter_id != UINT64_MAX)
3923 bnxt_hwrm_clear_em_filter(bp, filter);
3925 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3927 req.flags = rte_cpu_to_le_32(filter->flags);
3929 enables = filter->enables |
3930 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3931 req.dst_id = rte_cpu_to_le_16(dst_id);
3933 if (filter->ip_addr_type) {
3934 req.ip_addr_type = filter->ip_addr_type;
3935 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3938 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3939 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3941 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3942 memcpy(req.src_macaddr, filter->src_macaddr,
3943 RTE_ETHER_ADDR_LEN);
3945 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3946 memcpy(req.dst_macaddr, filter->dst_macaddr,
3947 RTE_ETHER_ADDR_LEN);
3949 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3950 req.ovlan_vid = filter->l2_ovlan;
3952 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3953 req.ivlan_vid = filter->l2_ivlan;
3955 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3956 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3958 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3959 req.ip_protocol = filter->ip_protocol;
3961 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3962 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3964 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3965 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3967 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3968 req.src_port = rte_cpu_to_be_16(filter->src_port);
3970 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3971 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3973 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3974 req.mirror_vnic_id = filter->mirror_vnic_id;
3976 req.enables = rte_cpu_to_le_32(enables);
3978 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3980 HWRM_CHECK_RESULT();
3982 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3988 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3991 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3992 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3994 if (filter->fw_em_filter_id == UINT64_MAX)
3997 PMD_DRV_LOG(ERR, "Clear EM filter\n");
3998 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4000 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4002 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4004 HWRM_CHECK_RESULT();
4007 filter->fw_em_filter_id = UINT64_MAX;
4008 filter->fw_l2_filter_id = UINT64_MAX;
4013 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4015 struct bnxt_filter_info *filter)
4018 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4019 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4020 bp->hwrm_cmd_resp_addr;
4021 uint32_t enables = 0;
4023 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4024 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4026 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4028 req.flags = rte_cpu_to_le_32(filter->flags);
4030 enables = filter->enables |
4031 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4032 req.dst_id = rte_cpu_to_le_16(dst_id);
4035 if (filter->ip_addr_type) {
4036 req.ip_addr_type = filter->ip_addr_type;
4038 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4041 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4042 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4044 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4045 memcpy(req.src_macaddr, filter->src_macaddr,
4046 RTE_ETHER_ADDR_LEN);
4048 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4049 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4050 //RTE_ETHER_ADDR_LEN);
4052 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4053 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4055 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4056 req.ip_protocol = filter->ip_protocol;
4058 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4059 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4061 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4062 req.src_ipaddr_mask[0] =
4063 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4065 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4066 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4068 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4069 req.dst_ipaddr_mask[0] =
4070 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4072 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4073 req.src_port = rte_cpu_to_le_16(filter->src_port);
4075 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4076 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4078 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4079 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4081 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4082 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4084 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4085 req.mirror_vnic_id = filter->mirror_vnic_id;
4087 req.enables = rte_cpu_to_le_32(enables);
4089 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4091 HWRM_CHECK_RESULT();
4093 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4099 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4100 struct bnxt_filter_info *filter)
4103 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4104 struct hwrm_cfa_ntuple_filter_free_output *resp =
4105 bp->hwrm_cmd_resp_addr;
4107 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4110 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4112 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4114 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4116 HWRM_CHECK_RESULT();
4119 filter->fw_ntuple_filter_id = UINT64_MAX;
4125 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4127 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4128 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4129 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4130 int nr_ctxs = bp->max_ring_grps;
4131 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4132 uint16_t *ring_tbl = vnic->rss_table;
4133 int max_rings = bp->rx_nr_rings;
4137 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4139 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4140 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4141 req.hash_mode_flags = vnic->hash_mode;
4143 req.ring_grp_tbl_addr =
4144 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
4145 req.hash_key_tbl_addr =
4146 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4148 for (i = 0, k = 0; i < nr_ctxs; i++) {
4149 struct bnxt_rx_ring_info *rxr;
4150 struct bnxt_cp_ring_info *cpr;
4152 req.ring_table_pair_index = i;
4153 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4155 for (j = 0; j < 64; j++) {
4158 /* Find next active ring. */
4159 for (cnt = 0; cnt < max_rings; cnt++) {
4160 if (rx_queue_state[k] !=
4161 RTE_ETH_QUEUE_STATE_STOPPED)
4163 if (++k == max_rings)
4167 /* Return if no rings are active. */
4168 if (cnt == max_rings)
4171 /* Add rx/cp ring pair to RSS table. */
4172 rxr = rxqs[k]->rx_ring;
4173 cpr = rxqs[k]->cp_ring;
4175 ring_id = rxr->rx_ring_struct->fw_ring_id;
4176 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4177 ring_id = cpr->cp_ring_struct->fw_ring_id;
4178 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4180 if (++k == max_rings)
4183 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4186 HWRM_CHECK_RESULT();
4196 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4198 unsigned int rss_idx, fw_idx, i;
4200 if (!(vnic->rss_table && vnic->hash_type))
4203 if (BNXT_CHIP_THOR(bp))
4204 return bnxt_vnic_rss_configure_thor(bp, vnic);
4207 * Fill the RSS hash & redirection table with
4208 * ring group ids for all VNICs
4210 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4211 rss_idx++, fw_idx++) {
4212 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4213 fw_idx %= bp->rx_cp_nr_rings;
4214 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4218 if (i == bp->rx_cp_nr_rings)
4220 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4222 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4225 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4226 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4230 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4232 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4233 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4235 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4236 req->num_cmpl_dma_aggr_during_int =
4237 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4239 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4241 /* min timer set to 1/2 of interrupt timer */
4242 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4244 /* buf timer set to 1/4 of interrupt timer */
4245 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4247 req->cmpl_aggr_dma_tmr_during_int =
4248 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4250 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4251 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4252 req->flags = rte_cpu_to_le_16(flags);
4255 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4256 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4258 struct hwrm_ring_aggint_qcaps_input req = {0};
4259 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4264 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4265 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4269 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4270 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4272 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4273 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4274 agg_req->flags = rte_cpu_to_le_16(flags);
4276 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4277 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4278 agg_req->enables = rte_cpu_to_le_32(enables);
4281 HWRM_CHECK_RESULT();
4286 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4287 struct bnxt_coal *coal, uint16_t ring_id)
4289 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4290 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4291 bp->hwrm_cmd_resp_addr;
4294 /* Set ring coalesce parameters only for 100G NICs */
4295 if (BNXT_CHIP_THOR(bp)) {
4296 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4298 } else if (bnxt_stratus_device(bp)) {
4299 bnxt_hwrm_set_coal_params(coal, &req);
4304 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4305 req.ring_id = rte_cpu_to_le_16(ring_id);
4306 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4307 HWRM_CHECK_RESULT();
4312 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4313 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4315 struct hwrm_func_backing_store_qcaps_input req = {0};
4316 struct hwrm_func_backing_store_qcaps_output *resp =
4317 bp->hwrm_cmd_resp_addr;
4320 if (!BNXT_CHIP_THOR(bp) ||
4321 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4326 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4327 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4328 HWRM_CHECK_RESULT_SILENT();
4331 struct bnxt_ctx_pg_info *ctx_pg;
4332 struct bnxt_ctx_mem_info *ctx;
4333 int total_alloc_len;
4336 total_alloc_len = sizeof(*ctx);
4337 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4338 RTE_CACHE_LINE_SIZE);
4343 memset(ctx, 0, total_alloc_len);
4345 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4346 sizeof(*ctx_pg) * BNXT_MAX_Q,
4347 RTE_CACHE_LINE_SIZE);
4352 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4353 ctx->tqm_mem[i] = ctx_pg;
4356 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4357 ctx->qp_min_qp1_entries =
4358 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4359 ctx->qp_max_l2_entries =
4360 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4361 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4362 ctx->srq_max_l2_entries =
4363 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4364 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4365 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4366 ctx->cq_max_l2_entries =
4367 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4368 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4369 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4370 ctx->vnic_max_vnic_entries =
4371 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4372 ctx->vnic_max_ring_table_entries =
4373 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4374 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4375 ctx->stat_max_entries =
4376 rte_le_to_cpu_32(resp->stat_max_entries);
4377 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4378 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4379 ctx->tqm_min_entries_per_ring =
4380 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4381 ctx->tqm_max_entries_per_ring =
4382 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4383 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4384 if (!ctx->tqm_entries_multiple)
4385 ctx->tqm_entries_multiple = 1;
4386 ctx->mrav_max_entries =
4387 rte_le_to_cpu_32(resp->mrav_max_entries);
4388 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4389 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4390 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4399 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4401 struct hwrm_func_backing_store_cfg_input req = {0};
4402 struct hwrm_func_backing_store_cfg_output *resp =
4403 bp->hwrm_cmd_resp_addr;
4404 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4405 struct bnxt_ctx_pg_info *ctx_pg;
4406 uint32_t *num_entries;
4415 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4416 req.enables = rte_cpu_to_le_32(enables);
4418 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4419 ctx_pg = &ctx->qp_mem;
4420 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4421 req.qp_num_qp1_entries =
4422 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4423 req.qp_num_l2_entries =
4424 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4425 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4426 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4427 &req.qpc_pg_size_qpc_lvl,
4431 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4432 ctx_pg = &ctx->srq_mem;
4433 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4434 req.srq_num_l2_entries =
4435 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4436 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4437 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4438 &req.srq_pg_size_srq_lvl,
4442 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4443 ctx_pg = &ctx->cq_mem;
4444 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4445 req.cq_num_l2_entries =
4446 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4447 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4448 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4449 &req.cq_pg_size_cq_lvl,
4453 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4454 ctx_pg = &ctx->vnic_mem;
4455 req.vnic_num_vnic_entries =
4456 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4457 req.vnic_num_ring_table_entries =
4458 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4459 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4460 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4461 &req.vnic_pg_size_vnic_lvl,
4462 &req.vnic_page_dir);
4465 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4466 ctx_pg = &ctx->stat_mem;
4467 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4468 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4469 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4470 &req.stat_pg_size_stat_lvl,
4471 &req.stat_page_dir);
4474 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4475 num_entries = &req.tqm_sp_num_entries;
4476 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4477 pg_dir = &req.tqm_sp_page_dir;
4478 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4479 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4480 if (!(enables & ena))
4483 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4485 ctx_pg = ctx->tqm_mem[i];
4486 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4487 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4490 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4491 HWRM_CHECK_RESULT();
4498 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4500 struct hwrm_port_qstats_ext_input req = {0};
4501 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4502 struct bnxt_pf_info *pf = &bp->pf;
4505 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4506 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4509 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4511 req.port_id = rte_cpu_to_le_16(pf->port_id);
4512 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4513 req.tx_stat_host_addr =
4514 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4516 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4518 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4519 req.rx_stat_host_addr =
4520 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4522 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4524 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4527 bp->fw_rx_port_stats_ext_size = 0;
4528 bp->fw_tx_port_stats_ext_size = 0;
4530 bp->fw_rx_port_stats_ext_size =
4531 rte_le_to_cpu_16(resp->rx_stat_size);
4532 bp->fw_tx_port_stats_ext_size =
4533 rte_le_to_cpu_16(resp->tx_stat_size);
4536 HWRM_CHECK_RESULT();
4543 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4545 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4546 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4547 bp->hwrm_cmd_resp_addr;
4550 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_KONG(bp));
4551 req.tunnel_type = type;
4552 req.dest_fid = bp->fw_fid;
4553 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4554 HWRM_CHECK_RESULT();
4562 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4564 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4565 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4566 bp->hwrm_cmd_resp_addr;
4569 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_KONG(bp));
4570 req.tunnel_type = type;
4571 req.dest_fid = bp->fw_fid;
4572 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4573 HWRM_CHECK_RESULT();
4580 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4582 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4583 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4584 bp->hwrm_cmd_resp_addr;
4587 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_KONG(bp));
4588 req.src_fid = bp->fw_fid;
4589 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4590 HWRM_CHECK_RESULT();
4593 *type = resp->tunnel_mask;
4600 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4603 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4604 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4605 bp->hwrm_cmd_resp_addr;
4608 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_KONG(bp));
4609 req.src_fid = bp->fw_fid;
4610 req.tunnel_type = tun_type;
4611 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4612 HWRM_CHECK_RESULT();
4615 *dst_fid = resp->dest_fid;
4617 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4624 int bnxt_hwrm_set_mac(struct bnxt *bp)
4626 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4627 struct hwrm_func_vf_cfg_input req = {0};
4633 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4636 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4637 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4639 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4641 HWRM_CHECK_RESULT();
4643 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);