1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2021 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
30 #define HWRM_VERSION_1_10_2_13 0x10a020d
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(int) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
67 if (rmem->nr_pages == 0)
70 if (rmem->nr_pages > 1) {
72 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
74 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
78 static struct bnxt_cp_ring_info*
79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
81 struct bnxt_cp_ring_info *cp_ring = NULL;
85 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
86 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
88 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
89 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
91 if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
92 rte_cpu_to_le_16(rid)) {
97 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
98 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
99 struct bnxt_tx_queue *txq = bp->tx_queues[i];
101 if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
102 rte_cpu_to_le_16(rid)) {
113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
114 * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
115 * before timeout, we force the done bit for the cleanup to proceed.
116 * Also if cpr is null, do nothing.. The HWRM command is not for a
117 * Tx/Rx/AGG ring cleanup.
120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
121 bool tx, bool rx, bool timeout)
127 done = bnxt_flush_tx_cmp(cpr);
130 done = bnxt_flush_rx_cmp(cpr);
133 PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
136 /* We are about to timeout and still haven't seen the
137 * HWRM done for the Ring free. Force the cleanup.
139 if (!done && timeout) {
141 PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
145 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
146 * Otherwise the cpr would have been valid. So do nothing.
155 * HWRM Functions (sent to HWRM)
156 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
157 * HWRM command times out, or a negative error code if the HWRM
158 * command was failed by the FW.
161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
162 uint32_t msg_len, bool use_kong_mb)
165 struct input *req = msg;
166 struct output *resp = bp->hwrm_cmd_resp_addr;
167 uint32_t *data = msg;
170 uint16_t max_req_len = bp->max_req_len;
171 struct hwrm_short_input short_input = { 0 };
172 uint16_t bar_offset = use_kong_mb ?
173 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
174 uint16_t mb_trigger_offset = use_kong_mb ?
175 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
176 struct bnxt_cp_ring_info *cpr = NULL;
181 /* Do not send HWRM commands to firmware in error state */
182 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
185 timeout = bp->hwrm_cmd_timeout;
187 /* Update the message length for backing store config for new FW. */
188 if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
189 rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
190 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
192 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
193 msg_len > bp->max_req_len) {
194 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
196 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
197 memcpy(short_cmd_req, req, msg_len);
199 short_input.req_type = rte_cpu_to_le_16(req->req_type);
200 short_input.signature = rte_cpu_to_le_16(
201 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
202 short_input.size = rte_cpu_to_le_16(msg_len);
203 short_input.req_addr =
204 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
206 data = (uint32_t *)&short_input;
207 msg_len = sizeof(short_input);
209 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
212 /* Write request msg to hwrm channel */
213 for (i = 0; i < msg_len; i += 4) {
214 bar = (uint8_t *)bp->bar0 + bar_offset + i;
215 rte_write32(*data, bar);
219 /* Zero the rest of the request space */
220 for (; i < max_req_len; i += 4) {
221 bar = (uint8_t *)bp->bar0 + bar_offset + i;
225 /* Ring channel doorbell */
226 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
229 * Make sure the channel doorbell ring command complete before
230 * reading the response to avoid getting stale or invalid
235 /* Check ring flush is done.
236 * This is valid only for Tx and Rx rings (including AGG rings).
237 * The Tx and Rx rings should be freed once the HW confirms all
238 * the internal buffers and BDs associated with the rings are
239 * consumed and the corresponding DMA is handled.
241 if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
242 /* Check if the TxCQ matches. If that fails check if RxCQ
243 * matches. And if neither match, is_rx = false, is_tx = false.
245 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
246 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
248 /* Not a TxCQ. Check if the RxCQ matches. */
250 bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
251 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
259 /* Poll for the valid bit */
260 for (i = 0; i < timeout; i++) {
263 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
265 /* Sanity check on the resp->resp_len */
267 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
268 /* Last byte of resp contains the valid key */
269 valid = (uint8_t *)resp + resp->resp_len - 1;
270 if (*valid == HWRM_RESP_VALID_KEY && done)
277 /* Suppress VER_GET timeout messages during reset recovery */
278 if (bp->flags & BNXT_FLAG_FW_RESET &&
279 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
283 "Error(timeout) sending msg 0x%04x, seq_id %d\n",
284 req->req_type, req->seq_id);
291 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
292 * spinlock, and does initial processing.
294 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
295 * releases the spinlock only if it returns. If the regular int return codes
296 * are not used by the function, HWRM_CHECK_RESULT() should not be used
297 * directly, rather it should be copied and modified to suit the function.
299 * HWRM_UNLOCK() must be called after all response processing is completed.
301 #define HWRM_PREP(req, type, kong) do { \
302 rte_spinlock_lock(&bp->hwrm_lock); \
303 if (bp->hwrm_cmd_resp_addr == NULL) { \
304 rte_spinlock_unlock(&bp->hwrm_lock); \
307 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
308 (req)->req_type = rte_cpu_to_le_16(type); \
309 (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
310 (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
311 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
312 (req)->target_id = rte_cpu_to_le_16(0xffff); \
313 (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
316 #define HWRM_CHECK_RESULT_SILENT() do {\
318 rte_spinlock_unlock(&bp->hwrm_lock); \
321 if (resp->error_code) { \
322 rc = rte_le_to_cpu_16(resp->error_code); \
323 rte_spinlock_unlock(&bp->hwrm_lock); \
328 #define HWRM_CHECK_RESULT() do {\
330 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
331 rte_spinlock_unlock(&bp->hwrm_lock); \
332 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
334 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
336 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
338 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
340 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
346 if (resp->error_code) { \
347 rc = rte_le_to_cpu_16(resp->error_code); \
348 if (resp->resp_len >= 16) { \
349 struct hwrm_err_output *tmp_hwrm_err_op = \
352 "error %d:%d:%08x:%04x\n", \
353 rc, tmp_hwrm_err_op->cmd_err, \
355 tmp_hwrm_err_op->opaque_0), \
357 tmp_hwrm_err_op->opaque_1)); \
359 PMD_DRV_LOG(ERR, "error %d\n", rc); \
361 rte_spinlock_unlock(&bp->hwrm_lock); \
362 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
364 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
366 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
368 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
370 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
378 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
389 bool mailbox = BNXT_USE_CHIMP_MB;
390 struct input *req = msg;
391 struct output *resp = bp->hwrm_cmd_resp_addr;
394 mailbox = BNXT_USE_KONG(bp);
396 HWRM_PREP(req, msg_type, mailbox);
398 rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
403 memcpy(resp_msg, resp, resp_len);
410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
414 uint32_t *tf_response_code,
418 uint32_t response_len)
421 struct hwrm_cfa_tflib_input req = { .req_type = 0 };
422 struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
423 bool mailbox = BNXT_USE_CHIMP_MB;
425 if (msg_len > sizeof(req.tf_req))
429 mailbox = BNXT_USE_KONG(bp);
431 HWRM_PREP(&req, HWRM_TF, mailbox);
432 /* Build request using the user supplied request payload.
433 * TLV request size is checked at build time against HWRM
434 * request max size, thus no checking required.
436 req.tf_type = tf_type;
437 req.tf_subtype = tf_subtype;
438 memcpy(req.tf_req, msg, msg_len);
440 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
443 /* Copy the resp to user provided response buffer */
444 if (response != NULL)
445 /* Post process response data. We need to copy only
446 * the 'payload' as the HWRM data structure really is
447 * HWRM header + msg header + payload and the TFLIB
448 * only provided a payload place holder.
450 if (response_len != 0) {
456 /* Extract the internal tflib response code */
457 *tf_response_code = resp->tf_resp_code;
463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
466 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
467 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
469 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
470 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
473 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
482 struct bnxt_vnic_info *vnic,
484 struct bnxt_vlan_table_entry *vlan_table)
487 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
488 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
491 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
494 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
495 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
497 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
498 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
499 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
500 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
502 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
503 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
505 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
506 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
507 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
508 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
509 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
510 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
513 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
514 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
515 req.vlan_tag_tbl_addr =
516 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
517 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
519 req.mask = rte_cpu_to_le_32(mask);
521 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
531 struct bnxt_vlan_antispoof_table_entry *vlan_table)
534 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
535 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
536 bp->hwrm_cmd_resp_addr;
539 * Older HWRM versions did not support this command, and the set_rx_mask
540 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
541 * removed from set_rx_mask call, and this command was added.
543 * This command is also present from 1.7.8.11 and higher,
546 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
547 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
548 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
553 HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
554 req.fid = rte_cpu_to_le_16(fid);
556 req.vlan_tag_mask_tbl_addr =
557 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
558 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
560 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
569 struct bnxt_filter_info *filter)
572 struct bnxt_filter_info *l2_filter = filter;
573 struct bnxt_vnic_info *vnic = NULL;
574 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
575 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
577 if (filter->fw_l2_filter_id == UINT64_MAX)
580 if (filter->matching_l2_fltr_ptr)
581 l2_filter = filter->matching_l2_fltr_ptr;
583 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
584 filter, l2_filter, l2_filter->l2_ref_cnt);
586 if (l2_filter->l2_ref_cnt == 0)
589 if (l2_filter->l2_ref_cnt > 0)
590 l2_filter->l2_ref_cnt--;
592 if (l2_filter->l2_ref_cnt > 0)
595 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
597 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
599 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
604 filter->fw_l2_filter_id = UINT64_MAX;
605 if (l2_filter->l2_ref_cnt == 0) {
606 vnic = l2_filter->vnic;
608 STAILQ_REMOVE(&vnic->filter, l2_filter,
609 bnxt_filter_info, next);
610 bnxt_free_filter(bp, l2_filter);
617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
619 struct bnxt_filter_info *filter)
622 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
623 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
624 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
625 const struct rte_eth_vmdq_rx_conf *conf =
626 &dev_conf->rx_adv_conf.vmdq_rx_conf;
627 uint32_t enables = 0;
628 uint16_t j = dst_id - 1;
630 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
631 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
632 conf->pool_map[j].pools & (1UL << j)) {
634 "Add vlan %u to vmdq pool %u\n",
635 conf->pool_map[j].vlan_id, j);
637 filter->l2_ivlan = conf->pool_map[j].vlan_id;
639 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
640 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
643 if (filter->fw_l2_filter_id != UINT64_MAX)
644 bnxt_hwrm_clear_l2_filter(bp, filter);
646 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
648 /* PMD does not support XDP and RoCE */
649 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
650 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
651 req.flags = rte_cpu_to_le_32(filter->flags);
653 enables = filter->enables |
654 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
655 req.dst_id = rte_cpu_to_le_16(dst_id);
658 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
659 memcpy(req.l2_addr, filter->l2_addr,
662 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
663 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
666 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
667 req.l2_ovlan = filter->l2_ovlan;
669 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
670 req.l2_ivlan = filter->l2_ivlan;
672 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
673 req.l2_ovlan_mask = filter->l2_ovlan_mask;
675 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
676 req.l2_ivlan_mask = filter->l2_ivlan_mask;
677 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
678 req.src_id = rte_cpu_to_le_32(filter->src_id);
679 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
680 req.src_type = filter->src_type;
681 if (filter->pri_hint) {
682 req.pri_hint = filter->pri_hint;
683 req.l2_filter_id_hint =
684 rte_cpu_to_le_64(filter->l2_filter_id_hint);
687 req.enables = rte_cpu_to_le_32(enables);
689 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
693 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
694 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
697 filter->l2_ref_cnt++;
702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
704 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
705 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
712 HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
715 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
718 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
719 if (ptp->tx_tstamp_en)
720 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
723 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
724 req.flags = rte_cpu_to_le_32(flags);
725 req.enables = rte_cpu_to_le_32
726 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
727 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
729 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
738 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
739 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
740 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
745 HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
747 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
749 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
753 if (BNXT_CHIP_P5(bp)) {
754 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS))
757 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
761 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
762 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
764 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
768 if (!BNXT_CHIP_P5(bp)) {
769 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
770 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
771 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
772 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
773 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
774 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
775 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
776 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
777 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
778 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
779 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
780 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
781 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
782 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
783 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
784 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
785 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
786 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
795 void bnxt_free_vf_info(struct bnxt *bp)
802 if (bp->pf->vf_info == NULL)
805 for (i = 0; i < bp->pf->max_vfs; i++) {
806 rte_free(bp->pf->vf_info[i].vlan_table);
807 bp->pf->vf_info[i].vlan_table = NULL;
808 rte_free(bp->pf->vf_info[i].vlan_as_table);
809 bp->pf->vf_info[i].vlan_as_table = NULL;
811 rte_free(bp->pf->vf_info);
812 bp->pf->vf_info = NULL;
815 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
817 struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
821 bnxt_free_vf_info(bp);
823 vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
824 if (vf_info == NULL) {
825 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
829 bp->pf->max_vfs = max_vfs;
830 for (i = 0; i < max_vfs; i++) {
831 vf_info[i].fid = bp->pf->first_vf_id + i;
832 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
833 getpagesize(), getpagesize());
834 if (vf_info[i].vlan_table == NULL) {
835 PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
838 rte_mem_lock_page(vf_info[i].vlan_table);
840 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
841 getpagesize(), getpagesize());
842 if (vf_info[i].vlan_as_table == NULL) {
843 PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
846 rte_mem_lock_page(vf_info[i].vlan_as_table);
848 STAILQ_INIT(&vf_info[i].filter);
851 bp->pf->vf_info = vf_info;
855 bnxt_free_vf_info(bp);
859 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
862 struct hwrm_func_qcaps_input req = {.req_type = 0 };
863 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
864 uint16_t new_max_vfs;
867 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
869 req.fid = rte_cpu_to_le_16(0xffff);
871 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
875 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
876 flags = rte_le_to_cpu_32(resp->flags);
878 bp->pf->port_id = resp->port_id;
879 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
880 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
881 new_max_vfs = bp->pdev->max_vfs;
882 if (new_max_vfs != bp->pf->max_vfs) {
883 rc = bnxt_alloc_vf_info(bp, new_max_vfs);
889 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
890 if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
891 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
892 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
894 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
896 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
897 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
898 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
899 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
900 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
901 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
902 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
903 if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
904 bp->max_l2_ctx += bp->max_rx_em_flows;
905 /* TODO: For now, do not support VMDq/RFS on VFs. */
910 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
914 PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
915 bp->max_l2_ctx, bp->max_vnics);
916 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
918 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
919 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
920 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
921 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
923 bnxt_hwrm_ptp_qcfg(bp);
927 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
928 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
930 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
931 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
932 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
935 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
936 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
938 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
939 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
941 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
942 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
950 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
954 rc = __bnxt_hwrm_func_qcaps(bp);
958 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
959 rc = bnxt_alloc_ctx_mem(bp);
964 * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
965 * But the error can be ignored. Return success.
967 rc = bnxt_hwrm_func_resc_qcaps(bp);
969 bp->flags |= BNXT_FLAG_NEW_RM;
975 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
976 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
980 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
981 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
983 HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
985 req.target_id = rte_cpu_to_le_16(0xffff);
987 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
991 flags = rte_le_to_cpu_32(resp->flags);
993 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
994 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
995 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
998 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
999 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
1001 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
1002 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
1004 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
1011 int bnxt_hwrm_func_reset(struct bnxt *bp)
1014 struct hwrm_func_reset_input req = {.req_type = 0 };
1015 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1017 HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1019 req.enables = rte_cpu_to_le_32(0);
1021 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1023 HWRM_CHECK_RESULT();
1029 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1033 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1034 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1036 if (bp->flags & BNXT_FLAG_REGISTERED)
1039 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1040 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1041 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1042 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1044 /* PFs and trusted VFs should indicate the support of the
1045 * Master capability on non Stingray platform
1047 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1048 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1050 HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1051 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1052 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1053 req.ver_maj = RTE_VER_YEAR;
1054 req.ver_min = RTE_VER_MONTH;
1055 req.ver_upd = RTE_VER_MINOR;
1058 req.enables |= rte_cpu_to_le_32(
1059 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1060 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1061 RTE_MIN(sizeof(req.vf_req_fwd),
1062 sizeof(bp->pf->vf_req_fwd)));
1065 req.flags = rte_cpu_to_le_32(flags);
1067 req.async_event_fwd[0] |=
1068 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1069 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1070 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1071 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1072 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1073 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1074 req.async_event_fwd[0] |=
1075 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1076 req.async_event_fwd[1] |=
1077 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1078 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1080 req.async_event_fwd[1] |=
1081 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1083 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1084 req.async_event_fwd[1] |=
1085 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1087 req.async_event_fwd[2] |=
1088 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST);
1090 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1092 HWRM_CHECK_RESULT();
1094 flags = rte_le_to_cpu_32(resp->flags);
1095 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1096 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1100 bp->flags |= BNXT_FLAG_REGISTERED;
1105 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1107 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1110 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1113 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1118 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1119 struct hwrm_func_vf_cfg_input req = {0};
1121 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1123 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
1124 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
1125 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
1126 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1127 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1129 if (BNXT_HAS_RING_GRPS(bp)) {
1130 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1131 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1134 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1135 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1136 AGG_RING_MULTIPLIER);
1137 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1138 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1140 BNXT_NUM_ASYNC_CPR(bp));
1141 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1142 if (bp->vf_resv_strategy ==
1143 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1144 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1145 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1146 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1147 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1148 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1149 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1150 } else if (bp->vf_resv_strategy ==
1151 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1152 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1153 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1157 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1158 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1159 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1160 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1161 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1162 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1164 if (test && BNXT_HAS_RING_GRPS(bp))
1165 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1167 req.flags = rte_cpu_to_le_32(flags);
1168 req.enables |= rte_cpu_to_le_32(enables);
1170 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1173 HWRM_CHECK_RESULT_SILENT();
1175 HWRM_CHECK_RESULT();
1181 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1184 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1185 struct hwrm_func_resource_qcaps_input req = {0};
1187 HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1188 req.fid = rte_cpu_to_le_16(0xffff);
1190 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1192 HWRM_CHECK_RESULT_SILENT();
1194 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1195 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1196 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1197 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1198 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1199 /* func_resource_qcaps does not return max_rx_em_flows.
1200 * So use the value provided by func_qcaps.
1202 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1203 if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1204 bp->max_l2_ctx += bp->max_rx_em_flows;
1205 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1206 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1207 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1208 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1209 if (bp->vf_resv_strategy >
1210 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1211 bp->vf_resv_strategy =
1212 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1218 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1221 struct hwrm_ver_get_input req = {.req_type = 0 };
1222 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1223 uint32_t fw_version;
1224 uint16_t max_resp_len;
1225 char type[RTE_MEMZONE_NAMESIZE];
1226 uint32_t dev_caps_cfg;
1228 bp->max_req_len = HWRM_MAX_REQ_LEN;
1229 bp->hwrm_cmd_timeout = timeout;
1230 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1232 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1233 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1234 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1236 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1238 if (bp->flags & BNXT_FLAG_FW_RESET)
1239 HWRM_CHECK_RESULT_SILENT();
1241 HWRM_CHECK_RESULT();
1243 if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
1248 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1249 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1250 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1251 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1252 resp->hwrm_fw_rsvd_8b);
1253 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1254 (resp->hwrm_fw_min_8b << 16) |
1255 (resp->hwrm_fw_bld_8b << 8) |
1256 resp->hwrm_fw_rsvd_8b;
1257 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1258 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1260 fw_version = resp->hwrm_intf_maj_8b << 16;
1261 fw_version |= resp->hwrm_intf_min_8b << 8;
1262 fw_version |= resp->hwrm_intf_upd_8b;
1263 bp->hwrm_spec_code = fw_version;
1265 /* def_req_timeout value is in milliseconds */
1266 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1267 /* convert timeout to usec */
1268 bp->hwrm_cmd_timeout *= 1000;
1269 if (!bp->hwrm_cmd_timeout)
1270 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1272 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1273 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1278 if (bp->max_req_len > resp->max_req_win_len) {
1279 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1284 bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1286 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1287 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1288 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1289 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1291 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1292 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1294 RTE_VERIFY(max_resp_len <= bp->max_resp_len);
1295 bp->max_resp_len = max_resp_len;
1298 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1300 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1301 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1302 bp->flags |= BNXT_FLAG_SHORT_CMD;
1305 if (((dev_caps_cfg &
1306 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1308 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1309 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1310 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1311 bp->pdev->addr.domain, bp->pdev->addr.bus,
1312 bp->pdev->addr.devid, bp->pdev->addr.function);
1314 rte_free(bp->hwrm_short_cmd_req_addr);
1316 bp->hwrm_short_cmd_req_addr =
1317 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1318 if (bp->hwrm_short_cmd_req_addr == NULL) {
1322 bp->hwrm_short_cmd_req_dma_addr =
1323 rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1324 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1325 rte_free(bp->hwrm_short_cmd_req_addr);
1327 "Unable to map buffer to physical memory.\n");
1333 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1334 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1335 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1338 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1339 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1341 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1342 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1343 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1347 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1348 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1349 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1357 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1360 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1361 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1363 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1366 HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1369 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1371 HWRM_CHECK_RESULT();
1374 PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1375 bp->eth_dev->data->port_id);
1380 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1383 struct hwrm_port_phy_cfg_input req = {0};
1384 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1385 uint32_t enables = 0;
1387 HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1389 if (conf->link_up) {
1390 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1391 if (bp->link_info->auto_mode && conf->link_speed) {
1392 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1393 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1396 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1398 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1399 * any auto mode, even "none".
1401 if (!conf->link_speed) {
1402 /* No speeds specified. Enable AutoNeg - all speeds */
1403 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1405 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1407 if (bp->link_info->link_signal_mode) {
1409 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1410 req.force_pam4_link_speed =
1411 rte_cpu_to_le_16(conf->link_speed);
1413 req.force_link_speed =
1414 rte_cpu_to_le_16(conf->link_speed);
1417 /* AutoNeg - Advertise speeds specified. */
1418 if (conf->auto_link_speed_mask &&
1419 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1421 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1422 req.auto_link_speed_mask =
1423 conf->auto_link_speed_mask;
1424 if (conf->auto_pam4_link_speeds) {
1426 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1427 req.auto_link_pam4_speed_mask =
1428 conf->auto_pam4_link_speeds;
1431 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1434 if (conf->auto_link_speed &&
1435 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1437 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1439 req.auto_duplex = conf->duplex;
1440 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1441 req.auto_pause = conf->auto_pause;
1442 req.force_pause = conf->force_pause;
1443 /* Set force_pause if there is no auto or if there is a force */
1444 if (req.auto_pause && !req.force_pause)
1445 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1447 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1449 req.enables = rte_cpu_to_le_32(enables);
1452 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1453 PMD_DRV_LOG(INFO, "Force Link Down\n");
1456 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1458 HWRM_CHECK_RESULT();
1464 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1465 struct bnxt_link_info *link_info)
1468 struct hwrm_port_phy_qcfg_input req = {0};
1469 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1471 HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1473 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1475 HWRM_CHECK_RESULT();
1477 link_info->phy_link_status = resp->link;
1478 link_info->link_up =
1479 (link_info->phy_link_status ==
1480 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1481 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1482 link_info->duplex = resp->duplex_cfg;
1483 link_info->pause = resp->pause;
1484 link_info->auto_pause = resp->auto_pause;
1485 link_info->force_pause = resp->force_pause;
1486 link_info->auto_mode = resp->auto_mode;
1487 link_info->phy_type = resp->phy_type;
1488 link_info->media_type = resp->media_type;
1490 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1491 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1492 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1493 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1494 link_info->phy_ver[0] = resp->phy_maj;
1495 link_info->phy_ver[1] = resp->phy_min;
1496 link_info->phy_ver[2] = resp->phy_bld;
1497 link_info->link_signal_mode =
1498 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1499 link_info->force_pam4_link_speed =
1500 rte_le_to_cpu_16(resp->force_pam4_link_speed);
1501 link_info->support_pam4_speeds =
1502 rte_le_to_cpu_16(resp->support_pam4_speeds);
1503 link_info->auto_pam4_link_speeds =
1504 rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1507 PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1508 link_info->link_speed, link_info->auto_mode,
1509 link_info->auto_link_speed, link_info->auto_link_speed_mask,
1510 link_info->support_speeds, link_info->force_link_speed);
1511 PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1512 link_info->link_signal_mode,
1513 link_info->auto_pam4_link_speeds,
1514 link_info->support_pam4_speeds,
1515 link_info->force_pam4_link_speed);
1519 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1522 struct hwrm_port_phy_qcaps_input req = {0};
1523 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1524 struct bnxt_link_info *link_info = bp->link_info;
1526 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1529 HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1531 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1533 HWRM_CHECK_RESULT_SILENT();
1535 bp->port_cnt = resp->port_cnt;
1536 if (resp->supported_speeds_auto_mode)
1537 link_info->support_auto_speeds =
1538 rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1539 if (resp->supported_pam4_speeds_auto_mode)
1540 link_info->support_pam4_auto_speeds =
1541 rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1548 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1552 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1553 if (bp->tx_cos_queue[i].profile ==
1554 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1555 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1562 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1566 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1567 if (bp->tx_cos_queue[i].profile !=
1568 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1569 bp->tx_cos_queue[i].id !=
1570 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1571 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1577 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1580 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1581 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1582 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1586 HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1588 req.flags = rte_cpu_to_le_32(dir);
1589 /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1590 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1591 !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1593 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1594 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1596 HWRM_CHECK_RESULT();
1598 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1599 GET_TX_QUEUE_INFO(0);
1600 GET_TX_QUEUE_INFO(1);
1601 GET_TX_QUEUE_INFO(2);
1602 GET_TX_QUEUE_INFO(3);
1603 GET_TX_QUEUE_INFO(4);
1604 GET_TX_QUEUE_INFO(5);
1605 GET_TX_QUEUE_INFO(6);
1606 GET_TX_QUEUE_INFO(7);
1608 GET_RX_QUEUE_INFO(0);
1609 GET_RX_QUEUE_INFO(1);
1610 GET_RX_QUEUE_INFO(2);
1611 GET_RX_QUEUE_INFO(3);
1612 GET_RX_QUEUE_INFO(4);
1613 GET_RX_QUEUE_INFO(5);
1614 GET_RX_QUEUE_INFO(6);
1615 GET_RX_QUEUE_INFO(7);
1620 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1623 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1624 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1628 /* iterate and find the COSq profile to use for Tx */
1629 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1630 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1631 if (bp->tx_cos_queue[i].id != 0xff)
1632 bp->tx_cosq_id[j++] =
1633 bp->tx_cos_queue[i].id;
1636 /* When CoS classification is disabled, for normal NIC
1637 * operations, ideally we should look to use LOSSY.
1638 * If not found, fallback to the first valid profile
1640 if (!bnxt_find_lossy_profile(bp))
1641 bnxt_find_first_valid_profile(bp);
1646 bp->max_tc = resp->max_configurable_queues;
1647 bp->max_lltc = resp->max_configurable_lossless_queues;
1648 if (bp->max_tc > BNXT_MAX_QUEUE)
1649 bp->max_tc = BNXT_MAX_QUEUE;
1650 bp->max_q = bp->max_tc;
1652 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1653 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1661 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1662 struct bnxt_ring *ring,
1663 uint32_t ring_type, uint32_t map_index,
1664 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1665 uint16_t tx_cosq_id)
1668 uint32_t enables = 0;
1669 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1670 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1671 struct rte_mempool *mb_pool;
1672 uint16_t rx_buf_size;
1674 HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1676 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1677 req.fbo = rte_cpu_to_le_32(0);
1678 /* Association of ring index with doorbell index */
1679 req.logical_id = rte_cpu_to_le_16(map_index);
1680 req.length = rte_cpu_to_le_32(ring->ring_size);
1682 switch (ring_type) {
1683 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1684 req.ring_type = ring_type;
1685 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1686 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1687 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1688 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1690 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1692 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1693 req.ring_type = ring_type;
1694 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1695 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1696 if (BNXT_CHIP_P5(bp)) {
1697 mb_pool = bp->rx_queues[0]->mb_pool;
1698 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1699 RTE_PKTMBUF_HEADROOM;
1700 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1701 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1703 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1705 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1707 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1709 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1710 req.ring_type = ring_type;
1711 if (BNXT_HAS_NQ(bp)) {
1712 /* Association of cp ring with nq */
1713 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1715 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1717 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1719 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1720 req.ring_type = ring_type;
1721 req.page_size = BNXT_PAGE_SHFT;
1722 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1724 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1725 req.ring_type = ring_type;
1726 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1728 mb_pool = bp->rx_queues[0]->mb_pool;
1729 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1730 RTE_PKTMBUF_HEADROOM;
1731 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1732 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1734 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1735 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1736 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1737 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1740 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1745 req.enables = rte_cpu_to_le_32(enables);
1747 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1749 if (rc || resp->error_code) {
1750 if (rc == 0 && resp->error_code)
1751 rc = rte_le_to_cpu_16(resp->error_code);
1752 switch (ring_type) {
1753 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1755 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1758 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1760 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1763 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1765 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1769 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1771 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1774 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1776 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1780 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1786 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1791 int bnxt_hwrm_ring_free(struct bnxt *bp,
1792 struct bnxt_ring *ring, uint32_t ring_type,
1793 uint16_t cp_ring_id)
1796 struct hwrm_ring_free_input req = {.req_type = 0 };
1797 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1799 HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1801 req.ring_type = ring_type;
1802 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1803 req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1805 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1807 if (rc || resp->error_code) {
1808 if (rc == 0 && resp->error_code)
1809 rc = rte_le_to_cpu_16(resp->error_code);
1812 switch (ring_type) {
1813 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1814 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1817 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1818 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1821 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1822 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1825 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1827 "hwrm_ring_free nq failed. rc:%d\n", rc);
1829 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1831 "hwrm_ring_free agg failed. rc:%d\n", rc);
1834 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1842 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1845 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1846 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1848 HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1850 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1851 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1852 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1853 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1855 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1857 HWRM_CHECK_RESULT();
1859 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1866 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1869 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1870 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1872 HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1874 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1876 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1878 HWRM_CHECK_RESULT();
1881 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1885 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1888 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1889 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1891 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1894 HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1896 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1898 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1900 HWRM_CHECK_RESULT();
1906 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1909 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1910 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1912 HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1914 req.update_period_ms = rte_cpu_to_le_32(0);
1916 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1918 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1920 HWRM_CHECK_RESULT();
1922 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1929 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1932 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1933 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1935 HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1937 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1939 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1941 HWRM_CHECK_RESULT();
1947 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1950 struct hwrm_vnic_alloc_input req = { 0 };
1951 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1953 if (!BNXT_HAS_RING_GRPS(bp))
1954 goto skip_ring_grps;
1956 /* map ring groups to this vnic */
1957 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1958 vnic->start_grp_id, vnic->end_grp_id);
1959 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1960 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1962 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1963 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1964 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1965 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1968 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1969 HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1971 if (vnic->func_default)
1973 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1974 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1976 HWRM_CHECK_RESULT();
1978 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1980 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1984 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1985 struct bnxt_vnic_info *vnic,
1986 struct bnxt_plcmodes_cfg *pmode)
1989 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1990 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1992 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1994 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1996 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1998 HWRM_CHECK_RESULT();
2000 pmode->flags = rte_le_to_cpu_32(resp->flags);
2001 /* dflt_vnic bit doesn't exist in the _cfg command */
2002 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
2003 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
2004 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2005 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2012 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2013 struct bnxt_vnic_info *vnic,
2014 struct bnxt_plcmodes_cfg *pmode)
2017 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2018 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2020 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2021 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2025 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2027 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2028 req.flags = rte_cpu_to_le_32(pmode->flags);
2029 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2030 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2031 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2032 req.enables = rte_cpu_to_le_32(
2033 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2034 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2035 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2038 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2040 HWRM_CHECK_RESULT();
2046 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2049 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2050 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2051 struct bnxt_plcmodes_cfg pmodes = { 0 };
2052 uint32_t ctx_enable_flag = 0;
2053 uint32_t enables = 0;
2055 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2056 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2060 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2064 HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2066 if (BNXT_CHIP_P5(bp)) {
2067 int dflt_rxq = vnic->start_grp_id;
2068 struct bnxt_rx_ring_info *rxr;
2069 struct bnxt_cp_ring_info *cpr;
2070 struct bnxt_rx_queue *rxq;
2074 * The first active receive ring is used as the VNIC
2075 * default receive ring. If there are no active receive
2076 * rings (all corresponding receive queues are stopped),
2077 * the first receive ring is used.
2079 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2080 rxq = bp->eth_dev->data->rx_queues[i];
2081 if (rxq->rx_started) {
2087 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2091 req.default_rx_ring_id =
2092 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2093 req.default_cmpl_ring_id =
2094 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2095 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2096 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2097 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2098 enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2099 req.rx_csum_v2_mode =
2100 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2105 /* Only RSS support for now TBD: COS & LB */
2106 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2107 if (vnic->lb_rule != 0xffff)
2108 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2109 if (vnic->cos_rule != 0xffff)
2110 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2111 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2112 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2113 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2115 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2116 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2117 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2120 enables |= ctx_enable_flag;
2121 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2122 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2123 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2124 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2127 req.enables = rte_cpu_to_le_32(enables);
2128 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2129 req.mru = rte_cpu_to_le_16(vnic->mru);
2130 /* Configure default VNIC only once. */
2131 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2133 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2134 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2136 if (vnic->vlan_strip)
2138 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2141 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2142 if (vnic->rss_dflt_cr)
2143 req.flags |= rte_cpu_to_le_32(
2144 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2146 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2148 HWRM_CHECK_RESULT();
2151 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2156 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2160 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2161 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2163 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2164 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2167 HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2170 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2171 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2172 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2174 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2176 HWRM_CHECK_RESULT();
2178 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2179 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2180 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2181 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2182 vnic->mru = rte_le_to_cpu_16(resp->mru);
2183 vnic->func_default = rte_le_to_cpu_32(
2184 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2185 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2186 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2187 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2188 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2189 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2190 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2197 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2198 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2202 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2203 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2204 bp->hwrm_cmd_resp_addr;
2206 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2208 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2209 HWRM_CHECK_RESULT();
2211 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2212 if (!BNXT_HAS_RING_GRPS(bp))
2213 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2214 else if (ctx_idx == 0)
2215 vnic->rss_rule = ctx_id;
2223 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2224 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2227 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2228 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2229 bp->hwrm_cmd_resp_addr;
2231 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2232 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2235 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2237 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2239 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2241 HWRM_CHECK_RESULT();
2247 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2251 if (BNXT_CHIP_P5(bp)) {
2254 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2255 rc = _bnxt_hwrm_vnic_ctx_free(bp,
2257 vnic->fw_grp_ids[j]);
2258 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2260 vnic->num_lb_ctxts = 0;
2262 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2263 vnic->rss_rule = INVALID_HW_RING_ID;
2269 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2272 struct hwrm_vnic_free_input req = {.req_type = 0 };
2273 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2275 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2276 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2280 HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2282 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2284 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2286 HWRM_CHECK_RESULT();
2289 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2290 /* Configure default VNIC again if necessary. */
2291 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2292 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2298 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2302 int nr_ctxs = vnic->num_lb_ctxts;
2303 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2304 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2306 for (i = 0; i < nr_ctxs; i++) {
2307 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2309 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2310 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2311 req.hash_mode_flags = vnic->hash_mode;
2313 req.hash_key_tbl_addr =
2314 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2316 req.ring_grp_tbl_addr =
2317 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2318 i * HW_HASH_INDEX_SIZE);
2319 req.ring_table_pair_index = i;
2320 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2322 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2325 HWRM_CHECK_RESULT();
2332 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2333 struct bnxt_vnic_info *vnic)
2336 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2337 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2339 if (!vnic->rss_table)
2342 if (BNXT_CHIP_P5(bp))
2343 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2345 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2347 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2348 req.hash_mode_flags = vnic->hash_mode;
2350 req.ring_grp_tbl_addr =
2351 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2352 req.hash_key_tbl_addr =
2353 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2354 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2355 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2359 HWRM_CHECK_RESULT();
2365 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2366 struct bnxt_vnic_info *vnic)
2369 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2370 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2373 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2374 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2378 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2380 req.flags = rte_cpu_to_le_32(
2381 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2383 req.enables = rte_cpu_to_le_32(
2384 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2386 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2387 size -= RTE_PKTMBUF_HEADROOM;
2388 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2390 req.jumbo_thresh = rte_cpu_to_le_16(size);
2391 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2393 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2395 HWRM_CHECK_RESULT();
2401 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2402 struct bnxt_vnic_info *vnic, bool enable)
2405 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2406 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2408 if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2410 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2414 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2415 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2419 HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2422 req.enables = rte_cpu_to_le_32(
2423 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2424 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2425 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2426 req.flags = rte_cpu_to_le_32(
2427 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2428 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2429 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2430 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2431 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2432 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2433 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2434 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2435 req.min_agg_len = rte_cpu_to_le_32(512);
2437 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2439 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2441 HWRM_CHECK_RESULT();
2447 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2449 struct hwrm_func_cfg_input req = {0};
2450 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2453 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2454 req.enables = rte_cpu_to_le_32(
2455 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2456 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2457 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2459 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2461 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2462 HWRM_CHECK_RESULT();
2465 bp->pf->vf_info[vf].random_mac = false;
2470 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2474 struct hwrm_func_qstats_input req = {.req_type = 0};
2475 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2477 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2479 req.fid = rte_cpu_to_le_16(fid);
2481 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2483 HWRM_CHECK_RESULT();
2486 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2493 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2494 struct rte_eth_stats *stats,
2495 struct hwrm_func_qstats_output *func_qstats)
2498 struct hwrm_func_qstats_input req = {.req_type = 0};
2499 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2501 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2503 req.fid = rte_cpu_to_le_16(fid);
2505 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2507 HWRM_CHECK_RESULT();
2509 memcpy(func_qstats, resp,
2510 sizeof(struct hwrm_func_qstats_output));
2515 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2516 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2517 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2518 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2519 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2520 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2522 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2523 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2524 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2525 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2526 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2527 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2529 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2530 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2531 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2539 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2542 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2543 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2545 HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2547 req.fid = rte_cpu_to_le_16(fid);
2549 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2551 HWRM_CHECK_RESULT();
2557 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2562 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2563 struct bnxt_tx_queue *txq;
2564 struct bnxt_rx_queue *rxq;
2565 struct bnxt_cp_ring_info *cpr;
2567 if (i >= bp->rx_cp_nr_rings) {
2568 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2571 rxq = bp->rx_queues[i];
2575 rc = bnxt_hwrm_stat_clear(bp, cpr);
2583 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2587 struct bnxt_cp_ring_info *cpr;
2589 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2591 if (i >= bp->rx_cp_nr_rings) {
2592 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2594 cpr = bp->rx_queues[i]->cp_ring;
2595 if (BNXT_HAS_RING_GRPS(bp))
2596 bp->grp_info[i].fw_stats_ctx = -1;
2598 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2599 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2600 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2608 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2613 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2614 struct bnxt_tx_queue *txq;
2615 struct bnxt_rx_queue *rxq;
2616 struct bnxt_cp_ring_info *cpr;
2618 if (i >= bp->rx_cp_nr_rings) {
2619 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2622 rxq = bp->rx_queues[i];
2626 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
2635 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2640 if (!BNXT_HAS_RING_GRPS(bp))
2643 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2645 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2648 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2656 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2658 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2660 bnxt_hwrm_ring_free(bp, cp_ring,
2661 HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2662 INVALID_HW_RING_ID);
2663 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2664 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2665 sizeof(*cpr->cp_desc_ring));
2666 cpr->cp_raw_cons = 0;
2670 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2672 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2674 bnxt_hwrm_ring_free(bp, cp_ring,
2675 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2676 INVALID_HW_RING_ID);
2677 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2678 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2679 sizeof(*cpr->cp_desc_ring));
2680 cpr->cp_raw_cons = 0;
2684 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2686 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2687 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2688 struct bnxt_ring *ring = rxr->rx_ring_struct;
2689 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2691 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2692 bnxt_hwrm_ring_free(bp, ring,
2693 HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2694 cpr->cp_ring_struct->fw_ring_id);
2695 ring->fw_ring_id = INVALID_HW_RING_ID;
2696 if (BNXT_HAS_RING_GRPS(bp))
2697 bp->grp_info[queue_index].rx_fw_ring_id =
2700 ring = rxr->ag_ring_struct;
2701 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2702 bnxt_hwrm_ring_free(bp, ring,
2704 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2705 HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2706 cpr->cp_ring_struct->fw_ring_id);
2707 if (BNXT_HAS_RING_GRPS(bp))
2708 bp->grp_info[queue_index].ag_fw_ring_id =
2711 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2712 bnxt_free_cp_ring(bp, cpr);
2714 if (BNXT_HAS_RING_GRPS(bp))
2715 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2718 int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int queue_index)
2721 struct hwrm_ring_reset_input req = {.req_type = 0 };
2722 struct hwrm_ring_reset_output *resp = bp->hwrm_cmd_resp_addr;
2724 HWRM_PREP(&req, HWRM_RING_RESET, BNXT_USE_CHIMP_MB);
2726 req.ring_type = HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP;
2727 req.ring_id = rte_cpu_to_le_16(bp->grp_info[queue_index].fw_grp_id);
2728 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2730 HWRM_CHECK_RESULT();
2738 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2742 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2743 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2744 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2745 struct bnxt_ring *ring = txr->tx_ring_struct;
2746 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2748 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2749 bnxt_hwrm_ring_free(bp, ring,
2750 HWRM_RING_FREE_INPUT_RING_TYPE_TX,
2751 cpr->cp_ring_struct->fw_ring_id);
2752 ring->fw_ring_id = INVALID_HW_RING_ID;
2753 memset(txr->tx_desc_ring, 0,
2754 txr->tx_ring_struct->ring_size *
2755 sizeof(*txr->tx_desc_ring));
2756 memset(txr->tx_buf_ring, 0,
2757 txr->tx_ring_struct->ring_size *
2758 sizeof(*txr->tx_buf_ring));
2759 txr->tx_raw_prod = 0;
2760 txr->tx_raw_cons = 0;
2762 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2763 bnxt_free_cp_ring(bp, cpr);
2764 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2768 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2769 bnxt_free_hwrm_rx_ring(bp, i);
2774 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2779 if (!BNXT_HAS_RING_GRPS(bp))
2782 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2783 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2791 * HWRM utility functions
2794 void bnxt_free_hwrm_resources(struct bnxt *bp)
2796 /* Release memzone */
2797 rte_free(bp->hwrm_cmd_resp_addr);
2798 rte_free(bp->hwrm_short_cmd_req_addr);
2799 bp->hwrm_cmd_resp_addr = NULL;
2800 bp->hwrm_short_cmd_req_addr = NULL;
2801 bp->hwrm_cmd_resp_dma_addr = 0;
2802 bp->hwrm_short_cmd_req_dma_addr = 0;
2805 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2807 struct rte_pci_device *pdev = bp->pdev;
2808 char type[RTE_MEMZONE_NAMESIZE];
2810 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2811 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2812 bp->max_resp_len = BNXT_PAGE_SIZE;
2813 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2814 if (bp->hwrm_cmd_resp_addr == NULL)
2816 bp->hwrm_cmd_resp_dma_addr =
2817 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2818 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2820 "unable to map response address to physical memory\n");
2823 rte_spinlock_init(&bp->hwrm_lock);
2829 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2833 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2834 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2837 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2838 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2843 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2848 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2850 struct bnxt_filter_info *filter;
2853 STAILQ_FOREACH(filter, &vnic->filter, next) {
2854 rc = bnxt_clear_one_vnic_filter(bp, filter);
2855 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2856 bnxt_free_filter(bp, filter);
2862 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2864 struct bnxt_filter_info *filter;
2865 struct rte_flow *flow;
2868 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2869 flow = STAILQ_FIRST(&vnic->flow_list);
2870 filter = flow->filter;
2871 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2872 rc = bnxt_clear_one_vnic_filter(bp, filter);
2874 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2880 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2882 struct bnxt_filter_info *filter;
2885 STAILQ_FOREACH(filter, &vnic->filter, next) {
2886 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2887 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2889 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2890 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2893 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2902 bnxt_free_tunnel_ports(struct bnxt *bp)
2904 if (bp->vxlan_port_cnt)
2905 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2906 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2908 if (bp->geneve_port_cnt)
2909 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2910 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2913 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2917 if (bp->vnic_info == NULL)
2921 * Cleanup VNICs in reverse order, to make sure the L2 filter
2922 * from vnic0 is last to be cleaned up.
2924 for (i = bp->max_vnics - 1; i >= 0; i--) {
2925 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2927 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2930 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2932 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2934 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2936 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2938 bnxt_hwrm_vnic_free(bp, vnic);
2940 rte_free(vnic->fw_grp_ids);
2942 /* Ring resources */
2943 bnxt_free_all_hwrm_rings(bp);
2944 bnxt_free_all_hwrm_ring_grps(bp);
2945 bnxt_free_all_hwrm_stat_ctxs(bp);
2946 bnxt_free_tunnel_ports(bp);
2949 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2951 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2953 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2954 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2956 switch (conf_link_speed) {
2957 case ETH_LINK_SPEED_10M_HD:
2958 case ETH_LINK_SPEED_100M_HD:
2960 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2962 return hw_link_duplex;
2965 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2970 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2973 uint16_t eth_link_speed = 0;
2975 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2976 return ETH_LINK_SPEED_AUTONEG;
2978 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2979 case ETH_LINK_SPEED_100M:
2980 case ETH_LINK_SPEED_100M_HD:
2983 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2985 case ETH_LINK_SPEED_1G:
2987 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2989 case ETH_LINK_SPEED_2_5G:
2991 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2993 case ETH_LINK_SPEED_10G:
2995 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2997 case ETH_LINK_SPEED_20G:
2999 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
3001 case ETH_LINK_SPEED_25G:
3003 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
3005 case ETH_LINK_SPEED_40G:
3007 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
3009 case ETH_LINK_SPEED_50G:
3010 eth_link_speed = pam4_link ?
3011 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
3012 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
3014 case ETH_LINK_SPEED_100G:
3015 eth_link_speed = pam4_link ?
3016 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
3017 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
3019 case ETH_LINK_SPEED_200G:
3021 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3025 "Unsupported link speed %d; default to AUTO\n",
3029 return eth_link_speed;
3032 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
3033 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
3034 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
3035 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
3036 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
3038 static int bnxt_validate_link_speed(struct bnxt *bp)
3040 uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3041 uint16_t port_id = bp->eth_dev->data->port_id;
3042 uint32_t link_speed_capa;
3045 if (link_speed == ETH_LINK_SPEED_AUTONEG)
3048 link_speed_capa = bnxt_get_speed_capabilities(bp);
3050 if (link_speed & ETH_LINK_SPEED_FIXED) {
3051 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
3053 if (one_speed & (one_speed - 1)) {
3055 "Invalid advertised speeds (%u) for port %u\n",
3056 link_speed, port_id);
3059 if ((one_speed & link_speed_capa) != one_speed) {
3061 "Unsupported advertised speed (%u) for port %u\n",
3062 link_speed, port_id);
3066 if (!(link_speed & link_speed_capa)) {
3068 "Unsupported advertised speeds (%u) for port %u\n",
3069 link_speed, port_id);
3077 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3081 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
3082 if (bp->link_info->support_speeds)
3083 return bp->link_info->support_speeds;
3084 link_speed = BNXT_SUPPORTED_SPEEDS;
3087 if (link_speed & ETH_LINK_SPEED_100M)
3088 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3089 if (link_speed & ETH_LINK_SPEED_100M_HD)
3090 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3091 if (link_speed & ETH_LINK_SPEED_1G)
3092 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3093 if (link_speed & ETH_LINK_SPEED_2_5G)
3094 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3095 if (link_speed & ETH_LINK_SPEED_10G)
3096 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3097 if (link_speed & ETH_LINK_SPEED_20G)
3098 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3099 if (link_speed & ETH_LINK_SPEED_25G)
3100 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3101 if (link_speed & ETH_LINK_SPEED_40G)
3102 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3103 if (link_speed & ETH_LINK_SPEED_50G)
3104 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3105 if (link_speed & ETH_LINK_SPEED_100G)
3106 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3107 if (link_speed & ETH_LINK_SPEED_200G)
3108 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3112 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3114 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
3116 switch (hw_link_speed) {
3117 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3118 eth_link_speed = ETH_SPEED_NUM_100M;
3120 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3121 eth_link_speed = ETH_SPEED_NUM_1G;
3123 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3124 eth_link_speed = ETH_SPEED_NUM_2_5G;
3126 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3127 eth_link_speed = ETH_SPEED_NUM_10G;
3129 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3130 eth_link_speed = ETH_SPEED_NUM_20G;
3132 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3133 eth_link_speed = ETH_SPEED_NUM_25G;
3135 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3136 eth_link_speed = ETH_SPEED_NUM_40G;
3138 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3139 eth_link_speed = ETH_SPEED_NUM_50G;
3141 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3142 eth_link_speed = ETH_SPEED_NUM_100G;
3144 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3145 eth_link_speed = ETH_SPEED_NUM_200G;
3147 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3149 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3153 return eth_link_speed;
3156 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3158 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3160 switch (hw_link_duplex) {
3161 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3162 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3164 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3166 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3167 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3170 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3174 return eth_link_duplex;
3177 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3180 struct bnxt_link_info *link_info = bp->link_info;
3182 rc = bnxt_hwrm_port_phy_qcaps(bp);
3184 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3186 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3188 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3192 if (link_info->link_speed)
3194 bnxt_parse_hw_link_speed(link_info->link_speed);
3196 link->link_speed = ETH_SPEED_NUM_NONE;
3197 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3198 link->link_status = link_info->link_up;
3199 link->link_autoneg = link_info->auto_mode ==
3200 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3201 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3206 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3209 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3210 struct bnxt_link_info link_req;
3211 uint16_t speed, autoneg;
3213 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3216 rc = bnxt_validate_link_speed(bp);
3220 memset(&link_req, 0, sizeof(link_req));
3221 link_req.link_up = link_up;
3225 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3226 if (BNXT_CHIP_P5(bp) &&
3227 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3228 /* 40G is not supported as part of media auto detect.
3229 * The speed should be forced and autoneg disabled
3230 * to configure 40G speed.
3232 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3236 /* No auto speeds and no auto_pam4_link. Disable autoneg */
3237 if (bp->link_info->auto_link_speed == 0 &&
3238 bp->link_info->link_signal_mode &&
3239 bp->link_info->auto_pam4_link_speeds == 0)
3242 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3243 bp->link_info->link_signal_mode);
3244 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3245 /* Autoneg can be done only when the FW allows.
3246 * When user configures fixed speed of 40G and later changes to
3247 * any other speed, auto_link_speed/force_link_speed is still set
3248 * to 40G until link comes up at new speed.
3251 !(!BNXT_CHIP_P5(bp) &&
3252 (bp->link_info->auto_link_speed ||
3253 bp->link_info->force_link_speed))) {
3254 link_req.phy_flags |=
3255 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3256 link_req.auto_link_speed_mask =
3257 bnxt_parse_eth_link_speed_mask(bp,
3258 dev_conf->link_speeds);
3260 if (bp->link_info->phy_type ==
3261 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3262 bp->link_info->phy_type ==
3263 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3264 bp->link_info->media_type ==
3265 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3266 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3270 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3271 /* If user wants a particular speed try that first. */
3273 link_req.link_speed = speed;
3274 else if (bp->link_info->force_pam4_link_speed)
3275 link_req.link_speed =
3276 bp->link_info->force_pam4_link_speed;
3277 else if (bp->link_info->auto_pam4_link_speeds)
3278 link_req.link_speed =
3279 bp->link_info->auto_pam4_link_speeds;
3280 else if (bp->link_info->support_pam4_speeds)
3281 link_req.link_speed =
3282 bp->link_info->support_pam4_speeds;
3283 else if (bp->link_info->force_link_speed)
3284 link_req.link_speed = bp->link_info->force_link_speed;
3286 link_req.link_speed = bp->link_info->auto_link_speed;
3287 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3288 * zero. Use the auto_link_speed.
3290 if (bp->link_info->auto_link_speed != 0 &&
3291 bp->link_info->auto_pam4_link_speeds == 0)
3292 link_req.link_speed = bp->link_info->auto_link_speed;
3294 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3295 link_req.auto_pause = bp->link_info->auto_pause;
3296 link_req.force_pause = bp->link_info->force_pause;
3299 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3302 "Set link config failed with rc %d\n", rc);
3310 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3312 struct hwrm_func_qcfg_input req = {0};
3313 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3316 bp->func_svif = BNXT_SVIF_INVALID;
3319 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3320 req.fid = rte_cpu_to_le_16(0xffff);
3322 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3324 HWRM_CHECK_RESULT();
3326 /* Hard Coded.. 0xfff VLAN ID mask */
3327 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3329 svif_info = rte_le_to_cpu_16(resp->svif_info);
3330 if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3331 bp->func_svif = svif_info &
3332 HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3334 flags = rte_le_to_cpu_16(resp->flags);
3335 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3336 bp->flags |= BNXT_FLAG_MULTI_HOST;
3339 !BNXT_VF_IS_TRUSTED(bp) &&
3340 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3341 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3342 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3343 } else if (BNXT_VF(bp) &&
3344 BNXT_VF_IS_TRUSTED(bp) &&
3345 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3346 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3347 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3351 *mtu = rte_le_to_cpu_16(resp->mtu);
3353 switch (resp->port_partition_type) {
3354 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3355 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3356 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3358 bp->flags |= BNXT_FLAG_NPAR_PF;
3361 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3365 bp->legacy_db_size =
3366 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3373 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3375 struct hwrm_func_qcfg_input req = {0};
3376 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3379 if (!BNXT_VF_IS_TRUSTED(bp))
3385 bp->parent->fid = BNXT_PF_FID_INVALID;
3387 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3389 req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3391 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3393 HWRM_CHECK_RESULT_SILENT();
3395 memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3396 bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3397 bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3398 bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3400 /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3401 if (bp->parent->vnic == 0) {
3402 PMD_DRV_LOG(DEBUG, "parent VNIC unavailable.\n");
3403 /* Use hard-coded values appropriate for current Wh+ fw. */
3404 if (bp->parent->fid == 2)
3405 bp->parent->vnic = 0x100;
3407 bp->parent->vnic = 1;
3415 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3416 uint16_t *vnic_id, uint16_t *svif)
3418 struct hwrm_func_qcfg_input req = {0};
3419 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3423 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3424 req.fid = rte_cpu_to_le_16(fid);
3426 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3428 HWRM_CHECK_RESULT();
3431 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3433 svif_info = rte_le_to_cpu_16(resp->svif_info);
3434 if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3435 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3442 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3444 struct hwrm_port_mac_qcfg_input req = {0};
3445 struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3446 uint16_t port_svif_info;
3449 bp->port_svif = BNXT_SVIF_INVALID;
3451 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3454 HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3456 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3458 HWRM_CHECK_RESULT_SILENT();
3460 port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3461 if (port_svif_info &
3462 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3463 bp->port_svif = port_svif_info &
3464 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3471 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3472 struct bnxt_pf_resource_info *pf_resc)
3474 struct hwrm_func_cfg_input req = {0};
3475 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3479 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3480 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3481 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3482 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3483 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3484 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3485 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3486 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3487 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3489 if (BNXT_HAS_RING_GRPS(bp)) {
3490 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3491 req.num_hw_ring_grps =
3492 rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3493 } else if (BNXT_HAS_NQ(bp)) {
3494 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3495 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3498 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3499 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3500 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3501 req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3502 req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3503 req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3504 req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3505 req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3506 req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3507 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3508 req.fid = rte_cpu_to_le_16(0xffff);
3509 req.enables = rte_cpu_to_le_32(enables);
3511 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3513 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3515 HWRM_CHECK_RESULT();
3521 /* min values are the guaranteed resources and max values are subject
3522 * to availability. The strategy for now is to keep both min & max
3526 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3527 struct hwrm_func_vf_resource_cfg_input *req,
3530 req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3532 req->min_rsscos_ctx = req->max_rsscos_ctx;
3533 req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3534 req->min_stat_ctx = req->max_stat_ctx;
3535 req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3537 req->min_cmpl_rings = req->max_cmpl_rings;
3538 req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3539 req->min_tx_rings = req->max_tx_rings;
3540 req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3541 req->min_rx_rings = req->max_rx_rings;
3542 req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3543 req->min_l2_ctxs = req->max_l2_ctxs;
3544 /* TODO: For now, do not support VMDq/RFS on VFs. */
3545 req->max_vnics = rte_cpu_to_le_16(1);
3546 req->min_vnics = req->max_vnics;
3547 req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3549 req->min_hw_ring_grps = req->max_hw_ring_grps;
3551 rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3555 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3556 struct hwrm_func_cfg_input *req,
3559 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3560 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3561 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3562 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3563 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3564 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3565 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3566 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3567 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3568 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3570 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3571 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3573 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3574 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3576 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3577 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3579 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3580 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3581 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3582 /* TODO: For now, do not support VMDq/RFS on VFs. */
3583 req->num_vnics = rte_cpu_to_le_16(1);
3584 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3588 /* Update the port wide resource values based on how many resources
3589 * got allocated to the VF.
3591 static int bnxt_update_max_resources(struct bnxt *bp,
3594 struct hwrm_func_qcfg_input req = {0};
3595 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3598 /* Get the actual allocated values now */
3599 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3600 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3601 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3602 HWRM_CHECK_RESULT();
3604 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3605 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3606 bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3607 bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3608 bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3609 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3610 bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3617 /* Update the PF resource values based on how many resources
3618 * got allocated to it.
3620 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3622 struct hwrm_func_qcfg_input req = {0};
3623 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3626 /* Get the actual allocated values now */
3627 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3628 req.fid = rte_cpu_to_le_16(0xffff);
3629 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3630 HWRM_CHECK_RESULT();
3632 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3633 bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3634 bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3635 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3636 bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3637 bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3638 bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3639 bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3646 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3648 struct hwrm_func_qcfg_input req = {0};
3649 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3652 /* Check for zero MAC address */
3653 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3654 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3655 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3656 HWRM_CHECK_RESULT();
3657 rc = rte_le_to_cpu_16(resp->vlan);
3664 static int bnxt_query_pf_resources(struct bnxt *bp,
3665 struct bnxt_pf_resource_info *pf_resc)
3667 struct hwrm_func_qcfg_input req = {0};
3668 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3671 /* And copy the allocated numbers into the pf struct */
3672 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3673 req.fid = rte_cpu_to_le_16(0xffff);
3674 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3675 HWRM_CHECK_RESULT();
3677 pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3678 pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3679 pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3680 pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3681 pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3682 pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3683 pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3684 bp->pf->evb_mode = resp->evb_mode;
3692 bnxt_calculate_pf_resources(struct bnxt *bp,
3693 struct bnxt_pf_resource_info *pf_resc,
3697 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3698 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3699 pf_resc->num_cp_rings = bp->max_cp_rings;
3700 pf_resc->num_tx_rings = bp->max_tx_rings;
3701 pf_resc->num_rx_rings = bp->max_rx_rings;
3702 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3703 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3708 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3709 bp->max_rsscos_ctx % (num_vfs + 1);
3710 pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3711 bp->max_stat_ctx % (num_vfs + 1);
3712 pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3713 bp->max_cp_rings % (num_vfs + 1);
3714 pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3715 bp->max_tx_rings % (num_vfs + 1);
3716 pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3717 bp->max_rx_rings % (num_vfs + 1);
3718 pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3719 bp->max_l2_ctx % (num_vfs + 1);
3720 pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3721 bp->max_ring_grps % (num_vfs + 1);
3724 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3726 struct bnxt_pf_resource_info pf_resc = { 0 };
3730 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3734 rc = bnxt_hwrm_func_qcaps(bp);
3738 bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3740 bp->pf->func_cfg_flags &=
3741 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3742 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3743 bp->pf->func_cfg_flags |=
3744 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3746 rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3750 rc = bnxt_update_max_resources_pf_only(bp);
3756 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3758 size_t req_buf_sz, sz;
3761 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3762 bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3763 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3764 if (bp->pf->vf_req_buf == NULL) {
3768 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3769 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3771 for (i = 0; i < num_vfs; i++)
3772 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3773 (i * HWRM_MAX_REQ_LEN);
3775 rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3777 rte_free(bp->pf->vf_req_buf);
3783 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3785 struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3786 struct hwrm_func_vf_resource_cfg_input req = {0};
3789 bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3790 bp->pf->active_vfs = 0;
3791 for (i = 0; i < num_vfs; i++) {
3792 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3793 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3794 rc = bnxt_hwrm_send_message(bp,
3798 if (rc || resp->error_code) {
3800 "Failed to initialize VF %d\n", i);
3802 "Not all VFs available. (%d, %d)\n",
3803 rc, resp->error_code);
3806 /* If the first VF configuration itself fails,
3807 * unregister the vf_fwd_request buffer.
3810 bnxt_hwrm_func_buf_unrgtr(bp);
3815 /* Update the max resource values based on the resource values
3816 * allocated to the VF.
3818 bnxt_update_max_resources(bp, i);
3819 bp->pf->active_vfs++;
3820 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3827 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3829 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3830 struct hwrm_func_cfg_input req = {0};
3833 bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3835 bp->pf->active_vfs = 0;
3836 for (i = 0; i < num_vfs; i++) {
3837 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3838 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3839 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3840 rc = bnxt_hwrm_send_message(bp,
3845 /* Clear enable flag for next pass */
3846 req.enables &= ~rte_cpu_to_le_32(
3847 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3849 if (rc || resp->error_code) {
3851 "Failed to initialize VF %d\n", i);
3853 "Not all VFs available. (%d, %d)\n",
3854 rc, resp->error_code);
3857 /* If the first VF configuration itself fails,
3858 * unregister the vf_fwd_request buffer.
3861 bnxt_hwrm_func_buf_unrgtr(bp);
3867 /* Update the max resource values based on the resource values
3868 * allocated to the VF.
3870 bnxt_update_max_resources(bp, i);
3871 bp->pf->active_vfs++;
3872 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3879 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3881 if (bp->flags & BNXT_FLAG_NEW_RM)
3882 bnxt_process_vf_resc_config_new(bp, num_vfs);
3884 bnxt_process_vf_resc_config_old(bp, num_vfs);
3888 bnxt_update_pf_resources(struct bnxt *bp,
3889 struct bnxt_pf_resource_info *pf_resc)
3891 bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3892 bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3893 bp->max_cp_rings = pf_resc->num_cp_rings;
3894 bp->max_tx_rings = pf_resc->num_tx_rings;
3895 bp->max_rx_rings = pf_resc->num_rx_rings;
3896 bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3900 bnxt_configure_pf_resources(struct bnxt *bp,
3901 struct bnxt_pf_resource_info *pf_resc)
3904 * We're using STD_TX_RING_MODE here which will limit the TX
3905 * rings. This will allow QoS to function properly. Not setting this
3906 * will cause PF rings to break bandwidth settings.
3908 bp->pf->func_cfg_flags &=
3909 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3910 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3911 bp->pf->func_cfg_flags |=
3912 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3913 return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3916 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3918 struct bnxt_pf_resource_info pf_resc = { 0 };
3922 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3926 rc = bnxt_hwrm_func_qcaps(bp);
3930 bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3932 rc = bnxt_configure_pf_resources(bp, &pf_resc);
3936 rc = bnxt_query_pf_resources(bp, &pf_resc);
3941 * Now, create and register a buffer to hold forwarded VF requests
3943 rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3947 bnxt_configure_vf_resources(bp, num_vfs);
3949 bnxt_update_pf_resources(bp, &pf_resc);
3954 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3956 struct hwrm_func_cfg_input req = {0};
3957 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3960 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3962 req.fid = rte_cpu_to_le_16(0xffff);
3963 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3964 req.evb_mode = bp->pf->evb_mode;
3966 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3967 HWRM_CHECK_RESULT();
3973 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3974 uint8_t tunnel_type)
3976 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3977 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3980 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3981 req.tunnel_type = tunnel_type;
3982 req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3983 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3984 HWRM_CHECK_RESULT();
3986 switch (tunnel_type) {
3987 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3988 bp->vxlan_fw_dst_port_id =
3989 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3990 bp->vxlan_port = port;
3992 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3993 bp->geneve_fw_dst_port_id =
3994 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3995 bp->geneve_port = port;
4006 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
4007 uint8_t tunnel_type)
4009 struct hwrm_tunnel_dst_port_free_input req = {0};
4010 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
4013 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
4015 req.tunnel_type = tunnel_type;
4016 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
4017 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4019 HWRM_CHECK_RESULT();
4023 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4025 bp->vxlan_port_cnt = 0;
4029 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4030 bp->geneve_port = 0;
4031 bp->geneve_port_cnt = 0;
4037 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4040 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4041 struct hwrm_func_cfg_input req = {0};
4044 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4046 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4047 req.flags = rte_cpu_to_le_32(flags);
4048 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4050 HWRM_CHECK_RESULT();
4056 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4058 uint32_t *flag = flagp;
4060 vnic->flags = *flag;
4063 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4065 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4068 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4070 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4071 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4074 HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4076 req.req_buf_num_pages = rte_cpu_to_le_16(1);
4077 req.req_buf_page_size =
4078 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4079 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4080 req.req_buf_page_addr0 =
4081 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4082 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4084 "unable to map buffer address to physical memory\n");
4089 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4091 HWRM_CHECK_RESULT();
4097 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4100 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4101 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4103 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4106 HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4108 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4110 HWRM_CHECK_RESULT();
4116 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4118 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4119 struct hwrm_func_cfg_input req = {0};
4122 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4124 req.fid = rte_cpu_to_le_16(0xffff);
4125 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4126 req.enables = rte_cpu_to_le_32(
4127 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4128 req.async_event_cr = rte_cpu_to_le_16(
4129 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4130 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4132 HWRM_CHECK_RESULT();
4138 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4140 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4141 struct hwrm_func_vf_cfg_input req = {0};
4144 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4146 req.enables = rte_cpu_to_le_32(
4147 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4148 req.async_event_cr = rte_cpu_to_le_16(
4149 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4150 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4152 HWRM_CHECK_RESULT();
4158 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4160 struct hwrm_func_cfg_input req = {0};
4161 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4162 uint16_t dflt_vlan, fid;
4163 uint32_t func_cfg_flags;
4166 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4169 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4170 fid = bp->pf->vf_info[vf].fid;
4171 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4173 fid = rte_cpu_to_le_16(0xffff);
4174 func_cfg_flags = bp->pf->func_cfg_flags;
4175 dflt_vlan = bp->vlan;
4178 req.flags = rte_cpu_to_le_32(func_cfg_flags);
4179 req.fid = rte_cpu_to_le_16(fid);
4180 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4181 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4183 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4185 HWRM_CHECK_RESULT();
4191 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4192 uint16_t max_bw, uint16_t enables)
4194 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4195 struct hwrm_func_cfg_input req = {0};
4198 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4200 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4201 req.enables |= rte_cpu_to_le_32(enables);
4202 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4203 req.max_bw = rte_cpu_to_le_32(max_bw);
4204 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4206 HWRM_CHECK_RESULT();
4212 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4214 struct hwrm_func_cfg_input req = {0};
4215 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4218 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4220 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4221 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4222 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4223 req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4225 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4227 HWRM_CHECK_RESULT();
4233 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4238 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4240 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4245 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4246 void *encaped, size_t ec_size)
4249 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4250 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4252 if (ec_size > sizeof(req.encap_request))
4255 HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4257 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4258 memcpy(req.encap_request, encaped, ec_size);
4260 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4262 HWRM_CHECK_RESULT();
4268 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4269 struct rte_ether_addr *mac)
4271 struct hwrm_func_qcfg_input req = {0};
4272 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4275 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4277 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4278 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4280 HWRM_CHECK_RESULT();
4282 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4289 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4290 void *encaped, size_t ec_size)
4293 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4294 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4296 if (ec_size > sizeof(req.encap_request))
4299 HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4301 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4302 memcpy(req.encap_request, encaped, ec_size);
4304 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4306 HWRM_CHECK_RESULT();
4312 static void bnxt_update_prev_stat(uint64_t *cntr, uint64_t *prev_cntr)
4314 /* One of the HW stat values that make up this counter was zero as
4315 * returned by HW in this iteration, so use the previous
4316 * iteration's counter value
4318 if (*prev_cntr && *cntr == 0)
4324 int bnxt_hwrm_ring_stats(struct bnxt *bp, uint32_t cid, int idx,
4325 struct bnxt_ring_stats *ring_stats, bool rx)
4328 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4329 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4331 HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4333 req.stat_ctx_id = rte_cpu_to_le_32(cid);
4335 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4337 HWRM_CHECK_RESULT();
4340 struct bnxt_ring_stats *prev_stats = &bp->prev_rx_ring_stats[idx];
4342 ring_stats->rx_ucast_pkts = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4343 bnxt_update_prev_stat(&ring_stats->rx_ucast_pkts,
4344 &prev_stats->rx_ucast_pkts);
4346 ring_stats->rx_mcast_pkts = rte_le_to_cpu_64(resp->rx_mcast_pkts);
4347 bnxt_update_prev_stat(&ring_stats->rx_mcast_pkts,
4348 &prev_stats->rx_mcast_pkts);
4350 ring_stats->rx_bcast_pkts = rte_le_to_cpu_64(resp->rx_bcast_pkts);
4351 bnxt_update_prev_stat(&ring_stats->rx_bcast_pkts,
4352 &prev_stats->rx_bcast_pkts);
4354 ring_stats->rx_ucast_bytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4355 bnxt_update_prev_stat(&ring_stats->rx_ucast_bytes,
4356 &prev_stats->rx_ucast_bytes);
4358 ring_stats->rx_mcast_bytes = rte_le_to_cpu_64(resp->rx_mcast_bytes);
4359 bnxt_update_prev_stat(&ring_stats->rx_mcast_bytes,
4360 &prev_stats->rx_mcast_bytes);
4362 ring_stats->rx_bcast_bytes = rte_le_to_cpu_64(resp->rx_bcast_bytes);
4363 bnxt_update_prev_stat(&ring_stats->rx_bcast_bytes,
4364 &prev_stats->rx_bcast_bytes);
4366 ring_stats->rx_discard_pkts = rte_le_to_cpu_64(resp->rx_discard_pkts);
4367 bnxt_update_prev_stat(&ring_stats->rx_discard_pkts,
4368 &prev_stats->rx_discard_pkts);
4370 ring_stats->rx_error_pkts = rte_le_to_cpu_64(resp->rx_error_pkts);
4371 bnxt_update_prev_stat(&ring_stats->rx_error_pkts,
4372 &prev_stats->rx_error_pkts);
4374 ring_stats->rx_agg_pkts = rte_le_to_cpu_64(resp->rx_agg_pkts);
4375 bnxt_update_prev_stat(&ring_stats->rx_agg_pkts,
4376 &prev_stats->rx_agg_pkts);
4378 ring_stats->rx_agg_bytes = rte_le_to_cpu_64(resp->rx_agg_bytes);
4379 bnxt_update_prev_stat(&ring_stats->rx_agg_bytes,
4380 &prev_stats->rx_agg_bytes);
4382 ring_stats->rx_agg_events = rte_le_to_cpu_64(resp->rx_agg_events);
4383 bnxt_update_prev_stat(&ring_stats->rx_agg_events,
4384 &prev_stats->rx_agg_events);
4386 ring_stats->rx_agg_aborts = rte_le_to_cpu_64(resp->rx_agg_aborts);
4387 bnxt_update_prev_stat(&ring_stats->rx_agg_aborts,
4388 &prev_stats->rx_agg_aborts);
4390 struct bnxt_ring_stats *prev_stats = &bp->prev_tx_ring_stats[idx];
4392 ring_stats->tx_ucast_pkts = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4393 bnxt_update_prev_stat(&ring_stats->tx_ucast_pkts,
4394 &prev_stats->tx_ucast_pkts);
4396 ring_stats->tx_mcast_pkts = rte_le_to_cpu_64(resp->tx_mcast_pkts);
4397 bnxt_update_prev_stat(&ring_stats->tx_mcast_pkts,
4398 &prev_stats->tx_mcast_pkts);
4400 ring_stats->tx_bcast_pkts = rte_le_to_cpu_64(resp->tx_bcast_pkts);
4401 bnxt_update_prev_stat(&ring_stats->tx_bcast_pkts,
4402 &prev_stats->tx_bcast_pkts);
4404 ring_stats->tx_ucast_bytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4405 bnxt_update_prev_stat(&ring_stats->tx_ucast_bytes,
4406 &prev_stats->tx_ucast_bytes);
4408 ring_stats->tx_mcast_bytes = rte_le_to_cpu_64(resp->tx_mcast_bytes);
4409 bnxt_update_prev_stat(&ring_stats->tx_mcast_bytes,
4410 &prev_stats->tx_mcast_bytes);
4412 ring_stats->tx_bcast_bytes = rte_le_to_cpu_64(resp->tx_bcast_bytes);
4413 bnxt_update_prev_stat(&ring_stats->tx_bcast_bytes,
4414 &prev_stats->tx_bcast_bytes);
4416 ring_stats->tx_discard_pkts = rte_le_to_cpu_64(resp->tx_discard_pkts);
4417 bnxt_update_prev_stat(&ring_stats->tx_discard_pkts,
4418 &prev_stats->tx_discard_pkts);
4426 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4428 struct hwrm_port_qstats_input req = {0};
4429 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4430 struct bnxt_pf_info *pf = bp->pf;
4433 HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4435 req.port_id = rte_cpu_to_le_16(pf->port_id);
4436 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4437 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4438 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4440 HWRM_CHECK_RESULT();
4446 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4448 struct hwrm_port_clr_stats_input req = {0};
4449 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4450 struct bnxt_pf_info *pf = bp->pf;
4453 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4454 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4455 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4458 HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4460 req.port_id = rte_cpu_to_le_16(pf->port_id);
4461 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4463 HWRM_CHECK_RESULT();
4469 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4471 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4472 struct hwrm_port_led_qcaps_input req = {0};
4478 HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4479 req.port_id = bp->pf->port_id;
4480 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4482 HWRM_CHECK_RESULT_SILENT();
4484 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4487 bp->leds->num_leds = resp->num_leds;
4488 memcpy(bp->leds, &resp->led0_id,
4489 sizeof(bp->leds[0]) * bp->leds->num_leds);
4490 for (i = 0; i < bp->leds->num_leds; i++) {
4491 struct bnxt_led_info *led = &bp->leds[i];
4493 uint16_t caps = led->led_state_caps;
4495 if (!led->led_group_id ||
4496 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4497 bp->leds->num_leds = 0;
4508 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4510 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4511 struct hwrm_port_led_cfg_input req = {0};
4512 struct bnxt_led_cfg *led_cfg;
4513 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4514 uint16_t duration = 0;
4517 if (!bp->leds->num_leds || BNXT_VF(bp))
4520 HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4523 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4524 duration = rte_cpu_to_le_16(500);
4526 req.port_id = bp->pf->port_id;
4527 req.num_leds = bp->leds->num_leds;
4528 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4529 for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4530 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4531 led_cfg->led_id = bp->leds[i].led_id;
4532 led_cfg->led_state = led_state;
4533 led_cfg->led_blink_on = duration;
4534 led_cfg->led_blink_off = duration;
4535 led_cfg->led_group_id = bp->leds[i].led_group_id;
4538 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4540 HWRM_CHECK_RESULT();
4546 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4550 struct hwrm_nvm_get_dir_info_input req = {0};
4551 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4553 HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4555 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4557 HWRM_CHECK_RESULT();
4559 *entries = rte_le_to_cpu_32(resp->entries);
4560 *length = rte_le_to_cpu_32(resp->entry_length);
4566 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4569 uint32_t dir_entries;
4570 uint32_t entry_length;
4573 rte_iova_t dma_handle;
4574 struct hwrm_nvm_get_dir_entries_input req = {0};
4575 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4577 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4581 *data++ = dir_entries;
4582 *data++ = entry_length;
4584 memset(data, 0xff, len);
4586 buflen = dir_entries * entry_length;
4587 buf = rte_malloc("nvm_dir", buflen, 0);
4590 dma_handle = rte_malloc_virt2iova(buf);
4591 if (dma_handle == RTE_BAD_IOVA) {
4594 "unable to map response address to physical memory\n");
4597 HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4598 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4599 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4602 memcpy(data, buf, len > buflen ? buflen : len);
4605 HWRM_CHECK_RESULT();
4611 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4612 uint32_t offset, uint32_t length,
4617 rte_iova_t dma_handle;
4618 struct hwrm_nvm_read_input req = {0};
4619 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4621 buf = rte_malloc("nvm_item", length, 0);
4625 dma_handle = rte_malloc_virt2iova(buf);
4626 if (dma_handle == RTE_BAD_IOVA) {
4629 "unable to map response address to physical memory\n");
4632 HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4633 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4634 req.dir_idx = rte_cpu_to_le_16(index);
4635 req.offset = rte_cpu_to_le_32(offset);
4636 req.len = rte_cpu_to_le_32(length);
4637 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4639 memcpy(data, buf, length);
4642 HWRM_CHECK_RESULT();
4648 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4651 struct hwrm_nvm_erase_dir_entry_input req = {0};
4652 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4654 HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4655 req.dir_idx = rte_cpu_to_le_16(index);
4656 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4657 HWRM_CHECK_RESULT();
4664 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4665 uint16_t dir_ordinal, uint16_t dir_ext,
4666 uint16_t dir_attr, const uint8_t *data,
4670 struct hwrm_nvm_write_input req = {0};
4671 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4672 rte_iova_t dma_handle;
4675 buf = rte_malloc("nvm_write", data_len, 0);
4679 dma_handle = rte_malloc_virt2iova(buf);
4680 if (dma_handle == RTE_BAD_IOVA) {
4683 "unable to map response address to physical memory\n");
4686 memcpy(buf, data, data_len);
4688 HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4690 req.dir_type = rte_cpu_to_le_16(dir_type);
4691 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4692 req.dir_ext = rte_cpu_to_le_16(dir_ext);
4693 req.dir_attr = rte_cpu_to_le_16(dir_attr);
4694 req.dir_data_length = rte_cpu_to_le_32(data_len);
4695 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4697 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4700 HWRM_CHECK_RESULT();
4707 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4709 uint32_t *count = cbdata;
4711 *count = *count + 1;
4714 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4715 struct bnxt_vnic_info *vnic __rte_unused)
4720 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4724 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4725 &count, bnxt_vnic_count_hwrm_stub);
4730 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4733 struct hwrm_func_vf_vnic_ids_query_input req = {0};
4734 struct hwrm_func_vf_vnic_ids_query_output *resp =
4735 bp->hwrm_cmd_resp_addr;
4738 /* First query all VNIC ids */
4739 HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4741 req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4742 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4743 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4745 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4748 "unable to map VNIC ID table address to physical memory\n");
4751 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4752 HWRM_CHECK_RESULT();
4753 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4761 * This function queries the VNIC IDs for a specified VF. It then calls
4762 * the vnic_cb to update the necessary field in vnic_info with cbdata.
4763 * Then it calls the hwrm_cb function to program this new vnic configuration.
4765 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4766 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4767 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4769 struct bnxt_vnic_info vnic;
4771 int i, num_vnic_ids;
4776 /* First query all VNIC ids */
4777 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4778 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4779 RTE_CACHE_LINE_SIZE);
4780 if (vnic_ids == NULL)
4783 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4784 rte_mem_lock_page(((char *)vnic_ids) + sz);
4786 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4788 if (num_vnic_ids < 0)
4789 return num_vnic_ids;
4791 /* Retrieve VNIC, update bd_stall then update */
4793 for (i = 0; i < num_vnic_ids; i++) {
4794 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4795 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4796 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4799 if (vnic.mru <= 4) /* Indicates unallocated */
4802 vnic_cb(&vnic, cbdata);
4804 rc = hwrm_cb(bp, &vnic);
4814 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4817 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4818 struct hwrm_func_cfg_input req = {0};
4821 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4823 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4824 req.enables |= rte_cpu_to_le_32(
4825 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4826 req.vlan_antispoof_mode = on ?
4827 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4828 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4829 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4831 HWRM_CHECK_RESULT();
4837 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4839 struct bnxt_vnic_info vnic;
4842 int num_vnic_ids, i;
4846 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4847 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4848 RTE_CACHE_LINE_SIZE);
4849 if (vnic_ids == NULL)
4852 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4853 rte_mem_lock_page(((char *)vnic_ids) + sz);
4855 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4861 * Loop through to find the default VNIC ID.
4862 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4863 * by sending the hwrm_func_qcfg command to the firmware.
4865 for (i = 0; i < num_vnic_ids; i++) {
4866 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4867 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4868 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4869 bp->pf->first_vf_id + vf);
4872 if (vnic.func_default) {
4874 return vnic.fw_vnic_id;
4877 /* Could not find a default VNIC. */
4878 PMD_DRV_LOG(ERR, "No default VNIC\n");
4884 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4886 struct bnxt_filter_info *filter)
4889 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4890 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4891 uint32_t enables = 0;
4893 if (filter->fw_em_filter_id != UINT64_MAX)
4894 bnxt_hwrm_clear_em_filter(bp, filter);
4896 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4898 req.flags = rte_cpu_to_le_32(filter->flags);
4900 enables = filter->enables |
4901 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4902 req.dst_id = rte_cpu_to_le_16(dst_id);
4904 if (filter->ip_addr_type) {
4905 req.ip_addr_type = filter->ip_addr_type;
4906 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4909 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4910 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4912 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4913 memcpy(req.src_macaddr, filter->src_macaddr,
4914 RTE_ETHER_ADDR_LEN);
4916 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4917 memcpy(req.dst_macaddr, filter->dst_macaddr,
4918 RTE_ETHER_ADDR_LEN);
4920 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4921 req.ovlan_vid = filter->l2_ovlan;
4923 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4924 req.ivlan_vid = filter->l2_ivlan;
4926 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4927 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4929 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4930 req.ip_protocol = filter->ip_protocol;
4932 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4933 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4935 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4936 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4938 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4939 req.src_port = rte_cpu_to_be_16(filter->src_port);
4941 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4942 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4944 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4945 req.mirror_vnic_id = filter->mirror_vnic_id;
4947 req.enables = rte_cpu_to_le_32(enables);
4949 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4951 HWRM_CHECK_RESULT();
4953 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4959 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4962 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4963 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4965 if (filter->fw_em_filter_id == UINT64_MAX)
4968 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4970 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4972 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4974 HWRM_CHECK_RESULT();
4977 filter->fw_em_filter_id = UINT64_MAX;
4978 filter->fw_l2_filter_id = UINT64_MAX;
4983 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4985 struct bnxt_filter_info *filter)
4988 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4989 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4990 bp->hwrm_cmd_resp_addr;
4991 uint32_t enables = 0;
4993 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4994 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4996 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4998 req.flags = rte_cpu_to_le_32(filter->flags);
5000 enables = filter->enables |
5001 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
5002 req.dst_id = rte_cpu_to_le_16(dst_id);
5004 if (filter->ip_addr_type) {
5005 req.ip_addr_type = filter->ip_addr_type;
5007 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
5010 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
5011 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
5013 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
5014 memcpy(req.src_macaddr, filter->src_macaddr,
5015 RTE_ETHER_ADDR_LEN);
5017 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
5018 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
5020 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
5021 req.ip_protocol = filter->ip_protocol;
5023 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
5024 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
5026 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
5027 req.src_ipaddr_mask[0] =
5028 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
5030 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
5031 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
5033 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
5034 req.dst_ipaddr_mask[0] =
5035 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
5037 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
5038 req.src_port = rte_cpu_to_le_16(filter->src_port);
5040 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
5041 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
5043 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
5044 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
5046 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
5047 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
5049 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
5050 req.mirror_vnic_id = filter->mirror_vnic_id;
5052 req.enables = rte_cpu_to_le_32(enables);
5054 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5056 HWRM_CHECK_RESULT();
5058 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
5059 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
5065 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
5066 struct bnxt_filter_info *filter)
5069 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
5070 struct hwrm_cfa_ntuple_filter_free_output *resp =
5071 bp->hwrm_cmd_resp_addr;
5073 if (filter->fw_ntuple_filter_id == UINT64_MAX)
5076 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
5078 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
5080 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5082 HWRM_CHECK_RESULT();
5085 filter->fw_ntuple_filter_id = UINT64_MAX;
5091 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5093 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5094 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
5095 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
5096 struct bnxt_rx_queue **rxqs = bp->rx_queues;
5097 uint16_t *ring_tbl = vnic->rss_table;
5098 int nr_ctxs = vnic->num_lb_ctxts;
5099 int max_rings = bp->rx_nr_rings;
5103 for (i = 0, k = 0; i < nr_ctxs; i++) {
5104 struct bnxt_rx_ring_info *rxr;
5105 struct bnxt_cp_ring_info *cpr;
5107 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5109 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5110 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5111 req.hash_mode_flags = vnic->hash_mode;
5113 req.ring_grp_tbl_addr =
5114 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5115 i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5116 2 * sizeof(*ring_tbl));
5117 req.hash_key_tbl_addr =
5118 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5120 req.ring_table_pair_index = i;
5121 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5123 for (j = 0; j < 64; j++) {
5126 /* Find next active ring. */
5127 for (cnt = 0; cnt < max_rings; cnt++) {
5128 if (rx_queue_state[k] !=
5129 RTE_ETH_QUEUE_STATE_STOPPED)
5131 if (++k == max_rings)
5135 /* Return if no rings are active. */
5136 if (cnt == max_rings) {
5141 /* Add rx/cp ring pair to RSS table. */
5142 rxr = rxqs[k]->rx_ring;
5143 cpr = rxqs[k]->cp_ring;
5145 ring_id = rxr->rx_ring_struct->fw_ring_id;
5146 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5147 ring_id = cpr->cp_ring_struct->fw_ring_id;
5148 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5150 if (++k == max_rings)
5153 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5156 HWRM_CHECK_RESULT();
5163 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5165 unsigned int rss_idx, fw_idx, i;
5167 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5170 if (!(vnic->rss_table && vnic->hash_type))
5173 if (BNXT_CHIP_P5(bp))
5174 return bnxt_vnic_rss_configure_p5(bp, vnic);
5177 * Fill the RSS hash & redirection table with
5178 * ring group ids for all VNICs
5180 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5181 rss_idx++, fw_idx++) {
5182 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5183 fw_idx %= bp->rx_cp_nr_rings;
5184 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5189 if (i == bp->rx_cp_nr_rings)
5192 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5195 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5198 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5199 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5203 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5205 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5206 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5208 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5209 req->num_cmpl_dma_aggr_during_int =
5210 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5212 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5214 /* min timer set to 1/2 of interrupt timer */
5215 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5217 /* buf timer set to 1/4 of interrupt timer */
5218 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5220 req->cmpl_aggr_dma_tmr_during_int =
5221 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5223 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5224 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5225 req->flags = rte_cpu_to_le_16(flags);
5228 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5229 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5231 struct hwrm_ring_aggint_qcaps_input req = {0};
5232 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5237 HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5238 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5239 HWRM_CHECK_RESULT();
5241 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5242 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5244 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5245 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5246 agg_req->flags = rte_cpu_to_le_16(flags);
5248 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5249 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5250 agg_req->enables = rte_cpu_to_le_32(enables);
5256 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5257 struct bnxt_coal *coal, uint16_t ring_id)
5259 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5260 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5261 bp->hwrm_cmd_resp_addr;
5264 /* Set ring coalesce parameters only for 100G NICs */
5265 if (BNXT_CHIP_P5(bp)) {
5266 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5268 } else if (bnxt_stratus_device(bp)) {
5269 bnxt_hwrm_set_coal_params(coal, &req);
5275 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5277 req.ring_id = rte_cpu_to_le_16(ring_id);
5278 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5279 HWRM_CHECK_RESULT();
5284 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5285 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5287 struct hwrm_func_backing_store_qcaps_input req = {0};
5288 struct hwrm_func_backing_store_qcaps_output *resp =
5289 bp->hwrm_cmd_resp_addr;
5290 struct bnxt_ctx_pg_info *ctx_pg;
5291 struct bnxt_ctx_mem_info *ctx;
5292 int total_alloc_len;
5293 int rc, i, tqm_rings;
5295 if (!BNXT_CHIP_P5(bp) ||
5296 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5301 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5302 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5303 HWRM_CHECK_RESULT_SILENT();
5305 total_alloc_len = sizeof(*ctx);
5306 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5307 RTE_CACHE_LINE_SIZE);
5313 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5314 ctx->qp_min_qp1_entries =
5315 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5316 ctx->qp_max_l2_entries =
5317 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5318 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5319 ctx->srq_max_l2_entries =
5320 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5321 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5322 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5323 ctx->cq_max_l2_entries =
5324 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5325 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5326 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5327 ctx->vnic_max_vnic_entries =
5328 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5329 ctx->vnic_max_ring_table_entries =
5330 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5331 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5332 ctx->stat_max_entries =
5333 rte_le_to_cpu_32(resp->stat_max_entries);
5334 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5335 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5336 ctx->tqm_min_entries_per_ring =
5337 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5338 ctx->tqm_max_entries_per_ring =
5339 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5340 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5341 if (!ctx->tqm_entries_multiple)
5342 ctx->tqm_entries_multiple = 1;
5343 ctx->mrav_max_entries =
5344 rte_le_to_cpu_32(resp->mrav_max_entries);
5345 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5346 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5347 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5348 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5350 ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5351 RTE_MIN(ctx->tqm_fp_rings_count,
5352 BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5355 /* Check if the ext ring count needs to be counted.
5356 * Ext ring count is available only with new FW so we should not
5357 * look at the field on older FW.
5359 if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5360 bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5361 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5362 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5363 ctx->tqm_fp_rings_count);
5366 tqm_rings = ctx->tqm_fp_rings_count + 1;
5368 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5369 sizeof(*ctx_pg) * tqm_rings,
5370 RTE_CACHE_LINE_SIZE);
5375 for (i = 0; i < tqm_rings; i++, ctx_pg++)
5376 ctx->tqm_mem[i] = ctx_pg;
5384 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5386 struct hwrm_func_backing_store_cfg_input req = {0};
5387 struct hwrm_func_backing_store_cfg_output *resp =
5388 bp->hwrm_cmd_resp_addr;
5389 struct bnxt_ctx_mem_info *ctx = bp->ctx;
5390 struct bnxt_ctx_pg_info *ctx_pg;
5391 uint32_t *num_entries;
5400 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5401 req.enables = rte_cpu_to_le_32(enables);
5403 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5404 ctx_pg = &ctx->qp_mem;
5405 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5406 req.qp_num_qp1_entries =
5407 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5408 req.qp_num_l2_entries =
5409 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5410 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5411 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5412 &req.qpc_pg_size_qpc_lvl,
5416 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5417 ctx_pg = &ctx->srq_mem;
5418 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5419 req.srq_num_l2_entries =
5420 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5421 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5422 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5423 &req.srq_pg_size_srq_lvl,
5427 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5428 ctx_pg = &ctx->cq_mem;
5429 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5430 req.cq_num_l2_entries =
5431 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5432 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5433 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5434 &req.cq_pg_size_cq_lvl,
5438 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5439 ctx_pg = &ctx->vnic_mem;
5440 req.vnic_num_vnic_entries =
5441 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5442 req.vnic_num_ring_table_entries =
5443 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5444 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5445 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5446 &req.vnic_pg_size_vnic_lvl,
5447 &req.vnic_page_dir);
5450 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5451 ctx_pg = &ctx->stat_mem;
5452 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5453 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5454 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5455 &req.stat_pg_size_stat_lvl,
5456 &req.stat_page_dir);
5459 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5460 num_entries = &req.tqm_sp_num_entries;
5461 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5462 pg_dir = &req.tqm_sp_page_dir;
5463 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5464 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5465 if (!(enables & ena))
5468 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5470 ctx_pg = ctx->tqm_mem[i];
5471 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5472 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5475 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5476 /* DPDK does not need to configure MRAV and TIM type.
5477 * So we are skipping over MRAV and TIM. Skip to configure
5478 * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5480 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5481 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5482 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5483 &req.tqm_ring8_pg_size_tqm_ring_lvl,
5484 &req.tqm_ring8_page_dir);
5487 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5488 HWRM_CHECK_RESULT();
5494 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5496 struct hwrm_port_qstats_ext_input req = {0};
5497 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5498 struct bnxt_pf_info *pf = bp->pf;
5501 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5502 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5505 HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5507 req.port_id = rte_cpu_to_le_16(pf->port_id);
5508 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5509 req.tx_stat_host_addr =
5510 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5512 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5514 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5515 req.rx_stat_host_addr =
5516 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5518 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5520 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5523 bp->fw_rx_port_stats_ext_size = 0;
5524 bp->fw_tx_port_stats_ext_size = 0;
5526 bp->fw_rx_port_stats_ext_size =
5527 rte_le_to_cpu_16(resp->rx_stat_size);
5528 bp->fw_tx_port_stats_ext_size =
5529 rte_le_to_cpu_16(resp->tx_stat_size);
5532 HWRM_CHECK_RESULT();
5539 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5541 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5542 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5543 bp->hwrm_cmd_resp_addr;
5546 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5547 req.tunnel_type = type;
5548 req.dest_fid = bp->fw_fid;
5549 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5550 HWRM_CHECK_RESULT();
5558 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5560 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5561 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5562 bp->hwrm_cmd_resp_addr;
5565 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5566 req.tunnel_type = type;
5567 req.dest_fid = bp->fw_fid;
5568 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5569 HWRM_CHECK_RESULT();
5576 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5578 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5579 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5580 bp->hwrm_cmd_resp_addr;
5583 HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5584 req.src_fid = bp->fw_fid;
5585 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5586 HWRM_CHECK_RESULT();
5589 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5596 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5599 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5600 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5601 bp->hwrm_cmd_resp_addr;
5604 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5605 req.src_fid = bp->fw_fid;
5606 req.tunnel_type = tun_type;
5607 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5608 HWRM_CHECK_RESULT();
5611 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5613 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5620 int bnxt_hwrm_set_mac(struct bnxt *bp)
5622 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5623 struct hwrm_func_vf_cfg_input req = {0};
5629 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5632 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5633 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5635 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5637 HWRM_CHECK_RESULT();
5644 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5646 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5647 struct hwrm_func_drv_if_change_input req = {0};
5651 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5654 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5655 * If we issue FUNC_DRV_IF_CHANGE with flags down before
5656 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5658 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5661 HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5665 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5667 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5669 HWRM_CHECK_RESULT();
5670 flags = rte_le_to_cpu_32(resp->flags);
5676 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5677 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5678 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5684 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5686 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5687 struct bnxt_error_recovery_info *info = bp->recovery_info;
5688 struct hwrm_error_recovery_qcfg_input req = {0};
5693 /* Older FW does not have error recovery support */
5694 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5697 HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5699 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5701 HWRM_CHECK_RESULT();
5703 flags = rte_le_to_cpu_32(resp->flags);
5704 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5705 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5706 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5707 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5709 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5710 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5715 /* FW returned values are in units of 100msec */
5716 info->driver_polling_freq =
5717 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5718 info->master_func_wait_period =
5719 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5720 info->normal_func_wait_period =
5721 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5722 info->master_func_wait_period_after_reset =
5723 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5724 info->max_bailout_time_after_reset =
5725 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5726 info->status_regs[BNXT_FW_STATUS_REG] =
5727 rte_le_to_cpu_32(resp->fw_health_status_reg);
5728 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5729 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5730 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5731 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5732 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5733 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5734 info->reg_array_cnt =
5735 rte_le_to_cpu_32(resp->reg_array_cnt);
5737 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5742 for (i = 0; i < info->reg_array_cnt; i++) {
5743 info->reset_reg[i] =
5744 rte_le_to_cpu_32(resp->reset_reg[i]);
5745 info->reset_reg_val[i] =
5746 rte_le_to_cpu_32(resp->reset_reg_val[i]);
5747 info->delay_after_reset[i] =
5748 resp->delay_after_reset[i];
5753 /* Map the FW status registers */
5755 rc = bnxt_map_fw_health_status_regs(bp);
5758 rte_free(bp->recovery_info);
5759 bp->recovery_info = NULL;
5764 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5766 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5767 struct hwrm_fw_reset_input req = {0};
5773 HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5775 req.embedded_proc_type =
5776 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5777 req.selfrst_status =
5778 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5779 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5781 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5784 HWRM_CHECK_RESULT();
5790 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5792 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5793 struct hwrm_port_ts_query_input req = {0};
5794 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5801 HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5804 case BNXT_PTP_FLAGS_PATH_TX:
5805 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5807 case BNXT_PTP_FLAGS_PATH_RX:
5808 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5810 case BNXT_PTP_FLAGS_CURRENT_TIME:
5811 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5815 req.flags = rte_cpu_to_le_32(flags);
5816 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5818 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5820 HWRM_CHECK_RESULT();
5823 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5825 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5832 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5836 struct hwrm_cfa_counter_qcaps_input req = {0};
5837 struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5839 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5841 "Not a PF or trusted VF. Command not supported\n");
5845 HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5846 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5847 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5849 HWRM_CHECK_RESULT();
5851 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5857 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5860 struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5861 struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5863 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5865 "Not a PF or trusted VF. Command not supported\n");
5869 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5871 req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5872 req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5873 req.page_dir = rte_cpu_to_le_64(dma_addr);
5875 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5877 HWRM_CHECK_RESULT();
5879 *ctx_id = rte_le_to_cpu_16(resp->ctx_id);
5880 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5887 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5890 struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5891 struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5893 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5895 "Not a PF or trusted VF. Command not supported\n");
5899 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5901 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5903 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5905 HWRM_CHECK_RESULT();
5911 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5912 uint16_t cntr, uint16_t ctx_id,
5913 uint32_t num_entries, bool enable)
5915 struct hwrm_cfa_counter_cfg_input req = {0};
5916 struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5920 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5922 "Not a PF or trusted VF. Command not supported\n");
5926 HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5928 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5929 req.counter_type = rte_cpu_to_le_16(cntr);
5930 flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5931 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5932 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5933 if (dir == BNXT_DIR_RX)
5934 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5935 else if (dir == BNXT_DIR_TX)
5936 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5937 req.flags = rte_cpu_to_le_16(flags);
5938 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5939 req.num_entries = rte_cpu_to_le_32(num_entries);
5941 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5942 HWRM_CHECK_RESULT();
5948 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5949 enum bnxt_flow_dir dir,
5951 uint16_t num_entries)
5953 struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5954 struct hwrm_cfa_counter_qstats_input req = {0};
5955 uint16_t flow_ctx_id = 0;
5959 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5961 "Not a PF or trusted VF. Command not supported\n");
5965 if (dir == BNXT_DIR_RX) {
5966 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5967 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5968 } else if (dir == BNXT_DIR_TX) {
5969 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5970 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5973 HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5974 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5975 req.counter_type = rte_cpu_to_le_16(cntr);
5976 req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5977 req.num_entries = rte_cpu_to_le_16(num_entries);
5978 req.flags = rte_cpu_to_le_16(flags);
5979 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5981 HWRM_CHECK_RESULT();
5987 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5988 uint16_t *first_vf_id)
5991 struct hwrm_func_qcaps_input req = {.req_type = 0 };
5992 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5994 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5996 req.fid = rte_cpu_to_le_16(fid);
5998 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6000 HWRM_CHECK_RESULT();
6003 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
6010 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
6012 struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6013 struct hwrm_cfa_pair_alloc_input req = {0};
6016 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6018 "Not a PF or trusted VF. Command not supported\n");
6022 HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
6023 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6024 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6025 bp->eth_dev->data->name, rep_bp->vf_id);
6027 req.pf_b_id = rep_bp->parent_pf_idx;
6028 req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6029 rte_cpu_to_le_16(rep_bp->vf_id);
6030 req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
6031 req.host_b_id = 1; /* TBD - Confirm if this is OK */
6033 req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
6034 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
6035 req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
6036 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
6037 req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
6038 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
6039 req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
6040 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
6042 req.q_ab = rep_bp->rep_q_r2f;
6043 req.q_ba = rep_bp->rep_q_f2r;
6044 req.fc_ab = rep_bp->rep_fc_r2f;
6045 req.fc_ba = rep_bp->rep_fc_f2r;
6047 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6048 HWRM_CHECK_RESULT();
6051 PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
6052 BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
6056 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
6058 struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
6059 struct hwrm_cfa_pair_free_input req = {0};
6062 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6064 "Not a PF or trusted VF. Command not supported\n");
6068 HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
6069 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6070 bp->eth_dev->data->name, rep_bp->vf_id);
6071 req.pf_b_id = rep_bp->parent_pf_idx;
6072 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6073 req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6074 rte_cpu_to_le_16(rep_bp->vf_id);
6075 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6076 HWRM_CHECK_RESULT();
6078 PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
6083 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
6085 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
6086 bp->hwrm_cmd_resp_addr;
6087 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
6091 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
6094 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6096 "Not a PF or trusted VF. Command not supported\n");
6100 HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
6101 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6103 HWRM_CHECK_RESULT();
6104 flags = rte_le_to_cpu_32(resp->flags);
6107 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
6108 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
6110 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
6115 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6116 uint32_t echo_req_data2)
6118 struct hwrm_func_echo_response_input req = {0};
6119 struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6122 HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6123 req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6124 req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6126 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6128 HWRM_CHECK_RESULT();
6134 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6136 struct hwrm_ver_get_input req = {.req_type = 0 };
6137 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6140 bp->max_req_len = HWRM_MAX_REQ_LEN;
6141 bp->max_resp_len = BNXT_PAGE_SIZE;
6142 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6144 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6145 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6146 req.hwrm_intf_min = HWRM_VERSION_MINOR;
6147 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6149 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6151 HWRM_CHECK_RESULT_SILENT();
6153 if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)