1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SHORT_CMD_TIMEOUT 50000
31 #define HWRM_SPEC_CODE_1_8_3 0x10803
32 #define HWRM_VERSION_1_9_1 0x10901
33 #define HWRM_VERSION_1_9_2 0x10903
35 struct bnxt_plcmodes_cfg {
37 uint16_t jumbo_thresh;
39 uint16_t hds_threshold;
42 static int page_getenum(size_t size)
58 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
59 return sizeof(void *) * 8 - 1;
62 static int page_roundup(size_t size)
64 return 1 << page_getenum(size);
67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
71 if (rmem->nr_pages > 1) {
73 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
75 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
80 * HWRM Functions (sent to HWRM)
81 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
82 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
83 * command was failed by the ChiMP.
86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
87 uint32_t msg_len, bool use_kong_mb)
90 struct input *req = msg;
91 struct output *resp = bp->hwrm_cmd_resp_addr;
95 uint16_t max_req_len = bp->max_req_len;
96 struct hwrm_short_input short_input = { 0 };
97 uint16_t bar_offset = use_kong_mb ?
98 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
99 uint16_t mb_trigger_offset = use_kong_mb ?
100 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
103 /* Do not send HWRM commands to firmware in error state */
104 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
107 /* For VER_GET command, set timeout as 50ms */
108 if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
109 timeout = HWRM_SHORT_CMD_TIMEOUT;
111 timeout = HWRM_CMD_TIMEOUT;
113 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
114 msg_len > bp->max_req_len) {
115 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
117 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
118 memcpy(short_cmd_req, req, msg_len);
120 short_input.req_type = rte_cpu_to_le_16(req->req_type);
121 short_input.signature = rte_cpu_to_le_16(
122 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
123 short_input.size = rte_cpu_to_le_16(msg_len);
124 short_input.req_addr =
125 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
127 data = (uint32_t *)&short_input;
128 msg_len = sizeof(short_input);
130 /* Sync memory write before updating doorbell */
133 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
136 /* Write request msg to hwrm channel */
137 for (i = 0; i < msg_len; i += 4) {
138 bar = (uint8_t *)bp->bar0 + bar_offset + i;
139 rte_write32(*data, bar);
143 /* Zero the rest of the request space */
144 for (; i < max_req_len; i += 4) {
145 bar = (uint8_t *)bp->bar0 + bar_offset + i;
149 /* Ring channel doorbell */
150 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
153 /* Poll for the valid bit */
154 for (i = 0; i < timeout; i++) {
155 /* Sanity check on the resp->resp_len */
157 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
158 /* Last byte of resp contains the valid key */
159 valid = (uint8_t *)resp + resp->resp_len - 1;
160 if (*valid == HWRM_RESP_VALID_KEY)
167 /* Suppress VER_GET timeout messages during reset recovery */
168 if (bp->flags & BNXT_FLAG_FW_RESET &&
169 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
172 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
180 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
181 * spinlock, and does initial processing.
183 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
184 * releases the spinlock only if it returns. If the regular int return codes
185 * are not used by the function, HWRM_CHECK_RESULT() should not be used
186 * directly, rather it should be copied and modified to suit the function.
188 * HWRM_UNLOCK() must be called after all response processing is completed.
190 #define HWRM_PREP(req, type, kong) do { \
191 rte_spinlock_lock(&bp->hwrm_lock); \
192 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
193 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
194 req.cmpl_ring = rte_cpu_to_le_16(-1); \
195 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
196 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
197 req.target_id = rte_cpu_to_le_16(0xffff); \
198 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
201 #define HWRM_CHECK_RESULT_SILENT() do {\
203 rte_spinlock_unlock(&bp->hwrm_lock); \
206 if (resp->error_code) { \
207 rc = rte_le_to_cpu_16(resp->error_code); \
208 rte_spinlock_unlock(&bp->hwrm_lock); \
213 #define HWRM_CHECK_RESULT() do {\
215 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
216 rte_spinlock_unlock(&bp->hwrm_lock); \
217 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
223 if (resp->error_code) { \
224 rc = rte_le_to_cpu_16(resp->error_code); \
225 if (resp->resp_len >= 16) { \
226 struct hwrm_err_output *tmp_hwrm_err_op = \
229 "error %d:%d:%08x:%04x\n", \
230 rc, tmp_hwrm_err_op->cmd_err, \
232 tmp_hwrm_err_op->opaque_0), \
234 tmp_hwrm_err_op->opaque_1)); \
236 PMD_DRV_LOG(ERR, "error %d\n", rc); \
238 rte_spinlock_unlock(&bp->hwrm_lock); \
239 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
247 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
249 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
252 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
253 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
255 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
256 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
259 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
267 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
268 struct bnxt_vnic_info *vnic,
270 struct bnxt_vlan_table_entry *vlan_table)
273 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
274 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
277 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
280 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
281 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
283 /* FIXME add multicast flag, when multicast adding options is supported
286 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
287 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
288 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
289 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
290 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
291 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
292 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
293 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
294 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
295 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
296 if (vnic->mc_addr_cnt) {
297 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
298 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
299 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
302 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
303 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
304 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
305 rte_mem_virt2iova(vlan_table));
306 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
308 req.mask = rte_cpu_to_le_32(mask);
310 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
318 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
320 struct bnxt_vlan_antispoof_table_entry *vlan_table)
323 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
324 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
325 bp->hwrm_cmd_resp_addr;
328 * Older HWRM versions did not support this command, and the set_rx_mask
329 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
330 * removed from set_rx_mask call, and this command was added.
332 * This command is also present from 1.7.8.11 and higher,
335 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
336 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
337 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
342 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
343 req.fid = rte_cpu_to_le_16(fid);
345 req.vlan_tag_mask_tbl_addr =
346 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
347 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
349 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
357 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
358 struct bnxt_filter_info *filter)
361 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
362 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
364 if (filter->fw_l2_filter_id == UINT64_MAX)
367 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
369 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
371 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
376 filter->fw_l2_filter_id = UINT64_MAX;
381 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
383 struct bnxt_filter_info *filter)
386 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
387 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
388 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
389 const struct rte_eth_vmdq_rx_conf *conf =
390 &dev_conf->rx_adv_conf.vmdq_rx_conf;
391 uint32_t enables = 0;
392 uint16_t j = dst_id - 1;
394 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
395 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
396 conf->pool_map[j].pools & (1UL << j)) {
398 "Add vlan %u to vmdq pool %u\n",
399 conf->pool_map[j].vlan_id, j);
401 filter->l2_ivlan = conf->pool_map[j].vlan_id;
403 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
404 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
407 if (filter->fw_l2_filter_id != UINT64_MAX)
408 bnxt_hwrm_clear_l2_filter(bp, filter);
410 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
412 req.flags = rte_cpu_to_le_32(filter->flags);
414 rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
416 enables = filter->enables |
417 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
418 req.dst_id = rte_cpu_to_le_16(dst_id);
421 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
422 memcpy(req.l2_addr, filter->l2_addr,
425 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
426 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
429 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
430 req.l2_ovlan = filter->l2_ovlan;
432 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
433 req.l2_ivlan = filter->l2_ivlan;
435 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
436 req.l2_ovlan_mask = filter->l2_ovlan_mask;
438 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
439 req.l2_ivlan_mask = filter->l2_ivlan_mask;
440 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
441 req.src_id = rte_cpu_to_le_32(filter->src_id);
442 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
443 req.src_type = filter->src_type;
445 req.enables = rte_cpu_to_le_32(enables);
447 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
451 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
457 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
459 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
460 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
467 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
470 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
473 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
474 if (ptp->tx_tstamp_en)
475 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
478 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
479 req.flags = rte_cpu_to_le_32(flags);
480 req.enables = rte_cpu_to_le_32
481 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
482 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
484 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
490 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
493 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
494 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
495 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
497 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
501 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
503 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
505 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
509 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
512 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
516 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
517 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
518 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
519 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
520 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
521 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
522 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
523 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
524 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
525 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
526 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
527 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
528 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
529 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
530 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
531 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
532 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
533 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
541 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
544 struct hwrm_func_qcaps_input req = {.req_type = 0 };
545 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
546 uint16_t new_max_vfs;
550 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
552 req.fid = rte_cpu_to_le_16(0xffff);
554 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
558 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
559 flags = rte_le_to_cpu_32(resp->flags);
561 bp->pf.port_id = resp->port_id;
562 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
563 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
564 new_max_vfs = bp->pdev->max_vfs;
565 if (new_max_vfs != bp->pf.max_vfs) {
567 rte_free(bp->pf.vf_info);
568 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
569 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
570 bp->pf.max_vfs = new_max_vfs;
571 for (i = 0; i < new_max_vfs; i++) {
572 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
573 bp->pf.vf_info[i].vlan_table =
574 rte_zmalloc("VF VLAN table",
577 if (bp->pf.vf_info[i].vlan_table == NULL)
579 "Fail to alloc VLAN table for VF %d\n",
583 bp->pf.vf_info[i].vlan_table);
584 bp->pf.vf_info[i].vlan_as_table =
585 rte_zmalloc("VF VLAN AS table",
588 if (bp->pf.vf_info[i].vlan_as_table == NULL)
590 "Alloc VLAN AS table for VF %d fail\n",
594 bp->pf.vf_info[i].vlan_as_table);
595 STAILQ_INIT(&bp->pf.vf_info[i].filter);
600 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
601 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
602 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
603 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
604 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
605 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
606 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
607 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
609 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
610 /* TODO: For now, do not support VMDq/RFS on VFs. */
615 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
619 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
621 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
622 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
623 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
624 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
626 bnxt_hwrm_ptp_qcfg(bp);
630 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
631 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
638 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
642 rc = __bnxt_hwrm_func_qcaps(bp);
643 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
644 rc = bnxt_alloc_ctx_mem(bp);
648 rc = bnxt_hwrm_func_resc_qcaps(bp);
650 bp->flags |= BNXT_FLAG_NEW_RM;
656 int bnxt_hwrm_func_reset(struct bnxt *bp)
659 struct hwrm_func_reset_input req = {.req_type = 0 };
660 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
662 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
664 req.enables = rte_cpu_to_le_32(0);
666 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
674 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
678 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
679 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
681 if (bp->flags & BNXT_FLAG_REGISTERED)
684 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
686 /* PFs and trusted VFs should indicate the support of the
687 * Master capability on non Stingray platform
689 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
690 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
692 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
693 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
694 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
695 req.ver_maj = RTE_VER_YEAR;
696 req.ver_min = RTE_VER_MONTH;
697 req.ver_upd = RTE_VER_MINOR;
700 req.enables |= rte_cpu_to_le_32(
701 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
702 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
703 RTE_MIN(sizeof(req.vf_req_fwd),
704 sizeof(bp->pf.vf_req_fwd)));
707 * PF can sniff HWRM API issued by VF. This can be set up by
708 * linux driver and inherited by the DPDK PF driver. Clear
709 * this HWRM sniffer list in FW because DPDK PF driver does
712 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
715 req.flags = rte_cpu_to_le_32(flags);
717 req.async_event_fwd[0] |=
718 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
719 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
720 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
721 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
722 req.async_event_fwd[1] |=
723 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
724 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
726 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
731 bp->flags |= BNXT_FLAG_REGISTERED;
736 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
738 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
741 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
744 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
749 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
750 struct hwrm_func_vf_cfg_input req = {0};
752 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
754 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
755 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
756 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
757 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
758 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
760 if (BNXT_HAS_RING_GRPS(bp)) {
761 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
762 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
765 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
766 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
767 AGG_RING_MULTIPLIER);
768 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
770 BNXT_NUM_ASYNC_CPR(bp));
771 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
773 BNXT_NUM_ASYNC_CPR(bp));
774 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
775 if (bp->vf_resv_strategy ==
776 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
777 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
778 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
779 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
780 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
781 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
782 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
786 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
787 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
788 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
789 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
790 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
791 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
793 if (test && BNXT_HAS_RING_GRPS(bp))
794 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
796 req.flags = rte_cpu_to_le_32(flags);
797 req.enables |= rte_cpu_to_le_32(enables);
799 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
802 HWRM_CHECK_RESULT_SILENT();
810 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
813 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
814 struct hwrm_func_resource_qcaps_input req = {0};
816 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
817 req.fid = rte_cpu_to_le_16(0xffff);
819 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
824 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
825 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
826 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
827 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
828 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
829 /* func_resource_qcaps does not return max_rx_em_flows.
830 * So use the value provided by func_qcaps.
833 rte_le_to_cpu_16(resp->max_l2_ctxs) +
835 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
836 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
838 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
839 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
840 if (bp->vf_resv_strategy >
841 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
842 bp->vf_resv_strategy =
843 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
849 int bnxt_hwrm_ver_get(struct bnxt *bp)
852 struct hwrm_ver_get_input req = {.req_type = 0 };
853 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
855 uint16_t max_resp_len;
856 char type[RTE_MEMZONE_NAMESIZE];
857 uint32_t dev_caps_cfg;
859 bp->max_req_len = HWRM_MAX_REQ_LEN;
860 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
862 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
863 req.hwrm_intf_min = HWRM_VERSION_MINOR;
864 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
866 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
868 if (bp->flags & BNXT_FLAG_FW_RESET)
869 HWRM_CHECK_RESULT_SILENT();
873 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
874 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
875 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
876 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
877 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
878 (resp->hwrm_fw_min_8b << 16) |
879 (resp->hwrm_fw_bld_8b << 8) |
880 resp->hwrm_fw_rsvd_8b;
881 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
882 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
884 fw_version = resp->hwrm_intf_maj_8b << 16;
885 fw_version |= resp->hwrm_intf_min_8b << 8;
886 fw_version |= resp->hwrm_intf_upd_8b;
887 bp->hwrm_spec_code = fw_version;
889 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
890 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
895 if (bp->max_req_len > resp->max_req_win_len) {
896 PMD_DRV_LOG(ERR, "Unsupported request length\n");
899 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
900 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
901 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
902 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
904 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
905 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
907 if (bp->max_resp_len != max_resp_len) {
908 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
909 bp->pdev->addr.domain, bp->pdev->addr.bus,
910 bp->pdev->addr.devid, bp->pdev->addr.function);
912 rte_free(bp->hwrm_cmd_resp_addr);
914 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
915 if (bp->hwrm_cmd_resp_addr == NULL) {
919 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
920 bp->hwrm_cmd_resp_dma_addr =
921 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
922 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
924 "Unable to map response buffer to physical memory.\n");
928 bp->max_resp_len = max_resp_len;
932 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
934 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
935 PMD_DRV_LOG(DEBUG, "Short command supported\n");
936 bp->flags |= BNXT_FLAG_SHORT_CMD;
940 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
942 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
943 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
944 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
945 bp->pdev->addr.domain, bp->pdev->addr.bus,
946 bp->pdev->addr.devid, bp->pdev->addr.function);
948 rte_free(bp->hwrm_short_cmd_req_addr);
950 bp->hwrm_short_cmd_req_addr =
951 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
952 if (bp->hwrm_short_cmd_req_addr == NULL) {
956 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
957 bp->hwrm_short_cmd_req_dma_addr =
958 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
959 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
960 rte_free(bp->hwrm_short_cmd_req_addr);
962 "Unable to map buffer to physical memory.\n");
968 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
969 bp->flags |= BNXT_FLAG_KONG_MB_EN;
970 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
973 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
974 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
981 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
984 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
985 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
987 if (!(bp->flags & BNXT_FLAG_REGISTERED))
990 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
993 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1001 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1004 struct hwrm_port_phy_cfg_input req = {0};
1005 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1006 uint32_t enables = 0;
1008 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1010 if (conf->link_up) {
1011 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1012 if (bp->link_info.auto_mode && conf->link_speed) {
1013 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1014 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1017 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1018 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1019 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1021 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1022 * any auto mode, even "none".
1024 if (!conf->link_speed) {
1025 /* No speeds specified. Enable AutoNeg - all speeds */
1027 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1029 /* AutoNeg - Advertise speeds specified. */
1030 if (conf->auto_link_speed_mask &&
1031 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1033 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1034 req.auto_link_speed_mask =
1035 conf->auto_link_speed_mask;
1037 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1040 req.auto_duplex = conf->duplex;
1041 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1042 req.auto_pause = conf->auto_pause;
1043 req.force_pause = conf->force_pause;
1044 /* Set force_pause if there is no auto or if there is a force */
1045 if (req.auto_pause && !req.force_pause)
1046 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1048 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1050 req.enables = rte_cpu_to_le_32(enables);
1053 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1054 PMD_DRV_LOG(INFO, "Force Link Down\n");
1057 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1059 HWRM_CHECK_RESULT();
1065 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1066 struct bnxt_link_info *link_info)
1069 struct hwrm_port_phy_qcfg_input req = {0};
1070 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1072 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1074 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1076 HWRM_CHECK_RESULT();
1078 link_info->phy_link_status = resp->link;
1079 link_info->link_up =
1080 (link_info->phy_link_status ==
1081 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1082 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1083 link_info->duplex = resp->duplex_cfg;
1084 link_info->pause = resp->pause;
1085 link_info->auto_pause = resp->auto_pause;
1086 link_info->force_pause = resp->force_pause;
1087 link_info->auto_mode = resp->auto_mode;
1088 link_info->phy_type = resp->phy_type;
1089 link_info->media_type = resp->media_type;
1091 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1092 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1093 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1094 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1095 link_info->phy_ver[0] = resp->phy_maj;
1096 link_info->phy_ver[1] = resp->phy_min;
1097 link_info->phy_ver[2] = resp->phy_bld;
1101 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1102 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1103 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1104 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1105 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1106 link_info->auto_link_speed_mask);
1107 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1108 link_info->force_link_speed);
1113 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1116 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1117 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1120 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1122 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1123 /* HWRM Version >= 1.9.1 */
1124 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1126 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1127 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1129 HWRM_CHECK_RESULT();
1131 #define GET_QUEUE_INFO(x) \
1132 bp->cos_queue[x].id = resp->queue_id##x; \
1133 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1146 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1147 bp->tx_cosq_id = bp->cos_queue[0].id;
1149 /* iterate and find the COSq profile to use for Tx */
1150 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1151 if (bp->cos_queue[i].profile ==
1152 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1153 bp->tx_cosq_id = bp->cos_queue[i].id;
1159 bp->max_tc = resp->max_configurable_queues;
1160 bp->max_lltc = resp->max_configurable_lossless_queues;
1161 if (bp->max_tc > BNXT_MAX_QUEUE)
1162 bp->max_tc = BNXT_MAX_QUEUE;
1163 bp->max_q = bp->max_tc;
1165 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1170 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1171 struct bnxt_ring *ring,
1172 uint32_t ring_type, uint32_t map_index,
1173 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1176 uint32_t enables = 0;
1177 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1178 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1179 struct rte_mempool *mb_pool;
1180 uint16_t rx_buf_size;
1182 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1184 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1185 req.fbo = rte_cpu_to_le_32(0);
1186 /* Association of ring index with doorbell index */
1187 req.logical_id = rte_cpu_to_le_16(map_index);
1188 req.length = rte_cpu_to_le_32(ring->ring_size);
1190 switch (ring_type) {
1191 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1192 req.ring_type = ring_type;
1193 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1194 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1195 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1196 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1198 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1200 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1201 req.ring_type = ring_type;
1202 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1203 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1204 if (BNXT_CHIP_THOR(bp)) {
1205 mb_pool = bp->rx_queues[0]->mb_pool;
1206 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1207 RTE_PKTMBUF_HEADROOM;
1208 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1210 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1212 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1214 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1216 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1217 req.ring_type = ring_type;
1218 if (BNXT_HAS_NQ(bp)) {
1219 /* Association of cp ring with nq */
1220 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1222 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1224 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1226 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1227 req.ring_type = ring_type;
1228 req.page_size = BNXT_PAGE_SHFT;
1229 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1231 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1232 req.ring_type = ring_type;
1233 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1235 mb_pool = bp->rx_queues[0]->mb_pool;
1236 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1237 RTE_PKTMBUF_HEADROOM;
1238 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1240 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1241 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1242 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1243 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1246 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1251 req.enables = rte_cpu_to_le_32(enables);
1253 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1255 if (rc || resp->error_code) {
1256 if (rc == 0 && resp->error_code)
1257 rc = rte_le_to_cpu_16(resp->error_code);
1258 switch (ring_type) {
1259 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1261 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1264 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1266 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1269 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1271 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1275 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1277 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1280 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1282 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1286 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1292 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1297 int bnxt_hwrm_ring_free(struct bnxt *bp,
1298 struct bnxt_ring *ring, uint32_t ring_type)
1301 struct hwrm_ring_free_input req = {.req_type = 0 };
1302 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1304 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1306 req.ring_type = ring_type;
1307 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1309 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1311 if (rc || resp->error_code) {
1312 if (rc == 0 && resp->error_code)
1313 rc = rte_le_to_cpu_16(resp->error_code);
1316 switch (ring_type) {
1317 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1318 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1321 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1322 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1325 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1326 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1329 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1331 "hwrm_ring_free nq failed. rc:%d\n", rc);
1333 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1335 "hwrm_ring_free agg failed. rc:%d\n", rc);
1338 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1346 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1349 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1350 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1352 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1354 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1355 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1356 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1357 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1359 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1361 HWRM_CHECK_RESULT();
1363 bp->grp_info[idx].fw_grp_id =
1364 rte_le_to_cpu_16(resp->ring_group_id);
1371 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1374 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1375 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1377 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1379 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1381 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1383 HWRM_CHECK_RESULT();
1386 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1390 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1393 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1394 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1396 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1399 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1401 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1403 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1405 HWRM_CHECK_RESULT();
1411 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1412 unsigned int idx __rte_unused)
1415 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1416 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1418 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1420 req.update_period_ms = rte_cpu_to_le_32(0);
1422 req.stats_dma_addr =
1423 rte_cpu_to_le_64(cpr->hw_stats_map);
1425 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1427 HWRM_CHECK_RESULT();
1429 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1436 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1437 unsigned int idx __rte_unused)
1440 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1441 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1443 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1445 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1447 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1449 HWRM_CHECK_RESULT();
1455 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1458 struct hwrm_vnic_alloc_input req = { 0 };
1459 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1461 if (!BNXT_HAS_RING_GRPS(bp))
1462 goto skip_ring_grps;
1464 /* map ring groups to this vnic */
1465 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1466 vnic->start_grp_id, vnic->end_grp_id);
1467 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1468 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1470 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1471 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1472 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1473 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1476 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1477 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1478 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1480 if (vnic->func_default)
1482 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1483 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1485 HWRM_CHECK_RESULT();
1487 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1489 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1493 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1494 struct bnxt_vnic_info *vnic,
1495 struct bnxt_plcmodes_cfg *pmode)
1498 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1499 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1501 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1503 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1505 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1507 HWRM_CHECK_RESULT();
1509 pmode->flags = rte_le_to_cpu_32(resp->flags);
1510 /* dflt_vnic bit doesn't exist in the _cfg command */
1511 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1512 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1513 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1514 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1521 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1522 struct bnxt_vnic_info *vnic,
1523 struct bnxt_plcmodes_cfg *pmode)
1526 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1527 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1529 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1530 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1534 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1536 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1537 req.flags = rte_cpu_to_le_32(pmode->flags);
1538 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1539 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1540 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1541 req.enables = rte_cpu_to_le_32(
1542 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1543 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1544 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1547 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1549 HWRM_CHECK_RESULT();
1555 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1558 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1559 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1560 struct bnxt_plcmodes_cfg pmodes = { 0 };
1561 uint32_t ctx_enable_flag = 0;
1562 uint32_t enables = 0;
1564 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1565 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1569 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1573 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1575 if (BNXT_CHIP_THOR(bp)) {
1576 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1577 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1578 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1580 req.default_rx_ring_id =
1581 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1582 req.default_cmpl_ring_id =
1583 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1584 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1585 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1589 /* Only RSS support for now TBD: COS & LB */
1590 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1591 if (vnic->lb_rule != 0xffff)
1592 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1593 if (vnic->cos_rule != 0xffff)
1594 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1595 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1596 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1597 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1599 enables |= ctx_enable_flag;
1600 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1601 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1602 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1603 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1606 req.enables = rte_cpu_to_le_32(enables);
1607 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1608 req.mru = rte_cpu_to_le_16(vnic->mru);
1609 /* Configure default VNIC only once. */
1610 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1612 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1613 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1615 if (vnic->vlan_strip)
1617 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1620 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1621 if (vnic->roce_dual)
1622 req.flags |= rte_cpu_to_le_32(
1623 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1624 if (vnic->roce_only)
1625 req.flags |= rte_cpu_to_le_32(
1626 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1627 if (vnic->rss_dflt_cr)
1628 req.flags |= rte_cpu_to_le_32(
1629 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1631 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1633 HWRM_CHECK_RESULT();
1636 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1641 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1645 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1646 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1648 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1649 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1652 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1655 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1656 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1657 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1659 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1661 HWRM_CHECK_RESULT();
1663 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1664 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1665 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1666 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1667 vnic->mru = rte_le_to_cpu_16(resp->mru);
1668 vnic->func_default = rte_le_to_cpu_32(
1669 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1670 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1671 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1672 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1673 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1674 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1675 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1676 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1677 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1678 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1679 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1686 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1687 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1691 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1692 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1693 bp->hwrm_cmd_resp_addr;
1695 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1697 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1698 HWRM_CHECK_RESULT();
1700 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1701 if (!BNXT_HAS_RING_GRPS(bp))
1702 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1703 else if (ctx_idx == 0)
1704 vnic->rss_rule = ctx_id;
1711 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1712 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1715 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1716 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1717 bp->hwrm_cmd_resp_addr;
1719 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1720 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1723 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1725 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1727 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1729 HWRM_CHECK_RESULT();
1735 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1738 struct hwrm_vnic_free_input req = {.req_type = 0 };
1739 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1741 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1742 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1746 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1748 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1750 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1752 HWRM_CHECK_RESULT();
1755 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1756 /* Configure default VNIC again if necessary. */
1757 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1758 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1764 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1768 int nr_ctxs = vnic->num_lb_ctxts;
1769 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1770 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1772 for (i = 0; i < nr_ctxs; i++) {
1773 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1775 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1776 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1777 req.hash_mode_flags = vnic->hash_mode;
1779 req.hash_key_tbl_addr =
1780 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1782 req.ring_grp_tbl_addr =
1783 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1784 i * HW_HASH_INDEX_SIZE);
1785 req.ring_table_pair_index = i;
1786 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1788 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1791 HWRM_CHECK_RESULT();
1798 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1799 struct bnxt_vnic_info *vnic)
1802 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1803 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1805 if (!vnic->rss_table)
1808 if (BNXT_CHIP_THOR(bp))
1809 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1811 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1813 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1814 req.hash_mode_flags = vnic->hash_mode;
1816 req.ring_grp_tbl_addr =
1817 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1818 req.hash_key_tbl_addr =
1819 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1820 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1821 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1823 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1825 HWRM_CHECK_RESULT();
1831 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1832 struct bnxt_vnic_info *vnic)
1835 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1836 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1839 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1840 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1844 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1846 req.flags = rte_cpu_to_le_32(
1847 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1849 req.enables = rte_cpu_to_le_32(
1850 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1852 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1853 size -= RTE_PKTMBUF_HEADROOM;
1855 req.jumbo_thresh = rte_cpu_to_le_16(size);
1856 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1858 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1860 HWRM_CHECK_RESULT();
1866 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1867 struct bnxt_vnic_info *vnic, bool enable)
1870 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1871 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1873 if (BNXT_CHIP_THOR(bp))
1876 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1879 req.enables = rte_cpu_to_le_32(
1880 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1881 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1882 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1883 req.flags = rte_cpu_to_le_32(
1884 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1885 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1886 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1887 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1888 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1889 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1890 req.max_agg_segs = rte_cpu_to_le_16(5);
1892 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1893 req.min_agg_len = rte_cpu_to_le_32(512);
1895 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1897 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1899 HWRM_CHECK_RESULT();
1905 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1907 struct hwrm_func_cfg_input req = {0};
1908 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1911 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1912 req.enables = rte_cpu_to_le_32(
1913 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1914 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1915 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1917 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1919 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1920 HWRM_CHECK_RESULT();
1923 bp->pf.vf_info[vf].random_mac = false;
1928 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1932 struct hwrm_func_qstats_input req = {.req_type = 0};
1933 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1935 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1937 req.fid = rte_cpu_to_le_16(fid);
1939 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1941 HWRM_CHECK_RESULT();
1944 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1951 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1952 struct rte_eth_stats *stats)
1955 struct hwrm_func_qstats_input req = {.req_type = 0};
1956 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1958 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1960 req.fid = rte_cpu_to_le_16(fid);
1962 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1964 HWRM_CHECK_RESULT();
1966 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1967 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1968 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1969 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1970 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1971 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1973 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1974 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1975 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1976 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1977 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1978 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1980 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1981 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1982 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1989 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1992 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1993 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1995 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1997 req.fid = rte_cpu_to_le_16(fid);
1999 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2001 HWRM_CHECK_RESULT();
2008 * HWRM utility functions
2011 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2016 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2017 struct bnxt_tx_queue *txq;
2018 struct bnxt_rx_queue *rxq;
2019 struct bnxt_cp_ring_info *cpr;
2021 if (i >= bp->rx_cp_nr_rings) {
2022 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2025 rxq = bp->rx_queues[i];
2029 rc = bnxt_hwrm_stat_clear(bp, cpr);
2036 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2040 struct bnxt_cp_ring_info *cpr;
2042 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2044 if (i >= bp->rx_cp_nr_rings) {
2045 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2047 cpr = bp->rx_queues[i]->cp_ring;
2048 if (BNXT_HAS_RING_GRPS(bp))
2049 bp->grp_info[i].fw_stats_ctx = -1;
2051 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2052 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2053 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2061 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2066 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2067 struct bnxt_tx_queue *txq;
2068 struct bnxt_rx_queue *rxq;
2069 struct bnxt_cp_ring_info *cpr;
2071 if (i >= bp->rx_cp_nr_rings) {
2072 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2075 rxq = bp->rx_queues[i];
2079 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2087 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2092 if (!BNXT_HAS_RING_GRPS(bp))
2095 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2097 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2100 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2108 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2110 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2112 bnxt_hwrm_ring_free(bp, cp_ring,
2113 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2114 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2115 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2116 sizeof(*cpr->cp_desc_ring));
2117 cpr->cp_raw_cons = 0;
2121 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2123 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2125 bnxt_hwrm_ring_free(bp, cp_ring,
2126 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2127 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2128 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2129 sizeof(*cpr->cp_desc_ring));
2130 cpr->cp_raw_cons = 0;
2134 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2136 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2137 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2138 struct bnxt_ring *ring = rxr->rx_ring_struct;
2139 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2141 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2142 bnxt_hwrm_ring_free(bp, ring,
2143 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2144 ring->fw_ring_id = INVALID_HW_RING_ID;
2145 if (BNXT_HAS_RING_GRPS(bp))
2146 bp->grp_info[queue_index].rx_fw_ring_id =
2148 memset(rxr->rx_desc_ring, 0,
2149 rxr->rx_ring_struct->ring_size *
2150 sizeof(*rxr->rx_desc_ring));
2151 memset(rxr->rx_buf_ring, 0,
2152 rxr->rx_ring_struct->ring_size *
2153 sizeof(*rxr->rx_buf_ring));
2156 ring = rxr->ag_ring_struct;
2157 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2158 bnxt_hwrm_ring_free(bp, ring,
2159 BNXT_CHIP_THOR(bp) ?
2160 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2161 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2162 ring->fw_ring_id = INVALID_HW_RING_ID;
2163 memset(rxr->ag_buf_ring, 0,
2164 rxr->ag_ring_struct->ring_size *
2165 sizeof(*rxr->ag_buf_ring));
2167 if (BNXT_HAS_RING_GRPS(bp))
2168 bp->grp_info[queue_index].ag_fw_ring_id =
2171 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2172 bnxt_free_cp_ring(bp, cpr);
2174 bnxt_free_nq_ring(bp, rxq->nq_ring);
2177 if (BNXT_HAS_RING_GRPS(bp))
2178 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2181 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2185 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2186 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2187 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2188 struct bnxt_ring *ring = txr->tx_ring_struct;
2189 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2191 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2192 bnxt_hwrm_ring_free(bp, ring,
2193 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2194 ring->fw_ring_id = INVALID_HW_RING_ID;
2195 memset(txr->tx_desc_ring, 0,
2196 txr->tx_ring_struct->ring_size *
2197 sizeof(*txr->tx_desc_ring));
2198 memset(txr->tx_buf_ring, 0,
2199 txr->tx_ring_struct->ring_size *
2200 sizeof(*txr->tx_buf_ring));
2204 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2205 bnxt_free_cp_ring(bp, cpr);
2206 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2208 bnxt_free_nq_ring(bp, txq->nq_ring);
2212 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2213 bnxt_free_hwrm_rx_ring(bp, i);
2218 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2223 if (!BNXT_HAS_RING_GRPS(bp))
2226 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2227 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2234 void bnxt_free_hwrm_resources(struct bnxt *bp)
2236 /* Release memzone */
2237 rte_free(bp->hwrm_cmd_resp_addr);
2238 rte_free(bp->hwrm_short_cmd_req_addr);
2239 bp->hwrm_cmd_resp_addr = NULL;
2240 bp->hwrm_short_cmd_req_addr = NULL;
2241 bp->hwrm_cmd_resp_dma_addr = 0;
2242 bp->hwrm_short_cmd_req_dma_addr = 0;
2245 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2247 struct rte_pci_device *pdev = bp->pdev;
2248 char type[RTE_MEMZONE_NAMESIZE];
2250 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2251 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2252 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2253 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2254 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2255 if (bp->hwrm_cmd_resp_addr == NULL)
2257 bp->hwrm_cmd_resp_dma_addr =
2258 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2259 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2261 "unable to map response address to physical memory\n");
2264 rte_spinlock_init(&bp->hwrm_lock);
2269 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2271 struct bnxt_filter_info *filter;
2274 STAILQ_FOREACH(filter, &vnic->filter, next) {
2275 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2276 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2277 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2278 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2280 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2281 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2289 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2291 struct bnxt_filter_info *filter;
2292 struct rte_flow *flow;
2295 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2296 filter = flow->filter;
2297 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2298 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2299 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2300 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2301 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2303 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2305 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2313 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2315 struct bnxt_filter_info *filter;
2318 STAILQ_FOREACH(filter, &vnic->filter, next) {
2319 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2320 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2322 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2323 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2326 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2334 void bnxt_free_tunnel_ports(struct bnxt *bp)
2336 if (bp->vxlan_port_cnt)
2337 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2338 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2340 if (bp->geneve_port_cnt)
2341 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2342 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2343 bp->geneve_port = 0;
2346 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2350 if (bp->vnic_info == NULL)
2354 * Cleanup VNICs in reverse order, to make sure the L2 filter
2355 * from vnic0 is last to be cleaned up.
2357 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2358 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2360 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2361 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2365 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2367 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2369 if (BNXT_CHIP_THOR(bp)) {
2370 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2371 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2372 vnic->fw_grp_ids[j]);
2373 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2375 vnic->num_lb_ctxts = 0;
2377 bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2378 vnic->rss_rule = INVALID_HW_RING_ID;
2381 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2383 bnxt_hwrm_vnic_free(bp, vnic);
2385 rte_free(vnic->fw_grp_ids);
2387 /* Ring resources */
2388 bnxt_free_all_hwrm_rings(bp);
2389 bnxt_free_all_hwrm_ring_grps(bp);
2390 bnxt_free_all_hwrm_stat_ctxs(bp);
2391 bnxt_free_tunnel_ports(bp);
2394 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2396 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2398 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2399 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2401 switch (conf_link_speed) {
2402 case ETH_LINK_SPEED_10M_HD:
2403 case ETH_LINK_SPEED_100M_HD:
2405 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2407 return hw_link_duplex;
2410 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2412 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2415 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2417 uint16_t eth_link_speed = 0;
2419 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2420 return ETH_LINK_SPEED_AUTONEG;
2422 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2423 case ETH_LINK_SPEED_100M:
2424 case ETH_LINK_SPEED_100M_HD:
2427 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2429 case ETH_LINK_SPEED_1G:
2431 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2433 case ETH_LINK_SPEED_2_5G:
2435 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2437 case ETH_LINK_SPEED_10G:
2439 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2441 case ETH_LINK_SPEED_20G:
2443 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2445 case ETH_LINK_SPEED_25G:
2447 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2449 case ETH_LINK_SPEED_40G:
2451 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2453 case ETH_LINK_SPEED_50G:
2455 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2457 case ETH_LINK_SPEED_100G:
2459 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2463 "Unsupported link speed %d; default to AUTO\n",
2467 return eth_link_speed;
2470 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2471 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2472 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2473 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2475 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2479 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2482 if (link_speed & ETH_LINK_SPEED_FIXED) {
2483 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2485 if (one_speed & (one_speed - 1)) {
2487 "Invalid advertised speeds (%u) for port %u\n",
2488 link_speed, port_id);
2491 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2493 "Unsupported advertised speed (%u) for port %u\n",
2494 link_speed, port_id);
2498 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2500 "Unsupported advertised speeds (%u) for port %u\n",
2501 link_speed, port_id);
2509 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2513 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2514 if (bp->link_info.support_speeds)
2515 return bp->link_info.support_speeds;
2516 link_speed = BNXT_SUPPORTED_SPEEDS;
2519 if (link_speed & ETH_LINK_SPEED_100M)
2520 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2521 if (link_speed & ETH_LINK_SPEED_100M_HD)
2522 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2523 if (link_speed & ETH_LINK_SPEED_1G)
2524 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2525 if (link_speed & ETH_LINK_SPEED_2_5G)
2526 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2527 if (link_speed & ETH_LINK_SPEED_10G)
2528 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2529 if (link_speed & ETH_LINK_SPEED_20G)
2530 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2531 if (link_speed & ETH_LINK_SPEED_25G)
2532 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2533 if (link_speed & ETH_LINK_SPEED_40G)
2534 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2535 if (link_speed & ETH_LINK_SPEED_50G)
2536 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2537 if (link_speed & ETH_LINK_SPEED_100G)
2538 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2542 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2544 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2546 switch (hw_link_speed) {
2547 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2548 eth_link_speed = ETH_SPEED_NUM_100M;
2550 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2551 eth_link_speed = ETH_SPEED_NUM_1G;
2553 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2554 eth_link_speed = ETH_SPEED_NUM_2_5G;
2556 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2557 eth_link_speed = ETH_SPEED_NUM_10G;
2559 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2560 eth_link_speed = ETH_SPEED_NUM_20G;
2562 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2563 eth_link_speed = ETH_SPEED_NUM_25G;
2565 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2566 eth_link_speed = ETH_SPEED_NUM_40G;
2568 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2569 eth_link_speed = ETH_SPEED_NUM_50G;
2571 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2572 eth_link_speed = ETH_SPEED_NUM_100G;
2574 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2576 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2580 return eth_link_speed;
2583 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2585 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2587 switch (hw_link_duplex) {
2588 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2589 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2591 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2593 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2594 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2597 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2601 return eth_link_duplex;
2604 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2607 struct bnxt_link_info *link_info = &bp->link_info;
2609 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2612 "Get link config failed with rc %d\n", rc);
2615 if (link_info->link_speed)
2617 bnxt_parse_hw_link_speed(link_info->link_speed);
2619 link->link_speed = ETH_SPEED_NUM_NONE;
2620 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2621 link->link_status = link_info->link_up;
2622 link->link_autoneg = link_info->auto_mode ==
2623 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2624 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2629 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2632 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2633 struct bnxt_link_info link_req;
2634 uint16_t speed, autoneg;
2636 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2639 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2640 bp->eth_dev->data->port_id);
2644 memset(&link_req, 0, sizeof(link_req));
2645 link_req.link_up = link_up;
2649 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2650 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2651 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2652 /* Autoneg can be done only when the FW allows */
2653 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2654 bp->link_info.force_link_speed)) {
2655 link_req.phy_flags |=
2656 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2657 link_req.auto_link_speed_mask =
2658 bnxt_parse_eth_link_speed_mask(bp,
2659 dev_conf->link_speeds);
2661 if (bp->link_info.phy_type ==
2662 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2663 bp->link_info.phy_type ==
2664 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2665 bp->link_info.media_type ==
2666 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2667 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2671 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2672 /* If user wants a particular speed try that first. */
2674 link_req.link_speed = speed;
2675 else if (bp->link_info.force_link_speed)
2676 link_req.link_speed = bp->link_info.force_link_speed;
2678 link_req.link_speed = bp->link_info.auto_link_speed;
2680 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2681 link_req.auto_pause = bp->link_info.auto_pause;
2682 link_req.force_pause = bp->link_info.force_pause;
2685 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2688 "Set link config failed with rc %d\n", rc);
2696 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2698 struct hwrm_func_qcfg_input req = {0};
2699 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2703 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2704 req.fid = rte_cpu_to_le_16(0xffff);
2706 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2708 HWRM_CHECK_RESULT();
2710 /* Hard Coded.. 0xfff VLAN ID mask */
2711 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2712 flags = rte_le_to_cpu_16(resp->flags);
2713 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2714 bp->flags |= BNXT_FLAG_MULTI_HOST;
2716 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2717 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2718 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2719 } else if (BNXT_VF(bp) &&
2720 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2721 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2722 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2728 switch (resp->port_partition_type) {
2729 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2730 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2731 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2733 bp->port_partition_type = resp->port_partition_type;
2736 bp->port_partition_type = 0;
2745 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2746 struct hwrm_func_qcaps_output *qcaps)
2748 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2749 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2750 sizeof(qcaps->mac_address));
2751 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2752 qcaps->max_rx_rings = fcfg->num_rx_rings;
2753 qcaps->max_tx_rings = fcfg->num_tx_rings;
2754 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2755 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2757 qcaps->first_vf_id = 0;
2758 qcaps->max_vnics = fcfg->num_vnics;
2759 qcaps->max_decap_records = 0;
2760 qcaps->max_encap_records = 0;
2761 qcaps->max_tx_wm_flows = 0;
2762 qcaps->max_tx_em_flows = 0;
2763 qcaps->max_rx_wm_flows = 0;
2764 qcaps->max_rx_em_flows = 0;
2765 qcaps->max_flow_id = 0;
2766 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2767 qcaps->max_sp_tx_rings = 0;
2768 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2771 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2773 struct hwrm_func_cfg_input req = {0};
2774 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2778 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2779 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2780 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2781 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2782 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2783 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2784 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2785 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2786 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2788 if (BNXT_HAS_RING_GRPS(bp)) {
2789 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2790 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2791 } else if (BNXT_HAS_NQ(bp)) {
2792 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2793 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2796 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2797 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2798 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2799 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2801 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2802 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2803 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2804 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2805 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2806 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2807 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2808 req.fid = rte_cpu_to_le_16(0xffff);
2809 req.enables = rte_cpu_to_le_32(enables);
2811 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2813 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2815 HWRM_CHECK_RESULT();
2821 static void populate_vf_func_cfg_req(struct bnxt *bp,
2822 struct hwrm_func_cfg_input *req,
2825 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2826 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2827 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2828 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2829 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2830 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2831 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2832 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2833 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2834 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2836 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2837 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2839 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2840 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2842 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2844 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2845 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2847 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2848 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2849 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2850 /* TODO: For now, do not support VMDq/RFS on VFs. */
2851 req->num_vnics = rte_cpu_to_le_16(1);
2852 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2856 static void add_random_mac_if_needed(struct bnxt *bp,
2857 struct hwrm_func_cfg_input *cfg_req,
2860 struct rte_ether_addr mac;
2862 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2865 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2867 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2868 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2869 bp->pf.vf_info[vf].random_mac = true;
2871 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2872 RTE_ETHER_ADDR_LEN);
2876 static void reserve_resources_from_vf(struct bnxt *bp,
2877 struct hwrm_func_cfg_input *cfg_req,
2880 struct hwrm_func_qcaps_input req = {0};
2881 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2884 /* Get the actual allocated values now */
2885 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2886 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2887 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2890 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2891 copy_func_cfg_to_qcaps(cfg_req, resp);
2892 } else if (resp->error_code) {
2893 rc = rte_le_to_cpu_16(resp->error_code);
2894 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2895 copy_func_cfg_to_qcaps(cfg_req, resp);
2898 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2899 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2900 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2901 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2902 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2903 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2905 * TODO: While not supporting VMDq with VFs, max_vnics is always
2906 * forced to 1 in this case
2908 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2909 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2914 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2916 struct hwrm_func_qcfg_input req = {0};
2917 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2920 /* Check for zero MAC address */
2921 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2922 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2923 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2924 HWRM_CHECK_RESULT();
2925 rc = rte_le_to_cpu_16(resp->vlan);
2932 static int update_pf_resource_max(struct bnxt *bp)
2934 struct hwrm_func_qcfg_input req = {0};
2935 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2938 /* And copy the allocated numbers into the pf struct */
2939 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2940 req.fid = rte_cpu_to_le_16(0xffff);
2941 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2942 HWRM_CHECK_RESULT();
2944 /* Only TX ring value reflects actual allocation? TODO */
2945 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2946 bp->pf.evb_mode = resp->evb_mode;
2953 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2958 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2962 rc = bnxt_hwrm_func_qcaps(bp);
2966 bp->pf.func_cfg_flags &=
2967 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2968 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2969 bp->pf.func_cfg_flags |=
2970 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2971 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2972 rc = __bnxt_hwrm_func_qcaps(bp);
2976 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2978 struct hwrm_func_cfg_input req = {0};
2979 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2986 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2990 rc = bnxt_hwrm_func_qcaps(bp);
2995 bp->pf.active_vfs = num_vfs;
2998 * First, configure the PF to only use one TX ring. This ensures that
2999 * there are enough rings for all VFs.
3001 * If we don't do this, when we call func_alloc() later, we will lock
3002 * extra rings to the PF that won't be available during func_cfg() of
3005 * This has been fixed with firmware versions above 20.6.54
3007 bp->pf.func_cfg_flags &=
3008 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3009 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3010 bp->pf.func_cfg_flags |=
3011 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3012 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3017 * Now, create and register a buffer to hold forwarded VF requests
3019 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3020 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3021 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3022 if (bp->pf.vf_req_buf == NULL) {
3026 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3027 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3028 for (i = 0; i < num_vfs; i++)
3029 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3030 (i * HWRM_MAX_REQ_LEN);
3032 rc = bnxt_hwrm_func_buf_rgtr(bp);
3036 populate_vf_func_cfg_req(bp, &req, num_vfs);
3038 bp->pf.active_vfs = 0;
3039 for (i = 0; i < num_vfs; i++) {
3040 add_random_mac_if_needed(bp, &req, i);
3042 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3043 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3044 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3045 rc = bnxt_hwrm_send_message(bp,
3050 /* Clear enable flag for next pass */
3051 req.enables &= ~rte_cpu_to_le_32(
3052 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3054 if (rc || resp->error_code) {
3056 "Failed to initizlie VF %d\n", i);
3058 "Not all VFs available. (%d, %d)\n",
3059 rc, resp->error_code);
3066 reserve_resources_from_vf(bp, &req, i);
3067 bp->pf.active_vfs++;
3068 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3072 * Now configure the PF to use "the rest" of the resources
3073 * We're using STD_TX_RING_MODE here though which will limit the TX
3074 * rings. This will allow QoS to function properly. Not setting this
3075 * will cause PF rings to break bandwidth settings.
3077 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3081 rc = update_pf_resource_max(bp);
3088 bnxt_hwrm_func_buf_unrgtr(bp);
3092 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3094 struct hwrm_func_cfg_input req = {0};
3095 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3098 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3100 req.fid = rte_cpu_to_le_16(0xffff);
3101 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3102 req.evb_mode = bp->pf.evb_mode;
3104 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3105 HWRM_CHECK_RESULT();
3111 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3112 uint8_t tunnel_type)
3114 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3115 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3118 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3119 req.tunnel_type = tunnel_type;
3120 req.tunnel_dst_port_val = port;
3121 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3122 HWRM_CHECK_RESULT();
3124 switch (tunnel_type) {
3125 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3126 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3127 bp->vxlan_port = port;
3129 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3130 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3131 bp->geneve_port = port;
3142 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3143 uint8_t tunnel_type)
3145 struct hwrm_tunnel_dst_port_free_input req = {0};
3146 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3149 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3151 req.tunnel_type = tunnel_type;
3152 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3153 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3155 HWRM_CHECK_RESULT();
3161 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3164 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3165 struct hwrm_func_cfg_input req = {0};
3168 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3170 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3171 req.flags = rte_cpu_to_le_32(flags);
3172 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3174 HWRM_CHECK_RESULT();
3180 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3182 uint32_t *flag = flagp;
3184 vnic->flags = *flag;
3187 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3189 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3192 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3195 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3196 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3198 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3200 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3201 req.req_buf_page_size = rte_cpu_to_le_16(
3202 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3203 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3204 req.req_buf_page_addr0 =
3205 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3206 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3208 "unable to map buffer address to physical memory\n");
3212 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3214 HWRM_CHECK_RESULT();
3220 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3223 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3224 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3226 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3229 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3231 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3233 HWRM_CHECK_RESULT();
3239 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3241 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3242 struct hwrm_func_cfg_input req = {0};
3245 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3247 req.fid = rte_cpu_to_le_16(0xffff);
3248 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3249 req.enables = rte_cpu_to_le_32(
3250 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3251 req.async_event_cr = rte_cpu_to_le_16(
3252 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3253 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3255 HWRM_CHECK_RESULT();
3261 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3263 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3264 struct hwrm_func_vf_cfg_input req = {0};
3267 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3269 req.enables = rte_cpu_to_le_32(
3270 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3271 req.async_event_cr = rte_cpu_to_le_16(
3272 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3273 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3275 HWRM_CHECK_RESULT();
3281 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3283 struct hwrm_func_cfg_input req = {0};
3284 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3285 uint16_t dflt_vlan, fid;
3286 uint32_t func_cfg_flags;
3289 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3292 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3293 fid = bp->pf.vf_info[vf].fid;
3294 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3296 fid = rte_cpu_to_le_16(0xffff);
3297 func_cfg_flags = bp->pf.func_cfg_flags;
3298 dflt_vlan = bp->vlan;
3301 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3302 req.fid = rte_cpu_to_le_16(fid);
3303 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3304 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3306 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3308 HWRM_CHECK_RESULT();
3314 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3315 uint16_t max_bw, uint16_t enables)
3317 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3318 struct hwrm_func_cfg_input req = {0};
3321 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3323 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3324 req.enables |= rte_cpu_to_le_32(enables);
3325 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3326 req.max_bw = rte_cpu_to_le_32(max_bw);
3327 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3329 HWRM_CHECK_RESULT();
3335 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3337 struct hwrm_func_cfg_input req = {0};
3338 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3341 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3343 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3344 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3345 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3346 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3348 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3350 HWRM_CHECK_RESULT();
3356 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3361 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3363 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3368 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3369 void *encaped, size_t ec_size)
3372 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3373 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3375 if (ec_size > sizeof(req.encap_request))
3378 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3380 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3381 memcpy(req.encap_request, encaped, ec_size);
3383 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3385 HWRM_CHECK_RESULT();
3391 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3392 struct rte_ether_addr *mac)
3394 struct hwrm_func_qcfg_input req = {0};
3395 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3398 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3400 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3401 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3403 HWRM_CHECK_RESULT();
3405 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3412 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3413 void *encaped, size_t ec_size)
3416 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3417 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3419 if (ec_size > sizeof(req.encap_request))
3422 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3424 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3425 memcpy(req.encap_request, encaped, ec_size);
3427 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3429 HWRM_CHECK_RESULT();
3435 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3436 struct rte_eth_stats *stats, uint8_t rx)
3439 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3440 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3442 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3444 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3446 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3448 HWRM_CHECK_RESULT();
3451 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3452 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3453 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3454 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3455 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3456 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3457 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3458 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3460 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3461 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3462 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3463 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3464 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3465 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3474 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3476 struct hwrm_port_qstats_input req = {0};
3477 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3478 struct bnxt_pf_info *pf = &bp->pf;
3481 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3483 req.port_id = rte_cpu_to_le_16(pf->port_id);
3484 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3485 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3486 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3488 HWRM_CHECK_RESULT();
3494 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3496 struct hwrm_port_clr_stats_input req = {0};
3497 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3498 struct bnxt_pf_info *pf = &bp->pf;
3501 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3502 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3503 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3506 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3508 req.port_id = rte_cpu_to_le_16(pf->port_id);
3509 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3511 HWRM_CHECK_RESULT();
3517 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3519 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3520 struct hwrm_port_led_qcaps_input req = {0};
3526 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3527 req.port_id = bp->pf.port_id;
3528 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3530 HWRM_CHECK_RESULT();
3532 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3535 bp->num_leds = resp->num_leds;
3536 memcpy(bp->leds, &resp->led0_id,
3537 sizeof(bp->leds[0]) * bp->num_leds);
3538 for (i = 0; i < bp->num_leds; i++) {
3539 struct bnxt_led_info *led = &bp->leds[i];
3541 uint16_t caps = led->led_state_caps;
3543 if (!led->led_group_id ||
3544 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3556 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3558 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3559 struct hwrm_port_led_cfg_input req = {0};
3560 struct bnxt_led_cfg *led_cfg;
3561 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3562 uint16_t duration = 0;
3565 if (!bp->num_leds || BNXT_VF(bp))
3568 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3571 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3572 duration = rte_cpu_to_le_16(500);
3574 req.port_id = bp->pf.port_id;
3575 req.num_leds = bp->num_leds;
3576 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3577 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3578 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3579 led_cfg->led_id = bp->leds[i].led_id;
3580 led_cfg->led_state = led_state;
3581 led_cfg->led_blink_on = duration;
3582 led_cfg->led_blink_off = duration;
3583 led_cfg->led_group_id = bp->leds[i].led_group_id;
3586 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3588 HWRM_CHECK_RESULT();
3594 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3598 struct hwrm_nvm_get_dir_info_input req = {0};
3599 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3601 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3603 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3605 HWRM_CHECK_RESULT();
3607 *entries = rte_le_to_cpu_32(resp->entries);
3608 *length = rte_le_to_cpu_32(resp->entry_length);
3614 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3617 uint32_t dir_entries;
3618 uint32_t entry_length;
3621 rte_iova_t dma_handle;
3622 struct hwrm_nvm_get_dir_entries_input req = {0};
3623 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3625 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3629 *data++ = dir_entries;
3630 *data++ = entry_length;
3632 memset(data, 0xff, len);
3634 buflen = dir_entries * entry_length;
3635 buf = rte_malloc("nvm_dir", buflen, 0);
3636 rte_mem_lock_page(buf);
3639 dma_handle = rte_mem_virt2iova(buf);
3640 if (dma_handle == RTE_BAD_IOVA) {
3642 "unable to map response address to physical memory\n");
3645 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3646 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3647 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3650 memcpy(data, buf, len > buflen ? buflen : len);
3653 HWRM_CHECK_RESULT();
3659 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3660 uint32_t offset, uint32_t length,
3665 rte_iova_t dma_handle;
3666 struct hwrm_nvm_read_input req = {0};
3667 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3669 buf = rte_malloc("nvm_item", length, 0);
3670 rte_mem_lock_page(buf);
3674 dma_handle = rte_mem_virt2iova(buf);
3675 if (dma_handle == RTE_BAD_IOVA) {
3677 "unable to map response address to physical memory\n");
3680 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3681 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3682 req.dir_idx = rte_cpu_to_le_16(index);
3683 req.offset = rte_cpu_to_le_32(offset);
3684 req.len = rte_cpu_to_le_32(length);
3685 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3687 memcpy(data, buf, length);
3690 HWRM_CHECK_RESULT();
3696 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3699 struct hwrm_nvm_erase_dir_entry_input req = {0};
3700 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3702 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3703 req.dir_idx = rte_cpu_to_le_16(index);
3704 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3705 HWRM_CHECK_RESULT();
3712 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3713 uint16_t dir_ordinal, uint16_t dir_ext,
3714 uint16_t dir_attr, const uint8_t *data,
3718 struct hwrm_nvm_write_input req = {0};
3719 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3720 rte_iova_t dma_handle;
3723 buf = rte_malloc("nvm_write", data_len, 0);
3724 rte_mem_lock_page(buf);
3728 dma_handle = rte_mem_virt2iova(buf);
3729 if (dma_handle == RTE_BAD_IOVA) {
3731 "unable to map response address to physical memory\n");
3734 memcpy(buf, data, data_len);
3736 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3738 req.dir_type = rte_cpu_to_le_16(dir_type);
3739 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3740 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3741 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3742 req.dir_data_length = rte_cpu_to_le_32(data_len);
3743 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3745 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3748 HWRM_CHECK_RESULT();
3755 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3757 uint32_t *count = cbdata;
3759 *count = *count + 1;
3762 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3763 struct bnxt_vnic_info *vnic __rte_unused)
3768 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3772 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3773 &count, bnxt_vnic_count_hwrm_stub);
3778 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3781 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3782 struct hwrm_func_vf_vnic_ids_query_output *resp =
3783 bp->hwrm_cmd_resp_addr;
3786 /* First query all VNIC ids */
3787 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3789 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3790 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3791 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3793 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3796 "unable to map VNIC ID table address to physical memory\n");
3799 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3800 HWRM_CHECK_RESULT();
3801 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3809 * This function queries the VNIC IDs for a specified VF. It then calls
3810 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3811 * Then it calls the hwrm_cb function to program this new vnic configuration.
3813 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3814 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3815 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3817 struct bnxt_vnic_info vnic;
3819 int i, num_vnic_ids;
3824 /* First query all VNIC ids */
3825 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3826 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3827 RTE_CACHE_LINE_SIZE);
3828 if (vnic_ids == NULL)
3831 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3832 rte_mem_lock_page(((char *)vnic_ids) + sz);
3834 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3836 if (num_vnic_ids < 0)
3837 return num_vnic_ids;
3839 /* Retrieve VNIC, update bd_stall then update */
3841 for (i = 0; i < num_vnic_ids; i++) {
3842 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3843 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3844 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3847 if (vnic.mru <= 4) /* Indicates unallocated */
3850 vnic_cb(&vnic, cbdata);
3852 rc = hwrm_cb(bp, &vnic);
3862 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3865 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3866 struct hwrm_func_cfg_input req = {0};
3869 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3871 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3872 req.enables |= rte_cpu_to_le_32(
3873 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3874 req.vlan_antispoof_mode = on ?
3875 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3876 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3877 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3879 HWRM_CHECK_RESULT();
3885 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3887 struct bnxt_vnic_info vnic;
3890 int num_vnic_ids, i;
3894 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3895 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3896 RTE_CACHE_LINE_SIZE);
3897 if (vnic_ids == NULL)
3900 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3901 rte_mem_lock_page(((char *)vnic_ids) + sz);
3903 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3909 * Loop through to find the default VNIC ID.
3910 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3911 * by sending the hwrm_func_qcfg command to the firmware.
3913 for (i = 0; i < num_vnic_ids; i++) {
3914 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3915 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3916 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3917 bp->pf.first_vf_id + vf);
3920 if (vnic.func_default) {
3922 return vnic.fw_vnic_id;
3925 /* Could not find a default VNIC. */
3926 PMD_DRV_LOG(ERR, "No default VNIC\n");
3932 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3934 struct bnxt_filter_info *filter)
3937 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3938 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3939 uint32_t enables = 0;
3941 if (filter->fw_em_filter_id != UINT64_MAX)
3942 bnxt_hwrm_clear_em_filter(bp, filter);
3944 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3946 req.flags = rte_cpu_to_le_32(filter->flags);
3948 enables = filter->enables |
3949 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3950 req.dst_id = rte_cpu_to_le_16(dst_id);
3952 if (filter->ip_addr_type) {
3953 req.ip_addr_type = filter->ip_addr_type;
3954 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3957 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3958 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3960 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3961 memcpy(req.src_macaddr, filter->src_macaddr,
3962 RTE_ETHER_ADDR_LEN);
3964 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3965 memcpy(req.dst_macaddr, filter->dst_macaddr,
3966 RTE_ETHER_ADDR_LEN);
3968 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3969 req.ovlan_vid = filter->l2_ovlan;
3971 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3972 req.ivlan_vid = filter->l2_ivlan;
3974 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3975 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3977 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3978 req.ip_protocol = filter->ip_protocol;
3980 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3981 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3983 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3984 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3986 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3987 req.src_port = rte_cpu_to_be_16(filter->src_port);
3989 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3990 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3992 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3993 req.mirror_vnic_id = filter->mirror_vnic_id;
3995 req.enables = rte_cpu_to_le_32(enables);
3997 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3999 HWRM_CHECK_RESULT();
4001 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4007 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4010 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4011 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4013 if (filter->fw_em_filter_id == UINT64_MAX)
4016 PMD_DRV_LOG(ERR, "Clear EM filter\n");
4017 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4019 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4021 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4023 HWRM_CHECK_RESULT();
4026 filter->fw_em_filter_id = UINT64_MAX;
4027 filter->fw_l2_filter_id = UINT64_MAX;
4032 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4034 struct bnxt_filter_info *filter)
4037 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4038 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4039 bp->hwrm_cmd_resp_addr;
4040 uint32_t enables = 0;
4042 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4043 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4045 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4047 req.flags = rte_cpu_to_le_32(filter->flags);
4049 enables = filter->enables |
4050 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4051 req.dst_id = rte_cpu_to_le_16(dst_id);
4054 if (filter->ip_addr_type) {
4055 req.ip_addr_type = filter->ip_addr_type;
4057 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4060 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4061 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4063 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4064 memcpy(req.src_macaddr, filter->src_macaddr,
4065 RTE_ETHER_ADDR_LEN);
4067 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4068 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4069 //RTE_ETHER_ADDR_LEN);
4071 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4072 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4074 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4075 req.ip_protocol = filter->ip_protocol;
4077 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4078 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4080 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4081 req.src_ipaddr_mask[0] =
4082 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4084 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4085 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4087 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4088 req.dst_ipaddr_mask[0] =
4089 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4091 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4092 req.src_port = rte_cpu_to_le_16(filter->src_port);
4094 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4095 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4097 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4098 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4100 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4101 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4103 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4104 req.mirror_vnic_id = filter->mirror_vnic_id;
4106 req.enables = rte_cpu_to_le_32(enables);
4108 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4110 HWRM_CHECK_RESULT();
4112 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4118 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4119 struct bnxt_filter_info *filter)
4122 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4123 struct hwrm_cfa_ntuple_filter_free_output *resp =
4124 bp->hwrm_cmd_resp_addr;
4126 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4129 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4131 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4133 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4135 HWRM_CHECK_RESULT();
4138 filter->fw_ntuple_filter_id = UINT64_MAX;
4144 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4146 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4147 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4148 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4149 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4150 uint16_t *ring_tbl = vnic->rss_table;
4151 int nr_ctxs = vnic->num_lb_ctxts;
4152 int max_rings = bp->rx_nr_rings;
4156 for (i = 0, k = 0; i < nr_ctxs; i++) {
4157 struct bnxt_rx_ring_info *rxr;
4158 struct bnxt_cp_ring_info *cpr;
4160 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4162 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4163 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4164 req.hash_mode_flags = vnic->hash_mode;
4166 req.ring_grp_tbl_addr =
4167 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4168 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4169 2 * sizeof(*ring_tbl));
4170 req.hash_key_tbl_addr =
4171 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4173 req.ring_table_pair_index = i;
4174 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4176 for (j = 0; j < 64; j++) {
4179 /* Find next active ring. */
4180 for (cnt = 0; cnt < max_rings; cnt++) {
4181 if (rx_queue_state[k] !=
4182 RTE_ETH_QUEUE_STATE_STOPPED)
4184 if (++k == max_rings)
4188 /* Return if no rings are active. */
4189 if (cnt == max_rings)
4192 /* Add rx/cp ring pair to RSS table. */
4193 rxr = rxqs[k]->rx_ring;
4194 cpr = rxqs[k]->cp_ring;
4196 ring_id = rxr->rx_ring_struct->fw_ring_id;
4197 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4198 ring_id = cpr->cp_ring_struct->fw_ring_id;
4199 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4201 if (++k == max_rings)
4204 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4207 HWRM_CHECK_RESULT();
4214 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4216 unsigned int rss_idx, fw_idx, i;
4218 if (!(vnic->rss_table && vnic->hash_type))
4221 if (BNXT_CHIP_THOR(bp))
4222 return bnxt_vnic_rss_configure_thor(bp, vnic);
4225 * Fill the RSS hash & redirection table with
4226 * ring group ids for all VNICs
4228 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4229 rss_idx++, fw_idx++) {
4230 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4231 fw_idx %= bp->rx_cp_nr_rings;
4232 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4236 if (i == bp->rx_cp_nr_rings)
4238 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4240 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4243 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4244 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4248 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4250 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4251 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4253 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4254 req->num_cmpl_dma_aggr_during_int =
4255 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4257 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4259 /* min timer set to 1/2 of interrupt timer */
4260 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4262 /* buf timer set to 1/4 of interrupt timer */
4263 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4265 req->cmpl_aggr_dma_tmr_during_int =
4266 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4268 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4269 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4270 req->flags = rte_cpu_to_le_16(flags);
4273 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4274 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4276 struct hwrm_ring_aggint_qcaps_input req = {0};
4277 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4282 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4283 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4284 HWRM_CHECK_RESULT();
4286 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4287 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4289 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4290 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4291 agg_req->flags = rte_cpu_to_le_16(flags);
4293 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4294 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4295 agg_req->enables = rte_cpu_to_le_32(enables);
4301 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4302 struct bnxt_coal *coal, uint16_t ring_id)
4304 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4305 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4306 bp->hwrm_cmd_resp_addr;
4309 /* Set ring coalesce parameters only for 100G NICs */
4310 if (BNXT_CHIP_THOR(bp)) {
4311 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4313 } else if (bnxt_stratus_device(bp)) {
4314 bnxt_hwrm_set_coal_params(coal, &req);
4319 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4320 req.ring_id = rte_cpu_to_le_16(ring_id);
4321 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4322 HWRM_CHECK_RESULT();
4327 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4328 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4330 struct hwrm_func_backing_store_qcaps_input req = {0};
4331 struct hwrm_func_backing_store_qcaps_output *resp =
4332 bp->hwrm_cmd_resp_addr;
4335 if (!BNXT_CHIP_THOR(bp) ||
4336 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4341 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4342 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4343 HWRM_CHECK_RESULT_SILENT();
4346 struct bnxt_ctx_pg_info *ctx_pg;
4347 struct bnxt_ctx_mem_info *ctx;
4348 int total_alloc_len;
4351 total_alloc_len = sizeof(*ctx);
4352 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4353 RTE_CACHE_LINE_SIZE);
4358 memset(ctx, 0, total_alloc_len);
4360 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4361 sizeof(*ctx_pg) * BNXT_MAX_Q,
4362 RTE_CACHE_LINE_SIZE);
4367 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4368 ctx->tqm_mem[i] = ctx_pg;
4371 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4372 ctx->qp_min_qp1_entries =
4373 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4374 ctx->qp_max_l2_entries =
4375 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4376 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4377 ctx->srq_max_l2_entries =
4378 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4379 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4380 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4381 ctx->cq_max_l2_entries =
4382 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4383 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4384 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4385 ctx->vnic_max_vnic_entries =
4386 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4387 ctx->vnic_max_ring_table_entries =
4388 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4389 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4390 ctx->stat_max_entries =
4391 rte_le_to_cpu_32(resp->stat_max_entries);
4392 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4393 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4394 ctx->tqm_min_entries_per_ring =
4395 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4396 ctx->tqm_max_entries_per_ring =
4397 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4398 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4399 if (!ctx->tqm_entries_multiple)
4400 ctx->tqm_entries_multiple = 1;
4401 ctx->mrav_max_entries =
4402 rte_le_to_cpu_32(resp->mrav_max_entries);
4403 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4404 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4405 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4414 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4416 struct hwrm_func_backing_store_cfg_input req = {0};
4417 struct hwrm_func_backing_store_cfg_output *resp =
4418 bp->hwrm_cmd_resp_addr;
4419 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4420 struct bnxt_ctx_pg_info *ctx_pg;
4421 uint32_t *num_entries;
4430 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4431 req.enables = rte_cpu_to_le_32(enables);
4433 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4434 ctx_pg = &ctx->qp_mem;
4435 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4436 req.qp_num_qp1_entries =
4437 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4438 req.qp_num_l2_entries =
4439 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4440 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4441 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4442 &req.qpc_pg_size_qpc_lvl,
4446 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4447 ctx_pg = &ctx->srq_mem;
4448 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4449 req.srq_num_l2_entries =
4450 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4451 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4452 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4453 &req.srq_pg_size_srq_lvl,
4457 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4458 ctx_pg = &ctx->cq_mem;
4459 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4460 req.cq_num_l2_entries =
4461 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4462 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4463 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4464 &req.cq_pg_size_cq_lvl,
4468 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4469 ctx_pg = &ctx->vnic_mem;
4470 req.vnic_num_vnic_entries =
4471 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4472 req.vnic_num_ring_table_entries =
4473 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4474 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4475 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4476 &req.vnic_pg_size_vnic_lvl,
4477 &req.vnic_page_dir);
4480 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4481 ctx_pg = &ctx->stat_mem;
4482 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4483 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4484 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4485 &req.stat_pg_size_stat_lvl,
4486 &req.stat_page_dir);
4489 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4490 num_entries = &req.tqm_sp_num_entries;
4491 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4492 pg_dir = &req.tqm_sp_page_dir;
4493 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4494 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4495 if (!(enables & ena))
4498 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4500 ctx_pg = ctx->tqm_mem[i];
4501 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4502 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4505 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4506 HWRM_CHECK_RESULT();
4512 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4514 struct hwrm_port_qstats_ext_input req = {0};
4515 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4516 struct bnxt_pf_info *pf = &bp->pf;
4519 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4520 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4523 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4525 req.port_id = rte_cpu_to_le_16(pf->port_id);
4526 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4527 req.tx_stat_host_addr =
4528 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4530 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4532 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4533 req.rx_stat_host_addr =
4534 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4536 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4538 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4541 bp->fw_rx_port_stats_ext_size = 0;
4542 bp->fw_tx_port_stats_ext_size = 0;
4544 bp->fw_rx_port_stats_ext_size =
4545 rte_le_to_cpu_16(resp->rx_stat_size);
4546 bp->fw_tx_port_stats_ext_size =
4547 rte_le_to_cpu_16(resp->tx_stat_size);
4550 HWRM_CHECK_RESULT();
4557 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4559 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4560 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4561 bp->hwrm_cmd_resp_addr;
4564 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4565 req.tunnel_type = type;
4566 req.dest_fid = bp->fw_fid;
4567 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4568 HWRM_CHECK_RESULT();
4576 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4578 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4579 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4580 bp->hwrm_cmd_resp_addr;
4583 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4584 req.tunnel_type = type;
4585 req.dest_fid = bp->fw_fid;
4586 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4587 HWRM_CHECK_RESULT();
4594 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4596 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4597 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4598 bp->hwrm_cmd_resp_addr;
4601 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4602 req.src_fid = bp->fw_fid;
4603 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4604 HWRM_CHECK_RESULT();
4607 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4614 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4617 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4618 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4619 bp->hwrm_cmd_resp_addr;
4622 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4623 req.src_fid = bp->fw_fid;
4624 req.tunnel_type = tun_type;
4625 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4626 HWRM_CHECK_RESULT();
4629 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4631 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4638 int bnxt_hwrm_set_mac(struct bnxt *bp)
4640 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4641 struct hwrm_func_vf_cfg_input req = {0};
4647 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4650 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4651 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4653 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4655 HWRM_CHECK_RESULT();
4657 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);