1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SHORT_CMD_TIMEOUT 50000
31 #define HWRM_SPEC_CODE_1_8_3 0x10803
32 #define HWRM_VERSION_1_9_1 0x10901
33 #define HWRM_VERSION_1_9_2 0x10903
35 struct bnxt_plcmodes_cfg {
37 uint16_t jumbo_thresh;
39 uint16_t hds_threshold;
42 static int page_getenum(size_t size)
58 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
59 return sizeof(void *) * 8 - 1;
62 static int page_roundup(size_t size)
64 return 1 << page_getenum(size);
67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
71 if (rmem->nr_pages > 1) {
73 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
75 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
80 * HWRM Functions (sent to HWRM)
81 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
82 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
83 * command was failed by the ChiMP.
86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
87 uint32_t msg_len, bool use_kong_mb)
90 struct input *req = msg;
91 struct output *resp = bp->hwrm_cmd_resp_addr;
95 uint16_t max_req_len = bp->max_req_len;
96 struct hwrm_short_input short_input = { 0 };
97 uint16_t bar_offset = use_kong_mb ?
98 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
99 uint16_t mb_trigger_offset = use_kong_mb ?
100 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
103 /* Do not send HWRM commands to firmware in error state */
104 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
107 /* For VER_GET command, set timeout as 50ms */
108 if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
109 timeout = HWRM_SHORT_CMD_TIMEOUT;
111 timeout = HWRM_CMD_TIMEOUT;
113 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
114 msg_len > bp->max_req_len) {
115 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
117 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
118 memcpy(short_cmd_req, req, msg_len);
120 short_input.req_type = rte_cpu_to_le_16(req->req_type);
121 short_input.signature = rte_cpu_to_le_16(
122 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
123 short_input.size = rte_cpu_to_le_16(msg_len);
124 short_input.req_addr =
125 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
127 data = (uint32_t *)&short_input;
128 msg_len = sizeof(short_input);
130 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
133 /* Write request msg to hwrm channel */
134 for (i = 0; i < msg_len; i += 4) {
135 bar = (uint8_t *)bp->bar0 + bar_offset + i;
136 rte_write32(*data, bar);
140 /* Zero the rest of the request space */
141 for (; i < max_req_len; i += 4) {
142 bar = (uint8_t *)bp->bar0 + bar_offset + i;
146 /* Ring channel doorbell */
147 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
150 * Make sure the channel doorbell ring command complete before
151 * reading the response to avoid getting stale or invalid
156 /* Poll for the valid bit */
157 for (i = 0; i < timeout; i++) {
158 /* Sanity check on the resp->resp_len */
160 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
161 /* Last byte of resp contains the valid key */
162 valid = (uint8_t *)resp + resp->resp_len - 1;
163 if (*valid == HWRM_RESP_VALID_KEY)
170 /* Suppress VER_GET timeout messages during reset recovery */
171 if (bp->flags & BNXT_FLAG_FW_RESET &&
172 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
175 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
183 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
184 * spinlock, and does initial processing.
186 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
187 * releases the spinlock only if it returns. If the regular int return codes
188 * are not used by the function, HWRM_CHECK_RESULT() should not be used
189 * directly, rather it should be copied and modified to suit the function.
191 * HWRM_UNLOCK() must be called after all response processing is completed.
193 #define HWRM_PREP(req, type, kong) do { \
194 rte_spinlock_lock(&bp->hwrm_lock); \
195 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
196 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
197 req.cmpl_ring = rte_cpu_to_le_16(-1); \
198 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
199 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
200 req.target_id = rte_cpu_to_le_16(0xffff); \
201 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
204 #define HWRM_CHECK_RESULT_SILENT() do {\
206 rte_spinlock_unlock(&bp->hwrm_lock); \
209 if (resp->error_code) { \
210 rc = rte_le_to_cpu_16(resp->error_code); \
211 rte_spinlock_unlock(&bp->hwrm_lock); \
216 #define HWRM_CHECK_RESULT() do {\
218 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
219 rte_spinlock_unlock(&bp->hwrm_lock); \
220 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
222 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
224 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
226 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
232 if (resp->error_code) { \
233 rc = rte_le_to_cpu_16(resp->error_code); \
234 if (resp->resp_len >= 16) { \
235 struct hwrm_err_output *tmp_hwrm_err_op = \
238 "error %d:%d:%08x:%04x\n", \
239 rc, tmp_hwrm_err_op->cmd_err, \
241 tmp_hwrm_err_op->opaque_0), \
243 tmp_hwrm_err_op->opaque_1)); \
245 PMD_DRV_LOG(ERR, "error %d\n", rc); \
247 rte_spinlock_unlock(&bp->hwrm_lock); \
248 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
250 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
252 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
254 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
262 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
264 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
267 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
268 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
270 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
271 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
274 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
282 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
283 struct bnxt_vnic_info *vnic,
285 struct bnxt_vlan_table_entry *vlan_table)
288 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
289 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
292 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
295 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
296 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
298 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
299 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
300 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
301 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
303 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
304 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
306 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
307 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
308 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
309 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
310 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
311 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
314 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
315 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
316 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
317 rte_mem_virt2iova(vlan_table));
318 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
320 req.mask = rte_cpu_to_le_32(mask);
322 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
330 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
332 struct bnxt_vlan_antispoof_table_entry *vlan_table)
335 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
336 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
337 bp->hwrm_cmd_resp_addr;
340 * Older HWRM versions did not support this command, and the set_rx_mask
341 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
342 * removed from set_rx_mask call, and this command was added.
344 * This command is also present from 1.7.8.11 and higher,
347 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
348 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
349 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
354 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
355 req.fid = rte_cpu_to_le_16(fid);
357 req.vlan_tag_mask_tbl_addr =
358 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
359 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
361 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
369 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
370 struct bnxt_filter_info *filter)
373 struct bnxt_filter_info *l2_filter = filter;
374 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
375 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
377 if (filter->fw_l2_filter_id == UINT64_MAX)
380 if (filter->matching_l2_fltr_ptr)
381 l2_filter = filter->matching_l2_fltr_ptr;
383 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
384 filter, l2_filter, l2_filter->l2_ref_cnt);
386 if (l2_filter->l2_ref_cnt > 0)
387 l2_filter->l2_ref_cnt--;
389 if (l2_filter->l2_ref_cnt > 0)
392 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
394 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
396 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
401 filter->fw_l2_filter_id = UINT64_MAX;
406 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
408 struct bnxt_filter_info *filter)
411 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
412 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
413 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
414 const struct rte_eth_vmdq_rx_conf *conf =
415 &dev_conf->rx_adv_conf.vmdq_rx_conf;
416 uint32_t enables = 0;
417 uint16_t j = dst_id - 1;
419 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
420 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
421 conf->pool_map[j].pools & (1UL << j)) {
423 "Add vlan %u to vmdq pool %u\n",
424 conf->pool_map[j].vlan_id, j);
426 filter->l2_ivlan = conf->pool_map[j].vlan_id;
428 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
429 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
432 if (filter->fw_l2_filter_id != UINT64_MAX)
433 bnxt_hwrm_clear_l2_filter(bp, filter);
435 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
437 req.flags = rte_cpu_to_le_32(filter->flags);
439 enables = filter->enables |
440 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
441 req.dst_id = rte_cpu_to_le_16(dst_id);
444 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
445 memcpy(req.l2_addr, filter->l2_addr,
448 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
449 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
452 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
453 req.l2_ovlan = filter->l2_ovlan;
455 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
456 req.l2_ivlan = filter->l2_ivlan;
458 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
459 req.l2_ovlan_mask = filter->l2_ovlan_mask;
461 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
462 req.l2_ivlan_mask = filter->l2_ivlan_mask;
463 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
464 req.src_id = rte_cpu_to_le_32(filter->src_id);
465 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
466 req.src_type = filter->src_type;
467 if (filter->pri_hint) {
468 req.pri_hint = filter->pri_hint;
469 req.l2_filter_id_hint =
470 rte_cpu_to_le_64(filter->l2_filter_id_hint);
473 req.enables = rte_cpu_to_le_32(enables);
475 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
479 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
485 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
487 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
488 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
495 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
498 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
501 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
502 if (ptp->tx_tstamp_en)
503 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
506 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
507 req.flags = rte_cpu_to_le_32(flags);
508 req.enables = rte_cpu_to_le_32
509 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
510 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
512 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
518 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
521 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
522 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
523 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
525 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
529 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
531 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
533 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
537 if (!BNXT_CHIP_THOR(bp) &&
538 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
541 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
542 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
544 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
548 if (!BNXT_CHIP_THOR(bp)) {
549 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
550 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
551 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
552 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
553 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
554 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
555 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
556 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
557 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
558 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
559 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
560 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
561 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
562 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
563 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
564 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
565 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
566 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
575 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
578 struct hwrm_func_qcaps_input req = {.req_type = 0 };
579 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
580 uint16_t new_max_vfs;
584 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
586 req.fid = rte_cpu_to_le_16(0xffff);
588 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
592 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
593 flags = rte_le_to_cpu_32(resp->flags);
595 bp->pf.port_id = resp->port_id;
596 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
597 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
598 new_max_vfs = bp->pdev->max_vfs;
599 if (new_max_vfs != bp->pf.max_vfs) {
601 rte_free(bp->pf.vf_info);
602 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
603 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
604 bp->pf.max_vfs = new_max_vfs;
605 for (i = 0; i < new_max_vfs; i++) {
606 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
607 bp->pf.vf_info[i].vlan_table =
608 rte_zmalloc("VF VLAN table",
611 if (bp->pf.vf_info[i].vlan_table == NULL)
613 "Fail to alloc VLAN table for VF %d\n",
617 bp->pf.vf_info[i].vlan_table);
618 bp->pf.vf_info[i].vlan_as_table =
619 rte_zmalloc("VF VLAN AS table",
622 if (bp->pf.vf_info[i].vlan_as_table == NULL)
624 "Alloc VLAN AS table for VF %d fail\n",
628 bp->pf.vf_info[i].vlan_as_table);
629 STAILQ_INIT(&bp->pf.vf_info[i].filter);
634 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
635 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
636 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
637 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
638 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
639 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
640 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
641 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
642 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
643 if (!BNXT_CHIP_THOR(bp))
644 bp->max_l2_ctx += bp->max_rx_em_flows;
645 /* TODO: For now, do not support VMDq/RFS on VFs. */
650 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
654 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
656 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
657 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
658 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
659 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
661 bnxt_hwrm_ptp_qcfg(bp);
665 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
666 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
668 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
669 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
670 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
672 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
675 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
676 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
678 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
685 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
689 rc = __bnxt_hwrm_func_qcaps(bp);
690 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
691 rc = bnxt_alloc_ctx_mem(bp);
695 rc = bnxt_hwrm_func_resc_qcaps(bp);
697 bp->flags |= BNXT_FLAG_NEW_RM;
703 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
704 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
707 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
708 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
710 HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
712 req.target_id = rte_cpu_to_le_16(0xffff);
714 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
718 if (rte_le_to_cpu_32(resp->flags) &
719 HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
720 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
721 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
724 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
731 int bnxt_hwrm_func_reset(struct bnxt *bp)
734 struct hwrm_func_reset_input req = {.req_type = 0 };
735 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
737 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
739 req.enables = rte_cpu_to_le_32(0);
741 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
749 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
753 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
754 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
756 if (bp->flags & BNXT_FLAG_REGISTERED)
759 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
760 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
761 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
763 /* PFs and trusted VFs should indicate the support of the
764 * Master capability on non Stingray platform
766 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
767 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
769 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
770 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
771 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
772 req.ver_maj = RTE_VER_YEAR;
773 req.ver_min = RTE_VER_MONTH;
774 req.ver_upd = RTE_VER_MINOR;
777 req.enables |= rte_cpu_to_le_32(
778 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
779 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
780 RTE_MIN(sizeof(req.vf_req_fwd),
781 sizeof(bp->pf.vf_req_fwd)));
784 * PF can sniff HWRM API issued by VF. This can be set up by
785 * linux driver and inherited by the DPDK PF driver. Clear
786 * this HWRM sniffer list in FW because DPDK PF driver does
789 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
792 req.flags = rte_cpu_to_le_32(flags);
794 req.async_event_fwd[0] |=
795 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
796 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
797 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
798 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
799 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
800 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
801 req.async_event_fwd[0] |=
802 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
803 req.async_event_fwd[1] |=
804 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
805 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
807 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
811 flags = rte_le_to_cpu_32(resp->flags);
812 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
813 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
817 bp->flags |= BNXT_FLAG_REGISTERED;
822 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
824 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
827 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
830 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
835 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
836 struct hwrm_func_vf_cfg_input req = {0};
838 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
840 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
841 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
842 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
843 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
844 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
846 if (BNXT_HAS_RING_GRPS(bp)) {
847 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
848 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
851 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
852 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
853 AGG_RING_MULTIPLIER);
854 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
856 BNXT_NUM_ASYNC_CPR(bp));
857 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
859 BNXT_NUM_ASYNC_CPR(bp));
860 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
861 if (bp->vf_resv_strategy ==
862 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
863 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
864 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
865 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
866 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
867 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
868 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
872 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
873 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
874 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
875 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
876 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
877 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
879 if (test && BNXT_HAS_RING_GRPS(bp))
880 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
882 req.flags = rte_cpu_to_le_32(flags);
883 req.enables |= rte_cpu_to_le_32(enables);
885 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
888 HWRM_CHECK_RESULT_SILENT();
896 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
899 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
900 struct hwrm_func_resource_qcaps_input req = {0};
902 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
903 req.fid = rte_cpu_to_le_16(0xffff);
905 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
910 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
911 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
912 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
913 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
914 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
915 /* func_resource_qcaps does not return max_rx_em_flows.
916 * So use the value provided by func_qcaps.
918 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
919 if (!BNXT_CHIP_THOR(bp))
920 bp->max_l2_ctx += bp->max_rx_em_flows;
921 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
922 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
924 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
925 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
926 if (bp->vf_resv_strategy >
927 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
928 bp->vf_resv_strategy =
929 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
935 int bnxt_hwrm_ver_get(struct bnxt *bp)
938 struct hwrm_ver_get_input req = {.req_type = 0 };
939 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
941 uint16_t max_resp_len;
942 char type[RTE_MEMZONE_NAMESIZE];
943 uint32_t dev_caps_cfg;
945 bp->max_req_len = HWRM_MAX_REQ_LEN;
946 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
948 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
949 req.hwrm_intf_min = HWRM_VERSION_MINOR;
950 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
952 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
954 if (bp->flags & BNXT_FLAG_FW_RESET)
955 HWRM_CHECK_RESULT_SILENT();
959 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
960 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
961 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
962 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
963 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
964 (resp->hwrm_fw_min_8b << 16) |
965 (resp->hwrm_fw_bld_8b << 8) |
966 resp->hwrm_fw_rsvd_8b;
967 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
968 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
970 fw_version = resp->hwrm_intf_maj_8b << 16;
971 fw_version |= resp->hwrm_intf_min_8b << 8;
972 fw_version |= resp->hwrm_intf_upd_8b;
973 bp->hwrm_spec_code = fw_version;
975 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
976 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
981 if (bp->max_req_len > resp->max_req_win_len) {
982 PMD_DRV_LOG(ERR, "Unsupported request length\n");
985 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
986 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
987 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
988 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
990 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
991 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
993 if (bp->max_resp_len != max_resp_len) {
994 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
995 bp->pdev->addr.domain, bp->pdev->addr.bus,
996 bp->pdev->addr.devid, bp->pdev->addr.function);
998 rte_free(bp->hwrm_cmd_resp_addr);
1000 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1001 if (bp->hwrm_cmd_resp_addr == NULL) {
1005 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1006 bp->hwrm_cmd_resp_dma_addr =
1007 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1008 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1010 "Unable to map response buffer to physical memory.\n");
1014 bp->max_resp_len = max_resp_len;
1018 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1020 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1021 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1022 bp->flags |= BNXT_FLAG_SHORT_CMD;
1025 if (((dev_caps_cfg &
1026 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1028 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1029 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1030 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1031 bp->pdev->addr.domain, bp->pdev->addr.bus,
1032 bp->pdev->addr.devid, bp->pdev->addr.function);
1034 rte_free(bp->hwrm_short_cmd_req_addr);
1036 bp->hwrm_short_cmd_req_addr =
1037 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1038 if (bp->hwrm_short_cmd_req_addr == NULL) {
1042 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1043 bp->hwrm_short_cmd_req_dma_addr =
1044 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1045 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1046 rte_free(bp->hwrm_short_cmd_req_addr);
1048 "Unable to map buffer to physical memory.\n");
1054 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1055 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1056 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1059 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1060 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1062 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1063 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1064 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1072 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1075 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1076 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1078 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1081 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1084 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1086 HWRM_CHECK_RESULT();
1092 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1095 struct hwrm_port_phy_cfg_input req = {0};
1096 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1097 uint32_t enables = 0;
1099 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1101 if (conf->link_up) {
1102 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1103 if (bp->link_info.auto_mode && conf->link_speed) {
1104 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1105 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1108 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1109 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1110 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1112 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1113 * any auto mode, even "none".
1115 if (!conf->link_speed) {
1116 /* No speeds specified. Enable AutoNeg - all speeds */
1118 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1120 /* AutoNeg - Advertise speeds specified. */
1121 if (conf->auto_link_speed_mask &&
1122 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1124 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1125 req.auto_link_speed_mask =
1126 conf->auto_link_speed_mask;
1128 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1131 req.auto_duplex = conf->duplex;
1132 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1133 req.auto_pause = conf->auto_pause;
1134 req.force_pause = conf->force_pause;
1135 /* Set force_pause if there is no auto or if there is a force */
1136 if (req.auto_pause && !req.force_pause)
1137 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1139 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1141 req.enables = rte_cpu_to_le_32(enables);
1144 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1145 PMD_DRV_LOG(INFO, "Force Link Down\n");
1148 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1150 HWRM_CHECK_RESULT();
1156 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1157 struct bnxt_link_info *link_info)
1160 struct hwrm_port_phy_qcfg_input req = {0};
1161 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1163 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1165 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1167 HWRM_CHECK_RESULT();
1169 link_info->phy_link_status = resp->link;
1170 link_info->link_up =
1171 (link_info->phy_link_status ==
1172 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1173 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1174 link_info->duplex = resp->duplex_cfg;
1175 link_info->pause = resp->pause;
1176 link_info->auto_pause = resp->auto_pause;
1177 link_info->force_pause = resp->force_pause;
1178 link_info->auto_mode = resp->auto_mode;
1179 link_info->phy_type = resp->phy_type;
1180 link_info->media_type = resp->media_type;
1182 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1183 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1184 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1185 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1186 link_info->phy_ver[0] = resp->phy_maj;
1187 link_info->phy_ver[1] = resp->phy_min;
1188 link_info->phy_ver[2] = resp->phy_bld;
1192 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1193 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1194 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1195 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1196 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1197 link_info->auto_link_speed_mask);
1198 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1199 link_info->force_link_speed);
1204 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1207 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1208 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1209 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1213 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1215 req.flags = rte_cpu_to_le_32(dir);
1216 /* HWRM Version >= 1.9.1 */
1217 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1219 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1220 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1222 HWRM_CHECK_RESULT();
1224 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1225 GET_TX_QUEUE_INFO(0);
1226 GET_TX_QUEUE_INFO(1);
1227 GET_TX_QUEUE_INFO(2);
1228 GET_TX_QUEUE_INFO(3);
1229 GET_TX_QUEUE_INFO(4);
1230 GET_TX_QUEUE_INFO(5);
1231 GET_TX_QUEUE_INFO(6);
1232 GET_TX_QUEUE_INFO(7);
1234 GET_RX_QUEUE_INFO(0);
1235 GET_RX_QUEUE_INFO(1);
1236 GET_RX_QUEUE_INFO(2);
1237 GET_RX_QUEUE_INFO(3);
1238 GET_RX_QUEUE_INFO(4);
1239 GET_RX_QUEUE_INFO(5);
1240 GET_RX_QUEUE_INFO(6);
1241 GET_RX_QUEUE_INFO(7);
1246 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1249 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1250 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1254 /* iterate and find the COSq profile to use for Tx */
1255 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1256 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1257 if (bp->tx_cos_queue[i].id != 0xff)
1258 bp->tx_cosq_id[j++] =
1259 bp->tx_cos_queue[i].id;
1262 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1263 if (bp->tx_cos_queue[i].profile ==
1264 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1266 bp->tx_cos_queue[i].id;
1273 bp->max_tc = resp->max_configurable_queues;
1274 bp->max_lltc = resp->max_configurable_lossless_queues;
1275 if (bp->max_tc > BNXT_MAX_QUEUE)
1276 bp->max_tc = BNXT_MAX_QUEUE;
1277 bp->max_q = bp->max_tc;
1279 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1280 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1288 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1289 struct bnxt_ring *ring,
1290 uint32_t ring_type, uint32_t map_index,
1291 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1292 uint16_t tx_cosq_id)
1295 uint32_t enables = 0;
1296 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1297 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1298 struct rte_mempool *mb_pool;
1299 uint16_t rx_buf_size;
1301 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1303 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1304 req.fbo = rte_cpu_to_le_32(0);
1305 /* Association of ring index with doorbell index */
1306 req.logical_id = rte_cpu_to_le_16(map_index);
1307 req.length = rte_cpu_to_le_32(ring->ring_size);
1309 switch (ring_type) {
1310 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1311 req.ring_type = ring_type;
1312 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1313 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1314 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1315 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1317 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1319 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1320 req.ring_type = ring_type;
1321 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1322 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1323 if (BNXT_CHIP_THOR(bp)) {
1324 mb_pool = bp->rx_queues[0]->mb_pool;
1325 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1326 RTE_PKTMBUF_HEADROOM;
1327 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1328 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1330 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1332 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1334 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1336 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1337 req.ring_type = ring_type;
1338 if (BNXT_HAS_NQ(bp)) {
1339 /* Association of cp ring with nq */
1340 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1342 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1344 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1346 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1347 req.ring_type = ring_type;
1348 req.page_size = BNXT_PAGE_SHFT;
1349 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1351 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1352 req.ring_type = ring_type;
1353 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1355 mb_pool = bp->rx_queues[0]->mb_pool;
1356 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1357 RTE_PKTMBUF_HEADROOM;
1358 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1359 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1361 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1362 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1363 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1364 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1367 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1372 req.enables = rte_cpu_to_le_32(enables);
1374 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1376 if (rc || resp->error_code) {
1377 if (rc == 0 && resp->error_code)
1378 rc = rte_le_to_cpu_16(resp->error_code);
1379 switch (ring_type) {
1380 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1382 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1385 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1387 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1390 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1392 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1396 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1398 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1401 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1403 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1407 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1413 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1418 int bnxt_hwrm_ring_free(struct bnxt *bp,
1419 struct bnxt_ring *ring, uint32_t ring_type)
1422 struct hwrm_ring_free_input req = {.req_type = 0 };
1423 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1425 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1427 req.ring_type = ring_type;
1428 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1430 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1432 if (rc || resp->error_code) {
1433 if (rc == 0 && resp->error_code)
1434 rc = rte_le_to_cpu_16(resp->error_code);
1437 switch (ring_type) {
1438 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1439 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1442 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1443 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1446 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1447 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1450 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1452 "hwrm_ring_free nq failed. rc:%d\n", rc);
1454 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1456 "hwrm_ring_free agg failed. rc:%d\n", rc);
1459 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1467 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1470 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1471 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1473 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1475 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1476 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1477 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1478 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1480 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1482 HWRM_CHECK_RESULT();
1484 bp->grp_info[idx].fw_grp_id =
1485 rte_le_to_cpu_16(resp->ring_group_id);
1492 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1495 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1496 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1498 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1500 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1502 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1504 HWRM_CHECK_RESULT();
1507 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1511 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1514 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1515 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1517 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1520 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1522 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1524 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1526 HWRM_CHECK_RESULT();
1532 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1533 unsigned int idx __rte_unused)
1536 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1537 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1539 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1541 req.update_period_ms = rte_cpu_to_le_32(0);
1543 req.stats_dma_addr =
1544 rte_cpu_to_le_64(cpr->hw_stats_map);
1546 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1548 HWRM_CHECK_RESULT();
1550 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1557 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1558 unsigned int idx __rte_unused)
1561 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1562 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1564 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1566 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1568 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1570 HWRM_CHECK_RESULT();
1576 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1579 struct hwrm_vnic_alloc_input req = { 0 };
1580 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1582 if (!BNXT_HAS_RING_GRPS(bp))
1583 goto skip_ring_grps;
1585 /* map ring groups to this vnic */
1586 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1587 vnic->start_grp_id, vnic->end_grp_id);
1588 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1589 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1591 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1592 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1593 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1594 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1597 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1598 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1599 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1601 if (vnic->func_default)
1603 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1604 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1606 HWRM_CHECK_RESULT();
1608 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1610 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1614 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1615 struct bnxt_vnic_info *vnic,
1616 struct bnxt_plcmodes_cfg *pmode)
1619 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1620 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1622 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1624 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1626 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1628 HWRM_CHECK_RESULT();
1630 pmode->flags = rte_le_to_cpu_32(resp->flags);
1631 /* dflt_vnic bit doesn't exist in the _cfg command */
1632 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1633 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1634 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1635 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1642 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1643 struct bnxt_vnic_info *vnic,
1644 struct bnxt_plcmodes_cfg *pmode)
1647 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1648 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1650 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1651 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1655 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1657 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1658 req.flags = rte_cpu_to_le_32(pmode->flags);
1659 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1660 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1661 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1662 req.enables = rte_cpu_to_le_32(
1663 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1664 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1665 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1668 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1670 HWRM_CHECK_RESULT();
1676 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1679 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1680 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1681 struct bnxt_plcmodes_cfg pmodes = { 0 };
1682 uint32_t ctx_enable_flag = 0;
1683 uint32_t enables = 0;
1685 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1686 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1690 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1694 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1696 if (BNXT_CHIP_THOR(bp)) {
1697 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1698 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1699 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1701 req.default_rx_ring_id =
1702 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1703 req.default_cmpl_ring_id =
1704 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1705 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1706 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1710 /* Only RSS support for now TBD: COS & LB */
1711 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1712 if (vnic->lb_rule != 0xffff)
1713 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1714 if (vnic->cos_rule != 0xffff)
1715 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1716 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1717 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1718 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1720 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1721 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1722 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1725 enables |= ctx_enable_flag;
1726 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1727 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1728 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1729 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1732 req.enables = rte_cpu_to_le_32(enables);
1733 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1734 req.mru = rte_cpu_to_le_16(vnic->mru);
1735 /* Configure default VNIC only once. */
1736 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1738 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1739 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1741 if (vnic->vlan_strip)
1743 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1746 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1747 if (vnic->roce_dual)
1748 req.flags |= rte_cpu_to_le_32(
1749 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1750 if (vnic->roce_only)
1751 req.flags |= rte_cpu_to_le_32(
1752 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1753 if (vnic->rss_dflt_cr)
1754 req.flags |= rte_cpu_to_le_32(
1755 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1757 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1759 HWRM_CHECK_RESULT();
1762 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1767 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1771 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1772 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1774 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1775 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1778 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1781 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1782 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1783 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1785 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1787 HWRM_CHECK_RESULT();
1789 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1790 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1791 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1792 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1793 vnic->mru = rte_le_to_cpu_16(resp->mru);
1794 vnic->func_default = rte_le_to_cpu_32(
1795 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1796 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1797 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1798 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1799 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1800 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1801 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1802 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1803 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1804 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1805 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1812 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1813 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1817 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1818 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1819 bp->hwrm_cmd_resp_addr;
1821 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1823 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1824 HWRM_CHECK_RESULT();
1826 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1827 if (!BNXT_HAS_RING_GRPS(bp))
1828 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1829 else if (ctx_idx == 0)
1830 vnic->rss_rule = ctx_id;
1838 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1839 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1842 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1843 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1844 bp->hwrm_cmd_resp_addr;
1846 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1847 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1850 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1852 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1854 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1856 HWRM_CHECK_RESULT();
1862 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1866 if (BNXT_CHIP_THOR(bp)) {
1869 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1870 rc = _bnxt_hwrm_vnic_ctx_free(bp,
1872 vnic->fw_grp_ids[j]);
1873 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1875 vnic->num_lb_ctxts = 0;
1877 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1878 vnic->rss_rule = INVALID_HW_RING_ID;
1884 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1887 struct hwrm_vnic_free_input req = {.req_type = 0 };
1888 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1890 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1891 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1895 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1897 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1899 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1901 HWRM_CHECK_RESULT();
1904 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1905 /* Configure default VNIC again if necessary. */
1906 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1907 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1913 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1917 int nr_ctxs = vnic->num_lb_ctxts;
1918 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1919 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1921 for (i = 0; i < nr_ctxs; i++) {
1922 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1924 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1925 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1926 req.hash_mode_flags = vnic->hash_mode;
1928 req.hash_key_tbl_addr =
1929 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1931 req.ring_grp_tbl_addr =
1932 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1933 i * HW_HASH_INDEX_SIZE);
1934 req.ring_table_pair_index = i;
1935 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1937 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1940 HWRM_CHECK_RESULT();
1947 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1948 struct bnxt_vnic_info *vnic)
1951 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1952 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1954 if (!vnic->rss_table)
1957 if (BNXT_CHIP_THOR(bp))
1958 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1960 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1962 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1963 req.hash_mode_flags = vnic->hash_mode;
1965 req.ring_grp_tbl_addr =
1966 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1967 req.hash_key_tbl_addr =
1968 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1969 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1970 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1972 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1974 HWRM_CHECK_RESULT();
1980 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1981 struct bnxt_vnic_info *vnic)
1984 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1985 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1988 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1989 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1993 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1995 req.flags = rte_cpu_to_le_32(
1996 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1998 req.enables = rte_cpu_to_le_32(
1999 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2001 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2002 size -= RTE_PKTMBUF_HEADROOM;
2003 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2005 req.jumbo_thresh = rte_cpu_to_le_16(size);
2006 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2008 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2010 HWRM_CHECK_RESULT();
2016 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2017 struct bnxt_vnic_info *vnic, bool enable)
2020 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2021 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2023 if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2025 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2029 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2030 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2034 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2037 req.enables = rte_cpu_to_le_32(
2038 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2039 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2040 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2041 req.flags = rte_cpu_to_le_32(
2042 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2043 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2044 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2045 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2046 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2047 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2048 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2049 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2050 req.min_agg_len = rte_cpu_to_le_32(512);
2052 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2054 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2056 HWRM_CHECK_RESULT();
2062 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2064 struct hwrm_func_cfg_input req = {0};
2065 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2068 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2069 req.enables = rte_cpu_to_le_32(
2070 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2071 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2072 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2074 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2076 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2077 HWRM_CHECK_RESULT();
2080 bp->pf.vf_info[vf].random_mac = false;
2085 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2089 struct hwrm_func_qstats_input req = {.req_type = 0};
2090 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2092 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2094 req.fid = rte_cpu_to_le_16(fid);
2096 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2098 HWRM_CHECK_RESULT();
2101 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2108 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2109 struct rte_eth_stats *stats)
2112 struct hwrm_func_qstats_input req = {.req_type = 0};
2113 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2115 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2117 req.fid = rte_cpu_to_le_16(fid);
2119 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2121 HWRM_CHECK_RESULT();
2123 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2124 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2125 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2126 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2127 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2128 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2130 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2131 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2132 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2133 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2134 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2135 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2137 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2138 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2139 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2146 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2149 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2150 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2152 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2154 req.fid = rte_cpu_to_le_16(fid);
2156 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2158 HWRM_CHECK_RESULT();
2165 * HWRM utility functions
2168 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2173 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2174 struct bnxt_tx_queue *txq;
2175 struct bnxt_rx_queue *rxq;
2176 struct bnxt_cp_ring_info *cpr;
2178 if (i >= bp->rx_cp_nr_rings) {
2179 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2182 rxq = bp->rx_queues[i];
2186 rc = bnxt_hwrm_stat_clear(bp, cpr);
2193 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2197 struct bnxt_cp_ring_info *cpr;
2199 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2201 if (i >= bp->rx_cp_nr_rings) {
2202 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2204 cpr = bp->rx_queues[i]->cp_ring;
2205 if (BNXT_HAS_RING_GRPS(bp))
2206 bp->grp_info[i].fw_stats_ctx = -1;
2208 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2209 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2210 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2218 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2223 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2224 struct bnxt_tx_queue *txq;
2225 struct bnxt_rx_queue *rxq;
2226 struct bnxt_cp_ring_info *cpr;
2228 if (i >= bp->rx_cp_nr_rings) {
2229 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2232 rxq = bp->rx_queues[i];
2236 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2244 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2249 if (!BNXT_HAS_RING_GRPS(bp))
2252 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2254 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2257 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2265 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2267 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2269 bnxt_hwrm_ring_free(bp, cp_ring,
2270 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2271 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2272 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2273 sizeof(*cpr->cp_desc_ring));
2274 cpr->cp_raw_cons = 0;
2278 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2280 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2282 bnxt_hwrm_ring_free(bp, cp_ring,
2283 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2284 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2285 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2286 sizeof(*cpr->cp_desc_ring));
2287 cpr->cp_raw_cons = 0;
2291 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2293 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2294 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2295 struct bnxt_ring *ring = rxr->rx_ring_struct;
2296 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2298 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2299 bnxt_hwrm_ring_free(bp, ring,
2300 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2301 ring->fw_ring_id = INVALID_HW_RING_ID;
2302 if (BNXT_HAS_RING_GRPS(bp))
2303 bp->grp_info[queue_index].rx_fw_ring_id =
2305 memset(rxr->rx_desc_ring, 0,
2306 rxr->rx_ring_struct->ring_size *
2307 sizeof(*rxr->rx_desc_ring));
2308 memset(rxr->rx_buf_ring, 0,
2309 rxr->rx_ring_struct->ring_size *
2310 sizeof(*rxr->rx_buf_ring));
2313 ring = rxr->ag_ring_struct;
2314 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2315 bnxt_hwrm_ring_free(bp, ring,
2316 BNXT_CHIP_THOR(bp) ?
2317 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2318 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2319 ring->fw_ring_id = INVALID_HW_RING_ID;
2320 memset(rxr->ag_buf_ring, 0,
2321 rxr->ag_ring_struct->ring_size *
2322 sizeof(*rxr->ag_buf_ring));
2324 if (BNXT_HAS_RING_GRPS(bp))
2325 bp->grp_info[queue_index].ag_fw_ring_id =
2328 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2329 bnxt_free_cp_ring(bp, cpr);
2331 if (BNXT_HAS_RING_GRPS(bp))
2332 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2335 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2339 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2340 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2341 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2342 struct bnxt_ring *ring = txr->tx_ring_struct;
2343 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2345 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2346 bnxt_hwrm_ring_free(bp, ring,
2347 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2348 ring->fw_ring_id = INVALID_HW_RING_ID;
2349 memset(txr->tx_desc_ring, 0,
2350 txr->tx_ring_struct->ring_size *
2351 sizeof(*txr->tx_desc_ring));
2352 memset(txr->tx_buf_ring, 0,
2353 txr->tx_ring_struct->ring_size *
2354 sizeof(*txr->tx_buf_ring));
2358 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2359 bnxt_free_cp_ring(bp, cpr);
2360 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2364 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2365 bnxt_free_hwrm_rx_ring(bp, i);
2370 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2375 if (!BNXT_HAS_RING_GRPS(bp))
2378 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2379 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2386 void bnxt_free_hwrm_resources(struct bnxt *bp)
2388 /* Release memzone */
2389 rte_free(bp->hwrm_cmd_resp_addr);
2390 rte_free(bp->hwrm_short_cmd_req_addr);
2391 bp->hwrm_cmd_resp_addr = NULL;
2392 bp->hwrm_short_cmd_req_addr = NULL;
2393 bp->hwrm_cmd_resp_dma_addr = 0;
2394 bp->hwrm_short_cmd_req_dma_addr = 0;
2397 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2399 struct rte_pci_device *pdev = bp->pdev;
2400 char type[RTE_MEMZONE_NAMESIZE];
2402 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2403 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2404 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2405 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2406 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2407 if (bp->hwrm_cmd_resp_addr == NULL)
2409 bp->hwrm_cmd_resp_dma_addr =
2410 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2411 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2413 "unable to map response address to physical memory\n");
2416 rte_spinlock_init(&bp->hwrm_lock);
2421 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2423 struct bnxt_filter_info *filter;
2426 STAILQ_FOREACH(filter, &vnic->filter, next) {
2427 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2428 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2429 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2430 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2432 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2433 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2434 bnxt_free_filter(bp, filter);
2442 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2444 struct bnxt_filter_info *filter;
2445 struct rte_flow *flow;
2448 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2449 flow = STAILQ_FIRST(&vnic->flow_list);
2450 filter = flow->filter;
2451 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2452 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2453 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2454 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2455 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2457 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2459 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2467 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2469 struct bnxt_filter_info *filter;
2472 STAILQ_FOREACH(filter, &vnic->filter, next) {
2473 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2474 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2476 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2477 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2480 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2491 void bnxt_free_tunnel_ports(struct bnxt *bp)
2493 if (bp->vxlan_port_cnt)
2494 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2495 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2497 if (bp->geneve_port_cnt)
2498 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2499 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2500 bp->geneve_port = 0;
2503 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2507 if (bp->vnic_info == NULL)
2511 * Cleanup VNICs in reverse order, to make sure the L2 filter
2512 * from vnic0 is last to be cleaned up.
2514 for (i = bp->max_vnics - 1; i >= 0; i--) {
2515 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2517 // If the VNIC ID is invalid we are not currently using the VNIC
2518 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2521 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2523 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2525 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2527 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2529 bnxt_hwrm_vnic_free(bp, vnic);
2531 rte_free(vnic->fw_grp_ids);
2533 /* Ring resources */
2534 bnxt_free_all_hwrm_rings(bp);
2535 bnxt_free_all_hwrm_ring_grps(bp);
2536 bnxt_free_all_hwrm_stat_ctxs(bp);
2537 bnxt_free_tunnel_ports(bp);
2540 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2542 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2544 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2545 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2547 switch (conf_link_speed) {
2548 case ETH_LINK_SPEED_10M_HD:
2549 case ETH_LINK_SPEED_100M_HD:
2551 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2553 return hw_link_duplex;
2556 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2558 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2561 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2563 uint16_t eth_link_speed = 0;
2565 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2566 return ETH_LINK_SPEED_AUTONEG;
2568 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2569 case ETH_LINK_SPEED_100M:
2570 case ETH_LINK_SPEED_100M_HD:
2573 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2575 case ETH_LINK_SPEED_1G:
2577 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2579 case ETH_LINK_SPEED_2_5G:
2581 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2583 case ETH_LINK_SPEED_10G:
2585 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2587 case ETH_LINK_SPEED_20G:
2589 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2591 case ETH_LINK_SPEED_25G:
2593 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2595 case ETH_LINK_SPEED_40G:
2597 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2599 case ETH_LINK_SPEED_50G:
2601 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2603 case ETH_LINK_SPEED_100G:
2605 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2609 "Unsupported link speed %d; default to AUTO\n",
2613 return eth_link_speed;
2616 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2617 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2618 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2619 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2621 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2625 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2628 if (link_speed & ETH_LINK_SPEED_FIXED) {
2629 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2631 if (one_speed & (one_speed - 1)) {
2633 "Invalid advertised speeds (%u) for port %u\n",
2634 link_speed, port_id);
2637 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2639 "Unsupported advertised speed (%u) for port %u\n",
2640 link_speed, port_id);
2644 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2646 "Unsupported advertised speeds (%u) for port %u\n",
2647 link_speed, port_id);
2655 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2659 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2660 if (bp->link_info.support_speeds)
2661 return bp->link_info.support_speeds;
2662 link_speed = BNXT_SUPPORTED_SPEEDS;
2665 if (link_speed & ETH_LINK_SPEED_100M)
2666 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2667 if (link_speed & ETH_LINK_SPEED_100M_HD)
2668 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2669 if (link_speed & ETH_LINK_SPEED_1G)
2670 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2671 if (link_speed & ETH_LINK_SPEED_2_5G)
2672 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2673 if (link_speed & ETH_LINK_SPEED_10G)
2674 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2675 if (link_speed & ETH_LINK_SPEED_20G)
2676 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2677 if (link_speed & ETH_LINK_SPEED_25G)
2678 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2679 if (link_speed & ETH_LINK_SPEED_40G)
2680 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2681 if (link_speed & ETH_LINK_SPEED_50G)
2682 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2683 if (link_speed & ETH_LINK_SPEED_100G)
2684 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2688 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2690 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2692 switch (hw_link_speed) {
2693 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2694 eth_link_speed = ETH_SPEED_NUM_100M;
2696 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2697 eth_link_speed = ETH_SPEED_NUM_1G;
2699 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2700 eth_link_speed = ETH_SPEED_NUM_2_5G;
2702 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2703 eth_link_speed = ETH_SPEED_NUM_10G;
2705 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2706 eth_link_speed = ETH_SPEED_NUM_20G;
2708 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2709 eth_link_speed = ETH_SPEED_NUM_25G;
2711 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2712 eth_link_speed = ETH_SPEED_NUM_40G;
2714 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2715 eth_link_speed = ETH_SPEED_NUM_50G;
2717 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2718 eth_link_speed = ETH_SPEED_NUM_100G;
2720 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2722 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2726 return eth_link_speed;
2729 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2731 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2733 switch (hw_link_duplex) {
2734 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2735 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2737 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2739 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2740 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2743 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2747 return eth_link_duplex;
2750 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2753 struct bnxt_link_info *link_info = &bp->link_info;
2755 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2758 "Get link config failed with rc %d\n", rc);
2761 if (link_info->link_speed)
2763 bnxt_parse_hw_link_speed(link_info->link_speed);
2765 link->link_speed = ETH_SPEED_NUM_NONE;
2766 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2767 link->link_status = link_info->link_up;
2768 link->link_autoneg = link_info->auto_mode ==
2769 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2770 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2775 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2778 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2779 struct bnxt_link_info link_req;
2780 uint16_t speed, autoneg;
2782 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2785 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2786 bp->eth_dev->data->port_id);
2790 memset(&link_req, 0, sizeof(link_req));
2791 link_req.link_up = link_up;
2795 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2796 if (BNXT_CHIP_THOR(bp) &&
2797 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2798 /* 40G is not supported as part of media auto detect.
2799 * The speed should be forced and autoneg disabled
2800 * to configure 40G speed.
2802 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2806 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2807 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2808 /* Autoneg can be done only when the FW allows.
2809 * When user configures fixed speed of 40G and later changes to
2810 * any other speed, auto_link_speed/force_link_speed is still set
2811 * to 40G until link comes up at new speed.
2814 !(!BNXT_CHIP_THOR(bp) &&
2815 (bp->link_info.auto_link_speed ||
2816 bp->link_info.force_link_speed))) {
2817 link_req.phy_flags |=
2818 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2819 link_req.auto_link_speed_mask =
2820 bnxt_parse_eth_link_speed_mask(bp,
2821 dev_conf->link_speeds);
2823 if (bp->link_info.phy_type ==
2824 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2825 bp->link_info.phy_type ==
2826 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2827 bp->link_info.media_type ==
2828 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2829 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2833 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2834 /* If user wants a particular speed try that first. */
2836 link_req.link_speed = speed;
2837 else if (bp->link_info.force_link_speed)
2838 link_req.link_speed = bp->link_info.force_link_speed;
2840 link_req.link_speed = bp->link_info.auto_link_speed;
2842 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2843 link_req.auto_pause = bp->link_info.auto_pause;
2844 link_req.force_pause = bp->link_info.force_pause;
2847 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2850 "Set link config failed with rc %d\n", rc);
2858 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2860 struct hwrm_func_qcfg_input req = {0};
2861 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2865 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2866 req.fid = rte_cpu_to_le_16(0xffff);
2868 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2870 HWRM_CHECK_RESULT();
2872 /* Hard Coded.. 0xfff VLAN ID mask */
2873 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2874 flags = rte_le_to_cpu_16(resp->flags);
2875 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2876 bp->flags |= BNXT_FLAG_MULTI_HOST;
2878 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2879 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2880 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2881 } else if (BNXT_VF(bp) &&
2882 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2883 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2884 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2890 switch (resp->port_partition_type) {
2891 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2892 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2893 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2895 bp->port_partition_type = resp->port_partition_type;
2898 bp->port_partition_type = 0;
2907 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2908 struct hwrm_func_qcaps_output *qcaps)
2910 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2911 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2912 sizeof(qcaps->mac_address));
2913 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2914 qcaps->max_rx_rings = fcfg->num_rx_rings;
2915 qcaps->max_tx_rings = fcfg->num_tx_rings;
2916 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2917 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2919 qcaps->first_vf_id = 0;
2920 qcaps->max_vnics = fcfg->num_vnics;
2921 qcaps->max_decap_records = 0;
2922 qcaps->max_encap_records = 0;
2923 qcaps->max_tx_wm_flows = 0;
2924 qcaps->max_tx_em_flows = 0;
2925 qcaps->max_rx_wm_flows = 0;
2926 qcaps->max_rx_em_flows = 0;
2927 qcaps->max_flow_id = 0;
2928 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2929 qcaps->max_sp_tx_rings = 0;
2930 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2933 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2935 struct hwrm_func_cfg_input req = {0};
2936 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2940 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2941 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2942 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2943 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2944 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2945 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2946 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2947 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2948 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2950 if (BNXT_HAS_RING_GRPS(bp)) {
2951 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2952 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2953 } else if (BNXT_HAS_NQ(bp)) {
2954 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2955 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2958 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2959 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2960 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2961 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2963 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2964 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2965 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2966 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2967 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2968 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2969 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2970 req.fid = rte_cpu_to_le_16(0xffff);
2971 req.enables = rte_cpu_to_le_32(enables);
2973 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2975 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2977 HWRM_CHECK_RESULT();
2983 static void populate_vf_func_cfg_req(struct bnxt *bp,
2984 struct hwrm_func_cfg_input *req,
2987 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2988 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2989 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2990 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2991 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2992 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2993 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2994 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2995 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2996 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2998 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2999 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3001 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3002 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3004 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3006 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3007 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3009 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3010 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3011 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3012 /* TODO: For now, do not support VMDq/RFS on VFs. */
3013 req->num_vnics = rte_cpu_to_le_16(1);
3014 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3018 static void add_random_mac_if_needed(struct bnxt *bp,
3019 struct hwrm_func_cfg_input *cfg_req,
3022 struct rte_ether_addr mac;
3024 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3027 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3029 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3030 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3031 bp->pf.vf_info[vf].random_mac = true;
3033 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3034 RTE_ETHER_ADDR_LEN);
3038 static void reserve_resources_from_vf(struct bnxt *bp,
3039 struct hwrm_func_cfg_input *cfg_req,
3042 struct hwrm_func_qcaps_input req = {0};
3043 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3046 /* Get the actual allocated values now */
3047 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3048 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3049 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3052 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3053 copy_func_cfg_to_qcaps(cfg_req, resp);
3054 } else if (resp->error_code) {
3055 rc = rte_le_to_cpu_16(resp->error_code);
3056 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3057 copy_func_cfg_to_qcaps(cfg_req, resp);
3060 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3061 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3062 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3063 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3064 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3065 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3067 * TODO: While not supporting VMDq with VFs, max_vnics is always
3068 * forced to 1 in this case
3070 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3071 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3076 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3078 struct hwrm_func_qcfg_input req = {0};
3079 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3082 /* Check for zero MAC address */
3083 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3084 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3085 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3086 HWRM_CHECK_RESULT();
3087 rc = rte_le_to_cpu_16(resp->vlan);
3094 static int update_pf_resource_max(struct bnxt *bp)
3096 struct hwrm_func_qcfg_input req = {0};
3097 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3100 /* And copy the allocated numbers into the pf struct */
3101 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3102 req.fid = rte_cpu_to_le_16(0xffff);
3103 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3104 HWRM_CHECK_RESULT();
3106 /* Only TX ring value reflects actual allocation? TODO */
3107 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3108 bp->pf.evb_mode = resp->evb_mode;
3115 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3120 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3124 rc = bnxt_hwrm_func_qcaps(bp);
3128 bp->pf.func_cfg_flags &=
3129 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3130 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3131 bp->pf.func_cfg_flags |=
3132 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3133 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3134 rc = __bnxt_hwrm_func_qcaps(bp);
3138 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3140 struct hwrm_func_cfg_input req = {0};
3141 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3148 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3152 rc = bnxt_hwrm_func_qcaps(bp);
3157 bp->pf.active_vfs = num_vfs;
3160 * First, configure the PF to only use one TX ring. This ensures that
3161 * there are enough rings for all VFs.
3163 * If we don't do this, when we call func_alloc() later, we will lock
3164 * extra rings to the PF that won't be available during func_cfg() of
3167 * This has been fixed with firmware versions above 20.6.54
3169 bp->pf.func_cfg_flags &=
3170 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3171 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3172 bp->pf.func_cfg_flags |=
3173 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3174 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3179 * Now, create and register a buffer to hold forwarded VF requests
3181 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3182 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3183 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3184 if (bp->pf.vf_req_buf == NULL) {
3188 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3189 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3190 for (i = 0; i < num_vfs; i++)
3191 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3192 (i * HWRM_MAX_REQ_LEN);
3194 rc = bnxt_hwrm_func_buf_rgtr(bp);
3198 populate_vf_func_cfg_req(bp, &req, num_vfs);
3200 bp->pf.active_vfs = 0;
3201 for (i = 0; i < num_vfs; i++) {
3202 add_random_mac_if_needed(bp, &req, i);
3204 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3205 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3206 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3207 rc = bnxt_hwrm_send_message(bp,
3212 /* Clear enable flag for next pass */
3213 req.enables &= ~rte_cpu_to_le_32(
3214 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3216 if (rc || resp->error_code) {
3218 "Failed to initizlie VF %d\n", i);
3220 "Not all VFs available. (%d, %d)\n",
3221 rc, resp->error_code);
3228 reserve_resources_from_vf(bp, &req, i);
3229 bp->pf.active_vfs++;
3230 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3234 * Now configure the PF to use "the rest" of the resources
3235 * We're using STD_TX_RING_MODE here though which will limit the TX
3236 * rings. This will allow QoS to function properly. Not setting this
3237 * will cause PF rings to break bandwidth settings.
3239 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3243 rc = update_pf_resource_max(bp);
3250 bnxt_hwrm_func_buf_unrgtr(bp);
3254 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3256 struct hwrm_func_cfg_input req = {0};
3257 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3260 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3262 req.fid = rte_cpu_to_le_16(0xffff);
3263 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3264 req.evb_mode = bp->pf.evb_mode;
3266 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3267 HWRM_CHECK_RESULT();
3273 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3274 uint8_t tunnel_type)
3276 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3277 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3280 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3281 req.tunnel_type = tunnel_type;
3282 req.tunnel_dst_port_val = port;
3283 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3284 HWRM_CHECK_RESULT();
3286 switch (tunnel_type) {
3287 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3288 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3289 bp->vxlan_port = port;
3291 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3292 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3293 bp->geneve_port = port;
3304 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3305 uint8_t tunnel_type)
3307 struct hwrm_tunnel_dst_port_free_input req = {0};
3308 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3311 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3313 req.tunnel_type = tunnel_type;
3314 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3315 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3317 HWRM_CHECK_RESULT();
3323 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3326 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3327 struct hwrm_func_cfg_input req = {0};
3330 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3332 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3333 req.flags = rte_cpu_to_le_32(flags);
3334 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3336 HWRM_CHECK_RESULT();
3342 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3344 uint32_t *flag = flagp;
3346 vnic->flags = *flag;
3349 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3351 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3354 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3357 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3358 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3360 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3362 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3363 req.req_buf_page_size = rte_cpu_to_le_16(
3364 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3365 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3366 req.req_buf_page_addr0 =
3367 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3368 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3370 "unable to map buffer address to physical memory\n");
3374 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3376 HWRM_CHECK_RESULT();
3382 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3385 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3386 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3388 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3391 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3393 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3395 HWRM_CHECK_RESULT();
3401 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3403 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3404 struct hwrm_func_cfg_input req = {0};
3407 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3409 req.fid = rte_cpu_to_le_16(0xffff);
3410 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3411 req.enables = rte_cpu_to_le_32(
3412 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3413 req.async_event_cr = rte_cpu_to_le_16(
3414 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3415 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3417 HWRM_CHECK_RESULT();
3423 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3425 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3426 struct hwrm_func_vf_cfg_input req = {0};
3429 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3431 req.enables = rte_cpu_to_le_32(
3432 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3433 req.async_event_cr = rte_cpu_to_le_16(
3434 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3435 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3437 HWRM_CHECK_RESULT();
3443 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3445 struct hwrm_func_cfg_input req = {0};
3446 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3447 uint16_t dflt_vlan, fid;
3448 uint32_t func_cfg_flags;
3451 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3454 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3455 fid = bp->pf.vf_info[vf].fid;
3456 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3458 fid = rte_cpu_to_le_16(0xffff);
3459 func_cfg_flags = bp->pf.func_cfg_flags;
3460 dflt_vlan = bp->vlan;
3463 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3464 req.fid = rte_cpu_to_le_16(fid);
3465 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3466 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3468 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3470 HWRM_CHECK_RESULT();
3476 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3477 uint16_t max_bw, uint16_t enables)
3479 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3480 struct hwrm_func_cfg_input req = {0};
3483 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3485 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3486 req.enables |= rte_cpu_to_le_32(enables);
3487 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3488 req.max_bw = rte_cpu_to_le_32(max_bw);
3489 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3491 HWRM_CHECK_RESULT();
3497 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3499 struct hwrm_func_cfg_input req = {0};
3500 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3503 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3505 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3506 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3507 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3508 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3510 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3512 HWRM_CHECK_RESULT();
3518 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3523 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3525 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3530 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3531 void *encaped, size_t ec_size)
3534 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3535 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3537 if (ec_size > sizeof(req.encap_request))
3540 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3542 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3543 memcpy(req.encap_request, encaped, ec_size);
3545 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3547 HWRM_CHECK_RESULT();
3553 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3554 struct rte_ether_addr *mac)
3556 struct hwrm_func_qcfg_input req = {0};
3557 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3560 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3562 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3563 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3565 HWRM_CHECK_RESULT();
3567 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3574 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3575 void *encaped, size_t ec_size)
3578 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3579 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3581 if (ec_size > sizeof(req.encap_request))
3584 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3586 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3587 memcpy(req.encap_request, encaped, ec_size);
3589 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3591 HWRM_CHECK_RESULT();
3597 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3598 struct rte_eth_stats *stats, uint8_t rx)
3601 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3602 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3604 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3606 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3608 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3610 HWRM_CHECK_RESULT();
3613 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3614 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3615 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3616 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3617 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3618 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3619 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3620 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3622 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3623 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3624 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3625 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3626 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3627 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3636 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3638 struct hwrm_port_qstats_input req = {0};
3639 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3640 struct bnxt_pf_info *pf = &bp->pf;
3643 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3645 req.port_id = rte_cpu_to_le_16(pf->port_id);
3646 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3647 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3648 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3650 HWRM_CHECK_RESULT();
3656 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3658 struct hwrm_port_clr_stats_input req = {0};
3659 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3660 struct bnxt_pf_info *pf = &bp->pf;
3663 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3664 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3665 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3668 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3670 req.port_id = rte_cpu_to_le_16(pf->port_id);
3671 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3673 HWRM_CHECK_RESULT();
3679 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3681 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3682 struct hwrm_port_led_qcaps_input req = {0};
3688 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3689 req.port_id = bp->pf.port_id;
3690 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3692 HWRM_CHECK_RESULT();
3694 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3697 bp->num_leds = resp->num_leds;
3698 memcpy(bp->leds, &resp->led0_id,
3699 sizeof(bp->leds[0]) * bp->num_leds);
3700 for (i = 0; i < bp->num_leds; i++) {
3701 struct bnxt_led_info *led = &bp->leds[i];
3703 uint16_t caps = led->led_state_caps;
3705 if (!led->led_group_id ||
3706 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3718 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3720 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3721 struct hwrm_port_led_cfg_input req = {0};
3722 struct bnxt_led_cfg *led_cfg;
3723 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3724 uint16_t duration = 0;
3727 if (!bp->num_leds || BNXT_VF(bp))
3730 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3733 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3734 duration = rte_cpu_to_le_16(500);
3736 req.port_id = bp->pf.port_id;
3737 req.num_leds = bp->num_leds;
3738 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3739 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3740 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3741 led_cfg->led_id = bp->leds[i].led_id;
3742 led_cfg->led_state = led_state;
3743 led_cfg->led_blink_on = duration;
3744 led_cfg->led_blink_off = duration;
3745 led_cfg->led_group_id = bp->leds[i].led_group_id;
3748 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3750 HWRM_CHECK_RESULT();
3756 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3760 struct hwrm_nvm_get_dir_info_input req = {0};
3761 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3763 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3765 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3767 HWRM_CHECK_RESULT();
3769 *entries = rte_le_to_cpu_32(resp->entries);
3770 *length = rte_le_to_cpu_32(resp->entry_length);
3776 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3779 uint32_t dir_entries;
3780 uint32_t entry_length;
3783 rte_iova_t dma_handle;
3784 struct hwrm_nvm_get_dir_entries_input req = {0};
3785 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3787 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3791 *data++ = dir_entries;
3792 *data++ = entry_length;
3794 memset(data, 0xff, len);
3796 buflen = dir_entries * entry_length;
3797 buf = rte_malloc("nvm_dir", buflen, 0);
3798 rte_mem_lock_page(buf);
3801 dma_handle = rte_mem_virt2iova(buf);
3802 if (dma_handle == RTE_BAD_IOVA) {
3804 "unable to map response address to physical memory\n");
3807 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3808 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3809 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3812 memcpy(data, buf, len > buflen ? buflen : len);
3815 HWRM_CHECK_RESULT();
3821 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3822 uint32_t offset, uint32_t length,
3827 rte_iova_t dma_handle;
3828 struct hwrm_nvm_read_input req = {0};
3829 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3831 buf = rte_malloc("nvm_item", length, 0);
3832 rte_mem_lock_page(buf);
3836 dma_handle = rte_mem_virt2iova(buf);
3837 if (dma_handle == RTE_BAD_IOVA) {
3839 "unable to map response address to physical memory\n");
3842 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3843 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3844 req.dir_idx = rte_cpu_to_le_16(index);
3845 req.offset = rte_cpu_to_le_32(offset);
3846 req.len = rte_cpu_to_le_32(length);
3847 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3849 memcpy(data, buf, length);
3852 HWRM_CHECK_RESULT();
3858 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3861 struct hwrm_nvm_erase_dir_entry_input req = {0};
3862 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3864 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3865 req.dir_idx = rte_cpu_to_le_16(index);
3866 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3867 HWRM_CHECK_RESULT();
3874 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3875 uint16_t dir_ordinal, uint16_t dir_ext,
3876 uint16_t dir_attr, const uint8_t *data,
3880 struct hwrm_nvm_write_input req = {0};
3881 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3882 rte_iova_t dma_handle;
3885 buf = rte_malloc("nvm_write", data_len, 0);
3886 rte_mem_lock_page(buf);
3890 dma_handle = rte_mem_virt2iova(buf);
3891 if (dma_handle == RTE_BAD_IOVA) {
3893 "unable to map response address to physical memory\n");
3896 memcpy(buf, data, data_len);
3898 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3900 req.dir_type = rte_cpu_to_le_16(dir_type);
3901 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3902 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3903 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3904 req.dir_data_length = rte_cpu_to_le_32(data_len);
3905 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3907 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3910 HWRM_CHECK_RESULT();
3917 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3919 uint32_t *count = cbdata;
3921 *count = *count + 1;
3924 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3925 struct bnxt_vnic_info *vnic __rte_unused)
3930 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3934 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3935 &count, bnxt_vnic_count_hwrm_stub);
3940 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3943 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3944 struct hwrm_func_vf_vnic_ids_query_output *resp =
3945 bp->hwrm_cmd_resp_addr;
3948 /* First query all VNIC ids */
3949 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3951 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3952 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3953 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3955 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3958 "unable to map VNIC ID table address to physical memory\n");
3961 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3962 HWRM_CHECK_RESULT();
3963 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3971 * This function queries the VNIC IDs for a specified VF. It then calls
3972 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3973 * Then it calls the hwrm_cb function to program this new vnic configuration.
3975 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3976 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3977 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3979 struct bnxt_vnic_info vnic;
3981 int i, num_vnic_ids;
3986 /* First query all VNIC ids */
3987 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3988 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3989 RTE_CACHE_LINE_SIZE);
3990 if (vnic_ids == NULL)
3993 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3994 rte_mem_lock_page(((char *)vnic_ids) + sz);
3996 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3998 if (num_vnic_ids < 0)
3999 return num_vnic_ids;
4001 /* Retrieve VNIC, update bd_stall then update */
4003 for (i = 0; i < num_vnic_ids; i++) {
4004 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4005 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4006 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4009 if (vnic.mru <= 4) /* Indicates unallocated */
4012 vnic_cb(&vnic, cbdata);
4014 rc = hwrm_cb(bp, &vnic);
4024 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4027 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4028 struct hwrm_func_cfg_input req = {0};
4031 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4033 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4034 req.enables |= rte_cpu_to_le_32(
4035 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4036 req.vlan_antispoof_mode = on ?
4037 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4038 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4039 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4041 HWRM_CHECK_RESULT();
4047 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4049 struct bnxt_vnic_info vnic;
4052 int num_vnic_ids, i;
4056 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4057 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4058 RTE_CACHE_LINE_SIZE);
4059 if (vnic_ids == NULL)
4062 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4063 rte_mem_lock_page(((char *)vnic_ids) + sz);
4065 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4071 * Loop through to find the default VNIC ID.
4072 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4073 * by sending the hwrm_func_qcfg command to the firmware.
4075 for (i = 0; i < num_vnic_ids; i++) {
4076 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4077 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4078 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4079 bp->pf.first_vf_id + vf);
4082 if (vnic.func_default) {
4084 return vnic.fw_vnic_id;
4087 /* Could not find a default VNIC. */
4088 PMD_DRV_LOG(ERR, "No default VNIC\n");
4094 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4096 struct bnxt_filter_info *filter)
4099 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4100 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4101 uint32_t enables = 0;
4103 if (filter->fw_em_filter_id != UINT64_MAX)
4104 bnxt_hwrm_clear_em_filter(bp, filter);
4106 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4108 req.flags = rte_cpu_to_le_32(filter->flags);
4110 enables = filter->enables |
4111 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4112 req.dst_id = rte_cpu_to_le_16(dst_id);
4114 if (filter->ip_addr_type) {
4115 req.ip_addr_type = filter->ip_addr_type;
4116 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4119 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4120 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4122 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4123 memcpy(req.src_macaddr, filter->src_macaddr,
4124 RTE_ETHER_ADDR_LEN);
4126 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4127 memcpy(req.dst_macaddr, filter->dst_macaddr,
4128 RTE_ETHER_ADDR_LEN);
4130 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4131 req.ovlan_vid = filter->l2_ovlan;
4133 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4134 req.ivlan_vid = filter->l2_ivlan;
4136 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4137 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4139 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4140 req.ip_protocol = filter->ip_protocol;
4142 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4143 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4145 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4146 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4148 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4149 req.src_port = rte_cpu_to_be_16(filter->src_port);
4151 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4152 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4154 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4155 req.mirror_vnic_id = filter->mirror_vnic_id;
4157 req.enables = rte_cpu_to_le_32(enables);
4159 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4161 HWRM_CHECK_RESULT();
4163 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4169 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4172 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4173 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4175 if (filter->fw_em_filter_id == UINT64_MAX)
4178 PMD_DRV_LOG(ERR, "Clear EM filter\n");
4179 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4181 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4183 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4185 HWRM_CHECK_RESULT();
4188 filter->fw_em_filter_id = UINT64_MAX;
4189 filter->fw_l2_filter_id = UINT64_MAX;
4194 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4196 struct bnxt_filter_info *filter)
4199 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4200 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4201 bp->hwrm_cmd_resp_addr;
4202 uint32_t enables = 0;
4204 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4205 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4207 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4209 req.flags = rte_cpu_to_le_32(filter->flags);
4211 enables = filter->enables |
4212 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4213 req.dst_id = rte_cpu_to_le_16(dst_id);
4216 if (filter->ip_addr_type) {
4217 req.ip_addr_type = filter->ip_addr_type;
4219 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4222 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4223 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4225 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4226 memcpy(req.src_macaddr, filter->src_macaddr,
4227 RTE_ETHER_ADDR_LEN);
4229 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4230 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4231 //RTE_ETHER_ADDR_LEN);
4233 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4234 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4236 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4237 req.ip_protocol = filter->ip_protocol;
4239 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4240 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4242 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4243 req.src_ipaddr_mask[0] =
4244 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4246 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4247 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4249 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4250 req.dst_ipaddr_mask[0] =
4251 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4253 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4254 req.src_port = rte_cpu_to_le_16(filter->src_port);
4256 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4257 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4259 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4260 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4262 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4263 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4265 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4266 req.mirror_vnic_id = filter->mirror_vnic_id;
4268 req.enables = rte_cpu_to_le_32(enables);
4270 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4272 HWRM_CHECK_RESULT();
4274 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4280 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4281 struct bnxt_filter_info *filter)
4284 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4285 struct hwrm_cfa_ntuple_filter_free_output *resp =
4286 bp->hwrm_cmd_resp_addr;
4288 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4291 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4293 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4295 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4297 HWRM_CHECK_RESULT();
4300 filter->fw_ntuple_filter_id = UINT64_MAX;
4306 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4308 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4309 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4310 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4311 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4312 uint16_t *ring_tbl = vnic->rss_table;
4313 int nr_ctxs = vnic->num_lb_ctxts;
4314 int max_rings = bp->rx_nr_rings;
4318 for (i = 0, k = 0; i < nr_ctxs; i++) {
4319 struct bnxt_rx_ring_info *rxr;
4320 struct bnxt_cp_ring_info *cpr;
4322 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4324 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4325 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4326 req.hash_mode_flags = vnic->hash_mode;
4328 req.ring_grp_tbl_addr =
4329 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4330 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4331 2 * sizeof(*ring_tbl));
4332 req.hash_key_tbl_addr =
4333 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4335 req.ring_table_pair_index = i;
4336 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4338 for (j = 0; j < 64; j++) {
4341 /* Find next active ring. */
4342 for (cnt = 0; cnt < max_rings; cnt++) {
4343 if (rx_queue_state[k] !=
4344 RTE_ETH_QUEUE_STATE_STOPPED)
4346 if (++k == max_rings)
4350 /* Return if no rings are active. */
4351 if (cnt == max_rings)
4354 /* Add rx/cp ring pair to RSS table. */
4355 rxr = rxqs[k]->rx_ring;
4356 cpr = rxqs[k]->cp_ring;
4358 ring_id = rxr->rx_ring_struct->fw_ring_id;
4359 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4360 ring_id = cpr->cp_ring_struct->fw_ring_id;
4361 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4363 if (++k == max_rings)
4366 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4369 HWRM_CHECK_RESULT();
4376 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4378 unsigned int rss_idx, fw_idx, i;
4380 if (!(vnic->rss_table && vnic->hash_type))
4383 if (BNXT_CHIP_THOR(bp))
4384 return bnxt_vnic_rss_configure_thor(bp, vnic);
4386 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4389 if (vnic->rss_table && vnic->hash_type) {
4391 * Fill the RSS hash & redirection table with
4392 * ring group ids for all VNICs
4394 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4395 rss_idx++, fw_idx++) {
4396 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4397 fw_idx %= bp->rx_cp_nr_rings;
4398 if (vnic->fw_grp_ids[fw_idx] !=
4403 if (i == bp->rx_cp_nr_rings)
4405 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4407 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4413 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4414 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4418 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4420 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4421 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4423 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4424 req->num_cmpl_dma_aggr_during_int =
4425 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4427 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4429 /* min timer set to 1/2 of interrupt timer */
4430 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4432 /* buf timer set to 1/4 of interrupt timer */
4433 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4435 req->cmpl_aggr_dma_tmr_during_int =
4436 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4438 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4439 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4440 req->flags = rte_cpu_to_le_16(flags);
4443 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4444 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4446 struct hwrm_ring_aggint_qcaps_input req = {0};
4447 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4452 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4453 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4454 HWRM_CHECK_RESULT();
4456 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4457 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4459 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4460 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4461 agg_req->flags = rte_cpu_to_le_16(flags);
4463 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4464 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4465 agg_req->enables = rte_cpu_to_le_32(enables);
4471 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4472 struct bnxt_coal *coal, uint16_t ring_id)
4474 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4475 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4476 bp->hwrm_cmd_resp_addr;
4479 /* Set ring coalesce parameters only for 100G NICs */
4480 if (BNXT_CHIP_THOR(bp)) {
4481 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4483 } else if (bnxt_stratus_device(bp)) {
4484 bnxt_hwrm_set_coal_params(coal, &req);
4489 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4490 req.ring_id = rte_cpu_to_le_16(ring_id);
4491 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4492 HWRM_CHECK_RESULT();
4497 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4498 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4500 struct hwrm_func_backing_store_qcaps_input req = {0};
4501 struct hwrm_func_backing_store_qcaps_output *resp =
4502 bp->hwrm_cmd_resp_addr;
4503 struct bnxt_ctx_pg_info *ctx_pg;
4504 struct bnxt_ctx_mem_info *ctx;
4505 int total_alloc_len;
4508 if (!BNXT_CHIP_THOR(bp) ||
4509 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4514 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4515 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4516 HWRM_CHECK_RESULT_SILENT();
4518 total_alloc_len = sizeof(*ctx);
4519 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4520 RTE_CACHE_LINE_SIZE);
4526 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4527 sizeof(*ctx_pg) * BNXT_MAX_Q,
4528 RTE_CACHE_LINE_SIZE);
4533 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4534 ctx->tqm_mem[i] = ctx_pg;
4537 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4538 ctx->qp_min_qp1_entries =
4539 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4540 ctx->qp_max_l2_entries =
4541 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4542 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4543 ctx->srq_max_l2_entries =
4544 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4545 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4546 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4547 ctx->cq_max_l2_entries =
4548 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4549 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4550 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4551 ctx->vnic_max_vnic_entries =
4552 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4553 ctx->vnic_max_ring_table_entries =
4554 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4555 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4556 ctx->stat_max_entries =
4557 rte_le_to_cpu_32(resp->stat_max_entries);
4558 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4559 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4560 ctx->tqm_min_entries_per_ring =
4561 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4562 ctx->tqm_max_entries_per_ring =
4563 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4564 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4565 if (!ctx->tqm_entries_multiple)
4566 ctx->tqm_entries_multiple = 1;
4567 ctx->mrav_max_entries =
4568 rte_le_to_cpu_32(resp->mrav_max_entries);
4569 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4570 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4571 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4577 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4579 struct hwrm_func_backing_store_cfg_input req = {0};
4580 struct hwrm_func_backing_store_cfg_output *resp =
4581 bp->hwrm_cmd_resp_addr;
4582 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4583 struct bnxt_ctx_pg_info *ctx_pg;
4584 uint32_t *num_entries;
4593 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4594 req.enables = rte_cpu_to_le_32(enables);
4596 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4597 ctx_pg = &ctx->qp_mem;
4598 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4599 req.qp_num_qp1_entries =
4600 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4601 req.qp_num_l2_entries =
4602 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4603 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4604 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4605 &req.qpc_pg_size_qpc_lvl,
4609 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4610 ctx_pg = &ctx->srq_mem;
4611 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4612 req.srq_num_l2_entries =
4613 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4614 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4615 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4616 &req.srq_pg_size_srq_lvl,
4620 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4621 ctx_pg = &ctx->cq_mem;
4622 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4623 req.cq_num_l2_entries =
4624 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4625 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4626 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4627 &req.cq_pg_size_cq_lvl,
4631 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4632 ctx_pg = &ctx->vnic_mem;
4633 req.vnic_num_vnic_entries =
4634 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4635 req.vnic_num_ring_table_entries =
4636 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4637 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4638 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4639 &req.vnic_pg_size_vnic_lvl,
4640 &req.vnic_page_dir);
4643 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4644 ctx_pg = &ctx->stat_mem;
4645 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4646 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4647 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4648 &req.stat_pg_size_stat_lvl,
4649 &req.stat_page_dir);
4652 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4653 num_entries = &req.tqm_sp_num_entries;
4654 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4655 pg_dir = &req.tqm_sp_page_dir;
4656 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4657 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4658 if (!(enables & ena))
4661 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4663 ctx_pg = ctx->tqm_mem[i];
4664 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4665 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4668 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4669 HWRM_CHECK_RESULT();
4675 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4677 struct hwrm_port_qstats_ext_input req = {0};
4678 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4679 struct bnxt_pf_info *pf = &bp->pf;
4682 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4683 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4686 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4688 req.port_id = rte_cpu_to_le_16(pf->port_id);
4689 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4690 req.tx_stat_host_addr =
4691 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4693 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4695 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4696 req.rx_stat_host_addr =
4697 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4699 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4701 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4704 bp->fw_rx_port_stats_ext_size = 0;
4705 bp->fw_tx_port_stats_ext_size = 0;
4707 bp->fw_rx_port_stats_ext_size =
4708 rte_le_to_cpu_16(resp->rx_stat_size);
4709 bp->fw_tx_port_stats_ext_size =
4710 rte_le_to_cpu_16(resp->tx_stat_size);
4713 HWRM_CHECK_RESULT();
4720 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4722 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4723 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4724 bp->hwrm_cmd_resp_addr;
4727 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4728 req.tunnel_type = type;
4729 req.dest_fid = bp->fw_fid;
4730 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4731 HWRM_CHECK_RESULT();
4739 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4741 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4742 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4743 bp->hwrm_cmd_resp_addr;
4746 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4747 req.tunnel_type = type;
4748 req.dest_fid = bp->fw_fid;
4749 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4750 HWRM_CHECK_RESULT();
4757 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4759 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4760 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4761 bp->hwrm_cmd_resp_addr;
4764 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4765 req.src_fid = bp->fw_fid;
4766 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4767 HWRM_CHECK_RESULT();
4770 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4777 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4780 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4781 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4782 bp->hwrm_cmd_resp_addr;
4785 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4786 req.src_fid = bp->fw_fid;
4787 req.tunnel_type = tun_type;
4788 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4789 HWRM_CHECK_RESULT();
4792 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4794 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4801 int bnxt_hwrm_set_mac(struct bnxt *bp)
4803 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4804 struct hwrm_func_vf_cfg_input req = {0};
4810 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4813 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4814 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4816 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4818 HWRM_CHECK_RESULT();
4820 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4826 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4828 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4829 struct hwrm_func_drv_if_change_input req = {0};
4833 if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4836 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4837 * If we issue FUNC_DRV_IF_CHANGE with flags down before
4838 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4840 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4843 HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4847 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4849 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4851 HWRM_CHECK_RESULT();
4852 flags = rte_le_to_cpu_32(resp->flags);
4855 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4856 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4857 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4863 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4865 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4866 struct bnxt_error_recovery_info *info = bp->recovery_info;
4867 struct hwrm_error_recovery_qcfg_input req = {0};
4872 /* Older FW does not have error recovery support */
4873 if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4877 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4879 bp->recovery_info = info;
4883 memset(info, 0, sizeof(*info));
4886 HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4888 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4890 HWRM_CHECK_RESULT();
4892 flags = rte_le_to_cpu_32(resp->flags);
4893 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4894 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4895 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4896 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4898 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4899 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4904 /* FW returned values are in units of 100msec */
4905 info->driver_polling_freq =
4906 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4907 info->master_func_wait_period =
4908 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4909 info->normal_func_wait_period =
4910 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4911 info->master_func_wait_period_after_reset =
4912 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4913 info->max_bailout_time_after_reset =
4914 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4915 info->status_regs[BNXT_FW_STATUS_REG] =
4916 rte_le_to_cpu_32(resp->fw_health_status_reg);
4917 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4918 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4919 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4920 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4921 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4922 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4923 info->reg_array_cnt =
4924 rte_le_to_cpu_32(resp->reg_array_cnt);
4926 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4931 for (i = 0; i < info->reg_array_cnt; i++) {
4932 info->reset_reg[i] =
4933 rte_le_to_cpu_32(resp->reset_reg[i]);
4934 info->reset_reg_val[i] =
4935 rte_le_to_cpu_32(resp->reset_reg_val[i]);
4936 info->delay_after_reset[i] =
4937 resp->delay_after_reset[i];
4942 /* Map the FW status registers */
4944 rc = bnxt_map_fw_health_status_regs(bp);
4947 rte_free(bp->recovery_info);
4948 bp->recovery_info = NULL;
4953 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4955 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4956 struct hwrm_fw_reset_input req = {0};
4962 HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4964 req.embedded_proc_type =
4965 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4966 req.selfrst_status =
4967 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4968 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4970 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4973 HWRM_CHECK_RESULT();
4979 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4981 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4982 struct hwrm_port_ts_query_input req = {0};
4983 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4990 HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4993 case BNXT_PTP_FLAGS_PATH_TX:
4994 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4996 case BNXT_PTP_FLAGS_PATH_RX:
4997 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4999 case BNXT_PTP_FLAGS_CURRENT_TIME:
5000 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5004 req.flags = rte_cpu_to_le_32(flags);
5005 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5007 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5009 HWRM_CHECK_RESULT();
5012 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5014 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5021 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5023 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5024 bp->hwrm_cmd_resp_addr;
5025 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5029 if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5032 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5034 "Not a PF or trusted VF. Command not supported\n");
5038 HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5039 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5041 HWRM_CHECK_RESULT();
5042 flags = rte_le_to_cpu_32(resp->flags);
5045 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5046 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5047 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");