1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SPEC_CODE_1_8_3 0x10803
31 #define HWRM_VERSION_1_9_1 0x10901
32 #define HWRM_VERSION_1_9_2 0x10903
34 struct bnxt_plcmodes_cfg {
36 uint16_t jumbo_thresh;
38 uint16_t hds_threshold;
41 static int page_getenum(size_t size)
57 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
58 return sizeof(void *) * 8 - 1;
61 static int page_roundup(size_t size)
63 return 1 << page_getenum(size);
66 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
70 if (rmem->nr_pages > 1) {
72 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
74 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
79 * HWRM Functions (sent to HWRM)
80 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
81 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
82 * command was failed by the ChiMP.
85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
86 uint32_t msg_len, bool use_kong_mb)
89 struct input *req = msg;
90 struct output *resp = bp->hwrm_cmd_resp_addr;
94 uint16_t max_req_len = bp->max_req_len;
95 struct hwrm_short_input short_input = { 0 };
96 uint16_t bar_offset = use_kong_mb ?
97 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
98 uint16_t mb_trigger_offset = use_kong_mb ?
99 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
101 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
102 msg_len > bp->max_req_len) {
103 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
105 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
106 memcpy(short_cmd_req, req, msg_len);
108 short_input.req_type = rte_cpu_to_le_16(req->req_type);
109 short_input.signature = rte_cpu_to_le_16(
110 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
111 short_input.size = rte_cpu_to_le_16(msg_len);
112 short_input.req_addr =
113 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
115 data = (uint32_t *)&short_input;
116 msg_len = sizeof(short_input);
118 /* Sync memory write before updating doorbell */
121 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
124 /* Write request msg to hwrm channel */
125 for (i = 0; i < msg_len; i += 4) {
126 bar = (uint8_t *)bp->bar0 + bar_offset + i;
127 rte_write32(*data, bar);
131 /* Zero the rest of the request space */
132 for (; i < max_req_len; i += 4) {
133 bar = (uint8_t *)bp->bar0 + bar_offset + i;
137 /* Ring channel doorbell */
138 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
141 /* Poll for the valid bit */
142 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
143 /* Sanity check on the resp->resp_len */
145 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
146 /* Last byte of resp contains the valid key */
147 valid = (uint8_t *)resp + resp->resp_len - 1;
148 if (*valid == HWRM_RESP_VALID_KEY)
154 if (i >= HWRM_CMD_TIMEOUT) {
155 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
166 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
167 * spinlock, and does initial processing.
169 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
170 * releases the spinlock only if it returns. If the regular int return codes
171 * are not used by the function, HWRM_CHECK_RESULT() should not be used
172 * directly, rather it should be copied and modified to suit the function.
174 * HWRM_UNLOCK() must be called after all response processing is completed.
176 #define HWRM_PREP(req, type, kong) do { \
177 rte_spinlock_lock(&bp->hwrm_lock); \
178 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
179 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
180 req.cmpl_ring = rte_cpu_to_le_16(-1); \
181 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
182 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
183 req.target_id = rte_cpu_to_le_16(0xffff); \
184 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
187 #define HWRM_CHECK_RESULT_SILENT() do {\
189 rte_spinlock_unlock(&bp->hwrm_lock); \
192 if (resp->error_code) { \
193 rc = rte_le_to_cpu_16(resp->error_code); \
194 rte_spinlock_unlock(&bp->hwrm_lock); \
199 #define HWRM_CHECK_RESULT() do {\
201 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
202 rte_spinlock_unlock(&bp->hwrm_lock); \
203 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
209 if (resp->error_code) { \
210 rc = rte_le_to_cpu_16(resp->error_code); \
211 if (resp->resp_len >= 16) { \
212 struct hwrm_err_output *tmp_hwrm_err_op = \
215 "error %d:%d:%08x:%04x\n", \
216 rc, tmp_hwrm_err_op->cmd_err, \
218 tmp_hwrm_err_op->opaque_0), \
220 tmp_hwrm_err_op->opaque_1)); \
222 PMD_DRV_LOG(ERR, "error %d\n", rc); \
224 rte_spinlock_unlock(&bp->hwrm_lock); \
225 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
233 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
235 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
238 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
239 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
241 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
242 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
245 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
253 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
254 struct bnxt_vnic_info *vnic,
256 struct bnxt_vlan_table_entry *vlan_table)
259 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
260 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
263 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
266 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
267 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
269 /* FIXME add multicast flag, when multicast adding options is supported
272 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
273 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
274 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
275 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
276 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
277 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
278 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
279 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
280 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
281 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
282 if (vnic->mc_addr_cnt) {
283 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
284 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
285 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
288 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
289 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
290 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
291 rte_mem_virt2iova(vlan_table));
292 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
294 req.mask = rte_cpu_to_le_32(mask);
296 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
304 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
306 struct bnxt_vlan_antispoof_table_entry *vlan_table)
309 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
310 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
311 bp->hwrm_cmd_resp_addr;
314 * Older HWRM versions did not support this command, and the set_rx_mask
315 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
316 * removed from set_rx_mask call, and this command was added.
318 * This command is also present from 1.7.8.11 and higher,
321 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
322 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
323 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
328 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
329 req.fid = rte_cpu_to_le_16(fid);
331 req.vlan_tag_mask_tbl_addr =
332 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
333 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
335 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
343 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
344 struct bnxt_filter_info *filter)
347 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
348 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
350 if (filter->fw_l2_filter_id == UINT64_MAX)
353 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
355 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
362 filter->fw_l2_filter_id = UINT64_MAX;
367 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
369 struct bnxt_filter_info *filter)
372 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
373 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
374 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
375 const struct rte_eth_vmdq_rx_conf *conf =
376 &dev_conf->rx_adv_conf.vmdq_rx_conf;
377 uint32_t enables = 0;
378 uint16_t j = dst_id - 1;
380 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
381 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
382 conf->pool_map[j].pools & (1UL << j)) {
384 "Add vlan %u to vmdq pool %u\n",
385 conf->pool_map[j].vlan_id, j);
387 filter->l2_ivlan = conf->pool_map[j].vlan_id;
389 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
390 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
393 if (filter->fw_l2_filter_id != UINT64_MAX)
394 bnxt_hwrm_clear_l2_filter(bp, filter);
396 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
398 req.flags = rte_cpu_to_le_32(filter->flags);
400 rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
402 enables = filter->enables |
403 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
404 req.dst_id = rte_cpu_to_le_16(dst_id);
407 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
408 memcpy(req.l2_addr, filter->l2_addr,
411 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
412 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
415 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
416 req.l2_ovlan = filter->l2_ovlan;
418 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
419 req.l2_ivlan = filter->l2_ivlan;
421 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
422 req.l2_ovlan_mask = filter->l2_ovlan_mask;
424 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
425 req.l2_ivlan_mask = filter->l2_ivlan_mask;
426 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
427 req.src_id = rte_cpu_to_le_32(filter->src_id);
428 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
429 req.src_type = filter->src_type;
431 req.enables = rte_cpu_to_le_32(enables);
433 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
437 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
443 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
445 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
446 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
453 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
456 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
459 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
460 if (ptp->tx_tstamp_en)
461 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
464 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
465 req.flags = rte_cpu_to_le_32(flags);
466 req.enables = rte_cpu_to_le_32
467 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
468 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
470 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
476 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
479 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
480 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
481 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
483 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
487 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
489 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
491 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
495 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
498 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
502 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
503 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
504 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
505 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
506 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
507 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
508 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
509 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
510 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
511 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
512 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
513 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
514 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
515 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
516 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
517 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
518 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
519 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
527 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
530 struct hwrm_func_qcaps_input req = {.req_type = 0 };
531 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
532 uint16_t new_max_vfs;
536 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
538 req.fid = rte_cpu_to_le_16(0xffff);
540 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
544 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
545 flags = rte_le_to_cpu_32(resp->flags);
547 bp->pf.port_id = resp->port_id;
548 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
549 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
550 new_max_vfs = bp->pdev->max_vfs;
551 if (new_max_vfs != bp->pf.max_vfs) {
553 rte_free(bp->pf.vf_info);
554 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
555 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
556 bp->pf.max_vfs = new_max_vfs;
557 for (i = 0; i < new_max_vfs; i++) {
558 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
559 bp->pf.vf_info[i].vlan_table =
560 rte_zmalloc("VF VLAN table",
563 if (bp->pf.vf_info[i].vlan_table == NULL)
565 "Fail to alloc VLAN table for VF %d\n",
569 bp->pf.vf_info[i].vlan_table);
570 bp->pf.vf_info[i].vlan_as_table =
571 rte_zmalloc("VF VLAN AS table",
574 if (bp->pf.vf_info[i].vlan_as_table == NULL)
576 "Alloc VLAN AS table for VF %d fail\n",
580 bp->pf.vf_info[i].vlan_as_table);
581 STAILQ_INIT(&bp->pf.vf_info[i].filter);
586 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
587 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
588 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
589 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
590 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
591 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
592 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
593 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
594 /* TODO: For now, do not support VMDq/RFS on VFs. */
599 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
603 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
605 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
606 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
607 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
608 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
610 bnxt_hwrm_ptp_qcfg(bp);
614 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
615 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
622 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
626 rc = __bnxt_hwrm_func_qcaps(bp);
627 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
628 rc = bnxt_alloc_ctx_mem(bp);
632 rc = bnxt_hwrm_func_resc_qcaps(bp);
634 bp->flags |= BNXT_FLAG_NEW_RM;
640 int bnxt_hwrm_func_reset(struct bnxt *bp)
643 struct hwrm_func_reset_input req = {.req_type = 0 };
644 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
646 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
648 req.enables = rte_cpu_to_le_32(0);
650 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
658 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
661 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
662 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
664 if (bp->flags & BNXT_FLAG_REGISTERED)
667 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
668 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
669 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
670 req.ver_maj = RTE_VER_YEAR;
671 req.ver_min = RTE_VER_MONTH;
672 req.ver_upd = RTE_VER_MINOR;
675 req.enables |= rte_cpu_to_le_32(
676 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
677 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
678 RTE_MIN(sizeof(req.vf_req_fwd),
679 sizeof(bp->pf.vf_req_fwd)));
682 * PF can sniff HWRM API issued by VF. This can be set up by
683 * linux driver and inherited by the DPDK PF driver. Clear
684 * this HWRM sniffer list in FW because DPDK PF driver does
688 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
691 req.async_event_fwd[0] |=
692 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
693 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
694 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
695 req.async_event_fwd[1] |=
696 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
697 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
699 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
704 bp->flags |= BNXT_FLAG_REGISTERED;
709 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
711 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
714 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
717 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
722 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
723 struct hwrm_func_vf_cfg_input req = {0};
725 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
727 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
728 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
729 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
730 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
731 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
733 if (BNXT_HAS_RING_GRPS(bp)) {
734 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
735 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
738 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
739 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
740 AGG_RING_MULTIPLIER);
741 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
742 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
744 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
745 if (bp->vf_resv_strategy ==
746 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
747 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
748 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
749 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
750 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
751 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
752 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
756 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
757 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
758 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
759 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
760 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
761 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
763 if (test && BNXT_HAS_RING_GRPS(bp))
764 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
766 req.flags = rte_cpu_to_le_32(flags);
767 req.enables |= rte_cpu_to_le_32(enables);
769 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
772 HWRM_CHECK_RESULT_SILENT();
780 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
783 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
784 struct hwrm_func_resource_qcaps_input req = {0};
786 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
787 req.fid = rte_cpu_to_le_16(0xffff);
789 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
794 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
795 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
796 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
797 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
798 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
799 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
800 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
801 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
803 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
804 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
805 if (bp->vf_resv_strategy >
806 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
807 bp->vf_resv_strategy =
808 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
814 int bnxt_hwrm_ver_get(struct bnxt *bp)
817 struct hwrm_ver_get_input req = {.req_type = 0 };
818 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
820 uint16_t max_resp_len;
821 char type[RTE_MEMZONE_NAMESIZE];
822 uint32_t dev_caps_cfg;
824 bp->max_req_len = HWRM_MAX_REQ_LEN;
825 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
827 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
828 req.hwrm_intf_min = HWRM_VERSION_MINOR;
829 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
831 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
835 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
836 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
837 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
838 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
839 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
840 (resp->hwrm_fw_min_8b << 16) |
841 (resp->hwrm_fw_bld_8b << 8) |
842 resp->hwrm_fw_rsvd_8b;
843 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
844 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
846 fw_version = resp->hwrm_intf_maj_8b << 16;
847 fw_version |= resp->hwrm_intf_min_8b << 8;
848 fw_version |= resp->hwrm_intf_upd_8b;
849 bp->hwrm_spec_code = fw_version;
851 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
852 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
857 if (bp->max_req_len > resp->max_req_win_len) {
858 PMD_DRV_LOG(ERR, "Unsupported request length\n");
861 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
862 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
863 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
864 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
866 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
867 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
869 if (bp->max_resp_len != max_resp_len) {
870 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
871 bp->pdev->addr.domain, bp->pdev->addr.bus,
872 bp->pdev->addr.devid, bp->pdev->addr.function);
874 rte_free(bp->hwrm_cmd_resp_addr);
876 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
877 if (bp->hwrm_cmd_resp_addr == NULL) {
881 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
882 bp->hwrm_cmd_resp_dma_addr =
883 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
884 if (bp->hwrm_cmd_resp_dma_addr == 0) {
886 "Unable to map response buffer to physical memory.\n");
890 bp->max_resp_len = max_resp_len;
894 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
896 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
897 PMD_DRV_LOG(DEBUG, "Short command supported\n");
898 bp->flags |= BNXT_FLAG_SHORT_CMD;
902 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
904 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
905 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
906 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
907 bp->pdev->addr.domain, bp->pdev->addr.bus,
908 bp->pdev->addr.devid, bp->pdev->addr.function);
910 rte_free(bp->hwrm_short_cmd_req_addr);
912 bp->hwrm_short_cmd_req_addr =
913 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
914 if (bp->hwrm_short_cmd_req_addr == NULL) {
918 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
919 bp->hwrm_short_cmd_req_dma_addr =
920 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
921 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
922 rte_free(bp->hwrm_short_cmd_req_addr);
924 "Unable to map buffer to physical memory.\n");
930 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
931 bp->flags |= BNXT_FLAG_KONG_MB_EN;
932 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
935 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
936 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
943 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
946 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
947 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
949 if (!(bp->flags & BNXT_FLAG_REGISTERED))
952 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
955 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
960 bp->flags &= ~BNXT_FLAG_REGISTERED;
965 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
968 struct hwrm_port_phy_cfg_input req = {0};
969 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
970 uint32_t enables = 0;
972 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
975 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
976 if (bp->link_info.auto_mode && conf->link_speed) {
977 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
978 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
981 req.flags = rte_cpu_to_le_32(conf->phy_flags);
982 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
983 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
985 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
986 * any auto mode, even "none".
988 if (!conf->link_speed) {
989 /* No speeds specified. Enable AutoNeg - all speeds */
991 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
993 /* AutoNeg - Advertise speeds specified. */
994 if (conf->auto_link_speed_mask &&
995 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
997 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
998 req.auto_link_speed_mask =
999 conf->auto_link_speed_mask;
1001 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1004 req.auto_duplex = conf->duplex;
1005 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1006 req.auto_pause = conf->auto_pause;
1007 req.force_pause = conf->force_pause;
1008 /* Set force_pause if there is no auto or if there is a force */
1009 if (req.auto_pause && !req.force_pause)
1010 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1012 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1014 req.enables = rte_cpu_to_le_32(enables);
1017 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1018 PMD_DRV_LOG(INFO, "Force Link Down\n");
1021 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1023 HWRM_CHECK_RESULT();
1029 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1030 struct bnxt_link_info *link_info)
1033 struct hwrm_port_phy_qcfg_input req = {0};
1034 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1036 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1038 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1040 HWRM_CHECK_RESULT();
1042 link_info->phy_link_status = resp->link;
1043 link_info->link_up =
1044 (link_info->phy_link_status ==
1045 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1046 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1047 link_info->duplex = resp->duplex_cfg;
1048 link_info->pause = resp->pause;
1049 link_info->auto_pause = resp->auto_pause;
1050 link_info->force_pause = resp->force_pause;
1051 link_info->auto_mode = resp->auto_mode;
1052 link_info->phy_type = resp->phy_type;
1053 link_info->media_type = resp->media_type;
1055 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1056 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1057 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1058 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1059 link_info->phy_ver[0] = resp->phy_maj;
1060 link_info->phy_ver[1] = resp->phy_min;
1061 link_info->phy_ver[2] = resp->phy_bld;
1065 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1066 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1067 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1068 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1069 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1070 link_info->auto_link_speed_mask);
1071 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1072 link_info->force_link_speed);
1077 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1080 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1081 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1084 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1086 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1087 /* HWRM Version >= 1.9.1 */
1088 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1090 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1091 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1093 HWRM_CHECK_RESULT();
1095 #define GET_QUEUE_INFO(x) \
1096 bp->cos_queue[x].id = resp->queue_id##x; \
1097 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1110 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1111 bp->tx_cosq_id = bp->cos_queue[0].id;
1113 /* iterate and find the COSq profile to use for Tx */
1114 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1115 if (bp->cos_queue[i].profile ==
1116 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1117 bp->tx_cosq_id = bp->cos_queue[i].id;
1123 bp->max_tc = resp->max_configurable_queues;
1124 bp->max_lltc = resp->max_configurable_lossless_queues;
1125 if (bp->max_tc > BNXT_MAX_QUEUE)
1126 bp->max_tc = BNXT_MAX_QUEUE;
1127 bp->max_q = bp->max_tc;
1129 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1134 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1135 struct bnxt_ring *ring,
1136 uint32_t ring_type, uint32_t map_index,
1137 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1140 uint32_t enables = 0;
1141 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1142 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1143 struct rte_mempool *mb_pool;
1144 uint16_t rx_buf_size;
1146 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1148 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1149 req.fbo = rte_cpu_to_le_32(0);
1150 /* Association of ring index with doorbell index */
1151 req.logical_id = rte_cpu_to_le_16(map_index);
1152 req.length = rte_cpu_to_le_32(ring->ring_size);
1154 switch (ring_type) {
1155 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1156 req.ring_type = ring_type;
1157 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1158 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1159 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1160 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1162 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1164 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1165 req.ring_type = ring_type;
1166 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1167 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1168 if (BNXT_CHIP_THOR(bp)) {
1169 mb_pool = bp->rx_queues[0]->mb_pool;
1170 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1171 RTE_PKTMBUF_HEADROOM;
1172 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1174 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1176 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1178 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1180 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1181 req.ring_type = ring_type;
1182 if (BNXT_HAS_NQ(bp)) {
1183 /* Association of cp ring with nq */
1184 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1186 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1188 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1190 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1191 req.ring_type = ring_type;
1192 req.page_size = BNXT_PAGE_SHFT;
1193 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1195 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1196 req.ring_type = ring_type;
1197 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1199 mb_pool = bp->rx_queues[0]->mb_pool;
1200 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1201 RTE_PKTMBUF_HEADROOM;
1202 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1204 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1205 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1206 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1207 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1210 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1215 req.enables = rte_cpu_to_le_32(enables);
1217 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1219 if (rc || resp->error_code) {
1220 if (rc == 0 && resp->error_code)
1221 rc = rte_le_to_cpu_16(resp->error_code);
1222 switch (ring_type) {
1223 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1225 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1228 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1230 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1233 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1235 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1239 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1241 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1244 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1246 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1250 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1256 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1261 int bnxt_hwrm_ring_free(struct bnxt *bp,
1262 struct bnxt_ring *ring, uint32_t ring_type)
1265 struct hwrm_ring_free_input req = {.req_type = 0 };
1266 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1268 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1270 req.ring_type = ring_type;
1271 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1273 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1275 if (rc || resp->error_code) {
1276 if (rc == 0 && resp->error_code)
1277 rc = rte_le_to_cpu_16(resp->error_code);
1280 switch (ring_type) {
1281 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1282 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1285 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1286 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1289 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1290 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1293 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1295 "hwrm_ring_free nq failed. rc:%d\n", rc);
1297 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1299 "hwrm_ring_free agg failed. rc:%d\n", rc);
1302 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1310 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1313 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1314 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1316 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1318 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1319 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1320 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1321 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1323 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1325 HWRM_CHECK_RESULT();
1327 bp->grp_info[idx].fw_grp_id =
1328 rte_le_to_cpu_16(resp->ring_group_id);
1335 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1338 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1339 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1341 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1343 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1345 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1347 HWRM_CHECK_RESULT();
1350 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1354 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1357 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1358 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1360 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1363 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1365 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1367 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1369 HWRM_CHECK_RESULT();
1375 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1376 unsigned int idx __rte_unused)
1379 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1380 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1382 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1384 req.update_period_ms = rte_cpu_to_le_32(0);
1386 req.stats_dma_addr =
1387 rte_cpu_to_le_64(cpr->hw_stats_map);
1389 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1391 HWRM_CHECK_RESULT();
1393 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1400 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1401 unsigned int idx __rte_unused)
1404 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1405 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1407 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1409 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1411 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1413 HWRM_CHECK_RESULT();
1419 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1422 struct hwrm_vnic_alloc_input req = { 0 };
1423 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1425 if (!BNXT_HAS_RING_GRPS(bp))
1426 goto skip_ring_grps;
1428 /* map ring groups to this vnic */
1429 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1430 vnic->start_grp_id, vnic->end_grp_id);
1431 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1432 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1434 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1435 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1436 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1437 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1440 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1441 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1442 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1444 if (vnic->func_default)
1446 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1447 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1449 HWRM_CHECK_RESULT();
1451 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1453 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1457 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1458 struct bnxt_vnic_info *vnic,
1459 struct bnxt_plcmodes_cfg *pmode)
1462 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1463 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1465 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1467 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1469 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1471 HWRM_CHECK_RESULT();
1473 pmode->flags = rte_le_to_cpu_32(resp->flags);
1474 /* dflt_vnic bit doesn't exist in the _cfg command */
1475 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1476 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1477 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1478 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1485 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1486 struct bnxt_vnic_info *vnic,
1487 struct bnxt_plcmodes_cfg *pmode)
1490 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1491 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1493 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1495 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1496 req.flags = rte_cpu_to_le_32(pmode->flags);
1497 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1498 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1499 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1500 req.enables = rte_cpu_to_le_32(
1501 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1502 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1503 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1506 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1508 HWRM_CHECK_RESULT();
1514 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1517 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1518 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1519 uint32_t ctx_enable_flag = 0;
1520 struct bnxt_plcmodes_cfg pmodes;
1521 uint32_t enables = 0;
1523 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1524 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1528 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1532 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1534 if (BNXT_CHIP_THOR(bp)) {
1535 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1536 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1537 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1539 req.default_rx_ring_id =
1540 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1541 req.default_cmpl_ring_id =
1542 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1543 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1544 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1548 /* Only RSS support for now TBD: COS & LB */
1549 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1550 if (vnic->lb_rule != 0xffff)
1551 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1552 if (vnic->cos_rule != 0xffff)
1553 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1554 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1555 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1556 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1558 enables |= ctx_enable_flag;
1559 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1560 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1561 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1562 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1565 req.enables = rte_cpu_to_le_32(enables);
1566 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1567 req.mru = rte_cpu_to_le_16(vnic->mru);
1568 /* Configure default VNIC only once. */
1569 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1571 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1572 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1574 if (vnic->vlan_strip)
1576 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1579 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1580 if (vnic->roce_dual)
1581 req.flags |= rte_cpu_to_le_32(
1582 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1583 if (vnic->roce_only)
1584 req.flags |= rte_cpu_to_le_32(
1585 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1586 if (vnic->rss_dflt_cr)
1587 req.flags |= rte_cpu_to_le_32(
1588 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1590 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1592 HWRM_CHECK_RESULT();
1595 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1600 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1604 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1605 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1607 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1608 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1611 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1614 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1615 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1616 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1618 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1620 HWRM_CHECK_RESULT();
1622 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1623 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1624 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1625 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1626 vnic->mru = rte_le_to_cpu_16(resp->mru);
1627 vnic->func_default = rte_le_to_cpu_32(
1628 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1629 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1630 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1631 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1632 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1633 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1634 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1635 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1636 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1637 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1638 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1645 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1646 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1650 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1651 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1652 bp->hwrm_cmd_resp_addr;
1654 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1656 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1657 HWRM_CHECK_RESULT();
1659 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1660 if (!BNXT_HAS_RING_GRPS(bp))
1661 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1662 else if (ctx_idx == 0)
1663 vnic->rss_rule = ctx_id;
1670 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1671 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1674 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1675 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1676 bp->hwrm_cmd_resp_addr;
1678 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1679 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1682 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1684 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1686 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1688 HWRM_CHECK_RESULT();
1694 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1697 struct hwrm_vnic_free_input req = {.req_type = 0 };
1698 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1700 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1701 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1705 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1707 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1709 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1711 HWRM_CHECK_RESULT();
1714 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1715 /* Configure default VNIC again if necessary. */
1716 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1717 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1723 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1727 int nr_ctxs = bp->max_ring_grps;
1728 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1729 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1731 if (!(vnic->rss_table && vnic->hash_type))
1734 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1736 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1737 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1738 req.hash_mode_flags = vnic->hash_mode;
1740 req.hash_key_tbl_addr =
1741 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1743 for (i = 0; i < nr_ctxs; i++) {
1744 req.ring_grp_tbl_addr =
1745 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1746 i * HW_HASH_INDEX_SIZE);
1747 req.ring_table_pair_index = i;
1748 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1750 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1753 HWRM_CHECK_RESULT();
1763 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1764 struct bnxt_vnic_info *vnic)
1767 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1768 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1770 if (BNXT_CHIP_THOR(bp))
1771 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1773 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1775 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1776 req.hash_mode_flags = vnic->hash_mode;
1778 req.ring_grp_tbl_addr =
1779 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1780 req.hash_key_tbl_addr =
1781 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1782 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1783 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1785 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1787 HWRM_CHECK_RESULT();
1793 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1794 struct bnxt_vnic_info *vnic)
1797 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1798 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1801 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1802 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1806 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1808 req.flags = rte_cpu_to_le_32(
1809 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1811 req.enables = rte_cpu_to_le_32(
1812 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1814 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1815 size -= RTE_PKTMBUF_HEADROOM;
1817 req.jumbo_thresh = rte_cpu_to_le_16(size);
1818 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1820 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1822 HWRM_CHECK_RESULT();
1828 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1829 struct bnxt_vnic_info *vnic, bool enable)
1832 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1833 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1835 if (BNXT_CHIP_THOR(bp))
1838 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1841 req.enables = rte_cpu_to_le_32(
1842 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1843 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1844 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1845 req.flags = rte_cpu_to_le_32(
1846 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1847 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1848 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1849 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1850 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1851 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1852 req.max_agg_segs = rte_cpu_to_le_16(5);
1854 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1855 req.min_agg_len = rte_cpu_to_le_32(512);
1857 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1859 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1861 HWRM_CHECK_RESULT();
1867 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1869 struct hwrm_func_cfg_input req = {0};
1870 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1873 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1874 req.enables = rte_cpu_to_le_32(
1875 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1876 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1877 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1879 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1881 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1882 HWRM_CHECK_RESULT();
1885 bp->pf.vf_info[vf].random_mac = false;
1890 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1894 struct hwrm_func_qstats_input req = {.req_type = 0};
1895 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1897 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1899 req.fid = rte_cpu_to_le_16(fid);
1901 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1903 HWRM_CHECK_RESULT();
1906 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1913 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1914 struct rte_eth_stats *stats)
1917 struct hwrm_func_qstats_input req = {.req_type = 0};
1918 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1920 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1922 req.fid = rte_cpu_to_le_16(fid);
1924 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1926 HWRM_CHECK_RESULT();
1928 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1929 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1930 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1931 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1932 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1933 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1935 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1936 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1937 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1938 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1939 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1940 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1942 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1943 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1944 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1951 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1954 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1955 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1957 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1959 req.fid = rte_cpu_to_le_16(fid);
1961 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1963 HWRM_CHECK_RESULT();
1970 * HWRM utility functions
1973 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1978 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1979 struct bnxt_tx_queue *txq;
1980 struct bnxt_rx_queue *rxq;
1981 struct bnxt_cp_ring_info *cpr;
1983 if (i >= bp->rx_cp_nr_rings) {
1984 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1987 rxq = bp->rx_queues[i];
1991 rc = bnxt_hwrm_stat_clear(bp, cpr);
1998 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2002 struct bnxt_cp_ring_info *cpr;
2004 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2006 if (i >= bp->rx_cp_nr_rings) {
2007 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2009 cpr = bp->rx_queues[i]->cp_ring;
2010 if (BNXT_HAS_RING_GRPS(bp))
2011 bp->grp_info[i].fw_stats_ctx = -1;
2013 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2014 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2015 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2023 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2028 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2029 struct bnxt_tx_queue *txq;
2030 struct bnxt_rx_queue *rxq;
2031 struct bnxt_cp_ring_info *cpr;
2033 if (i >= bp->rx_cp_nr_rings) {
2034 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2037 rxq = bp->rx_queues[i];
2041 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2049 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2054 if (!BNXT_HAS_RING_GRPS(bp))
2057 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2059 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2062 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2070 static void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2072 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2074 bnxt_hwrm_ring_free(bp, cp_ring,
2075 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2076 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2077 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2078 sizeof(*cpr->cp_desc_ring));
2079 cpr->cp_raw_cons = 0;
2082 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2084 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2086 bnxt_hwrm_ring_free(bp, cp_ring,
2087 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2088 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2089 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2090 sizeof(*cpr->cp_desc_ring));
2091 cpr->cp_raw_cons = 0;
2095 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2097 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2098 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2099 struct bnxt_ring *ring = rxr->rx_ring_struct;
2100 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2102 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2103 bnxt_hwrm_ring_free(bp, ring,
2104 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2105 ring->fw_ring_id = INVALID_HW_RING_ID;
2106 if (BNXT_HAS_RING_GRPS(bp))
2107 bp->grp_info[queue_index].rx_fw_ring_id =
2109 memset(rxr->rx_desc_ring, 0,
2110 rxr->rx_ring_struct->ring_size *
2111 sizeof(*rxr->rx_desc_ring));
2112 memset(rxr->rx_buf_ring, 0,
2113 rxr->rx_ring_struct->ring_size *
2114 sizeof(*rxr->rx_buf_ring));
2117 ring = rxr->ag_ring_struct;
2118 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2119 bnxt_hwrm_ring_free(bp, ring,
2120 BNXT_CHIP_THOR(bp) ?
2121 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2122 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2123 ring->fw_ring_id = INVALID_HW_RING_ID;
2124 memset(rxr->ag_buf_ring, 0,
2125 rxr->ag_ring_struct->ring_size *
2126 sizeof(*rxr->ag_buf_ring));
2128 if (BNXT_HAS_RING_GRPS(bp))
2129 bp->grp_info[queue_index].ag_fw_ring_id =
2132 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2133 bnxt_free_cp_ring(bp, cpr);
2135 bnxt_free_nq_ring(bp, rxq->nq_ring);
2138 if (BNXT_HAS_RING_GRPS(bp))
2139 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2142 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2146 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2147 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2148 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2149 struct bnxt_ring *ring = txr->tx_ring_struct;
2150 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2152 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2153 bnxt_hwrm_ring_free(bp, ring,
2154 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2155 ring->fw_ring_id = INVALID_HW_RING_ID;
2156 memset(txr->tx_desc_ring, 0,
2157 txr->tx_ring_struct->ring_size *
2158 sizeof(*txr->tx_desc_ring));
2159 memset(txr->tx_buf_ring, 0,
2160 txr->tx_ring_struct->ring_size *
2161 sizeof(*txr->tx_buf_ring));
2165 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2166 bnxt_free_cp_ring(bp, cpr);
2167 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2169 bnxt_free_nq_ring(bp, txq->nq_ring);
2173 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2174 bnxt_free_hwrm_rx_ring(bp, i);
2179 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2184 if (!BNXT_HAS_RING_GRPS(bp))
2187 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2188 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2195 void bnxt_free_hwrm_resources(struct bnxt *bp)
2197 /* Release memzone */
2198 rte_free(bp->hwrm_cmd_resp_addr);
2199 rte_free(bp->hwrm_short_cmd_req_addr);
2200 bp->hwrm_cmd_resp_addr = NULL;
2201 bp->hwrm_short_cmd_req_addr = NULL;
2202 bp->hwrm_cmd_resp_dma_addr = 0;
2203 bp->hwrm_short_cmd_req_dma_addr = 0;
2206 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2208 struct rte_pci_device *pdev = bp->pdev;
2209 char type[RTE_MEMZONE_NAMESIZE];
2211 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2212 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2213 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2214 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2215 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2216 if (bp->hwrm_cmd_resp_addr == NULL)
2218 bp->hwrm_cmd_resp_dma_addr =
2219 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2220 if (bp->hwrm_cmd_resp_dma_addr == 0) {
2222 "unable to map response address to physical memory\n");
2225 rte_spinlock_init(&bp->hwrm_lock);
2230 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2232 struct bnxt_filter_info *filter;
2235 STAILQ_FOREACH(filter, &vnic->filter, next) {
2236 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2237 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2238 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2239 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2241 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2242 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2250 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2252 struct bnxt_filter_info *filter;
2253 struct rte_flow *flow;
2256 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2257 filter = flow->filter;
2258 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
2259 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2260 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2261 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2262 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2264 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2266 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2274 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2276 struct bnxt_filter_info *filter;
2279 STAILQ_FOREACH(filter, &vnic->filter, next) {
2280 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2281 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2283 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2284 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2287 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2295 void bnxt_free_tunnel_ports(struct bnxt *bp)
2297 if (bp->vxlan_port_cnt)
2298 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2299 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2301 if (bp->geneve_port_cnt)
2302 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2303 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2304 bp->geneve_port = 0;
2307 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2311 if (bp->vnic_info == NULL)
2315 * Cleanup VNICs in reverse order, to make sure the L2 filter
2316 * from vnic0 is last to be cleaned up.
2318 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2319 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2321 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2323 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2325 if (BNXT_CHIP_THOR(bp)) {
2326 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2327 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2328 vnic->fw_grp_ids[j]);
2329 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2331 vnic->num_lb_ctxts = 0;
2333 bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2334 vnic->rss_rule = INVALID_HW_RING_ID;
2337 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2339 bnxt_hwrm_vnic_free(bp, vnic);
2341 rte_free(vnic->fw_grp_ids);
2343 /* Ring resources */
2344 bnxt_free_all_hwrm_rings(bp);
2345 bnxt_free_all_hwrm_ring_grps(bp);
2346 bnxt_free_all_hwrm_stat_ctxs(bp);
2347 bnxt_free_tunnel_ports(bp);
2350 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2352 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2354 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2355 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2357 switch (conf_link_speed) {
2358 case ETH_LINK_SPEED_10M_HD:
2359 case ETH_LINK_SPEED_100M_HD:
2361 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2363 return hw_link_duplex;
2366 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2368 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2371 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2373 uint16_t eth_link_speed = 0;
2375 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2376 return ETH_LINK_SPEED_AUTONEG;
2378 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2379 case ETH_LINK_SPEED_100M:
2380 case ETH_LINK_SPEED_100M_HD:
2383 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2385 case ETH_LINK_SPEED_1G:
2387 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2389 case ETH_LINK_SPEED_2_5G:
2391 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2393 case ETH_LINK_SPEED_10G:
2395 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2397 case ETH_LINK_SPEED_20G:
2399 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2401 case ETH_LINK_SPEED_25G:
2403 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2405 case ETH_LINK_SPEED_40G:
2407 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2409 case ETH_LINK_SPEED_50G:
2411 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2413 case ETH_LINK_SPEED_100G:
2415 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2419 "Unsupported link speed %d; default to AUTO\n",
2423 return eth_link_speed;
2426 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2427 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2428 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2429 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2431 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2435 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2438 if (link_speed & ETH_LINK_SPEED_FIXED) {
2439 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2441 if (one_speed & (one_speed - 1)) {
2443 "Invalid advertised speeds (%u) for port %u\n",
2444 link_speed, port_id);
2447 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2449 "Unsupported advertised speed (%u) for port %u\n",
2450 link_speed, port_id);
2454 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2456 "Unsupported advertised speeds (%u) for port %u\n",
2457 link_speed, port_id);
2465 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2469 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2470 if (bp->link_info.support_speeds)
2471 return bp->link_info.support_speeds;
2472 link_speed = BNXT_SUPPORTED_SPEEDS;
2475 if (link_speed & ETH_LINK_SPEED_100M)
2476 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2477 if (link_speed & ETH_LINK_SPEED_100M_HD)
2478 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2479 if (link_speed & ETH_LINK_SPEED_1G)
2480 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2481 if (link_speed & ETH_LINK_SPEED_2_5G)
2482 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2483 if (link_speed & ETH_LINK_SPEED_10G)
2484 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2485 if (link_speed & ETH_LINK_SPEED_20G)
2486 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2487 if (link_speed & ETH_LINK_SPEED_25G)
2488 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2489 if (link_speed & ETH_LINK_SPEED_40G)
2490 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2491 if (link_speed & ETH_LINK_SPEED_50G)
2492 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2493 if (link_speed & ETH_LINK_SPEED_100G)
2494 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2498 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2500 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2502 switch (hw_link_speed) {
2503 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2504 eth_link_speed = ETH_SPEED_NUM_100M;
2506 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2507 eth_link_speed = ETH_SPEED_NUM_1G;
2509 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2510 eth_link_speed = ETH_SPEED_NUM_2_5G;
2512 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2513 eth_link_speed = ETH_SPEED_NUM_10G;
2515 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2516 eth_link_speed = ETH_SPEED_NUM_20G;
2518 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2519 eth_link_speed = ETH_SPEED_NUM_25G;
2521 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2522 eth_link_speed = ETH_SPEED_NUM_40G;
2524 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2525 eth_link_speed = ETH_SPEED_NUM_50G;
2527 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2528 eth_link_speed = ETH_SPEED_NUM_100G;
2530 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2532 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2536 return eth_link_speed;
2539 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2541 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2543 switch (hw_link_duplex) {
2544 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2545 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2547 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2549 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2550 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2553 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2557 return eth_link_duplex;
2560 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2563 struct bnxt_link_info *link_info = &bp->link_info;
2565 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2568 "Get link config failed with rc %d\n", rc);
2571 if (link_info->link_speed)
2573 bnxt_parse_hw_link_speed(link_info->link_speed);
2575 link->link_speed = ETH_SPEED_NUM_NONE;
2576 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2577 link->link_status = link_info->link_up;
2578 link->link_autoneg = link_info->auto_mode ==
2579 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2580 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2585 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2588 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2589 struct bnxt_link_info link_req;
2590 uint16_t speed, autoneg;
2592 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2595 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2596 bp->eth_dev->data->port_id);
2600 memset(&link_req, 0, sizeof(link_req));
2601 link_req.link_up = link_up;
2605 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2606 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2607 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2608 /* Autoneg can be done only when the FW allows */
2609 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2610 bp->link_info.force_link_speed)) {
2611 link_req.phy_flags |=
2612 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2613 link_req.auto_link_speed_mask =
2614 bnxt_parse_eth_link_speed_mask(bp,
2615 dev_conf->link_speeds);
2617 if (bp->link_info.phy_type ==
2618 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2619 bp->link_info.phy_type ==
2620 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2621 bp->link_info.media_type ==
2622 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2623 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2627 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2628 /* If user wants a particular speed try that first. */
2630 link_req.link_speed = speed;
2631 else if (bp->link_info.force_link_speed)
2632 link_req.link_speed = bp->link_info.force_link_speed;
2634 link_req.link_speed = bp->link_info.auto_link_speed;
2636 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2637 link_req.auto_pause = bp->link_info.auto_pause;
2638 link_req.force_pause = bp->link_info.force_pause;
2641 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2644 "Set link config failed with rc %d\n", rc);
2652 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2654 struct hwrm_func_qcfg_input req = {0};
2655 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2659 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2660 req.fid = rte_cpu_to_le_16(0xffff);
2662 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2664 HWRM_CHECK_RESULT();
2666 /* Hard Coded.. 0xfff VLAN ID mask */
2667 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2668 flags = rte_le_to_cpu_16(resp->flags);
2669 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2670 bp->flags |= BNXT_FLAG_MULTI_HOST;
2672 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2673 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2674 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2680 switch (resp->port_partition_type) {
2681 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2682 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2683 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2685 bp->port_partition_type = resp->port_partition_type;
2688 bp->port_partition_type = 0;
2697 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2698 struct hwrm_func_qcaps_output *qcaps)
2700 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2701 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2702 sizeof(qcaps->mac_address));
2703 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2704 qcaps->max_rx_rings = fcfg->num_rx_rings;
2705 qcaps->max_tx_rings = fcfg->num_tx_rings;
2706 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2707 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2709 qcaps->first_vf_id = 0;
2710 qcaps->max_vnics = fcfg->num_vnics;
2711 qcaps->max_decap_records = 0;
2712 qcaps->max_encap_records = 0;
2713 qcaps->max_tx_wm_flows = 0;
2714 qcaps->max_tx_em_flows = 0;
2715 qcaps->max_rx_wm_flows = 0;
2716 qcaps->max_rx_em_flows = 0;
2717 qcaps->max_flow_id = 0;
2718 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2719 qcaps->max_sp_tx_rings = 0;
2720 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2723 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2725 struct hwrm_func_cfg_input req = {0};
2726 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2730 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2731 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2732 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2733 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2734 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2735 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2736 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2737 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2738 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2740 if (BNXT_HAS_RING_GRPS(bp)) {
2741 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2742 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2743 } else if (BNXT_HAS_NQ(bp)) {
2744 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2745 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2748 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2749 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2750 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2751 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2753 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2754 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2755 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2756 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2757 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2758 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2759 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2760 req.fid = rte_cpu_to_le_16(0xffff);
2761 req.enables = rte_cpu_to_le_32(enables);
2763 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2765 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2767 HWRM_CHECK_RESULT();
2773 static void populate_vf_func_cfg_req(struct bnxt *bp,
2774 struct hwrm_func_cfg_input *req,
2777 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2778 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2779 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2780 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2781 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2782 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2783 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2784 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2785 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2786 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2788 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2789 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2791 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2792 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2794 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2796 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2797 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2799 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2800 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2801 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2802 /* TODO: For now, do not support VMDq/RFS on VFs. */
2803 req->num_vnics = rte_cpu_to_le_16(1);
2804 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2808 static void add_random_mac_if_needed(struct bnxt *bp,
2809 struct hwrm_func_cfg_input *cfg_req,
2812 struct rte_ether_addr mac;
2814 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2817 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2819 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2820 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2821 bp->pf.vf_info[vf].random_mac = true;
2823 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2824 RTE_ETHER_ADDR_LEN);
2828 static void reserve_resources_from_vf(struct bnxt *bp,
2829 struct hwrm_func_cfg_input *cfg_req,
2832 struct hwrm_func_qcaps_input req = {0};
2833 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2836 /* Get the actual allocated values now */
2837 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2838 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2839 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2842 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2843 copy_func_cfg_to_qcaps(cfg_req, resp);
2844 } else if (resp->error_code) {
2845 rc = rte_le_to_cpu_16(resp->error_code);
2846 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2847 copy_func_cfg_to_qcaps(cfg_req, resp);
2850 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2851 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2852 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2853 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2854 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2855 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2857 * TODO: While not supporting VMDq with VFs, max_vnics is always
2858 * forced to 1 in this case
2860 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2861 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2866 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2868 struct hwrm_func_qcfg_input req = {0};
2869 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2872 /* Check for zero MAC address */
2873 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2874 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2875 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2877 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2879 } else if (resp->error_code) {
2880 rc = rte_le_to_cpu_16(resp->error_code);
2881 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2884 rc = rte_le_to_cpu_16(resp->vlan);
2891 static int update_pf_resource_max(struct bnxt *bp)
2893 struct hwrm_func_qcfg_input req = {0};
2894 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2897 /* And copy the allocated numbers into the pf struct */
2898 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2899 req.fid = rte_cpu_to_le_16(0xffff);
2900 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2901 HWRM_CHECK_RESULT();
2903 /* Only TX ring value reflects actual allocation? TODO */
2904 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2905 bp->pf.evb_mode = resp->evb_mode;
2912 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2917 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2921 rc = bnxt_hwrm_func_qcaps(bp);
2925 bp->pf.func_cfg_flags &=
2926 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2927 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2928 bp->pf.func_cfg_flags |=
2929 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2930 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2931 rc = __bnxt_hwrm_func_qcaps(bp);
2935 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2937 struct hwrm_func_cfg_input req = {0};
2938 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2945 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2949 rc = bnxt_hwrm_func_qcaps(bp);
2954 bp->pf.active_vfs = num_vfs;
2957 * First, configure the PF to only use one TX ring. This ensures that
2958 * there are enough rings for all VFs.
2960 * If we don't do this, when we call func_alloc() later, we will lock
2961 * extra rings to the PF that won't be available during func_cfg() of
2964 * This has been fixed with firmware versions above 20.6.54
2966 bp->pf.func_cfg_flags &=
2967 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2968 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2969 bp->pf.func_cfg_flags |=
2970 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2971 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2976 * Now, create and register a buffer to hold forwarded VF requests
2978 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2979 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2980 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2981 if (bp->pf.vf_req_buf == NULL) {
2985 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2986 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2987 for (i = 0; i < num_vfs; i++)
2988 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2989 (i * HWRM_MAX_REQ_LEN);
2991 rc = bnxt_hwrm_func_buf_rgtr(bp);
2995 populate_vf_func_cfg_req(bp, &req, num_vfs);
2997 bp->pf.active_vfs = 0;
2998 for (i = 0; i < num_vfs; i++) {
2999 add_random_mac_if_needed(bp, &req, i);
3001 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3002 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3003 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3004 rc = bnxt_hwrm_send_message(bp,
3009 /* Clear enable flag for next pass */
3010 req.enables &= ~rte_cpu_to_le_32(
3011 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3013 if (rc || resp->error_code) {
3015 "Failed to initizlie VF %d\n", i);
3017 "Not all VFs available. (%d, %d)\n",
3018 rc, resp->error_code);
3025 reserve_resources_from_vf(bp, &req, i);
3026 bp->pf.active_vfs++;
3027 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3031 * Now configure the PF to use "the rest" of the resources
3032 * We're using STD_TX_RING_MODE here though which will limit the TX
3033 * rings. This will allow QoS to function properly. Not setting this
3034 * will cause PF rings to break bandwidth settings.
3036 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3040 rc = update_pf_resource_max(bp);
3047 bnxt_hwrm_func_buf_unrgtr(bp);
3051 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3053 struct hwrm_func_cfg_input req = {0};
3054 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3057 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3059 req.fid = rte_cpu_to_le_16(0xffff);
3060 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3061 req.evb_mode = bp->pf.evb_mode;
3063 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3064 HWRM_CHECK_RESULT();
3070 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3071 uint8_t tunnel_type)
3073 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3074 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3077 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3078 req.tunnel_type = tunnel_type;
3079 req.tunnel_dst_port_val = port;
3080 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3081 HWRM_CHECK_RESULT();
3083 switch (tunnel_type) {
3084 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3085 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3086 bp->vxlan_port = port;
3088 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3089 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3090 bp->geneve_port = port;
3101 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3102 uint8_t tunnel_type)
3104 struct hwrm_tunnel_dst_port_free_input req = {0};
3105 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3108 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3110 req.tunnel_type = tunnel_type;
3111 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3112 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3114 HWRM_CHECK_RESULT();
3120 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3123 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3124 struct hwrm_func_cfg_input req = {0};
3127 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3129 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3130 req.flags = rte_cpu_to_le_32(flags);
3131 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3133 HWRM_CHECK_RESULT();
3139 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3141 uint32_t *flag = flagp;
3143 vnic->flags = *flag;
3146 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3148 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3151 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3154 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3155 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3157 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3159 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3160 req.req_buf_page_size = rte_cpu_to_le_16(
3161 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3162 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3163 req.req_buf_page_addr0 =
3164 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3165 if (req.req_buf_page_addr0 == 0) {
3167 "unable to map buffer address to physical memory\n");
3171 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3173 HWRM_CHECK_RESULT();
3179 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3182 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3183 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3185 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3187 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3189 HWRM_CHECK_RESULT();
3195 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3197 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3198 struct hwrm_func_cfg_input req = {0};
3201 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3203 req.fid = rte_cpu_to_le_16(0xffff);
3204 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3205 req.enables = rte_cpu_to_le_32(
3206 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3207 req.async_event_cr = rte_cpu_to_le_16(
3208 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3209 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3211 HWRM_CHECK_RESULT();
3217 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3219 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3220 struct hwrm_func_vf_cfg_input req = {0};
3223 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3225 req.enables = rte_cpu_to_le_32(
3226 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3227 req.async_event_cr = rte_cpu_to_le_16(
3228 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3229 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3231 HWRM_CHECK_RESULT();
3237 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3239 struct hwrm_func_cfg_input req = {0};
3240 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3241 uint16_t dflt_vlan, fid;
3242 uint32_t func_cfg_flags;
3245 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3248 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3249 fid = bp->pf.vf_info[vf].fid;
3250 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3252 fid = rte_cpu_to_le_16(0xffff);
3253 func_cfg_flags = bp->pf.func_cfg_flags;
3254 dflt_vlan = bp->vlan;
3257 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3258 req.fid = rte_cpu_to_le_16(fid);
3259 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3260 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3262 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3264 HWRM_CHECK_RESULT();
3270 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3271 uint16_t max_bw, uint16_t enables)
3273 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3274 struct hwrm_func_cfg_input req = {0};
3277 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3279 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3280 req.enables |= rte_cpu_to_le_32(enables);
3281 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3282 req.max_bw = rte_cpu_to_le_32(max_bw);
3283 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3285 HWRM_CHECK_RESULT();
3291 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3293 struct hwrm_func_cfg_input req = {0};
3294 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3297 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3299 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3300 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3301 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3302 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3304 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3306 HWRM_CHECK_RESULT();
3312 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3317 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3319 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3324 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3325 void *encaped, size_t ec_size)
3328 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3329 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3331 if (ec_size > sizeof(req.encap_request))
3334 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3336 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3337 memcpy(req.encap_request, encaped, ec_size);
3339 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3341 HWRM_CHECK_RESULT();
3347 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3348 struct rte_ether_addr *mac)
3350 struct hwrm_func_qcfg_input req = {0};
3351 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3354 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3356 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3359 HWRM_CHECK_RESULT();
3361 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3368 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3369 void *encaped, size_t ec_size)
3372 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3373 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3375 if (ec_size > sizeof(req.encap_request))
3378 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3380 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3381 memcpy(req.encap_request, encaped, ec_size);
3383 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3385 HWRM_CHECK_RESULT();
3391 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3392 struct rte_eth_stats *stats, uint8_t rx)
3395 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3396 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3398 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3400 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3402 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3404 HWRM_CHECK_RESULT();
3407 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3408 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3409 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3410 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3411 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3412 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3413 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3414 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3416 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3417 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3418 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3419 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3420 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3421 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3430 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3432 struct hwrm_port_qstats_input req = {0};
3433 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3434 struct bnxt_pf_info *pf = &bp->pf;
3437 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3439 req.port_id = rte_cpu_to_le_16(pf->port_id);
3440 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3441 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3442 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3444 HWRM_CHECK_RESULT();
3450 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3452 struct hwrm_port_clr_stats_input req = {0};
3453 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3454 struct bnxt_pf_info *pf = &bp->pf;
3457 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3458 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3459 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3462 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3464 req.port_id = rte_cpu_to_le_16(pf->port_id);
3465 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3467 HWRM_CHECK_RESULT();
3473 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3475 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3476 struct hwrm_port_led_qcaps_input req = {0};
3482 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3483 req.port_id = bp->pf.port_id;
3484 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3486 HWRM_CHECK_RESULT();
3488 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3491 bp->num_leds = resp->num_leds;
3492 memcpy(bp->leds, &resp->led0_id,
3493 sizeof(bp->leds[0]) * bp->num_leds);
3494 for (i = 0; i < bp->num_leds; i++) {
3495 struct bnxt_led_info *led = &bp->leds[i];
3497 uint16_t caps = led->led_state_caps;
3499 if (!led->led_group_id ||
3500 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3512 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3514 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3515 struct hwrm_port_led_cfg_input req = {0};
3516 struct bnxt_led_cfg *led_cfg;
3517 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3518 uint16_t duration = 0;
3521 if (!bp->num_leds || BNXT_VF(bp))
3524 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3527 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3528 duration = rte_cpu_to_le_16(500);
3530 req.port_id = bp->pf.port_id;
3531 req.num_leds = bp->num_leds;
3532 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3533 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3534 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3535 led_cfg->led_id = bp->leds[i].led_id;
3536 led_cfg->led_state = led_state;
3537 led_cfg->led_blink_on = duration;
3538 led_cfg->led_blink_off = duration;
3539 led_cfg->led_group_id = bp->leds[i].led_group_id;
3542 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3544 HWRM_CHECK_RESULT();
3550 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3554 struct hwrm_nvm_get_dir_info_input req = {0};
3555 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3557 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3559 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3561 HWRM_CHECK_RESULT();
3565 *entries = rte_le_to_cpu_32(resp->entries);
3566 *length = rte_le_to_cpu_32(resp->entry_length);
3571 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3574 uint32_t dir_entries;
3575 uint32_t entry_length;
3578 rte_iova_t dma_handle;
3579 struct hwrm_nvm_get_dir_entries_input req = {0};
3580 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3582 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3586 *data++ = dir_entries;
3587 *data++ = entry_length;
3589 memset(data, 0xff, len);
3591 buflen = dir_entries * entry_length;
3592 buf = rte_malloc("nvm_dir", buflen, 0);
3593 rte_mem_lock_page(buf);
3596 dma_handle = rte_mem_virt2iova(buf);
3597 if (dma_handle == 0) {
3599 "unable to map response address to physical memory\n");
3602 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3603 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3604 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3607 memcpy(data, buf, len > buflen ? buflen : len);
3610 HWRM_CHECK_RESULT();
3616 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3617 uint32_t offset, uint32_t length,
3622 rte_iova_t dma_handle;
3623 struct hwrm_nvm_read_input req = {0};
3624 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3626 buf = rte_malloc("nvm_item", length, 0);
3627 rte_mem_lock_page(buf);
3631 dma_handle = rte_mem_virt2iova(buf);
3632 if (dma_handle == 0) {
3634 "unable to map response address to physical memory\n");
3637 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3638 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3639 req.dir_idx = rte_cpu_to_le_16(index);
3640 req.offset = rte_cpu_to_le_32(offset);
3641 req.len = rte_cpu_to_le_32(length);
3642 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3644 memcpy(data, buf, length);
3647 HWRM_CHECK_RESULT();
3653 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3656 struct hwrm_nvm_erase_dir_entry_input req = {0};
3657 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3659 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3660 req.dir_idx = rte_cpu_to_le_16(index);
3661 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3662 HWRM_CHECK_RESULT();
3669 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3670 uint16_t dir_ordinal, uint16_t dir_ext,
3671 uint16_t dir_attr, const uint8_t *data,
3675 struct hwrm_nvm_write_input req = {0};
3676 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3677 rte_iova_t dma_handle;
3680 buf = rte_malloc("nvm_write", data_len, 0);
3681 rte_mem_lock_page(buf);
3685 dma_handle = rte_mem_virt2iova(buf);
3686 if (dma_handle == 0) {
3688 "unable to map response address to physical memory\n");
3691 memcpy(buf, data, data_len);
3693 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3695 req.dir_type = rte_cpu_to_le_16(dir_type);
3696 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3697 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3698 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3699 req.dir_data_length = rte_cpu_to_le_32(data_len);
3700 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3702 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3705 HWRM_CHECK_RESULT();
3712 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3714 uint32_t *count = cbdata;
3716 *count = *count + 1;
3719 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3720 struct bnxt_vnic_info *vnic __rte_unused)
3725 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3729 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3730 &count, bnxt_vnic_count_hwrm_stub);
3735 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3738 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3739 struct hwrm_func_vf_vnic_ids_query_output *resp =
3740 bp->hwrm_cmd_resp_addr;
3743 /* First query all VNIC ids */
3744 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3746 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3747 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3748 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3750 if (req.vnic_id_tbl_addr == 0) {
3753 "unable to map VNIC ID table address to physical memory\n");
3756 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3759 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3761 } else if (resp->error_code) {
3762 rc = rte_le_to_cpu_16(resp->error_code);
3764 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3767 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3775 * This function queries the VNIC IDs for a specified VF. It then calls
3776 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3777 * Then it calls the hwrm_cb function to program this new vnic configuration.
3779 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3780 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3781 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3783 struct bnxt_vnic_info vnic;
3785 int i, num_vnic_ids;
3790 /* First query all VNIC ids */
3791 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3792 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3793 RTE_CACHE_LINE_SIZE);
3794 if (vnic_ids == NULL) {
3798 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3799 rte_mem_lock_page(((char *)vnic_ids) + sz);
3801 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3803 if (num_vnic_ids < 0)
3804 return num_vnic_ids;
3806 /* Retrieve VNIC, update bd_stall then update */
3808 for (i = 0; i < num_vnic_ids; i++) {
3809 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3810 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3811 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3814 if (vnic.mru <= 4) /* Indicates unallocated */
3817 vnic_cb(&vnic, cbdata);
3819 rc = hwrm_cb(bp, &vnic);
3829 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3832 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3833 struct hwrm_func_cfg_input req = {0};
3836 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3838 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3839 req.enables |= rte_cpu_to_le_32(
3840 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3841 req.vlan_antispoof_mode = on ?
3842 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3843 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3844 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3846 HWRM_CHECK_RESULT();
3852 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3854 struct bnxt_vnic_info vnic;
3857 int num_vnic_ids, i;
3861 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3862 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3863 RTE_CACHE_LINE_SIZE);
3864 if (vnic_ids == NULL) {
3869 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3870 rte_mem_lock_page(((char *)vnic_ids) + sz);
3872 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3878 * Loop through to find the default VNIC ID.
3879 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3880 * by sending the hwrm_func_qcfg command to the firmware.
3882 for (i = 0; i < num_vnic_ids; i++) {
3883 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3884 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3885 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3886 bp->pf.first_vf_id + vf);
3889 if (vnic.func_default) {
3891 return vnic.fw_vnic_id;
3894 /* Could not find a default VNIC. */
3895 PMD_DRV_LOG(ERR, "No default VNIC\n");
3901 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3903 struct bnxt_filter_info *filter)
3906 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3907 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3908 uint32_t enables = 0;
3910 if (filter->fw_em_filter_id != UINT64_MAX)
3911 bnxt_hwrm_clear_em_filter(bp, filter);
3913 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3915 req.flags = rte_cpu_to_le_32(filter->flags);
3917 enables = filter->enables |
3918 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3919 req.dst_id = rte_cpu_to_le_16(dst_id);
3921 if (filter->ip_addr_type) {
3922 req.ip_addr_type = filter->ip_addr_type;
3923 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3926 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3927 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3929 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3930 memcpy(req.src_macaddr, filter->src_macaddr,
3931 RTE_ETHER_ADDR_LEN);
3933 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3934 memcpy(req.dst_macaddr, filter->dst_macaddr,
3935 RTE_ETHER_ADDR_LEN);
3937 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3938 req.ovlan_vid = filter->l2_ovlan;
3940 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3941 req.ivlan_vid = filter->l2_ivlan;
3943 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3944 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3946 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3947 req.ip_protocol = filter->ip_protocol;
3949 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3950 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3952 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3953 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3955 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3956 req.src_port = rte_cpu_to_be_16(filter->src_port);
3958 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3959 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3961 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3962 req.mirror_vnic_id = filter->mirror_vnic_id;
3964 req.enables = rte_cpu_to_le_32(enables);
3966 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3968 HWRM_CHECK_RESULT();
3970 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3976 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3979 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3980 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3982 if (filter->fw_em_filter_id == UINT64_MAX)
3985 PMD_DRV_LOG(ERR, "Clear EM filter\n");
3986 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
3988 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3990 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3992 HWRM_CHECK_RESULT();
3995 filter->fw_em_filter_id = UINT64_MAX;
3996 filter->fw_l2_filter_id = UINT64_MAX;
4001 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4003 struct bnxt_filter_info *filter)
4006 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4007 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4008 bp->hwrm_cmd_resp_addr;
4009 uint32_t enables = 0;
4011 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4012 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4014 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4016 req.flags = rte_cpu_to_le_32(filter->flags);
4018 enables = filter->enables |
4019 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4020 req.dst_id = rte_cpu_to_le_16(dst_id);
4023 if (filter->ip_addr_type) {
4024 req.ip_addr_type = filter->ip_addr_type;
4026 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4029 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4030 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4032 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4033 memcpy(req.src_macaddr, filter->src_macaddr,
4034 RTE_ETHER_ADDR_LEN);
4036 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4037 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4038 //RTE_ETHER_ADDR_LEN);
4040 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4041 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4043 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4044 req.ip_protocol = filter->ip_protocol;
4046 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4047 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4049 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4050 req.src_ipaddr_mask[0] =
4051 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4053 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4054 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4056 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4057 req.dst_ipaddr_mask[0] =
4058 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4060 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4061 req.src_port = rte_cpu_to_le_16(filter->src_port);
4063 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4064 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4066 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4067 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4069 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4070 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4072 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4073 req.mirror_vnic_id = filter->mirror_vnic_id;
4075 req.enables = rte_cpu_to_le_32(enables);
4077 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4079 HWRM_CHECK_RESULT();
4081 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4087 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4088 struct bnxt_filter_info *filter)
4091 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4092 struct hwrm_cfa_ntuple_filter_free_output *resp =
4093 bp->hwrm_cmd_resp_addr;
4095 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4098 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4100 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4102 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4104 HWRM_CHECK_RESULT();
4107 filter->fw_ntuple_filter_id = UINT64_MAX;
4113 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4115 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4116 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4117 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4118 int nr_ctxs = bp->max_ring_grps;
4119 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4120 uint16_t *ring_tbl = vnic->rss_table;
4121 int max_rings = bp->rx_nr_rings;
4125 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4127 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4128 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4129 req.hash_mode_flags = vnic->hash_mode;
4131 req.ring_grp_tbl_addr =
4132 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
4133 req.hash_key_tbl_addr =
4134 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4136 for (i = 0, k = 0; i < nr_ctxs; i++) {
4137 struct bnxt_rx_ring_info *rxr;
4138 struct bnxt_cp_ring_info *cpr;
4140 req.ring_table_pair_index = i;
4141 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4143 for (j = 0; j < 64; j++) {
4146 /* Find next active ring. */
4147 for (cnt = 0; cnt < max_rings; cnt++) {
4148 if (rx_queue_state[k] !=
4149 RTE_ETH_QUEUE_STATE_STOPPED)
4151 if (++k == max_rings)
4155 /* Return if no rings are active. */
4156 if (cnt == max_rings)
4159 /* Add rx/cp ring pair to RSS table. */
4160 rxr = rxqs[k]->rx_ring;
4161 cpr = rxqs[k]->cp_ring;
4163 ring_id = rxr->rx_ring_struct->fw_ring_id;
4164 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4165 ring_id = cpr->cp_ring_struct->fw_ring_id;
4166 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4168 if (++k == max_rings)
4171 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4174 HWRM_CHECK_RESULT();
4184 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4186 unsigned int rss_idx, fw_idx, i;
4188 if (!(vnic->rss_table && vnic->hash_type))
4191 if (BNXT_CHIP_THOR(bp))
4192 return bnxt_vnic_rss_configure_thor(bp, vnic);
4195 * Fill the RSS hash & redirection table with
4196 * ring group ids for all VNICs
4198 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4199 rss_idx++, fw_idx++) {
4200 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4201 fw_idx %= bp->rx_cp_nr_rings;
4202 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4206 if (i == bp->rx_cp_nr_rings)
4208 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4210 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4213 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4214 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4218 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4220 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4221 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4223 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4224 req->num_cmpl_dma_aggr_during_int =
4225 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4227 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4229 /* min timer set to 1/2 of interrupt timer */
4230 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4232 /* buf timer set to 1/4 of interrupt timer */
4233 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4235 req->cmpl_aggr_dma_tmr_during_int =
4236 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4238 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4239 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4240 req->flags = rte_cpu_to_le_16(flags);
4243 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4244 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4246 struct hwrm_ring_aggint_qcaps_input req = {0};
4247 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4252 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4253 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4257 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4258 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4260 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4261 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4262 agg_req->flags = rte_cpu_to_le_16(flags);
4264 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4265 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4266 agg_req->enables = rte_cpu_to_le_32(enables);
4269 HWRM_CHECK_RESULT();
4274 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4275 struct bnxt_coal *coal, uint16_t ring_id)
4277 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4278 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4279 bp->hwrm_cmd_resp_addr;
4282 /* Set ring coalesce parameters only for 100G NICs */
4283 if (BNXT_CHIP_THOR(bp)) {
4284 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4286 } else if (bnxt_stratus_device(bp)) {
4287 bnxt_hwrm_set_coal_params(coal, &req);
4292 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4293 req.ring_id = rte_cpu_to_le_16(ring_id);
4294 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4295 HWRM_CHECK_RESULT();
4300 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4301 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4303 struct hwrm_func_backing_store_qcaps_input req = {0};
4304 struct hwrm_func_backing_store_qcaps_output *resp =
4305 bp->hwrm_cmd_resp_addr;
4308 if (!BNXT_CHIP_THOR(bp) ||
4309 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4314 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4315 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4316 HWRM_CHECK_RESULT_SILENT();
4319 struct bnxt_ctx_pg_info *ctx_pg;
4320 struct bnxt_ctx_mem_info *ctx;
4321 int total_alloc_len;
4324 total_alloc_len = sizeof(*ctx);
4325 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4326 RTE_CACHE_LINE_SIZE);
4331 memset(ctx, 0, total_alloc_len);
4333 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4334 sizeof(*ctx_pg) * BNXT_MAX_Q,
4335 RTE_CACHE_LINE_SIZE);
4340 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4341 ctx->tqm_mem[i] = ctx_pg;
4344 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4345 ctx->qp_min_qp1_entries =
4346 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4347 ctx->qp_max_l2_entries =
4348 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4349 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4350 ctx->srq_max_l2_entries =
4351 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4352 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4353 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4354 ctx->cq_max_l2_entries =
4355 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4356 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4357 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4358 ctx->vnic_max_vnic_entries =
4359 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4360 ctx->vnic_max_ring_table_entries =
4361 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4362 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4363 ctx->stat_max_entries =
4364 rte_le_to_cpu_32(resp->stat_max_entries);
4365 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4366 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4367 ctx->tqm_min_entries_per_ring =
4368 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4369 ctx->tqm_max_entries_per_ring =
4370 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4371 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4372 if (!ctx->tqm_entries_multiple)
4373 ctx->tqm_entries_multiple = 1;
4374 ctx->mrav_max_entries =
4375 rte_le_to_cpu_32(resp->mrav_max_entries);
4376 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4377 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4378 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4387 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4389 struct hwrm_func_backing_store_cfg_input req = {0};
4390 struct hwrm_func_backing_store_cfg_output *resp =
4391 bp->hwrm_cmd_resp_addr;
4392 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4393 struct bnxt_ctx_pg_info *ctx_pg;
4394 uint32_t *num_entries;
4403 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4404 req.enables = rte_cpu_to_le_32(enables);
4406 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4407 ctx_pg = &ctx->qp_mem;
4408 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4409 req.qp_num_qp1_entries =
4410 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4411 req.qp_num_l2_entries =
4412 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4413 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4414 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4415 &req.qpc_pg_size_qpc_lvl,
4419 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4420 ctx_pg = &ctx->srq_mem;
4421 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4422 req.srq_num_l2_entries =
4423 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4424 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4425 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4426 &req.srq_pg_size_srq_lvl,
4430 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4431 ctx_pg = &ctx->cq_mem;
4432 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4433 req.cq_num_l2_entries =
4434 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4435 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4436 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4437 &req.cq_pg_size_cq_lvl,
4441 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4442 ctx_pg = &ctx->vnic_mem;
4443 req.vnic_num_vnic_entries =
4444 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4445 req.vnic_num_ring_table_entries =
4446 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4447 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4448 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4449 &req.vnic_pg_size_vnic_lvl,
4450 &req.vnic_page_dir);
4453 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4454 ctx_pg = &ctx->stat_mem;
4455 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4456 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4457 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4458 &req.stat_pg_size_stat_lvl,
4459 &req.stat_page_dir);
4462 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4463 num_entries = &req.tqm_sp_num_entries;
4464 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4465 pg_dir = &req.tqm_sp_page_dir;
4466 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4467 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4468 if (!(enables & ena))
4471 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4473 ctx_pg = ctx->tqm_mem[i];
4474 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4475 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4478 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4479 HWRM_CHECK_RESULT();
4486 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4488 struct hwrm_port_qstats_ext_input req = {0};
4489 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4490 struct bnxt_pf_info *pf = &bp->pf;
4493 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4494 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4497 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4499 req.port_id = rte_cpu_to_le_16(pf->port_id);
4500 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4501 req.tx_stat_host_addr =
4502 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4504 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4506 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4507 req.rx_stat_host_addr =
4508 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4510 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4512 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4515 bp->fw_rx_port_stats_ext_size = 0;
4516 bp->fw_tx_port_stats_ext_size = 0;
4518 bp->fw_rx_port_stats_ext_size =
4519 rte_le_to_cpu_16(resp->rx_stat_size);
4520 bp->fw_tx_port_stats_ext_size =
4521 rte_le_to_cpu_16(resp->tx_stat_size);
4524 HWRM_CHECK_RESULT();
4531 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4533 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4534 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4535 bp->hwrm_cmd_resp_addr;
4538 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_KONG(bp));
4539 req.tunnel_type = type;
4540 req.dest_fid = bp->fw_fid;
4541 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4542 HWRM_CHECK_RESULT();
4550 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4552 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4553 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4554 bp->hwrm_cmd_resp_addr;
4557 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_KONG(bp));
4558 req.tunnel_type = type;
4559 req.dest_fid = bp->fw_fid;
4560 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4561 HWRM_CHECK_RESULT();
4568 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4570 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4571 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4572 bp->hwrm_cmd_resp_addr;
4575 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_KONG(bp));
4576 req.src_fid = bp->fw_fid;
4577 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4578 HWRM_CHECK_RESULT();
4581 *type = resp->tunnel_mask;
4588 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4591 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4592 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4593 bp->hwrm_cmd_resp_addr;
4596 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_KONG(bp));
4597 req.src_fid = bp->fw_fid;
4598 req.tunnel_type = tun_type;
4599 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4600 HWRM_CHECK_RESULT();
4603 *dst_fid = resp->dest_fid;
4605 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4612 int bnxt_hwrm_set_mac(struct bnxt *bp)
4614 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4615 struct hwrm_func_vf_cfg_input req = {0};
4621 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4624 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4625 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4627 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4629 HWRM_CHECK_RESULT();
4631 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);