1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(void *) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
67 if (rmem->nr_pages > 1) {
69 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
71 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
76 * HWRM Functions (sent to HWRM)
77 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
78 * HWRM command times out, or a negative error code if the HWRM
79 * command was failed by the FW.
82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
83 uint32_t msg_len, bool use_kong_mb)
86 struct input *req = msg;
87 struct output *resp = bp->hwrm_cmd_resp_addr;
91 uint16_t max_req_len = bp->max_req_len;
92 struct hwrm_short_input short_input = { 0 };
93 uint16_t bar_offset = use_kong_mb ?
94 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
95 uint16_t mb_trigger_offset = use_kong_mb ?
96 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
99 /* Do not send HWRM commands to firmware in error state */
100 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
103 /* For VER_GET command, set timeout as 50ms */
104 if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
105 timeout = HWRM_CMD_TIMEOUT;
107 timeout = bp->hwrm_cmd_timeout;
109 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
110 msg_len > bp->max_req_len) {
111 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
113 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
114 memcpy(short_cmd_req, req, msg_len);
116 short_input.req_type = rte_cpu_to_le_16(req->req_type);
117 short_input.signature = rte_cpu_to_le_16(
118 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
119 short_input.size = rte_cpu_to_le_16(msg_len);
120 short_input.req_addr =
121 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
123 data = (uint32_t *)&short_input;
124 msg_len = sizeof(short_input);
126 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
129 /* Write request msg to hwrm channel */
130 for (i = 0; i < msg_len; i += 4) {
131 bar = (uint8_t *)bp->bar0 + bar_offset + i;
132 rte_write32(*data, bar);
136 /* Zero the rest of the request space */
137 for (; i < max_req_len; i += 4) {
138 bar = (uint8_t *)bp->bar0 + bar_offset + i;
142 /* Ring channel doorbell */
143 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
146 * Make sure the channel doorbell ring command complete before
147 * reading the response to avoid getting stale or invalid
152 /* Poll for the valid bit */
153 for (i = 0; i < timeout; i++) {
154 /* Sanity check on the resp->resp_len */
156 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
157 /* Last byte of resp contains the valid key */
158 valid = (uint8_t *)resp + resp->resp_len - 1;
159 if (*valid == HWRM_RESP_VALID_KEY)
166 /* Suppress VER_GET timeout messages during reset recovery */
167 if (bp->flags & BNXT_FLAG_FW_RESET &&
168 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
171 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
179 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
180 * spinlock, and does initial processing.
182 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
183 * releases the spinlock only if it returns. If the regular int return codes
184 * are not used by the function, HWRM_CHECK_RESULT() should not be used
185 * directly, rather it should be copied and modified to suit the function.
187 * HWRM_UNLOCK() must be called after all response processing is completed.
189 #define HWRM_PREP(req, type, kong) do { \
190 rte_spinlock_lock(&bp->hwrm_lock); \
191 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
192 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
193 req.cmpl_ring = rte_cpu_to_le_16(-1); \
194 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
195 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
196 req.target_id = rte_cpu_to_le_16(0xffff); \
197 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
200 #define HWRM_CHECK_RESULT_SILENT() do {\
202 rte_spinlock_unlock(&bp->hwrm_lock); \
205 if (resp->error_code) { \
206 rc = rte_le_to_cpu_16(resp->error_code); \
207 rte_spinlock_unlock(&bp->hwrm_lock); \
212 #define HWRM_CHECK_RESULT() do {\
214 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
215 rte_spinlock_unlock(&bp->hwrm_lock); \
216 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
218 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
220 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
222 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
228 if (resp->error_code) { \
229 rc = rte_le_to_cpu_16(resp->error_code); \
230 if (resp->resp_len >= 16) { \
231 struct hwrm_err_output *tmp_hwrm_err_op = \
234 "error %d:%d:%08x:%04x\n", \
235 rc, tmp_hwrm_err_op->cmd_err, \
237 tmp_hwrm_err_op->opaque_0), \
239 tmp_hwrm_err_op->opaque_1)); \
241 PMD_DRV_LOG(ERR, "error %d\n", rc); \
243 rte_spinlock_unlock(&bp->hwrm_lock); \
244 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
246 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
248 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
250 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
258 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
260 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
263 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
264 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
266 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
267 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
270 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
278 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
279 struct bnxt_vnic_info *vnic,
281 struct bnxt_vlan_table_entry *vlan_table)
284 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
285 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
288 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
291 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
292 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
294 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
295 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
296 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
297 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
299 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
300 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
302 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
303 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
304 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
305 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
306 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
307 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
310 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
311 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
312 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
313 rte_mem_virt2iova(vlan_table));
314 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
316 req.mask = rte_cpu_to_le_32(mask);
318 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
326 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
328 struct bnxt_vlan_antispoof_table_entry *vlan_table)
331 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
332 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
333 bp->hwrm_cmd_resp_addr;
336 * Older HWRM versions did not support this command, and the set_rx_mask
337 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
338 * removed from set_rx_mask call, and this command was added.
340 * This command is also present from 1.7.8.11 and higher,
343 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
344 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
345 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
350 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
351 req.fid = rte_cpu_to_le_16(fid);
353 req.vlan_tag_mask_tbl_addr =
354 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
355 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
365 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
366 struct bnxt_filter_info *filter)
369 struct bnxt_filter_info *l2_filter = filter;
370 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
371 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
373 if (filter->fw_l2_filter_id == UINT64_MAX)
376 if (filter->matching_l2_fltr_ptr)
377 l2_filter = filter->matching_l2_fltr_ptr;
379 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
380 filter, l2_filter, l2_filter->l2_ref_cnt);
382 if (l2_filter->l2_ref_cnt > 0)
383 l2_filter->l2_ref_cnt--;
385 if (l2_filter->l2_ref_cnt > 0)
388 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
390 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
392 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
397 filter->fw_l2_filter_id = UINT64_MAX;
402 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
404 struct bnxt_filter_info *filter)
407 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
408 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
409 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
410 const struct rte_eth_vmdq_rx_conf *conf =
411 &dev_conf->rx_adv_conf.vmdq_rx_conf;
412 uint32_t enables = 0;
413 uint16_t j = dst_id - 1;
415 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
416 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
417 conf->pool_map[j].pools & (1UL << j)) {
419 "Add vlan %u to vmdq pool %u\n",
420 conf->pool_map[j].vlan_id, j);
422 filter->l2_ivlan = conf->pool_map[j].vlan_id;
424 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
425 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
428 if (filter->fw_l2_filter_id != UINT64_MAX)
429 bnxt_hwrm_clear_l2_filter(bp, filter);
431 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
433 req.flags = rte_cpu_to_le_32(filter->flags);
435 enables = filter->enables |
436 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
437 req.dst_id = rte_cpu_to_le_16(dst_id);
440 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
441 memcpy(req.l2_addr, filter->l2_addr,
444 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
445 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
448 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
449 req.l2_ovlan = filter->l2_ovlan;
451 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
452 req.l2_ivlan = filter->l2_ivlan;
454 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
455 req.l2_ovlan_mask = filter->l2_ovlan_mask;
457 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
458 req.l2_ivlan_mask = filter->l2_ivlan_mask;
459 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
460 req.src_id = rte_cpu_to_le_32(filter->src_id);
461 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
462 req.src_type = filter->src_type;
463 if (filter->pri_hint) {
464 req.pri_hint = filter->pri_hint;
465 req.l2_filter_id_hint =
466 rte_cpu_to_le_64(filter->l2_filter_id_hint);
469 req.enables = rte_cpu_to_le_32(enables);
471 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
475 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
481 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
483 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
484 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
491 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
494 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
497 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
498 if (ptp->tx_tstamp_en)
499 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
502 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
503 req.flags = rte_cpu_to_le_32(flags);
504 req.enables = rte_cpu_to_le_32
505 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
506 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
508 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
514 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
517 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
518 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
519 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
524 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
526 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
528 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
532 if (!BNXT_CHIP_THOR(bp) &&
533 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
536 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
537 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
539 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
543 if (!BNXT_CHIP_THOR(bp)) {
544 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
545 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
546 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
547 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
548 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
549 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
550 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
551 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
552 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
553 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
554 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
555 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
556 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
557 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
558 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
559 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
560 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
561 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
570 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
573 struct hwrm_func_qcaps_input req = {.req_type = 0 };
574 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
575 uint16_t new_max_vfs;
579 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
581 req.fid = rte_cpu_to_le_16(0xffff);
583 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
587 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
588 flags = rte_le_to_cpu_32(resp->flags);
590 bp->pf.port_id = resp->port_id;
591 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
592 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
593 new_max_vfs = bp->pdev->max_vfs;
594 if (new_max_vfs != bp->pf.max_vfs) {
596 rte_free(bp->pf.vf_info);
597 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
598 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
599 bp->pf.max_vfs = new_max_vfs;
600 for (i = 0; i < new_max_vfs; i++) {
601 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
602 bp->pf.vf_info[i].vlan_table =
603 rte_zmalloc("VF VLAN table",
606 if (bp->pf.vf_info[i].vlan_table == NULL)
608 "Fail to alloc VLAN table for VF %d\n",
612 bp->pf.vf_info[i].vlan_table);
613 bp->pf.vf_info[i].vlan_as_table =
614 rte_zmalloc("VF VLAN AS table",
617 if (bp->pf.vf_info[i].vlan_as_table == NULL)
619 "Alloc VLAN AS table for VF %d fail\n",
623 bp->pf.vf_info[i].vlan_as_table);
624 STAILQ_INIT(&bp->pf.vf_info[i].filter);
629 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
630 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
631 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
632 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
633 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
634 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
635 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
636 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
637 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
638 if (!BNXT_CHIP_THOR(bp))
639 bp->max_l2_ctx += bp->max_rx_em_flows;
640 /* TODO: For now, do not support VMDq/RFS on VFs. */
645 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
649 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
651 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
652 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
653 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
654 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
656 bnxt_hwrm_ptp_qcfg(bp);
660 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
661 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
663 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
664 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
665 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
668 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
669 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
671 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
672 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
679 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
683 rc = __bnxt_hwrm_func_qcaps(bp);
684 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
685 rc = bnxt_alloc_ctx_mem(bp);
689 rc = bnxt_hwrm_func_resc_qcaps(bp);
691 bp->flags |= BNXT_FLAG_NEW_RM;
695 * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
696 * But the error can be ignored. Return success.
702 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
703 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
706 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
707 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
709 HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
711 req.target_id = rte_cpu_to_le_16(0xffff);
713 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
717 if (rte_le_to_cpu_32(resp->flags) &
718 HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
719 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
720 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
723 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
730 int bnxt_hwrm_func_reset(struct bnxt *bp)
733 struct hwrm_func_reset_input req = {.req_type = 0 };
734 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
736 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
738 req.enables = rte_cpu_to_le_32(0);
740 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
748 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
752 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
753 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
755 if (bp->flags & BNXT_FLAG_REGISTERED)
758 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
759 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
760 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
761 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
763 /* PFs and trusted VFs should indicate the support of the
764 * Master capability on non Stingray platform
766 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
767 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
769 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
770 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
771 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
772 req.ver_maj = RTE_VER_YEAR;
773 req.ver_min = RTE_VER_MONTH;
774 req.ver_upd = RTE_VER_MINOR;
777 req.enables |= rte_cpu_to_le_32(
778 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
779 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
780 RTE_MIN(sizeof(req.vf_req_fwd),
781 sizeof(bp->pf.vf_req_fwd)));
784 * PF can sniff HWRM API issued by VF. This can be set up by
785 * linux driver and inherited by the DPDK PF driver. Clear
786 * this HWRM sniffer list in FW because DPDK PF driver does
789 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
792 req.flags = rte_cpu_to_le_32(flags);
794 req.async_event_fwd[0] |=
795 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
796 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
797 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
798 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
799 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
800 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
801 req.async_event_fwd[0] |=
802 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
803 req.async_event_fwd[1] |=
804 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
805 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
807 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
811 flags = rte_le_to_cpu_32(resp->flags);
812 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
813 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
817 bp->flags |= BNXT_FLAG_REGISTERED;
822 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
824 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
827 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
830 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
835 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
836 struct hwrm_func_vf_cfg_input req = {0};
838 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
840 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
841 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
842 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
843 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
844 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
846 if (BNXT_HAS_RING_GRPS(bp)) {
847 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
848 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
851 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
852 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
853 AGG_RING_MULTIPLIER);
854 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
855 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
857 BNXT_NUM_ASYNC_CPR(bp));
858 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
859 if (bp->vf_resv_strategy ==
860 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
861 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
862 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
863 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
864 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
865 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
866 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
867 } else if (bp->vf_resv_strategy ==
868 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
869 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
870 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
874 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
875 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
876 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
877 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
878 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
879 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
881 if (test && BNXT_HAS_RING_GRPS(bp))
882 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
884 req.flags = rte_cpu_to_le_32(flags);
885 req.enables |= rte_cpu_to_le_32(enables);
887 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
890 HWRM_CHECK_RESULT_SILENT();
898 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
901 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
902 struct hwrm_func_resource_qcaps_input req = {0};
904 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
905 req.fid = rte_cpu_to_le_16(0xffff);
907 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
909 HWRM_CHECK_RESULT_SILENT();
912 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
913 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
914 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
915 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
916 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
917 /* func_resource_qcaps does not return max_rx_em_flows.
918 * So use the value provided by func_qcaps.
920 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
921 if (!BNXT_CHIP_THOR(bp))
922 bp->max_l2_ctx += bp->max_rx_em_flows;
923 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
924 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
926 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
927 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
928 if (bp->vf_resv_strategy >
929 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
930 bp->vf_resv_strategy =
931 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
937 int bnxt_hwrm_ver_get(struct bnxt *bp)
940 struct hwrm_ver_get_input req = {.req_type = 0 };
941 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
943 uint16_t max_resp_len;
944 char type[RTE_MEMZONE_NAMESIZE];
945 uint32_t dev_caps_cfg;
947 bp->max_req_len = HWRM_MAX_REQ_LEN;
948 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
950 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
951 req.hwrm_intf_min = HWRM_VERSION_MINOR;
952 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
954 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
956 if (bp->flags & BNXT_FLAG_FW_RESET)
957 HWRM_CHECK_RESULT_SILENT();
961 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
962 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
963 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
964 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
965 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
966 (resp->hwrm_fw_min_8b << 16) |
967 (resp->hwrm_fw_bld_8b << 8) |
968 resp->hwrm_fw_rsvd_8b;
969 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
970 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
972 fw_version = resp->hwrm_intf_maj_8b << 16;
973 fw_version |= resp->hwrm_intf_min_8b << 8;
974 fw_version |= resp->hwrm_intf_upd_8b;
975 bp->hwrm_spec_code = fw_version;
977 /* def_req_timeout value is in milliseconds */
978 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
979 /* convert timeout to usec */
980 bp->hwrm_cmd_timeout *= 1000;
981 if (!bp->hwrm_cmd_timeout)
982 bp->hwrm_cmd_timeout = HWRM_CMD_TIMEOUT;
984 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
985 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
990 if (bp->max_req_len > resp->max_req_win_len) {
991 PMD_DRV_LOG(ERR, "Unsupported request length\n");
994 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
995 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
996 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
997 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
999 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1000 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1002 if (bp->max_resp_len != max_resp_len) {
1003 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
1004 bp->pdev->addr.domain, bp->pdev->addr.bus,
1005 bp->pdev->addr.devid, bp->pdev->addr.function);
1007 rte_free(bp->hwrm_cmd_resp_addr);
1009 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1010 if (bp->hwrm_cmd_resp_addr == NULL) {
1014 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1015 bp->hwrm_cmd_resp_dma_addr =
1016 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1017 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1019 "Unable to map response buffer to physical memory.\n");
1023 bp->max_resp_len = max_resp_len;
1027 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1029 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1030 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1031 bp->flags |= BNXT_FLAG_SHORT_CMD;
1034 if (((dev_caps_cfg &
1035 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1037 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1038 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1039 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1040 bp->pdev->addr.domain, bp->pdev->addr.bus,
1041 bp->pdev->addr.devid, bp->pdev->addr.function);
1043 rte_free(bp->hwrm_short_cmd_req_addr);
1045 bp->hwrm_short_cmd_req_addr =
1046 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1047 if (bp->hwrm_short_cmd_req_addr == NULL) {
1051 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1052 bp->hwrm_short_cmd_req_dma_addr =
1053 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1054 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1055 rte_free(bp->hwrm_short_cmd_req_addr);
1057 "Unable to map buffer to physical memory.\n");
1063 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1064 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1065 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1068 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1069 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1071 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1072 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1073 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1081 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1084 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1085 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1087 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1090 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1093 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1095 HWRM_CHECK_RESULT();
1101 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1104 struct hwrm_port_phy_cfg_input req = {0};
1105 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1106 uint32_t enables = 0;
1108 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1110 if (conf->link_up) {
1111 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1112 if (bp->link_info.auto_mode && conf->link_speed) {
1113 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1114 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1117 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1118 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1119 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1121 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1122 * any auto mode, even "none".
1124 if (!conf->link_speed) {
1125 /* No speeds specified. Enable AutoNeg - all speeds */
1127 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1129 /* AutoNeg - Advertise speeds specified. */
1130 if (conf->auto_link_speed_mask &&
1131 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1133 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1134 req.auto_link_speed_mask =
1135 conf->auto_link_speed_mask;
1137 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1140 req.auto_duplex = conf->duplex;
1141 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1142 req.auto_pause = conf->auto_pause;
1143 req.force_pause = conf->force_pause;
1144 /* Set force_pause if there is no auto or if there is a force */
1145 if (req.auto_pause && !req.force_pause)
1146 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1148 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1150 req.enables = rte_cpu_to_le_32(enables);
1153 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1154 PMD_DRV_LOG(INFO, "Force Link Down\n");
1157 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1159 HWRM_CHECK_RESULT();
1165 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1166 struct bnxt_link_info *link_info)
1169 struct hwrm_port_phy_qcfg_input req = {0};
1170 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1172 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1174 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1176 HWRM_CHECK_RESULT();
1178 link_info->phy_link_status = resp->link;
1179 link_info->link_up =
1180 (link_info->phy_link_status ==
1181 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1182 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1183 link_info->duplex = resp->duplex_cfg;
1184 link_info->pause = resp->pause;
1185 link_info->auto_pause = resp->auto_pause;
1186 link_info->force_pause = resp->force_pause;
1187 link_info->auto_mode = resp->auto_mode;
1188 link_info->phy_type = resp->phy_type;
1189 link_info->media_type = resp->media_type;
1191 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1192 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1193 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1194 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1195 link_info->phy_ver[0] = resp->phy_maj;
1196 link_info->phy_ver[1] = resp->phy_min;
1197 link_info->phy_ver[2] = resp->phy_bld;
1201 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1202 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1203 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1204 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1205 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1206 link_info->auto_link_speed_mask);
1207 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1208 link_info->force_link_speed);
1213 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1217 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1218 if (bp->tx_cos_queue[i].profile ==
1219 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1220 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1227 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1231 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1232 if (bp->tx_cos_queue[i].profile !=
1233 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1234 bp->tx_cos_queue[i].id !=
1235 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1236 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1242 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1245 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1246 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1247 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1251 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1253 req.flags = rte_cpu_to_le_32(dir);
1254 /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1255 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1256 !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1258 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1259 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1261 HWRM_CHECK_RESULT();
1263 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1264 GET_TX_QUEUE_INFO(0);
1265 GET_TX_QUEUE_INFO(1);
1266 GET_TX_QUEUE_INFO(2);
1267 GET_TX_QUEUE_INFO(3);
1268 GET_TX_QUEUE_INFO(4);
1269 GET_TX_QUEUE_INFO(5);
1270 GET_TX_QUEUE_INFO(6);
1271 GET_TX_QUEUE_INFO(7);
1273 GET_RX_QUEUE_INFO(0);
1274 GET_RX_QUEUE_INFO(1);
1275 GET_RX_QUEUE_INFO(2);
1276 GET_RX_QUEUE_INFO(3);
1277 GET_RX_QUEUE_INFO(4);
1278 GET_RX_QUEUE_INFO(5);
1279 GET_RX_QUEUE_INFO(6);
1280 GET_RX_QUEUE_INFO(7);
1285 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1288 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1289 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1293 /* iterate and find the COSq profile to use for Tx */
1294 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1295 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1296 if (bp->tx_cos_queue[i].id != 0xff)
1297 bp->tx_cosq_id[j++] =
1298 bp->tx_cos_queue[i].id;
1301 /* When CoS classification is disabled, for normal NIC
1302 * operations, ideally we should look to use LOSSY.
1303 * If not found, fallback to the first valid profile
1305 if (!bnxt_find_lossy_profile(bp))
1306 bnxt_find_first_valid_profile(bp);
1311 bp->max_tc = resp->max_configurable_queues;
1312 bp->max_lltc = resp->max_configurable_lossless_queues;
1313 if (bp->max_tc > BNXT_MAX_QUEUE)
1314 bp->max_tc = BNXT_MAX_QUEUE;
1315 bp->max_q = bp->max_tc;
1317 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1318 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1326 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1327 struct bnxt_ring *ring,
1328 uint32_t ring_type, uint32_t map_index,
1329 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1330 uint16_t tx_cosq_id)
1333 uint32_t enables = 0;
1334 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1335 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1336 struct rte_mempool *mb_pool;
1337 uint16_t rx_buf_size;
1339 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1341 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1342 req.fbo = rte_cpu_to_le_32(0);
1343 /* Association of ring index with doorbell index */
1344 req.logical_id = rte_cpu_to_le_16(map_index);
1345 req.length = rte_cpu_to_le_32(ring->ring_size);
1347 switch (ring_type) {
1348 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1349 req.ring_type = ring_type;
1350 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1351 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1352 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1353 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1355 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1357 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1358 req.ring_type = ring_type;
1359 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1360 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1361 if (BNXT_CHIP_THOR(bp)) {
1362 mb_pool = bp->rx_queues[0]->mb_pool;
1363 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1364 RTE_PKTMBUF_HEADROOM;
1365 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1366 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1368 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1370 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1372 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1374 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1375 req.ring_type = ring_type;
1376 if (BNXT_HAS_NQ(bp)) {
1377 /* Association of cp ring with nq */
1378 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1380 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1382 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1384 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1385 req.ring_type = ring_type;
1386 req.page_size = BNXT_PAGE_SHFT;
1387 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1389 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1390 req.ring_type = ring_type;
1391 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1393 mb_pool = bp->rx_queues[0]->mb_pool;
1394 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1395 RTE_PKTMBUF_HEADROOM;
1396 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1397 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1399 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1400 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1401 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1402 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1405 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1410 req.enables = rte_cpu_to_le_32(enables);
1412 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1414 if (rc || resp->error_code) {
1415 if (rc == 0 && resp->error_code)
1416 rc = rte_le_to_cpu_16(resp->error_code);
1417 switch (ring_type) {
1418 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1420 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1423 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1425 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1428 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1430 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1434 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1436 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1439 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1441 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1445 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1451 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1456 int bnxt_hwrm_ring_free(struct bnxt *bp,
1457 struct bnxt_ring *ring, uint32_t ring_type)
1460 struct hwrm_ring_free_input req = {.req_type = 0 };
1461 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1463 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1465 req.ring_type = ring_type;
1466 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1468 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1470 if (rc || resp->error_code) {
1471 if (rc == 0 && resp->error_code)
1472 rc = rte_le_to_cpu_16(resp->error_code);
1475 switch (ring_type) {
1476 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1477 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1480 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1481 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1484 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1485 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1488 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1490 "hwrm_ring_free nq failed. rc:%d\n", rc);
1492 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1494 "hwrm_ring_free agg failed. rc:%d\n", rc);
1497 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1505 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1508 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1509 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1511 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1513 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1514 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1515 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1516 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1518 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1520 HWRM_CHECK_RESULT();
1522 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1529 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1532 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1533 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1535 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1537 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1539 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1541 HWRM_CHECK_RESULT();
1544 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1548 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1551 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1552 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1554 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1557 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1559 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1561 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1563 HWRM_CHECK_RESULT();
1569 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1570 unsigned int idx __rte_unused)
1573 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1574 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1576 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1578 req.update_period_ms = rte_cpu_to_le_32(0);
1580 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1582 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1584 HWRM_CHECK_RESULT();
1586 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1593 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1594 unsigned int idx __rte_unused)
1597 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1598 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1600 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1602 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1604 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1606 HWRM_CHECK_RESULT();
1612 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1615 struct hwrm_vnic_alloc_input req = { 0 };
1616 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1618 if (!BNXT_HAS_RING_GRPS(bp))
1619 goto skip_ring_grps;
1621 /* map ring groups to this vnic */
1622 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1623 vnic->start_grp_id, vnic->end_grp_id);
1624 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1625 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1627 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1628 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1629 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1630 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1633 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1634 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1636 if (vnic->func_default)
1638 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1639 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1641 HWRM_CHECK_RESULT();
1643 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1645 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1649 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1650 struct bnxt_vnic_info *vnic,
1651 struct bnxt_plcmodes_cfg *pmode)
1654 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1655 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1657 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1659 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1661 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1663 HWRM_CHECK_RESULT();
1665 pmode->flags = rte_le_to_cpu_32(resp->flags);
1666 /* dflt_vnic bit doesn't exist in the _cfg command */
1667 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1668 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1669 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1670 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1677 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1678 struct bnxt_vnic_info *vnic,
1679 struct bnxt_plcmodes_cfg *pmode)
1682 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1683 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1685 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1686 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1690 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1692 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1693 req.flags = rte_cpu_to_le_32(pmode->flags);
1694 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1695 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1696 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1697 req.enables = rte_cpu_to_le_32(
1698 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1699 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1700 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1703 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1705 HWRM_CHECK_RESULT();
1711 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1714 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1715 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1716 struct bnxt_plcmodes_cfg pmodes = { 0 };
1717 uint32_t ctx_enable_flag = 0;
1718 uint32_t enables = 0;
1720 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1721 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1725 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1729 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1731 if (BNXT_CHIP_THOR(bp)) {
1732 int dflt_rxq = vnic->start_grp_id;
1733 struct bnxt_rx_ring_info *rxr;
1734 struct bnxt_cp_ring_info *cpr;
1735 struct bnxt_rx_queue *rxq;
1739 * The first active receive ring is used as the VNIC
1740 * default receive ring. If there are no active receive
1741 * rings (all corresponding receive queues are stopped),
1742 * the first receive ring is used.
1744 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1745 rxq = bp->eth_dev->data->rx_queues[i];
1746 if (rxq->rx_started) {
1752 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1756 req.default_rx_ring_id =
1757 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1758 req.default_cmpl_ring_id =
1759 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1760 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1761 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1765 /* Only RSS support for now TBD: COS & LB */
1766 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1767 if (vnic->lb_rule != 0xffff)
1768 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1769 if (vnic->cos_rule != 0xffff)
1770 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1771 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1772 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1773 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1775 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1776 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1777 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1780 enables |= ctx_enable_flag;
1781 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1782 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1783 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1784 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1787 req.enables = rte_cpu_to_le_32(enables);
1788 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1789 req.mru = rte_cpu_to_le_16(vnic->mru);
1790 /* Configure default VNIC only once. */
1791 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1793 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1794 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1796 if (vnic->vlan_strip)
1798 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1801 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1802 if (vnic->roce_dual)
1803 req.flags |= rte_cpu_to_le_32(
1804 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1805 if (vnic->roce_only)
1806 req.flags |= rte_cpu_to_le_32(
1807 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1808 if (vnic->rss_dflt_cr)
1809 req.flags |= rte_cpu_to_le_32(
1810 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1812 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1814 HWRM_CHECK_RESULT();
1817 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1822 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1826 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1827 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1829 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1830 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1833 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1836 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1837 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1838 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1840 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1842 HWRM_CHECK_RESULT();
1844 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1845 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1846 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1847 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1848 vnic->mru = rte_le_to_cpu_16(resp->mru);
1849 vnic->func_default = rte_le_to_cpu_32(
1850 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1851 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1852 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1853 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1854 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1855 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1856 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1857 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1858 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1859 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1860 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1867 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1868 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1872 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1873 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1874 bp->hwrm_cmd_resp_addr;
1876 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1878 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1879 HWRM_CHECK_RESULT();
1881 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1882 if (!BNXT_HAS_RING_GRPS(bp))
1883 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1884 else if (ctx_idx == 0)
1885 vnic->rss_rule = ctx_id;
1893 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1894 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1897 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1898 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1899 bp->hwrm_cmd_resp_addr;
1901 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1902 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1905 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1907 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1909 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1911 HWRM_CHECK_RESULT();
1917 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1921 if (BNXT_CHIP_THOR(bp)) {
1924 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1925 rc = _bnxt_hwrm_vnic_ctx_free(bp,
1927 vnic->fw_grp_ids[j]);
1928 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1930 vnic->num_lb_ctxts = 0;
1932 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1933 vnic->rss_rule = INVALID_HW_RING_ID;
1939 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1942 struct hwrm_vnic_free_input req = {.req_type = 0 };
1943 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1945 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1946 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1950 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1952 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1954 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1956 HWRM_CHECK_RESULT();
1959 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1960 /* Configure default VNIC again if necessary. */
1961 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1962 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1968 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1972 int nr_ctxs = vnic->num_lb_ctxts;
1973 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1974 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1976 for (i = 0; i < nr_ctxs; i++) {
1977 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1979 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1980 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1981 req.hash_mode_flags = vnic->hash_mode;
1983 req.hash_key_tbl_addr =
1984 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1986 req.ring_grp_tbl_addr =
1987 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1988 i * HW_HASH_INDEX_SIZE);
1989 req.ring_table_pair_index = i;
1990 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1992 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1995 HWRM_CHECK_RESULT();
2002 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2003 struct bnxt_vnic_info *vnic)
2006 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2007 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2009 if (!vnic->rss_table)
2012 if (BNXT_CHIP_THOR(bp))
2013 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2015 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2017 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2018 req.hash_mode_flags = vnic->hash_mode;
2020 req.ring_grp_tbl_addr =
2021 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2022 req.hash_key_tbl_addr =
2023 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2024 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2025 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2027 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2029 HWRM_CHECK_RESULT();
2035 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2036 struct bnxt_vnic_info *vnic)
2039 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2040 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2043 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2044 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2048 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2050 req.flags = rte_cpu_to_le_32(
2051 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2053 req.enables = rte_cpu_to_le_32(
2054 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2056 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2057 size -= RTE_PKTMBUF_HEADROOM;
2058 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2060 req.jumbo_thresh = rte_cpu_to_le_16(size);
2061 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2063 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2065 HWRM_CHECK_RESULT();
2071 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2072 struct bnxt_vnic_info *vnic, bool enable)
2075 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2076 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2078 if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2080 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2084 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2085 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2089 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2092 req.enables = rte_cpu_to_le_32(
2093 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2094 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2095 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2096 req.flags = rte_cpu_to_le_32(
2097 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2098 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2099 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2100 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2101 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2102 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2103 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2104 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2105 req.min_agg_len = rte_cpu_to_le_32(512);
2107 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2109 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2111 HWRM_CHECK_RESULT();
2117 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2119 struct hwrm_func_cfg_input req = {0};
2120 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2123 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2124 req.enables = rte_cpu_to_le_32(
2125 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2126 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2127 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2129 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2131 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2132 HWRM_CHECK_RESULT();
2135 bp->pf.vf_info[vf].random_mac = false;
2140 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2144 struct hwrm_func_qstats_input req = {.req_type = 0};
2145 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2147 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2149 req.fid = rte_cpu_to_le_16(fid);
2151 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2153 HWRM_CHECK_RESULT();
2156 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2163 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2164 struct rte_eth_stats *stats)
2167 struct hwrm_func_qstats_input req = {.req_type = 0};
2168 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2170 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2172 req.fid = rte_cpu_to_le_16(fid);
2174 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2176 HWRM_CHECK_RESULT();
2178 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2179 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2180 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2181 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2182 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2183 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2185 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2186 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2187 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2188 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2189 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2190 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2192 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2193 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2194 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2201 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2204 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2205 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2207 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2209 req.fid = rte_cpu_to_le_16(fid);
2211 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2213 HWRM_CHECK_RESULT();
2219 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2224 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2225 struct bnxt_tx_queue *txq;
2226 struct bnxt_rx_queue *rxq;
2227 struct bnxt_cp_ring_info *cpr;
2229 if (i >= bp->rx_cp_nr_rings) {
2230 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2233 rxq = bp->rx_queues[i];
2237 rc = bnxt_hwrm_stat_clear(bp, cpr);
2244 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2248 struct bnxt_cp_ring_info *cpr;
2250 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2252 if (i >= bp->rx_cp_nr_rings) {
2253 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2255 cpr = bp->rx_queues[i]->cp_ring;
2256 if (BNXT_HAS_RING_GRPS(bp))
2257 bp->grp_info[i].fw_stats_ctx = -1;
2259 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2260 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2261 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2269 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2274 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2275 struct bnxt_tx_queue *txq;
2276 struct bnxt_rx_queue *rxq;
2277 struct bnxt_cp_ring_info *cpr;
2279 if (i >= bp->rx_cp_nr_rings) {
2280 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2283 rxq = bp->rx_queues[i];
2287 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2295 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2300 if (!BNXT_HAS_RING_GRPS(bp))
2303 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2305 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2308 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2316 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2318 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2320 bnxt_hwrm_ring_free(bp, cp_ring,
2321 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2322 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2323 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2324 sizeof(*cpr->cp_desc_ring));
2325 cpr->cp_raw_cons = 0;
2329 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2331 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2333 bnxt_hwrm_ring_free(bp, cp_ring,
2334 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2335 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2336 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2337 sizeof(*cpr->cp_desc_ring));
2338 cpr->cp_raw_cons = 0;
2342 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2344 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2345 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2346 struct bnxt_ring *ring = rxr->rx_ring_struct;
2347 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2349 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2350 bnxt_hwrm_ring_free(bp, ring,
2351 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2352 ring->fw_ring_id = INVALID_HW_RING_ID;
2353 if (BNXT_HAS_RING_GRPS(bp))
2354 bp->grp_info[queue_index].rx_fw_ring_id =
2356 memset(rxr->rx_desc_ring, 0,
2357 rxr->rx_ring_struct->ring_size *
2358 sizeof(*rxr->rx_desc_ring));
2359 memset(rxr->rx_buf_ring, 0,
2360 rxr->rx_ring_struct->ring_size *
2361 sizeof(*rxr->rx_buf_ring));
2364 ring = rxr->ag_ring_struct;
2365 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2366 bnxt_hwrm_ring_free(bp, ring,
2367 BNXT_CHIP_THOR(bp) ?
2368 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2369 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2370 ring->fw_ring_id = INVALID_HW_RING_ID;
2371 memset(rxr->ag_buf_ring, 0,
2372 rxr->ag_ring_struct->ring_size *
2373 sizeof(*rxr->ag_buf_ring));
2375 if (BNXT_HAS_RING_GRPS(bp))
2376 bp->grp_info[queue_index].ag_fw_ring_id =
2379 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2380 bnxt_free_cp_ring(bp, cpr);
2382 if (BNXT_HAS_RING_GRPS(bp))
2383 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2386 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2390 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2391 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2392 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2393 struct bnxt_ring *ring = txr->tx_ring_struct;
2394 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2396 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2397 bnxt_hwrm_ring_free(bp, ring,
2398 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2399 ring->fw_ring_id = INVALID_HW_RING_ID;
2400 memset(txr->tx_desc_ring, 0,
2401 txr->tx_ring_struct->ring_size *
2402 sizeof(*txr->tx_desc_ring));
2403 memset(txr->tx_buf_ring, 0,
2404 txr->tx_ring_struct->ring_size *
2405 sizeof(*txr->tx_buf_ring));
2409 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2410 bnxt_free_cp_ring(bp, cpr);
2411 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2415 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2416 bnxt_free_hwrm_rx_ring(bp, i);
2421 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2426 if (!BNXT_HAS_RING_GRPS(bp))
2429 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2430 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2438 * HWRM utility functions
2441 void bnxt_free_hwrm_resources(struct bnxt *bp)
2443 /* Release memzone */
2444 rte_free(bp->hwrm_cmd_resp_addr);
2445 rte_free(bp->hwrm_short_cmd_req_addr);
2446 bp->hwrm_cmd_resp_addr = NULL;
2447 bp->hwrm_short_cmd_req_addr = NULL;
2448 bp->hwrm_cmd_resp_dma_addr = 0;
2449 bp->hwrm_short_cmd_req_dma_addr = 0;
2452 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2454 struct rte_pci_device *pdev = bp->pdev;
2455 char type[RTE_MEMZONE_NAMESIZE];
2457 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2458 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2459 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2460 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2461 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2462 if (bp->hwrm_cmd_resp_addr == NULL)
2464 bp->hwrm_cmd_resp_dma_addr =
2465 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2466 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2468 "unable to map response address to physical memory\n");
2471 rte_spinlock_init(&bp->hwrm_lock);
2476 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2478 struct bnxt_filter_info *filter;
2481 STAILQ_FOREACH(filter, &vnic->filter, next) {
2482 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2483 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2484 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2485 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2487 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2488 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2489 bnxt_free_filter(bp, filter);
2495 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2497 struct bnxt_filter_info *filter;
2498 struct rte_flow *flow;
2501 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2502 flow = STAILQ_FIRST(&vnic->flow_list);
2503 filter = flow->filter;
2504 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2505 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2506 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2507 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2508 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2510 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2512 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2518 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2520 struct bnxt_filter_info *filter;
2523 STAILQ_FOREACH(filter, &vnic->filter, next) {
2524 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2525 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2527 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2528 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2531 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2539 void bnxt_free_tunnel_ports(struct bnxt *bp)
2541 if (bp->vxlan_port_cnt)
2542 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2543 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2545 if (bp->geneve_port_cnt)
2546 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2547 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2548 bp->geneve_port = 0;
2551 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2555 if (bp->vnic_info == NULL)
2559 * Cleanup VNICs in reverse order, to make sure the L2 filter
2560 * from vnic0 is last to be cleaned up.
2562 for (i = bp->max_vnics - 1; i >= 0; i--) {
2563 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2565 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2568 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2570 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2572 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2574 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2576 bnxt_hwrm_vnic_free(bp, vnic);
2578 rte_free(vnic->fw_grp_ids);
2580 /* Ring resources */
2581 bnxt_free_all_hwrm_rings(bp);
2582 bnxt_free_all_hwrm_ring_grps(bp);
2583 bnxt_free_all_hwrm_stat_ctxs(bp);
2584 bnxt_free_tunnel_ports(bp);
2587 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2589 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2591 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2592 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2594 switch (conf_link_speed) {
2595 case ETH_LINK_SPEED_10M_HD:
2596 case ETH_LINK_SPEED_100M_HD:
2598 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2600 return hw_link_duplex;
2603 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2605 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2608 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2610 uint16_t eth_link_speed = 0;
2612 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2613 return ETH_LINK_SPEED_AUTONEG;
2615 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2616 case ETH_LINK_SPEED_100M:
2617 case ETH_LINK_SPEED_100M_HD:
2620 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2622 case ETH_LINK_SPEED_1G:
2624 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2626 case ETH_LINK_SPEED_2_5G:
2628 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2630 case ETH_LINK_SPEED_10G:
2632 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2634 case ETH_LINK_SPEED_20G:
2636 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2638 case ETH_LINK_SPEED_25G:
2640 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2642 case ETH_LINK_SPEED_40G:
2644 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2646 case ETH_LINK_SPEED_50G:
2648 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2650 case ETH_LINK_SPEED_100G:
2652 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2656 "Unsupported link speed %d; default to AUTO\n",
2660 return eth_link_speed;
2663 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2664 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2665 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2666 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2668 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2672 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2675 if (link_speed & ETH_LINK_SPEED_FIXED) {
2676 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2678 if (one_speed & (one_speed - 1)) {
2680 "Invalid advertised speeds (%u) for port %u\n",
2681 link_speed, port_id);
2684 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2686 "Unsupported advertised speed (%u) for port %u\n",
2687 link_speed, port_id);
2691 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2693 "Unsupported advertised speeds (%u) for port %u\n",
2694 link_speed, port_id);
2702 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2706 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2707 if (bp->link_info.support_speeds)
2708 return bp->link_info.support_speeds;
2709 link_speed = BNXT_SUPPORTED_SPEEDS;
2712 if (link_speed & ETH_LINK_SPEED_100M)
2713 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2714 if (link_speed & ETH_LINK_SPEED_100M_HD)
2715 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2716 if (link_speed & ETH_LINK_SPEED_1G)
2717 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2718 if (link_speed & ETH_LINK_SPEED_2_5G)
2719 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2720 if (link_speed & ETH_LINK_SPEED_10G)
2721 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2722 if (link_speed & ETH_LINK_SPEED_20G)
2723 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2724 if (link_speed & ETH_LINK_SPEED_25G)
2725 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2726 if (link_speed & ETH_LINK_SPEED_40G)
2727 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2728 if (link_speed & ETH_LINK_SPEED_50G)
2729 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2730 if (link_speed & ETH_LINK_SPEED_100G)
2731 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2735 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2737 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2739 switch (hw_link_speed) {
2740 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2741 eth_link_speed = ETH_SPEED_NUM_100M;
2743 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2744 eth_link_speed = ETH_SPEED_NUM_1G;
2746 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2747 eth_link_speed = ETH_SPEED_NUM_2_5G;
2749 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2750 eth_link_speed = ETH_SPEED_NUM_10G;
2752 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2753 eth_link_speed = ETH_SPEED_NUM_20G;
2755 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2756 eth_link_speed = ETH_SPEED_NUM_25G;
2758 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2759 eth_link_speed = ETH_SPEED_NUM_40G;
2761 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2762 eth_link_speed = ETH_SPEED_NUM_50G;
2764 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2765 eth_link_speed = ETH_SPEED_NUM_100G;
2767 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2769 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2773 return eth_link_speed;
2776 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2778 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2780 switch (hw_link_duplex) {
2781 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2782 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2784 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2786 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2787 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2790 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2794 return eth_link_duplex;
2797 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2800 struct bnxt_link_info *link_info = &bp->link_info;
2802 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2805 "Get link config failed with rc %d\n", rc);
2808 if (link_info->link_speed)
2810 bnxt_parse_hw_link_speed(link_info->link_speed);
2812 link->link_speed = ETH_SPEED_NUM_NONE;
2813 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2814 link->link_status = link_info->link_up;
2815 link->link_autoneg = link_info->auto_mode ==
2816 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2817 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2822 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2825 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2826 struct bnxt_link_info link_req;
2827 uint16_t speed, autoneg;
2829 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2832 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2833 bp->eth_dev->data->port_id);
2837 memset(&link_req, 0, sizeof(link_req));
2838 link_req.link_up = link_up;
2842 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2843 if (BNXT_CHIP_THOR(bp) &&
2844 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2845 /* 40G is not supported as part of media auto detect.
2846 * The speed should be forced and autoneg disabled
2847 * to configure 40G speed.
2849 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2853 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2854 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2855 /* Autoneg can be done only when the FW allows.
2856 * When user configures fixed speed of 40G and later changes to
2857 * any other speed, auto_link_speed/force_link_speed is still set
2858 * to 40G until link comes up at new speed.
2861 !(!BNXT_CHIP_THOR(bp) &&
2862 (bp->link_info.auto_link_speed ||
2863 bp->link_info.force_link_speed))) {
2864 link_req.phy_flags |=
2865 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2866 link_req.auto_link_speed_mask =
2867 bnxt_parse_eth_link_speed_mask(bp,
2868 dev_conf->link_speeds);
2870 if (bp->link_info.phy_type ==
2871 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2872 bp->link_info.phy_type ==
2873 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2874 bp->link_info.media_type ==
2875 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2876 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2880 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2881 /* If user wants a particular speed try that first. */
2883 link_req.link_speed = speed;
2884 else if (bp->link_info.force_link_speed)
2885 link_req.link_speed = bp->link_info.force_link_speed;
2887 link_req.link_speed = bp->link_info.auto_link_speed;
2889 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2890 link_req.auto_pause = bp->link_info.auto_pause;
2891 link_req.force_pause = bp->link_info.force_pause;
2894 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2897 "Set link config failed with rc %d\n", rc);
2905 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2907 struct hwrm_func_qcfg_input req = {0};
2908 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2912 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2913 req.fid = rte_cpu_to_le_16(0xffff);
2915 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2917 HWRM_CHECK_RESULT();
2919 /* Hard Coded.. 0xfff VLAN ID mask */
2920 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2921 flags = rte_le_to_cpu_16(resp->flags);
2922 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2923 bp->flags |= BNXT_FLAG_MULTI_HOST;
2926 !BNXT_VF_IS_TRUSTED(bp) &&
2927 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2928 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2929 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2930 } else if (BNXT_VF(bp) &&
2931 BNXT_VF_IS_TRUSTED(bp) &&
2932 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2933 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2934 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2938 *mtu = rte_le_to_cpu_16(resp->mtu);
2940 switch (resp->port_partition_type) {
2941 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2942 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2943 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2945 bp->port_partition_type = resp->port_partition_type;
2948 bp->port_partition_type = 0;
2957 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2958 struct hwrm_func_qcaps_output *qcaps)
2960 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2961 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2962 sizeof(qcaps->mac_address));
2963 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2964 qcaps->max_rx_rings = fcfg->num_rx_rings;
2965 qcaps->max_tx_rings = fcfg->num_tx_rings;
2966 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2967 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2969 qcaps->first_vf_id = 0;
2970 qcaps->max_vnics = fcfg->num_vnics;
2971 qcaps->max_decap_records = 0;
2972 qcaps->max_encap_records = 0;
2973 qcaps->max_tx_wm_flows = 0;
2974 qcaps->max_tx_em_flows = 0;
2975 qcaps->max_rx_wm_flows = 0;
2976 qcaps->max_rx_em_flows = 0;
2977 qcaps->max_flow_id = 0;
2978 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2979 qcaps->max_sp_tx_rings = 0;
2980 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2983 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2985 struct hwrm_func_cfg_input req = {0};
2986 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2990 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2991 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2992 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2993 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2994 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2995 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2996 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2997 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2998 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3000 if (BNXT_HAS_RING_GRPS(bp)) {
3001 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3002 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3003 } else if (BNXT_HAS_NQ(bp)) {
3004 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3005 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3008 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3009 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3010 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3011 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3012 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3013 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3014 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3015 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3016 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3017 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3018 req.fid = rte_cpu_to_le_16(0xffff);
3019 req.enables = rte_cpu_to_le_32(enables);
3021 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3023 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3025 HWRM_CHECK_RESULT();
3031 static void populate_vf_func_cfg_req(struct bnxt *bp,
3032 struct hwrm_func_cfg_input *req,
3035 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3036 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3037 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3038 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3039 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3040 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3041 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3042 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3043 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3044 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3046 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3047 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3049 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3050 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3052 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3053 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3055 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3056 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3057 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3058 /* TODO: For now, do not support VMDq/RFS on VFs. */
3059 req->num_vnics = rte_cpu_to_le_16(1);
3060 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3064 static void add_random_mac_if_needed(struct bnxt *bp,
3065 struct hwrm_func_cfg_input *cfg_req,
3068 struct rte_ether_addr mac;
3070 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3073 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3075 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3076 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3077 bp->pf.vf_info[vf].random_mac = true;
3079 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3080 RTE_ETHER_ADDR_LEN);
3084 static void reserve_resources_from_vf(struct bnxt *bp,
3085 struct hwrm_func_cfg_input *cfg_req,
3088 struct hwrm_func_qcaps_input req = {0};
3089 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3092 /* Get the actual allocated values now */
3093 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3094 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3095 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3098 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3099 copy_func_cfg_to_qcaps(cfg_req, resp);
3100 } else if (resp->error_code) {
3101 rc = rte_le_to_cpu_16(resp->error_code);
3102 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3103 copy_func_cfg_to_qcaps(cfg_req, resp);
3106 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3107 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3108 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3109 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3110 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3111 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3113 * TODO: While not supporting VMDq with VFs, max_vnics is always
3114 * forced to 1 in this case
3116 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3117 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3122 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3124 struct hwrm_func_qcfg_input req = {0};
3125 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3128 /* Check for zero MAC address */
3129 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3130 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3131 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3132 HWRM_CHECK_RESULT();
3133 rc = rte_le_to_cpu_16(resp->vlan);
3140 static int update_pf_resource_max(struct bnxt *bp)
3142 struct hwrm_func_qcfg_input req = {0};
3143 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3146 /* And copy the allocated numbers into the pf struct */
3147 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3148 req.fid = rte_cpu_to_le_16(0xffff);
3149 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3150 HWRM_CHECK_RESULT();
3152 /* Only TX ring value reflects actual allocation? TODO */
3153 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3154 bp->pf.evb_mode = resp->evb_mode;
3161 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3166 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3170 rc = bnxt_hwrm_func_qcaps(bp);
3174 bp->pf.func_cfg_flags &=
3175 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3176 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3177 bp->pf.func_cfg_flags |=
3178 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3179 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3180 rc = __bnxt_hwrm_func_qcaps(bp);
3184 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3186 struct hwrm_func_cfg_input req = {0};
3187 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3194 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3198 rc = bnxt_hwrm_func_qcaps(bp);
3203 bp->pf.active_vfs = num_vfs;
3206 * First, configure the PF to only use one TX ring. This ensures that
3207 * there are enough rings for all VFs.
3209 * If we don't do this, when we call func_alloc() later, we will lock
3210 * extra rings to the PF that won't be available during func_cfg() of
3213 * This has been fixed with firmware versions above 20.6.54
3215 bp->pf.func_cfg_flags &=
3216 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3217 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3218 bp->pf.func_cfg_flags |=
3219 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3220 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3225 * Now, create and register a buffer to hold forwarded VF requests
3227 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3228 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3229 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3230 if (bp->pf.vf_req_buf == NULL) {
3234 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3235 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3236 for (i = 0; i < num_vfs; i++)
3237 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3238 (i * HWRM_MAX_REQ_LEN);
3240 rc = bnxt_hwrm_func_buf_rgtr(bp);
3244 populate_vf_func_cfg_req(bp, &req, num_vfs);
3246 bp->pf.active_vfs = 0;
3247 for (i = 0; i < num_vfs; i++) {
3248 add_random_mac_if_needed(bp, &req, i);
3250 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3251 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3252 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3253 rc = bnxt_hwrm_send_message(bp,
3258 /* Clear enable flag for next pass */
3259 req.enables &= ~rte_cpu_to_le_32(
3260 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3262 if (rc || resp->error_code) {
3264 "Failed to initizlie VF %d\n", i);
3266 "Not all VFs available. (%d, %d)\n",
3267 rc, resp->error_code);
3274 reserve_resources_from_vf(bp, &req, i);
3275 bp->pf.active_vfs++;
3276 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3280 * Now configure the PF to use "the rest" of the resources
3281 * We're using STD_TX_RING_MODE here though which will limit the TX
3282 * rings. This will allow QoS to function properly. Not setting this
3283 * will cause PF rings to break bandwidth settings.
3285 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3289 rc = update_pf_resource_max(bp);
3296 bnxt_hwrm_func_buf_unrgtr(bp);
3300 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3302 struct hwrm_func_cfg_input req = {0};
3303 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3306 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3308 req.fid = rte_cpu_to_le_16(0xffff);
3309 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3310 req.evb_mode = bp->pf.evb_mode;
3312 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3313 HWRM_CHECK_RESULT();
3319 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3320 uint8_t tunnel_type)
3322 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3323 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3326 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3327 req.tunnel_type = tunnel_type;
3328 req.tunnel_dst_port_val = port;
3329 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3330 HWRM_CHECK_RESULT();
3332 switch (tunnel_type) {
3333 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3334 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3335 bp->vxlan_port = port;
3337 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3338 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3339 bp->geneve_port = port;
3350 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3351 uint8_t tunnel_type)
3353 struct hwrm_tunnel_dst_port_free_input req = {0};
3354 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3357 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3359 req.tunnel_type = tunnel_type;
3360 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3361 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3363 HWRM_CHECK_RESULT();
3369 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3372 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3373 struct hwrm_func_cfg_input req = {0};
3376 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3378 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3379 req.flags = rte_cpu_to_le_32(flags);
3380 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3382 HWRM_CHECK_RESULT();
3388 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3390 uint32_t *flag = flagp;
3392 vnic->flags = *flag;
3395 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3397 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3400 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3403 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3404 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3406 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3408 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3409 req.req_buf_page_size = rte_cpu_to_le_16(
3410 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3411 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3412 req.req_buf_page_addr0 =
3413 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3414 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3416 "unable to map buffer address to physical memory\n");
3420 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3422 HWRM_CHECK_RESULT();
3428 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3431 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3432 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3434 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3437 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3439 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3441 HWRM_CHECK_RESULT();
3447 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3449 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3450 struct hwrm_func_cfg_input req = {0};
3453 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3455 req.fid = rte_cpu_to_le_16(0xffff);
3456 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3457 req.enables = rte_cpu_to_le_32(
3458 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3459 req.async_event_cr = rte_cpu_to_le_16(
3460 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3461 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3463 HWRM_CHECK_RESULT();
3469 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3471 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3472 struct hwrm_func_vf_cfg_input req = {0};
3475 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3477 req.enables = rte_cpu_to_le_32(
3478 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3479 req.async_event_cr = rte_cpu_to_le_16(
3480 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3481 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3483 HWRM_CHECK_RESULT();
3489 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3491 struct hwrm_func_cfg_input req = {0};
3492 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3493 uint16_t dflt_vlan, fid;
3494 uint32_t func_cfg_flags;
3497 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3500 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3501 fid = bp->pf.vf_info[vf].fid;
3502 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3504 fid = rte_cpu_to_le_16(0xffff);
3505 func_cfg_flags = bp->pf.func_cfg_flags;
3506 dflt_vlan = bp->vlan;
3509 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3510 req.fid = rte_cpu_to_le_16(fid);
3511 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3512 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3514 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3516 HWRM_CHECK_RESULT();
3522 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3523 uint16_t max_bw, uint16_t enables)
3525 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3526 struct hwrm_func_cfg_input req = {0};
3529 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3531 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3532 req.enables |= rte_cpu_to_le_32(enables);
3533 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3534 req.max_bw = rte_cpu_to_le_32(max_bw);
3535 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3537 HWRM_CHECK_RESULT();
3543 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3545 struct hwrm_func_cfg_input req = {0};
3546 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3549 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3551 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3552 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3553 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3554 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3556 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3558 HWRM_CHECK_RESULT();
3564 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3569 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3571 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3576 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3577 void *encaped, size_t ec_size)
3580 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3581 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3583 if (ec_size > sizeof(req.encap_request))
3586 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3588 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3589 memcpy(req.encap_request, encaped, ec_size);
3591 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3593 HWRM_CHECK_RESULT();
3599 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3600 struct rte_ether_addr *mac)
3602 struct hwrm_func_qcfg_input req = {0};
3603 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3606 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3608 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3609 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3611 HWRM_CHECK_RESULT();
3613 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3620 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3621 void *encaped, size_t ec_size)
3624 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3625 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3627 if (ec_size > sizeof(req.encap_request))
3630 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3632 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3633 memcpy(req.encap_request, encaped, ec_size);
3635 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3637 HWRM_CHECK_RESULT();
3643 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3644 struct rte_eth_stats *stats, uint8_t rx)
3647 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3648 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3650 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3652 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3654 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3656 HWRM_CHECK_RESULT();
3659 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3660 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3661 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3662 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3663 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3664 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3665 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3666 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3668 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3669 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3670 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3671 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3672 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3673 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3681 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3683 struct hwrm_port_qstats_input req = {0};
3684 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3685 struct bnxt_pf_info *pf = &bp->pf;
3688 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3690 req.port_id = rte_cpu_to_le_16(pf->port_id);
3691 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3692 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3693 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3695 HWRM_CHECK_RESULT();
3701 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3703 struct hwrm_port_clr_stats_input req = {0};
3704 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3705 struct bnxt_pf_info *pf = &bp->pf;
3708 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3709 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3710 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3713 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3715 req.port_id = rte_cpu_to_le_16(pf->port_id);
3716 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3718 HWRM_CHECK_RESULT();
3724 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3726 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3727 struct hwrm_port_led_qcaps_input req = {0};
3733 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3734 req.port_id = bp->pf.port_id;
3735 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3737 HWRM_CHECK_RESULT();
3739 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3742 bp->num_leds = resp->num_leds;
3743 memcpy(bp->leds, &resp->led0_id,
3744 sizeof(bp->leds[0]) * bp->num_leds);
3745 for (i = 0; i < bp->num_leds; i++) {
3746 struct bnxt_led_info *led = &bp->leds[i];
3748 uint16_t caps = led->led_state_caps;
3750 if (!led->led_group_id ||
3751 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3763 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3765 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3766 struct hwrm_port_led_cfg_input req = {0};
3767 struct bnxt_led_cfg *led_cfg;
3768 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3769 uint16_t duration = 0;
3772 if (!bp->num_leds || BNXT_VF(bp))
3775 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3778 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3779 duration = rte_cpu_to_le_16(500);
3781 req.port_id = bp->pf.port_id;
3782 req.num_leds = bp->num_leds;
3783 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3784 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3785 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3786 led_cfg->led_id = bp->leds[i].led_id;
3787 led_cfg->led_state = led_state;
3788 led_cfg->led_blink_on = duration;
3789 led_cfg->led_blink_off = duration;
3790 led_cfg->led_group_id = bp->leds[i].led_group_id;
3793 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3795 HWRM_CHECK_RESULT();
3801 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3805 struct hwrm_nvm_get_dir_info_input req = {0};
3806 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3808 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3810 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3812 HWRM_CHECK_RESULT();
3814 *entries = rte_le_to_cpu_32(resp->entries);
3815 *length = rte_le_to_cpu_32(resp->entry_length);
3821 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3824 uint32_t dir_entries;
3825 uint32_t entry_length;
3828 rte_iova_t dma_handle;
3829 struct hwrm_nvm_get_dir_entries_input req = {0};
3830 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3832 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3836 *data++ = dir_entries;
3837 *data++ = entry_length;
3839 memset(data, 0xff, len);
3841 buflen = dir_entries * entry_length;
3842 buf = rte_malloc("nvm_dir", buflen, 0);
3843 rte_mem_lock_page(buf);
3846 dma_handle = rte_mem_virt2iova(buf);
3847 if (dma_handle == RTE_BAD_IOVA) {
3849 "unable to map response address to physical memory\n");
3852 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3853 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3854 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3857 memcpy(data, buf, len > buflen ? buflen : len);
3860 HWRM_CHECK_RESULT();
3866 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3867 uint32_t offset, uint32_t length,
3872 rte_iova_t dma_handle;
3873 struct hwrm_nvm_read_input req = {0};
3874 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3876 buf = rte_malloc("nvm_item", length, 0);
3877 rte_mem_lock_page(buf);
3881 dma_handle = rte_mem_virt2iova(buf);
3882 if (dma_handle == RTE_BAD_IOVA) {
3884 "unable to map response address to physical memory\n");
3887 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3888 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3889 req.dir_idx = rte_cpu_to_le_16(index);
3890 req.offset = rte_cpu_to_le_32(offset);
3891 req.len = rte_cpu_to_le_32(length);
3892 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3894 memcpy(data, buf, length);
3897 HWRM_CHECK_RESULT();
3903 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3906 struct hwrm_nvm_erase_dir_entry_input req = {0};
3907 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3909 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3910 req.dir_idx = rte_cpu_to_le_16(index);
3911 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3912 HWRM_CHECK_RESULT();
3919 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3920 uint16_t dir_ordinal, uint16_t dir_ext,
3921 uint16_t dir_attr, const uint8_t *data,
3925 struct hwrm_nvm_write_input req = {0};
3926 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3927 rte_iova_t dma_handle;
3930 buf = rte_malloc("nvm_write", data_len, 0);
3931 rte_mem_lock_page(buf);
3935 dma_handle = rte_mem_virt2iova(buf);
3936 if (dma_handle == RTE_BAD_IOVA) {
3938 "unable to map response address to physical memory\n");
3941 memcpy(buf, data, data_len);
3943 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3945 req.dir_type = rte_cpu_to_le_16(dir_type);
3946 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3947 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3948 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3949 req.dir_data_length = rte_cpu_to_le_32(data_len);
3950 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3952 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3955 HWRM_CHECK_RESULT();
3962 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3964 uint32_t *count = cbdata;
3966 *count = *count + 1;
3969 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3970 struct bnxt_vnic_info *vnic __rte_unused)
3975 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3979 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3980 &count, bnxt_vnic_count_hwrm_stub);
3985 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3988 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3989 struct hwrm_func_vf_vnic_ids_query_output *resp =
3990 bp->hwrm_cmd_resp_addr;
3993 /* First query all VNIC ids */
3994 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3996 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3997 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3998 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
4000 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4003 "unable to map VNIC ID table address to physical memory\n");
4006 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4007 HWRM_CHECK_RESULT();
4008 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4016 * This function queries the VNIC IDs for a specified VF. It then calls
4017 * the vnic_cb to update the necessary field in vnic_info with cbdata.
4018 * Then it calls the hwrm_cb function to program this new vnic configuration.
4020 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4021 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4022 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4024 struct bnxt_vnic_info vnic;
4026 int i, num_vnic_ids;
4031 /* First query all VNIC ids */
4032 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4033 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4034 RTE_CACHE_LINE_SIZE);
4035 if (vnic_ids == NULL)
4038 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4039 rte_mem_lock_page(((char *)vnic_ids) + sz);
4041 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4043 if (num_vnic_ids < 0)
4044 return num_vnic_ids;
4046 /* Retrieve VNIC, update bd_stall then update */
4048 for (i = 0; i < num_vnic_ids; i++) {
4049 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4050 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4051 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4054 if (vnic.mru <= 4) /* Indicates unallocated */
4057 vnic_cb(&vnic, cbdata);
4059 rc = hwrm_cb(bp, &vnic);
4069 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4072 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4073 struct hwrm_func_cfg_input req = {0};
4076 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4078 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4079 req.enables |= rte_cpu_to_le_32(
4080 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4081 req.vlan_antispoof_mode = on ?
4082 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4083 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4084 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4086 HWRM_CHECK_RESULT();
4092 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4094 struct bnxt_vnic_info vnic;
4097 int num_vnic_ids, i;
4101 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4102 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4103 RTE_CACHE_LINE_SIZE);
4104 if (vnic_ids == NULL)
4107 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4108 rte_mem_lock_page(((char *)vnic_ids) + sz);
4110 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4116 * Loop through to find the default VNIC ID.
4117 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4118 * by sending the hwrm_func_qcfg command to the firmware.
4120 for (i = 0; i < num_vnic_ids; i++) {
4121 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4122 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4123 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4124 bp->pf.first_vf_id + vf);
4127 if (vnic.func_default) {
4129 return vnic.fw_vnic_id;
4132 /* Could not find a default VNIC. */
4133 PMD_DRV_LOG(ERR, "No default VNIC\n");
4139 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4141 struct bnxt_filter_info *filter)
4144 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4145 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4146 uint32_t enables = 0;
4148 if (filter->fw_em_filter_id != UINT64_MAX)
4149 bnxt_hwrm_clear_em_filter(bp, filter);
4151 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4153 req.flags = rte_cpu_to_le_32(filter->flags);
4155 enables = filter->enables |
4156 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4157 req.dst_id = rte_cpu_to_le_16(dst_id);
4159 if (filter->ip_addr_type) {
4160 req.ip_addr_type = filter->ip_addr_type;
4161 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4164 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4165 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4167 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4168 memcpy(req.src_macaddr, filter->src_macaddr,
4169 RTE_ETHER_ADDR_LEN);
4171 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4172 memcpy(req.dst_macaddr, filter->dst_macaddr,
4173 RTE_ETHER_ADDR_LEN);
4175 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4176 req.ovlan_vid = filter->l2_ovlan;
4178 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4179 req.ivlan_vid = filter->l2_ivlan;
4181 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4182 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4184 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4185 req.ip_protocol = filter->ip_protocol;
4187 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4188 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4190 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4191 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4193 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4194 req.src_port = rte_cpu_to_be_16(filter->src_port);
4196 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4197 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4199 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4200 req.mirror_vnic_id = filter->mirror_vnic_id;
4202 req.enables = rte_cpu_to_le_32(enables);
4204 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4206 HWRM_CHECK_RESULT();
4208 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4214 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4217 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4218 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4220 if (filter->fw_em_filter_id == UINT64_MAX)
4223 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4225 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4227 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4229 HWRM_CHECK_RESULT();
4232 filter->fw_em_filter_id = UINT64_MAX;
4233 filter->fw_l2_filter_id = UINT64_MAX;
4238 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4240 struct bnxt_filter_info *filter)
4243 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4244 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4245 bp->hwrm_cmd_resp_addr;
4246 uint32_t enables = 0;
4248 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4249 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4251 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4253 req.flags = rte_cpu_to_le_32(filter->flags);
4255 enables = filter->enables |
4256 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4257 req.dst_id = rte_cpu_to_le_16(dst_id);
4259 if (filter->ip_addr_type) {
4260 req.ip_addr_type = filter->ip_addr_type;
4262 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4265 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4266 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4268 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4269 memcpy(req.src_macaddr, filter->src_macaddr,
4270 RTE_ETHER_ADDR_LEN);
4272 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4273 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4275 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4276 req.ip_protocol = filter->ip_protocol;
4278 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4279 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4281 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4282 req.src_ipaddr_mask[0] =
4283 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4285 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4286 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4288 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4289 req.dst_ipaddr_mask[0] =
4290 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4292 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4293 req.src_port = rte_cpu_to_le_16(filter->src_port);
4295 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4296 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4298 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4299 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4301 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4302 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4304 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4305 req.mirror_vnic_id = filter->mirror_vnic_id;
4307 req.enables = rte_cpu_to_le_32(enables);
4309 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4311 HWRM_CHECK_RESULT();
4313 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4319 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4320 struct bnxt_filter_info *filter)
4323 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4324 struct hwrm_cfa_ntuple_filter_free_output *resp =
4325 bp->hwrm_cmd_resp_addr;
4327 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4330 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4332 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4334 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4336 HWRM_CHECK_RESULT();
4339 filter->fw_ntuple_filter_id = UINT64_MAX;
4345 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4347 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4348 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4349 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4350 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4351 uint16_t *ring_tbl = vnic->rss_table;
4352 int nr_ctxs = vnic->num_lb_ctxts;
4353 int max_rings = bp->rx_nr_rings;
4357 for (i = 0, k = 0; i < nr_ctxs; i++) {
4358 struct bnxt_rx_ring_info *rxr;
4359 struct bnxt_cp_ring_info *cpr;
4361 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4363 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4364 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4365 req.hash_mode_flags = vnic->hash_mode;
4367 req.ring_grp_tbl_addr =
4368 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4369 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4370 2 * sizeof(*ring_tbl));
4371 req.hash_key_tbl_addr =
4372 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4374 req.ring_table_pair_index = i;
4375 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4377 for (j = 0; j < 64; j++) {
4380 /* Find next active ring. */
4381 for (cnt = 0; cnt < max_rings; cnt++) {
4382 if (rx_queue_state[k] !=
4383 RTE_ETH_QUEUE_STATE_STOPPED)
4385 if (++k == max_rings)
4389 /* Return if no rings are active. */
4390 if (cnt == max_rings) {
4395 /* Add rx/cp ring pair to RSS table. */
4396 rxr = rxqs[k]->rx_ring;
4397 cpr = rxqs[k]->cp_ring;
4399 ring_id = rxr->rx_ring_struct->fw_ring_id;
4400 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4401 ring_id = cpr->cp_ring_struct->fw_ring_id;
4402 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4404 if (++k == max_rings)
4407 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4410 HWRM_CHECK_RESULT();
4417 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4419 unsigned int rss_idx, fw_idx, i;
4421 if (!(vnic->rss_table && vnic->hash_type))
4424 if (BNXT_CHIP_THOR(bp))
4425 return bnxt_vnic_rss_configure_thor(bp, vnic);
4427 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4430 if (vnic->rss_table && vnic->hash_type) {
4432 * Fill the RSS hash & redirection table with
4433 * ring group ids for all VNICs
4435 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4436 rss_idx++, fw_idx++) {
4437 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4438 fw_idx %= bp->rx_cp_nr_rings;
4439 if (vnic->fw_grp_ids[fw_idx] !=
4444 if (i == bp->rx_cp_nr_rings)
4446 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4448 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4454 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4455 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4459 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4461 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4462 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4464 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4465 req->num_cmpl_dma_aggr_during_int =
4466 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4468 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4470 /* min timer set to 1/2 of interrupt timer */
4471 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4473 /* buf timer set to 1/4 of interrupt timer */
4474 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4476 req->cmpl_aggr_dma_tmr_during_int =
4477 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4479 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4480 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4481 req->flags = rte_cpu_to_le_16(flags);
4484 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4485 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4487 struct hwrm_ring_aggint_qcaps_input req = {0};
4488 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4493 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4494 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4495 HWRM_CHECK_RESULT();
4497 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4498 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4500 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4501 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4502 agg_req->flags = rte_cpu_to_le_16(flags);
4504 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4505 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4506 agg_req->enables = rte_cpu_to_le_32(enables);
4512 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4513 struct bnxt_coal *coal, uint16_t ring_id)
4515 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4516 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4517 bp->hwrm_cmd_resp_addr;
4520 /* Set ring coalesce parameters only for 100G NICs */
4521 if (BNXT_CHIP_THOR(bp)) {
4522 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4524 } else if (bnxt_stratus_device(bp)) {
4525 bnxt_hwrm_set_coal_params(coal, &req);
4530 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4531 req.ring_id = rte_cpu_to_le_16(ring_id);
4532 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4533 HWRM_CHECK_RESULT();
4538 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4539 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4541 struct hwrm_func_backing_store_qcaps_input req = {0};
4542 struct hwrm_func_backing_store_qcaps_output *resp =
4543 bp->hwrm_cmd_resp_addr;
4544 struct bnxt_ctx_pg_info *ctx_pg;
4545 struct bnxt_ctx_mem_info *ctx;
4546 int total_alloc_len;
4549 if (!BNXT_CHIP_THOR(bp) ||
4550 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4555 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4556 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4557 HWRM_CHECK_RESULT_SILENT();
4559 total_alloc_len = sizeof(*ctx);
4560 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4561 RTE_CACHE_LINE_SIZE);
4567 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4568 sizeof(*ctx_pg) * BNXT_MAX_Q,
4569 RTE_CACHE_LINE_SIZE);
4574 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4575 ctx->tqm_mem[i] = ctx_pg;
4578 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4579 ctx->qp_min_qp1_entries =
4580 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4581 ctx->qp_max_l2_entries =
4582 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4583 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4584 ctx->srq_max_l2_entries =
4585 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4586 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4587 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4588 ctx->cq_max_l2_entries =
4589 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4590 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4591 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4592 ctx->vnic_max_vnic_entries =
4593 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4594 ctx->vnic_max_ring_table_entries =
4595 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4596 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4597 ctx->stat_max_entries =
4598 rte_le_to_cpu_32(resp->stat_max_entries);
4599 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4600 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4601 ctx->tqm_min_entries_per_ring =
4602 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4603 ctx->tqm_max_entries_per_ring =
4604 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4605 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4606 if (!ctx->tqm_entries_multiple)
4607 ctx->tqm_entries_multiple = 1;
4608 ctx->mrav_max_entries =
4609 rte_le_to_cpu_32(resp->mrav_max_entries);
4610 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4611 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4612 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4618 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4620 struct hwrm_func_backing_store_cfg_input req = {0};
4621 struct hwrm_func_backing_store_cfg_output *resp =
4622 bp->hwrm_cmd_resp_addr;
4623 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4624 struct bnxt_ctx_pg_info *ctx_pg;
4625 uint32_t *num_entries;
4634 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4635 req.enables = rte_cpu_to_le_32(enables);
4637 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4638 ctx_pg = &ctx->qp_mem;
4639 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4640 req.qp_num_qp1_entries =
4641 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4642 req.qp_num_l2_entries =
4643 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4644 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4645 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4646 &req.qpc_pg_size_qpc_lvl,
4650 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4651 ctx_pg = &ctx->srq_mem;
4652 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4653 req.srq_num_l2_entries =
4654 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4655 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4656 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4657 &req.srq_pg_size_srq_lvl,
4661 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4662 ctx_pg = &ctx->cq_mem;
4663 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4664 req.cq_num_l2_entries =
4665 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4666 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4667 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4668 &req.cq_pg_size_cq_lvl,
4672 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4673 ctx_pg = &ctx->vnic_mem;
4674 req.vnic_num_vnic_entries =
4675 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4676 req.vnic_num_ring_table_entries =
4677 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4678 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4679 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4680 &req.vnic_pg_size_vnic_lvl,
4681 &req.vnic_page_dir);
4684 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4685 ctx_pg = &ctx->stat_mem;
4686 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4687 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4688 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4689 &req.stat_pg_size_stat_lvl,
4690 &req.stat_page_dir);
4693 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4694 num_entries = &req.tqm_sp_num_entries;
4695 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4696 pg_dir = &req.tqm_sp_page_dir;
4697 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4698 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4699 if (!(enables & ena))
4702 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4704 ctx_pg = ctx->tqm_mem[i];
4705 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4706 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4709 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4710 HWRM_CHECK_RESULT();
4716 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4718 struct hwrm_port_qstats_ext_input req = {0};
4719 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4720 struct bnxt_pf_info *pf = &bp->pf;
4723 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4724 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4727 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4729 req.port_id = rte_cpu_to_le_16(pf->port_id);
4730 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4731 req.tx_stat_host_addr =
4732 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4734 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4736 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4737 req.rx_stat_host_addr =
4738 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4740 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4742 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4745 bp->fw_rx_port_stats_ext_size = 0;
4746 bp->fw_tx_port_stats_ext_size = 0;
4748 bp->fw_rx_port_stats_ext_size =
4749 rte_le_to_cpu_16(resp->rx_stat_size);
4750 bp->fw_tx_port_stats_ext_size =
4751 rte_le_to_cpu_16(resp->tx_stat_size);
4754 HWRM_CHECK_RESULT();
4761 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4763 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4764 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4765 bp->hwrm_cmd_resp_addr;
4768 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4769 req.tunnel_type = type;
4770 req.dest_fid = bp->fw_fid;
4771 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4772 HWRM_CHECK_RESULT();
4780 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4782 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4783 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4784 bp->hwrm_cmd_resp_addr;
4787 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4788 req.tunnel_type = type;
4789 req.dest_fid = bp->fw_fid;
4790 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4791 HWRM_CHECK_RESULT();
4798 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4800 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4801 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4802 bp->hwrm_cmd_resp_addr;
4805 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4806 req.src_fid = bp->fw_fid;
4807 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4808 HWRM_CHECK_RESULT();
4811 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4818 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4821 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4822 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4823 bp->hwrm_cmd_resp_addr;
4826 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4827 req.src_fid = bp->fw_fid;
4828 req.tunnel_type = tun_type;
4829 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4830 HWRM_CHECK_RESULT();
4833 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4835 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4842 int bnxt_hwrm_set_mac(struct bnxt *bp)
4844 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4845 struct hwrm_func_vf_cfg_input req = {0};
4851 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4854 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4855 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4857 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4859 HWRM_CHECK_RESULT();
4861 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4867 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4869 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4870 struct hwrm_func_drv_if_change_input req = {0};
4874 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
4877 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4878 * If we issue FUNC_DRV_IF_CHANGE with flags down before
4879 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4881 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4884 HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4888 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4890 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4892 HWRM_CHECK_RESULT();
4893 flags = rte_le_to_cpu_32(resp->flags);
4899 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4900 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4901 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4907 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4909 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4910 struct bnxt_error_recovery_info *info = bp->recovery_info;
4911 struct hwrm_error_recovery_qcfg_input req = {0};
4916 /* Older FW does not have error recovery support */
4917 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4921 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4923 bp->recovery_info = info;
4927 memset(info, 0, sizeof(*info));
4930 HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4932 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4934 HWRM_CHECK_RESULT();
4936 flags = rte_le_to_cpu_32(resp->flags);
4937 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4938 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4939 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4940 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4942 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4943 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4948 /* FW returned values are in units of 100msec */
4949 info->driver_polling_freq =
4950 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4951 info->master_func_wait_period =
4952 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4953 info->normal_func_wait_period =
4954 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4955 info->master_func_wait_period_after_reset =
4956 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4957 info->max_bailout_time_after_reset =
4958 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4959 info->status_regs[BNXT_FW_STATUS_REG] =
4960 rte_le_to_cpu_32(resp->fw_health_status_reg);
4961 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4962 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4963 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4964 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4965 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4966 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4967 info->reg_array_cnt =
4968 rte_le_to_cpu_32(resp->reg_array_cnt);
4970 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4975 for (i = 0; i < info->reg_array_cnt; i++) {
4976 info->reset_reg[i] =
4977 rte_le_to_cpu_32(resp->reset_reg[i]);
4978 info->reset_reg_val[i] =
4979 rte_le_to_cpu_32(resp->reset_reg_val[i]);
4980 info->delay_after_reset[i] =
4981 resp->delay_after_reset[i];
4986 /* Map the FW status registers */
4988 rc = bnxt_map_fw_health_status_regs(bp);
4991 rte_free(bp->recovery_info);
4992 bp->recovery_info = NULL;
4997 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4999 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5000 struct hwrm_fw_reset_input req = {0};
5006 HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
5008 req.embedded_proc_type =
5009 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5010 req.selfrst_status =
5011 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5012 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5014 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5017 HWRM_CHECK_RESULT();
5023 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5025 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5026 struct hwrm_port_ts_query_input req = {0};
5027 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5034 HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5037 case BNXT_PTP_FLAGS_PATH_TX:
5038 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5040 case BNXT_PTP_FLAGS_PATH_RX:
5041 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5043 case BNXT_PTP_FLAGS_CURRENT_TIME:
5044 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5048 req.flags = rte_cpu_to_le_32(flags);
5049 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5051 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5053 HWRM_CHECK_RESULT();
5056 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5058 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5065 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5067 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5068 bp->hwrm_cmd_resp_addr;
5069 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5073 if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5076 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5078 "Not a PF or trusted VF. Command not supported\n");
5082 HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5083 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5085 HWRM_CHECK_RESULT();
5086 flags = rte_le_to_cpu_32(resp->flags);
5089 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5090 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5091 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");