1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(void *) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
67 if (rmem->nr_pages > 1) {
69 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
71 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
76 * HWRM Functions (sent to HWRM)
77 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
78 * HWRM command times out, or a negative error code if the HWRM
79 * command was failed by the FW.
82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
83 uint32_t msg_len, bool use_kong_mb)
86 struct input *req = msg;
87 struct output *resp = bp->hwrm_cmd_resp_addr;
91 uint16_t max_req_len = bp->max_req_len;
92 struct hwrm_short_input short_input = { 0 };
93 uint16_t bar_offset = use_kong_mb ?
94 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
95 uint16_t mb_trigger_offset = use_kong_mb ?
96 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
99 /* Do not send HWRM commands to firmware in error state */
100 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
103 timeout = bp->hwrm_cmd_timeout;
105 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
106 msg_len > bp->max_req_len) {
107 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
109 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
110 memcpy(short_cmd_req, req, msg_len);
112 short_input.req_type = rte_cpu_to_le_16(req->req_type);
113 short_input.signature = rte_cpu_to_le_16(
114 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
115 short_input.size = rte_cpu_to_le_16(msg_len);
116 short_input.req_addr =
117 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
119 data = (uint32_t *)&short_input;
120 msg_len = sizeof(short_input);
122 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
125 /* Write request msg to hwrm channel */
126 for (i = 0; i < msg_len; i += 4) {
127 bar = (uint8_t *)bp->bar0 + bar_offset + i;
128 rte_write32(*data, bar);
132 /* Zero the rest of the request space */
133 for (; i < max_req_len; i += 4) {
134 bar = (uint8_t *)bp->bar0 + bar_offset + i;
138 /* Ring channel doorbell */
139 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
142 * Make sure the channel doorbell ring command complete before
143 * reading the response to avoid getting stale or invalid
148 /* Poll for the valid bit */
149 for (i = 0; i < timeout; i++) {
150 /* Sanity check on the resp->resp_len */
152 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
153 /* Last byte of resp contains the valid key */
154 valid = (uint8_t *)resp + resp->resp_len - 1;
155 if (*valid == HWRM_RESP_VALID_KEY)
162 /* Suppress VER_GET timeout messages during reset recovery */
163 if (bp->flags & BNXT_FLAG_FW_RESET &&
164 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
168 "Error(timeout) sending msg 0x%04x, seq_id %d\n",
169 req->req_type, req->seq_id);
176 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
177 * spinlock, and does initial processing.
179 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
180 * releases the spinlock only if it returns. If the regular int return codes
181 * are not used by the function, HWRM_CHECK_RESULT() should not be used
182 * directly, rather it should be copied and modified to suit the function.
184 * HWRM_UNLOCK() must be called after all response processing is completed.
186 #define HWRM_PREP(req, type, kong) do { \
187 rte_spinlock_lock(&bp->hwrm_lock); \
188 if (bp->hwrm_cmd_resp_addr == NULL) { \
189 rte_spinlock_unlock(&bp->hwrm_lock); \
192 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
193 (req)->req_type = rte_cpu_to_le_16(type); \
194 (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
195 (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
196 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
197 (req)->target_id = rte_cpu_to_le_16(0xffff); \
198 (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
201 #define HWRM_CHECK_RESULT_SILENT() do {\
203 rte_spinlock_unlock(&bp->hwrm_lock); \
206 if (resp->error_code) { \
207 rc = rte_le_to_cpu_16(resp->error_code); \
208 rte_spinlock_unlock(&bp->hwrm_lock); \
213 #define HWRM_CHECK_RESULT() do {\
215 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
216 rte_spinlock_unlock(&bp->hwrm_lock); \
217 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
219 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
221 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
223 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
225 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
231 if (resp->error_code) { \
232 rc = rte_le_to_cpu_16(resp->error_code); \
233 if (resp->resp_len >= 16) { \
234 struct hwrm_err_output *tmp_hwrm_err_op = \
237 "error %d:%d:%08x:%04x\n", \
238 rc, tmp_hwrm_err_op->cmd_err, \
240 tmp_hwrm_err_op->opaque_0), \
242 tmp_hwrm_err_op->opaque_1)); \
244 PMD_DRV_LOG(ERR, "error %d\n", rc); \
246 rte_spinlock_unlock(&bp->hwrm_lock); \
247 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
249 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
251 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
253 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
255 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
263 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
265 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
274 bool mailbox = BNXT_USE_CHIMP_MB;
275 struct input *req = msg;
276 struct output *resp = bp->hwrm_cmd_resp_addr;
279 mailbox = BNXT_USE_KONG(bp);
281 HWRM_PREP(req, msg_type, mailbox);
283 rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
288 memcpy(resp_msg, resp, resp_len);
295 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
299 uint32_t *tf_response_code,
303 uint32_t response_len)
306 struct hwrm_cfa_tflib_input req = { .req_type = 0 };
307 struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
308 bool mailbox = BNXT_USE_CHIMP_MB;
310 if (msg_len > sizeof(req.tf_req))
314 mailbox = BNXT_USE_KONG(bp);
316 HWRM_PREP(&req, HWRM_TF, mailbox);
317 /* Build request using the user supplied request payload.
318 * TLV request size is checked at build time against HWRM
319 * request max size, thus no checking required.
321 req.tf_type = tf_type;
322 req.tf_subtype = tf_subtype;
323 memcpy(req.tf_req, msg, msg_len);
325 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
328 /* Copy the resp to user provided response buffer */
329 if (response != NULL)
330 /* Post process response data. We need to copy only
331 * the 'payload' as the HWRM data structure really is
332 * HWRM header + msg header + payload and the TFLIB
333 * only provided a payload place holder.
335 if (response_len != 0) {
341 /* Extract the internal tflib response code */
342 *tf_response_code = resp->tf_resp_code;
348 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
351 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
352 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
354 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
355 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
358 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
366 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
367 struct bnxt_vnic_info *vnic,
369 struct bnxt_vlan_table_entry *vlan_table)
372 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
373 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
376 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
379 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
380 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
382 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
383 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
384 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
385 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
387 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
388 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
390 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
391 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
392 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
393 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
394 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
395 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
398 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
399 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
400 req.vlan_tag_tbl_addr =
401 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
402 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
404 req.mask = rte_cpu_to_le_32(mask);
406 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
414 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
416 struct bnxt_vlan_antispoof_table_entry *vlan_table)
419 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
420 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
421 bp->hwrm_cmd_resp_addr;
424 * Older HWRM versions did not support this command, and the set_rx_mask
425 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
426 * removed from set_rx_mask call, and this command was added.
428 * This command is also present from 1.7.8.11 and higher,
431 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
432 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
433 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
438 HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
439 req.fid = rte_cpu_to_le_16(fid);
441 req.vlan_tag_mask_tbl_addr =
442 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
443 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
445 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
453 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
454 struct bnxt_filter_info *filter)
457 struct bnxt_filter_info *l2_filter = filter;
458 struct bnxt_vnic_info *vnic = NULL;
459 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
460 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
462 if (filter->fw_l2_filter_id == UINT64_MAX)
465 if (filter->matching_l2_fltr_ptr)
466 l2_filter = filter->matching_l2_fltr_ptr;
468 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
469 filter, l2_filter, l2_filter->l2_ref_cnt);
471 if (l2_filter->l2_ref_cnt == 0)
474 if (l2_filter->l2_ref_cnt > 0)
475 l2_filter->l2_ref_cnt--;
477 if (l2_filter->l2_ref_cnt > 0)
480 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
482 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
484 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
489 filter->fw_l2_filter_id = UINT64_MAX;
490 if (l2_filter->l2_ref_cnt == 0) {
491 vnic = l2_filter->vnic;
493 STAILQ_REMOVE(&vnic->filter, l2_filter,
494 bnxt_filter_info, next);
495 bnxt_free_filter(bp, l2_filter);
502 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
504 struct bnxt_filter_info *filter)
507 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
508 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
509 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
510 const struct rte_eth_vmdq_rx_conf *conf =
511 &dev_conf->rx_adv_conf.vmdq_rx_conf;
512 uint32_t enables = 0;
513 uint16_t j = dst_id - 1;
515 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
516 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
517 conf->pool_map[j].pools & (1UL << j)) {
519 "Add vlan %u to vmdq pool %u\n",
520 conf->pool_map[j].vlan_id, j);
522 filter->l2_ivlan = conf->pool_map[j].vlan_id;
524 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
525 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
528 if (filter->fw_l2_filter_id != UINT64_MAX)
529 bnxt_hwrm_clear_l2_filter(bp, filter);
531 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
533 req.flags = rte_cpu_to_le_32(filter->flags);
535 enables = filter->enables |
536 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
537 req.dst_id = rte_cpu_to_le_16(dst_id);
540 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
541 memcpy(req.l2_addr, filter->l2_addr,
544 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
545 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
548 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
549 req.l2_ovlan = filter->l2_ovlan;
551 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
552 req.l2_ivlan = filter->l2_ivlan;
554 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
555 req.l2_ovlan_mask = filter->l2_ovlan_mask;
557 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
558 req.l2_ivlan_mask = filter->l2_ivlan_mask;
559 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
560 req.src_id = rte_cpu_to_le_32(filter->src_id);
561 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
562 req.src_type = filter->src_type;
563 if (filter->pri_hint) {
564 req.pri_hint = filter->pri_hint;
565 req.l2_filter_id_hint =
566 rte_cpu_to_le_64(filter->l2_filter_id_hint);
569 req.enables = rte_cpu_to_le_32(enables);
571 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
575 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
576 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
579 filter->l2_ref_cnt++;
584 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
586 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
587 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
594 HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
597 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
600 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
601 if (ptp->tx_tstamp_en)
602 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
605 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
606 req.flags = rte_cpu_to_le_32(flags);
607 req.enables = rte_cpu_to_le_32
608 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
609 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
611 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
617 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
620 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
621 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
622 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
627 HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
629 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
631 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
635 if (!BNXT_CHIP_THOR(bp) &&
636 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
639 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
640 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
642 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
646 if (!BNXT_CHIP_THOR(bp)) {
647 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
648 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
649 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
650 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
651 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
652 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
653 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
654 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
655 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
656 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
657 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
658 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
659 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
660 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
661 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
662 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
663 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
664 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
673 void bnxt_hwrm_free_vf_info(struct bnxt *bp)
677 for (i = 0; i < bp->pf->max_vfs; i++) {
678 rte_free(bp->pf->vf_info[i].vlan_table);
679 bp->pf->vf_info[i].vlan_table = NULL;
680 rte_free(bp->pf->vf_info[i].vlan_as_table);
681 bp->pf->vf_info[i].vlan_as_table = NULL;
683 rte_free(bp->pf->vf_info);
684 bp->pf->vf_info = NULL;
687 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
690 struct hwrm_func_qcaps_input req = {.req_type = 0 };
691 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
692 uint16_t new_max_vfs;
696 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
698 req.fid = rte_cpu_to_le_16(0xffff);
700 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
704 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
705 flags = rte_le_to_cpu_32(resp->flags);
707 bp->pf->port_id = resp->port_id;
708 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
709 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
710 new_max_vfs = bp->pdev->max_vfs;
711 if (new_max_vfs != bp->pf->max_vfs) {
713 bnxt_hwrm_free_vf_info(bp);
714 bp->pf->vf_info = rte_zmalloc("bnxt_vf_info",
715 sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
716 if (bp->pf->vf_info == NULL) {
717 PMD_DRV_LOG(ERR, "Alloc vf info fail\n");
720 bp->pf->max_vfs = new_max_vfs;
721 for (i = 0; i < new_max_vfs; i++) {
722 bp->pf->vf_info[i].fid =
723 bp->pf->first_vf_id + i;
724 bp->pf->vf_info[i].vlan_table =
725 rte_zmalloc("VF VLAN table",
728 if (bp->pf->vf_info[i].vlan_table == NULL)
730 "Fail to alloc VLAN table for VF %d\n",
734 bp->pf->vf_info[i].vlan_table);
735 bp->pf->vf_info[i].vlan_as_table =
736 rte_zmalloc("VF VLAN AS table",
739 if (bp->pf->vf_info[i].vlan_as_table == NULL)
741 "Alloc VLAN AS table for VF %d fail\n",
745 bp->pf->vf_info[i].vlan_as_table);
746 STAILQ_INIT(&bp->pf->vf_info[i].filter);
751 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
752 if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
753 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
754 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
756 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
758 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
759 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
760 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
761 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
762 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
763 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
764 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
765 if (!BNXT_CHIP_THOR(bp))
766 bp->max_l2_ctx += bp->max_rx_em_flows;
767 /* TODO: For now, do not support VMDq/RFS on VFs. */
772 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
776 PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
777 bp->max_l2_ctx, bp->max_vnics);
778 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
780 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
781 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
782 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
783 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
785 bnxt_hwrm_ptp_qcfg(bp);
789 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
790 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
792 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
793 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
794 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
797 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
798 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
800 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
801 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
808 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
812 rc = __bnxt_hwrm_func_qcaps(bp);
813 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
814 rc = bnxt_alloc_ctx_mem(bp);
818 rc = bnxt_hwrm_func_resc_qcaps(bp);
820 bp->flags |= BNXT_FLAG_NEW_RM;
824 * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
825 * But the error can be ignored. Return success.
831 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
832 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
835 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
836 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
838 HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
840 req.target_id = rte_cpu_to_le_16(0xffff);
842 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
846 if (rte_le_to_cpu_32(resp->flags) &
847 HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
848 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
849 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
852 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
859 int bnxt_hwrm_func_reset(struct bnxt *bp)
862 struct hwrm_func_reset_input req = {.req_type = 0 };
863 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
865 HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
867 req.enables = rte_cpu_to_le_32(0);
869 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
877 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
881 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
882 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
884 if (bp->flags & BNXT_FLAG_REGISTERED)
887 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
888 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
889 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
890 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
892 /* PFs and trusted VFs should indicate the support of the
893 * Master capability on non Stingray platform
895 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
896 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
898 HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
899 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
900 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
901 req.ver_maj = RTE_VER_YEAR;
902 req.ver_min = RTE_VER_MONTH;
903 req.ver_upd = RTE_VER_MINOR;
906 req.enables |= rte_cpu_to_le_32(
907 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
908 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
909 RTE_MIN(sizeof(req.vf_req_fwd),
910 sizeof(bp->pf->vf_req_fwd)));
913 * PF can sniff HWRM API issued by VF. This can be set up by
914 * linux driver and inherited by the DPDK PF driver. Clear
915 * this HWRM sniffer list in FW because DPDK PF driver does
918 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
921 req.flags = rte_cpu_to_le_32(flags);
923 req.async_event_fwd[0] |=
924 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
925 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
926 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
927 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
928 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
929 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
930 req.async_event_fwd[0] |=
931 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
932 req.async_event_fwd[1] |=
933 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
934 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
936 req.async_event_fwd[1] |=
937 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
939 if (BNXT_VF_IS_TRUSTED(bp))
940 req.async_event_fwd[1] |=
941 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
943 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
947 flags = rte_le_to_cpu_32(resp->flags);
948 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
949 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
953 bp->flags |= BNXT_FLAG_REGISTERED;
958 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
960 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
963 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
966 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
971 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
972 struct hwrm_func_vf_cfg_input req = {0};
974 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
976 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
977 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
978 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
979 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
980 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
982 if (BNXT_HAS_RING_GRPS(bp)) {
983 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
984 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
987 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
988 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
989 AGG_RING_MULTIPLIER);
990 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
991 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
993 BNXT_NUM_ASYNC_CPR(bp));
994 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
995 if (bp->vf_resv_strategy ==
996 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
997 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
998 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
999 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1000 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1001 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1002 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1003 } else if (bp->vf_resv_strategy ==
1004 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1005 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1006 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1010 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1011 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1012 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1013 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1014 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1015 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1017 if (test && BNXT_HAS_RING_GRPS(bp))
1018 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1020 req.flags = rte_cpu_to_le_32(flags);
1021 req.enables |= rte_cpu_to_le_32(enables);
1023 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1026 HWRM_CHECK_RESULT_SILENT();
1028 HWRM_CHECK_RESULT();
1034 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1037 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1038 struct hwrm_func_resource_qcaps_input req = {0};
1040 HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1041 req.fid = rte_cpu_to_le_16(0xffff);
1043 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1045 HWRM_CHECK_RESULT_SILENT();
1048 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1049 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1050 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1051 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1052 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1053 /* func_resource_qcaps does not return max_rx_em_flows.
1054 * So use the value provided by func_qcaps.
1056 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1057 if (!BNXT_CHIP_THOR(bp))
1058 bp->max_l2_ctx += bp->max_rx_em_flows;
1059 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1060 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1062 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1063 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1064 if (bp->vf_resv_strategy >
1065 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1066 bp->vf_resv_strategy =
1067 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1073 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1076 struct hwrm_ver_get_input req = {.req_type = 0 };
1077 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1078 uint32_t fw_version;
1079 uint16_t max_resp_len;
1080 char type[RTE_MEMZONE_NAMESIZE];
1081 uint32_t dev_caps_cfg;
1083 bp->max_req_len = HWRM_MAX_REQ_LEN;
1084 bp->hwrm_cmd_timeout = timeout;
1085 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1087 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1088 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1089 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1091 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1093 if (bp->flags & BNXT_FLAG_FW_RESET)
1094 HWRM_CHECK_RESULT_SILENT();
1096 HWRM_CHECK_RESULT();
1098 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1099 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1100 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1101 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1102 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1103 (resp->hwrm_fw_min_8b << 16) |
1104 (resp->hwrm_fw_bld_8b << 8) |
1105 resp->hwrm_fw_rsvd_8b;
1106 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1107 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1109 fw_version = resp->hwrm_intf_maj_8b << 16;
1110 fw_version |= resp->hwrm_intf_min_8b << 8;
1111 fw_version |= resp->hwrm_intf_upd_8b;
1112 bp->hwrm_spec_code = fw_version;
1114 /* def_req_timeout value is in milliseconds */
1115 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1116 /* convert timeout to usec */
1117 bp->hwrm_cmd_timeout *= 1000;
1118 if (!bp->hwrm_cmd_timeout)
1119 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1121 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1122 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1127 if (bp->max_req_len > resp->max_req_win_len) {
1128 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1131 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1132 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1133 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1134 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1136 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1137 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1139 if (bp->max_resp_len != max_resp_len) {
1140 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1141 bp->pdev->addr.domain, bp->pdev->addr.bus,
1142 bp->pdev->addr.devid, bp->pdev->addr.function);
1144 rte_free(bp->hwrm_cmd_resp_addr);
1146 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1147 if (bp->hwrm_cmd_resp_addr == NULL) {
1151 bp->hwrm_cmd_resp_dma_addr =
1152 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1153 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1155 "Unable to map response buffer to physical memory.\n");
1159 bp->max_resp_len = max_resp_len;
1163 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1165 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1166 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1167 bp->flags |= BNXT_FLAG_SHORT_CMD;
1170 if (((dev_caps_cfg &
1171 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1173 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1174 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1175 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1176 bp->pdev->addr.domain, bp->pdev->addr.bus,
1177 bp->pdev->addr.devid, bp->pdev->addr.function);
1179 rte_free(bp->hwrm_short_cmd_req_addr);
1181 bp->hwrm_short_cmd_req_addr =
1182 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1183 if (bp->hwrm_short_cmd_req_addr == NULL) {
1187 bp->hwrm_short_cmd_req_dma_addr =
1188 rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1189 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1190 rte_free(bp->hwrm_short_cmd_req_addr);
1192 "Unable to map buffer to physical memory.\n");
1198 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1199 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1200 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1203 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1204 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1206 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1207 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1208 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1212 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1213 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1214 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1223 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1226 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1227 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1229 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1232 HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1235 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1237 HWRM_CHECK_RESULT();
1243 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1246 struct hwrm_port_phy_cfg_input req = {0};
1247 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1248 uint32_t enables = 0;
1250 HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1252 if (conf->link_up) {
1253 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1254 if (bp->link_info->auto_mode && conf->link_speed) {
1255 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1256 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1259 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1260 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1261 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1263 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1264 * any auto mode, even "none".
1266 if (!conf->link_speed) {
1267 /* No speeds specified. Enable AutoNeg - all speeds */
1269 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1271 /* AutoNeg - Advertise speeds specified. */
1272 if (conf->auto_link_speed_mask &&
1273 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1275 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1276 req.auto_link_speed_mask =
1277 conf->auto_link_speed_mask;
1279 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1282 req.auto_duplex = conf->duplex;
1283 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1284 req.auto_pause = conf->auto_pause;
1285 req.force_pause = conf->force_pause;
1286 /* Set force_pause if there is no auto or if there is a force */
1287 if (req.auto_pause && !req.force_pause)
1288 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1290 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1292 req.enables = rte_cpu_to_le_32(enables);
1295 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1296 PMD_DRV_LOG(INFO, "Force Link Down\n");
1299 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1301 HWRM_CHECK_RESULT();
1307 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1308 struct bnxt_link_info *link_info)
1311 struct hwrm_port_phy_qcfg_input req = {0};
1312 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1314 HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1316 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1318 HWRM_CHECK_RESULT();
1320 link_info->phy_link_status = resp->link;
1321 link_info->link_up =
1322 (link_info->phy_link_status ==
1323 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1324 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1325 link_info->duplex = resp->duplex_cfg;
1326 link_info->pause = resp->pause;
1327 link_info->auto_pause = resp->auto_pause;
1328 link_info->force_pause = resp->force_pause;
1329 link_info->auto_mode = resp->auto_mode;
1330 link_info->phy_type = resp->phy_type;
1331 link_info->media_type = resp->media_type;
1333 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1334 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1335 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1336 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1337 link_info->phy_ver[0] = resp->phy_maj;
1338 link_info->phy_ver[1] = resp->phy_min;
1339 link_info->phy_ver[2] = resp->phy_bld;
1343 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1344 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1345 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1346 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1347 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1348 link_info->auto_link_speed_mask);
1349 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1350 link_info->force_link_speed);
1355 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1358 struct hwrm_port_phy_qcaps_input req = {0};
1359 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1361 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1364 HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1366 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1368 HWRM_CHECK_RESULT();
1370 bp->port_cnt = resp->port_cnt;
1377 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1381 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1382 if (bp->tx_cos_queue[i].profile ==
1383 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1384 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1391 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1395 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1396 if (bp->tx_cos_queue[i].profile !=
1397 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1398 bp->tx_cos_queue[i].id !=
1399 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1400 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1406 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1409 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1410 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1411 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1415 HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1417 req.flags = rte_cpu_to_le_32(dir);
1418 /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1419 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1420 !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1422 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1423 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1425 HWRM_CHECK_RESULT();
1427 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1428 GET_TX_QUEUE_INFO(0);
1429 GET_TX_QUEUE_INFO(1);
1430 GET_TX_QUEUE_INFO(2);
1431 GET_TX_QUEUE_INFO(3);
1432 GET_TX_QUEUE_INFO(4);
1433 GET_TX_QUEUE_INFO(5);
1434 GET_TX_QUEUE_INFO(6);
1435 GET_TX_QUEUE_INFO(7);
1437 GET_RX_QUEUE_INFO(0);
1438 GET_RX_QUEUE_INFO(1);
1439 GET_RX_QUEUE_INFO(2);
1440 GET_RX_QUEUE_INFO(3);
1441 GET_RX_QUEUE_INFO(4);
1442 GET_RX_QUEUE_INFO(5);
1443 GET_RX_QUEUE_INFO(6);
1444 GET_RX_QUEUE_INFO(7);
1449 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1452 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1453 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1457 /* iterate and find the COSq profile to use for Tx */
1458 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1459 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1460 if (bp->tx_cos_queue[i].id != 0xff)
1461 bp->tx_cosq_id[j++] =
1462 bp->tx_cos_queue[i].id;
1465 /* When CoS classification is disabled, for normal NIC
1466 * operations, ideally we should look to use LOSSY.
1467 * If not found, fallback to the first valid profile
1469 if (!bnxt_find_lossy_profile(bp))
1470 bnxt_find_first_valid_profile(bp);
1475 bp->max_tc = resp->max_configurable_queues;
1476 bp->max_lltc = resp->max_configurable_lossless_queues;
1477 if (bp->max_tc > BNXT_MAX_QUEUE)
1478 bp->max_tc = BNXT_MAX_QUEUE;
1479 bp->max_q = bp->max_tc;
1481 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1482 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1490 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1491 struct bnxt_ring *ring,
1492 uint32_t ring_type, uint32_t map_index,
1493 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1494 uint16_t tx_cosq_id)
1497 uint32_t enables = 0;
1498 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1499 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1500 struct rte_mempool *mb_pool;
1501 uint16_t rx_buf_size;
1503 HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1505 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1506 req.fbo = rte_cpu_to_le_32(0);
1507 /* Association of ring index with doorbell index */
1508 req.logical_id = rte_cpu_to_le_16(map_index);
1509 req.length = rte_cpu_to_le_32(ring->ring_size);
1511 switch (ring_type) {
1512 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1513 req.ring_type = ring_type;
1514 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1515 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1516 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1517 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1519 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1521 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1522 req.ring_type = ring_type;
1523 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1524 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1525 if (BNXT_CHIP_THOR(bp)) {
1526 mb_pool = bp->rx_queues[0]->mb_pool;
1527 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1528 RTE_PKTMBUF_HEADROOM;
1529 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1530 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1532 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1534 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1536 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1538 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1539 req.ring_type = ring_type;
1540 if (BNXT_HAS_NQ(bp)) {
1541 /* Association of cp ring with nq */
1542 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1544 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1546 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1548 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1549 req.ring_type = ring_type;
1550 req.page_size = BNXT_PAGE_SHFT;
1551 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1553 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1554 req.ring_type = ring_type;
1555 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1557 mb_pool = bp->rx_queues[0]->mb_pool;
1558 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1559 RTE_PKTMBUF_HEADROOM;
1560 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1561 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1563 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1564 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1565 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1566 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1569 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1574 req.enables = rte_cpu_to_le_32(enables);
1576 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1578 if (rc || resp->error_code) {
1579 if (rc == 0 && resp->error_code)
1580 rc = rte_le_to_cpu_16(resp->error_code);
1581 switch (ring_type) {
1582 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1584 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1587 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1589 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1592 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1594 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1598 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1600 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1603 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1605 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1609 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1615 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1620 int bnxt_hwrm_ring_free(struct bnxt *bp,
1621 struct bnxt_ring *ring, uint32_t ring_type)
1624 struct hwrm_ring_free_input req = {.req_type = 0 };
1625 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1627 HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1629 req.ring_type = ring_type;
1630 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1632 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1634 if (rc || resp->error_code) {
1635 if (rc == 0 && resp->error_code)
1636 rc = rte_le_to_cpu_16(resp->error_code);
1639 switch (ring_type) {
1640 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1641 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1644 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1645 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1648 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1649 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1652 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1654 "hwrm_ring_free nq failed. rc:%d\n", rc);
1656 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1658 "hwrm_ring_free agg failed. rc:%d\n", rc);
1661 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1669 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1672 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1673 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1675 HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1677 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1678 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1679 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1680 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1682 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1684 HWRM_CHECK_RESULT();
1686 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1693 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1696 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1697 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1699 HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1701 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1703 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1705 HWRM_CHECK_RESULT();
1708 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1712 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1715 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1716 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1718 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1721 HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1723 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1725 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1727 HWRM_CHECK_RESULT();
1733 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1734 unsigned int idx __rte_unused)
1737 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1738 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1740 HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1742 req.update_period_ms = rte_cpu_to_le_32(0);
1744 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1746 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1748 HWRM_CHECK_RESULT();
1750 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1757 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1758 unsigned int idx __rte_unused)
1761 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1762 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1764 HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1766 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1768 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1770 HWRM_CHECK_RESULT();
1776 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1779 struct hwrm_vnic_alloc_input req = { 0 };
1780 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1782 if (!BNXT_HAS_RING_GRPS(bp))
1783 goto skip_ring_grps;
1785 /* map ring groups to this vnic */
1786 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1787 vnic->start_grp_id, vnic->end_grp_id);
1788 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1789 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1791 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1792 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1793 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1794 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1797 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1798 HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1800 if (vnic->func_default)
1802 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1803 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1805 HWRM_CHECK_RESULT();
1807 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1809 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1813 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1814 struct bnxt_vnic_info *vnic,
1815 struct bnxt_plcmodes_cfg *pmode)
1818 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1819 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1821 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1823 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1825 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1827 HWRM_CHECK_RESULT();
1829 pmode->flags = rte_le_to_cpu_32(resp->flags);
1830 /* dflt_vnic bit doesn't exist in the _cfg command */
1831 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1832 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1833 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1834 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1841 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1842 struct bnxt_vnic_info *vnic,
1843 struct bnxt_plcmodes_cfg *pmode)
1846 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1847 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1849 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1850 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1854 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1856 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1857 req.flags = rte_cpu_to_le_32(pmode->flags);
1858 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1859 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1860 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1861 req.enables = rte_cpu_to_le_32(
1862 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1863 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1864 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1867 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1869 HWRM_CHECK_RESULT();
1875 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1878 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1879 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1880 struct bnxt_plcmodes_cfg pmodes = { 0 };
1881 uint32_t ctx_enable_flag = 0;
1882 uint32_t enables = 0;
1884 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1885 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1889 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1893 HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1895 if (BNXT_CHIP_THOR(bp)) {
1896 int dflt_rxq = vnic->start_grp_id;
1897 struct bnxt_rx_ring_info *rxr;
1898 struct bnxt_cp_ring_info *cpr;
1899 struct bnxt_rx_queue *rxq;
1903 * The first active receive ring is used as the VNIC
1904 * default receive ring. If there are no active receive
1905 * rings (all corresponding receive queues are stopped),
1906 * the first receive ring is used.
1908 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1909 rxq = bp->eth_dev->data->rx_queues[i];
1910 if (rxq->rx_started) {
1916 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1920 req.default_rx_ring_id =
1921 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1922 req.default_cmpl_ring_id =
1923 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1924 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1925 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1929 /* Only RSS support for now TBD: COS & LB */
1930 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1931 if (vnic->lb_rule != 0xffff)
1932 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1933 if (vnic->cos_rule != 0xffff)
1934 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1935 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1936 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1937 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1939 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1940 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1941 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1944 enables |= ctx_enable_flag;
1945 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1946 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1947 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1948 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1951 req.enables = rte_cpu_to_le_32(enables);
1952 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1953 req.mru = rte_cpu_to_le_16(vnic->mru);
1954 /* Configure default VNIC only once. */
1955 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1957 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1958 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1960 if (vnic->vlan_strip)
1962 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1965 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1966 if (vnic->roce_dual)
1967 req.flags |= rte_cpu_to_le_32(
1968 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1969 if (vnic->roce_only)
1970 req.flags |= rte_cpu_to_le_32(
1971 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1972 if (vnic->rss_dflt_cr)
1973 req.flags |= rte_cpu_to_le_32(
1974 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1976 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1978 HWRM_CHECK_RESULT();
1981 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1986 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1990 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1991 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1993 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1994 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1997 HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2000 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2001 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2002 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2004 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2006 HWRM_CHECK_RESULT();
2008 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2009 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2010 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2011 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2012 vnic->mru = rte_le_to_cpu_16(resp->mru);
2013 vnic->func_default = rte_le_to_cpu_32(
2014 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2015 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2016 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2017 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2018 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2019 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
2020 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
2021 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
2022 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
2023 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2024 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2031 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2032 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2036 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2037 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2038 bp->hwrm_cmd_resp_addr;
2040 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2042 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2043 HWRM_CHECK_RESULT();
2045 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2046 if (!BNXT_HAS_RING_GRPS(bp))
2047 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2048 else if (ctx_idx == 0)
2049 vnic->rss_rule = ctx_id;
2057 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2058 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2061 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2062 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2063 bp->hwrm_cmd_resp_addr;
2065 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2066 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2069 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2071 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2073 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2075 HWRM_CHECK_RESULT();
2081 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2085 if (BNXT_CHIP_THOR(bp)) {
2088 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2089 rc = _bnxt_hwrm_vnic_ctx_free(bp,
2091 vnic->fw_grp_ids[j]);
2092 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2094 vnic->num_lb_ctxts = 0;
2096 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2097 vnic->rss_rule = INVALID_HW_RING_ID;
2103 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2106 struct hwrm_vnic_free_input req = {.req_type = 0 };
2107 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2109 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2110 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2114 HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2116 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2118 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2120 HWRM_CHECK_RESULT();
2123 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2124 /* Configure default VNIC again if necessary. */
2125 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2126 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2132 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2136 int nr_ctxs = vnic->num_lb_ctxts;
2137 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2138 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2140 for (i = 0; i < nr_ctxs; i++) {
2141 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2143 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2144 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2145 req.hash_mode_flags = vnic->hash_mode;
2147 req.hash_key_tbl_addr =
2148 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2150 req.ring_grp_tbl_addr =
2151 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2152 i * HW_HASH_INDEX_SIZE);
2153 req.ring_table_pair_index = i;
2154 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2156 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2159 HWRM_CHECK_RESULT();
2166 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2167 struct bnxt_vnic_info *vnic)
2170 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2171 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2173 if (!vnic->rss_table)
2176 if (BNXT_CHIP_THOR(bp))
2177 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2179 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2181 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2182 req.hash_mode_flags = vnic->hash_mode;
2184 req.ring_grp_tbl_addr =
2185 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2186 req.hash_key_tbl_addr =
2187 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2188 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2189 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2191 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2193 HWRM_CHECK_RESULT();
2199 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2200 struct bnxt_vnic_info *vnic)
2203 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2204 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2207 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2208 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2212 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2214 req.flags = rte_cpu_to_le_32(
2215 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2217 req.enables = rte_cpu_to_le_32(
2218 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2220 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2221 size -= RTE_PKTMBUF_HEADROOM;
2222 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2224 req.jumbo_thresh = rte_cpu_to_le_16(size);
2225 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2227 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2229 HWRM_CHECK_RESULT();
2235 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2236 struct bnxt_vnic_info *vnic, bool enable)
2239 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2240 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2242 if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2244 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2248 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2249 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2253 HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2256 req.enables = rte_cpu_to_le_32(
2257 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2258 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2259 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2260 req.flags = rte_cpu_to_le_32(
2261 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2262 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2263 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2264 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2265 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2266 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2267 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2268 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2269 req.min_agg_len = rte_cpu_to_le_32(512);
2271 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2273 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2275 HWRM_CHECK_RESULT();
2281 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2283 struct hwrm_func_cfg_input req = {0};
2284 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2287 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2288 req.enables = rte_cpu_to_le_32(
2289 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2290 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2291 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2293 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2295 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2296 HWRM_CHECK_RESULT();
2299 bp->pf->vf_info[vf].random_mac = false;
2304 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2308 struct hwrm_func_qstats_input req = {.req_type = 0};
2309 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2311 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2313 req.fid = rte_cpu_to_le_16(fid);
2315 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2317 HWRM_CHECK_RESULT();
2320 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2327 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2328 struct rte_eth_stats *stats,
2329 struct hwrm_func_qstats_output *func_qstats)
2332 struct hwrm_func_qstats_input req = {.req_type = 0};
2333 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2335 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2337 req.fid = rte_cpu_to_le_16(fid);
2339 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2341 HWRM_CHECK_RESULT();
2343 memcpy(func_qstats, resp,
2344 sizeof(struct hwrm_func_qstats_output));
2349 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2350 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2351 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2352 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2353 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2354 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2356 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2357 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2358 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2359 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2360 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2361 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2363 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2364 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2365 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2373 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2376 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2377 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2379 HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2381 req.fid = rte_cpu_to_le_16(fid);
2383 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2385 HWRM_CHECK_RESULT();
2391 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2396 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2397 struct bnxt_tx_queue *txq;
2398 struct bnxt_rx_queue *rxq;
2399 struct bnxt_cp_ring_info *cpr;
2401 if (i >= bp->rx_cp_nr_rings) {
2402 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2405 rxq = bp->rx_queues[i];
2409 rc = bnxt_hwrm_stat_clear(bp, cpr);
2417 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2421 struct bnxt_cp_ring_info *cpr;
2423 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2425 if (i >= bp->rx_cp_nr_rings) {
2426 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2428 cpr = bp->rx_queues[i]->cp_ring;
2429 if (BNXT_HAS_RING_GRPS(bp))
2430 bp->grp_info[i].fw_stats_ctx = -1;
2432 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2433 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2434 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2442 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2447 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2448 struct bnxt_tx_queue *txq;
2449 struct bnxt_rx_queue *rxq;
2450 struct bnxt_cp_ring_info *cpr;
2452 if (i >= bp->rx_cp_nr_rings) {
2453 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2456 rxq = bp->rx_queues[i];
2460 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2469 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2474 if (!BNXT_HAS_RING_GRPS(bp))
2477 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2479 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2482 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2490 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2492 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2494 bnxt_hwrm_ring_free(bp, cp_ring,
2495 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2496 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2497 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2498 sizeof(*cpr->cp_desc_ring));
2499 cpr->cp_raw_cons = 0;
2503 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2505 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2507 bnxt_hwrm_ring_free(bp, cp_ring,
2508 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2509 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2510 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2511 sizeof(*cpr->cp_desc_ring));
2512 cpr->cp_raw_cons = 0;
2516 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2518 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2519 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2520 struct bnxt_ring *ring = rxr->rx_ring_struct;
2521 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2523 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2524 bnxt_hwrm_ring_free(bp, ring,
2525 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2526 ring->fw_ring_id = INVALID_HW_RING_ID;
2527 if (BNXT_HAS_RING_GRPS(bp))
2528 bp->grp_info[queue_index].rx_fw_ring_id =
2531 ring = rxr->ag_ring_struct;
2532 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2533 bnxt_hwrm_ring_free(bp, ring,
2534 BNXT_CHIP_THOR(bp) ?
2535 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2536 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2537 if (BNXT_HAS_RING_GRPS(bp))
2538 bp->grp_info[queue_index].ag_fw_ring_id =
2541 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2542 bnxt_free_cp_ring(bp, cpr);
2544 if (BNXT_HAS_RING_GRPS(bp))
2545 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2549 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2553 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2554 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2555 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2556 struct bnxt_ring *ring = txr->tx_ring_struct;
2557 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2559 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2560 bnxt_hwrm_ring_free(bp, ring,
2561 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2562 ring->fw_ring_id = INVALID_HW_RING_ID;
2563 memset(txr->tx_desc_ring, 0,
2564 txr->tx_ring_struct->ring_size *
2565 sizeof(*txr->tx_desc_ring));
2566 memset(txr->tx_buf_ring, 0,
2567 txr->tx_ring_struct->ring_size *
2568 sizeof(*txr->tx_buf_ring));
2572 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2573 bnxt_free_cp_ring(bp, cpr);
2574 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2578 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2579 bnxt_free_hwrm_rx_ring(bp, i);
2584 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2589 if (!BNXT_HAS_RING_GRPS(bp))
2592 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2593 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2601 * HWRM utility functions
2604 void bnxt_free_hwrm_resources(struct bnxt *bp)
2606 /* Release memzone */
2607 rte_free(bp->hwrm_cmd_resp_addr);
2608 rte_free(bp->hwrm_short_cmd_req_addr);
2609 bp->hwrm_cmd_resp_addr = NULL;
2610 bp->hwrm_short_cmd_req_addr = NULL;
2611 bp->hwrm_cmd_resp_dma_addr = 0;
2612 bp->hwrm_short_cmd_req_dma_addr = 0;
2615 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2617 struct rte_pci_device *pdev = bp->pdev;
2618 char type[RTE_MEMZONE_NAMESIZE];
2620 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2621 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2622 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2623 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2624 if (bp->hwrm_cmd_resp_addr == NULL)
2626 bp->hwrm_cmd_resp_dma_addr =
2627 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2628 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2630 "unable to map response address to physical memory\n");
2633 rte_spinlock_init(&bp->hwrm_lock);
2639 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2643 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2644 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2647 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2648 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2653 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2658 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2660 struct bnxt_filter_info *filter;
2663 STAILQ_FOREACH(filter, &vnic->filter, next) {
2664 rc = bnxt_clear_one_vnic_filter(bp, filter);
2665 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2666 bnxt_free_filter(bp, filter);
2672 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2674 struct bnxt_filter_info *filter;
2675 struct rte_flow *flow;
2678 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2679 flow = STAILQ_FIRST(&vnic->flow_list);
2680 filter = flow->filter;
2681 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2682 rc = bnxt_clear_one_vnic_filter(bp, filter);
2684 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2690 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2692 struct bnxt_filter_info *filter;
2695 STAILQ_FOREACH(filter, &vnic->filter, next) {
2696 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2697 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2699 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2700 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2703 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2712 bnxt_free_tunnel_ports(struct bnxt *bp)
2714 if (bp->vxlan_port_cnt)
2715 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2716 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2718 if (bp->geneve_port_cnt)
2719 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2720 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2721 bp->geneve_port = 0;
2724 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2728 if (bp->vnic_info == NULL)
2732 * Cleanup VNICs in reverse order, to make sure the L2 filter
2733 * from vnic0 is last to be cleaned up.
2735 for (i = bp->max_vnics - 1; i >= 0; i--) {
2736 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2738 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2741 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2743 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2745 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2747 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2749 bnxt_hwrm_vnic_free(bp, vnic);
2751 rte_free(vnic->fw_grp_ids);
2753 /* Ring resources */
2754 bnxt_free_all_hwrm_rings(bp);
2755 bnxt_free_all_hwrm_ring_grps(bp);
2756 bnxt_free_all_hwrm_stat_ctxs(bp);
2757 bnxt_free_tunnel_ports(bp);
2760 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2762 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2764 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2765 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2767 switch (conf_link_speed) {
2768 case ETH_LINK_SPEED_10M_HD:
2769 case ETH_LINK_SPEED_100M_HD:
2771 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2773 return hw_link_duplex;
2776 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2778 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2781 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2783 uint16_t eth_link_speed = 0;
2785 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2786 return ETH_LINK_SPEED_AUTONEG;
2788 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2789 case ETH_LINK_SPEED_100M:
2790 case ETH_LINK_SPEED_100M_HD:
2793 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2795 case ETH_LINK_SPEED_1G:
2797 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2799 case ETH_LINK_SPEED_2_5G:
2801 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2803 case ETH_LINK_SPEED_10G:
2805 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2807 case ETH_LINK_SPEED_20G:
2809 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2811 case ETH_LINK_SPEED_25G:
2813 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2815 case ETH_LINK_SPEED_40G:
2817 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2819 case ETH_LINK_SPEED_50G:
2821 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2823 case ETH_LINK_SPEED_100G:
2825 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2827 case ETH_LINK_SPEED_200G:
2829 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB;
2833 "Unsupported link speed %d; default to AUTO\n",
2837 return eth_link_speed;
2840 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2841 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2842 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2843 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2844 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2846 static int bnxt_validate_link_speed(struct bnxt *bp)
2848 uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
2849 uint16_t port_id = bp->eth_dev->data->port_id;
2850 uint32_t link_speed_capa;
2853 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2856 link_speed_capa = bnxt_get_speed_capabilities(bp);
2858 if (link_speed & ETH_LINK_SPEED_FIXED) {
2859 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2861 if (one_speed & (one_speed - 1)) {
2863 "Invalid advertised speeds (%u) for port %u\n",
2864 link_speed, port_id);
2867 if ((one_speed & link_speed_capa) != one_speed) {
2869 "Unsupported advertised speed (%u) for port %u\n",
2870 link_speed, port_id);
2874 if (!(link_speed & link_speed_capa)) {
2876 "Unsupported advertised speeds (%u) for port %u\n",
2877 link_speed, port_id);
2885 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2889 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2890 if (bp->link_info->support_speeds)
2891 return bp->link_info->support_speeds;
2892 link_speed = BNXT_SUPPORTED_SPEEDS;
2895 if (link_speed & ETH_LINK_SPEED_100M)
2896 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2897 if (link_speed & ETH_LINK_SPEED_100M_HD)
2898 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2899 if (link_speed & ETH_LINK_SPEED_1G)
2900 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2901 if (link_speed & ETH_LINK_SPEED_2_5G)
2902 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2903 if (link_speed & ETH_LINK_SPEED_10G)
2904 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2905 if (link_speed & ETH_LINK_SPEED_20G)
2906 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2907 if (link_speed & ETH_LINK_SPEED_25G)
2908 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2909 if (link_speed & ETH_LINK_SPEED_40G)
2910 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2911 if (link_speed & ETH_LINK_SPEED_50G)
2912 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2913 if (link_speed & ETH_LINK_SPEED_100G)
2914 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2915 if (link_speed & ETH_LINK_SPEED_200G)
2916 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB;
2920 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2922 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2924 switch (hw_link_speed) {
2925 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2926 eth_link_speed = ETH_SPEED_NUM_100M;
2928 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2929 eth_link_speed = ETH_SPEED_NUM_1G;
2931 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2932 eth_link_speed = ETH_SPEED_NUM_2_5G;
2934 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2935 eth_link_speed = ETH_SPEED_NUM_10G;
2937 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2938 eth_link_speed = ETH_SPEED_NUM_20G;
2940 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2941 eth_link_speed = ETH_SPEED_NUM_25G;
2943 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2944 eth_link_speed = ETH_SPEED_NUM_40G;
2946 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2947 eth_link_speed = ETH_SPEED_NUM_50G;
2949 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2950 eth_link_speed = ETH_SPEED_NUM_100G;
2952 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
2953 eth_link_speed = ETH_SPEED_NUM_200G;
2955 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2957 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2961 return eth_link_speed;
2964 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2966 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2968 switch (hw_link_duplex) {
2969 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2970 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2972 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2974 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2975 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2978 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2982 return eth_link_duplex;
2985 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2988 struct bnxt_link_info *link_info = bp->link_info;
2990 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2993 "Get link config failed with rc %d\n", rc);
2996 if (link_info->link_speed)
2998 bnxt_parse_hw_link_speed(link_info->link_speed);
3000 link->link_speed = ETH_SPEED_NUM_NONE;
3001 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3002 link->link_status = link_info->link_up;
3003 link->link_autoneg = link_info->auto_mode ==
3004 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3005 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3010 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3013 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3014 struct bnxt_link_info link_req;
3015 uint16_t speed, autoneg;
3017 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3020 rc = bnxt_validate_link_speed(bp);
3024 memset(&link_req, 0, sizeof(link_req));
3025 link_req.link_up = link_up;
3029 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3030 if (BNXT_CHIP_THOR(bp) &&
3031 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3032 /* 40G is not supported as part of media auto detect.
3033 * The speed should be forced and autoneg disabled
3034 * to configure 40G speed.
3036 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3040 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
3041 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3042 /* Autoneg can be done only when the FW allows.
3043 * When user configures fixed speed of 40G and later changes to
3044 * any other speed, auto_link_speed/force_link_speed is still set
3045 * to 40G until link comes up at new speed.
3048 !(!BNXT_CHIP_THOR(bp) &&
3049 (bp->link_info->auto_link_speed ||
3050 bp->link_info->force_link_speed))) {
3051 link_req.phy_flags |=
3052 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3053 link_req.auto_link_speed_mask =
3054 bnxt_parse_eth_link_speed_mask(bp,
3055 dev_conf->link_speeds);
3057 if (bp->link_info->phy_type ==
3058 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3059 bp->link_info->phy_type ==
3060 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3061 bp->link_info->media_type ==
3062 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3063 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3067 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3068 /* If user wants a particular speed try that first. */
3070 link_req.link_speed = speed;
3071 else if (bp->link_info->force_link_speed)
3072 link_req.link_speed = bp->link_info->force_link_speed;
3074 link_req.link_speed = bp->link_info->auto_link_speed;
3076 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3077 link_req.auto_pause = bp->link_info->auto_pause;
3078 link_req.force_pause = bp->link_info->force_pause;
3081 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3084 "Set link config failed with rc %d\n", rc);
3092 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3094 struct hwrm_func_qcfg_input req = {0};
3095 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3098 bp->func_svif = BNXT_SVIF_INVALID;
3101 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3102 req.fid = rte_cpu_to_le_16(0xffff);
3104 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3106 HWRM_CHECK_RESULT();
3108 /* Hard Coded.. 0xfff VLAN ID mask */
3109 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3111 svif_info = rte_le_to_cpu_16(resp->svif_info);
3112 if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3113 bp->func_svif = svif_info &
3114 HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3116 flags = rte_le_to_cpu_16(resp->flags);
3117 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3118 bp->flags |= BNXT_FLAG_MULTI_HOST;
3121 !BNXT_VF_IS_TRUSTED(bp) &&
3122 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3123 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3124 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3125 } else if (BNXT_VF(bp) &&
3126 BNXT_VF_IS_TRUSTED(bp) &&
3127 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3128 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3129 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3133 *mtu = rte_le_to_cpu_16(resp->mtu);
3135 switch (resp->port_partition_type) {
3136 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3137 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3138 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3140 bp->flags |= BNXT_FLAG_NPAR_PF;
3143 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3152 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3154 struct hwrm_func_qcfg_input req = {0};
3155 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3158 if (!BNXT_VF_IS_TRUSTED(bp))
3164 bp->parent->fid = BNXT_PF_FID_INVALID;
3166 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3168 req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3170 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3172 HWRM_CHECK_RESULT();
3174 memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3175 bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3176 bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3177 bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3179 /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3180 if (bp->parent->vnic == 0) {
3181 PMD_DRV_LOG(ERR, "Error: parent VNIC unavailable.\n");
3182 /* Use hard-coded values appropriate for current Wh+ fw. */
3183 if (bp->parent->fid == 2)
3184 bp->parent->vnic = 0x100;
3186 bp->parent->vnic = 1;
3194 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3195 uint16_t *vnic_id, uint16_t *svif)
3197 struct hwrm_func_qcfg_input req = {0};
3198 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3202 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3203 req.fid = rte_cpu_to_le_16(fid);
3205 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3207 HWRM_CHECK_RESULT();
3210 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3212 svif_info = rte_le_to_cpu_16(resp->svif_info);
3213 if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3214 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3221 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3223 struct hwrm_port_mac_qcfg_input req = {0};
3224 struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3225 uint16_t port_svif_info;
3228 bp->port_svif = BNXT_SVIF_INVALID;
3230 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3233 HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3235 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3237 HWRM_CHECK_RESULT_SILENT();
3239 port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3240 if (port_svif_info &
3241 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3242 bp->port_svif = port_svif_info &
3243 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3250 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
3251 struct hwrm_func_qcaps_output *qcaps)
3253 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
3254 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
3255 sizeof(qcaps->mac_address));
3256 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
3257 qcaps->max_rx_rings = fcfg->num_rx_rings;
3258 qcaps->max_tx_rings = fcfg->num_tx_rings;
3259 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
3260 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
3262 qcaps->first_vf_id = 0;
3263 qcaps->max_vnics = fcfg->num_vnics;
3264 qcaps->max_decap_records = 0;
3265 qcaps->max_encap_records = 0;
3266 qcaps->max_tx_wm_flows = 0;
3267 qcaps->max_tx_em_flows = 0;
3268 qcaps->max_rx_wm_flows = 0;
3269 qcaps->max_rx_em_flows = 0;
3270 qcaps->max_flow_id = 0;
3271 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
3272 qcaps->max_sp_tx_rings = 0;
3273 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3276 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3278 struct hwrm_func_cfg_input req = {0};
3279 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3283 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3284 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3285 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3286 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3287 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3288 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3289 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3290 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3291 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3293 if (BNXT_HAS_RING_GRPS(bp)) {
3294 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3295 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3296 } else if (BNXT_HAS_NQ(bp)) {
3297 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3298 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3301 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3302 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3303 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3304 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3305 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3306 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3307 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3308 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3309 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3310 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3311 req.fid = rte_cpu_to_le_16(0xffff);
3312 req.enables = rte_cpu_to_le_32(enables);
3314 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3316 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3318 HWRM_CHECK_RESULT();
3324 static void populate_vf_func_cfg_req(struct bnxt *bp,
3325 struct hwrm_func_cfg_input *req,
3328 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3329 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3330 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3331 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3332 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3333 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3334 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3335 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3336 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3337 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3339 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3340 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3342 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3343 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3345 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3346 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3348 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3349 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3350 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3351 /* TODO: For now, do not support VMDq/RFS on VFs. */
3352 req->num_vnics = rte_cpu_to_le_16(1);
3353 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3357 static void add_random_mac_if_needed(struct bnxt *bp,
3358 struct hwrm_func_cfg_input *cfg_req,
3361 struct rte_ether_addr mac;
3363 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3366 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3368 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3369 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3370 bp->pf->vf_info[vf].random_mac = true;
3372 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3373 RTE_ETHER_ADDR_LEN);
3377 static int reserve_resources_from_vf(struct bnxt *bp,
3378 struct hwrm_func_cfg_input *cfg_req,
3381 struct hwrm_func_qcaps_input req = {0};
3382 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3385 /* Get the actual allocated values now */
3386 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3387 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3388 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3391 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3392 copy_func_cfg_to_qcaps(cfg_req, resp);
3393 } else if (resp->error_code) {
3394 rc = rte_le_to_cpu_16(resp->error_code);
3395 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3396 copy_func_cfg_to_qcaps(cfg_req, resp);
3399 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3400 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3401 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3402 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3403 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3404 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3406 * TODO: While not supporting VMDq with VFs, max_vnics is always
3407 * forced to 1 in this case
3409 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3410 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3417 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3419 struct hwrm_func_qcfg_input req = {0};
3420 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3423 /* Check for zero MAC address */
3424 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3425 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3426 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3427 HWRM_CHECK_RESULT();
3428 rc = rte_le_to_cpu_16(resp->vlan);
3435 static int update_pf_resource_max(struct bnxt *bp)
3437 struct hwrm_func_qcfg_input req = {0};
3438 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3441 /* And copy the allocated numbers into the pf struct */
3442 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3443 req.fid = rte_cpu_to_le_16(0xffff);
3444 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3445 HWRM_CHECK_RESULT();
3447 /* Only TX ring value reflects actual allocation? TODO */
3448 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3449 bp->pf->evb_mode = resp->evb_mode;
3456 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3461 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3465 rc = bnxt_hwrm_func_qcaps(bp);
3469 bp->pf->func_cfg_flags &=
3470 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3471 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3472 bp->pf->func_cfg_flags |=
3473 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3474 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3475 rc = __bnxt_hwrm_func_qcaps(bp);
3479 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3481 struct hwrm_func_cfg_input req = {0};
3482 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3489 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3493 rc = bnxt_hwrm_func_qcaps(bp);
3498 bp->pf->active_vfs = num_vfs;
3501 * First, configure the PF to only use one TX ring. This ensures that
3502 * there are enough rings for all VFs.
3504 * If we don't do this, when we call func_alloc() later, we will lock
3505 * extra rings to the PF that won't be available during func_cfg() of
3508 * This has been fixed with firmware versions above 20.6.54
3510 bp->pf->func_cfg_flags &=
3511 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3512 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3513 bp->pf->func_cfg_flags |=
3514 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3515 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3520 * Now, create and register a buffer to hold forwarded VF requests
3522 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3523 bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3524 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3525 if (bp->pf->vf_req_buf == NULL) {
3529 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3530 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3531 for (i = 0; i < num_vfs; i++)
3532 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3533 (i * HWRM_MAX_REQ_LEN);
3535 rc = bnxt_hwrm_func_buf_rgtr(bp);
3539 populate_vf_func_cfg_req(bp, &req, num_vfs);
3541 bp->pf->active_vfs = 0;
3542 for (i = 0; i < num_vfs; i++) {
3543 add_random_mac_if_needed(bp, &req, i);
3545 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3546 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3547 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3548 rc = bnxt_hwrm_send_message(bp,
3553 /* Clear enable flag for next pass */
3554 req.enables &= ~rte_cpu_to_le_32(
3555 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3557 if (rc || resp->error_code) {
3559 "Failed to initizlie VF %d\n", i);
3561 "Not all VFs available. (%d, %d)\n",
3562 rc, resp->error_code);
3569 reserve_resources_from_vf(bp, &req, i);
3570 bp->pf->active_vfs++;
3571 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3575 * Now configure the PF to use "the rest" of the resources
3576 * We're using STD_TX_RING_MODE here though which will limit the TX
3577 * rings. This will allow QoS to function properly. Not setting this
3578 * will cause PF rings to break bandwidth settings.
3580 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3584 rc = update_pf_resource_max(bp);
3591 bnxt_hwrm_func_buf_unrgtr(bp);
3595 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3597 struct hwrm_func_cfg_input req = {0};
3598 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3601 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3603 req.fid = rte_cpu_to_le_16(0xffff);
3604 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3605 req.evb_mode = bp->pf->evb_mode;
3607 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3608 HWRM_CHECK_RESULT();
3614 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3615 uint8_t tunnel_type)
3617 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3618 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3621 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3622 req.tunnel_type = tunnel_type;
3623 req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3624 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3625 HWRM_CHECK_RESULT();
3627 switch (tunnel_type) {
3628 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3629 bp->vxlan_fw_dst_port_id =
3630 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3631 bp->vxlan_port = port;
3633 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3634 bp->geneve_fw_dst_port_id =
3635 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3636 bp->geneve_port = port;
3647 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3648 uint8_t tunnel_type)
3650 struct hwrm_tunnel_dst_port_free_input req = {0};
3651 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3654 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3656 req.tunnel_type = tunnel_type;
3657 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3658 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3660 HWRM_CHECK_RESULT();
3666 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3669 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3670 struct hwrm_func_cfg_input req = {0};
3673 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3675 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3676 req.flags = rte_cpu_to_le_32(flags);
3677 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3679 HWRM_CHECK_RESULT();
3685 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3687 uint32_t *flag = flagp;
3689 vnic->flags = *flag;
3692 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3694 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3697 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3700 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3701 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3703 HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3705 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3706 req.req_buf_page_size = rte_cpu_to_le_16(
3707 page_getenum(bp->pf->active_vfs * HWRM_MAX_REQ_LEN));
3708 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3709 req.req_buf_page_addr0 =
3710 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3711 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3713 "unable to map buffer address to physical memory\n");
3717 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3719 HWRM_CHECK_RESULT();
3725 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3728 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3729 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3731 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3734 HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3736 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3738 HWRM_CHECK_RESULT();
3744 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3746 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3747 struct hwrm_func_cfg_input req = {0};
3750 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3752 req.fid = rte_cpu_to_le_16(0xffff);
3753 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3754 req.enables = rte_cpu_to_le_32(
3755 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3756 req.async_event_cr = rte_cpu_to_le_16(
3757 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3758 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3760 HWRM_CHECK_RESULT();
3766 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3768 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3769 struct hwrm_func_vf_cfg_input req = {0};
3772 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3774 req.enables = rte_cpu_to_le_32(
3775 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3776 req.async_event_cr = rte_cpu_to_le_16(
3777 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3778 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3780 HWRM_CHECK_RESULT();
3786 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3788 struct hwrm_func_cfg_input req = {0};
3789 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3790 uint16_t dflt_vlan, fid;
3791 uint32_t func_cfg_flags;
3794 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3797 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
3798 fid = bp->pf->vf_info[vf].fid;
3799 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
3801 fid = rte_cpu_to_le_16(0xffff);
3802 func_cfg_flags = bp->pf->func_cfg_flags;
3803 dflt_vlan = bp->vlan;
3806 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3807 req.fid = rte_cpu_to_le_16(fid);
3808 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3809 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3811 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3813 HWRM_CHECK_RESULT();
3819 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3820 uint16_t max_bw, uint16_t enables)
3822 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3823 struct hwrm_func_cfg_input req = {0};
3826 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3828 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3829 req.enables |= rte_cpu_to_le_32(enables);
3830 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3831 req.max_bw = rte_cpu_to_le_32(max_bw);
3832 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3834 HWRM_CHECK_RESULT();
3840 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3842 struct hwrm_func_cfg_input req = {0};
3843 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3846 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3848 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3849 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3850 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3851 req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
3853 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3855 HWRM_CHECK_RESULT();
3861 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3866 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3868 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3873 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3874 void *encaped, size_t ec_size)
3877 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3878 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3880 if (ec_size > sizeof(req.encap_request))
3883 HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3885 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3886 memcpy(req.encap_request, encaped, ec_size);
3888 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3890 HWRM_CHECK_RESULT();
3896 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3897 struct rte_ether_addr *mac)
3899 struct hwrm_func_qcfg_input req = {0};
3900 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3903 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3905 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3906 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3908 HWRM_CHECK_RESULT();
3910 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3917 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3918 void *encaped, size_t ec_size)
3921 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3922 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3924 if (ec_size > sizeof(req.encap_request))
3927 HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3929 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3930 memcpy(req.encap_request, encaped, ec_size);
3932 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3934 HWRM_CHECK_RESULT();
3940 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3941 struct rte_eth_stats *stats, uint8_t rx)
3944 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3945 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3947 HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3949 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3951 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3953 HWRM_CHECK_RESULT();
3956 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3957 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3958 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3959 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3960 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3961 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3962 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3963 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3965 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3966 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3967 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3968 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3969 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3970 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3978 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3980 struct hwrm_port_qstats_input req = {0};
3981 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3982 struct bnxt_pf_info *pf = bp->pf;
3985 HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
3987 req.port_id = rte_cpu_to_le_16(pf->port_id);
3988 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3989 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3990 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3992 HWRM_CHECK_RESULT();
3998 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4000 struct hwrm_port_clr_stats_input req = {0};
4001 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4002 struct bnxt_pf_info *pf = bp->pf;
4005 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4006 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4007 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4010 HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4012 req.port_id = rte_cpu_to_le_16(pf->port_id);
4013 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4015 HWRM_CHECK_RESULT();
4021 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4023 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4024 struct hwrm_port_led_qcaps_input req = {0};
4030 HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4031 req.port_id = bp->pf->port_id;
4032 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4034 HWRM_CHECK_RESULT();
4036 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4039 bp->leds->num_leds = resp->num_leds;
4040 memcpy(bp->leds, &resp->led0_id,
4041 sizeof(bp->leds[0]) * bp->leds->num_leds);
4042 for (i = 0; i < bp->leds->num_leds; i++) {
4043 struct bnxt_led_info *led = &bp->leds[i];
4045 uint16_t caps = led->led_state_caps;
4047 if (!led->led_group_id ||
4048 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4049 bp->leds->num_leds = 0;
4060 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4062 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4063 struct hwrm_port_led_cfg_input req = {0};
4064 struct bnxt_led_cfg *led_cfg;
4065 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4066 uint16_t duration = 0;
4069 if (!bp->leds->num_leds || BNXT_VF(bp))
4072 HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4075 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4076 duration = rte_cpu_to_le_16(500);
4078 req.port_id = bp->pf->port_id;
4079 req.num_leds = bp->leds->num_leds;
4080 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4081 for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4082 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4083 led_cfg->led_id = bp->leds[i].led_id;
4084 led_cfg->led_state = led_state;
4085 led_cfg->led_blink_on = duration;
4086 led_cfg->led_blink_off = duration;
4087 led_cfg->led_group_id = bp->leds[i].led_group_id;
4090 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4092 HWRM_CHECK_RESULT();
4098 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4102 struct hwrm_nvm_get_dir_info_input req = {0};
4103 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4105 HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4107 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4109 HWRM_CHECK_RESULT();
4111 *entries = rte_le_to_cpu_32(resp->entries);
4112 *length = rte_le_to_cpu_32(resp->entry_length);
4118 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4121 uint32_t dir_entries;
4122 uint32_t entry_length;
4125 rte_iova_t dma_handle;
4126 struct hwrm_nvm_get_dir_entries_input req = {0};
4127 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4129 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4133 *data++ = dir_entries;
4134 *data++ = entry_length;
4136 memset(data, 0xff, len);
4138 buflen = dir_entries * entry_length;
4139 buf = rte_malloc("nvm_dir", buflen, 0);
4142 dma_handle = rte_malloc_virt2iova(buf);
4143 if (dma_handle == RTE_BAD_IOVA) {
4145 "unable to map response address to physical memory\n");
4148 HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4149 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4150 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4153 memcpy(data, buf, len > buflen ? buflen : len);
4156 HWRM_CHECK_RESULT();
4162 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4163 uint32_t offset, uint32_t length,
4168 rte_iova_t dma_handle;
4169 struct hwrm_nvm_read_input req = {0};
4170 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4172 buf = rte_malloc("nvm_item", length, 0);
4176 dma_handle = rte_malloc_virt2iova(buf);
4177 if (dma_handle == RTE_BAD_IOVA) {
4179 "unable to map response address to physical memory\n");
4182 HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4183 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4184 req.dir_idx = rte_cpu_to_le_16(index);
4185 req.offset = rte_cpu_to_le_32(offset);
4186 req.len = rte_cpu_to_le_32(length);
4187 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4189 memcpy(data, buf, length);
4192 HWRM_CHECK_RESULT();
4198 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4201 struct hwrm_nvm_erase_dir_entry_input req = {0};
4202 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4204 HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4205 req.dir_idx = rte_cpu_to_le_16(index);
4206 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4207 HWRM_CHECK_RESULT();
4214 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4215 uint16_t dir_ordinal, uint16_t dir_ext,
4216 uint16_t dir_attr, const uint8_t *data,
4220 struct hwrm_nvm_write_input req = {0};
4221 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4222 rte_iova_t dma_handle;
4225 buf = rte_malloc("nvm_write", data_len, 0);
4229 dma_handle = rte_malloc_virt2iova(buf);
4230 if (dma_handle == RTE_BAD_IOVA) {
4232 "unable to map response address to physical memory\n");
4235 memcpy(buf, data, data_len);
4237 HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4239 req.dir_type = rte_cpu_to_le_16(dir_type);
4240 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4241 req.dir_ext = rte_cpu_to_le_16(dir_ext);
4242 req.dir_attr = rte_cpu_to_le_16(dir_attr);
4243 req.dir_data_length = rte_cpu_to_le_32(data_len);
4244 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4246 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4249 HWRM_CHECK_RESULT();
4256 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4258 uint32_t *count = cbdata;
4260 *count = *count + 1;
4263 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4264 struct bnxt_vnic_info *vnic __rte_unused)
4269 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4273 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4274 &count, bnxt_vnic_count_hwrm_stub);
4279 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4282 struct hwrm_func_vf_vnic_ids_query_input req = {0};
4283 struct hwrm_func_vf_vnic_ids_query_output *resp =
4284 bp->hwrm_cmd_resp_addr;
4287 /* First query all VNIC ids */
4288 HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4290 req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4291 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4292 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4294 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4297 "unable to map VNIC ID table address to physical memory\n");
4300 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4301 HWRM_CHECK_RESULT();
4302 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4310 * This function queries the VNIC IDs for a specified VF. It then calls
4311 * the vnic_cb to update the necessary field in vnic_info with cbdata.
4312 * Then it calls the hwrm_cb function to program this new vnic configuration.
4314 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4315 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4316 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4318 struct bnxt_vnic_info vnic;
4320 int i, num_vnic_ids;
4325 /* First query all VNIC ids */
4326 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4327 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4328 RTE_CACHE_LINE_SIZE);
4329 if (vnic_ids == NULL)
4332 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4333 rte_mem_lock_page(((char *)vnic_ids) + sz);
4335 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4337 if (num_vnic_ids < 0)
4338 return num_vnic_ids;
4340 /* Retrieve VNIC, update bd_stall then update */
4342 for (i = 0; i < num_vnic_ids; i++) {
4343 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4344 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4345 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4348 if (vnic.mru <= 4) /* Indicates unallocated */
4351 vnic_cb(&vnic, cbdata);
4353 rc = hwrm_cb(bp, &vnic);
4363 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4366 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4367 struct hwrm_func_cfg_input req = {0};
4370 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4372 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4373 req.enables |= rte_cpu_to_le_32(
4374 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4375 req.vlan_antispoof_mode = on ?
4376 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4377 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4378 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4380 HWRM_CHECK_RESULT();
4386 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4388 struct bnxt_vnic_info vnic;
4391 int num_vnic_ids, i;
4395 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4396 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4397 RTE_CACHE_LINE_SIZE);
4398 if (vnic_ids == NULL)
4401 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4402 rte_mem_lock_page(((char *)vnic_ids) + sz);
4404 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4410 * Loop through to find the default VNIC ID.
4411 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4412 * by sending the hwrm_func_qcfg command to the firmware.
4414 for (i = 0; i < num_vnic_ids; i++) {
4415 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4416 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4417 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4418 bp->pf->first_vf_id + vf);
4421 if (vnic.func_default) {
4423 return vnic.fw_vnic_id;
4426 /* Could not find a default VNIC. */
4427 PMD_DRV_LOG(ERR, "No default VNIC\n");
4433 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4435 struct bnxt_filter_info *filter)
4438 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4439 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4440 uint32_t enables = 0;
4442 if (filter->fw_em_filter_id != UINT64_MAX)
4443 bnxt_hwrm_clear_em_filter(bp, filter);
4445 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4447 req.flags = rte_cpu_to_le_32(filter->flags);
4449 enables = filter->enables |
4450 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4451 req.dst_id = rte_cpu_to_le_16(dst_id);
4453 if (filter->ip_addr_type) {
4454 req.ip_addr_type = filter->ip_addr_type;
4455 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4458 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4459 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4461 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4462 memcpy(req.src_macaddr, filter->src_macaddr,
4463 RTE_ETHER_ADDR_LEN);
4465 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4466 memcpy(req.dst_macaddr, filter->dst_macaddr,
4467 RTE_ETHER_ADDR_LEN);
4469 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4470 req.ovlan_vid = filter->l2_ovlan;
4472 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4473 req.ivlan_vid = filter->l2_ivlan;
4475 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4476 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4478 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4479 req.ip_protocol = filter->ip_protocol;
4481 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4482 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4484 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4485 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4487 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4488 req.src_port = rte_cpu_to_be_16(filter->src_port);
4490 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4491 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4493 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4494 req.mirror_vnic_id = filter->mirror_vnic_id;
4496 req.enables = rte_cpu_to_le_32(enables);
4498 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4500 HWRM_CHECK_RESULT();
4502 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4508 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4511 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4512 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4514 if (filter->fw_em_filter_id == UINT64_MAX)
4517 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4519 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4521 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4523 HWRM_CHECK_RESULT();
4526 filter->fw_em_filter_id = UINT64_MAX;
4527 filter->fw_l2_filter_id = UINT64_MAX;
4532 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4534 struct bnxt_filter_info *filter)
4537 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4538 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4539 bp->hwrm_cmd_resp_addr;
4540 uint32_t enables = 0;
4542 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4543 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4545 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4547 req.flags = rte_cpu_to_le_32(filter->flags);
4549 enables = filter->enables |
4550 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4551 req.dst_id = rte_cpu_to_le_16(dst_id);
4553 if (filter->ip_addr_type) {
4554 req.ip_addr_type = filter->ip_addr_type;
4556 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4559 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4560 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4562 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4563 memcpy(req.src_macaddr, filter->src_macaddr,
4564 RTE_ETHER_ADDR_LEN);
4566 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4567 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4569 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4570 req.ip_protocol = filter->ip_protocol;
4572 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4573 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4575 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4576 req.src_ipaddr_mask[0] =
4577 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4579 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4580 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4582 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4583 req.dst_ipaddr_mask[0] =
4584 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4586 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4587 req.src_port = rte_cpu_to_le_16(filter->src_port);
4589 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4590 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4592 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4593 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4595 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4596 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4598 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4599 req.mirror_vnic_id = filter->mirror_vnic_id;
4601 req.enables = rte_cpu_to_le_32(enables);
4603 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4605 HWRM_CHECK_RESULT();
4607 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4608 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4614 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4615 struct bnxt_filter_info *filter)
4618 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4619 struct hwrm_cfa_ntuple_filter_free_output *resp =
4620 bp->hwrm_cmd_resp_addr;
4622 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4625 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4627 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4629 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4631 HWRM_CHECK_RESULT();
4634 filter->fw_ntuple_filter_id = UINT64_MAX;
4640 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4642 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4643 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4644 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4645 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4646 uint16_t *ring_tbl = vnic->rss_table;
4647 int nr_ctxs = vnic->num_lb_ctxts;
4648 int max_rings = bp->rx_nr_rings;
4652 for (i = 0, k = 0; i < nr_ctxs; i++) {
4653 struct bnxt_rx_ring_info *rxr;
4654 struct bnxt_cp_ring_info *cpr;
4656 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4658 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4659 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4660 req.hash_mode_flags = vnic->hash_mode;
4662 req.ring_grp_tbl_addr =
4663 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4664 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4665 2 * sizeof(*ring_tbl));
4666 req.hash_key_tbl_addr =
4667 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4669 req.ring_table_pair_index = i;
4670 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4672 for (j = 0; j < 64; j++) {
4675 /* Find next active ring. */
4676 for (cnt = 0; cnt < max_rings; cnt++) {
4677 if (rx_queue_state[k] !=
4678 RTE_ETH_QUEUE_STATE_STOPPED)
4680 if (++k == max_rings)
4684 /* Return if no rings are active. */
4685 if (cnt == max_rings) {
4690 /* Add rx/cp ring pair to RSS table. */
4691 rxr = rxqs[k]->rx_ring;
4692 cpr = rxqs[k]->cp_ring;
4694 ring_id = rxr->rx_ring_struct->fw_ring_id;
4695 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4696 ring_id = cpr->cp_ring_struct->fw_ring_id;
4697 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4699 if (++k == max_rings)
4702 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4705 HWRM_CHECK_RESULT();
4712 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4714 unsigned int rss_idx, fw_idx, i;
4716 if (!(vnic->rss_table && vnic->hash_type))
4719 if (BNXT_CHIP_THOR(bp))
4720 return bnxt_vnic_rss_configure_thor(bp, vnic);
4722 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4725 if (vnic->rss_table && vnic->hash_type) {
4727 * Fill the RSS hash & redirection table with
4728 * ring group ids for all VNICs
4730 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4731 rss_idx++, fw_idx++) {
4732 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4733 fw_idx %= bp->rx_cp_nr_rings;
4734 if (vnic->fw_grp_ids[fw_idx] !=
4739 if (i == bp->rx_cp_nr_rings)
4741 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4743 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4749 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4750 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4754 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4756 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4757 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4759 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4760 req->num_cmpl_dma_aggr_during_int =
4761 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4763 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4765 /* min timer set to 1/2 of interrupt timer */
4766 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4768 /* buf timer set to 1/4 of interrupt timer */
4769 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4771 req->cmpl_aggr_dma_tmr_during_int =
4772 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4774 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4775 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4776 req->flags = rte_cpu_to_le_16(flags);
4779 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4780 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4782 struct hwrm_ring_aggint_qcaps_input req = {0};
4783 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4788 HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4789 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4790 HWRM_CHECK_RESULT();
4792 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4793 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4795 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4796 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4797 agg_req->flags = rte_cpu_to_le_16(flags);
4799 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4800 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4801 agg_req->enables = rte_cpu_to_le_32(enables);
4807 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4808 struct bnxt_coal *coal, uint16_t ring_id)
4810 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4811 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4812 bp->hwrm_cmd_resp_addr;
4815 /* Set ring coalesce parameters only for 100G NICs */
4816 if (BNXT_CHIP_THOR(bp)) {
4817 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4819 } else if (bnxt_stratus_device(bp)) {
4820 bnxt_hwrm_set_coal_params(coal, &req);
4826 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4828 req.ring_id = rte_cpu_to_le_16(ring_id);
4829 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4830 HWRM_CHECK_RESULT();
4835 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4836 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4838 struct hwrm_func_backing_store_qcaps_input req = {0};
4839 struct hwrm_func_backing_store_qcaps_output *resp =
4840 bp->hwrm_cmd_resp_addr;
4841 struct bnxt_ctx_pg_info *ctx_pg;
4842 struct bnxt_ctx_mem_info *ctx;
4843 int total_alloc_len;
4844 int rc, i, tqm_rings;
4846 if (!BNXT_CHIP_THOR(bp) ||
4847 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4852 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4853 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4854 HWRM_CHECK_RESULT_SILENT();
4856 total_alloc_len = sizeof(*ctx);
4857 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4858 RTE_CACHE_LINE_SIZE);
4864 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4865 ctx->qp_min_qp1_entries =
4866 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4867 ctx->qp_max_l2_entries =
4868 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4869 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4870 ctx->srq_max_l2_entries =
4871 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4872 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4873 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4874 ctx->cq_max_l2_entries =
4875 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4876 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4877 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4878 ctx->vnic_max_vnic_entries =
4879 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4880 ctx->vnic_max_ring_table_entries =
4881 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4882 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4883 ctx->stat_max_entries =
4884 rte_le_to_cpu_32(resp->stat_max_entries);
4885 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4886 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4887 ctx->tqm_min_entries_per_ring =
4888 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4889 ctx->tqm_max_entries_per_ring =
4890 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4891 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4892 if (!ctx->tqm_entries_multiple)
4893 ctx->tqm_entries_multiple = 1;
4894 ctx->mrav_max_entries =
4895 rte_le_to_cpu_32(resp->mrav_max_entries);
4896 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4897 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4898 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4899 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
4901 if (!ctx->tqm_fp_rings_count)
4902 ctx->tqm_fp_rings_count = bp->max_q;
4904 tqm_rings = ctx->tqm_fp_rings_count + 1;
4906 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4907 sizeof(*ctx_pg) * tqm_rings,
4908 RTE_CACHE_LINE_SIZE);
4913 for (i = 0; i < tqm_rings; i++, ctx_pg++)
4914 ctx->tqm_mem[i] = ctx_pg;
4922 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4924 struct hwrm_func_backing_store_cfg_input req = {0};
4925 struct hwrm_func_backing_store_cfg_output *resp =
4926 bp->hwrm_cmd_resp_addr;
4927 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4928 struct bnxt_ctx_pg_info *ctx_pg;
4929 uint32_t *num_entries;
4938 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4939 req.enables = rte_cpu_to_le_32(enables);
4941 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4942 ctx_pg = &ctx->qp_mem;
4943 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4944 req.qp_num_qp1_entries =
4945 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4946 req.qp_num_l2_entries =
4947 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4948 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4949 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4950 &req.qpc_pg_size_qpc_lvl,
4954 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4955 ctx_pg = &ctx->srq_mem;
4956 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4957 req.srq_num_l2_entries =
4958 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4959 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4960 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4961 &req.srq_pg_size_srq_lvl,
4965 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4966 ctx_pg = &ctx->cq_mem;
4967 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4968 req.cq_num_l2_entries =
4969 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4970 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4971 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4972 &req.cq_pg_size_cq_lvl,
4976 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4977 ctx_pg = &ctx->vnic_mem;
4978 req.vnic_num_vnic_entries =
4979 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4980 req.vnic_num_ring_table_entries =
4981 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4982 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4983 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4984 &req.vnic_pg_size_vnic_lvl,
4985 &req.vnic_page_dir);
4988 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4989 ctx_pg = &ctx->stat_mem;
4990 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4991 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4992 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4993 &req.stat_pg_size_stat_lvl,
4994 &req.stat_page_dir);
4997 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4998 num_entries = &req.tqm_sp_num_entries;
4999 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5000 pg_dir = &req.tqm_sp_page_dir;
5001 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5002 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5003 if (!(enables & ena))
5006 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5008 ctx_pg = ctx->tqm_mem[i];
5009 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5010 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5013 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5014 HWRM_CHECK_RESULT();
5020 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5022 struct hwrm_port_qstats_ext_input req = {0};
5023 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5024 struct bnxt_pf_info *pf = bp->pf;
5027 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5028 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5031 HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5033 req.port_id = rte_cpu_to_le_16(pf->port_id);
5034 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5035 req.tx_stat_host_addr =
5036 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5038 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5040 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5041 req.rx_stat_host_addr =
5042 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5044 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5046 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5049 bp->fw_rx_port_stats_ext_size = 0;
5050 bp->fw_tx_port_stats_ext_size = 0;
5052 bp->fw_rx_port_stats_ext_size =
5053 rte_le_to_cpu_16(resp->rx_stat_size);
5054 bp->fw_tx_port_stats_ext_size =
5055 rte_le_to_cpu_16(resp->tx_stat_size);
5058 HWRM_CHECK_RESULT();
5065 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5067 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5068 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5069 bp->hwrm_cmd_resp_addr;
5072 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5073 req.tunnel_type = type;
5074 req.dest_fid = bp->fw_fid;
5075 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5076 HWRM_CHECK_RESULT();
5084 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5086 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5087 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5088 bp->hwrm_cmd_resp_addr;
5091 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5092 req.tunnel_type = type;
5093 req.dest_fid = bp->fw_fid;
5094 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5095 HWRM_CHECK_RESULT();
5102 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5104 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5105 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5106 bp->hwrm_cmd_resp_addr;
5109 HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5110 req.src_fid = bp->fw_fid;
5111 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5112 HWRM_CHECK_RESULT();
5115 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5122 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5125 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5126 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5127 bp->hwrm_cmd_resp_addr;
5130 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5131 req.src_fid = bp->fw_fid;
5132 req.tunnel_type = tun_type;
5133 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5134 HWRM_CHECK_RESULT();
5137 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5139 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5146 int bnxt_hwrm_set_mac(struct bnxt *bp)
5148 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5149 struct hwrm_func_vf_cfg_input req = {0};
5155 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5158 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5159 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5161 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5163 HWRM_CHECK_RESULT();
5170 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5172 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5173 struct hwrm_func_drv_if_change_input req = {0};
5177 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5180 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5181 * If we issue FUNC_DRV_IF_CHANGE with flags down before
5182 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5184 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5187 HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5191 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5193 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5195 HWRM_CHECK_RESULT();
5196 flags = rte_le_to_cpu_32(resp->flags);
5202 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5203 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5204 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5210 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5212 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5213 struct bnxt_error_recovery_info *info = bp->recovery_info;
5214 struct hwrm_error_recovery_qcfg_input req = {0};
5219 /* Older FW does not have error recovery support */
5220 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5223 HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5225 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5227 HWRM_CHECK_RESULT();
5229 flags = rte_le_to_cpu_32(resp->flags);
5230 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5231 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5232 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5233 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5235 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5236 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5241 /* FW returned values are in units of 100msec */
5242 info->driver_polling_freq =
5243 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5244 info->master_func_wait_period =
5245 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5246 info->normal_func_wait_period =
5247 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5248 info->master_func_wait_period_after_reset =
5249 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5250 info->max_bailout_time_after_reset =
5251 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5252 info->status_regs[BNXT_FW_STATUS_REG] =
5253 rte_le_to_cpu_32(resp->fw_health_status_reg);
5254 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5255 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5256 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5257 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5258 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5259 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5260 info->reg_array_cnt =
5261 rte_le_to_cpu_32(resp->reg_array_cnt);
5263 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5268 for (i = 0; i < info->reg_array_cnt; i++) {
5269 info->reset_reg[i] =
5270 rte_le_to_cpu_32(resp->reset_reg[i]);
5271 info->reset_reg_val[i] =
5272 rte_le_to_cpu_32(resp->reset_reg_val[i]);
5273 info->delay_after_reset[i] =
5274 resp->delay_after_reset[i];
5279 /* Map the FW status registers */
5281 rc = bnxt_map_fw_health_status_regs(bp);
5284 rte_free(bp->recovery_info);
5285 bp->recovery_info = NULL;
5290 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5292 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5293 struct hwrm_fw_reset_input req = {0};
5299 HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5301 req.embedded_proc_type =
5302 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5303 req.selfrst_status =
5304 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5305 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5307 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5310 HWRM_CHECK_RESULT();
5316 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5318 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5319 struct hwrm_port_ts_query_input req = {0};
5320 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5327 HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5330 case BNXT_PTP_FLAGS_PATH_TX:
5331 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5333 case BNXT_PTP_FLAGS_PATH_RX:
5334 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5336 case BNXT_PTP_FLAGS_CURRENT_TIME:
5337 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5341 req.flags = rte_cpu_to_le_32(flags);
5342 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5344 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5346 HWRM_CHECK_RESULT();
5349 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5351 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5358 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5362 struct hwrm_cfa_counter_qcaps_input req = {0};
5363 struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5365 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5367 "Not a PF or trusted VF. Command not supported\n");
5371 HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5372 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5373 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5375 HWRM_CHECK_RESULT();
5377 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5383 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5386 struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5387 struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5389 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5391 "Not a PF or trusted VF. Command not supported\n");
5395 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5397 req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5398 req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5399 req.page_dir = rte_cpu_to_le_64(dma_addr);
5401 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5403 HWRM_CHECK_RESULT();
5405 *ctx_id = rte_le_to_cpu_16(resp->ctx_id);
5406 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5413 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5416 struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5417 struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5419 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5421 "Not a PF or trusted VF. Command not supported\n");
5425 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5427 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5429 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5431 HWRM_CHECK_RESULT();
5437 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5438 uint16_t cntr, uint16_t ctx_id,
5439 uint32_t num_entries, bool enable)
5441 struct hwrm_cfa_counter_cfg_input req = {0};
5442 struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5446 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5448 "Not a PF or trusted VF. Command not supported\n");
5452 HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5454 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5455 req.counter_type = rte_cpu_to_le_16(cntr);
5456 flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5457 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5458 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5459 if (dir == BNXT_DIR_RX)
5460 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5461 else if (dir == BNXT_DIR_TX)
5462 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5463 req.flags = rte_cpu_to_le_16(flags);
5464 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5465 req.num_entries = rte_cpu_to_le_32(num_entries);
5467 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5468 HWRM_CHECK_RESULT();
5474 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5475 enum bnxt_flow_dir dir,
5477 uint16_t num_entries)
5479 struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5480 struct hwrm_cfa_counter_qstats_input req = {0};
5481 uint16_t flow_ctx_id = 0;
5485 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5487 "Not a PF or trusted VF. Command not supported\n");
5491 if (dir == BNXT_DIR_RX) {
5492 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5493 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5494 } else if (dir == BNXT_DIR_TX) {
5495 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5496 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5499 HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5500 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5501 req.counter_type = rte_cpu_to_le_16(cntr);
5502 req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5503 req.num_entries = rte_cpu_to_le_16(num_entries);
5504 req.flags = rte_cpu_to_le_16(flags);
5505 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5507 HWRM_CHECK_RESULT();
5513 int bnxt_hwrm_cfa_vfr_alloc(struct bnxt *bp, uint16_t vf_idx)
5515 struct hwrm_cfa_vfr_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5516 struct hwrm_cfa_vfr_alloc_input req = {0};
5519 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5521 "Not a PF or trusted VF. Command not supported\n");
5525 HWRM_PREP(&req, HWRM_CFA_VFR_ALLOC, BNXT_USE_CHIMP_MB);
5526 req.vf_id = rte_cpu_to_le_16(vf_idx);
5527 snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
5528 bp->eth_dev->data->name, vf_idx);
5530 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5531 HWRM_CHECK_RESULT();
5534 PMD_DRV_LOG(DEBUG, "VFR %d allocated\n", vf_idx);
5538 int bnxt_hwrm_cfa_vfr_free(struct bnxt *bp, uint16_t vf_idx)
5540 struct hwrm_cfa_vfr_free_output *resp = bp->hwrm_cmd_resp_addr;
5541 struct hwrm_cfa_vfr_free_input req = {0};
5544 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5546 "Not a PF or trusted VF. Command not supported\n");
5550 HWRM_PREP(&req, HWRM_CFA_VFR_FREE, BNXT_USE_CHIMP_MB);
5551 req.vf_id = rte_cpu_to_le_16(vf_idx);
5552 snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
5553 bp->eth_dev->data->name, vf_idx);
5555 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5556 HWRM_CHECK_RESULT();
5558 PMD_DRV_LOG(DEBUG, "VFR %d freed\n", vf_idx);