1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(void *) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
67 if (rmem->nr_pages > 1) {
69 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
71 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
76 * HWRM Functions (sent to HWRM)
77 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
78 * HWRM command times out, or a negative error code if the HWRM
79 * command was failed by the FW.
82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
83 uint32_t msg_len, bool use_kong_mb)
86 struct input *req = msg;
87 struct output *resp = bp->hwrm_cmd_resp_addr;
91 uint16_t max_req_len = bp->max_req_len;
92 struct hwrm_short_input short_input = { 0 };
93 uint16_t bar_offset = use_kong_mb ?
94 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
95 uint16_t mb_trigger_offset = use_kong_mb ?
96 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
99 /* Do not send HWRM commands to firmware in error state */
100 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
103 /* For VER_GET command, set timeout as 50ms */
104 if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
105 timeout = HWRM_CMD_TIMEOUT;
107 timeout = bp->hwrm_cmd_timeout;
109 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
110 msg_len > bp->max_req_len) {
111 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
113 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
114 memcpy(short_cmd_req, req, msg_len);
116 short_input.req_type = rte_cpu_to_le_16(req->req_type);
117 short_input.signature = rte_cpu_to_le_16(
118 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
119 short_input.size = rte_cpu_to_le_16(msg_len);
120 short_input.req_addr =
121 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
123 data = (uint32_t *)&short_input;
124 msg_len = sizeof(short_input);
126 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
129 /* Write request msg to hwrm channel */
130 for (i = 0; i < msg_len; i += 4) {
131 bar = (uint8_t *)bp->bar0 + bar_offset + i;
132 rte_write32(*data, bar);
136 /* Zero the rest of the request space */
137 for (; i < max_req_len; i += 4) {
138 bar = (uint8_t *)bp->bar0 + bar_offset + i;
142 /* Ring channel doorbell */
143 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
146 * Make sure the channel doorbell ring command complete before
147 * reading the response to avoid getting stale or invalid
152 /* Poll for the valid bit */
153 for (i = 0; i < timeout; i++) {
154 /* Sanity check on the resp->resp_len */
156 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
157 /* Last byte of resp contains the valid key */
158 valid = (uint8_t *)resp + resp->resp_len - 1;
159 if (*valid == HWRM_RESP_VALID_KEY)
166 /* Suppress VER_GET timeout messages during reset recovery */
167 if (bp->flags & BNXT_FLAG_FW_RESET &&
168 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
171 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
179 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
180 * spinlock, and does initial processing.
182 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
183 * releases the spinlock only if it returns. If the regular int return codes
184 * are not used by the function, HWRM_CHECK_RESULT() should not be used
185 * directly, rather it should be copied and modified to suit the function.
187 * HWRM_UNLOCK() must be called after all response processing is completed.
189 #define HWRM_PREP(req, type, kong) do { \
190 rte_spinlock_lock(&bp->hwrm_lock); \
191 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
192 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
193 req.cmpl_ring = rte_cpu_to_le_16(-1); \
194 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
195 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
196 req.target_id = rte_cpu_to_le_16(0xffff); \
197 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
200 #define HWRM_CHECK_RESULT_SILENT() do {\
202 rte_spinlock_unlock(&bp->hwrm_lock); \
205 if (resp->error_code) { \
206 rc = rte_le_to_cpu_16(resp->error_code); \
207 rte_spinlock_unlock(&bp->hwrm_lock); \
212 #define HWRM_CHECK_RESULT() do {\
214 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
215 rte_spinlock_unlock(&bp->hwrm_lock); \
216 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
218 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
220 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
222 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
228 if (resp->error_code) { \
229 rc = rte_le_to_cpu_16(resp->error_code); \
230 if (resp->resp_len >= 16) { \
231 struct hwrm_err_output *tmp_hwrm_err_op = \
234 "error %d:%d:%08x:%04x\n", \
235 rc, tmp_hwrm_err_op->cmd_err, \
237 tmp_hwrm_err_op->opaque_0), \
239 tmp_hwrm_err_op->opaque_1)); \
241 PMD_DRV_LOG(ERR, "error %d\n", rc); \
243 rte_spinlock_unlock(&bp->hwrm_lock); \
244 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
246 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
248 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
250 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
258 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
260 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
263 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
264 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
266 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
267 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
270 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
278 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
279 struct bnxt_vnic_info *vnic,
281 struct bnxt_vlan_table_entry *vlan_table)
284 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
285 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
288 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
291 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
292 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
294 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
295 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
296 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
297 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
299 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
300 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
302 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
303 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
304 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
305 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
306 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
307 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
310 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
311 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
312 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
313 rte_mem_virt2iova(vlan_table));
314 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
316 req.mask = rte_cpu_to_le_32(mask);
318 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
326 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
328 struct bnxt_vlan_antispoof_table_entry *vlan_table)
331 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
332 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
333 bp->hwrm_cmd_resp_addr;
336 * Older HWRM versions did not support this command, and the set_rx_mask
337 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
338 * removed from set_rx_mask call, and this command was added.
340 * This command is also present from 1.7.8.11 and higher,
343 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
344 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
345 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
350 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
351 req.fid = rte_cpu_to_le_16(fid);
353 req.vlan_tag_mask_tbl_addr =
354 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
355 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
365 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
366 struct bnxt_filter_info *filter)
369 struct bnxt_filter_info *l2_filter = filter;
370 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
371 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
373 if (filter->fw_l2_filter_id == UINT64_MAX)
376 if (filter->matching_l2_fltr_ptr)
377 l2_filter = filter->matching_l2_fltr_ptr;
379 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
380 filter, l2_filter, l2_filter->l2_ref_cnt);
382 if (l2_filter->l2_ref_cnt > 0)
383 l2_filter->l2_ref_cnt--;
385 if (l2_filter->l2_ref_cnt > 0)
388 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
390 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
392 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
397 filter->fw_l2_filter_id = UINT64_MAX;
402 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
404 struct bnxt_filter_info *filter)
407 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
408 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
409 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
410 const struct rte_eth_vmdq_rx_conf *conf =
411 &dev_conf->rx_adv_conf.vmdq_rx_conf;
412 uint32_t enables = 0;
413 uint16_t j = dst_id - 1;
415 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
416 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
417 conf->pool_map[j].pools & (1UL << j)) {
419 "Add vlan %u to vmdq pool %u\n",
420 conf->pool_map[j].vlan_id, j);
422 filter->l2_ivlan = conf->pool_map[j].vlan_id;
424 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
425 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
428 if (filter->fw_l2_filter_id != UINT64_MAX)
429 bnxt_hwrm_clear_l2_filter(bp, filter);
431 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
433 req.flags = rte_cpu_to_le_32(filter->flags);
435 enables = filter->enables |
436 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
437 req.dst_id = rte_cpu_to_le_16(dst_id);
440 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
441 memcpy(req.l2_addr, filter->l2_addr,
444 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
445 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
448 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
449 req.l2_ovlan = filter->l2_ovlan;
451 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
452 req.l2_ivlan = filter->l2_ivlan;
454 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
455 req.l2_ovlan_mask = filter->l2_ovlan_mask;
457 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
458 req.l2_ivlan_mask = filter->l2_ivlan_mask;
459 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
460 req.src_id = rte_cpu_to_le_32(filter->src_id);
461 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
462 req.src_type = filter->src_type;
463 if (filter->pri_hint) {
464 req.pri_hint = filter->pri_hint;
465 req.l2_filter_id_hint =
466 rte_cpu_to_le_64(filter->l2_filter_id_hint);
469 req.enables = rte_cpu_to_le_32(enables);
471 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
475 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
481 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
483 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
484 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
491 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
494 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
497 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
498 if (ptp->tx_tstamp_en)
499 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
502 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
503 req.flags = rte_cpu_to_le_32(flags);
504 req.enables = rte_cpu_to_le_32
505 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
506 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
508 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
514 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
517 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
518 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
519 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
524 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
526 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
528 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
532 if (!BNXT_CHIP_THOR(bp) &&
533 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
536 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
537 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
539 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
543 if (!BNXT_CHIP_THOR(bp)) {
544 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
545 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
546 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
547 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
548 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
549 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
550 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
551 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
552 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
553 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
554 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
555 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
556 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
557 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
558 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
559 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
560 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
561 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
570 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
573 struct hwrm_func_qcaps_input req = {.req_type = 0 };
574 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
575 uint16_t new_max_vfs;
579 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
581 req.fid = rte_cpu_to_le_16(0xffff);
583 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
587 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
588 flags = rte_le_to_cpu_32(resp->flags);
590 bp->pf.port_id = resp->port_id;
591 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
592 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
593 new_max_vfs = bp->pdev->max_vfs;
594 if (new_max_vfs != bp->pf.max_vfs) {
596 rte_free(bp->pf.vf_info);
597 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
598 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
599 bp->pf.max_vfs = new_max_vfs;
600 for (i = 0; i < new_max_vfs; i++) {
601 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
602 bp->pf.vf_info[i].vlan_table =
603 rte_zmalloc("VF VLAN table",
606 if (bp->pf.vf_info[i].vlan_table == NULL)
608 "Fail to alloc VLAN table for VF %d\n",
612 bp->pf.vf_info[i].vlan_table);
613 bp->pf.vf_info[i].vlan_as_table =
614 rte_zmalloc("VF VLAN AS table",
617 if (bp->pf.vf_info[i].vlan_as_table == NULL)
619 "Alloc VLAN AS table for VF %d fail\n",
623 bp->pf.vf_info[i].vlan_as_table);
624 STAILQ_INIT(&bp->pf.vf_info[i].filter);
629 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
630 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
631 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
632 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
633 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
634 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
635 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
636 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
637 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
638 if (!BNXT_CHIP_THOR(bp))
639 bp->max_l2_ctx += bp->max_rx_em_flows;
640 /* TODO: For now, do not support VMDq/RFS on VFs. */
645 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
649 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
651 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
652 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
653 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
654 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
656 bnxt_hwrm_ptp_qcfg(bp);
660 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
661 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
663 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
664 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
665 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
667 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
670 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
671 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
673 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
680 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
684 rc = __bnxt_hwrm_func_qcaps(bp);
685 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
686 rc = bnxt_alloc_ctx_mem(bp);
690 rc = bnxt_hwrm_func_resc_qcaps(bp);
692 bp->flags |= BNXT_FLAG_NEW_RM;
698 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
699 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
702 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
703 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
705 HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
707 req.target_id = rte_cpu_to_le_16(0xffff);
709 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
713 if (rte_le_to_cpu_32(resp->flags) &
714 HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
715 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
716 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
719 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
726 int bnxt_hwrm_func_reset(struct bnxt *bp)
729 struct hwrm_func_reset_input req = {.req_type = 0 };
730 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
732 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
734 req.enables = rte_cpu_to_le_32(0);
736 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
744 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
748 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
749 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
751 if (bp->flags & BNXT_FLAG_REGISTERED)
754 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
755 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
756 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
758 /* PFs and trusted VFs should indicate the support of the
759 * Master capability on non Stingray platform
761 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
762 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
764 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
765 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
766 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
767 req.ver_maj = RTE_VER_YEAR;
768 req.ver_min = RTE_VER_MONTH;
769 req.ver_upd = RTE_VER_MINOR;
772 req.enables |= rte_cpu_to_le_32(
773 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
774 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
775 RTE_MIN(sizeof(req.vf_req_fwd),
776 sizeof(bp->pf.vf_req_fwd)));
779 * PF can sniff HWRM API issued by VF. This can be set up by
780 * linux driver and inherited by the DPDK PF driver. Clear
781 * this HWRM sniffer list in FW because DPDK PF driver does
784 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
787 req.flags = rte_cpu_to_le_32(flags);
789 req.async_event_fwd[0] |=
790 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
791 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
792 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
793 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
794 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
795 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
796 req.async_event_fwd[0] |=
797 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
798 req.async_event_fwd[1] |=
799 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
800 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
802 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
806 flags = rte_le_to_cpu_32(resp->flags);
807 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
808 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
812 bp->flags |= BNXT_FLAG_REGISTERED;
817 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
819 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
822 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
825 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
830 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
831 struct hwrm_func_vf_cfg_input req = {0};
833 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
835 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
836 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
837 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
838 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
839 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
841 if (BNXT_HAS_RING_GRPS(bp)) {
842 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
843 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
846 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
847 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
848 AGG_RING_MULTIPLIER);
849 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
850 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
852 BNXT_NUM_ASYNC_CPR(bp));
853 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
854 if (bp->vf_resv_strategy ==
855 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
856 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
857 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
858 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
859 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
860 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
861 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
862 } else if (bp->vf_resv_strategy ==
863 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
864 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
865 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
869 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
870 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
871 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
872 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
873 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
874 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
876 if (test && BNXT_HAS_RING_GRPS(bp))
877 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
879 req.flags = rte_cpu_to_le_32(flags);
880 req.enables |= rte_cpu_to_le_32(enables);
882 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
885 HWRM_CHECK_RESULT_SILENT();
893 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
896 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
897 struct hwrm_func_resource_qcaps_input req = {0};
899 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
900 req.fid = rte_cpu_to_le_16(0xffff);
902 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
907 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
908 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
909 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
910 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
911 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
912 /* func_resource_qcaps does not return max_rx_em_flows.
913 * So use the value provided by func_qcaps.
915 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
916 if (!BNXT_CHIP_THOR(bp))
917 bp->max_l2_ctx += bp->max_rx_em_flows;
918 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
919 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
921 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
922 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
923 if (bp->vf_resv_strategy >
924 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
925 bp->vf_resv_strategy =
926 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
932 int bnxt_hwrm_ver_get(struct bnxt *bp)
935 struct hwrm_ver_get_input req = {.req_type = 0 };
936 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
938 uint16_t max_resp_len;
939 char type[RTE_MEMZONE_NAMESIZE];
940 uint32_t dev_caps_cfg;
942 bp->max_req_len = HWRM_MAX_REQ_LEN;
943 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
945 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
946 req.hwrm_intf_min = HWRM_VERSION_MINOR;
947 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
949 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
951 if (bp->flags & BNXT_FLAG_FW_RESET)
952 HWRM_CHECK_RESULT_SILENT();
956 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
957 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
958 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
959 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
960 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
961 (resp->hwrm_fw_min_8b << 16) |
962 (resp->hwrm_fw_bld_8b << 8) |
963 resp->hwrm_fw_rsvd_8b;
964 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
965 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
967 fw_version = resp->hwrm_intf_maj_8b << 16;
968 fw_version |= resp->hwrm_intf_min_8b << 8;
969 fw_version |= resp->hwrm_intf_upd_8b;
970 bp->hwrm_spec_code = fw_version;
972 /* def_req_timeout value is in milliseconds */
973 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
974 /* convert timeout to usec */
975 bp->hwrm_cmd_timeout *= 1000;
976 if (!bp->hwrm_cmd_timeout)
977 bp->hwrm_cmd_timeout = HWRM_CMD_TIMEOUT;
979 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
980 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
985 if (bp->max_req_len > resp->max_req_win_len) {
986 PMD_DRV_LOG(ERR, "Unsupported request length\n");
989 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
990 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
991 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
992 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
994 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
995 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
997 if (bp->max_resp_len != max_resp_len) {
998 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
999 bp->pdev->addr.domain, bp->pdev->addr.bus,
1000 bp->pdev->addr.devid, bp->pdev->addr.function);
1002 rte_free(bp->hwrm_cmd_resp_addr);
1004 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1005 if (bp->hwrm_cmd_resp_addr == NULL) {
1009 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1010 bp->hwrm_cmd_resp_dma_addr =
1011 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1012 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1014 "Unable to map response buffer to physical memory.\n");
1018 bp->max_resp_len = max_resp_len;
1022 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1024 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1025 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1026 bp->flags |= BNXT_FLAG_SHORT_CMD;
1029 if (((dev_caps_cfg &
1030 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1032 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1033 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1034 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1035 bp->pdev->addr.domain, bp->pdev->addr.bus,
1036 bp->pdev->addr.devid, bp->pdev->addr.function);
1038 rte_free(bp->hwrm_short_cmd_req_addr);
1040 bp->hwrm_short_cmd_req_addr =
1041 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1042 if (bp->hwrm_short_cmd_req_addr == NULL) {
1046 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1047 bp->hwrm_short_cmd_req_dma_addr =
1048 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1049 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1050 rte_free(bp->hwrm_short_cmd_req_addr);
1052 "Unable to map buffer to physical memory.\n");
1058 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1059 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1060 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1063 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1064 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1066 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1067 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1068 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1076 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1079 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1080 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1082 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1085 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1088 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1090 HWRM_CHECK_RESULT();
1096 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1099 struct hwrm_port_phy_cfg_input req = {0};
1100 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1101 uint32_t enables = 0;
1103 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1105 if (conf->link_up) {
1106 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1107 if (bp->link_info.auto_mode && conf->link_speed) {
1108 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1109 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1112 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1113 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1114 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1116 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1117 * any auto mode, even "none".
1119 if (!conf->link_speed) {
1120 /* No speeds specified. Enable AutoNeg - all speeds */
1122 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1124 /* AutoNeg - Advertise speeds specified. */
1125 if (conf->auto_link_speed_mask &&
1126 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1128 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1129 req.auto_link_speed_mask =
1130 conf->auto_link_speed_mask;
1132 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1135 req.auto_duplex = conf->duplex;
1136 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1137 req.auto_pause = conf->auto_pause;
1138 req.force_pause = conf->force_pause;
1139 /* Set force_pause if there is no auto or if there is a force */
1140 if (req.auto_pause && !req.force_pause)
1141 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1143 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1145 req.enables = rte_cpu_to_le_32(enables);
1148 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1149 PMD_DRV_LOG(INFO, "Force Link Down\n");
1152 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1154 HWRM_CHECK_RESULT();
1160 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1161 struct bnxt_link_info *link_info)
1164 struct hwrm_port_phy_qcfg_input req = {0};
1165 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1167 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1169 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1171 HWRM_CHECK_RESULT();
1173 link_info->phy_link_status = resp->link;
1174 link_info->link_up =
1175 (link_info->phy_link_status ==
1176 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1177 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1178 link_info->duplex = resp->duplex_cfg;
1179 link_info->pause = resp->pause;
1180 link_info->auto_pause = resp->auto_pause;
1181 link_info->force_pause = resp->force_pause;
1182 link_info->auto_mode = resp->auto_mode;
1183 link_info->phy_type = resp->phy_type;
1184 link_info->media_type = resp->media_type;
1186 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1187 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1188 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1189 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1190 link_info->phy_ver[0] = resp->phy_maj;
1191 link_info->phy_ver[1] = resp->phy_min;
1192 link_info->phy_ver[2] = resp->phy_bld;
1196 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1197 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1198 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1199 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1200 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1201 link_info->auto_link_speed_mask);
1202 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1203 link_info->force_link_speed);
1208 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1211 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1212 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1213 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1217 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1219 req.flags = rte_cpu_to_le_32(dir);
1220 /* HWRM Version >= 1.9.1 */
1221 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1223 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1224 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1226 HWRM_CHECK_RESULT();
1228 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1229 GET_TX_QUEUE_INFO(0);
1230 GET_TX_QUEUE_INFO(1);
1231 GET_TX_QUEUE_INFO(2);
1232 GET_TX_QUEUE_INFO(3);
1233 GET_TX_QUEUE_INFO(4);
1234 GET_TX_QUEUE_INFO(5);
1235 GET_TX_QUEUE_INFO(6);
1236 GET_TX_QUEUE_INFO(7);
1238 GET_RX_QUEUE_INFO(0);
1239 GET_RX_QUEUE_INFO(1);
1240 GET_RX_QUEUE_INFO(2);
1241 GET_RX_QUEUE_INFO(3);
1242 GET_RX_QUEUE_INFO(4);
1243 GET_RX_QUEUE_INFO(5);
1244 GET_RX_QUEUE_INFO(6);
1245 GET_RX_QUEUE_INFO(7);
1250 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1253 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1254 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1258 /* iterate and find the COSq profile to use for Tx */
1259 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1260 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1261 if (bp->tx_cos_queue[i].id != 0xff)
1262 bp->tx_cosq_id[j++] =
1263 bp->tx_cos_queue[i].id;
1266 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1267 if (bp->tx_cos_queue[i].profile ==
1268 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1270 bp->tx_cos_queue[i].id;
1277 bp->max_tc = resp->max_configurable_queues;
1278 bp->max_lltc = resp->max_configurable_lossless_queues;
1279 if (bp->max_tc > BNXT_MAX_QUEUE)
1280 bp->max_tc = BNXT_MAX_QUEUE;
1281 bp->max_q = bp->max_tc;
1283 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1284 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1292 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1293 struct bnxt_ring *ring,
1294 uint32_t ring_type, uint32_t map_index,
1295 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1296 uint16_t tx_cosq_id)
1299 uint32_t enables = 0;
1300 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1301 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1302 struct rte_mempool *mb_pool;
1303 uint16_t rx_buf_size;
1305 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1307 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1308 req.fbo = rte_cpu_to_le_32(0);
1309 /* Association of ring index with doorbell index */
1310 req.logical_id = rte_cpu_to_le_16(map_index);
1311 req.length = rte_cpu_to_le_32(ring->ring_size);
1313 switch (ring_type) {
1314 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1315 req.ring_type = ring_type;
1316 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1317 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1318 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1319 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1321 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1323 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1324 req.ring_type = ring_type;
1325 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1326 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1327 if (BNXT_CHIP_THOR(bp)) {
1328 mb_pool = bp->rx_queues[0]->mb_pool;
1329 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1330 RTE_PKTMBUF_HEADROOM;
1331 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1332 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1334 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1336 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1338 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1340 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1341 req.ring_type = ring_type;
1342 if (BNXT_HAS_NQ(bp)) {
1343 /* Association of cp ring with nq */
1344 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1346 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1348 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1350 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1351 req.ring_type = ring_type;
1352 req.page_size = BNXT_PAGE_SHFT;
1353 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1355 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1356 req.ring_type = ring_type;
1357 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1359 mb_pool = bp->rx_queues[0]->mb_pool;
1360 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1361 RTE_PKTMBUF_HEADROOM;
1362 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1363 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1365 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1366 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1367 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1368 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1371 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1376 req.enables = rte_cpu_to_le_32(enables);
1378 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1380 if (rc || resp->error_code) {
1381 if (rc == 0 && resp->error_code)
1382 rc = rte_le_to_cpu_16(resp->error_code);
1383 switch (ring_type) {
1384 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1386 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1389 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1391 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1394 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1396 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1400 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1402 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1405 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1407 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1411 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1417 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1422 int bnxt_hwrm_ring_free(struct bnxt *bp,
1423 struct bnxt_ring *ring, uint32_t ring_type)
1426 struct hwrm_ring_free_input req = {.req_type = 0 };
1427 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1429 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1431 req.ring_type = ring_type;
1432 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1434 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1436 if (rc || resp->error_code) {
1437 if (rc == 0 && resp->error_code)
1438 rc = rte_le_to_cpu_16(resp->error_code);
1441 switch (ring_type) {
1442 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1443 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1446 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1447 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1450 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1451 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1454 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1456 "hwrm_ring_free nq failed. rc:%d\n", rc);
1458 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1460 "hwrm_ring_free agg failed. rc:%d\n", rc);
1463 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1471 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1474 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1475 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1477 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1479 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1480 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1481 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1482 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1484 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1486 HWRM_CHECK_RESULT();
1488 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1495 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1498 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1499 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1501 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1503 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1505 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1507 HWRM_CHECK_RESULT();
1510 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1514 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1517 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1518 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1520 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1523 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1525 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1527 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1529 HWRM_CHECK_RESULT();
1535 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1536 unsigned int idx __rte_unused)
1539 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1540 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1542 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1544 req.update_period_ms = rte_cpu_to_le_32(0);
1546 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1548 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1550 HWRM_CHECK_RESULT();
1552 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1559 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1560 unsigned int idx __rte_unused)
1563 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1564 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1566 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1568 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1570 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1572 HWRM_CHECK_RESULT();
1578 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1581 struct hwrm_vnic_alloc_input req = { 0 };
1582 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1584 if (!BNXT_HAS_RING_GRPS(bp))
1585 goto skip_ring_grps;
1587 /* map ring groups to this vnic */
1588 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1589 vnic->start_grp_id, vnic->end_grp_id);
1590 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1591 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1593 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1594 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1595 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1596 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1599 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1600 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1602 if (vnic->func_default)
1604 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1605 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1607 HWRM_CHECK_RESULT();
1609 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1611 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1615 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1616 struct bnxt_vnic_info *vnic,
1617 struct bnxt_plcmodes_cfg *pmode)
1620 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1621 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1623 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1625 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1627 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1629 HWRM_CHECK_RESULT();
1631 pmode->flags = rte_le_to_cpu_32(resp->flags);
1632 /* dflt_vnic bit doesn't exist in the _cfg command */
1633 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1634 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1635 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1636 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1643 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1644 struct bnxt_vnic_info *vnic,
1645 struct bnxt_plcmodes_cfg *pmode)
1648 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1649 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1651 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1652 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1656 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1658 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1659 req.flags = rte_cpu_to_le_32(pmode->flags);
1660 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1661 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1662 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1663 req.enables = rte_cpu_to_le_32(
1664 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1665 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1666 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1669 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1671 HWRM_CHECK_RESULT();
1677 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1680 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1681 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1682 struct bnxt_plcmodes_cfg pmodes = { 0 };
1683 uint32_t ctx_enable_flag = 0;
1684 uint32_t enables = 0;
1686 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1687 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1691 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1695 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1697 if (BNXT_CHIP_THOR(bp)) {
1698 struct bnxt_rx_queue *rxq =
1699 bp->eth_dev->data->rx_queues[vnic->start_grp_id];
1700 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1701 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1703 req.default_rx_ring_id =
1704 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1705 req.default_cmpl_ring_id =
1706 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1707 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1708 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1712 /* Only RSS support for now TBD: COS & LB */
1713 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1714 if (vnic->lb_rule != 0xffff)
1715 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1716 if (vnic->cos_rule != 0xffff)
1717 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1718 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1719 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1720 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1722 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1723 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1724 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1727 enables |= ctx_enable_flag;
1728 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1729 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1730 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1731 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1734 req.enables = rte_cpu_to_le_32(enables);
1735 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1736 req.mru = rte_cpu_to_le_16(vnic->mru);
1737 /* Configure default VNIC only once. */
1738 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1740 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1741 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1743 if (vnic->vlan_strip)
1745 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1748 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1749 if (vnic->roce_dual)
1750 req.flags |= rte_cpu_to_le_32(
1751 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1752 if (vnic->roce_only)
1753 req.flags |= rte_cpu_to_le_32(
1754 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1755 if (vnic->rss_dflt_cr)
1756 req.flags |= rte_cpu_to_le_32(
1757 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1759 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1761 HWRM_CHECK_RESULT();
1764 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1769 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1773 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1774 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1776 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1777 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1780 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1783 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1784 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1785 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1787 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1789 HWRM_CHECK_RESULT();
1791 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1792 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1793 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1794 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1795 vnic->mru = rte_le_to_cpu_16(resp->mru);
1796 vnic->func_default = rte_le_to_cpu_32(
1797 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1798 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1799 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1800 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1801 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1802 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1803 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1804 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1805 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1806 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1807 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1814 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1815 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1819 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1820 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1821 bp->hwrm_cmd_resp_addr;
1823 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1825 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1826 HWRM_CHECK_RESULT();
1828 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1829 if (!BNXT_HAS_RING_GRPS(bp))
1830 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1831 else if (ctx_idx == 0)
1832 vnic->rss_rule = ctx_id;
1840 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1841 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1844 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1845 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1846 bp->hwrm_cmd_resp_addr;
1848 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1849 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1852 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1854 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1856 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1858 HWRM_CHECK_RESULT();
1864 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1868 if (BNXT_CHIP_THOR(bp)) {
1871 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1872 rc = _bnxt_hwrm_vnic_ctx_free(bp,
1874 vnic->fw_grp_ids[j]);
1875 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1877 vnic->num_lb_ctxts = 0;
1879 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1880 vnic->rss_rule = INVALID_HW_RING_ID;
1886 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1889 struct hwrm_vnic_free_input req = {.req_type = 0 };
1890 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1892 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1893 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1897 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1899 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1901 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1903 HWRM_CHECK_RESULT();
1906 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1907 /* Configure default VNIC again if necessary. */
1908 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1909 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1915 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1919 int nr_ctxs = vnic->num_lb_ctxts;
1920 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1921 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1923 for (i = 0; i < nr_ctxs; i++) {
1924 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1926 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1927 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1928 req.hash_mode_flags = vnic->hash_mode;
1930 req.hash_key_tbl_addr =
1931 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1933 req.ring_grp_tbl_addr =
1934 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1935 i * HW_HASH_INDEX_SIZE);
1936 req.ring_table_pair_index = i;
1937 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1939 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1942 HWRM_CHECK_RESULT();
1949 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1950 struct bnxt_vnic_info *vnic)
1953 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1954 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1956 if (!vnic->rss_table)
1959 if (BNXT_CHIP_THOR(bp))
1960 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1962 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1964 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1965 req.hash_mode_flags = vnic->hash_mode;
1967 req.ring_grp_tbl_addr =
1968 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1969 req.hash_key_tbl_addr =
1970 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1971 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1972 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1974 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1976 HWRM_CHECK_RESULT();
1982 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1983 struct bnxt_vnic_info *vnic)
1986 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1987 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1990 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1991 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1995 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1997 req.flags = rte_cpu_to_le_32(
1998 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2000 req.enables = rte_cpu_to_le_32(
2001 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2003 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2004 size -= RTE_PKTMBUF_HEADROOM;
2005 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2007 req.jumbo_thresh = rte_cpu_to_le_16(size);
2008 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2010 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2012 HWRM_CHECK_RESULT();
2018 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2019 struct bnxt_vnic_info *vnic, bool enable)
2022 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2023 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2025 if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2027 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2031 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2032 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2036 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2039 req.enables = rte_cpu_to_le_32(
2040 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2041 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2042 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2043 req.flags = rte_cpu_to_le_32(
2044 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2045 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2046 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2047 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2048 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2049 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2050 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2051 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2052 req.min_agg_len = rte_cpu_to_le_32(512);
2054 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2056 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2058 HWRM_CHECK_RESULT();
2064 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2066 struct hwrm_func_cfg_input req = {0};
2067 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2070 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2071 req.enables = rte_cpu_to_le_32(
2072 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2073 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2074 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2076 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2078 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2079 HWRM_CHECK_RESULT();
2082 bp->pf.vf_info[vf].random_mac = false;
2087 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2091 struct hwrm_func_qstats_input req = {.req_type = 0};
2092 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2094 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2096 req.fid = rte_cpu_to_le_16(fid);
2098 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2100 HWRM_CHECK_RESULT();
2103 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2110 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2111 struct rte_eth_stats *stats)
2114 struct hwrm_func_qstats_input req = {.req_type = 0};
2115 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2117 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2119 req.fid = rte_cpu_to_le_16(fid);
2121 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2123 HWRM_CHECK_RESULT();
2125 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2126 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2127 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2128 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2129 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2130 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2132 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2133 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2134 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2135 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2136 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2137 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2139 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2140 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2141 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2148 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2151 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2152 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2154 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2156 req.fid = rte_cpu_to_le_16(fid);
2158 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2160 HWRM_CHECK_RESULT();
2166 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2171 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2172 struct bnxt_tx_queue *txq;
2173 struct bnxt_rx_queue *rxq;
2174 struct bnxt_cp_ring_info *cpr;
2176 if (i >= bp->rx_cp_nr_rings) {
2177 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2180 rxq = bp->rx_queues[i];
2184 rc = bnxt_hwrm_stat_clear(bp, cpr);
2191 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2195 struct bnxt_cp_ring_info *cpr;
2197 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2199 if (i >= bp->rx_cp_nr_rings) {
2200 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2202 cpr = bp->rx_queues[i]->cp_ring;
2203 if (BNXT_HAS_RING_GRPS(bp))
2204 bp->grp_info[i].fw_stats_ctx = -1;
2206 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2207 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2208 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2216 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2221 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2222 struct bnxt_tx_queue *txq;
2223 struct bnxt_rx_queue *rxq;
2224 struct bnxt_cp_ring_info *cpr;
2226 if (i >= bp->rx_cp_nr_rings) {
2227 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2230 rxq = bp->rx_queues[i];
2234 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2242 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2247 if (!BNXT_HAS_RING_GRPS(bp))
2250 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2252 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2255 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2263 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2265 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2267 bnxt_hwrm_ring_free(bp, cp_ring,
2268 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2269 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2270 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2271 sizeof(*cpr->cp_desc_ring));
2272 cpr->cp_raw_cons = 0;
2276 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2278 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2280 bnxt_hwrm_ring_free(bp, cp_ring,
2281 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2282 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2283 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2284 sizeof(*cpr->cp_desc_ring));
2285 cpr->cp_raw_cons = 0;
2289 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2291 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2292 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2293 struct bnxt_ring *ring = rxr->rx_ring_struct;
2294 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2296 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2297 bnxt_hwrm_ring_free(bp, ring,
2298 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2299 ring->fw_ring_id = INVALID_HW_RING_ID;
2300 if (BNXT_HAS_RING_GRPS(bp))
2301 bp->grp_info[queue_index].rx_fw_ring_id =
2303 memset(rxr->rx_desc_ring, 0,
2304 rxr->rx_ring_struct->ring_size *
2305 sizeof(*rxr->rx_desc_ring));
2306 memset(rxr->rx_buf_ring, 0,
2307 rxr->rx_ring_struct->ring_size *
2308 sizeof(*rxr->rx_buf_ring));
2311 ring = rxr->ag_ring_struct;
2312 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2313 bnxt_hwrm_ring_free(bp, ring,
2314 BNXT_CHIP_THOR(bp) ?
2315 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2316 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2317 ring->fw_ring_id = INVALID_HW_RING_ID;
2318 memset(rxr->ag_buf_ring, 0,
2319 rxr->ag_ring_struct->ring_size *
2320 sizeof(*rxr->ag_buf_ring));
2322 if (BNXT_HAS_RING_GRPS(bp))
2323 bp->grp_info[queue_index].ag_fw_ring_id =
2326 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2327 bnxt_free_cp_ring(bp, cpr);
2329 if (BNXT_HAS_RING_GRPS(bp))
2330 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2333 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2337 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2338 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2339 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2340 struct bnxt_ring *ring = txr->tx_ring_struct;
2341 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2343 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2344 bnxt_hwrm_ring_free(bp, ring,
2345 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2346 ring->fw_ring_id = INVALID_HW_RING_ID;
2347 memset(txr->tx_desc_ring, 0,
2348 txr->tx_ring_struct->ring_size *
2349 sizeof(*txr->tx_desc_ring));
2350 memset(txr->tx_buf_ring, 0,
2351 txr->tx_ring_struct->ring_size *
2352 sizeof(*txr->tx_buf_ring));
2356 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2357 bnxt_free_cp_ring(bp, cpr);
2358 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2362 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2363 bnxt_free_hwrm_rx_ring(bp, i);
2368 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2373 if (!BNXT_HAS_RING_GRPS(bp))
2376 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2377 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2385 * HWRM utility functions
2388 void bnxt_free_hwrm_resources(struct bnxt *bp)
2390 /* Release memzone */
2391 rte_free(bp->hwrm_cmd_resp_addr);
2392 rte_free(bp->hwrm_short_cmd_req_addr);
2393 bp->hwrm_cmd_resp_addr = NULL;
2394 bp->hwrm_short_cmd_req_addr = NULL;
2395 bp->hwrm_cmd_resp_dma_addr = 0;
2396 bp->hwrm_short_cmd_req_dma_addr = 0;
2399 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2401 struct rte_pci_device *pdev = bp->pdev;
2402 char type[RTE_MEMZONE_NAMESIZE];
2404 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2405 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2406 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2407 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2408 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2409 if (bp->hwrm_cmd_resp_addr == NULL)
2411 bp->hwrm_cmd_resp_dma_addr =
2412 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2413 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2415 "unable to map response address to physical memory\n");
2418 rte_spinlock_init(&bp->hwrm_lock);
2423 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2425 struct bnxt_filter_info *filter;
2428 STAILQ_FOREACH(filter, &vnic->filter, next) {
2429 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2430 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2431 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2432 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2434 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2435 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2436 bnxt_free_filter(bp, filter);
2442 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2444 struct bnxt_filter_info *filter;
2445 struct rte_flow *flow;
2448 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2449 flow = STAILQ_FIRST(&vnic->flow_list);
2450 filter = flow->filter;
2451 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2452 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2453 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2454 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2455 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2457 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2459 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2465 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2467 struct bnxt_filter_info *filter;
2470 STAILQ_FOREACH(filter, &vnic->filter, next) {
2471 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2472 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2474 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2475 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2478 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2489 void bnxt_free_tunnel_ports(struct bnxt *bp)
2491 if (bp->vxlan_port_cnt)
2492 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2493 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2495 if (bp->geneve_port_cnt)
2496 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2497 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2498 bp->geneve_port = 0;
2501 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2505 if (bp->vnic_info == NULL)
2509 * Cleanup VNICs in reverse order, to make sure the L2 filter
2510 * from vnic0 is last to be cleaned up.
2512 for (i = bp->max_vnics - 1; i >= 0; i--) {
2513 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2515 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2518 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2520 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2522 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2524 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2526 bnxt_hwrm_vnic_free(bp, vnic);
2528 rte_free(vnic->fw_grp_ids);
2530 /* Ring resources */
2531 bnxt_free_all_hwrm_rings(bp);
2532 bnxt_free_all_hwrm_ring_grps(bp);
2533 bnxt_free_all_hwrm_stat_ctxs(bp);
2534 bnxt_free_tunnel_ports(bp);
2537 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2539 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2541 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2542 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2544 switch (conf_link_speed) {
2545 case ETH_LINK_SPEED_10M_HD:
2546 case ETH_LINK_SPEED_100M_HD:
2548 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2550 return hw_link_duplex;
2553 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2555 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2558 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2560 uint16_t eth_link_speed = 0;
2562 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2563 return ETH_LINK_SPEED_AUTONEG;
2565 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2566 case ETH_LINK_SPEED_100M:
2567 case ETH_LINK_SPEED_100M_HD:
2570 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2572 case ETH_LINK_SPEED_1G:
2574 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2576 case ETH_LINK_SPEED_2_5G:
2578 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2580 case ETH_LINK_SPEED_10G:
2582 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2584 case ETH_LINK_SPEED_20G:
2586 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2588 case ETH_LINK_SPEED_25G:
2590 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2592 case ETH_LINK_SPEED_40G:
2594 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2596 case ETH_LINK_SPEED_50G:
2598 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2600 case ETH_LINK_SPEED_100G:
2602 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2606 "Unsupported link speed %d; default to AUTO\n",
2610 return eth_link_speed;
2613 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2614 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2615 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2616 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2618 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2622 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2625 if (link_speed & ETH_LINK_SPEED_FIXED) {
2626 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2628 if (one_speed & (one_speed - 1)) {
2630 "Invalid advertised speeds (%u) for port %u\n",
2631 link_speed, port_id);
2634 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2636 "Unsupported advertised speed (%u) for port %u\n",
2637 link_speed, port_id);
2641 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2643 "Unsupported advertised speeds (%u) for port %u\n",
2644 link_speed, port_id);
2652 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2656 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2657 if (bp->link_info.support_speeds)
2658 return bp->link_info.support_speeds;
2659 link_speed = BNXT_SUPPORTED_SPEEDS;
2662 if (link_speed & ETH_LINK_SPEED_100M)
2663 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2664 if (link_speed & ETH_LINK_SPEED_100M_HD)
2665 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2666 if (link_speed & ETH_LINK_SPEED_1G)
2667 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2668 if (link_speed & ETH_LINK_SPEED_2_5G)
2669 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2670 if (link_speed & ETH_LINK_SPEED_10G)
2671 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2672 if (link_speed & ETH_LINK_SPEED_20G)
2673 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2674 if (link_speed & ETH_LINK_SPEED_25G)
2675 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2676 if (link_speed & ETH_LINK_SPEED_40G)
2677 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2678 if (link_speed & ETH_LINK_SPEED_50G)
2679 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2680 if (link_speed & ETH_LINK_SPEED_100G)
2681 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2685 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2687 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2689 switch (hw_link_speed) {
2690 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2691 eth_link_speed = ETH_SPEED_NUM_100M;
2693 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2694 eth_link_speed = ETH_SPEED_NUM_1G;
2696 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2697 eth_link_speed = ETH_SPEED_NUM_2_5G;
2699 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2700 eth_link_speed = ETH_SPEED_NUM_10G;
2702 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2703 eth_link_speed = ETH_SPEED_NUM_20G;
2705 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2706 eth_link_speed = ETH_SPEED_NUM_25G;
2708 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2709 eth_link_speed = ETH_SPEED_NUM_40G;
2711 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2712 eth_link_speed = ETH_SPEED_NUM_50G;
2714 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2715 eth_link_speed = ETH_SPEED_NUM_100G;
2717 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2719 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2723 return eth_link_speed;
2726 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2728 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2730 switch (hw_link_duplex) {
2731 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2732 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2734 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2736 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2737 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2740 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2744 return eth_link_duplex;
2747 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2750 struct bnxt_link_info *link_info = &bp->link_info;
2752 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2755 "Get link config failed with rc %d\n", rc);
2758 if (link_info->link_speed)
2760 bnxt_parse_hw_link_speed(link_info->link_speed);
2762 link->link_speed = ETH_SPEED_NUM_NONE;
2763 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2764 link->link_status = link_info->link_up;
2765 link->link_autoneg = link_info->auto_mode ==
2766 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2767 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2772 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2775 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2776 struct bnxt_link_info link_req;
2777 uint16_t speed, autoneg;
2779 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2782 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2783 bp->eth_dev->data->port_id);
2787 memset(&link_req, 0, sizeof(link_req));
2788 link_req.link_up = link_up;
2792 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2793 if (BNXT_CHIP_THOR(bp) &&
2794 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2795 /* 40G is not supported as part of media auto detect.
2796 * The speed should be forced and autoneg disabled
2797 * to configure 40G speed.
2799 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2803 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2804 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2805 /* Autoneg can be done only when the FW allows.
2806 * When user configures fixed speed of 40G and later changes to
2807 * any other speed, auto_link_speed/force_link_speed is still set
2808 * to 40G until link comes up at new speed.
2811 !(!BNXT_CHIP_THOR(bp) &&
2812 (bp->link_info.auto_link_speed ||
2813 bp->link_info.force_link_speed))) {
2814 link_req.phy_flags |=
2815 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2816 link_req.auto_link_speed_mask =
2817 bnxt_parse_eth_link_speed_mask(bp,
2818 dev_conf->link_speeds);
2820 if (bp->link_info.phy_type ==
2821 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2822 bp->link_info.phy_type ==
2823 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2824 bp->link_info.media_type ==
2825 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2826 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2830 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2831 /* If user wants a particular speed try that first. */
2833 link_req.link_speed = speed;
2834 else if (bp->link_info.force_link_speed)
2835 link_req.link_speed = bp->link_info.force_link_speed;
2837 link_req.link_speed = bp->link_info.auto_link_speed;
2839 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2840 link_req.auto_pause = bp->link_info.auto_pause;
2841 link_req.force_pause = bp->link_info.force_pause;
2844 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2847 "Set link config failed with rc %d\n", rc);
2855 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2857 struct hwrm_func_qcfg_input req = {0};
2858 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2862 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2863 req.fid = rte_cpu_to_le_16(0xffff);
2865 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2867 HWRM_CHECK_RESULT();
2869 /* Hard Coded.. 0xfff VLAN ID mask */
2870 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2871 flags = rte_le_to_cpu_16(resp->flags);
2872 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2873 bp->flags |= BNXT_FLAG_MULTI_HOST;
2876 !BNXT_VF_IS_TRUSTED(bp) &&
2877 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2878 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2879 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2880 } else if (BNXT_VF(bp) &&
2881 BNXT_VF_IS_TRUSTED(bp) &&
2882 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2883 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2884 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2888 *mtu = rte_le_to_cpu_16(resp->mtu);
2890 switch (resp->port_partition_type) {
2891 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2892 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2893 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2895 bp->port_partition_type = resp->port_partition_type;
2898 bp->port_partition_type = 0;
2907 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2908 struct hwrm_func_qcaps_output *qcaps)
2910 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2911 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2912 sizeof(qcaps->mac_address));
2913 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2914 qcaps->max_rx_rings = fcfg->num_rx_rings;
2915 qcaps->max_tx_rings = fcfg->num_tx_rings;
2916 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2917 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2919 qcaps->first_vf_id = 0;
2920 qcaps->max_vnics = fcfg->num_vnics;
2921 qcaps->max_decap_records = 0;
2922 qcaps->max_encap_records = 0;
2923 qcaps->max_tx_wm_flows = 0;
2924 qcaps->max_tx_em_flows = 0;
2925 qcaps->max_rx_wm_flows = 0;
2926 qcaps->max_rx_em_flows = 0;
2927 qcaps->max_flow_id = 0;
2928 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2929 qcaps->max_sp_tx_rings = 0;
2930 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2933 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2935 struct hwrm_func_cfg_input req = {0};
2936 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2940 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2941 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2942 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2943 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2944 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2945 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2946 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2947 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2948 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2950 if (BNXT_HAS_RING_GRPS(bp)) {
2951 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2952 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2953 } else if (BNXT_HAS_NQ(bp)) {
2954 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2955 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2958 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2959 req.mtu = rte_cpu_to_le_16(RTE_MIN(bp->eth_dev->data->mtu,
2960 BNXT_MAX_MTU)); //FW adds hdr sizes
2961 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
2962 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2963 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2964 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2965 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2966 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2967 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2968 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2969 req.fid = rte_cpu_to_le_16(0xffff);
2970 req.enables = rte_cpu_to_le_32(enables);
2972 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2974 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2976 HWRM_CHECK_RESULT();
2982 static void populate_vf_func_cfg_req(struct bnxt *bp,
2983 struct hwrm_func_cfg_input *req,
2986 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2987 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2988 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2989 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2990 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2991 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2992 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2993 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2994 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2995 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2997 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2998 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3000 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3001 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3003 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3004 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3006 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3007 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3008 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3009 /* TODO: For now, do not support VMDq/RFS on VFs. */
3010 req->num_vnics = rte_cpu_to_le_16(1);
3011 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3015 static void add_random_mac_if_needed(struct bnxt *bp,
3016 struct hwrm_func_cfg_input *cfg_req,
3019 struct rte_ether_addr mac;
3021 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3024 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3026 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3027 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3028 bp->pf.vf_info[vf].random_mac = true;
3030 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3031 RTE_ETHER_ADDR_LEN);
3035 static void reserve_resources_from_vf(struct bnxt *bp,
3036 struct hwrm_func_cfg_input *cfg_req,
3039 struct hwrm_func_qcaps_input req = {0};
3040 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3043 /* Get the actual allocated values now */
3044 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3045 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3046 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3049 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3050 copy_func_cfg_to_qcaps(cfg_req, resp);
3051 } else if (resp->error_code) {
3052 rc = rte_le_to_cpu_16(resp->error_code);
3053 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3054 copy_func_cfg_to_qcaps(cfg_req, resp);
3057 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3058 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3059 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3060 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3061 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3062 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3064 * TODO: While not supporting VMDq with VFs, max_vnics is always
3065 * forced to 1 in this case
3067 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3068 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3073 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3075 struct hwrm_func_qcfg_input req = {0};
3076 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3079 /* Check for zero MAC address */
3080 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3081 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3082 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3083 HWRM_CHECK_RESULT();
3084 rc = rte_le_to_cpu_16(resp->vlan);
3091 static int update_pf_resource_max(struct bnxt *bp)
3093 struct hwrm_func_qcfg_input req = {0};
3094 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3097 /* And copy the allocated numbers into the pf struct */
3098 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3099 req.fid = rte_cpu_to_le_16(0xffff);
3100 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3101 HWRM_CHECK_RESULT();
3103 /* Only TX ring value reflects actual allocation? TODO */
3104 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3105 bp->pf.evb_mode = resp->evb_mode;
3112 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3117 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3121 rc = bnxt_hwrm_func_qcaps(bp);
3125 bp->pf.func_cfg_flags &=
3126 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3127 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3128 bp->pf.func_cfg_flags |=
3129 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3130 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3131 rc = __bnxt_hwrm_func_qcaps(bp);
3135 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3137 struct hwrm_func_cfg_input req = {0};
3138 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3145 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3149 rc = bnxt_hwrm_func_qcaps(bp);
3154 bp->pf.active_vfs = num_vfs;
3157 * First, configure the PF to only use one TX ring. This ensures that
3158 * there are enough rings for all VFs.
3160 * If we don't do this, when we call func_alloc() later, we will lock
3161 * extra rings to the PF that won't be available during func_cfg() of
3164 * This has been fixed with firmware versions above 20.6.54
3166 bp->pf.func_cfg_flags &=
3167 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3168 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3169 bp->pf.func_cfg_flags |=
3170 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3171 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3176 * Now, create and register a buffer to hold forwarded VF requests
3178 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3179 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3180 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3181 if (bp->pf.vf_req_buf == NULL) {
3185 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3186 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3187 for (i = 0; i < num_vfs; i++)
3188 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3189 (i * HWRM_MAX_REQ_LEN);
3191 rc = bnxt_hwrm_func_buf_rgtr(bp);
3195 populate_vf_func_cfg_req(bp, &req, num_vfs);
3197 bp->pf.active_vfs = 0;
3198 for (i = 0; i < num_vfs; i++) {
3199 add_random_mac_if_needed(bp, &req, i);
3201 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3202 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3203 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3204 rc = bnxt_hwrm_send_message(bp,
3209 /* Clear enable flag for next pass */
3210 req.enables &= ~rte_cpu_to_le_32(
3211 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3213 if (rc || resp->error_code) {
3215 "Failed to initizlie VF %d\n", i);
3217 "Not all VFs available. (%d, %d)\n",
3218 rc, resp->error_code);
3225 reserve_resources_from_vf(bp, &req, i);
3226 bp->pf.active_vfs++;
3227 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3231 * Now configure the PF to use "the rest" of the resources
3232 * We're using STD_TX_RING_MODE here though which will limit the TX
3233 * rings. This will allow QoS to function properly. Not setting this
3234 * will cause PF rings to break bandwidth settings.
3236 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3240 rc = update_pf_resource_max(bp);
3247 bnxt_hwrm_func_buf_unrgtr(bp);
3251 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3253 struct hwrm_func_cfg_input req = {0};
3254 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3257 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3259 req.fid = rte_cpu_to_le_16(0xffff);
3260 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3261 req.evb_mode = bp->pf.evb_mode;
3263 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3264 HWRM_CHECK_RESULT();
3270 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3271 uint8_t tunnel_type)
3273 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3274 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3277 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3278 req.tunnel_type = tunnel_type;
3279 req.tunnel_dst_port_val = port;
3280 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3281 HWRM_CHECK_RESULT();
3283 switch (tunnel_type) {
3284 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3285 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3286 bp->vxlan_port = port;
3288 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3289 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3290 bp->geneve_port = port;
3301 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3302 uint8_t tunnel_type)
3304 struct hwrm_tunnel_dst_port_free_input req = {0};
3305 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3308 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3310 req.tunnel_type = tunnel_type;
3311 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3312 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3314 HWRM_CHECK_RESULT();
3320 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3323 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3324 struct hwrm_func_cfg_input req = {0};
3327 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3329 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3330 req.flags = rte_cpu_to_le_32(flags);
3331 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3333 HWRM_CHECK_RESULT();
3339 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3341 uint32_t *flag = flagp;
3343 vnic->flags = *flag;
3346 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3348 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3351 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3354 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3355 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3357 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3359 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3360 req.req_buf_page_size = rte_cpu_to_le_16(
3361 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3362 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3363 req.req_buf_page_addr0 =
3364 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3365 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3367 "unable to map buffer address to physical memory\n");
3371 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3373 HWRM_CHECK_RESULT();
3379 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3382 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3383 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3385 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3388 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3390 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3392 HWRM_CHECK_RESULT();
3398 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3400 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3401 struct hwrm_func_cfg_input req = {0};
3404 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3406 req.fid = rte_cpu_to_le_16(0xffff);
3407 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3408 req.enables = rte_cpu_to_le_32(
3409 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3410 req.async_event_cr = rte_cpu_to_le_16(
3411 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3412 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3414 HWRM_CHECK_RESULT();
3420 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3422 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3423 struct hwrm_func_vf_cfg_input req = {0};
3426 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3428 req.enables = rte_cpu_to_le_32(
3429 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3430 req.async_event_cr = rte_cpu_to_le_16(
3431 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3432 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3434 HWRM_CHECK_RESULT();
3440 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3442 struct hwrm_func_cfg_input req = {0};
3443 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3444 uint16_t dflt_vlan, fid;
3445 uint32_t func_cfg_flags;
3448 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3451 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3452 fid = bp->pf.vf_info[vf].fid;
3453 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3455 fid = rte_cpu_to_le_16(0xffff);
3456 func_cfg_flags = bp->pf.func_cfg_flags;
3457 dflt_vlan = bp->vlan;
3460 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3461 req.fid = rte_cpu_to_le_16(fid);
3462 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3463 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3465 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3467 HWRM_CHECK_RESULT();
3473 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3474 uint16_t max_bw, uint16_t enables)
3476 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3477 struct hwrm_func_cfg_input req = {0};
3480 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3482 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3483 req.enables |= rte_cpu_to_le_32(enables);
3484 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3485 req.max_bw = rte_cpu_to_le_32(max_bw);
3486 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3488 HWRM_CHECK_RESULT();
3494 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3496 struct hwrm_func_cfg_input req = {0};
3497 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3500 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3502 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3503 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3504 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3505 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3507 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3509 HWRM_CHECK_RESULT();
3515 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3520 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3522 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3527 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3528 void *encaped, size_t ec_size)
3531 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3532 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3534 if (ec_size > sizeof(req.encap_request))
3537 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3539 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3540 memcpy(req.encap_request, encaped, ec_size);
3542 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3544 HWRM_CHECK_RESULT();
3550 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3551 struct rte_ether_addr *mac)
3553 struct hwrm_func_qcfg_input req = {0};
3554 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3557 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3559 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3560 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3562 HWRM_CHECK_RESULT();
3564 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3571 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3572 void *encaped, size_t ec_size)
3575 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3576 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3578 if (ec_size > sizeof(req.encap_request))
3581 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3583 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3584 memcpy(req.encap_request, encaped, ec_size);
3586 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3588 HWRM_CHECK_RESULT();
3594 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3595 struct rte_eth_stats *stats, uint8_t rx)
3598 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3599 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3601 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3603 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3605 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3607 HWRM_CHECK_RESULT();
3610 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3611 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3612 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3613 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3614 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3615 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3616 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3617 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3619 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3620 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3621 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3622 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3623 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3624 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3632 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3634 struct hwrm_port_qstats_input req = {0};
3635 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3636 struct bnxt_pf_info *pf = &bp->pf;
3639 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3641 req.port_id = rte_cpu_to_le_16(pf->port_id);
3642 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3643 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3644 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3646 HWRM_CHECK_RESULT();
3652 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3654 struct hwrm_port_clr_stats_input req = {0};
3655 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3656 struct bnxt_pf_info *pf = &bp->pf;
3659 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3660 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3661 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3664 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3666 req.port_id = rte_cpu_to_le_16(pf->port_id);
3667 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3669 HWRM_CHECK_RESULT();
3675 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3677 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3678 struct hwrm_port_led_qcaps_input req = {0};
3684 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3685 req.port_id = bp->pf.port_id;
3686 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3688 HWRM_CHECK_RESULT();
3690 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3693 bp->num_leds = resp->num_leds;
3694 memcpy(bp->leds, &resp->led0_id,
3695 sizeof(bp->leds[0]) * bp->num_leds);
3696 for (i = 0; i < bp->num_leds; i++) {
3697 struct bnxt_led_info *led = &bp->leds[i];
3699 uint16_t caps = led->led_state_caps;
3701 if (!led->led_group_id ||
3702 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3714 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3716 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3717 struct hwrm_port_led_cfg_input req = {0};
3718 struct bnxt_led_cfg *led_cfg;
3719 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3720 uint16_t duration = 0;
3723 if (!bp->num_leds || BNXT_VF(bp))
3726 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3729 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3730 duration = rte_cpu_to_le_16(500);
3732 req.port_id = bp->pf.port_id;
3733 req.num_leds = bp->num_leds;
3734 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3735 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3736 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3737 led_cfg->led_id = bp->leds[i].led_id;
3738 led_cfg->led_state = led_state;
3739 led_cfg->led_blink_on = duration;
3740 led_cfg->led_blink_off = duration;
3741 led_cfg->led_group_id = bp->leds[i].led_group_id;
3744 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3746 HWRM_CHECK_RESULT();
3752 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3756 struct hwrm_nvm_get_dir_info_input req = {0};
3757 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3759 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3761 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3763 HWRM_CHECK_RESULT();
3765 *entries = rte_le_to_cpu_32(resp->entries);
3766 *length = rte_le_to_cpu_32(resp->entry_length);
3772 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3775 uint32_t dir_entries;
3776 uint32_t entry_length;
3779 rte_iova_t dma_handle;
3780 struct hwrm_nvm_get_dir_entries_input req = {0};
3781 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3783 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3787 *data++ = dir_entries;
3788 *data++ = entry_length;
3790 memset(data, 0xff, len);
3792 buflen = dir_entries * entry_length;
3793 buf = rte_malloc("nvm_dir", buflen, 0);
3794 rte_mem_lock_page(buf);
3797 dma_handle = rte_mem_virt2iova(buf);
3798 if (dma_handle == RTE_BAD_IOVA) {
3800 "unable to map response address to physical memory\n");
3803 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3804 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3805 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3808 memcpy(data, buf, len > buflen ? buflen : len);
3811 HWRM_CHECK_RESULT();
3817 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3818 uint32_t offset, uint32_t length,
3823 rte_iova_t dma_handle;
3824 struct hwrm_nvm_read_input req = {0};
3825 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3827 buf = rte_malloc("nvm_item", length, 0);
3828 rte_mem_lock_page(buf);
3832 dma_handle = rte_mem_virt2iova(buf);
3833 if (dma_handle == RTE_BAD_IOVA) {
3835 "unable to map response address to physical memory\n");
3838 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3839 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3840 req.dir_idx = rte_cpu_to_le_16(index);
3841 req.offset = rte_cpu_to_le_32(offset);
3842 req.len = rte_cpu_to_le_32(length);
3843 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3845 memcpy(data, buf, length);
3848 HWRM_CHECK_RESULT();
3854 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3857 struct hwrm_nvm_erase_dir_entry_input req = {0};
3858 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3860 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3861 req.dir_idx = rte_cpu_to_le_16(index);
3862 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3863 HWRM_CHECK_RESULT();
3870 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3871 uint16_t dir_ordinal, uint16_t dir_ext,
3872 uint16_t dir_attr, const uint8_t *data,
3876 struct hwrm_nvm_write_input req = {0};
3877 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3878 rte_iova_t dma_handle;
3881 buf = rte_malloc("nvm_write", data_len, 0);
3882 rte_mem_lock_page(buf);
3886 dma_handle = rte_mem_virt2iova(buf);
3887 if (dma_handle == RTE_BAD_IOVA) {
3889 "unable to map response address to physical memory\n");
3892 memcpy(buf, data, data_len);
3894 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3896 req.dir_type = rte_cpu_to_le_16(dir_type);
3897 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3898 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3899 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3900 req.dir_data_length = rte_cpu_to_le_32(data_len);
3901 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3903 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3906 HWRM_CHECK_RESULT();
3913 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3915 uint32_t *count = cbdata;
3917 *count = *count + 1;
3920 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3921 struct bnxt_vnic_info *vnic __rte_unused)
3926 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3930 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3931 &count, bnxt_vnic_count_hwrm_stub);
3936 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3939 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3940 struct hwrm_func_vf_vnic_ids_query_output *resp =
3941 bp->hwrm_cmd_resp_addr;
3944 /* First query all VNIC ids */
3945 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3947 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3948 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3949 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3951 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3954 "unable to map VNIC ID table address to physical memory\n");
3957 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3958 HWRM_CHECK_RESULT();
3959 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3967 * This function queries the VNIC IDs for a specified VF. It then calls
3968 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3969 * Then it calls the hwrm_cb function to program this new vnic configuration.
3971 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3972 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3973 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3975 struct bnxt_vnic_info vnic;
3977 int i, num_vnic_ids;
3982 /* First query all VNIC ids */
3983 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3984 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3985 RTE_CACHE_LINE_SIZE);
3986 if (vnic_ids == NULL)
3989 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3990 rte_mem_lock_page(((char *)vnic_ids) + sz);
3992 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3994 if (num_vnic_ids < 0)
3995 return num_vnic_ids;
3997 /* Retrieve VNIC, update bd_stall then update */
3999 for (i = 0; i < num_vnic_ids; i++) {
4000 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4001 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4002 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4005 if (vnic.mru <= 4) /* Indicates unallocated */
4008 vnic_cb(&vnic, cbdata);
4010 rc = hwrm_cb(bp, &vnic);
4020 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4023 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4024 struct hwrm_func_cfg_input req = {0};
4027 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4029 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4030 req.enables |= rte_cpu_to_le_32(
4031 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4032 req.vlan_antispoof_mode = on ?
4033 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4034 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4035 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4037 HWRM_CHECK_RESULT();
4043 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4045 struct bnxt_vnic_info vnic;
4048 int num_vnic_ids, i;
4052 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4053 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4054 RTE_CACHE_LINE_SIZE);
4055 if (vnic_ids == NULL)
4058 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4059 rte_mem_lock_page(((char *)vnic_ids) + sz);
4061 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4067 * Loop through to find the default VNIC ID.
4068 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4069 * by sending the hwrm_func_qcfg command to the firmware.
4071 for (i = 0; i < num_vnic_ids; i++) {
4072 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4073 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4074 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4075 bp->pf.first_vf_id + vf);
4078 if (vnic.func_default) {
4080 return vnic.fw_vnic_id;
4083 /* Could not find a default VNIC. */
4084 PMD_DRV_LOG(ERR, "No default VNIC\n");
4090 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4092 struct bnxt_filter_info *filter)
4095 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4096 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4097 uint32_t enables = 0;
4099 if (filter->fw_em_filter_id != UINT64_MAX)
4100 bnxt_hwrm_clear_em_filter(bp, filter);
4102 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4104 req.flags = rte_cpu_to_le_32(filter->flags);
4106 enables = filter->enables |
4107 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4108 req.dst_id = rte_cpu_to_le_16(dst_id);
4110 if (filter->ip_addr_type) {
4111 req.ip_addr_type = filter->ip_addr_type;
4112 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4115 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4116 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4118 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4119 memcpy(req.src_macaddr, filter->src_macaddr,
4120 RTE_ETHER_ADDR_LEN);
4122 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4123 memcpy(req.dst_macaddr, filter->dst_macaddr,
4124 RTE_ETHER_ADDR_LEN);
4126 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4127 req.ovlan_vid = filter->l2_ovlan;
4129 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4130 req.ivlan_vid = filter->l2_ivlan;
4132 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4133 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4135 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4136 req.ip_protocol = filter->ip_protocol;
4138 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4139 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4141 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4142 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4144 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4145 req.src_port = rte_cpu_to_be_16(filter->src_port);
4147 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4148 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4150 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4151 req.mirror_vnic_id = filter->mirror_vnic_id;
4153 req.enables = rte_cpu_to_le_32(enables);
4155 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4157 HWRM_CHECK_RESULT();
4159 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4165 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4168 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4169 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4171 if (filter->fw_em_filter_id == UINT64_MAX)
4174 PMD_DRV_LOG(ERR, "Clear EM filter\n");
4175 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4177 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4179 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4181 HWRM_CHECK_RESULT();
4184 filter->fw_em_filter_id = UINT64_MAX;
4185 filter->fw_l2_filter_id = UINT64_MAX;
4190 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4192 struct bnxt_filter_info *filter)
4195 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4196 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4197 bp->hwrm_cmd_resp_addr;
4198 uint32_t enables = 0;
4200 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4201 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4203 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4205 req.flags = rte_cpu_to_le_32(filter->flags);
4207 enables = filter->enables |
4208 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4209 req.dst_id = rte_cpu_to_le_16(dst_id);
4211 if (filter->ip_addr_type) {
4212 req.ip_addr_type = filter->ip_addr_type;
4214 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4217 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4218 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4220 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4221 memcpy(req.src_macaddr, filter->src_macaddr,
4222 RTE_ETHER_ADDR_LEN);
4224 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4225 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4227 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4228 req.ip_protocol = filter->ip_protocol;
4230 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4231 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4233 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4234 req.src_ipaddr_mask[0] =
4235 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4237 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4238 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4240 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4241 req.dst_ipaddr_mask[0] =
4242 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4244 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4245 req.src_port = rte_cpu_to_le_16(filter->src_port);
4247 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4248 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4250 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4251 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4253 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4254 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4256 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4257 req.mirror_vnic_id = filter->mirror_vnic_id;
4259 req.enables = rte_cpu_to_le_32(enables);
4261 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4263 HWRM_CHECK_RESULT();
4265 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4271 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4272 struct bnxt_filter_info *filter)
4275 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4276 struct hwrm_cfa_ntuple_filter_free_output *resp =
4277 bp->hwrm_cmd_resp_addr;
4279 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4282 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4284 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4286 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4288 HWRM_CHECK_RESULT();
4291 filter->fw_ntuple_filter_id = UINT64_MAX;
4297 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4299 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4300 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4301 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4302 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4303 uint16_t *ring_tbl = vnic->rss_table;
4304 int nr_ctxs = vnic->num_lb_ctxts;
4305 int max_rings = bp->rx_nr_rings;
4309 for (i = 0, k = 0; i < nr_ctxs; i++) {
4310 struct bnxt_rx_ring_info *rxr;
4311 struct bnxt_cp_ring_info *cpr;
4313 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4315 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4316 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4317 req.hash_mode_flags = vnic->hash_mode;
4319 req.ring_grp_tbl_addr =
4320 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4321 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4322 2 * sizeof(*ring_tbl));
4323 req.hash_key_tbl_addr =
4324 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4326 req.ring_table_pair_index = i;
4327 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4329 for (j = 0; j < 64; j++) {
4332 /* Find next active ring. */
4333 for (cnt = 0; cnt < max_rings; cnt++) {
4334 if (rx_queue_state[k] !=
4335 RTE_ETH_QUEUE_STATE_STOPPED)
4337 if (++k == max_rings)
4341 /* Return if no rings are active. */
4342 if (cnt == max_rings)
4345 /* Add rx/cp ring pair to RSS table. */
4346 rxr = rxqs[k]->rx_ring;
4347 cpr = rxqs[k]->cp_ring;
4349 ring_id = rxr->rx_ring_struct->fw_ring_id;
4350 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4351 ring_id = cpr->cp_ring_struct->fw_ring_id;
4352 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4354 if (++k == max_rings)
4357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4360 HWRM_CHECK_RESULT();
4367 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4369 unsigned int rss_idx, fw_idx, i;
4371 if (!(vnic->rss_table && vnic->hash_type))
4374 if (BNXT_CHIP_THOR(bp))
4375 return bnxt_vnic_rss_configure_thor(bp, vnic);
4377 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4380 if (vnic->rss_table && vnic->hash_type) {
4382 * Fill the RSS hash & redirection table with
4383 * ring group ids for all VNICs
4385 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4386 rss_idx++, fw_idx++) {
4387 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4388 fw_idx %= bp->rx_cp_nr_rings;
4389 if (vnic->fw_grp_ids[fw_idx] !=
4394 if (i == bp->rx_cp_nr_rings)
4396 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4398 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4404 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4405 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4409 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4411 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4412 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4414 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4415 req->num_cmpl_dma_aggr_during_int =
4416 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4418 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4420 /* min timer set to 1/2 of interrupt timer */
4421 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4423 /* buf timer set to 1/4 of interrupt timer */
4424 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4426 req->cmpl_aggr_dma_tmr_during_int =
4427 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4429 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4430 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4431 req->flags = rte_cpu_to_le_16(flags);
4434 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4435 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4437 struct hwrm_ring_aggint_qcaps_input req = {0};
4438 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4443 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4444 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4445 HWRM_CHECK_RESULT();
4447 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4448 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4450 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4451 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4452 agg_req->flags = rte_cpu_to_le_16(flags);
4454 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4455 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4456 agg_req->enables = rte_cpu_to_le_32(enables);
4462 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4463 struct bnxt_coal *coal, uint16_t ring_id)
4465 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4466 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4467 bp->hwrm_cmd_resp_addr;
4470 /* Set ring coalesce parameters only for 100G NICs */
4471 if (BNXT_CHIP_THOR(bp)) {
4472 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4474 } else if (bnxt_stratus_device(bp)) {
4475 bnxt_hwrm_set_coal_params(coal, &req);
4480 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4481 req.ring_id = rte_cpu_to_le_16(ring_id);
4482 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4483 HWRM_CHECK_RESULT();
4488 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4489 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4491 struct hwrm_func_backing_store_qcaps_input req = {0};
4492 struct hwrm_func_backing_store_qcaps_output *resp =
4493 bp->hwrm_cmd_resp_addr;
4494 struct bnxt_ctx_pg_info *ctx_pg;
4495 struct bnxt_ctx_mem_info *ctx;
4496 int total_alloc_len;
4499 if (!BNXT_CHIP_THOR(bp) ||
4500 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4505 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4506 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4507 HWRM_CHECK_RESULT_SILENT();
4509 total_alloc_len = sizeof(*ctx);
4510 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4511 RTE_CACHE_LINE_SIZE);
4517 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4518 sizeof(*ctx_pg) * BNXT_MAX_Q,
4519 RTE_CACHE_LINE_SIZE);
4524 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4525 ctx->tqm_mem[i] = ctx_pg;
4528 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4529 ctx->qp_min_qp1_entries =
4530 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4531 ctx->qp_max_l2_entries =
4532 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4533 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4534 ctx->srq_max_l2_entries =
4535 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4536 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4537 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4538 ctx->cq_max_l2_entries =
4539 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4540 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4541 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4542 ctx->vnic_max_vnic_entries =
4543 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4544 ctx->vnic_max_ring_table_entries =
4545 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4546 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4547 ctx->stat_max_entries =
4548 rte_le_to_cpu_32(resp->stat_max_entries);
4549 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4550 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4551 ctx->tqm_min_entries_per_ring =
4552 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4553 ctx->tqm_max_entries_per_ring =
4554 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4555 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4556 if (!ctx->tqm_entries_multiple)
4557 ctx->tqm_entries_multiple = 1;
4558 ctx->mrav_max_entries =
4559 rte_le_to_cpu_32(resp->mrav_max_entries);
4560 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4561 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4562 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4568 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4570 struct hwrm_func_backing_store_cfg_input req = {0};
4571 struct hwrm_func_backing_store_cfg_output *resp =
4572 bp->hwrm_cmd_resp_addr;
4573 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4574 struct bnxt_ctx_pg_info *ctx_pg;
4575 uint32_t *num_entries;
4584 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4585 req.enables = rte_cpu_to_le_32(enables);
4587 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4588 ctx_pg = &ctx->qp_mem;
4589 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4590 req.qp_num_qp1_entries =
4591 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4592 req.qp_num_l2_entries =
4593 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4594 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4595 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4596 &req.qpc_pg_size_qpc_lvl,
4600 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4601 ctx_pg = &ctx->srq_mem;
4602 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4603 req.srq_num_l2_entries =
4604 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4605 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4606 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4607 &req.srq_pg_size_srq_lvl,
4611 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4612 ctx_pg = &ctx->cq_mem;
4613 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4614 req.cq_num_l2_entries =
4615 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4616 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4617 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4618 &req.cq_pg_size_cq_lvl,
4622 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4623 ctx_pg = &ctx->vnic_mem;
4624 req.vnic_num_vnic_entries =
4625 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4626 req.vnic_num_ring_table_entries =
4627 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4628 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4629 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4630 &req.vnic_pg_size_vnic_lvl,
4631 &req.vnic_page_dir);
4634 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4635 ctx_pg = &ctx->stat_mem;
4636 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4637 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4638 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4639 &req.stat_pg_size_stat_lvl,
4640 &req.stat_page_dir);
4643 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4644 num_entries = &req.tqm_sp_num_entries;
4645 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4646 pg_dir = &req.tqm_sp_page_dir;
4647 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4648 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4649 if (!(enables & ena))
4652 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4654 ctx_pg = ctx->tqm_mem[i];
4655 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4656 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4659 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4660 HWRM_CHECK_RESULT();
4666 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4668 struct hwrm_port_qstats_ext_input req = {0};
4669 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4670 struct bnxt_pf_info *pf = &bp->pf;
4673 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4674 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4677 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4679 req.port_id = rte_cpu_to_le_16(pf->port_id);
4680 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4681 req.tx_stat_host_addr =
4682 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4684 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4686 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4687 req.rx_stat_host_addr =
4688 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4690 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4692 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4695 bp->fw_rx_port_stats_ext_size = 0;
4696 bp->fw_tx_port_stats_ext_size = 0;
4698 bp->fw_rx_port_stats_ext_size =
4699 rte_le_to_cpu_16(resp->rx_stat_size);
4700 bp->fw_tx_port_stats_ext_size =
4701 rte_le_to_cpu_16(resp->tx_stat_size);
4704 HWRM_CHECK_RESULT();
4711 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4713 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4714 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4715 bp->hwrm_cmd_resp_addr;
4718 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4719 req.tunnel_type = type;
4720 req.dest_fid = bp->fw_fid;
4721 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4722 HWRM_CHECK_RESULT();
4730 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4732 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4733 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4734 bp->hwrm_cmd_resp_addr;
4737 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4738 req.tunnel_type = type;
4739 req.dest_fid = bp->fw_fid;
4740 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4741 HWRM_CHECK_RESULT();
4748 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4750 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4751 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4752 bp->hwrm_cmd_resp_addr;
4755 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4756 req.src_fid = bp->fw_fid;
4757 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4758 HWRM_CHECK_RESULT();
4761 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4768 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4771 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4772 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4773 bp->hwrm_cmd_resp_addr;
4776 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4777 req.src_fid = bp->fw_fid;
4778 req.tunnel_type = tun_type;
4779 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4780 HWRM_CHECK_RESULT();
4783 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4785 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4792 int bnxt_hwrm_set_mac(struct bnxt *bp)
4794 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4795 struct hwrm_func_vf_cfg_input req = {0};
4801 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4804 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4805 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4807 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4809 HWRM_CHECK_RESULT();
4811 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4817 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4819 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4820 struct hwrm_func_drv_if_change_input req = {0};
4824 if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4827 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4828 * If we issue FUNC_DRV_IF_CHANGE with flags down before
4829 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4831 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4834 HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4838 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4840 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4842 HWRM_CHECK_RESULT();
4843 flags = rte_le_to_cpu_32(resp->flags);
4849 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4850 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4851 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4857 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4859 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4860 struct bnxt_error_recovery_info *info = bp->recovery_info;
4861 struct hwrm_error_recovery_qcfg_input req = {0};
4866 /* Older FW does not have error recovery support */
4867 if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4871 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4873 bp->recovery_info = info;
4877 memset(info, 0, sizeof(*info));
4880 HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4882 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4884 HWRM_CHECK_RESULT();
4886 flags = rte_le_to_cpu_32(resp->flags);
4887 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4888 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4889 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4890 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4892 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4893 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4898 /* FW returned values are in units of 100msec */
4899 info->driver_polling_freq =
4900 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4901 info->master_func_wait_period =
4902 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4903 info->normal_func_wait_period =
4904 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4905 info->master_func_wait_period_after_reset =
4906 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4907 info->max_bailout_time_after_reset =
4908 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4909 info->status_regs[BNXT_FW_STATUS_REG] =
4910 rte_le_to_cpu_32(resp->fw_health_status_reg);
4911 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4912 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4913 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4914 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4915 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4916 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4917 info->reg_array_cnt =
4918 rte_le_to_cpu_32(resp->reg_array_cnt);
4920 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4925 for (i = 0; i < info->reg_array_cnt; i++) {
4926 info->reset_reg[i] =
4927 rte_le_to_cpu_32(resp->reset_reg[i]);
4928 info->reset_reg_val[i] =
4929 rte_le_to_cpu_32(resp->reset_reg_val[i]);
4930 info->delay_after_reset[i] =
4931 resp->delay_after_reset[i];
4936 /* Map the FW status registers */
4938 rc = bnxt_map_fw_health_status_regs(bp);
4941 rte_free(bp->recovery_info);
4942 bp->recovery_info = NULL;
4947 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4949 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4950 struct hwrm_fw_reset_input req = {0};
4956 HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4958 req.embedded_proc_type =
4959 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4960 req.selfrst_status =
4961 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4962 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4964 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4967 HWRM_CHECK_RESULT();
4973 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4975 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4976 struct hwrm_port_ts_query_input req = {0};
4977 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4984 HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4987 case BNXT_PTP_FLAGS_PATH_TX:
4988 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4990 case BNXT_PTP_FLAGS_PATH_RX:
4991 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4993 case BNXT_PTP_FLAGS_CURRENT_TIME:
4994 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
4998 req.flags = rte_cpu_to_le_32(flags);
4999 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5001 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5003 HWRM_CHECK_RESULT();
5006 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5008 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5015 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5017 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5018 bp->hwrm_cmd_resp_addr;
5019 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5023 if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5026 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5028 "Not a PF or trusted VF. Command not supported\n");
5032 HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5033 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5035 HWRM_CHECK_RESULT();
5036 flags = rte_le_to_cpu_32(resp->flags);
5039 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5040 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5041 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");