1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SHORT_CMD_TIMEOUT 50000
31 #define HWRM_SPEC_CODE_1_8_3 0x10803
32 #define HWRM_VERSION_1_9_1 0x10901
33 #define HWRM_VERSION_1_9_2 0x10903
35 struct bnxt_plcmodes_cfg {
37 uint16_t jumbo_thresh;
39 uint16_t hds_threshold;
42 static int page_getenum(size_t size)
58 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
59 return sizeof(void *) * 8 - 1;
62 static int page_roundup(size_t size)
64 return 1 << page_getenum(size);
67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
71 if (rmem->nr_pages > 1) {
73 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
75 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
80 * HWRM Functions (sent to HWRM)
81 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
82 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
83 * command was failed by the ChiMP.
86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
87 uint32_t msg_len, bool use_kong_mb)
90 struct input *req = msg;
91 struct output *resp = bp->hwrm_cmd_resp_addr;
95 uint16_t max_req_len = bp->max_req_len;
96 struct hwrm_short_input short_input = { 0 };
97 uint16_t bar_offset = use_kong_mb ?
98 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
99 uint16_t mb_trigger_offset = use_kong_mb ?
100 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
103 /* Do not send HWRM commands to firmware in error state */
104 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
107 /* For VER_GET command, set timeout as 50ms */
108 if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
109 timeout = HWRM_SHORT_CMD_TIMEOUT;
111 timeout = HWRM_CMD_TIMEOUT;
113 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
114 msg_len > bp->max_req_len) {
115 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
117 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
118 memcpy(short_cmd_req, req, msg_len);
120 short_input.req_type = rte_cpu_to_le_16(req->req_type);
121 short_input.signature = rte_cpu_to_le_16(
122 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
123 short_input.size = rte_cpu_to_le_16(msg_len);
124 short_input.req_addr =
125 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
127 data = (uint32_t *)&short_input;
128 msg_len = sizeof(short_input);
130 /* Sync memory write before updating doorbell */
133 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
136 /* Write request msg to hwrm channel */
137 for (i = 0; i < msg_len; i += 4) {
138 bar = (uint8_t *)bp->bar0 + bar_offset + i;
139 rte_write32(*data, bar);
143 /* Zero the rest of the request space */
144 for (; i < max_req_len; i += 4) {
145 bar = (uint8_t *)bp->bar0 + bar_offset + i;
149 /* Ring channel doorbell */
150 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
153 /* Poll for the valid bit */
154 for (i = 0; i < timeout; i++) {
155 /* Sanity check on the resp->resp_len */
157 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
158 /* Last byte of resp contains the valid key */
159 valid = (uint8_t *)resp + resp->resp_len - 1;
160 if (*valid == HWRM_RESP_VALID_KEY)
167 /* Suppress VER_GET timeout messages during reset recovery */
168 if (bp->flags & BNXT_FLAG_FW_RESET &&
169 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
172 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
180 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
181 * spinlock, and does initial processing.
183 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
184 * releases the spinlock only if it returns. If the regular int return codes
185 * are not used by the function, HWRM_CHECK_RESULT() should not be used
186 * directly, rather it should be copied and modified to suit the function.
188 * HWRM_UNLOCK() must be called after all response processing is completed.
190 #define HWRM_PREP(req, type, kong) do { \
191 rte_spinlock_lock(&bp->hwrm_lock); \
192 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
193 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
194 req.cmpl_ring = rte_cpu_to_le_16(-1); \
195 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
196 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
197 req.target_id = rte_cpu_to_le_16(0xffff); \
198 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
201 #define HWRM_CHECK_RESULT_SILENT() do {\
203 rte_spinlock_unlock(&bp->hwrm_lock); \
206 if (resp->error_code) { \
207 rc = rte_le_to_cpu_16(resp->error_code); \
208 rte_spinlock_unlock(&bp->hwrm_lock); \
213 #define HWRM_CHECK_RESULT() do {\
215 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
216 rte_spinlock_unlock(&bp->hwrm_lock); \
217 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
223 if (resp->error_code) { \
224 rc = rte_le_to_cpu_16(resp->error_code); \
225 if (resp->resp_len >= 16) { \
226 struct hwrm_err_output *tmp_hwrm_err_op = \
229 "error %d:%d:%08x:%04x\n", \
230 rc, tmp_hwrm_err_op->cmd_err, \
232 tmp_hwrm_err_op->opaque_0), \
234 tmp_hwrm_err_op->opaque_1)); \
236 PMD_DRV_LOG(ERR, "error %d\n", rc); \
238 rte_spinlock_unlock(&bp->hwrm_lock); \
239 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
247 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
249 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
252 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
253 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
255 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
256 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
259 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
267 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
268 struct bnxt_vnic_info *vnic,
270 struct bnxt_vlan_table_entry *vlan_table)
273 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
274 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
277 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
280 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
281 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
283 /* FIXME add multicast flag, when multicast adding options is supported
286 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
287 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
288 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
289 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
290 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
291 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
292 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
293 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
294 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
295 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
296 if (vnic->mc_addr_cnt) {
297 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
298 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
299 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
302 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
303 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
304 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
305 rte_mem_virt2iova(vlan_table));
306 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
308 req.mask = rte_cpu_to_le_32(mask);
310 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
318 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
320 struct bnxt_vlan_antispoof_table_entry *vlan_table)
323 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
324 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
325 bp->hwrm_cmd_resp_addr;
328 * Older HWRM versions did not support this command, and the set_rx_mask
329 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
330 * removed from set_rx_mask call, and this command was added.
332 * This command is also present from 1.7.8.11 and higher,
335 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
336 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
337 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
342 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
343 req.fid = rte_cpu_to_le_16(fid);
345 req.vlan_tag_mask_tbl_addr =
346 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
347 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
349 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
357 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
358 struct bnxt_filter_info *filter)
361 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
362 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
364 if (filter->fw_l2_filter_id == UINT64_MAX)
367 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
369 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
371 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
376 filter->fw_l2_filter_id = UINT64_MAX;
381 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
383 struct bnxt_filter_info *filter)
386 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
387 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
388 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
389 const struct rte_eth_vmdq_rx_conf *conf =
390 &dev_conf->rx_adv_conf.vmdq_rx_conf;
391 uint32_t enables = 0;
392 uint16_t j = dst_id - 1;
394 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
395 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
396 conf->pool_map[j].pools & (1UL << j)) {
398 "Add vlan %u to vmdq pool %u\n",
399 conf->pool_map[j].vlan_id, j);
401 filter->l2_ivlan = conf->pool_map[j].vlan_id;
403 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
404 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
407 if (filter->fw_l2_filter_id != UINT64_MAX)
408 bnxt_hwrm_clear_l2_filter(bp, filter);
410 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
412 req.flags = rte_cpu_to_le_32(filter->flags);
414 rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
416 enables = filter->enables |
417 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
418 req.dst_id = rte_cpu_to_le_16(dst_id);
421 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
422 memcpy(req.l2_addr, filter->l2_addr,
425 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
426 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
429 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
430 req.l2_ovlan = filter->l2_ovlan;
432 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
433 req.l2_ivlan = filter->l2_ivlan;
435 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
436 req.l2_ovlan_mask = filter->l2_ovlan_mask;
438 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
439 req.l2_ivlan_mask = filter->l2_ivlan_mask;
440 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
441 req.src_id = rte_cpu_to_le_32(filter->src_id);
442 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
443 req.src_type = filter->src_type;
445 req.enables = rte_cpu_to_le_32(enables);
447 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
451 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
457 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
459 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
460 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
467 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
470 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
473 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
474 if (ptp->tx_tstamp_en)
475 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
478 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
479 req.flags = rte_cpu_to_le_32(flags);
480 req.enables = rte_cpu_to_le_32
481 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
482 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
484 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
490 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
493 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
494 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
495 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
497 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
501 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
503 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
505 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
509 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
512 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
516 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
517 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
518 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
519 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
520 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
521 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
522 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
523 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
524 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
525 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
526 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
527 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
528 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
529 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
530 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
531 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
532 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
533 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
541 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
544 struct hwrm_func_qcaps_input req = {.req_type = 0 };
545 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
546 uint16_t new_max_vfs;
550 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
552 req.fid = rte_cpu_to_le_16(0xffff);
554 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
558 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
559 flags = rte_le_to_cpu_32(resp->flags);
561 bp->pf.port_id = resp->port_id;
562 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
563 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
564 new_max_vfs = bp->pdev->max_vfs;
565 if (new_max_vfs != bp->pf.max_vfs) {
567 rte_free(bp->pf.vf_info);
568 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
569 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
570 bp->pf.max_vfs = new_max_vfs;
571 for (i = 0; i < new_max_vfs; i++) {
572 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
573 bp->pf.vf_info[i].vlan_table =
574 rte_zmalloc("VF VLAN table",
577 if (bp->pf.vf_info[i].vlan_table == NULL)
579 "Fail to alloc VLAN table for VF %d\n",
583 bp->pf.vf_info[i].vlan_table);
584 bp->pf.vf_info[i].vlan_as_table =
585 rte_zmalloc("VF VLAN AS table",
588 if (bp->pf.vf_info[i].vlan_as_table == NULL)
590 "Alloc VLAN AS table for VF %d fail\n",
594 bp->pf.vf_info[i].vlan_as_table);
595 STAILQ_INIT(&bp->pf.vf_info[i].filter);
600 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
601 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
602 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
603 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
604 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
605 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
606 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
607 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
609 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
610 /* TODO: For now, do not support VMDq/RFS on VFs. */
615 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
619 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
621 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
622 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
623 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
624 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
626 bnxt_hwrm_ptp_qcfg(bp);
630 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
631 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
633 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
634 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
635 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
637 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
645 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
649 rc = __bnxt_hwrm_func_qcaps(bp);
650 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
651 rc = bnxt_alloc_ctx_mem(bp);
655 rc = bnxt_hwrm_func_resc_qcaps(bp);
657 bp->flags |= BNXT_FLAG_NEW_RM;
663 int bnxt_hwrm_func_reset(struct bnxt *bp)
666 struct hwrm_func_reset_input req = {.req_type = 0 };
667 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
669 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
671 req.enables = rte_cpu_to_le_32(0);
673 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
681 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
685 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
686 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
688 if (bp->flags & BNXT_FLAG_REGISTERED)
691 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
692 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
693 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
695 /* PFs and trusted VFs should indicate the support of the
696 * Master capability on non Stingray platform
698 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
699 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
701 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
702 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
703 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
704 req.ver_maj = RTE_VER_YEAR;
705 req.ver_min = RTE_VER_MONTH;
706 req.ver_upd = RTE_VER_MINOR;
709 req.enables |= rte_cpu_to_le_32(
710 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
711 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
712 RTE_MIN(sizeof(req.vf_req_fwd),
713 sizeof(bp->pf.vf_req_fwd)));
716 * PF can sniff HWRM API issued by VF. This can be set up by
717 * linux driver and inherited by the DPDK PF driver. Clear
718 * this HWRM sniffer list in FW because DPDK PF driver does
721 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
724 req.flags = rte_cpu_to_le_32(flags);
726 req.async_event_fwd[0] |=
727 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
728 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
729 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
730 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
731 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
732 req.async_event_fwd[0] |=
733 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
734 req.async_event_fwd[1] |=
735 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
736 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
738 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
742 flags = rte_le_to_cpu_32(resp->flags);
743 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
744 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
748 bp->flags |= BNXT_FLAG_REGISTERED;
753 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
755 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
758 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
761 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
766 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
767 struct hwrm_func_vf_cfg_input req = {0};
769 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
771 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
772 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
773 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
774 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
775 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
777 if (BNXT_HAS_RING_GRPS(bp)) {
778 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
779 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
782 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
783 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
784 AGG_RING_MULTIPLIER);
785 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
787 BNXT_NUM_ASYNC_CPR(bp));
788 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
790 BNXT_NUM_ASYNC_CPR(bp));
791 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
792 if (bp->vf_resv_strategy ==
793 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
794 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
795 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
796 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
797 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
798 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
799 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
803 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
804 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
805 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
806 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
807 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
808 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
810 if (test && BNXT_HAS_RING_GRPS(bp))
811 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
813 req.flags = rte_cpu_to_le_32(flags);
814 req.enables |= rte_cpu_to_le_32(enables);
816 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
819 HWRM_CHECK_RESULT_SILENT();
827 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
830 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
831 struct hwrm_func_resource_qcaps_input req = {0};
833 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
834 req.fid = rte_cpu_to_le_16(0xffff);
836 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
841 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
842 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
843 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
844 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
845 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
846 /* func_resource_qcaps does not return max_rx_em_flows.
847 * So use the value provided by func_qcaps.
850 rte_le_to_cpu_16(resp->max_l2_ctxs) +
852 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
853 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
855 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
856 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
857 if (bp->vf_resv_strategy >
858 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
859 bp->vf_resv_strategy =
860 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
866 int bnxt_hwrm_ver_get(struct bnxt *bp)
869 struct hwrm_ver_get_input req = {.req_type = 0 };
870 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
872 uint16_t max_resp_len;
873 char type[RTE_MEMZONE_NAMESIZE];
874 uint32_t dev_caps_cfg;
876 bp->max_req_len = HWRM_MAX_REQ_LEN;
877 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
879 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
880 req.hwrm_intf_min = HWRM_VERSION_MINOR;
881 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
883 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
885 if (bp->flags & BNXT_FLAG_FW_RESET)
886 HWRM_CHECK_RESULT_SILENT();
890 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
891 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
892 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
893 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
894 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
895 (resp->hwrm_fw_min_8b << 16) |
896 (resp->hwrm_fw_bld_8b << 8) |
897 resp->hwrm_fw_rsvd_8b;
898 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
899 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
901 fw_version = resp->hwrm_intf_maj_8b << 16;
902 fw_version |= resp->hwrm_intf_min_8b << 8;
903 fw_version |= resp->hwrm_intf_upd_8b;
904 bp->hwrm_spec_code = fw_version;
906 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
907 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
912 if (bp->max_req_len > resp->max_req_win_len) {
913 PMD_DRV_LOG(ERR, "Unsupported request length\n");
916 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
917 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
918 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
919 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
921 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
922 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
924 if (bp->max_resp_len != max_resp_len) {
925 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
926 bp->pdev->addr.domain, bp->pdev->addr.bus,
927 bp->pdev->addr.devid, bp->pdev->addr.function);
929 rte_free(bp->hwrm_cmd_resp_addr);
931 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
932 if (bp->hwrm_cmd_resp_addr == NULL) {
936 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
937 bp->hwrm_cmd_resp_dma_addr =
938 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
939 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
941 "Unable to map response buffer to physical memory.\n");
945 bp->max_resp_len = max_resp_len;
949 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
951 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
952 PMD_DRV_LOG(DEBUG, "Short command supported\n");
953 bp->flags |= BNXT_FLAG_SHORT_CMD;
957 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
959 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
960 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
961 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
962 bp->pdev->addr.domain, bp->pdev->addr.bus,
963 bp->pdev->addr.devid, bp->pdev->addr.function);
965 rte_free(bp->hwrm_short_cmd_req_addr);
967 bp->hwrm_short_cmd_req_addr =
968 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
969 if (bp->hwrm_short_cmd_req_addr == NULL) {
973 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
974 bp->hwrm_short_cmd_req_dma_addr =
975 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
976 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
977 rte_free(bp->hwrm_short_cmd_req_addr);
979 "Unable to map buffer to physical memory.\n");
985 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
986 bp->flags |= BNXT_FLAG_KONG_MB_EN;
987 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
990 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
991 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
998 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1001 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1002 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1004 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1007 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1010 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1012 HWRM_CHECK_RESULT();
1018 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1021 struct hwrm_port_phy_cfg_input req = {0};
1022 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1023 uint32_t enables = 0;
1025 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1027 if (conf->link_up) {
1028 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1029 if (bp->link_info.auto_mode && conf->link_speed) {
1030 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1031 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1034 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1035 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1036 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1038 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1039 * any auto mode, even "none".
1041 if (!conf->link_speed) {
1042 /* No speeds specified. Enable AutoNeg - all speeds */
1044 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1046 /* AutoNeg - Advertise speeds specified. */
1047 if (conf->auto_link_speed_mask &&
1048 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1050 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1051 req.auto_link_speed_mask =
1052 conf->auto_link_speed_mask;
1054 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1057 req.auto_duplex = conf->duplex;
1058 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1059 req.auto_pause = conf->auto_pause;
1060 req.force_pause = conf->force_pause;
1061 /* Set force_pause if there is no auto or if there is a force */
1062 if (req.auto_pause && !req.force_pause)
1063 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1065 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1067 req.enables = rte_cpu_to_le_32(enables);
1070 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1071 PMD_DRV_LOG(INFO, "Force Link Down\n");
1074 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1076 HWRM_CHECK_RESULT();
1082 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1083 struct bnxt_link_info *link_info)
1086 struct hwrm_port_phy_qcfg_input req = {0};
1087 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1089 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1091 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1093 HWRM_CHECK_RESULT();
1095 link_info->phy_link_status = resp->link;
1096 link_info->link_up =
1097 (link_info->phy_link_status ==
1098 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1099 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1100 link_info->duplex = resp->duplex_cfg;
1101 link_info->pause = resp->pause;
1102 link_info->auto_pause = resp->auto_pause;
1103 link_info->force_pause = resp->force_pause;
1104 link_info->auto_mode = resp->auto_mode;
1105 link_info->phy_type = resp->phy_type;
1106 link_info->media_type = resp->media_type;
1108 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1109 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1110 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1111 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1112 link_info->phy_ver[0] = resp->phy_maj;
1113 link_info->phy_ver[1] = resp->phy_min;
1114 link_info->phy_ver[2] = resp->phy_bld;
1118 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1119 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1120 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1121 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1122 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1123 link_info->auto_link_speed_mask);
1124 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1125 link_info->force_link_speed);
1130 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1133 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1134 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1137 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1139 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1140 /* HWRM Version >= 1.9.1 */
1141 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1143 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1144 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1146 HWRM_CHECK_RESULT();
1148 #define GET_QUEUE_INFO(x) \
1149 bp->cos_queue[x].id = resp->queue_id##x; \
1150 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1163 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1164 bp->tx_cosq_id = bp->cos_queue[0].id;
1166 /* iterate and find the COSq profile to use for Tx */
1167 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1168 if (bp->cos_queue[i].profile ==
1169 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1170 bp->tx_cosq_id = bp->cos_queue[i].id;
1176 bp->max_tc = resp->max_configurable_queues;
1177 bp->max_lltc = resp->max_configurable_lossless_queues;
1178 if (bp->max_tc > BNXT_MAX_QUEUE)
1179 bp->max_tc = BNXT_MAX_QUEUE;
1180 bp->max_q = bp->max_tc;
1182 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1187 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1188 struct bnxt_ring *ring,
1189 uint32_t ring_type, uint32_t map_index,
1190 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1193 uint32_t enables = 0;
1194 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1195 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1196 struct rte_mempool *mb_pool;
1197 uint16_t rx_buf_size;
1199 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1201 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1202 req.fbo = rte_cpu_to_le_32(0);
1203 /* Association of ring index with doorbell index */
1204 req.logical_id = rte_cpu_to_le_16(map_index);
1205 req.length = rte_cpu_to_le_32(ring->ring_size);
1207 switch (ring_type) {
1208 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1209 req.ring_type = ring_type;
1210 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1211 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1212 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1213 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1215 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1217 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1218 req.ring_type = ring_type;
1219 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1220 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1221 if (BNXT_CHIP_THOR(bp)) {
1222 mb_pool = bp->rx_queues[0]->mb_pool;
1223 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1224 RTE_PKTMBUF_HEADROOM;
1225 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1227 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1229 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1231 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1233 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1234 req.ring_type = ring_type;
1235 if (BNXT_HAS_NQ(bp)) {
1236 /* Association of cp ring with nq */
1237 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1239 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1241 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1243 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1244 req.ring_type = ring_type;
1245 req.page_size = BNXT_PAGE_SHFT;
1246 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1248 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1249 req.ring_type = ring_type;
1250 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1252 mb_pool = bp->rx_queues[0]->mb_pool;
1253 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1254 RTE_PKTMBUF_HEADROOM;
1255 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1257 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1258 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1259 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1260 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1263 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1268 req.enables = rte_cpu_to_le_32(enables);
1270 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1272 if (rc || resp->error_code) {
1273 if (rc == 0 && resp->error_code)
1274 rc = rte_le_to_cpu_16(resp->error_code);
1275 switch (ring_type) {
1276 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1278 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1281 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1283 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1286 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1288 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1292 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1294 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1297 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1299 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1303 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1309 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1314 int bnxt_hwrm_ring_free(struct bnxt *bp,
1315 struct bnxt_ring *ring, uint32_t ring_type)
1318 struct hwrm_ring_free_input req = {.req_type = 0 };
1319 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1321 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1323 req.ring_type = ring_type;
1324 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1326 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1328 if (rc || resp->error_code) {
1329 if (rc == 0 && resp->error_code)
1330 rc = rte_le_to_cpu_16(resp->error_code);
1333 switch (ring_type) {
1334 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1335 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1338 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1339 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1342 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1343 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1346 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1348 "hwrm_ring_free nq failed. rc:%d\n", rc);
1350 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1352 "hwrm_ring_free agg failed. rc:%d\n", rc);
1355 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1363 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1366 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1367 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1369 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1371 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1372 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1373 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1374 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1376 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1378 HWRM_CHECK_RESULT();
1380 bp->grp_info[idx].fw_grp_id =
1381 rte_le_to_cpu_16(resp->ring_group_id);
1388 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1391 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1392 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1394 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1396 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1398 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1400 HWRM_CHECK_RESULT();
1403 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1407 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1410 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1411 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1413 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1416 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1418 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1420 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1422 HWRM_CHECK_RESULT();
1428 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1429 unsigned int idx __rte_unused)
1432 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1433 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1435 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1437 req.update_period_ms = rte_cpu_to_le_32(0);
1439 req.stats_dma_addr =
1440 rte_cpu_to_le_64(cpr->hw_stats_map);
1442 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1444 HWRM_CHECK_RESULT();
1446 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1453 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1454 unsigned int idx __rte_unused)
1457 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1458 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1460 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1462 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1464 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1466 HWRM_CHECK_RESULT();
1472 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1475 struct hwrm_vnic_alloc_input req = { 0 };
1476 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1478 if (!BNXT_HAS_RING_GRPS(bp))
1479 goto skip_ring_grps;
1481 /* map ring groups to this vnic */
1482 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1483 vnic->start_grp_id, vnic->end_grp_id);
1484 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1485 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1487 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1488 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1489 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1490 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1493 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1494 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1495 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1497 if (vnic->func_default)
1499 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1500 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1502 HWRM_CHECK_RESULT();
1504 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1506 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1510 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1511 struct bnxt_vnic_info *vnic,
1512 struct bnxt_plcmodes_cfg *pmode)
1515 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1516 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1518 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1520 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1522 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1524 HWRM_CHECK_RESULT();
1526 pmode->flags = rte_le_to_cpu_32(resp->flags);
1527 /* dflt_vnic bit doesn't exist in the _cfg command */
1528 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1529 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1530 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1531 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1538 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1539 struct bnxt_vnic_info *vnic,
1540 struct bnxt_plcmodes_cfg *pmode)
1543 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1544 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1546 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1547 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1551 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1553 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1554 req.flags = rte_cpu_to_le_32(pmode->flags);
1555 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1556 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1557 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1558 req.enables = rte_cpu_to_le_32(
1559 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1560 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1561 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1564 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1566 HWRM_CHECK_RESULT();
1572 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1575 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1576 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1577 struct bnxt_plcmodes_cfg pmodes = { 0 };
1578 uint32_t ctx_enable_flag = 0;
1579 uint32_t enables = 0;
1581 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1582 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1586 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1590 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1592 if (BNXT_CHIP_THOR(bp)) {
1593 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1594 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1595 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1597 req.default_rx_ring_id =
1598 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1599 req.default_cmpl_ring_id =
1600 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1601 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1602 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1606 /* Only RSS support for now TBD: COS & LB */
1607 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1608 if (vnic->lb_rule != 0xffff)
1609 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1610 if (vnic->cos_rule != 0xffff)
1611 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1612 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1613 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1614 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1616 enables |= ctx_enable_flag;
1617 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1618 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1619 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1620 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1623 req.enables = rte_cpu_to_le_32(enables);
1624 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1625 req.mru = rte_cpu_to_le_16(vnic->mru);
1626 /* Configure default VNIC only once. */
1627 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1629 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1630 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1632 if (vnic->vlan_strip)
1634 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1637 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1638 if (vnic->roce_dual)
1639 req.flags |= rte_cpu_to_le_32(
1640 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1641 if (vnic->roce_only)
1642 req.flags |= rte_cpu_to_le_32(
1643 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1644 if (vnic->rss_dflt_cr)
1645 req.flags |= rte_cpu_to_le_32(
1646 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1648 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1650 HWRM_CHECK_RESULT();
1653 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1658 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1662 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1663 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1665 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1666 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1669 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1672 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1673 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1674 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1676 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1678 HWRM_CHECK_RESULT();
1680 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1681 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1682 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1683 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1684 vnic->mru = rte_le_to_cpu_16(resp->mru);
1685 vnic->func_default = rte_le_to_cpu_32(
1686 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1687 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1688 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1689 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1690 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1691 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1692 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1693 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1694 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1695 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1696 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1703 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1704 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1708 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1709 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1710 bp->hwrm_cmd_resp_addr;
1712 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1714 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1715 HWRM_CHECK_RESULT();
1717 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1718 if (!BNXT_HAS_RING_GRPS(bp))
1719 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1720 else if (ctx_idx == 0)
1721 vnic->rss_rule = ctx_id;
1728 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1729 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1732 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1733 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1734 bp->hwrm_cmd_resp_addr;
1736 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1737 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1740 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1742 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1744 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1746 HWRM_CHECK_RESULT();
1752 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1755 struct hwrm_vnic_free_input req = {.req_type = 0 };
1756 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1758 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1759 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1763 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1765 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1767 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1769 HWRM_CHECK_RESULT();
1772 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1773 /* Configure default VNIC again if necessary. */
1774 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1775 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1781 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1785 int nr_ctxs = vnic->num_lb_ctxts;
1786 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1787 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1789 for (i = 0; i < nr_ctxs; i++) {
1790 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1792 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1793 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1794 req.hash_mode_flags = vnic->hash_mode;
1796 req.hash_key_tbl_addr =
1797 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1799 req.ring_grp_tbl_addr =
1800 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1801 i * HW_HASH_INDEX_SIZE);
1802 req.ring_table_pair_index = i;
1803 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1805 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1808 HWRM_CHECK_RESULT();
1815 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1816 struct bnxt_vnic_info *vnic)
1819 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1820 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1822 if (!vnic->rss_table)
1825 if (BNXT_CHIP_THOR(bp))
1826 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1828 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1830 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1831 req.hash_mode_flags = vnic->hash_mode;
1833 req.ring_grp_tbl_addr =
1834 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1835 req.hash_key_tbl_addr =
1836 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1837 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1838 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1840 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1842 HWRM_CHECK_RESULT();
1848 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1849 struct bnxt_vnic_info *vnic)
1852 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1853 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1856 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1857 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1861 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1863 req.flags = rte_cpu_to_le_32(
1864 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1866 req.enables = rte_cpu_to_le_32(
1867 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1869 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1870 size -= RTE_PKTMBUF_HEADROOM;
1872 req.jumbo_thresh = rte_cpu_to_le_16(size);
1873 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1875 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1877 HWRM_CHECK_RESULT();
1883 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1884 struct bnxt_vnic_info *vnic, bool enable)
1887 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1888 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1890 if (BNXT_CHIP_THOR(bp))
1893 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1896 req.enables = rte_cpu_to_le_32(
1897 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1898 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1899 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1900 req.flags = rte_cpu_to_le_32(
1901 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1902 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1903 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1904 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1905 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1906 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1907 req.max_agg_segs = rte_cpu_to_le_16(5);
1909 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1910 req.min_agg_len = rte_cpu_to_le_32(512);
1912 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1914 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1916 HWRM_CHECK_RESULT();
1922 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1924 struct hwrm_func_cfg_input req = {0};
1925 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1928 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1929 req.enables = rte_cpu_to_le_32(
1930 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1931 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1932 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1934 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1936 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1937 HWRM_CHECK_RESULT();
1940 bp->pf.vf_info[vf].random_mac = false;
1945 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1949 struct hwrm_func_qstats_input req = {.req_type = 0};
1950 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1952 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1954 req.fid = rte_cpu_to_le_16(fid);
1956 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1958 HWRM_CHECK_RESULT();
1961 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1968 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1969 struct rte_eth_stats *stats)
1972 struct hwrm_func_qstats_input req = {.req_type = 0};
1973 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1975 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1977 req.fid = rte_cpu_to_le_16(fid);
1979 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1981 HWRM_CHECK_RESULT();
1983 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1984 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1985 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1986 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1987 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1988 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1990 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1991 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1992 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1993 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1994 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1995 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1997 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1998 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1999 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2006 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2009 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2010 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2012 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2014 req.fid = rte_cpu_to_le_16(fid);
2016 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2018 HWRM_CHECK_RESULT();
2025 * HWRM utility functions
2028 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2033 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2034 struct bnxt_tx_queue *txq;
2035 struct bnxt_rx_queue *rxq;
2036 struct bnxt_cp_ring_info *cpr;
2038 if (i >= bp->rx_cp_nr_rings) {
2039 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2042 rxq = bp->rx_queues[i];
2046 rc = bnxt_hwrm_stat_clear(bp, cpr);
2053 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2057 struct bnxt_cp_ring_info *cpr;
2059 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2061 if (i >= bp->rx_cp_nr_rings) {
2062 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2064 cpr = bp->rx_queues[i]->cp_ring;
2065 if (BNXT_HAS_RING_GRPS(bp))
2066 bp->grp_info[i].fw_stats_ctx = -1;
2068 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2069 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2070 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2078 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2083 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2084 struct bnxt_tx_queue *txq;
2085 struct bnxt_rx_queue *rxq;
2086 struct bnxt_cp_ring_info *cpr;
2088 if (i >= bp->rx_cp_nr_rings) {
2089 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2092 rxq = bp->rx_queues[i];
2096 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2104 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2109 if (!BNXT_HAS_RING_GRPS(bp))
2112 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2114 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2117 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2125 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2127 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2129 bnxt_hwrm_ring_free(bp, cp_ring,
2130 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2131 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2132 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2133 sizeof(*cpr->cp_desc_ring));
2134 cpr->cp_raw_cons = 0;
2138 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2140 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2142 bnxt_hwrm_ring_free(bp, cp_ring,
2143 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2144 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2145 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2146 sizeof(*cpr->cp_desc_ring));
2147 cpr->cp_raw_cons = 0;
2151 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2153 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2154 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2155 struct bnxt_ring *ring = rxr->rx_ring_struct;
2156 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2158 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2159 bnxt_hwrm_ring_free(bp, ring,
2160 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2161 ring->fw_ring_id = INVALID_HW_RING_ID;
2162 if (BNXT_HAS_RING_GRPS(bp))
2163 bp->grp_info[queue_index].rx_fw_ring_id =
2165 memset(rxr->rx_desc_ring, 0,
2166 rxr->rx_ring_struct->ring_size *
2167 sizeof(*rxr->rx_desc_ring));
2168 memset(rxr->rx_buf_ring, 0,
2169 rxr->rx_ring_struct->ring_size *
2170 sizeof(*rxr->rx_buf_ring));
2173 ring = rxr->ag_ring_struct;
2174 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2175 bnxt_hwrm_ring_free(bp, ring,
2176 BNXT_CHIP_THOR(bp) ?
2177 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2178 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2179 ring->fw_ring_id = INVALID_HW_RING_ID;
2180 memset(rxr->ag_buf_ring, 0,
2181 rxr->ag_ring_struct->ring_size *
2182 sizeof(*rxr->ag_buf_ring));
2184 if (BNXT_HAS_RING_GRPS(bp))
2185 bp->grp_info[queue_index].ag_fw_ring_id =
2188 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2189 bnxt_free_cp_ring(bp, cpr);
2191 bnxt_free_nq_ring(bp, rxq->nq_ring);
2194 if (BNXT_HAS_RING_GRPS(bp))
2195 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2198 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2202 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2203 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2204 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2205 struct bnxt_ring *ring = txr->tx_ring_struct;
2206 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2208 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2209 bnxt_hwrm_ring_free(bp, ring,
2210 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2211 ring->fw_ring_id = INVALID_HW_RING_ID;
2212 memset(txr->tx_desc_ring, 0,
2213 txr->tx_ring_struct->ring_size *
2214 sizeof(*txr->tx_desc_ring));
2215 memset(txr->tx_buf_ring, 0,
2216 txr->tx_ring_struct->ring_size *
2217 sizeof(*txr->tx_buf_ring));
2221 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2222 bnxt_free_cp_ring(bp, cpr);
2223 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2225 bnxt_free_nq_ring(bp, txq->nq_ring);
2229 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2230 bnxt_free_hwrm_rx_ring(bp, i);
2235 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2240 if (!BNXT_HAS_RING_GRPS(bp))
2243 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2244 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2251 void bnxt_free_hwrm_resources(struct bnxt *bp)
2253 /* Release memzone */
2254 rte_free(bp->hwrm_cmd_resp_addr);
2255 rte_free(bp->hwrm_short_cmd_req_addr);
2256 bp->hwrm_cmd_resp_addr = NULL;
2257 bp->hwrm_short_cmd_req_addr = NULL;
2258 bp->hwrm_cmd_resp_dma_addr = 0;
2259 bp->hwrm_short_cmd_req_dma_addr = 0;
2262 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2264 struct rte_pci_device *pdev = bp->pdev;
2265 char type[RTE_MEMZONE_NAMESIZE];
2267 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2268 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2269 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2270 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2271 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2272 if (bp->hwrm_cmd_resp_addr == NULL)
2274 bp->hwrm_cmd_resp_dma_addr =
2275 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2276 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2278 "unable to map response address to physical memory\n");
2281 rte_spinlock_init(&bp->hwrm_lock);
2286 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2288 struct bnxt_filter_info *filter;
2291 STAILQ_FOREACH(filter, &vnic->filter, next) {
2292 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2293 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2294 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2295 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2297 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2298 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2306 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2308 struct bnxt_filter_info *filter;
2309 struct rte_flow *flow;
2312 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2313 filter = flow->filter;
2314 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2315 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2316 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2317 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2318 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2320 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2322 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2330 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2332 struct bnxt_filter_info *filter;
2335 STAILQ_FOREACH(filter, &vnic->filter, next) {
2336 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2337 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2339 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2340 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2343 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2351 void bnxt_free_tunnel_ports(struct bnxt *bp)
2353 if (bp->vxlan_port_cnt)
2354 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2355 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2357 if (bp->geneve_port_cnt)
2358 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2359 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2360 bp->geneve_port = 0;
2363 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2367 if (bp->vnic_info == NULL)
2371 * Cleanup VNICs in reverse order, to make sure the L2 filter
2372 * from vnic0 is last to be cleaned up.
2374 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2375 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2377 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2378 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2382 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2384 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2386 if (BNXT_CHIP_THOR(bp)) {
2387 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2388 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2389 vnic->fw_grp_ids[j]);
2390 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2392 vnic->num_lb_ctxts = 0;
2394 bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2395 vnic->rss_rule = INVALID_HW_RING_ID;
2398 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2400 bnxt_hwrm_vnic_free(bp, vnic);
2402 rte_free(vnic->fw_grp_ids);
2404 /* Ring resources */
2405 bnxt_free_all_hwrm_rings(bp);
2406 bnxt_free_all_hwrm_ring_grps(bp);
2407 bnxt_free_all_hwrm_stat_ctxs(bp);
2408 bnxt_free_tunnel_ports(bp);
2411 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2413 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2415 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2416 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2418 switch (conf_link_speed) {
2419 case ETH_LINK_SPEED_10M_HD:
2420 case ETH_LINK_SPEED_100M_HD:
2422 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2424 return hw_link_duplex;
2427 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2429 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2432 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2434 uint16_t eth_link_speed = 0;
2436 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2437 return ETH_LINK_SPEED_AUTONEG;
2439 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2440 case ETH_LINK_SPEED_100M:
2441 case ETH_LINK_SPEED_100M_HD:
2444 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2446 case ETH_LINK_SPEED_1G:
2448 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2450 case ETH_LINK_SPEED_2_5G:
2452 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2454 case ETH_LINK_SPEED_10G:
2456 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2458 case ETH_LINK_SPEED_20G:
2460 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2462 case ETH_LINK_SPEED_25G:
2464 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2466 case ETH_LINK_SPEED_40G:
2468 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2470 case ETH_LINK_SPEED_50G:
2472 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2474 case ETH_LINK_SPEED_100G:
2476 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2480 "Unsupported link speed %d; default to AUTO\n",
2484 return eth_link_speed;
2487 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2488 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2489 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2490 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2492 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2496 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2499 if (link_speed & ETH_LINK_SPEED_FIXED) {
2500 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2502 if (one_speed & (one_speed - 1)) {
2504 "Invalid advertised speeds (%u) for port %u\n",
2505 link_speed, port_id);
2508 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2510 "Unsupported advertised speed (%u) for port %u\n",
2511 link_speed, port_id);
2515 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2517 "Unsupported advertised speeds (%u) for port %u\n",
2518 link_speed, port_id);
2526 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2530 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2531 if (bp->link_info.support_speeds)
2532 return bp->link_info.support_speeds;
2533 link_speed = BNXT_SUPPORTED_SPEEDS;
2536 if (link_speed & ETH_LINK_SPEED_100M)
2537 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2538 if (link_speed & ETH_LINK_SPEED_100M_HD)
2539 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2540 if (link_speed & ETH_LINK_SPEED_1G)
2541 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2542 if (link_speed & ETH_LINK_SPEED_2_5G)
2543 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2544 if (link_speed & ETH_LINK_SPEED_10G)
2545 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2546 if (link_speed & ETH_LINK_SPEED_20G)
2547 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2548 if (link_speed & ETH_LINK_SPEED_25G)
2549 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2550 if (link_speed & ETH_LINK_SPEED_40G)
2551 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2552 if (link_speed & ETH_LINK_SPEED_50G)
2553 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2554 if (link_speed & ETH_LINK_SPEED_100G)
2555 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2559 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2561 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2563 switch (hw_link_speed) {
2564 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2565 eth_link_speed = ETH_SPEED_NUM_100M;
2567 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2568 eth_link_speed = ETH_SPEED_NUM_1G;
2570 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2571 eth_link_speed = ETH_SPEED_NUM_2_5G;
2573 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2574 eth_link_speed = ETH_SPEED_NUM_10G;
2576 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2577 eth_link_speed = ETH_SPEED_NUM_20G;
2579 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2580 eth_link_speed = ETH_SPEED_NUM_25G;
2582 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2583 eth_link_speed = ETH_SPEED_NUM_40G;
2585 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2586 eth_link_speed = ETH_SPEED_NUM_50G;
2588 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2589 eth_link_speed = ETH_SPEED_NUM_100G;
2591 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2593 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2597 return eth_link_speed;
2600 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2602 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2604 switch (hw_link_duplex) {
2605 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2606 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2608 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2610 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2611 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2614 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2618 return eth_link_duplex;
2621 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2624 struct bnxt_link_info *link_info = &bp->link_info;
2626 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2629 "Get link config failed with rc %d\n", rc);
2632 if (link_info->link_speed)
2634 bnxt_parse_hw_link_speed(link_info->link_speed);
2636 link->link_speed = ETH_SPEED_NUM_NONE;
2637 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2638 link->link_status = link_info->link_up;
2639 link->link_autoneg = link_info->auto_mode ==
2640 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2641 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2646 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2649 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2650 struct bnxt_link_info link_req;
2651 uint16_t speed, autoneg;
2653 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2656 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2657 bp->eth_dev->data->port_id);
2661 memset(&link_req, 0, sizeof(link_req));
2662 link_req.link_up = link_up;
2666 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2667 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2668 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2669 /* Autoneg can be done only when the FW allows */
2670 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2671 bp->link_info.force_link_speed)) {
2672 link_req.phy_flags |=
2673 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2674 link_req.auto_link_speed_mask =
2675 bnxt_parse_eth_link_speed_mask(bp,
2676 dev_conf->link_speeds);
2678 if (bp->link_info.phy_type ==
2679 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2680 bp->link_info.phy_type ==
2681 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2682 bp->link_info.media_type ==
2683 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2684 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2688 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2689 /* If user wants a particular speed try that first. */
2691 link_req.link_speed = speed;
2692 else if (bp->link_info.force_link_speed)
2693 link_req.link_speed = bp->link_info.force_link_speed;
2695 link_req.link_speed = bp->link_info.auto_link_speed;
2697 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2698 link_req.auto_pause = bp->link_info.auto_pause;
2699 link_req.force_pause = bp->link_info.force_pause;
2702 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2705 "Set link config failed with rc %d\n", rc);
2713 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2715 struct hwrm_func_qcfg_input req = {0};
2716 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2720 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2721 req.fid = rte_cpu_to_le_16(0xffff);
2723 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2725 HWRM_CHECK_RESULT();
2727 /* Hard Coded.. 0xfff VLAN ID mask */
2728 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2729 flags = rte_le_to_cpu_16(resp->flags);
2730 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2731 bp->flags |= BNXT_FLAG_MULTI_HOST;
2733 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2734 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2735 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2736 } else if (BNXT_VF(bp) &&
2737 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2738 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2739 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2745 switch (resp->port_partition_type) {
2746 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2747 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2748 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2750 bp->port_partition_type = resp->port_partition_type;
2753 bp->port_partition_type = 0;
2762 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2763 struct hwrm_func_qcaps_output *qcaps)
2765 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2766 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2767 sizeof(qcaps->mac_address));
2768 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2769 qcaps->max_rx_rings = fcfg->num_rx_rings;
2770 qcaps->max_tx_rings = fcfg->num_tx_rings;
2771 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2772 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2774 qcaps->first_vf_id = 0;
2775 qcaps->max_vnics = fcfg->num_vnics;
2776 qcaps->max_decap_records = 0;
2777 qcaps->max_encap_records = 0;
2778 qcaps->max_tx_wm_flows = 0;
2779 qcaps->max_tx_em_flows = 0;
2780 qcaps->max_rx_wm_flows = 0;
2781 qcaps->max_rx_em_flows = 0;
2782 qcaps->max_flow_id = 0;
2783 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2784 qcaps->max_sp_tx_rings = 0;
2785 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2788 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2790 struct hwrm_func_cfg_input req = {0};
2791 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2795 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2796 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2797 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2798 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2799 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2800 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2801 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2802 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2803 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2805 if (BNXT_HAS_RING_GRPS(bp)) {
2806 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2807 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2808 } else if (BNXT_HAS_NQ(bp)) {
2809 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2810 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2813 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2814 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2815 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2816 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2818 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2819 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2820 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2821 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2822 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2823 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2824 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2825 req.fid = rte_cpu_to_le_16(0xffff);
2826 req.enables = rte_cpu_to_le_32(enables);
2828 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2830 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2832 HWRM_CHECK_RESULT();
2838 static void populate_vf_func_cfg_req(struct bnxt *bp,
2839 struct hwrm_func_cfg_input *req,
2842 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2843 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2844 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2845 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2846 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2847 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2848 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2849 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2850 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2851 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2853 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2854 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2856 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2857 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2859 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2861 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2862 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2864 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2865 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2866 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2867 /* TODO: For now, do not support VMDq/RFS on VFs. */
2868 req->num_vnics = rte_cpu_to_le_16(1);
2869 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2873 static void add_random_mac_if_needed(struct bnxt *bp,
2874 struct hwrm_func_cfg_input *cfg_req,
2877 struct rte_ether_addr mac;
2879 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2882 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2884 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2885 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2886 bp->pf.vf_info[vf].random_mac = true;
2888 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2889 RTE_ETHER_ADDR_LEN);
2893 static void reserve_resources_from_vf(struct bnxt *bp,
2894 struct hwrm_func_cfg_input *cfg_req,
2897 struct hwrm_func_qcaps_input req = {0};
2898 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2901 /* Get the actual allocated values now */
2902 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2903 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2904 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2907 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2908 copy_func_cfg_to_qcaps(cfg_req, resp);
2909 } else if (resp->error_code) {
2910 rc = rte_le_to_cpu_16(resp->error_code);
2911 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2912 copy_func_cfg_to_qcaps(cfg_req, resp);
2915 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2916 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2917 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2918 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2919 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2920 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2922 * TODO: While not supporting VMDq with VFs, max_vnics is always
2923 * forced to 1 in this case
2925 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2926 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2931 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2933 struct hwrm_func_qcfg_input req = {0};
2934 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2937 /* Check for zero MAC address */
2938 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2939 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2940 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2941 HWRM_CHECK_RESULT();
2942 rc = rte_le_to_cpu_16(resp->vlan);
2949 static int update_pf_resource_max(struct bnxt *bp)
2951 struct hwrm_func_qcfg_input req = {0};
2952 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2955 /* And copy the allocated numbers into the pf struct */
2956 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2957 req.fid = rte_cpu_to_le_16(0xffff);
2958 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2959 HWRM_CHECK_RESULT();
2961 /* Only TX ring value reflects actual allocation? TODO */
2962 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2963 bp->pf.evb_mode = resp->evb_mode;
2970 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2975 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2979 rc = bnxt_hwrm_func_qcaps(bp);
2983 bp->pf.func_cfg_flags &=
2984 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2985 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2986 bp->pf.func_cfg_flags |=
2987 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2988 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2989 rc = __bnxt_hwrm_func_qcaps(bp);
2993 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2995 struct hwrm_func_cfg_input req = {0};
2996 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3003 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3007 rc = bnxt_hwrm_func_qcaps(bp);
3012 bp->pf.active_vfs = num_vfs;
3015 * First, configure the PF to only use one TX ring. This ensures that
3016 * there are enough rings for all VFs.
3018 * If we don't do this, when we call func_alloc() later, we will lock
3019 * extra rings to the PF that won't be available during func_cfg() of
3022 * This has been fixed with firmware versions above 20.6.54
3024 bp->pf.func_cfg_flags &=
3025 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3026 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3027 bp->pf.func_cfg_flags |=
3028 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3029 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3034 * Now, create and register a buffer to hold forwarded VF requests
3036 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3037 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3038 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3039 if (bp->pf.vf_req_buf == NULL) {
3043 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3044 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3045 for (i = 0; i < num_vfs; i++)
3046 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3047 (i * HWRM_MAX_REQ_LEN);
3049 rc = bnxt_hwrm_func_buf_rgtr(bp);
3053 populate_vf_func_cfg_req(bp, &req, num_vfs);
3055 bp->pf.active_vfs = 0;
3056 for (i = 0; i < num_vfs; i++) {
3057 add_random_mac_if_needed(bp, &req, i);
3059 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3060 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3061 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3062 rc = bnxt_hwrm_send_message(bp,
3067 /* Clear enable flag for next pass */
3068 req.enables &= ~rte_cpu_to_le_32(
3069 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3071 if (rc || resp->error_code) {
3073 "Failed to initizlie VF %d\n", i);
3075 "Not all VFs available. (%d, %d)\n",
3076 rc, resp->error_code);
3083 reserve_resources_from_vf(bp, &req, i);
3084 bp->pf.active_vfs++;
3085 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3089 * Now configure the PF to use "the rest" of the resources
3090 * We're using STD_TX_RING_MODE here though which will limit the TX
3091 * rings. This will allow QoS to function properly. Not setting this
3092 * will cause PF rings to break bandwidth settings.
3094 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3098 rc = update_pf_resource_max(bp);
3105 bnxt_hwrm_func_buf_unrgtr(bp);
3109 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3111 struct hwrm_func_cfg_input req = {0};
3112 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3115 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3117 req.fid = rte_cpu_to_le_16(0xffff);
3118 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3119 req.evb_mode = bp->pf.evb_mode;
3121 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3122 HWRM_CHECK_RESULT();
3128 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3129 uint8_t tunnel_type)
3131 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3132 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3135 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3136 req.tunnel_type = tunnel_type;
3137 req.tunnel_dst_port_val = port;
3138 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3139 HWRM_CHECK_RESULT();
3141 switch (tunnel_type) {
3142 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3143 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3144 bp->vxlan_port = port;
3146 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3147 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3148 bp->geneve_port = port;
3159 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3160 uint8_t tunnel_type)
3162 struct hwrm_tunnel_dst_port_free_input req = {0};
3163 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3166 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3168 req.tunnel_type = tunnel_type;
3169 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3170 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3172 HWRM_CHECK_RESULT();
3178 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3181 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3182 struct hwrm_func_cfg_input req = {0};
3185 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3187 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3188 req.flags = rte_cpu_to_le_32(flags);
3189 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3191 HWRM_CHECK_RESULT();
3197 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3199 uint32_t *flag = flagp;
3201 vnic->flags = *flag;
3204 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3206 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3209 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3212 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3213 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3215 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3217 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3218 req.req_buf_page_size = rte_cpu_to_le_16(
3219 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3220 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3221 req.req_buf_page_addr0 =
3222 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3223 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3225 "unable to map buffer address to physical memory\n");
3229 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3231 HWRM_CHECK_RESULT();
3237 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3240 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3241 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3243 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3246 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3248 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3250 HWRM_CHECK_RESULT();
3256 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3258 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3259 struct hwrm_func_cfg_input req = {0};
3262 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3264 req.fid = rte_cpu_to_le_16(0xffff);
3265 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3266 req.enables = rte_cpu_to_le_32(
3267 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3268 req.async_event_cr = rte_cpu_to_le_16(
3269 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3270 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3272 HWRM_CHECK_RESULT();
3278 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3280 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3281 struct hwrm_func_vf_cfg_input req = {0};
3284 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3286 req.enables = rte_cpu_to_le_32(
3287 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3288 req.async_event_cr = rte_cpu_to_le_16(
3289 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3290 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3292 HWRM_CHECK_RESULT();
3298 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3300 struct hwrm_func_cfg_input req = {0};
3301 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3302 uint16_t dflt_vlan, fid;
3303 uint32_t func_cfg_flags;
3306 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3309 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3310 fid = bp->pf.vf_info[vf].fid;
3311 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3313 fid = rte_cpu_to_le_16(0xffff);
3314 func_cfg_flags = bp->pf.func_cfg_flags;
3315 dflt_vlan = bp->vlan;
3318 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3319 req.fid = rte_cpu_to_le_16(fid);
3320 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3321 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3323 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3325 HWRM_CHECK_RESULT();
3331 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3332 uint16_t max_bw, uint16_t enables)
3334 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3335 struct hwrm_func_cfg_input req = {0};
3338 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3340 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3341 req.enables |= rte_cpu_to_le_32(enables);
3342 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3343 req.max_bw = rte_cpu_to_le_32(max_bw);
3344 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3346 HWRM_CHECK_RESULT();
3352 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3354 struct hwrm_func_cfg_input req = {0};
3355 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3358 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3360 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3361 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3362 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3363 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3365 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3367 HWRM_CHECK_RESULT();
3373 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3378 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3380 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3385 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3386 void *encaped, size_t ec_size)
3389 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3390 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3392 if (ec_size > sizeof(req.encap_request))
3395 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3397 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3398 memcpy(req.encap_request, encaped, ec_size);
3400 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3402 HWRM_CHECK_RESULT();
3408 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3409 struct rte_ether_addr *mac)
3411 struct hwrm_func_qcfg_input req = {0};
3412 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3415 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3417 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3418 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3420 HWRM_CHECK_RESULT();
3422 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3429 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3430 void *encaped, size_t ec_size)
3433 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3434 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3436 if (ec_size > sizeof(req.encap_request))
3439 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3441 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3442 memcpy(req.encap_request, encaped, ec_size);
3444 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3446 HWRM_CHECK_RESULT();
3452 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3453 struct rte_eth_stats *stats, uint8_t rx)
3456 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3457 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3459 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3461 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3463 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3465 HWRM_CHECK_RESULT();
3468 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3469 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3470 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3471 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3472 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3473 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3474 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3475 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3477 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3478 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3479 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3480 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3481 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3482 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3491 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3493 struct hwrm_port_qstats_input req = {0};
3494 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3495 struct bnxt_pf_info *pf = &bp->pf;
3498 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3500 req.port_id = rte_cpu_to_le_16(pf->port_id);
3501 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3502 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3503 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3505 HWRM_CHECK_RESULT();
3511 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3513 struct hwrm_port_clr_stats_input req = {0};
3514 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3515 struct bnxt_pf_info *pf = &bp->pf;
3518 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3519 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3520 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3523 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3525 req.port_id = rte_cpu_to_le_16(pf->port_id);
3526 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3528 HWRM_CHECK_RESULT();
3534 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3536 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3537 struct hwrm_port_led_qcaps_input req = {0};
3543 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3544 req.port_id = bp->pf.port_id;
3545 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3547 HWRM_CHECK_RESULT();
3549 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3552 bp->num_leds = resp->num_leds;
3553 memcpy(bp->leds, &resp->led0_id,
3554 sizeof(bp->leds[0]) * bp->num_leds);
3555 for (i = 0; i < bp->num_leds; i++) {
3556 struct bnxt_led_info *led = &bp->leds[i];
3558 uint16_t caps = led->led_state_caps;
3560 if (!led->led_group_id ||
3561 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3573 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3575 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3576 struct hwrm_port_led_cfg_input req = {0};
3577 struct bnxt_led_cfg *led_cfg;
3578 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3579 uint16_t duration = 0;
3582 if (!bp->num_leds || BNXT_VF(bp))
3585 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3588 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3589 duration = rte_cpu_to_le_16(500);
3591 req.port_id = bp->pf.port_id;
3592 req.num_leds = bp->num_leds;
3593 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3594 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3595 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3596 led_cfg->led_id = bp->leds[i].led_id;
3597 led_cfg->led_state = led_state;
3598 led_cfg->led_blink_on = duration;
3599 led_cfg->led_blink_off = duration;
3600 led_cfg->led_group_id = bp->leds[i].led_group_id;
3603 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3605 HWRM_CHECK_RESULT();
3611 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3615 struct hwrm_nvm_get_dir_info_input req = {0};
3616 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3618 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3620 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3622 HWRM_CHECK_RESULT();
3624 *entries = rte_le_to_cpu_32(resp->entries);
3625 *length = rte_le_to_cpu_32(resp->entry_length);
3631 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3634 uint32_t dir_entries;
3635 uint32_t entry_length;
3638 rte_iova_t dma_handle;
3639 struct hwrm_nvm_get_dir_entries_input req = {0};
3640 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3642 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3646 *data++ = dir_entries;
3647 *data++ = entry_length;
3649 memset(data, 0xff, len);
3651 buflen = dir_entries * entry_length;
3652 buf = rte_malloc("nvm_dir", buflen, 0);
3653 rte_mem_lock_page(buf);
3656 dma_handle = rte_mem_virt2iova(buf);
3657 if (dma_handle == RTE_BAD_IOVA) {
3659 "unable to map response address to physical memory\n");
3662 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3663 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3664 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3667 memcpy(data, buf, len > buflen ? buflen : len);
3670 HWRM_CHECK_RESULT();
3676 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3677 uint32_t offset, uint32_t length,
3682 rte_iova_t dma_handle;
3683 struct hwrm_nvm_read_input req = {0};
3684 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3686 buf = rte_malloc("nvm_item", length, 0);
3687 rte_mem_lock_page(buf);
3691 dma_handle = rte_mem_virt2iova(buf);
3692 if (dma_handle == RTE_BAD_IOVA) {
3694 "unable to map response address to physical memory\n");
3697 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3698 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3699 req.dir_idx = rte_cpu_to_le_16(index);
3700 req.offset = rte_cpu_to_le_32(offset);
3701 req.len = rte_cpu_to_le_32(length);
3702 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3704 memcpy(data, buf, length);
3707 HWRM_CHECK_RESULT();
3713 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3716 struct hwrm_nvm_erase_dir_entry_input req = {0};
3717 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3719 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3720 req.dir_idx = rte_cpu_to_le_16(index);
3721 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3722 HWRM_CHECK_RESULT();
3729 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3730 uint16_t dir_ordinal, uint16_t dir_ext,
3731 uint16_t dir_attr, const uint8_t *data,
3735 struct hwrm_nvm_write_input req = {0};
3736 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3737 rte_iova_t dma_handle;
3740 buf = rte_malloc("nvm_write", data_len, 0);
3741 rte_mem_lock_page(buf);
3745 dma_handle = rte_mem_virt2iova(buf);
3746 if (dma_handle == RTE_BAD_IOVA) {
3748 "unable to map response address to physical memory\n");
3751 memcpy(buf, data, data_len);
3753 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3755 req.dir_type = rte_cpu_to_le_16(dir_type);
3756 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3757 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3758 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3759 req.dir_data_length = rte_cpu_to_le_32(data_len);
3760 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3762 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3765 HWRM_CHECK_RESULT();
3772 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3774 uint32_t *count = cbdata;
3776 *count = *count + 1;
3779 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3780 struct bnxt_vnic_info *vnic __rte_unused)
3785 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3789 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3790 &count, bnxt_vnic_count_hwrm_stub);
3795 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3798 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3799 struct hwrm_func_vf_vnic_ids_query_output *resp =
3800 bp->hwrm_cmd_resp_addr;
3803 /* First query all VNIC ids */
3804 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3806 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3807 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3808 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3810 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3813 "unable to map VNIC ID table address to physical memory\n");
3816 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3817 HWRM_CHECK_RESULT();
3818 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3826 * This function queries the VNIC IDs for a specified VF. It then calls
3827 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3828 * Then it calls the hwrm_cb function to program this new vnic configuration.
3830 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3831 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3832 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3834 struct bnxt_vnic_info vnic;
3836 int i, num_vnic_ids;
3841 /* First query all VNIC ids */
3842 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3843 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3844 RTE_CACHE_LINE_SIZE);
3845 if (vnic_ids == NULL)
3848 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3849 rte_mem_lock_page(((char *)vnic_ids) + sz);
3851 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3853 if (num_vnic_ids < 0)
3854 return num_vnic_ids;
3856 /* Retrieve VNIC, update bd_stall then update */
3858 for (i = 0; i < num_vnic_ids; i++) {
3859 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3860 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3861 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3864 if (vnic.mru <= 4) /* Indicates unallocated */
3867 vnic_cb(&vnic, cbdata);
3869 rc = hwrm_cb(bp, &vnic);
3879 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3882 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3883 struct hwrm_func_cfg_input req = {0};
3886 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3888 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3889 req.enables |= rte_cpu_to_le_32(
3890 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3891 req.vlan_antispoof_mode = on ?
3892 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3893 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3894 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3896 HWRM_CHECK_RESULT();
3902 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3904 struct bnxt_vnic_info vnic;
3907 int num_vnic_ids, i;
3911 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3912 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3913 RTE_CACHE_LINE_SIZE);
3914 if (vnic_ids == NULL)
3917 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3918 rte_mem_lock_page(((char *)vnic_ids) + sz);
3920 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3926 * Loop through to find the default VNIC ID.
3927 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3928 * by sending the hwrm_func_qcfg command to the firmware.
3930 for (i = 0; i < num_vnic_ids; i++) {
3931 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3932 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3933 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3934 bp->pf.first_vf_id + vf);
3937 if (vnic.func_default) {
3939 return vnic.fw_vnic_id;
3942 /* Could not find a default VNIC. */
3943 PMD_DRV_LOG(ERR, "No default VNIC\n");
3949 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3951 struct bnxt_filter_info *filter)
3954 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3955 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3956 uint32_t enables = 0;
3958 if (filter->fw_em_filter_id != UINT64_MAX)
3959 bnxt_hwrm_clear_em_filter(bp, filter);
3961 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3963 req.flags = rte_cpu_to_le_32(filter->flags);
3965 enables = filter->enables |
3966 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3967 req.dst_id = rte_cpu_to_le_16(dst_id);
3969 if (filter->ip_addr_type) {
3970 req.ip_addr_type = filter->ip_addr_type;
3971 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3974 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3975 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3977 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3978 memcpy(req.src_macaddr, filter->src_macaddr,
3979 RTE_ETHER_ADDR_LEN);
3981 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3982 memcpy(req.dst_macaddr, filter->dst_macaddr,
3983 RTE_ETHER_ADDR_LEN);
3985 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3986 req.ovlan_vid = filter->l2_ovlan;
3988 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3989 req.ivlan_vid = filter->l2_ivlan;
3991 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3992 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3994 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3995 req.ip_protocol = filter->ip_protocol;
3997 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3998 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4000 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4001 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4003 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4004 req.src_port = rte_cpu_to_be_16(filter->src_port);
4006 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4007 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4009 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4010 req.mirror_vnic_id = filter->mirror_vnic_id;
4012 req.enables = rte_cpu_to_le_32(enables);
4014 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4016 HWRM_CHECK_RESULT();
4018 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4024 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4027 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4028 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4030 if (filter->fw_em_filter_id == UINT64_MAX)
4033 PMD_DRV_LOG(ERR, "Clear EM filter\n");
4034 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4036 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4038 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4040 HWRM_CHECK_RESULT();
4043 filter->fw_em_filter_id = UINT64_MAX;
4044 filter->fw_l2_filter_id = UINT64_MAX;
4049 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4051 struct bnxt_filter_info *filter)
4054 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4055 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4056 bp->hwrm_cmd_resp_addr;
4057 uint32_t enables = 0;
4059 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4060 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4062 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4064 req.flags = rte_cpu_to_le_32(filter->flags);
4066 enables = filter->enables |
4067 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4068 req.dst_id = rte_cpu_to_le_16(dst_id);
4071 if (filter->ip_addr_type) {
4072 req.ip_addr_type = filter->ip_addr_type;
4074 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4077 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4078 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4080 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4081 memcpy(req.src_macaddr, filter->src_macaddr,
4082 RTE_ETHER_ADDR_LEN);
4084 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4085 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4086 //RTE_ETHER_ADDR_LEN);
4088 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4089 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4091 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4092 req.ip_protocol = filter->ip_protocol;
4094 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4095 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4097 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4098 req.src_ipaddr_mask[0] =
4099 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4101 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4102 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4104 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4105 req.dst_ipaddr_mask[0] =
4106 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4108 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4109 req.src_port = rte_cpu_to_le_16(filter->src_port);
4111 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4112 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4114 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4115 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4117 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4118 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4120 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4121 req.mirror_vnic_id = filter->mirror_vnic_id;
4123 req.enables = rte_cpu_to_le_32(enables);
4125 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4127 HWRM_CHECK_RESULT();
4129 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4135 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4136 struct bnxt_filter_info *filter)
4139 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4140 struct hwrm_cfa_ntuple_filter_free_output *resp =
4141 bp->hwrm_cmd_resp_addr;
4143 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4146 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4148 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4150 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4152 HWRM_CHECK_RESULT();
4155 filter->fw_ntuple_filter_id = UINT64_MAX;
4161 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4163 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4164 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4165 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4166 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4167 uint16_t *ring_tbl = vnic->rss_table;
4168 int nr_ctxs = vnic->num_lb_ctxts;
4169 int max_rings = bp->rx_nr_rings;
4173 for (i = 0, k = 0; i < nr_ctxs; i++) {
4174 struct bnxt_rx_ring_info *rxr;
4175 struct bnxt_cp_ring_info *cpr;
4177 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4179 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4180 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4181 req.hash_mode_flags = vnic->hash_mode;
4183 req.ring_grp_tbl_addr =
4184 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4185 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4186 2 * sizeof(*ring_tbl));
4187 req.hash_key_tbl_addr =
4188 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4190 req.ring_table_pair_index = i;
4191 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4193 for (j = 0; j < 64; j++) {
4196 /* Find next active ring. */
4197 for (cnt = 0; cnt < max_rings; cnt++) {
4198 if (rx_queue_state[k] !=
4199 RTE_ETH_QUEUE_STATE_STOPPED)
4201 if (++k == max_rings)
4205 /* Return if no rings are active. */
4206 if (cnt == max_rings)
4209 /* Add rx/cp ring pair to RSS table. */
4210 rxr = rxqs[k]->rx_ring;
4211 cpr = rxqs[k]->cp_ring;
4213 ring_id = rxr->rx_ring_struct->fw_ring_id;
4214 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4215 ring_id = cpr->cp_ring_struct->fw_ring_id;
4216 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4218 if (++k == max_rings)
4221 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4224 HWRM_CHECK_RESULT();
4231 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4233 unsigned int rss_idx, fw_idx, i;
4235 if (!(vnic->rss_table && vnic->hash_type))
4238 if (BNXT_CHIP_THOR(bp))
4239 return bnxt_vnic_rss_configure_thor(bp, vnic);
4242 * Fill the RSS hash & redirection table with
4243 * ring group ids for all VNICs
4245 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4246 rss_idx++, fw_idx++) {
4247 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4248 fw_idx %= bp->rx_cp_nr_rings;
4249 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4253 if (i == bp->rx_cp_nr_rings)
4255 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4257 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4260 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4261 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4265 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4267 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4268 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4270 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4271 req->num_cmpl_dma_aggr_during_int =
4272 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4274 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4276 /* min timer set to 1/2 of interrupt timer */
4277 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4279 /* buf timer set to 1/4 of interrupt timer */
4280 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4282 req->cmpl_aggr_dma_tmr_during_int =
4283 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4285 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4286 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4287 req->flags = rte_cpu_to_le_16(flags);
4290 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4291 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4293 struct hwrm_ring_aggint_qcaps_input req = {0};
4294 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4299 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4300 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4301 HWRM_CHECK_RESULT();
4303 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4304 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4306 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4307 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4308 agg_req->flags = rte_cpu_to_le_16(flags);
4310 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4311 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4312 agg_req->enables = rte_cpu_to_le_32(enables);
4318 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4319 struct bnxt_coal *coal, uint16_t ring_id)
4321 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4322 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4323 bp->hwrm_cmd_resp_addr;
4326 /* Set ring coalesce parameters only for 100G NICs */
4327 if (BNXT_CHIP_THOR(bp)) {
4328 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4330 } else if (bnxt_stratus_device(bp)) {
4331 bnxt_hwrm_set_coal_params(coal, &req);
4336 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4337 req.ring_id = rte_cpu_to_le_16(ring_id);
4338 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4339 HWRM_CHECK_RESULT();
4344 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4345 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4347 struct hwrm_func_backing_store_qcaps_input req = {0};
4348 struct hwrm_func_backing_store_qcaps_output *resp =
4349 bp->hwrm_cmd_resp_addr;
4352 if (!BNXT_CHIP_THOR(bp) ||
4353 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4358 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4359 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4360 HWRM_CHECK_RESULT_SILENT();
4363 struct bnxt_ctx_pg_info *ctx_pg;
4364 struct bnxt_ctx_mem_info *ctx;
4365 int total_alloc_len;
4368 total_alloc_len = sizeof(*ctx);
4369 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4370 RTE_CACHE_LINE_SIZE);
4375 memset(ctx, 0, total_alloc_len);
4377 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4378 sizeof(*ctx_pg) * BNXT_MAX_Q,
4379 RTE_CACHE_LINE_SIZE);
4384 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4385 ctx->tqm_mem[i] = ctx_pg;
4388 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4389 ctx->qp_min_qp1_entries =
4390 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4391 ctx->qp_max_l2_entries =
4392 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4393 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4394 ctx->srq_max_l2_entries =
4395 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4396 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4397 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4398 ctx->cq_max_l2_entries =
4399 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4400 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4401 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4402 ctx->vnic_max_vnic_entries =
4403 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4404 ctx->vnic_max_ring_table_entries =
4405 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4406 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4407 ctx->stat_max_entries =
4408 rte_le_to_cpu_32(resp->stat_max_entries);
4409 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4410 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4411 ctx->tqm_min_entries_per_ring =
4412 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4413 ctx->tqm_max_entries_per_ring =
4414 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4415 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4416 if (!ctx->tqm_entries_multiple)
4417 ctx->tqm_entries_multiple = 1;
4418 ctx->mrav_max_entries =
4419 rte_le_to_cpu_32(resp->mrav_max_entries);
4420 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4421 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4422 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4431 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4433 struct hwrm_func_backing_store_cfg_input req = {0};
4434 struct hwrm_func_backing_store_cfg_output *resp =
4435 bp->hwrm_cmd_resp_addr;
4436 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4437 struct bnxt_ctx_pg_info *ctx_pg;
4438 uint32_t *num_entries;
4447 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4448 req.enables = rte_cpu_to_le_32(enables);
4450 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4451 ctx_pg = &ctx->qp_mem;
4452 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4453 req.qp_num_qp1_entries =
4454 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4455 req.qp_num_l2_entries =
4456 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4457 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4458 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4459 &req.qpc_pg_size_qpc_lvl,
4463 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4464 ctx_pg = &ctx->srq_mem;
4465 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4466 req.srq_num_l2_entries =
4467 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4468 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4469 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4470 &req.srq_pg_size_srq_lvl,
4474 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4475 ctx_pg = &ctx->cq_mem;
4476 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4477 req.cq_num_l2_entries =
4478 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4479 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4480 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4481 &req.cq_pg_size_cq_lvl,
4485 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4486 ctx_pg = &ctx->vnic_mem;
4487 req.vnic_num_vnic_entries =
4488 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4489 req.vnic_num_ring_table_entries =
4490 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4491 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4492 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4493 &req.vnic_pg_size_vnic_lvl,
4494 &req.vnic_page_dir);
4497 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4498 ctx_pg = &ctx->stat_mem;
4499 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4500 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4501 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4502 &req.stat_pg_size_stat_lvl,
4503 &req.stat_page_dir);
4506 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4507 num_entries = &req.tqm_sp_num_entries;
4508 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4509 pg_dir = &req.tqm_sp_page_dir;
4510 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4511 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4512 if (!(enables & ena))
4515 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4517 ctx_pg = ctx->tqm_mem[i];
4518 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4519 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4522 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4523 HWRM_CHECK_RESULT();
4529 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4531 struct hwrm_port_qstats_ext_input req = {0};
4532 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4533 struct bnxt_pf_info *pf = &bp->pf;
4536 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4537 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4540 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4542 req.port_id = rte_cpu_to_le_16(pf->port_id);
4543 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4544 req.tx_stat_host_addr =
4545 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4547 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4549 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4550 req.rx_stat_host_addr =
4551 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4553 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4555 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4558 bp->fw_rx_port_stats_ext_size = 0;
4559 bp->fw_tx_port_stats_ext_size = 0;
4561 bp->fw_rx_port_stats_ext_size =
4562 rte_le_to_cpu_16(resp->rx_stat_size);
4563 bp->fw_tx_port_stats_ext_size =
4564 rte_le_to_cpu_16(resp->tx_stat_size);
4567 HWRM_CHECK_RESULT();
4574 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4576 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4577 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4578 bp->hwrm_cmd_resp_addr;
4581 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4582 req.tunnel_type = type;
4583 req.dest_fid = bp->fw_fid;
4584 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4585 HWRM_CHECK_RESULT();
4593 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4595 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4596 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4597 bp->hwrm_cmd_resp_addr;
4600 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4601 req.tunnel_type = type;
4602 req.dest_fid = bp->fw_fid;
4603 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4604 HWRM_CHECK_RESULT();
4611 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4613 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4614 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4615 bp->hwrm_cmd_resp_addr;
4618 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4619 req.src_fid = bp->fw_fid;
4620 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4621 HWRM_CHECK_RESULT();
4624 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4631 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4634 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4635 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4636 bp->hwrm_cmd_resp_addr;
4639 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4640 req.src_fid = bp->fw_fid;
4641 req.tunnel_type = tun_type;
4642 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4643 HWRM_CHECK_RESULT();
4646 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4648 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4655 int bnxt_hwrm_set_mac(struct bnxt *bp)
4657 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4658 struct hwrm_func_vf_cfg_input req = {0};
4664 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4667 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4668 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4670 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4672 HWRM_CHECK_RESULT();
4674 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4680 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4682 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4683 struct hwrm_func_drv_if_change_input req = {0};
4687 if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4690 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4691 * If we issue FUNC_DRV_IF_CHANGE with flags down before
4692 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4694 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4697 HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4701 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4703 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4705 HWRM_CHECK_RESULT();
4706 flags = rte_le_to_cpu_32(resp->flags);
4709 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4710 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4711 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4717 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4719 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4720 struct bnxt_error_recovery_info *info = bp->recovery_info;
4721 struct hwrm_error_recovery_qcfg_input req = {0};
4726 /* Older FW does not have error recovery support */
4727 if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4731 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4733 bp->recovery_info = info;
4737 memset(info, 0, sizeof(*info));
4740 HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4742 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4744 HWRM_CHECK_RESULT();
4746 flags = rte_le_to_cpu_32(resp->flags);
4747 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4748 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4749 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4750 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4752 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4753 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4758 /* FW returned values are in units of 100msec */
4759 info->driver_polling_freq =
4760 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4761 info->master_func_wait_period =
4762 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4763 info->normal_func_wait_period =
4764 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4765 info->master_func_wait_period_after_reset =
4766 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4767 info->max_bailout_time_after_reset =
4768 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4769 info->status_regs[BNXT_FW_STATUS_REG] =
4770 rte_le_to_cpu_32(resp->fw_health_status_reg);
4771 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4772 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4773 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4774 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4775 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4776 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4777 info->reg_array_cnt =
4778 rte_le_to_cpu_32(resp->reg_array_cnt);
4780 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4785 for (i = 0; i < info->reg_array_cnt; i++) {
4786 info->reset_reg[i] =
4787 rte_le_to_cpu_32(resp->reset_reg[i]);
4788 info->reset_reg_val[i] =
4789 rte_le_to_cpu_32(resp->reset_reg_val[i]);
4790 info->delay_after_reset[i] =
4791 resp->delay_after_reset[i];
4796 /* Map the FW status registers */
4798 rc = bnxt_map_fw_health_status_regs(bp);
4801 rte_free(bp->recovery_info);
4802 bp->recovery_info = NULL;