1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SHORT_CMD_TIMEOUT 50000
31 #define HWRM_SPEC_CODE_1_8_3 0x10803
32 #define HWRM_VERSION_1_9_1 0x10901
33 #define HWRM_VERSION_1_9_2 0x10903
35 struct bnxt_plcmodes_cfg {
37 uint16_t jumbo_thresh;
39 uint16_t hds_threshold;
42 static int page_getenum(size_t size)
58 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
59 return sizeof(void *) * 8 - 1;
62 static int page_roundup(size_t size)
64 return 1 << page_getenum(size);
67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
71 if (rmem->nr_pages > 1) {
73 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
75 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
80 * HWRM Functions (sent to HWRM)
81 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
82 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
83 * command was failed by the ChiMP.
86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
87 uint32_t msg_len, bool use_kong_mb)
90 struct input *req = msg;
91 struct output *resp = bp->hwrm_cmd_resp_addr;
95 uint16_t max_req_len = bp->max_req_len;
96 struct hwrm_short_input short_input = { 0 };
97 uint16_t bar_offset = use_kong_mb ?
98 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
99 uint16_t mb_trigger_offset = use_kong_mb ?
100 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
103 /* Do not send HWRM commands to firmware in error state */
104 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
107 /* For VER_GET command, set timeout as 50ms */
108 if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
109 timeout = HWRM_SHORT_CMD_TIMEOUT;
111 timeout = HWRM_CMD_TIMEOUT;
113 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
114 msg_len > bp->max_req_len) {
115 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
117 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
118 memcpy(short_cmd_req, req, msg_len);
120 short_input.req_type = rte_cpu_to_le_16(req->req_type);
121 short_input.signature = rte_cpu_to_le_16(
122 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
123 short_input.size = rte_cpu_to_le_16(msg_len);
124 short_input.req_addr =
125 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
127 data = (uint32_t *)&short_input;
128 msg_len = sizeof(short_input);
130 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
133 /* Write request msg to hwrm channel */
134 for (i = 0; i < msg_len; i += 4) {
135 bar = (uint8_t *)bp->bar0 + bar_offset + i;
136 rte_write32(*data, bar);
140 /* Zero the rest of the request space */
141 for (; i < max_req_len; i += 4) {
142 bar = (uint8_t *)bp->bar0 + bar_offset + i;
146 /* Ring channel doorbell */
147 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
150 * Make sure the channel doorbell ring command complete before
151 * reading the response to avoid getting stale or invalid
156 /* Poll for the valid bit */
157 for (i = 0; i < timeout; i++) {
158 /* Sanity check on the resp->resp_len */
160 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
161 /* Last byte of resp contains the valid key */
162 valid = (uint8_t *)resp + resp->resp_len - 1;
163 if (*valid == HWRM_RESP_VALID_KEY)
170 /* Suppress VER_GET timeout messages during reset recovery */
171 if (bp->flags & BNXT_FLAG_FW_RESET &&
172 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
175 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
183 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
184 * spinlock, and does initial processing.
186 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
187 * releases the spinlock only if it returns. If the regular int return codes
188 * are not used by the function, HWRM_CHECK_RESULT() should not be used
189 * directly, rather it should be copied and modified to suit the function.
191 * HWRM_UNLOCK() must be called after all response processing is completed.
193 #define HWRM_PREP(req, type, kong) do { \
194 rte_spinlock_lock(&bp->hwrm_lock); \
195 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
196 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
197 req.cmpl_ring = rte_cpu_to_le_16(-1); \
198 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
199 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
200 req.target_id = rte_cpu_to_le_16(0xffff); \
201 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
204 #define HWRM_CHECK_RESULT_SILENT() do {\
206 rte_spinlock_unlock(&bp->hwrm_lock); \
209 if (resp->error_code) { \
210 rc = rte_le_to_cpu_16(resp->error_code); \
211 rte_spinlock_unlock(&bp->hwrm_lock); \
216 #define HWRM_CHECK_RESULT() do {\
218 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
219 rte_spinlock_unlock(&bp->hwrm_lock); \
220 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
226 if (resp->error_code) { \
227 rc = rte_le_to_cpu_16(resp->error_code); \
228 if (resp->resp_len >= 16) { \
229 struct hwrm_err_output *tmp_hwrm_err_op = \
232 "error %d:%d:%08x:%04x\n", \
233 rc, tmp_hwrm_err_op->cmd_err, \
235 tmp_hwrm_err_op->opaque_0), \
237 tmp_hwrm_err_op->opaque_1)); \
239 PMD_DRV_LOG(ERR, "error %d\n", rc); \
241 rte_spinlock_unlock(&bp->hwrm_lock); \
242 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
250 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
252 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
255 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
256 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
258 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
259 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
262 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
270 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
271 struct bnxt_vnic_info *vnic,
273 struct bnxt_vlan_table_entry *vlan_table)
276 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
277 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
280 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
283 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
284 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
286 /* FIXME add multicast flag, when multicast adding options is supported
289 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
290 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
291 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
292 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
293 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
294 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
295 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
296 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
297 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
298 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
299 if (vnic->mc_addr_cnt) {
300 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
301 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
302 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
305 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
306 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
307 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
308 rte_mem_virt2iova(vlan_table));
309 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
311 req.mask = rte_cpu_to_le_32(mask);
313 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
321 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
323 struct bnxt_vlan_antispoof_table_entry *vlan_table)
326 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
327 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
328 bp->hwrm_cmd_resp_addr;
331 * Older HWRM versions did not support this command, and the set_rx_mask
332 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
333 * removed from set_rx_mask call, and this command was added.
335 * This command is also present from 1.7.8.11 and higher,
338 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
339 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
340 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
345 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
346 req.fid = rte_cpu_to_le_16(fid);
348 req.vlan_tag_mask_tbl_addr =
349 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
350 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
352 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
360 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
361 struct bnxt_filter_info *filter)
364 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
365 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
367 if (filter->fw_l2_filter_id == UINT64_MAX)
370 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
372 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
374 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
379 filter->fw_l2_filter_id = UINT64_MAX;
384 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
386 struct bnxt_filter_info *filter)
389 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
390 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
391 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
392 const struct rte_eth_vmdq_rx_conf *conf =
393 &dev_conf->rx_adv_conf.vmdq_rx_conf;
394 uint32_t enables = 0;
395 uint16_t j = dst_id - 1;
397 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
398 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
399 conf->pool_map[j].pools & (1UL << j)) {
401 "Add vlan %u to vmdq pool %u\n",
402 conf->pool_map[j].vlan_id, j);
404 filter->l2_ivlan = conf->pool_map[j].vlan_id;
406 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
407 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
410 if (filter->fw_l2_filter_id != UINT64_MAX)
411 bnxt_hwrm_clear_l2_filter(bp, filter);
413 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
415 req.flags = rte_cpu_to_le_32(filter->flags);
417 rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
419 enables = filter->enables |
420 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
421 req.dst_id = rte_cpu_to_le_16(dst_id);
424 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
425 memcpy(req.l2_addr, filter->l2_addr,
428 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
429 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
432 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
433 req.l2_ovlan = filter->l2_ovlan;
435 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
436 req.l2_ivlan = filter->l2_ivlan;
438 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
439 req.l2_ovlan_mask = filter->l2_ovlan_mask;
441 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
442 req.l2_ivlan_mask = filter->l2_ivlan_mask;
443 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
444 req.src_id = rte_cpu_to_le_32(filter->src_id);
445 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
446 req.src_type = filter->src_type;
448 req.enables = rte_cpu_to_le_32(enables);
450 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
454 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
460 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
462 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
463 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
470 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
473 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
476 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
477 if (ptp->tx_tstamp_en)
478 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
481 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
482 req.flags = rte_cpu_to_le_32(flags);
483 req.enables = rte_cpu_to_le_32
484 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
485 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
487 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
493 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
496 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
497 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
498 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
500 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
504 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
506 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
508 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
512 if (!BNXT_CHIP_THOR(bp) &&
513 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
516 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
517 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
519 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
523 if (!BNXT_CHIP_THOR(bp)) {
524 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
525 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
526 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
527 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
528 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
529 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
530 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
531 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
532 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
533 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
534 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
535 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
536 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
537 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
538 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
539 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
540 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
541 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
550 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
553 struct hwrm_func_qcaps_input req = {.req_type = 0 };
554 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
555 uint16_t new_max_vfs;
559 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
561 req.fid = rte_cpu_to_le_16(0xffff);
563 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
567 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
568 flags = rte_le_to_cpu_32(resp->flags);
570 bp->pf.port_id = resp->port_id;
571 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
572 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
573 new_max_vfs = bp->pdev->max_vfs;
574 if (new_max_vfs != bp->pf.max_vfs) {
576 rte_free(bp->pf.vf_info);
577 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
578 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
579 bp->pf.max_vfs = new_max_vfs;
580 for (i = 0; i < new_max_vfs; i++) {
581 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
582 bp->pf.vf_info[i].vlan_table =
583 rte_zmalloc("VF VLAN table",
586 if (bp->pf.vf_info[i].vlan_table == NULL)
588 "Fail to alloc VLAN table for VF %d\n",
592 bp->pf.vf_info[i].vlan_table);
593 bp->pf.vf_info[i].vlan_as_table =
594 rte_zmalloc("VF VLAN AS table",
597 if (bp->pf.vf_info[i].vlan_as_table == NULL)
599 "Alloc VLAN AS table for VF %d fail\n",
603 bp->pf.vf_info[i].vlan_as_table);
604 STAILQ_INIT(&bp->pf.vf_info[i].filter);
609 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
610 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
611 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
612 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
613 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
614 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
615 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
616 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
618 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
619 /* TODO: For now, do not support VMDq/RFS on VFs. */
624 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
628 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
630 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
631 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
632 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
633 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
635 bnxt_hwrm_ptp_qcfg(bp);
639 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
640 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
642 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
643 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
644 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
646 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
649 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
650 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
652 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
659 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
663 rc = __bnxt_hwrm_func_qcaps(bp);
664 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
665 rc = bnxt_alloc_ctx_mem(bp);
669 rc = bnxt_hwrm_func_resc_qcaps(bp);
671 bp->flags |= BNXT_FLAG_NEW_RM;
677 int bnxt_hwrm_func_reset(struct bnxt *bp)
680 struct hwrm_func_reset_input req = {.req_type = 0 };
681 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
683 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
685 req.enables = rte_cpu_to_le_32(0);
687 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
695 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
699 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
700 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
702 if (bp->flags & BNXT_FLAG_REGISTERED)
705 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
706 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
707 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
709 /* PFs and trusted VFs should indicate the support of the
710 * Master capability on non Stingray platform
712 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
713 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
715 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
716 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
717 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
718 req.ver_maj = RTE_VER_YEAR;
719 req.ver_min = RTE_VER_MONTH;
720 req.ver_upd = RTE_VER_MINOR;
723 req.enables |= rte_cpu_to_le_32(
724 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
725 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
726 RTE_MIN(sizeof(req.vf_req_fwd),
727 sizeof(bp->pf.vf_req_fwd)));
730 * PF can sniff HWRM API issued by VF. This can be set up by
731 * linux driver and inherited by the DPDK PF driver. Clear
732 * this HWRM sniffer list in FW because DPDK PF driver does
735 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
738 req.flags = rte_cpu_to_le_32(flags);
740 req.async_event_fwd[0] |=
741 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
742 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
743 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
744 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
745 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
746 req.async_event_fwd[0] |=
747 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
748 req.async_event_fwd[1] |=
749 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
750 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
752 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
756 flags = rte_le_to_cpu_32(resp->flags);
757 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
758 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
762 bp->flags |= BNXT_FLAG_REGISTERED;
767 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
769 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
772 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
775 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
780 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
781 struct hwrm_func_vf_cfg_input req = {0};
783 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
785 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
786 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
787 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
788 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
789 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
791 if (BNXT_HAS_RING_GRPS(bp)) {
792 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
793 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
796 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
797 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
798 AGG_RING_MULTIPLIER);
799 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
801 BNXT_NUM_ASYNC_CPR(bp));
802 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
804 BNXT_NUM_ASYNC_CPR(bp));
805 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
806 if (bp->vf_resv_strategy ==
807 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
808 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
809 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
810 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
811 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
812 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
813 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
817 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
818 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
819 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
820 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
821 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
822 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
824 if (test && BNXT_HAS_RING_GRPS(bp))
825 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
827 req.flags = rte_cpu_to_le_32(flags);
828 req.enables |= rte_cpu_to_le_32(enables);
830 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
833 HWRM_CHECK_RESULT_SILENT();
841 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
844 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
845 struct hwrm_func_resource_qcaps_input req = {0};
847 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
848 req.fid = rte_cpu_to_le_16(0xffff);
850 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
855 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
856 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
857 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
858 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
859 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
860 /* func_resource_qcaps does not return max_rx_em_flows.
861 * So use the value provided by func_qcaps.
864 rte_le_to_cpu_16(resp->max_l2_ctxs) +
866 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
867 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
869 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
870 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
871 if (bp->vf_resv_strategy >
872 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
873 bp->vf_resv_strategy =
874 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
880 int bnxt_hwrm_ver_get(struct bnxt *bp)
883 struct hwrm_ver_get_input req = {.req_type = 0 };
884 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
886 uint16_t max_resp_len;
887 char type[RTE_MEMZONE_NAMESIZE];
888 uint32_t dev_caps_cfg;
890 bp->max_req_len = HWRM_MAX_REQ_LEN;
891 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
893 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
894 req.hwrm_intf_min = HWRM_VERSION_MINOR;
895 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
897 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
899 if (bp->flags & BNXT_FLAG_FW_RESET)
900 HWRM_CHECK_RESULT_SILENT();
904 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
905 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
906 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
907 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
908 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
909 (resp->hwrm_fw_min_8b << 16) |
910 (resp->hwrm_fw_bld_8b << 8) |
911 resp->hwrm_fw_rsvd_8b;
912 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
913 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
915 fw_version = resp->hwrm_intf_maj_8b << 16;
916 fw_version |= resp->hwrm_intf_min_8b << 8;
917 fw_version |= resp->hwrm_intf_upd_8b;
918 bp->hwrm_spec_code = fw_version;
920 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
921 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
926 if (bp->max_req_len > resp->max_req_win_len) {
927 PMD_DRV_LOG(ERR, "Unsupported request length\n");
930 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
931 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
932 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
933 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
935 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
936 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
938 if (bp->max_resp_len != max_resp_len) {
939 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
940 bp->pdev->addr.domain, bp->pdev->addr.bus,
941 bp->pdev->addr.devid, bp->pdev->addr.function);
943 rte_free(bp->hwrm_cmd_resp_addr);
945 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
946 if (bp->hwrm_cmd_resp_addr == NULL) {
950 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
951 bp->hwrm_cmd_resp_dma_addr =
952 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
953 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
955 "Unable to map response buffer to physical memory.\n");
959 bp->max_resp_len = max_resp_len;
963 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
965 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
966 PMD_DRV_LOG(DEBUG, "Short command supported\n");
967 bp->flags |= BNXT_FLAG_SHORT_CMD;
971 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
973 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
974 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
975 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
976 bp->pdev->addr.domain, bp->pdev->addr.bus,
977 bp->pdev->addr.devid, bp->pdev->addr.function);
979 rte_free(bp->hwrm_short_cmd_req_addr);
981 bp->hwrm_short_cmd_req_addr =
982 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
983 if (bp->hwrm_short_cmd_req_addr == NULL) {
987 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
988 bp->hwrm_short_cmd_req_dma_addr =
989 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
990 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
991 rte_free(bp->hwrm_short_cmd_req_addr);
993 "Unable to map buffer to physical memory.\n");
999 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1000 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1001 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1004 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1005 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1012 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1015 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1016 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1018 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1021 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1024 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1026 HWRM_CHECK_RESULT();
1032 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1035 struct hwrm_port_phy_cfg_input req = {0};
1036 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1037 uint32_t enables = 0;
1039 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1041 if (conf->link_up) {
1042 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1043 if (bp->link_info.auto_mode && conf->link_speed) {
1044 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1045 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1048 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1049 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1050 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1052 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1053 * any auto mode, even "none".
1055 if (!conf->link_speed) {
1056 /* No speeds specified. Enable AutoNeg - all speeds */
1058 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1060 /* AutoNeg - Advertise speeds specified. */
1061 if (conf->auto_link_speed_mask &&
1062 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1064 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1065 req.auto_link_speed_mask =
1066 conf->auto_link_speed_mask;
1068 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1071 req.auto_duplex = conf->duplex;
1072 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1073 req.auto_pause = conf->auto_pause;
1074 req.force_pause = conf->force_pause;
1075 /* Set force_pause if there is no auto or if there is a force */
1076 if (req.auto_pause && !req.force_pause)
1077 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1079 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1081 req.enables = rte_cpu_to_le_32(enables);
1084 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1085 PMD_DRV_LOG(INFO, "Force Link Down\n");
1088 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1090 HWRM_CHECK_RESULT();
1096 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1097 struct bnxt_link_info *link_info)
1100 struct hwrm_port_phy_qcfg_input req = {0};
1101 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1103 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1105 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1107 HWRM_CHECK_RESULT();
1109 link_info->phy_link_status = resp->link;
1110 link_info->link_up =
1111 (link_info->phy_link_status ==
1112 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1113 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1114 link_info->duplex = resp->duplex_cfg;
1115 link_info->pause = resp->pause;
1116 link_info->auto_pause = resp->auto_pause;
1117 link_info->force_pause = resp->force_pause;
1118 link_info->auto_mode = resp->auto_mode;
1119 link_info->phy_type = resp->phy_type;
1120 link_info->media_type = resp->media_type;
1122 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1123 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1124 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1125 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1126 link_info->phy_ver[0] = resp->phy_maj;
1127 link_info->phy_ver[1] = resp->phy_min;
1128 link_info->phy_ver[2] = resp->phy_bld;
1132 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1133 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1134 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1135 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1136 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1137 link_info->auto_link_speed_mask);
1138 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1139 link_info->force_link_speed);
1144 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1147 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1148 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1151 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1153 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1154 /* HWRM Version >= 1.9.1 */
1155 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1157 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1158 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1160 HWRM_CHECK_RESULT();
1162 #define GET_QUEUE_INFO(x) \
1163 bp->cos_queue[x].id = resp->queue_id##x; \
1164 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1177 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1178 bp->tx_cosq_id = bp->cos_queue[0].id;
1180 /* iterate and find the COSq profile to use for Tx */
1181 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1182 if (bp->cos_queue[i].profile ==
1183 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1184 bp->tx_cosq_id = bp->cos_queue[i].id;
1190 bp->max_tc = resp->max_configurable_queues;
1191 bp->max_lltc = resp->max_configurable_lossless_queues;
1192 if (bp->max_tc > BNXT_MAX_QUEUE)
1193 bp->max_tc = BNXT_MAX_QUEUE;
1194 bp->max_q = bp->max_tc;
1196 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1201 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1202 struct bnxt_ring *ring,
1203 uint32_t ring_type, uint32_t map_index,
1204 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1207 uint32_t enables = 0;
1208 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1209 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1210 struct rte_mempool *mb_pool;
1211 uint16_t rx_buf_size;
1213 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1215 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1216 req.fbo = rte_cpu_to_le_32(0);
1217 /* Association of ring index with doorbell index */
1218 req.logical_id = rte_cpu_to_le_16(map_index);
1219 req.length = rte_cpu_to_le_32(ring->ring_size);
1221 switch (ring_type) {
1222 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1223 req.ring_type = ring_type;
1224 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1225 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1226 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1227 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1229 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1231 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1232 req.ring_type = ring_type;
1233 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1234 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1235 if (BNXT_CHIP_THOR(bp)) {
1236 mb_pool = bp->rx_queues[0]->mb_pool;
1237 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1238 RTE_PKTMBUF_HEADROOM;
1239 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1241 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1243 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1245 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1247 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1248 req.ring_type = ring_type;
1249 if (BNXT_HAS_NQ(bp)) {
1250 /* Association of cp ring with nq */
1251 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1253 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1255 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1257 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1258 req.ring_type = ring_type;
1259 req.page_size = BNXT_PAGE_SHFT;
1260 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1262 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1263 req.ring_type = ring_type;
1264 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1266 mb_pool = bp->rx_queues[0]->mb_pool;
1267 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1268 RTE_PKTMBUF_HEADROOM;
1269 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1271 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1272 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1273 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1274 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1277 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1282 req.enables = rte_cpu_to_le_32(enables);
1284 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1286 if (rc || resp->error_code) {
1287 if (rc == 0 && resp->error_code)
1288 rc = rte_le_to_cpu_16(resp->error_code);
1289 switch (ring_type) {
1290 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1292 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1295 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1297 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1300 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1302 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1306 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1308 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1311 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1313 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1317 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1323 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1328 int bnxt_hwrm_ring_free(struct bnxt *bp,
1329 struct bnxt_ring *ring, uint32_t ring_type)
1332 struct hwrm_ring_free_input req = {.req_type = 0 };
1333 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1335 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1337 req.ring_type = ring_type;
1338 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1340 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1342 if (rc || resp->error_code) {
1343 if (rc == 0 && resp->error_code)
1344 rc = rte_le_to_cpu_16(resp->error_code);
1347 switch (ring_type) {
1348 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1349 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1352 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1353 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1356 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1357 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1360 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1362 "hwrm_ring_free nq failed. rc:%d\n", rc);
1364 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1366 "hwrm_ring_free agg failed. rc:%d\n", rc);
1369 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1377 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1380 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1381 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1383 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1385 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1386 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1387 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1388 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1390 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1392 HWRM_CHECK_RESULT();
1394 bp->grp_info[idx].fw_grp_id =
1395 rte_le_to_cpu_16(resp->ring_group_id);
1402 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1405 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1406 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1408 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1410 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1412 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1414 HWRM_CHECK_RESULT();
1417 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1421 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1424 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1425 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1427 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1430 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1432 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1434 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1436 HWRM_CHECK_RESULT();
1442 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1443 unsigned int idx __rte_unused)
1446 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1447 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1449 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1451 req.update_period_ms = rte_cpu_to_le_32(0);
1453 req.stats_dma_addr =
1454 rte_cpu_to_le_64(cpr->hw_stats_map);
1456 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1458 HWRM_CHECK_RESULT();
1460 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1467 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1468 unsigned int idx __rte_unused)
1471 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1472 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1474 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1476 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1478 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1480 HWRM_CHECK_RESULT();
1486 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1489 struct hwrm_vnic_alloc_input req = { 0 };
1490 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1492 if (!BNXT_HAS_RING_GRPS(bp))
1493 goto skip_ring_grps;
1495 /* map ring groups to this vnic */
1496 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1497 vnic->start_grp_id, vnic->end_grp_id);
1498 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1499 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1501 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1502 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1503 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1504 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1507 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1508 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1509 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1511 if (vnic->func_default)
1513 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1514 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1516 HWRM_CHECK_RESULT();
1518 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1520 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1524 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1525 struct bnxt_vnic_info *vnic,
1526 struct bnxt_plcmodes_cfg *pmode)
1529 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1530 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1532 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1534 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1536 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1538 HWRM_CHECK_RESULT();
1540 pmode->flags = rte_le_to_cpu_32(resp->flags);
1541 /* dflt_vnic bit doesn't exist in the _cfg command */
1542 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1543 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1544 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1545 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1552 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1553 struct bnxt_vnic_info *vnic,
1554 struct bnxt_plcmodes_cfg *pmode)
1557 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1558 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1560 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1561 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1565 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1567 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1568 req.flags = rte_cpu_to_le_32(pmode->flags);
1569 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1570 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1571 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1572 req.enables = rte_cpu_to_le_32(
1573 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1574 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1575 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1578 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1580 HWRM_CHECK_RESULT();
1586 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1589 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1590 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1591 struct bnxt_plcmodes_cfg pmodes = { 0 };
1592 uint32_t ctx_enable_flag = 0;
1593 uint32_t enables = 0;
1595 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1596 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1600 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1604 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1606 if (BNXT_CHIP_THOR(bp)) {
1607 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1608 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1609 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1611 req.default_rx_ring_id =
1612 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1613 req.default_cmpl_ring_id =
1614 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1615 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1616 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1620 /* Only RSS support for now TBD: COS & LB */
1621 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1622 if (vnic->lb_rule != 0xffff)
1623 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1624 if (vnic->cos_rule != 0xffff)
1625 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1626 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1627 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1628 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1630 enables |= ctx_enable_flag;
1631 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1632 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1633 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1634 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1637 req.enables = rte_cpu_to_le_32(enables);
1638 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1639 req.mru = rte_cpu_to_le_16(vnic->mru);
1640 /* Configure default VNIC only once. */
1641 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1643 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1644 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1646 if (vnic->vlan_strip)
1648 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1651 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1652 if (vnic->roce_dual)
1653 req.flags |= rte_cpu_to_le_32(
1654 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1655 if (vnic->roce_only)
1656 req.flags |= rte_cpu_to_le_32(
1657 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1658 if (vnic->rss_dflt_cr)
1659 req.flags |= rte_cpu_to_le_32(
1660 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1662 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1664 HWRM_CHECK_RESULT();
1667 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1672 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1676 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1677 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1679 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1680 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1683 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1686 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1687 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1688 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1690 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1692 HWRM_CHECK_RESULT();
1694 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1695 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1696 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1697 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1698 vnic->mru = rte_le_to_cpu_16(resp->mru);
1699 vnic->func_default = rte_le_to_cpu_32(
1700 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1701 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1702 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1703 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1704 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1705 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1706 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1707 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1708 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1709 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1710 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1717 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1718 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1722 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1723 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1724 bp->hwrm_cmd_resp_addr;
1726 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1728 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1729 HWRM_CHECK_RESULT();
1731 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1732 if (!BNXT_HAS_RING_GRPS(bp))
1733 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1734 else if (ctx_idx == 0)
1735 vnic->rss_rule = ctx_id;
1742 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1743 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1746 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1747 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1748 bp->hwrm_cmd_resp_addr;
1750 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1751 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1754 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1756 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1758 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1760 HWRM_CHECK_RESULT();
1766 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1769 struct hwrm_vnic_free_input req = {.req_type = 0 };
1770 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1772 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1773 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1777 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1779 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1781 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1783 HWRM_CHECK_RESULT();
1786 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1787 /* Configure default VNIC again if necessary. */
1788 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1789 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1795 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1799 int nr_ctxs = vnic->num_lb_ctxts;
1800 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1801 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1803 for (i = 0; i < nr_ctxs; i++) {
1804 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1806 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1807 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1808 req.hash_mode_flags = vnic->hash_mode;
1810 req.hash_key_tbl_addr =
1811 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1813 req.ring_grp_tbl_addr =
1814 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1815 i * HW_HASH_INDEX_SIZE);
1816 req.ring_table_pair_index = i;
1817 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1819 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1822 HWRM_CHECK_RESULT();
1829 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1830 struct bnxt_vnic_info *vnic)
1833 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1834 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1836 if (!vnic->rss_table)
1839 if (BNXT_CHIP_THOR(bp))
1840 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1842 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1844 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1845 req.hash_mode_flags = vnic->hash_mode;
1847 req.ring_grp_tbl_addr =
1848 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1849 req.hash_key_tbl_addr =
1850 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1851 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1852 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1854 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1856 HWRM_CHECK_RESULT();
1862 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1863 struct bnxt_vnic_info *vnic)
1866 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1867 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1870 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1871 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1875 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1877 req.flags = rte_cpu_to_le_32(
1878 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1880 req.enables = rte_cpu_to_le_32(
1881 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1883 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1884 size -= RTE_PKTMBUF_HEADROOM;
1886 req.jumbo_thresh = rte_cpu_to_le_16(size);
1887 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1889 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1891 HWRM_CHECK_RESULT();
1897 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1898 struct bnxt_vnic_info *vnic, bool enable)
1901 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1902 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1904 if (BNXT_CHIP_THOR(bp))
1907 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1910 req.enables = rte_cpu_to_le_32(
1911 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1912 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1913 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1914 req.flags = rte_cpu_to_le_32(
1915 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1916 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1917 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1918 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1919 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1920 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1921 req.max_agg_segs = rte_cpu_to_le_16(5);
1923 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1924 req.min_agg_len = rte_cpu_to_le_32(512);
1926 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1928 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1930 HWRM_CHECK_RESULT();
1936 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1938 struct hwrm_func_cfg_input req = {0};
1939 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1942 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1943 req.enables = rte_cpu_to_le_32(
1944 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1945 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1946 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1948 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1950 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1951 HWRM_CHECK_RESULT();
1954 bp->pf.vf_info[vf].random_mac = false;
1959 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1963 struct hwrm_func_qstats_input req = {.req_type = 0};
1964 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1966 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1968 req.fid = rte_cpu_to_le_16(fid);
1970 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1972 HWRM_CHECK_RESULT();
1975 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1982 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1983 struct rte_eth_stats *stats)
1986 struct hwrm_func_qstats_input req = {.req_type = 0};
1987 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1989 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1991 req.fid = rte_cpu_to_le_16(fid);
1993 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1995 HWRM_CHECK_RESULT();
1997 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1998 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1999 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2000 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2001 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2002 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2004 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2005 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2006 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2007 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2008 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2009 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2011 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2012 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2013 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2020 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2023 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2024 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2026 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2028 req.fid = rte_cpu_to_le_16(fid);
2030 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2032 HWRM_CHECK_RESULT();
2039 * HWRM utility functions
2042 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2047 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2048 struct bnxt_tx_queue *txq;
2049 struct bnxt_rx_queue *rxq;
2050 struct bnxt_cp_ring_info *cpr;
2052 if (i >= bp->rx_cp_nr_rings) {
2053 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2056 rxq = bp->rx_queues[i];
2060 rc = bnxt_hwrm_stat_clear(bp, cpr);
2067 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2071 struct bnxt_cp_ring_info *cpr;
2073 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2075 if (i >= bp->rx_cp_nr_rings) {
2076 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2078 cpr = bp->rx_queues[i]->cp_ring;
2079 if (BNXT_HAS_RING_GRPS(bp))
2080 bp->grp_info[i].fw_stats_ctx = -1;
2082 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2083 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2084 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2092 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2097 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2098 struct bnxt_tx_queue *txq;
2099 struct bnxt_rx_queue *rxq;
2100 struct bnxt_cp_ring_info *cpr;
2102 if (i >= bp->rx_cp_nr_rings) {
2103 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2106 rxq = bp->rx_queues[i];
2110 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2118 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2123 if (!BNXT_HAS_RING_GRPS(bp))
2126 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2128 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2131 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2139 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2141 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2143 bnxt_hwrm_ring_free(bp, cp_ring,
2144 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2145 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2146 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2147 sizeof(*cpr->cp_desc_ring));
2148 cpr->cp_raw_cons = 0;
2152 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2154 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2156 bnxt_hwrm_ring_free(bp, cp_ring,
2157 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2158 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2159 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2160 sizeof(*cpr->cp_desc_ring));
2161 cpr->cp_raw_cons = 0;
2165 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2167 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2168 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2169 struct bnxt_ring *ring = rxr->rx_ring_struct;
2170 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2172 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2173 bnxt_hwrm_ring_free(bp, ring,
2174 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2175 ring->fw_ring_id = INVALID_HW_RING_ID;
2176 if (BNXT_HAS_RING_GRPS(bp))
2177 bp->grp_info[queue_index].rx_fw_ring_id =
2179 memset(rxr->rx_desc_ring, 0,
2180 rxr->rx_ring_struct->ring_size *
2181 sizeof(*rxr->rx_desc_ring));
2182 memset(rxr->rx_buf_ring, 0,
2183 rxr->rx_ring_struct->ring_size *
2184 sizeof(*rxr->rx_buf_ring));
2187 ring = rxr->ag_ring_struct;
2188 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2189 bnxt_hwrm_ring_free(bp, ring,
2190 BNXT_CHIP_THOR(bp) ?
2191 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2192 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2193 ring->fw_ring_id = INVALID_HW_RING_ID;
2194 memset(rxr->ag_buf_ring, 0,
2195 rxr->ag_ring_struct->ring_size *
2196 sizeof(*rxr->ag_buf_ring));
2198 if (BNXT_HAS_RING_GRPS(bp))
2199 bp->grp_info[queue_index].ag_fw_ring_id =
2202 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2203 bnxt_free_cp_ring(bp, cpr);
2205 bnxt_free_nq_ring(bp, rxq->nq_ring);
2208 if (BNXT_HAS_RING_GRPS(bp))
2209 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2212 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2216 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2217 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2218 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2219 struct bnxt_ring *ring = txr->tx_ring_struct;
2220 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2222 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2223 bnxt_hwrm_ring_free(bp, ring,
2224 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2225 ring->fw_ring_id = INVALID_HW_RING_ID;
2226 memset(txr->tx_desc_ring, 0,
2227 txr->tx_ring_struct->ring_size *
2228 sizeof(*txr->tx_desc_ring));
2229 memset(txr->tx_buf_ring, 0,
2230 txr->tx_ring_struct->ring_size *
2231 sizeof(*txr->tx_buf_ring));
2235 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2236 bnxt_free_cp_ring(bp, cpr);
2237 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2239 bnxt_free_nq_ring(bp, txq->nq_ring);
2243 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2244 bnxt_free_hwrm_rx_ring(bp, i);
2249 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2254 if (!BNXT_HAS_RING_GRPS(bp))
2257 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2258 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2265 void bnxt_free_hwrm_resources(struct bnxt *bp)
2267 /* Release memzone */
2268 rte_free(bp->hwrm_cmd_resp_addr);
2269 rte_free(bp->hwrm_short_cmd_req_addr);
2270 bp->hwrm_cmd_resp_addr = NULL;
2271 bp->hwrm_short_cmd_req_addr = NULL;
2272 bp->hwrm_cmd_resp_dma_addr = 0;
2273 bp->hwrm_short_cmd_req_dma_addr = 0;
2276 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2278 struct rte_pci_device *pdev = bp->pdev;
2279 char type[RTE_MEMZONE_NAMESIZE];
2281 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2282 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2283 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2284 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2285 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2286 if (bp->hwrm_cmd_resp_addr == NULL)
2288 bp->hwrm_cmd_resp_dma_addr =
2289 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2290 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2292 "unable to map response address to physical memory\n");
2295 rte_spinlock_init(&bp->hwrm_lock);
2300 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2302 struct bnxt_filter_info *filter;
2305 STAILQ_FOREACH(filter, &vnic->filter, next) {
2306 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2307 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2308 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2309 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2311 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2312 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2320 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2322 struct bnxt_filter_info *filter;
2323 struct rte_flow *flow;
2326 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2327 filter = flow->filter;
2328 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2329 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2330 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2331 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2332 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2334 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2336 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2344 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2346 struct bnxt_filter_info *filter;
2349 STAILQ_FOREACH(filter, &vnic->filter, next) {
2350 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2351 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2353 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2354 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2357 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2365 void bnxt_free_tunnel_ports(struct bnxt *bp)
2367 if (bp->vxlan_port_cnt)
2368 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2369 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2371 if (bp->geneve_port_cnt)
2372 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2373 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2374 bp->geneve_port = 0;
2377 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2381 if (bp->vnic_info == NULL)
2385 * Cleanup VNICs in reverse order, to make sure the L2 filter
2386 * from vnic0 is last to be cleaned up.
2388 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2389 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2391 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2392 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2396 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2398 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2400 if (BNXT_CHIP_THOR(bp)) {
2401 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2402 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2403 vnic->fw_grp_ids[j]);
2404 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2406 vnic->num_lb_ctxts = 0;
2408 bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2409 vnic->rss_rule = INVALID_HW_RING_ID;
2412 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2414 bnxt_hwrm_vnic_free(bp, vnic);
2416 rte_free(vnic->fw_grp_ids);
2418 /* Ring resources */
2419 bnxt_free_all_hwrm_rings(bp);
2420 bnxt_free_all_hwrm_ring_grps(bp);
2421 bnxt_free_all_hwrm_stat_ctxs(bp);
2422 bnxt_free_tunnel_ports(bp);
2425 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2427 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2429 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2430 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2432 switch (conf_link_speed) {
2433 case ETH_LINK_SPEED_10M_HD:
2434 case ETH_LINK_SPEED_100M_HD:
2436 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2438 return hw_link_duplex;
2441 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2443 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2446 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2448 uint16_t eth_link_speed = 0;
2450 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2451 return ETH_LINK_SPEED_AUTONEG;
2453 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2454 case ETH_LINK_SPEED_100M:
2455 case ETH_LINK_SPEED_100M_HD:
2458 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2460 case ETH_LINK_SPEED_1G:
2462 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2464 case ETH_LINK_SPEED_2_5G:
2466 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2468 case ETH_LINK_SPEED_10G:
2470 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2472 case ETH_LINK_SPEED_20G:
2474 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2476 case ETH_LINK_SPEED_25G:
2478 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2480 case ETH_LINK_SPEED_40G:
2482 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2484 case ETH_LINK_SPEED_50G:
2486 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2488 case ETH_LINK_SPEED_100G:
2490 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2494 "Unsupported link speed %d; default to AUTO\n",
2498 return eth_link_speed;
2501 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2502 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2503 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2504 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2506 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2510 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2513 if (link_speed & ETH_LINK_SPEED_FIXED) {
2514 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2516 if (one_speed & (one_speed - 1)) {
2518 "Invalid advertised speeds (%u) for port %u\n",
2519 link_speed, port_id);
2522 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2524 "Unsupported advertised speed (%u) for port %u\n",
2525 link_speed, port_id);
2529 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2531 "Unsupported advertised speeds (%u) for port %u\n",
2532 link_speed, port_id);
2540 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2544 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2545 if (bp->link_info.support_speeds)
2546 return bp->link_info.support_speeds;
2547 link_speed = BNXT_SUPPORTED_SPEEDS;
2550 if (link_speed & ETH_LINK_SPEED_100M)
2551 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2552 if (link_speed & ETH_LINK_SPEED_100M_HD)
2553 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2554 if (link_speed & ETH_LINK_SPEED_1G)
2555 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2556 if (link_speed & ETH_LINK_SPEED_2_5G)
2557 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2558 if (link_speed & ETH_LINK_SPEED_10G)
2559 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2560 if (link_speed & ETH_LINK_SPEED_20G)
2561 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2562 if (link_speed & ETH_LINK_SPEED_25G)
2563 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2564 if (link_speed & ETH_LINK_SPEED_40G)
2565 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2566 if (link_speed & ETH_LINK_SPEED_50G)
2567 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2568 if (link_speed & ETH_LINK_SPEED_100G)
2569 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2573 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2575 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2577 switch (hw_link_speed) {
2578 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2579 eth_link_speed = ETH_SPEED_NUM_100M;
2581 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2582 eth_link_speed = ETH_SPEED_NUM_1G;
2584 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2585 eth_link_speed = ETH_SPEED_NUM_2_5G;
2587 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2588 eth_link_speed = ETH_SPEED_NUM_10G;
2590 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2591 eth_link_speed = ETH_SPEED_NUM_20G;
2593 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2594 eth_link_speed = ETH_SPEED_NUM_25G;
2596 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2597 eth_link_speed = ETH_SPEED_NUM_40G;
2599 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2600 eth_link_speed = ETH_SPEED_NUM_50G;
2602 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2603 eth_link_speed = ETH_SPEED_NUM_100G;
2605 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2607 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2611 return eth_link_speed;
2614 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2616 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2618 switch (hw_link_duplex) {
2619 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2620 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2622 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2624 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2625 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2628 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2632 return eth_link_duplex;
2635 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2638 struct bnxt_link_info *link_info = &bp->link_info;
2640 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2643 "Get link config failed with rc %d\n", rc);
2646 if (link_info->link_speed)
2648 bnxt_parse_hw_link_speed(link_info->link_speed);
2650 link->link_speed = ETH_SPEED_NUM_NONE;
2651 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2652 link->link_status = link_info->link_up;
2653 link->link_autoneg = link_info->auto_mode ==
2654 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2655 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2660 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2663 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2664 struct bnxt_link_info link_req;
2665 uint16_t speed, autoneg;
2667 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2670 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2671 bp->eth_dev->data->port_id);
2675 memset(&link_req, 0, sizeof(link_req));
2676 link_req.link_up = link_up;
2680 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2681 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2682 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2683 /* Autoneg can be done only when the FW allows */
2684 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2685 bp->link_info.force_link_speed)) {
2686 link_req.phy_flags |=
2687 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2688 link_req.auto_link_speed_mask =
2689 bnxt_parse_eth_link_speed_mask(bp,
2690 dev_conf->link_speeds);
2692 if (bp->link_info.phy_type ==
2693 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2694 bp->link_info.phy_type ==
2695 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2696 bp->link_info.media_type ==
2697 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2698 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2702 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2703 /* If user wants a particular speed try that first. */
2705 link_req.link_speed = speed;
2706 else if (bp->link_info.force_link_speed)
2707 link_req.link_speed = bp->link_info.force_link_speed;
2709 link_req.link_speed = bp->link_info.auto_link_speed;
2711 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2712 link_req.auto_pause = bp->link_info.auto_pause;
2713 link_req.force_pause = bp->link_info.force_pause;
2716 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2719 "Set link config failed with rc %d\n", rc);
2727 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2729 struct hwrm_func_qcfg_input req = {0};
2730 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2734 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2735 req.fid = rte_cpu_to_le_16(0xffff);
2737 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2739 HWRM_CHECK_RESULT();
2741 /* Hard Coded.. 0xfff VLAN ID mask */
2742 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2743 flags = rte_le_to_cpu_16(resp->flags);
2744 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2745 bp->flags |= BNXT_FLAG_MULTI_HOST;
2747 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2748 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2749 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2750 } else if (BNXT_VF(bp) &&
2751 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2752 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2753 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2759 switch (resp->port_partition_type) {
2760 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2761 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2762 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2764 bp->port_partition_type = resp->port_partition_type;
2767 bp->port_partition_type = 0;
2776 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2777 struct hwrm_func_qcaps_output *qcaps)
2779 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2780 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2781 sizeof(qcaps->mac_address));
2782 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2783 qcaps->max_rx_rings = fcfg->num_rx_rings;
2784 qcaps->max_tx_rings = fcfg->num_tx_rings;
2785 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2786 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2788 qcaps->first_vf_id = 0;
2789 qcaps->max_vnics = fcfg->num_vnics;
2790 qcaps->max_decap_records = 0;
2791 qcaps->max_encap_records = 0;
2792 qcaps->max_tx_wm_flows = 0;
2793 qcaps->max_tx_em_flows = 0;
2794 qcaps->max_rx_wm_flows = 0;
2795 qcaps->max_rx_em_flows = 0;
2796 qcaps->max_flow_id = 0;
2797 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2798 qcaps->max_sp_tx_rings = 0;
2799 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2802 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2804 struct hwrm_func_cfg_input req = {0};
2805 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2809 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2810 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2811 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2812 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2813 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2814 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2815 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2816 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2817 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2819 if (BNXT_HAS_RING_GRPS(bp)) {
2820 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2821 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2822 } else if (BNXT_HAS_NQ(bp)) {
2823 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2824 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2827 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2828 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2829 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2830 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2832 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2833 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2834 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2835 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2836 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2837 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2838 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2839 req.fid = rte_cpu_to_le_16(0xffff);
2840 req.enables = rte_cpu_to_le_32(enables);
2842 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2844 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2846 HWRM_CHECK_RESULT();
2852 static void populate_vf_func_cfg_req(struct bnxt *bp,
2853 struct hwrm_func_cfg_input *req,
2856 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2857 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2858 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2859 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2860 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2861 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2862 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2863 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2864 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2865 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2867 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2868 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2870 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2871 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2873 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2875 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2876 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2878 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2879 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2880 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2881 /* TODO: For now, do not support VMDq/RFS on VFs. */
2882 req->num_vnics = rte_cpu_to_le_16(1);
2883 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2887 static void add_random_mac_if_needed(struct bnxt *bp,
2888 struct hwrm_func_cfg_input *cfg_req,
2891 struct rte_ether_addr mac;
2893 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2896 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2898 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2899 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2900 bp->pf.vf_info[vf].random_mac = true;
2902 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2903 RTE_ETHER_ADDR_LEN);
2907 static void reserve_resources_from_vf(struct bnxt *bp,
2908 struct hwrm_func_cfg_input *cfg_req,
2911 struct hwrm_func_qcaps_input req = {0};
2912 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2915 /* Get the actual allocated values now */
2916 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2917 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2918 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2921 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2922 copy_func_cfg_to_qcaps(cfg_req, resp);
2923 } else if (resp->error_code) {
2924 rc = rte_le_to_cpu_16(resp->error_code);
2925 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2926 copy_func_cfg_to_qcaps(cfg_req, resp);
2929 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2930 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2931 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2932 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2933 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2934 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2936 * TODO: While not supporting VMDq with VFs, max_vnics is always
2937 * forced to 1 in this case
2939 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2940 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2945 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2947 struct hwrm_func_qcfg_input req = {0};
2948 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2951 /* Check for zero MAC address */
2952 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2953 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2954 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2955 HWRM_CHECK_RESULT();
2956 rc = rte_le_to_cpu_16(resp->vlan);
2963 static int update_pf_resource_max(struct bnxt *bp)
2965 struct hwrm_func_qcfg_input req = {0};
2966 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2969 /* And copy the allocated numbers into the pf struct */
2970 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2971 req.fid = rte_cpu_to_le_16(0xffff);
2972 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2973 HWRM_CHECK_RESULT();
2975 /* Only TX ring value reflects actual allocation? TODO */
2976 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2977 bp->pf.evb_mode = resp->evb_mode;
2984 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2989 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2993 rc = bnxt_hwrm_func_qcaps(bp);
2997 bp->pf.func_cfg_flags &=
2998 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2999 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3000 bp->pf.func_cfg_flags |=
3001 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3002 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3003 rc = __bnxt_hwrm_func_qcaps(bp);
3007 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3009 struct hwrm_func_cfg_input req = {0};
3010 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3017 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3021 rc = bnxt_hwrm_func_qcaps(bp);
3026 bp->pf.active_vfs = num_vfs;
3029 * First, configure the PF to only use one TX ring. This ensures that
3030 * there are enough rings for all VFs.
3032 * If we don't do this, when we call func_alloc() later, we will lock
3033 * extra rings to the PF that won't be available during func_cfg() of
3036 * This has been fixed with firmware versions above 20.6.54
3038 bp->pf.func_cfg_flags &=
3039 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3040 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3041 bp->pf.func_cfg_flags |=
3042 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3043 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3048 * Now, create and register a buffer to hold forwarded VF requests
3050 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3051 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3052 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3053 if (bp->pf.vf_req_buf == NULL) {
3057 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3058 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3059 for (i = 0; i < num_vfs; i++)
3060 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3061 (i * HWRM_MAX_REQ_LEN);
3063 rc = bnxt_hwrm_func_buf_rgtr(bp);
3067 populate_vf_func_cfg_req(bp, &req, num_vfs);
3069 bp->pf.active_vfs = 0;
3070 for (i = 0; i < num_vfs; i++) {
3071 add_random_mac_if_needed(bp, &req, i);
3073 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3074 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3075 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3076 rc = bnxt_hwrm_send_message(bp,
3081 /* Clear enable flag for next pass */
3082 req.enables &= ~rte_cpu_to_le_32(
3083 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3085 if (rc || resp->error_code) {
3087 "Failed to initizlie VF %d\n", i);
3089 "Not all VFs available. (%d, %d)\n",
3090 rc, resp->error_code);
3097 reserve_resources_from_vf(bp, &req, i);
3098 bp->pf.active_vfs++;
3099 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3103 * Now configure the PF to use "the rest" of the resources
3104 * We're using STD_TX_RING_MODE here though which will limit the TX
3105 * rings. This will allow QoS to function properly. Not setting this
3106 * will cause PF rings to break bandwidth settings.
3108 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3112 rc = update_pf_resource_max(bp);
3119 bnxt_hwrm_func_buf_unrgtr(bp);
3123 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3125 struct hwrm_func_cfg_input req = {0};
3126 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3129 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3131 req.fid = rte_cpu_to_le_16(0xffff);
3132 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3133 req.evb_mode = bp->pf.evb_mode;
3135 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3136 HWRM_CHECK_RESULT();
3142 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3143 uint8_t tunnel_type)
3145 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3146 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3149 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3150 req.tunnel_type = tunnel_type;
3151 req.tunnel_dst_port_val = port;
3152 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3153 HWRM_CHECK_RESULT();
3155 switch (tunnel_type) {
3156 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3157 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3158 bp->vxlan_port = port;
3160 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3161 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3162 bp->geneve_port = port;
3173 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3174 uint8_t tunnel_type)
3176 struct hwrm_tunnel_dst_port_free_input req = {0};
3177 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3180 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3182 req.tunnel_type = tunnel_type;
3183 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3184 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3186 HWRM_CHECK_RESULT();
3192 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3195 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3196 struct hwrm_func_cfg_input req = {0};
3199 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3201 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3202 req.flags = rte_cpu_to_le_32(flags);
3203 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3205 HWRM_CHECK_RESULT();
3211 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3213 uint32_t *flag = flagp;
3215 vnic->flags = *flag;
3218 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3220 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3223 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3226 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3227 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3229 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3231 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3232 req.req_buf_page_size = rte_cpu_to_le_16(
3233 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3234 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3235 req.req_buf_page_addr0 =
3236 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3237 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3239 "unable to map buffer address to physical memory\n");
3243 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3245 HWRM_CHECK_RESULT();
3251 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3254 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3255 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3257 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3260 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3262 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3264 HWRM_CHECK_RESULT();
3270 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3272 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3273 struct hwrm_func_cfg_input req = {0};
3276 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3278 req.fid = rte_cpu_to_le_16(0xffff);
3279 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3280 req.enables = rte_cpu_to_le_32(
3281 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3282 req.async_event_cr = rte_cpu_to_le_16(
3283 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3284 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3286 HWRM_CHECK_RESULT();
3292 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3294 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3295 struct hwrm_func_vf_cfg_input req = {0};
3298 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3300 req.enables = rte_cpu_to_le_32(
3301 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3302 req.async_event_cr = rte_cpu_to_le_16(
3303 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3304 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3306 HWRM_CHECK_RESULT();
3312 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3314 struct hwrm_func_cfg_input req = {0};
3315 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3316 uint16_t dflt_vlan, fid;
3317 uint32_t func_cfg_flags;
3320 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3323 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3324 fid = bp->pf.vf_info[vf].fid;
3325 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3327 fid = rte_cpu_to_le_16(0xffff);
3328 func_cfg_flags = bp->pf.func_cfg_flags;
3329 dflt_vlan = bp->vlan;
3332 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3333 req.fid = rte_cpu_to_le_16(fid);
3334 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3335 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3337 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3339 HWRM_CHECK_RESULT();
3345 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3346 uint16_t max_bw, uint16_t enables)
3348 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3349 struct hwrm_func_cfg_input req = {0};
3352 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3354 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3355 req.enables |= rte_cpu_to_le_32(enables);
3356 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3357 req.max_bw = rte_cpu_to_le_32(max_bw);
3358 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3360 HWRM_CHECK_RESULT();
3366 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3368 struct hwrm_func_cfg_input req = {0};
3369 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3372 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3374 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3375 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3376 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3377 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3379 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3381 HWRM_CHECK_RESULT();
3387 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3392 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3394 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3399 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3400 void *encaped, size_t ec_size)
3403 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3404 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3406 if (ec_size > sizeof(req.encap_request))
3409 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3411 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3412 memcpy(req.encap_request, encaped, ec_size);
3414 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3416 HWRM_CHECK_RESULT();
3422 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3423 struct rte_ether_addr *mac)
3425 struct hwrm_func_qcfg_input req = {0};
3426 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3429 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3431 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3432 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3434 HWRM_CHECK_RESULT();
3436 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3443 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3444 void *encaped, size_t ec_size)
3447 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3448 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3450 if (ec_size > sizeof(req.encap_request))
3453 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3455 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3456 memcpy(req.encap_request, encaped, ec_size);
3458 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3460 HWRM_CHECK_RESULT();
3466 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3467 struct rte_eth_stats *stats, uint8_t rx)
3470 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3471 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3473 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3475 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3477 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3479 HWRM_CHECK_RESULT();
3482 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3483 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3484 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3485 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3486 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3487 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3488 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3489 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3491 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3492 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3493 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3494 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3495 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3496 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3505 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3507 struct hwrm_port_qstats_input req = {0};
3508 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3509 struct bnxt_pf_info *pf = &bp->pf;
3512 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3514 req.port_id = rte_cpu_to_le_16(pf->port_id);
3515 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3516 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3517 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3519 HWRM_CHECK_RESULT();
3525 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3527 struct hwrm_port_clr_stats_input req = {0};
3528 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3529 struct bnxt_pf_info *pf = &bp->pf;
3532 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3533 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3534 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3537 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3539 req.port_id = rte_cpu_to_le_16(pf->port_id);
3540 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3542 HWRM_CHECK_RESULT();
3548 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3550 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3551 struct hwrm_port_led_qcaps_input req = {0};
3557 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3558 req.port_id = bp->pf.port_id;
3559 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3561 HWRM_CHECK_RESULT();
3563 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3566 bp->num_leds = resp->num_leds;
3567 memcpy(bp->leds, &resp->led0_id,
3568 sizeof(bp->leds[0]) * bp->num_leds);
3569 for (i = 0; i < bp->num_leds; i++) {
3570 struct bnxt_led_info *led = &bp->leds[i];
3572 uint16_t caps = led->led_state_caps;
3574 if (!led->led_group_id ||
3575 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3587 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3589 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3590 struct hwrm_port_led_cfg_input req = {0};
3591 struct bnxt_led_cfg *led_cfg;
3592 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3593 uint16_t duration = 0;
3596 if (!bp->num_leds || BNXT_VF(bp))
3599 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3602 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3603 duration = rte_cpu_to_le_16(500);
3605 req.port_id = bp->pf.port_id;
3606 req.num_leds = bp->num_leds;
3607 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3608 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3609 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3610 led_cfg->led_id = bp->leds[i].led_id;
3611 led_cfg->led_state = led_state;
3612 led_cfg->led_blink_on = duration;
3613 led_cfg->led_blink_off = duration;
3614 led_cfg->led_group_id = bp->leds[i].led_group_id;
3617 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3619 HWRM_CHECK_RESULT();
3625 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3629 struct hwrm_nvm_get_dir_info_input req = {0};
3630 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3632 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3634 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3636 HWRM_CHECK_RESULT();
3638 *entries = rte_le_to_cpu_32(resp->entries);
3639 *length = rte_le_to_cpu_32(resp->entry_length);
3645 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3648 uint32_t dir_entries;
3649 uint32_t entry_length;
3652 rte_iova_t dma_handle;
3653 struct hwrm_nvm_get_dir_entries_input req = {0};
3654 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3656 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3660 *data++ = dir_entries;
3661 *data++ = entry_length;
3663 memset(data, 0xff, len);
3665 buflen = dir_entries * entry_length;
3666 buf = rte_malloc("nvm_dir", buflen, 0);
3667 rte_mem_lock_page(buf);
3670 dma_handle = rte_mem_virt2iova(buf);
3671 if (dma_handle == RTE_BAD_IOVA) {
3673 "unable to map response address to physical memory\n");
3676 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3677 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3678 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3681 memcpy(data, buf, len > buflen ? buflen : len);
3684 HWRM_CHECK_RESULT();
3690 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3691 uint32_t offset, uint32_t length,
3696 rte_iova_t dma_handle;
3697 struct hwrm_nvm_read_input req = {0};
3698 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3700 buf = rte_malloc("nvm_item", length, 0);
3701 rte_mem_lock_page(buf);
3705 dma_handle = rte_mem_virt2iova(buf);
3706 if (dma_handle == RTE_BAD_IOVA) {
3708 "unable to map response address to physical memory\n");
3711 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3712 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3713 req.dir_idx = rte_cpu_to_le_16(index);
3714 req.offset = rte_cpu_to_le_32(offset);
3715 req.len = rte_cpu_to_le_32(length);
3716 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3718 memcpy(data, buf, length);
3721 HWRM_CHECK_RESULT();
3727 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3730 struct hwrm_nvm_erase_dir_entry_input req = {0};
3731 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3733 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3734 req.dir_idx = rte_cpu_to_le_16(index);
3735 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3736 HWRM_CHECK_RESULT();
3743 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3744 uint16_t dir_ordinal, uint16_t dir_ext,
3745 uint16_t dir_attr, const uint8_t *data,
3749 struct hwrm_nvm_write_input req = {0};
3750 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3751 rte_iova_t dma_handle;
3754 buf = rte_malloc("nvm_write", data_len, 0);
3755 rte_mem_lock_page(buf);
3759 dma_handle = rte_mem_virt2iova(buf);
3760 if (dma_handle == RTE_BAD_IOVA) {
3762 "unable to map response address to physical memory\n");
3765 memcpy(buf, data, data_len);
3767 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3769 req.dir_type = rte_cpu_to_le_16(dir_type);
3770 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3771 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3772 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3773 req.dir_data_length = rte_cpu_to_le_32(data_len);
3774 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3776 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3779 HWRM_CHECK_RESULT();
3786 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3788 uint32_t *count = cbdata;
3790 *count = *count + 1;
3793 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3794 struct bnxt_vnic_info *vnic __rte_unused)
3799 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3803 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3804 &count, bnxt_vnic_count_hwrm_stub);
3809 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3812 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3813 struct hwrm_func_vf_vnic_ids_query_output *resp =
3814 bp->hwrm_cmd_resp_addr;
3817 /* First query all VNIC ids */
3818 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3820 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3821 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3822 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3824 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3827 "unable to map VNIC ID table address to physical memory\n");
3830 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3831 HWRM_CHECK_RESULT();
3832 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3840 * This function queries the VNIC IDs for a specified VF. It then calls
3841 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3842 * Then it calls the hwrm_cb function to program this new vnic configuration.
3844 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3845 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3846 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3848 struct bnxt_vnic_info vnic;
3850 int i, num_vnic_ids;
3855 /* First query all VNIC ids */
3856 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3857 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3858 RTE_CACHE_LINE_SIZE);
3859 if (vnic_ids == NULL)
3862 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3863 rte_mem_lock_page(((char *)vnic_ids) + sz);
3865 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3867 if (num_vnic_ids < 0)
3868 return num_vnic_ids;
3870 /* Retrieve VNIC, update bd_stall then update */
3872 for (i = 0; i < num_vnic_ids; i++) {
3873 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3874 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3875 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3878 if (vnic.mru <= 4) /* Indicates unallocated */
3881 vnic_cb(&vnic, cbdata);
3883 rc = hwrm_cb(bp, &vnic);
3893 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3896 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3897 struct hwrm_func_cfg_input req = {0};
3900 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3902 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3903 req.enables |= rte_cpu_to_le_32(
3904 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3905 req.vlan_antispoof_mode = on ?
3906 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3907 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3908 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3910 HWRM_CHECK_RESULT();
3916 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3918 struct bnxt_vnic_info vnic;
3921 int num_vnic_ids, i;
3925 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3926 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3927 RTE_CACHE_LINE_SIZE);
3928 if (vnic_ids == NULL)
3931 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3932 rte_mem_lock_page(((char *)vnic_ids) + sz);
3934 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3940 * Loop through to find the default VNIC ID.
3941 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3942 * by sending the hwrm_func_qcfg command to the firmware.
3944 for (i = 0; i < num_vnic_ids; i++) {
3945 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3946 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3947 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3948 bp->pf.first_vf_id + vf);
3951 if (vnic.func_default) {
3953 return vnic.fw_vnic_id;
3956 /* Could not find a default VNIC. */
3957 PMD_DRV_LOG(ERR, "No default VNIC\n");
3963 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3965 struct bnxt_filter_info *filter)
3968 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3969 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3970 uint32_t enables = 0;
3972 if (filter->fw_em_filter_id != UINT64_MAX)
3973 bnxt_hwrm_clear_em_filter(bp, filter);
3975 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3977 req.flags = rte_cpu_to_le_32(filter->flags);
3979 enables = filter->enables |
3980 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3981 req.dst_id = rte_cpu_to_le_16(dst_id);
3983 if (filter->ip_addr_type) {
3984 req.ip_addr_type = filter->ip_addr_type;
3985 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3988 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3989 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3991 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3992 memcpy(req.src_macaddr, filter->src_macaddr,
3993 RTE_ETHER_ADDR_LEN);
3995 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3996 memcpy(req.dst_macaddr, filter->dst_macaddr,
3997 RTE_ETHER_ADDR_LEN);
3999 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4000 req.ovlan_vid = filter->l2_ovlan;
4002 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4003 req.ivlan_vid = filter->l2_ivlan;
4005 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4006 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4008 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4009 req.ip_protocol = filter->ip_protocol;
4011 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4012 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4014 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4015 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4017 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4018 req.src_port = rte_cpu_to_be_16(filter->src_port);
4020 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4021 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4023 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4024 req.mirror_vnic_id = filter->mirror_vnic_id;
4026 req.enables = rte_cpu_to_le_32(enables);
4028 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4030 HWRM_CHECK_RESULT();
4032 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4038 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4041 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4042 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4044 if (filter->fw_em_filter_id == UINT64_MAX)
4047 PMD_DRV_LOG(ERR, "Clear EM filter\n");
4048 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4050 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4052 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4054 HWRM_CHECK_RESULT();
4057 filter->fw_em_filter_id = UINT64_MAX;
4058 filter->fw_l2_filter_id = UINT64_MAX;
4063 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4065 struct bnxt_filter_info *filter)
4068 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4069 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4070 bp->hwrm_cmd_resp_addr;
4071 uint32_t enables = 0;
4073 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4074 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4076 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4078 req.flags = rte_cpu_to_le_32(filter->flags);
4080 enables = filter->enables |
4081 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4082 req.dst_id = rte_cpu_to_le_16(dst_id);
4085 if (filter->ip_addr_type) {
4086 req.ip_addr_type = filter->ip_addr_type;
4088 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4091 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4092 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4094 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4095 memcpy(req.src_macaddr, filter->src_macaddr,
4096 RTE_ETHER_ADDR_LEN);
4098 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4099 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4100 //RTE_ETHER_ADDR_LEN);
4102 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4103 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4105 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4106 req.ip_protocol = filter->ip_protocol;
4108 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4109 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4111 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4112 req.src_ipaddr_mask[0] =
4113 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4115 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4116 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4118 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4119 req.dst_ipaddr_mask[0] =
4120 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4122 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4123 req.src_port = rte_cpu_to_le_16(filter->src_port);
4125 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4126 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4128 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4129 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4131 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4132 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4134 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4135 req.mirror_vnic_id = filter->mirror_vnic_id;
4137 req.enables = rte_cpu_to_le_32(enables);
4139 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4141 HWRM_CHECK_RESULT();
4143 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4149 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4150 struct bnxt_filter_info *filter)
4153 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4154 struct hwrm_cfa_ntuple_filter_free_output *resp =
4155 bp->hwrm_cmd_resp_addr;
4157 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4160 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4162 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4164 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4166 HWRM_CHECK_RESULT();
4169 filter->fw_ntuple_filter_id = UINT64_MAX;
4175 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4177 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4178 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4179 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4180 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4181 uint16_t *ring_tbl = vnic->rss_table;
4182 int nr_ctxs = vnic->num_lb_ctxts;
4183 int max_rings = bp->rx_nr_rings;
4187 for (i = 0, k = 0; i < nr_ctxs; i++) {
4188 struct bnxt_rx_ring_info *rxr;
4189 struct bnxt_cp_ring_info *cpr;
4191 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4193 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4194 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4195 req.hash_mode_flags = vnic->hash_mode;
4197 req.ring_grp_tbl_addr =
4198 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4199 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4200 2 * sizeof(*ring_tbl));
4201 req.hash_key_tbl_addr =
4202 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4204 req.ring_table_pair_index = i;
4205 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4207 for (j = 0; j < 64; j++) {
4210 /* Find next active ring. */
4211 for (cnt = 0; cnt < max_rings; cnt++) {
4212 if (rx_queue_state[k] !=
4213 RTE_ETH_QUEUE_STATE_STOPPED)
4215 if (++k == max_rings)
4219 /* Return if no rings are active. */
4220 if (cnt == max_rings)
4223 /* Add rx/cp ring pair to RSS table. */
4224 rxr = rxqs[k]->rx_ring;
4225 cpr = rxqs[k]->cp_ring;
4227 ring_id = rxr->rx_ring_struct->fw_ring_id;
4228 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4229 ring_id = cpr->cp_ring_struct->fw_ring_id;
4230 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4232 if (++k == max_rings)
4235 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4238 HWRM_CHECK_RESULT();
4245 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4247 unsigned int rss_idx, fw_idx, i;
4249 if (!(vnic->rss_table && vnic->hash_type))
4252 if (BNXT_CHIP_THOR(bp))
4253 return bnxt_vnic_rss_configure_thor(bp, vnic);
4256 * Fill the RSS hash & redirection table with
4257 * ring group ids for all VNICs
4259 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4260 rss_idx++, fw_idx++) {
4261 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4262 fw_idx %= bp->rx_cp_nr_rings;
4263 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4267 if (i == bp->rx_cp_nr_rings)
4269 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4271 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4274 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4275 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4279 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4281 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4282 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4284 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4285 req->num_cmpl_dma_aggr_during_int =
4286 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4288 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4290 /* min timer set to 1/2 of interrupt timer */
4291 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4293 /* buf timer set to 1/4 of interrupt timer */
4294 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4296 req->cmpl_aggr_dma_tmr_during_int =
4297 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4299 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4300 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4301 req->flags = rte_cpu_to_le_16(flags);
4304 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4305 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4307 struct hwrm_ring_aggint_qcaps_input req = {0};
4308 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4313 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4314 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4315 HWRM_CHECK_RESULT();
4317 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4318 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4320 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4321 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4322 agg_req->flags = rte_cpu_to_le_16(flags);
4324 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4325 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4326 agg_req->enables = rte_cpu_to_le_32(enables);
4332 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4333 struct bnxt_coal *coal, uint16_t ring_id)
4335 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4336 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4337 bp->hwrm_cmd_resp_addr;
4340 /* Set ring coalesce parameters only for 100G NICs */
4341 if (BNXT_CHIP_THOR(bp)) {
4342 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4344 } else if (bnxt_stratus_device(bp)) {
4345 bnxt_hwrm_set_coal_params(coal, &req);
4350 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4351 req.ring_id = rte_cpu_to_le_16(ring_id);
4352 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4353 HWRM_CHECK_RESULT();
4358 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4359 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4361 struct hwrm_func_backing_store_qcaps_input req = {0};
4362 struct hwrm_func_backing_store_qcaps_output *resp =
4363 bp->hwrm_cmd_resp_addr;
4366 if (!BNXT_CHIP_THOR(bp) ||
4367 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4372 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4373 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4374 HWRM_CHECK_RESULT_SILENT();
4377 struct bnxt_ctx_pg_info *ctx_pg;
4378 struct bnxt_ctx_mem_info *ctx;
4379 int total_alloc_len;
4382 total_alloc_len = sizeof(*ctx);
4383 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4384 RTE_CACHE_LINE_SIZE);
4389 memset(ctx, 0, total_alloc_len);
4391 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4392 sizeof(*ctx_pg) * BNXT_MAX_Q,
4393 RTE_CACHE_LINE_SIZE);
4398 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4399 ctx->tqm_mem[i] = ctx_pg;
4402 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4403 ctx->qp_min_qp1_entries =
4404 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4405 ctx->qp_max_l2_entries =
4406 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4407 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4408 ctx->srq_max_l2_entries =
4409 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4410 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4411 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4412 ctx->cq_max_l2_entries =
4413 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4414 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4415 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4416 ctx->vnic_max_vnic_entries =
4417 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4418 ctx->vnic_max_ring_table_entries =
4419 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4420 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4421 ctx->stat_max_entries =
4422 rte_le_to_cpu_32(resp->stat_max_entries);
4423 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4424 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4425 ctx->tqm_min_entries_per_ring =
4426 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4427 ctx->tqm_max_entries_per_ring =
4428 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4429 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4430 if (!ctx->tqm_entries_multiple)
4431 ctx->tqm_entries_multiple = 1;
4432 ctx->mrav_max_entries =
4433 rte_le_to_cpu_32(resp->mrav_max_entries);
4434 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4435 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4436 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4445 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4447 struct hwrm_func_backing_store_cfg_input req = {0};
4448 struct hwrm_func_backing_store_cfg_output *resp =
4449 bp->hwrm_cmd_resp_addr;
4450 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4451 struct bnxt_ctx_pg_info *ctx_pg;
4452 uint32_t *num_entries;
4461 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4462 req.enables = rte_cpu_to_le_32(enables);
4464 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4465 ctx_pg = &ctx->qp_mem;
4466 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4467 req.qp_num_qp1_entries =
4468 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4469 req.qp_num_l2_entries =
4470 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4471 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4472 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4473 &req.qpc_pg_size_qpc_lvl,
4477 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4478 ctx_pg = &ctx->srq_mem;
4479 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4480 req.srq_num_l2_entries =
4481 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4482 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4483 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4484 &req.srq_pg_size_srq_lvl,
4488 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4489 ctx_pg = &ctx->cq_mem;
4490 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4491 req.cq_num_l2_entries =
4492 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4493 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4494 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4495 &req.cq_pg_size_cq_lvl,
4499 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4500 ctx_pg = &ctx->vnic_mem;
4501 req.vnic_num_vnic_entries =
4502 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4503 req.vnic_num_ring_table_entries =
4504 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4505 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4506 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4507 &req.vnic_pg_size_vnic_lvl,
4508 &req.vnic_page_dir);
4511 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4512 ctx_pg = &ctx->stat_mem;
4513 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4514 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4515 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4516 &req.stat_pg_size_stat_lvl,
4517 &req.stat_page_dir);
4520 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4521 num_entries = &req.tqm_sp_num_entries;
4522 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4523 pg_dir = &req.tqm_sp_page_dir;
4524 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4525 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4526 if (!(enables & ena))
4529 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4531 ctx_pg = ctx->tqm_mem[i];
4532 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4533 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4536 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4537 HWRM_CHECK_RESULT();
4543 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4545 struct hwrm_port_qstats_ext_input req = {0};
4546 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4547 struct bnxt_pf_info *pf = &bp->pf;
4550 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4551 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4554 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4556 req.port_id = rte_cpu_to_le_16(pf->port_id);
4557 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4558 req.tx_stat_host_addr =
4559 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4561 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4563 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4564 req.rx_stat_host_addr =
4565 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4567 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4569 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4572 bp->fw_rx_port_stats_ext_size = 0;
4573 bp->fw_tx_port_stats_ext_size = 0;
4575 bp->fw_rx_port_stats_ext_size =
4576 rte_le_to_cpu_16(resp->rx_stat_size);
4577 bp->fw_tx_port_stats_ext_size =
4578 rte_le_to_cpu_16(resp->tx_stat_size);
4581 HWRM_CHECK_RESULT();
4588 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4590 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4591 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4592 bp->hwrm_cmd_resp_addr;
4595 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4596 req.tunnel_type = type;
4597 req.dest_fid = bp->fw_fid;
4598 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4599 HWRM_CHECK_RESULT();
4607 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4609 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4610 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4611 bp->hwrm_cmd_resp_addr;
4614 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4615 req.tunnel_type = type;
4616 req.dest_fid = bp->fw_fid;
4617 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4618 HWRM_CHECK_RESULT();
4625 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4627 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4628 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4629 bp->hwrm_cmd_resp_addr;
4632 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4633 req.src_fid = bp->fw_fid;
4634 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4635 HWRM_CHECK_RESULT();
4638 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4645 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4648 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4649 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4650 bp->hwrm_cmd_resp_addr;
4653 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4654 req.src_fid = bp->fw_fid;
4655 req.tunnel_type = tun_type;
4656 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4657 HWRM_CHECK_RESULT();
4660 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4662 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4669 int bnxt_hwrm_set_mac(struct bnxt *bp)
4671 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4672 struct hwrm_func_vf_cfg_input req = {0};
4678 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4681 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4682 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4684 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4686 HWRM_CHECK_RESULT();
4688 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4694 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4696 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4697 struct hwrm_func_drv_if_change_input req = {0};
4701 if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4704 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4705 * If we issue FUNC_DRV_IF_CHANGE with flags down before
4706 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4708 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4711 HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4715 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4717 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4719 HWRM_CHECK_RESULT();
4720 flags = rte_le_to_cpu_32(resp->flags);
4723 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4724 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4725 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4731 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4733 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4734 struct bnxt_error_recovery_info *info = bp->recovery_info;
4735 struct hwrm_error_recovery_qcfg_input req = {0};
4740 /* Older FW does not have error recovery support */
4741 if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4745 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4747 bp->recovery_info = info;
4751 memset(info, 0, sizeof(*info));
4754 HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4756 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4758 HWRM_CHECK_RESULT();
4760 flags = rte_le_to_cpu_32(resp->flags);
4761 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4762 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4763 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4764 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4766 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4767 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4772 /* FW returned values are in units of 100msec */
4773 info->driver_polling_freq =
4774 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4775 info->master_func_wait_period =
4776 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4777 info->normal_func_wait_period =
4778 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4779 info->master_func_wait_period_after_reset =
4780 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4781 info->max_bailout_time_after_reset =
4782 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4783 info->status_regs[BNXT_FW_STATUS_REG] =
4784 rte_le_to_cpu_32(resp->fw_health_status_reg);
4785 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4786 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4787 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4788 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4789 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4790 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4791 info->reg_array_cnt =
4792 rte_le_to_cpu_32(resp->reg_array_cnt);
4794 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4799 for (i = 0; i < info->reg_array_cnt; i++) {
4800 info->reset_reg[i] =
4801 rte_le_to_cpu_32(resp->reset_reg[i]);
4802 info->reset_reg_val[i] =
4803 rte_le_to_cpu_32(resp->reset_reg_val[i]);
4804 info->delay_after_reset[i] =
4805 resp->delay_after_reset[i];
4810 /* Map the FW status registers */
4812 rc = bnxt_map_fw_health_status_regs(bp);
4815 rte_free(bp->recovery_info);
4816 bp->recovery_info = NULL;
4821 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4823 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4824 struct hwrm_fw_reset_input req = {0};
4830 HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4832 req.embedded_proc_type =
4833 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4834 req.selfrst_status =
4835 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4836 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4838 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4841 HWRM_CHECK_RESULT();
4847 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4849 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4850 struct hwrm_port_ts_query_input req = {0};
4851 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4858 HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4861 case BNXT_PTP_FLAGS_PATH_TX:
4862 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4864 case BNXT_PTP_FLAGS_PATH_RX:
4865 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4867 case BNXT_PTP_FLAGS_CURRENT_TIME:
4868 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
4872 req.flags = rte_cpu_to_le_32(flags);
4873 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
4875 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4877 HWRM_CHECK_RESULT();
4880 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
4882 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;