4 * Copyright(c) Broadcom Limited.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_byteorder.h>
35 #include <rte_common.h>
36 #include <rte_cycles.h>
37 #include <rte_malloc.h>
38 #include <rte_memzone.h>
39 #include <rte_version.h>
43 #include "bnxt_filter.h"
44 #include "bnxt_hwrm.h"
47 #include "bnxt_vnic.h"
48 #include "hsi_struct_def_dpdk.h"
50 #define HWRM_CMD_TIMEOUT 2000
53 * HWRM Functions (sent to HWRM)
54 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
55 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
56 * command was failed by the ChiMP.
59 static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
63 struct input *req = msg;
64 struct output *resp = bp->hwrm_cmd_resp_addr;
69 /* Write request msg to hwrm channel */
70 for (i = 0; i < msg_len; i += 4) {
71 bar = (uint8_t *)bp->bar0 + i;
72 *(volatile uint32_t *)bar = *data;
76 /* Zero the rest of the request space */
77 for (; i < bp->max_req_len; i += 4) {
78 bar = (uint8_t *)bp->bar0 + i;
79 *(volatile uint32_t *)bar = 0;
82 /* Ring channel doorbell */
83 bar = (uint8_t *)bp->bar0 + 0x100;
84 *(volatile uint32_t *)bar = 1;
86 /* Poll for the valid bit */
87 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
88 /* Sanity check on the resp->resp_len */
90 if (resp->resp_len && resp->resp_len <=
92 /* Last byte of resp contains the valid key */
93 valid = (uint8_t *)resp + resp->resp_len - 1;
94 if (*valid == HWRM_RESP_VALID_KEY)
100 if (i >= HWRM_CMD_TIMEOUT) {
101 RTE_LOG(ERR, PMD, "Error sending msg %x\n",
111 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)
115 rte_spinlock_lock(&bp->hwrm_lock);
116 rc = bnxt_hwrm_send_message_locked(bp, msg, msg_len);
117 rte_spinlock_unlock(&bp->hwrm_lock);
121 #define HWRM_PREP(req, type, cr, resp) \
122 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
123 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
124 req.cmpl_ring = rte_cpu_to_le_16(cr); \
125 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
126 req.target_id = rte_cpu_to_le_16(0xffff); \
127 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr)
129 #define HWRM_CHECK_RESULT \
132 RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
136 if (resp->error_code) { \
137 rc = rte_le_to_cpu_16(resp->error_code); \
138 RTE_LOG(ERR, PMD, "%s error %d\n", __func__, rc); \
143 int bnxt_hwrm_clear_filter(struct bnxt *bp,
144 struct bnxt_filter_info *filter)
147 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
148 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
150 HWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);
152 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
154 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
158 filter->fw_l2_filter_id = -1;
163 int bnxt_hwrm_set_filter(struct bnxt *bp,
164 struct bnxt_vnic_info *vnic,
165 struct bnxt_filter_info *filter)
168 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
169 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
170 uint32_t enables = 0;
172 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, -1, resp);
174 req.flags = rte_cpu_to_le_32(filter->flags);
176 enables = filter->enables |
177 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
178 req.dst_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
181 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
182 memcpy(req.l2_addr, filter->l2_addr,
185 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
186 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
189 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
190 req.l2_ovlan = filter->l2_ovlan;
192 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
193 req.l2_ovlan_mask = filter->l2_ovlan_mask;
195 req.enables = rte_cpu_to_le_32(enables);
197 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
201 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
206 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, void *fwd_cmd)
209 struct hwrm_exec_fwd_resp_input req = {.req_type = 0 };
210 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
212 HWRM_PREP(req, EXEC_FWD_RESP, -1, resp);
214 memcpy(req.encap_request, fwd_cmd,
215 sizeof(req.encap_request));
217 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
224 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
227 struct hwrm_func_qcaps_input req = {.req_type = 0 };
228 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
230 HWRM_PREP(req, FUNC_QCAPS, -1, resp);
232 req.fid = rte_cpu_to_le_16(0xffff);
234 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
239 struct bnxt_pf_info *pf = &bp->pf;
241 pf->fw_fid = rte_le_to_cpu_32(resp->fid);
242 pf->port_id = resp->port_id;
243 memcpy(pf->mac_addr, resp->perm_mac_address, ETHER_ADDR_LEN);
244 pf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
245 pf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
246 pf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
247 pf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
248 pf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
249 pf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
250 pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
251 pf->max_vfs = rte_le_to_cpu_16(resp->max_vfs);
253 struct bnxt_vf_info *vf = &bp->vf;
255 vf->fw_fid = rte_le_to_cpu_32(resp->fid);
256 memcpy(vf->mac_addr, &resp->perm_mac_address, ETHER_ADDR_LEN);
257 vf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
258 vf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
259 vf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
260 vf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
261 vf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
262 vf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
268 int bnxt_hwrm_func_reset(struct bnxt *bp)
271 struct hwrm_func_reset_input req = {.req_type = 0 };
272 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
274 HWRM_PREP(req, FUNC_RESET, -1, resp);
276 req.enables = rte_cpu_to_le_32(0);
278 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
285 int bnxt_hwrm_func_driver_register(struct bnxt *bp, uint32_t flags,
286 uint32_t *vf_req_fwd)
289 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
290 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
292 if (bp->flags & BNXT_FLAG_REGISTERED)
295 HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
297 req.enables = HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER;
298 req.ver_maj = RTE_VER_YEAR;
299 req.ver_min = RTE_VER_MONTH;
300 req.ver_upd = RTE_VER_MINOR;
302 memcpy(req.vf_req_fwd, vf_req_fwd, sizeof(req.vf_req_fwd));
304 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
308 bp->flags |= BNXT_FLAG_REGISTERED;
313 int bnxt_hwrm_ver_get(struct bnxt *bp)
316 struct hwrm_ver_get_input req = {.req_type = 0 };
317 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
320 uint16_t max_resp_len;
321 char type[RTE_MEMZONE_NAMESIZE];
323 HWRM_PREP(req, VER_GET, -1, resp);
325 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
326 req.hwrm_intf_min = HWRM_VERSION_MINOR;
327 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
330 * Hold the lock since we may be adjusting the response pointers.
332 rte_spinlock_lock(&bp->hwrm_lock);
333 rc = bnxt_hwrm_send_message_locked(bp, &req, sizeof(req));
337 RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
338 resp->hwrm_intf_maj, resp->hwrm_intf_min,
340 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
342 my_version = HWRM_VERSION_MAJOR << 16;
343 my_version |= HWRM_VERSION_MINOR << 8;
344 my_version |= HWRM_VERSION_UPDATE;
346 fw_version = resp->hwrm_intf_maj << 16;
347 fw_version |= resp->hwrm_intf_min << 8;
348 fw_version |= resp->hwrm_intf_upd;
350 if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
351 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
356 if (my_version != fw_version) {
357 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
358 if (my_version < fw_version) {
360 "Firmware API version is newer than driver.\n");
362 "The driver may be missing features.\n");
365 "Firmware API version is older than driver.\n");
367 "Not all driver features may be functional.\n");
371 if (bp->max_req_len > resp->max_req_win_len) {
372 RTE_LOG(ERR, PMD, "Unsupported request length\n");
375 bp->max_req_len = resp->max_req_win_len;
376 max_resp_len = resp->max_resp_len;
377 if (bp->max_resp_len != max_resp_len) {
378 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
379 bp->pdev->addr.domain, bp->pdev->addr.bus,
380 bp->pdev->addr.devid, bp->pdev->addr.function);
382 rte_free(bp->hwrm_cmd_resp_addr);
384 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
385 if (bp->hwrm_cmd_resp_addr == NULL) {
389 bp->hwrm_cmd_resp_dma_addr =
390 rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
391 bp->max_resp_len = max_resp_len;
395 rte_spinlock_unlock(&bp->hwrm_lock);
399 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
402 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
403 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
405 if (!(bp->flags & BNXT_FLAG_REGISTERED))
408 HWRM_PREP(req, FUNC_DRV_UNRGTR, -1, resp);
411 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
415 bp->flags &= ~BNXT_FLAG_REGISTERED;
420 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
423 struct hwrm_port_phy_cfg_input req = {.req_type = 0};
424 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
426 HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
428 req.flags = conf->phy_flags;
430 req.force_link_speed = conf->link_speed;
432 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
433 * any auto mode, even "none".
435 if (req.auto_mode == HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE) {
436 req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
438 req.auto_mode = conf->auto_mode;
440 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
441 req.auto_link_speed_mask = conf->auto_link_speed_mask;
443 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
444 req.auto_link_speed = conf->auto_link_speed;
446 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
448 req.auto_duplex = conf->duplex;
449 req.enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
450 req.auto_pause = conf->auto_pause;
451 /* Set force_pause if there is no auto or if there is a force */
454 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
457 HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
458 req.force_pause = conf->force_pause;
461 HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
463 req.flags &= ~HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
464 req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN;
465 req.force_link_speed = 0;
468 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
475 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
478 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
479 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
481 HWRM_PREP(req, QUEUE_QPORTCFG, -1, resp);
483 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
487 #define GET_QUEUE_INFO(x) \
488 bp->cos_queue[x].id = resp->queue_id##x; \
489 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
503 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
506 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
507 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
509 HWRM_PREP(req, STAT_CTX_CLR_STATS, -1, resp);
511 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
514 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
515 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
517 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
525 * HWRM utility functions
528 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
533 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
534 struct bnxt_tx_queue *txq;
535 struct bnxt_rx_queue *rxq;
536 struct bnxt_cp_ring_info *cpr;
538 if (i >= bp->rx_cp_nr_rings) {
539 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
542 rxq = bp->rx_queues[i];
546 rc = bnxt_hwrm_stat_clear(bp, cpr);
553 void bnxt_free_hwrm_resources(struct bnxt *bp)
555 /* Release memzone */
556 rte_free(bp->hwrm_cmd_resp_addr);
557 bp->hwrm_cmd_resp_addr = NULL;
558 bp->hwrm_cmd_resp_dma_addr = 0;
561 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
563 struct rte_pci_device *pdev = bp->pdev;
564 char type[RTE_MEMZONE_NAMESIZE];
566 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
567 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
568 bp->max_req_len = HWRM_MAX_REQ_LEN;
569 bp->max_resp_len = HWRM_MAX_RESP_LEN;
570 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
571 if (bp->hwrm_cmd_resp_addr == NULL)
573 bp->hwrm_cmd_resp_dma_addr =
574 rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
575 rte_spinlock_init(&bp->hwrm_lock);
580 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
582 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
584 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
585 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
587 switch (conf_link_speed) {
588 case ETH_LINK_SPEED_10M_HD:
589 case ETH_LINK_SPEED_100M_HD:
590 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
592 return hw_link_duplex;
595 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
597 uint16_t eth_link_speed = 0;
599 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
600 return ETH_LINK_SPEED_AUTONEG;
602 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
603 case ETH_LINK_SPEED_100M:
604 case ETH_LINK_SPEED_100M_HD:
606 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB;
608 case ETH_LINK_SPEED_1G:
610 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
612 case ETH_LINK_SPEED_2_5G:
614 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
616 case ETH_LINK_SPEED_10G:
618 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
620 case ETH_LINK_SPEED_20G:
622 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
624 case ETH_LINK_SPEED_25G:
626 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
628 case ETH_LINK_SPEED_40G:
630 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
632 case ETH_LINK_SPEED_50G:
634 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
638 "Unsupported link speed %d; default to AUTO\n",
642 return eth_link_speed;
645 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
646 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
647 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
648 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
650 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
654 if (link_speed == ETH_LINK_SPEED_AUTONEG)
657 if (link_speed & ETH_LINK_SPEED_FIXED) {
658 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
660 if (one_speed & (one_speed - 1)) {
662 "Invalid advertised speeds (%u) for port %u\n",
663 link_speed, port_id);
666 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
668 "Unsupported advertised speed (%u) for port %u\n",
669 link_speed, port_id);
673 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
675 "Unsupported advertised speeds (%u) for port %u\n",
676 link_speed, port_id);
683 static uint16_t bnxt_parse_eth_link_speed_mask(uint32_t link_speed)
687 if (link_speed == ETH_LINK_SPEED_AUTONEG)
688 link_speed = BNXT_SUPPORTED_SPEEDS;
690 if (link_speed & ETH_LINK_SPEED_100M)
691 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
692 if (link_speed & ETH_LINK_SPEED_100M_HD)
693 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
694 if (link_speed & ETH_LINK_SPEED_1G)
695 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
696 if (link_speed & ETH_LINK_SPEED_2_5G)
697 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
698 if (link_speed & ETH_LINK_SPEED_10G)
699 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
700 if (link_speed & ETH_LINK_SPEED_20G)
701 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
702 if (link_speed & ETH_LINK_SPEED_25G)
703 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
704 if (link_speed & ETH_LINK_SPEED_40G)
705 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
706 if (link_speed & ETH_LINK_SPEED_50G)
707 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
711 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
714 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
715 struct bnxt_link_info link_req;
718 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
719 bp->eth_dev->data->port_id);
723 memset(&link_req, 0, sizeof(link_req));
724 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
725 link_req.link_up = link_up;
728 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
730 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW;
731 link_req.auto_link_speed_mask =
732 bnxt_parse_eth_link_speed_mask(dev_conf->link_speeds);
733 link_req.auto_link_speed =
734 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB;
736 link_req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
737 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE |
738 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
739 link_req.link_speed = speed;
741 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
742 link_req.auto_pause = bp->link_info.auto_pause;
743 link_req.force_pause = bp->link_info.force_pause;
745 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
748 "Set link config failed with rc %d\n", rc);