4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <rte_byteorder.h>
37 #include <rte_common.h>
38 #include <rte_cycles.h>
39 #include <rte_malloc.h>
40 #include <rte_memzone.h>
41 #include <rte_version.h>
45 #include "bnxt_filter.h"
46 #include "bnxt_hwrm.h"
49 #include "bnxt_ring.h"
52 #include "bnxt_vnic.h"
53 #include "hsi_struct_def_dpdk.h"
57 #define HWRM_CMD_TIMEOUT 10000
59 struct bnxt_plcmodes_cfg {
61 uint16_t jumbo_thresh;
63 uint16_t hds_threshold;
66 static int page_getenum(size_t size)
82 RTE_LOG(ERR, PMD, "Page size %zu out of range\n", size);
83 return sizeof(void *) * 8 - 1;
86 static int page_roundup(size_t size)
88 return 1 << page_getenum(size);
92 * HWRM Functions (sent to HWRM)
93 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
94 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
95 * command was failed by the ChiMP.
98 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
102 struct input *req = msg;
103 struct output *resp = bp->hwrm_cmd_resp_addr;
104 uint32_t *data = msg;
107 uint16_t max_req_len = bp->max_req_len;
108 struct hwrm_short_input short_input = { 0 };
110 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
111 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
113 memset(short_cmd_req, 0, bp->max_req_len);
114 memcpy(short_cmd_req, req, msg_len);
116 short_input.req_type = rte_cpu_to_le_16(req->req_type);
117 short_input.signature = rte_cpu_to_le_16(
118 HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
119 short_input.size = rte_cpu_to_le_16(msg_len);
120 short_input.req_addr =
121 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
123 data = (uint32_t *)&short_input;
124 msg_len = sizeof(short_input);
126 /* Sync memory write before updating doorbell */
129 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
132 /* Write request msg to hwrm channel */
133 for (i = 0; i < msg_len; i += 4) {
134 bar = (uint8_t *)bp->bar0 + i;
135 rte_write32(*data, bar);
139 /* Zero the rest of the request space */
140 for (; i < max_req_len; i += 4) {
141 bar = (uint8_t *)bp->bar0 + i;
145 /* Ring channel doorbell */
146 bar = (uint8_t *)bp->bar0 + 0x100;
149 /* Poll for the valid bit */
150 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
151 /* Sanity check on the resp->resp_len */
153 if (resp->resp_len && resp->resp_len <=
155 /* Last byte of resp contains the valid key */
156 valid = (uint8_t *)resp + resp->resp_len - 1;
157 if (*valid == HWRM_RESP_VALID_KEY)
163 if (i >= HWRM_CMD_TIMEOUT) {
164 RTE_LOG(ERR, PMD, "Error sending msg 0x%04x\n",
175 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
176 * spinlock, and does initial processing.
178 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
179 * releases the spinlock only if it returns. If the regular int return codes
180 * are not used by the function, HWRM_CHECK_RESULT() should not be used
181 * directly, rather it should be copied and modified to suit the function.
183 * HWRM_UNLOCK() must be called after all response processing is completed.
185 #define HWRM_PREP(req, type) do { \
186 rte_spinlock_lock(&bp->hwrm_lock); \
187 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
188 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
189 req.cmpl_ring = rte_cpu_to_le_16(-1); \
190 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
191 req.target_id = rte_cpu_to_le_16(0xffff); \
192 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
195 #define HWRM_CHECK_RESULT() do {\
197 RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
199 rte_spinlock_unlock(&bp->hwrm_lock); \
202 if (resp->error_code) { \
203 rc = rte_le_to_cpu_16(resp->error_code); \
204 if (resp->resp_len >= 16) { \
205 struct hwrm_err_output *tmp_hwrm_err_op = \
208 "%s error %d:%d:%08x:%04x\n", \
210 rc, tmp_hwrm_err_op->cmd_err, \
212 tmp_hwrm_err_op->opaque_0), \
214 tmp_hwrm_err_op->opaque_1)); \
218 "%s error %d\n", __func__, rc); \
220 rte_spinlock_unlock(&bp->hwrm_lock); \
225 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
227 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
230 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
231 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
233 HWRM_PREP(req, CFA_L2_SET_RX_MASK);
234 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
237 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
245 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
246 struct bnxt_vnic_info *vnic,
248 struct bnxt_vlan_table_entry *vlan_table)
251 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
252 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
255 HWRM_PREP(req, CFA_L2_SET_RX_MASK);
256 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
258 /* FIXME add multicast flag, when multicast adding options is supported
261 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
262 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
263 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
264 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
265 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
266 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
267 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
268 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
269 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
270 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
271 if (vnic->mc_addr_cnt) {
272 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
273 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
274 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
277 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
278 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
279 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
280 rte_mem_virt2iova(vlan_table));
281 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
283 req.mask = rte_cpu_to_le_32(mask);
285 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
293 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
295 struct bnxt_vlan_antispoof_table_entry *vlan_table)
298 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
299 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
300 bp->hwrm_cmd_resp_addr;
303 * Older HWRM versions did not support this command, and the set_rx_mask
304 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
305 * removed from set_rx_mask call, and this command was added.
307 * This command is also present from 1.7.8.11 and higher,
310 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
311 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
312 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
317 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG);
318 req.fid = rte_cpu_to_le_16(fid);
320 req.vlan_tag_mask_tbl_addr =
321 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
322 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
324 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
332 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
333 struct bnxt_filter_info *filter)
336 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
337 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
339 if (filter->fw_l2_filter_id == UINT64_MAX)
342 HWRM_PREP(req, CFA_L2_FILTER_FREE);
344 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
346 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
351 filter->fw_l2_filter_id = -1;
356 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
358 struct bnxt_filter_info *filter)
361 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
362 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
363 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
364 const struct rte_eth_vmdq_rx_conf *conf =
365 &dev_conf->rx_adv_conf.vmdq_rx_conf;
366 uint32_t enables = 0;
367 uint16_t j = dst_id - 1;
369 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
370 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
371 conf->pool_map[j].pools & (1UL << j)) {
373 "Add vlan %u to vmdq pool %u\n",
374 conf->pool_map[j].vlan_id, j);
376 filter->l2_ivlan = conf->pool_map[j].vlan_id;
378 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
379 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
382 if (filter->fw_l2_filter_id != UINT64_MAX)
383 bnxt_hwrm_clear_l2_filter(bp, filter);
385 HWRM_PREP(req, CFA_L2_FILTER_ALLOC);
387 req.flags = rte_cpu_to_le_32(filter->flags);
389 enables = filter->enables |
390 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
391 req.dst_id = rte_cpu_to_le_16(dst_id);
394 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
395 memcpy(req.l2_addr, filter->l2_addr,
398 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
399 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
402 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
403 req.l2_ovlan = filter->l2_ovlan;
405 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
406 req.l2_ovlan = filter->l2_ivlan;
408 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
409 req.l2_ovlan_mask = filter->l2_ovlan_mask;
411 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
412 req.l2_ovlan_mask = filter->l2_ivlan_mask;
413 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
414 req.src_id = rte_cpu_to_le_32(filter->src_id);
415 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
416 req.src_type = filter->src_type;
418 req.enables = rte_cpu_to_le_32(enables);
420 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
424 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
430 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
433 struct hwrm_func_qcaps_input req = {.req_type = 0 };
434 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
435 uint16_t new_max_vfs;
438 HWRM_PREP(req, FUNC_QCAPS);
440 req.fid = rte_cpu_to_le_16(0xffff);
442 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
446 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
448 bp->pf.port_id = resp->port_id;
449 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
450 new_max_vfs = bp->pdev->max_vfs;
451 if (new_max_vfs != bp->pf.max_vfs) {
453 rte_free(bp->pf.vf_info);
454 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
455 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
456 bp->pf.max_vfs = new_max_vfs;
457 for (i = 0; i < new_max_vfs; i++) {
458 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
459 bp->pf.vf_info[i].vlan_table =
460 rte_zmalloc("VF VLAN table",
463 if (bp->pf.vf_info[i].vlan_table == NULL)
465 "Fail to alloc VLAN table for VF %d\n",
469 bp->pf.vf_info[i].vlan_table);
470 bp->pf.vf_info[i].vlan_as_table =
471 rte_zmalloc("VF VLAN AS table",
474 if (bp->pf.vf_info[i].vlan_as_table == NULL)
476 "Alloc VLAN AS table for VF %d fail\n",
480 bp->pf.vf_info[i].vlan_as_table);
481 STAILQ_INIT(&bp->pf.vf_info[i].filter);
486 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
487 memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
488 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
489 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
490 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
491 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
492 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
493 /* TODO: For now, do not support VMDq/RFS on VFs. */
498 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
502 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
504 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
510 int bnxt_hwrm_func_reset(struct bnxt *bp)
513 struct hwrm_func_reset_input req = {.req_type = 0 };
514 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
516 HWRM_PREP(req, FUNC_RESET);
518 req.enables = rte_cpu_to_le_32(0);
520 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
528 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
531 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
532 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
534 if (bp->flags & BNXT_FLAG_REGISTERED)
537 HWRM_PREP(req, FUNC_DRV_RGTR);
538 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
539 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
540 req.ver_maj = RTE_VER_YEAR;
541 req.ver_min = RTE_VER_MONTH;
542 req.ver_upd = RTE_VER_MINOR;
545 req.enables |= rte_cpu_to_le_32(
546 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
547 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
548 RTE_MIN(sizeof(req.vf_req_fwd),
549 sizeof(bp->pf.vf_req_fwd)));
552 req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1); /* TODO: Use MACRO */
553 //memset(req.async_event_fwd, 0xff, sizeof(req.async_event_fwd));
555 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
560 bp->flags |= BNXT_FLAG_REGISTERED;
565 int bnxt_hwrm_ver_get(struct bnxt *bp)
568 struct hwrm_ver_get_input req = {.req_type = 0 };
569 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
572 uint16_t max_resp_len;
573 char type[RTE_MEMZONE_NAMESIZE];
574 uint32_t dev_caps_cfg;
576 bp->max_req_len = HWRM_MAX_REQ_LEN;
577 HWRM_PREP(req, VER_GET);
579 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
580 req.hwrm_intf_min = HWRM_VERSION_MINOR;
581 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
583 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
587 RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
588 resp->hwrm_intf_maj, resp->hwrm_intf_min,
590 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
591 bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
592 (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
593 RTE_LOG(INFO, PMD, "Driver HWRM version: %d.%d.%d\n",
594 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
596 my_version = HWRM_VERSION_MAJOR << 16;
597 my_version |= HWRM_VERSION_MINOR << 8;
598 my_version |= HWRM_VERSION_UPDATE;
600 fw_version = resp->hwrm_intf_maj << 16;
601 fw_version |= resp->hwrm_intf_min << 8;
602 fw_version |= resp->hwrm_intf_upd;
604 if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
605 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
610 if (my_version != fw_version) {
611 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
612 if (my_version < fw_version) {
614 "Firmware API version is newer than driver.\n");
616 "The driver may be missing features.\n");
619 "Firmware API version is older than driver.\n");
621 "Not all driver features may be functional.\n");
625 if (bp->max_req_len > resp->max_req_win_len) {
626 RTE_LOG(ERR, PMD, "Unsupported request length\n");
629 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
630 max_resp_len = resp->max_resp_len;
631 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
633 if (bp->max_resp_len != max_resp_len) {
634 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
635 bp->pdev->addr.domain, bp->pdev->addr.bus,
636 bp->pdev->addr.devid, bp->pdev->addr.function);
638 rte_free(bp->hwrm_cmd_resp_addr);
640 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
641 if (bp->hwrm_cmd_resp_addr == NULL) {
645 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
646 bp->hwrm_cmd_resp_dma_addr =
647 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
648 if (bp->hwrm_cmd_resp_dma_addr == 0) {
650 "Unable to map response buffer to physical memory.\n");
654 bp->max_resp_len = max_resp_len;
658 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
660 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
661 RTE_LOG(DEBUG, PMD, "Short command supported\n");
663 rte_free(bp->hwrm_short_cmd_req_addr);
665 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
667 if (bp->hwrm_short_cmd_req_addr == NULL) {
671 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
672 bp->hwrm_short_cmd_req_dma_addr =
673 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
674 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
675 rte_free(bp->hwrm_short_cmd_req_addr);
677 "Unable to map buffer to physical memory.\n");
682 bp->flags |= BNXT_FLAG_SHORT_CMD;
690 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
693 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
694 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
696 if (!(bp->flags & BNXT_FLAG_REGISTERED))
699 HWRM_PREP(req, FUNC_DRV_UNRGTR);
702 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
707 bp->flags &= ~BNXT_FLAG_REGISTERED;
712 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
715 struct hwrm_port_phy_cfg_input req = {0};
716 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
717 uint32_t enables = 0;
719 HWRM_PREP(req, PORT_PHY_CFG);
722 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
723 if (bp->link_info.auto_mode && conf->link_speed) {
724 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
725 RTE_LOG(DEBUG, PMD, "Disabling AutoNeg\n");
728 req.flags = rte_cpu_to_le_32(conf->phy_flags);
729 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
730 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
732 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
733 * any auto mode, even "none".
735 if (!conf->link_speed) {
736 /* No speeds specified. Enable AutoNeg - all speeds */
738 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
740 /* AutoNeg - Advertise speeds specified. */
741 if (conf->auto_link_speed_mask) {
743 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
744 req.auto_link_speed_mask =
745 conf->auto_link_speed_mask;
747 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
750 req.auto_duplex = conf->duplex;
751 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
752 req.auto_pause = conf->auto_pause;
753 req.force_pause = conf->force_pause;
754 /* Set force_pause if there is no auto or if there is a force */
755 if (req.auto_pause && !req.force_pause)
756 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
758 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
760 req.enables = rte_cpu_to_le_32(enables);
763 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
764 RTE_LOG(INFO, PMD, "Force Link Down\n");
767 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
775 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
776 struct bnxt_link_info *link_info)
779 struct hwrm_port_phy_qcfg_input req = {0};
780 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
782 HWRM_PREP(req, PORT_PHY_QCFG);
784 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
788 link_info->phy_link_status = resp->link;
790 (link_info->phy_link_status ==
791 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
792 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
793 link_info->duplex = resp->duplex_cfg;
794 link_info->pause = resp->pause;
795 link_info->auto_pause = resp->auto_pause;
796 link_info->force_pause = resp->force_pause;
797 link_info->auto_mode = resp->auto_mode;
798 link_info->phy_type = resp->phy_type;
799 link_info->media_type = resp->media_type;
801 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
802 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
803 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
804 link_info->phy_ver[0] = resp->phy_maj;
805 link_info->phy_ver[1] = resp->phy_min;
806 link_info->phy_ver[2] = resp->phy_bld;
813 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
816 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
817 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
819 HWRM_PREP(req, QUEUE_QPORTCFG);
821 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
825 #define GET_QUEUE_INFO(x) \
826 bp->cos_queue[x].id = resp->queue_id##x; \
827 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
843 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
844 struct bnxt_ring *ring,
845 uint32_t ring_type, uint32_t map_index,
846 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
849 uint32_t enables = 0;
850 struct hwrm_ring_alloc_input req = {.req_type = 0 };
851 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
853 HWRM_PREP(req, RING_ALLOC);
855 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
856 req.fbo = rte_cpu_to_le_32(0);
857 /* Association of ring index with doorbell index */
858 req.logical_id = rte_cpu_to_le_16(map_index);
859 req.length = rte_cpu_to_le_32(ring->ring_size);
862 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
863 req.queue_id = bp->cos_queue[0].id;
865 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
866 req.ring_type = ring_type;
867 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
868 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
869 if (stats_ctx_id != INVALID_STATS_CTX_ID)
871 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
873 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
874 req.ring_type = ring_type;
876 * TODO: Some HWRM versions crash with
877 * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
879 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
882 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
887 req.enables = rte_cpu_to_le_32(enables);
889 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
891 if (rc || resp->error_code) {
892 if (rc == 0 && resp->error_code)
893 rc = rte_le_to_cpu_16(resp->error_code);
895 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
897 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
900 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
902 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
905 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
907 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
911 RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
917 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
922 int bnxt_hwrm_ring_free(struct bnxt *bp,
923 struct bnxt_ring *ring, uint32_t ring_type)
926 struct hwrm_ring_free_input req = {.req_type = 0 };
927 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
929 HWRM_PREP(req, RING_FREE);
931 req.ring_type = ring_type;
932 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
934 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
936 if (rc || resp->error_code) {
937 if (rc == 0 && resp->error_code)
938 rc = rte_le_to_cpu_16(resp->error_code);
942 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
943 RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
946 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
947 RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
950 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
951 RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
955 RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
963 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
966 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
967 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
969 HWRM_PREP(req, RING_GRP_ALLOC);
971 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
972 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
973 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
974 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
976 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
980 bp->grp_info[idx].fw_grp_id =
981 rte_le_to_cpu_16(resp->ring_group_id);
988 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
991 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
992 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
994 HWRM_PREP(req, RING_GRP_FREE);
996 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
998 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1000 HWRM_CHECK_RESULT();
1003 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1007 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1010 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1011 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1013 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1016 HWRM_PREP(req, STAT_CTX_CLR_STATS);
1018 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1020 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1022 HWRM_CHECK_RESULT();
1028 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1029 unsigned int idx __rte_unused)
1032 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1033 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1035 HWRM_PREP(req, STAT_CTX_ALLOC);
1037 req.update_period_ms = rte_cpu_to_le_32(0);
1039 req.stats_dma_addr =
1040 rte_cpu_to_le_64(cpr->hw_stats_map);
1042 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1044 HWRM_CHECK_RESULT();
1046 cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
1049 bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
1054 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1055 unsigned int idx __rte_unused)
1058 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1059 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1061 HWRM_PREP(req, STAT_CTX_FREE);
1063 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1065 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1067 HWRM_CHECK_RESULT();
1073 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1076 struct hwrm_vnic_alloc_input req = { 0 };
1077 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1079 /* map ring groups to this vnic */
1080 RTE_LOG(DEBUG, PMD, "Alloc VNIC. Start %x, End %x\n",
1081 vnic->start_grp_id, vnic->end_grp_id);
1082 for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
1083 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1084 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1085 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1086 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1087 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1088 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1089 ETHER_CRC_LEN + VLAN_TAG_SIZE;
1090 HWRM_PREP(req, VNIC_ALLOC);
1092 if (vnic->func_default)
1093 req.flags = HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT;
1094 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1096 HWRM_CHECK_RESULT();
1098 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1100 RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1104 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1105 struct bnxt_vnic_info *vnic,
1106 struct bnxt_plcmodes_cfg *pmode)
1109 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1110 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1112 HWRM_PREP(req, VNIC_PLCMODES_QCFG);
1114 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1116 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1118 HWRM_CHECK_RESULT();
1120 pmode->flags = rte_le_to_cpu_32(resp->flags);
1121 /* dflt_vnic bit doesn't exist in the _cfg command */
1122 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1123 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1124 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1125 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1132 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1133 struct bnxt_vnic_info *vnic,
1134 struct bnxt_plcmodes_cfg *pmode)
1137 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1138 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1140 HWRM_PREP(req, VNIC_PLCMODES_CFG);
1142 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1143 req.flags = rte_cpu_to_le_32(pmode->flags);
1144 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1145 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1146 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1147 req.enables = rte_cpu_to_le_32(
1148 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1149 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1150 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1153 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1155 HWRM_CHECK_RESULT();
1161 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1164 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1165 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1166 uint32_t ctx_enable_flag = 0;
1167 struct bnxt_plcmodes_cfg pmodes;
1169 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1170 RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1174 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1178 HWRM_PREP(req, VNIC_CFG);
1180 /* Only RSS support for now TBD: COS & LB */
1182 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP);
1183 if (vnic->lb_rule != 0xffff)
1184 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1185 if (vnic->cos_rule != 0xffff)
1186 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1187 if (vnic->rss_rule != 0xffff) {
1188 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1189 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1191 req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1192 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1193 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1194 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1195 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1196 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1197 req.mru = rte_cpu_to_le_16(vnic->mru);
1198 if (vnic->func_default)
1200 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1201 if (vnic->vlan_strip)
1203 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1206 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1207 if (vnic->roce_dual)
1208 req.flags |= rte_cpu_to_le_32(
1209 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1210 if (vnic->roce_only)
1211 req.flags |= rte_cpu_to_le_32(
1212 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1213 if (vnic->rss_dflt_cr)
1214 req.flags |= rte_cpu_to_le_32(
1215 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1217 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1219 HWRM_CHECK_RESULT();
1222 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1227 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1231 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1232 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1234 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1235 RTE_LOG(DEBUG, PMD, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1238 HWRM_PREP(req, VNIC_QCFG);
1241 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1242 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1243 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1245 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1247 HWRM_CHECK_RESULT();
1249 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1250 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1251 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1252 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1253 vnic->mru = rte_le_to_cpu_16(resp->mru);
1254 vnic->func_default = rte_le_to_cpu_32(
1255 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1256 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1257 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1258 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1259 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1260 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1261 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1262 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1263 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1264 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1265 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1272 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1275 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1276 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1277 bp->hwrm_cmd_resp_addr;
1279 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC);
1281 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1283 HWRM_CHECK_RESULT();
1285 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1287 RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1292 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1295 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1296 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1297 bp->hwrm_cmd_resp_addr;
1299 if (vnic->rss_rule == 0xffff) {
1300 RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1303 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE);
1305 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1307 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1309 HWRM_CHECK_RESULT();
1312 vnic->rss_rule = INVALID_HW_RING_ID;
1317 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1320 struct hwrm_vnic_free_input req = {.req_type = 0 };
1321 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1323 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1324 RTE_LOG(DEBUG, PMD, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1328 HWRM_PREP(req, VNIC_FREE);
1330 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1332 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1334 HWRM_CHECK_RESULT();
1337 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1341 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1342 struct bnxt_vnic_info *vnic)
1345 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1346 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1348 HWRM_PREP(req, VNIC_RSS_CFG);
1350 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1352 req.ring_grp_tbl_addr =
1353 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1354 req.hash_key_tbl_addr =
1355 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1356 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1358 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1360 HWRM_CHECK_RESULT();
1366 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1367 struct bnxt_vnic_info *vnic)
1370 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1371 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1374 HWRM_PREP(req, VNIC_PLCMODES_CFG);
1376 req.flags = rte_cpu_to_le_32(
1377 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1379 req.enables = rte_cpu_to_le_32(
1380 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1382 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1383 size -= RTE_PKTMBUF_HEADROOM;
1385 req.jumbo_thresh = rte_cpu_to_le_16(size);
1386 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1388 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1390 HWRM_CHECK_RESULT();
1396 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1397 struct bnxt_vnic_info *vnic, bool enable)
1400 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1401 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1403 HWRM_PREP(req, VNIC_TPA_CFG);
1406 req.enables = rte_cpu_to_le_32(
1407 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1408 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1409 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1410 req.flags = rte_cpu_to_le_32(
1411 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1412 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1413 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1414 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1415 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1416 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1417 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1418 req.max_agg_segs = rte_cpu_to_le_16(5);
1420 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1421 req.min_agg_len = rte_cpu_to_le_32(512);
1424 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1426 HWRM_CHECK_RESULT();
1432 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1434 struct hwrm_func_cfg_input req = {0};
1435 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1438 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1439 req.enables = rte_cpu_to_le_32(
1440 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1441 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1442 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1444 HWRM_PREP(req, FUNC_CFG);
1446 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1447 HWRM_CHECK_RESULT();
1450 bp->pf.vf_info[vf].random_mac = false;
1455 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1459 struct hwrm_func_qstats_input req = {.req_type = 0};
1460 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1462 HWRM_PREP(req, FUNC_QSTATS);
1464 req.fid = rte_cpu_to_le_16(fid);
1466 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1468 HWRM_CHECK_RESULT();
1471 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1478 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1479 struct rte_eth_stats *stats)
1482 struct hwrm_func_qstats_input req = {.req_type = 0};
1483 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1485 HWRM_PREP(req, FUNC_QSTATS);
1487 req.fid = rte_cpu_to_le_16(fid);
1489 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1491 HWRM_CHECK_RESULT();
1493 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1494 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1495 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1496 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1497 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1498 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1500 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1501 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1502 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1503 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1504 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1505 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1507 stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1508 stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1510 stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1517 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1520 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1521 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1523 HWRM_PREP(req, FUNC_CLR_STATS);
1525 req.fid = rte_cpu_to_le_16(fid);
1527 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1529 HWRM_CHECK_RESULT();
1536 * HWRM utility functions
1539 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1544 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1545 struct bnxt_tx_queue *txq;
1546 struct bnxt_rx_queue *rxq;
1547 struct bnxt_cp_ring_info *cpr;
1549 if (i >= bp->rx_cp_nr_rings) {
1550 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1553 rxq = bp->rx_queues[i];
1557 rc = bnxt_hwrm_stat_clear(bp, cpr);
1564 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1568 struct bnxt_cp_ring_info *cpr;
1570 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1572 if (i >= bp->rx_cp_nr_rings)
1573 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1575 cpr = bp->rx_queues[i]->cp_ring;
1576 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1577 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1578 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1580 * TODO. Need a better way to reset grp_info.stats_ctx
1581 * for Rx rings only. stats_ctx is not saved for Tx
1584 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
1592 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1597 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1598 struct bnxt_tx_queue *txq;
1599 struct bnxt_rx_queue *rxq;
1600 struct bnxt_cp_ring_info *cpr;
1602 if (i >= bp->rx_cp_nr_rings) {
1603 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1606 rxq = bp->rx_queues[i];
1610 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1618 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1623 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1625 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1628 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1636 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1637 unsigned int idx __rte_unused)
1639 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1641 bnxt_hwrm_ring_free(bp, cp_ring,
1642 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1643 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1644 bp->grp_info[idx].cp_fw_ring_id = INVALID_HW_RING_ID;
1645 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1646 sizeof(*cpr->cp_desc_ring));
1647 cpr->cp_raw_cons = 0;
1650 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1655 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1656 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1657 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1658 struct bnxt_ring *ring = txr->tx_ring_struct;
1659 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1660 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1662 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1663 bnxt_hwrm_ring_free(bp, ring,
1664 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1665 ring->fw_ring_id = INVALID_HW_RING_ID;
1666 memset(txr->tx_desc_ring, 0,
1667 txr->tx_ring_struct->ring_size *
1668 sizeof(*txr->tx_desc_ring));
1669 memset(txr->tx_buf_ring, 0,
1670 txr->tx_ring_struct->ring_size *
1671 sizeof(*txr->tx_buf_ring));
1675 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1676 bnxt_free_cp_ring(bp, cpr, idx);
1677 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1681 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1682 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1683 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1684 struct bnxt_ring *ring = rxr->rx_ring_struct;
1685 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1686 unsigned int idx = i + 1;
1688 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1689 bnxt_hwrm_ring_free(bp, ring,
1690 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1691 ring->fw_ring_id = INVALID_HW_RING_ID;
1692 bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1693 memset(rxr->rx_desc_ring, 0,
1694 rxr->rx_ring_struct->ring_size *
1695 sizeof(*rxr->rx_desc_ring));
1696 memset(rxr->rx_buf_ring, 0,
1697 rxr->rx_ring_struct->ring_size *
1698 sizeof(*rxr->rx_buf_ring));
1700 memset(rxr->ag_buf_ring, 0,
1701 rxr->ag_ring_struct->ring_size *
1702 sizeof(*rxr->ag_buf_ring));
1705 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1706 bnxt_free_cp_ring(bp, cpr, idx);
1707 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1708 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1712 /* Default completion ring */
1714 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1716 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1717 bnxt_free_cp_ring(bp, cpr, 0);
1718 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1725 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1730 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1731 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1738 void bnxt_free_hwrm_resources(struct bnxt *bp)
1740 /* Release memzone */
1741 rte_free(bp->hwrm_cmd_resp_addr);
1742 rte_free(bp->hwrm_short_cmd_req_addr);
1743 bp->hwrm_cmd_resp_addr = NULL;
1744 bp->hwrm_short_cmd_req_addr = NULL;
1745 bp->hwrm_cmd_resp_dma_addr = 0;
1746 bp->hwrm_short_cmd_req_dma_addr = 0;
1749 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1751 struct rte_pci_device *pdev = bp->pdev;
1752 char type[RTE_MEMZONE_NAMESIZE];
1754 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1755 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1756 bp->max_resp_len = HWRM_MAX_RESP_LEN;
1757 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1758 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1759 if (bp->hwrm_cmd_resp_addr == NULL)
1761 bp->hwrm_cmd_resp_dma_addr =
1762 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1763 if (bp->hwrm_cmd_resp_dma_addr == 0) {
1765 "unable to map response address to physical memory\n");
1768 rte_spinlock_init(&bp->hwrm_lock);
1773 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1775 struct bnxt_filter_info *filter;
1778 STAILQ_FOREACH(filter, &vnic->filter, next) {
1779 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1780 rc = bnxt_hwrm_clear_em_filter(bp, filter);
1781 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1782 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1784 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1792 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1794 struct bnxt_filter_info *filter;
1795 struct rte_flow *flow;
1798 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
1799 filter = flow->filter;
1800 RTE_LOG(ERR, PMD, "filter type %d\n", filter->filter_type);
1801 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1802 rc = bnxt_hwrm_clear_em_filter(bp, filter);
1803 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1804 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1806 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1808 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
1816 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1818 struct bnxt_filter_info *filter;
1821 STAILQ_FOREACH(filter, &vnic->filter, next) {
1822 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1823 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
1825 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1826 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
1829 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
1837 void bnxt_free_tunnel_ports(struct bnxt *bp)
1839 if (bp->vxlan_port_cnt)
1840 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1841 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1843 if (bp->geneve_port_cnt)
1844 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1845 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1846 bp->geneve_port = 0;
1849 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1853 if (bp->vnic_info == NULL)
1857 * Cleanup VNICs in reverse order, to make sure the L2 filter
1858 * from vnic0 is last to be cleaned up.
1860 for (i = bp->nr_vnics - 1; i >= 0; i--) {
1861 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1863 bnxt_clear_hwrm_vnic_flows(bp, vnic);
1865 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1867 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1869 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1871 bnxt_hwrm_vnic_free(bp, vnic);
1873 /* Ring resources */
1874 bnxt_free_all_hwrm_rings(bp);
1875 bnxt_free_all_hwrm_ring_grps(bp);
1876 bnxt_free_all_hwrm_stat_ctxs(bp);
1877 bnxt_free_tunnel_ports(bp);
1880 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1882 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1884 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1885 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1887 switch (conf_link_speed) {
1888 case ETH_LINK_SPEED_10M_HD:
1889 case ETH_LINK_SPEED_100M_HD:
1890 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1892 return hw_link_duplex;
1895 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
1897 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
1900 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1902 uint16_t eth_link_speed = 0;
1904 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1905 return ETH_LINK_SPEED_AUTONEG;
1907 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1908 case ETH_LINK_SPEED_100M:
1909 case ETH_LINK_SPEED_100M_HD:
1911 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1913 case ETH_LINK_SPEED_1G:
1915 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1917 case ETH_LINK_SPEED_2_5G:
1919 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1921 case ETH_LINK_SPEED_10G:
1923 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
1925 case ETH_LINK_SPEED_20G:
1927 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
1929 case ETH_LINK_SPEED_25G:
1931 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
1933 case ETH_LINK_SPEED_40G:
1935 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
1937 case ETH_LINK_SPEED_50G:
1939 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
1943 "Unsupported link speed %d; default to AUTO\n",
1947 return eth_link_speed;
1950 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1951 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1952 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1953 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1955 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
1959 if (link_speed == ETH_LINK_SPEED_AUTONEG)
1962 if (link_speed & ETH_LINK_SPEED_FIXED) {
1963 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1965 if (one_speed & (one_speed - 1)) {
1967 "Invalid advertised speeds (%u) for port %u\n",
1968 link_speed, port_id);
1971 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1973 "Unsupported advertised speed (%u) for port %u\n",
1974 link_speed, port_id);
1978 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1980 "Unsupported advertised speeds (%u) for port %u\n",
1981 link_speed, port_id);
1989 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
1993 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
1994 if (bp->link_info.support_speeds)
1995 return bp->link_info.support_speeds;
1996 link_speed = BNXT_SUPPORTED_SPEEDS;
1999 if (link_speed & ETH_LINK_SPEED_100M)
2000 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2001 if (link_speed & ETH_LINK_SPEED_100M_HD)
2002 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2003 if (link_speed & ETH_LINK_SPEED_1G)
2004 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2005 if (link_speed & ETH_LINK_SPEED_2_5G)
2006 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2007 if (link_speed & ETH_LINK_SPEED_10G)
2008 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2009 if (link_speed & ETH_LINK_SPEED_20G)
2010 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2011 if (link_speed & ETH_LINK_SPEED_25G)
2012 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2013 if (link_speed & ETH_LINK_SPEED_40G)
2014 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2015 if (link_speed & ETH_LINK_SPEED_50G)
2016 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2020 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2022 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2024 switch (hw_link_speed) {
2025 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2026 eth_link_speed = ETH_SPEED_NUM_100M;
2028 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2029 eth_link_speed = ETH_SPEED_NUM_1G;
2031 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2032 eth_link_speed = ETH_SPEED_NUM_2_5G;
2034 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2035 eth_link_speed = ETH_SPEED_NUM_10G;
2037 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2038 eth_link_speed = ETH_SPEED_NUM_20G;
2040 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2041 eth_link_speed = ETH_SPEED_NUM_25G;
2043 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2044 eth_link_speed = ETH_SPEED_NUM_40G;
2046 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2047 eth_link_speed = ETH_SPEED_NUM_50G;
2049 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2051 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
2055 return eth_link_speed;
2058 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2060 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2062 switch (hw_link_duplex) {
2063 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2064 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2065 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2067 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2068 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2071 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
2075 return eth_link_duplex;
2078 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2081 struct bnxt_link_info *link_info = &bp->link_info;
2083 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2086 "Get link config failed with rc %d\n", rc);
2089 if (link_info->link_speed)
2091 bnxt_parse_hw_link_speed(link_info->link_speed);
2093 link->link_speed = ETH_SPEED_NUM_NONE;
2094 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2095 link->link_status = link_info->link_up;
2096 link->link_autoneg = link_info->auto_mode ==
2097 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2098 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2103 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2106 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2107 struct bnxt_link_info link_req;
2108 uint16_t speed, autoneg;
2110 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp))
2113 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2114 bp->eth_dev->data->port_id);
2118 memset(&link_req, 0, sizeof(link_req));
2119 link_req.link_up = link_up;
2123 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2124 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2125 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2127 link_req.phy_flags |=
2128 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2129 link_req.auto_link_speed_mask =
2130 bnxt_parse_eth_link_speed_mask(bp,
2131 dev_conf->link_speeds);
2133 if (bp->link_info.phy_type ==
2134 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2135 bp->link_info.phy_type ==
2136 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2137 bp->link_info.media_type ==
2138 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2139 RTE_LOG(ERR, PMD, "10GBase-T devices must autoneg\n");
2143 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2144 link_req.link_speed = speed;
2146 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2147 link_req.auto_pause = bp->link_info.auto_pause;
2148 link_req.force_pause = bp->link_info.force_pause;
2151 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2154 "Set link config failed with rc %d\n", rc);
2162 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2164 struct hwrm_func_qcfg_input req = {0};
2165 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2168 HWRM_PREP(req, FUNC_QCFG);
2169 req.fid = rte_cpu_to_le_16(0xffff);
2171 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2173 HWRM_CHECK_RESULT();
2175 /* Hard Coded.. 0xfff VLAN ID mask */
2176 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2178 switch (resp->port_partition_type) {
2179 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2180 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2181 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2182 bp->port_partition_type = resp->port_partition_type;
2185 bp->port_partition_type = 0;
2194 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2195 struct hwrm_func_qcaps_output *qcaps)
2197 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2198 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2199 sizeof(qcaps->mac_address));
2200 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2201 qcaps->max_rx_rings = fcfg->num_rx_rings;
2202 qcaps->max_tx_rings = fcfg->num_tx_rings;
2203 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2204 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2206 qcaps->first_vf_id = 0;
2207 qcaps->max_vnics = fcfg->num_vnics;
2208 qcaps->max_decap_records = 0;
2209 qcaps->max_encap_records = 0;
2210 qcaps->max_tx_wm_flows = 0;
2211 qcaps->max_tx_em_flows = 0;
2212 qcaps->max_rx_wm_flows = 0;
2213 qcaps->max_rx_em_flows = 0;
2214 qcaps->max_flow_id = 0;
2215 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2216 qcaps->max_sp_tx_rings = 0;
2217 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2220 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2222 struct hwrm_func_cfg_input req = {0};
2223 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2226 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2227 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2228 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2229 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2230 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2231 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2232 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2233 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2234 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2235 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2236 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2237 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2238 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2239 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2240 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2241 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2242 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2243 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2244 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2245 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2246 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2247 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2248 req.fid = rte_cpu_to_le_16(0xffff);
2250 HWRM_PREP(req, FUNC_CFG);
2252 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2254 HWRM_CHECK_RESULT();
2260 static void populate_vf_func_cfg_req(struct bnxt *bp,
2261 struct hwrm_func_cfg_input *req,
2264 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2265 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2266 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2267 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2268 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2269 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2270 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2271 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2272 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2273 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2275 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2276 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2277 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2278 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2279 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2281 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2282 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2284 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2285 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2286 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2287 /* TODO: For now, do not support VMDq/RFS on VFs. */
2288 req->num_vnics = rte_cpu_to_le_16(1);
2289 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2293 static void add_random_mac_if_needed(struct bnxt *bp,
2294 struct hwrm_func_cfg_input *cfg_req,
2297 struct ether_addr mac;
2299 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2302 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2304 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2305 eth_random_addr(cfg_req->dflt_mac_addr);
2306 bp->pf.vf_info[vf].random_mac = true;
2308 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2312 static void reserve_resources_from_vf(struct bnxt *bp,
2313 struct hwrm_func_cfg_input *cfg_req,
2316 struct hwrm_func_qcaps_input req = {0};
2317 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2320 /* Get the actual allocated values now */
2321 HWRM_PREP(req, FUNC_QCAPS);
2322 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2323 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2326 RTE_LOG(ERR, PMD, "hwrm_func_qcaps failed rc:%d\n", rc);
2327 copy_func_cfg_to_qcaps(cfg_req, resp);
2328 } else if (resp->error_code) {
2329 rc = rte_le_to_cpu_16(resp->error_code);
2330 RTE_LOG(ERR, PMD, "hwrm_func_qcaps error %d\n", rc);
2331 copy_func_cfg_to_qcaps(cfg_req, resp);
2334 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2335 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2336 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2337 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2338 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2339 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2341 * TODO: While not supporting VMDq with VFs, max_vnics is always
2342 * forced to 1 in this case
2344 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2345 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2350 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2352 struct hwrm_func_qcfg_input req = {0};
2353 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2356 /* Check for zero MAC address */
2357 HWRM_PREP(req, FUNC_QCFG);
2358 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2359 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2361 RTE_LOG(ERR, PMD, "hwrm_func_qcfg failed rc:%d\n", rc);
2363 } else if (resp->error_code) {
2364 rc = rte_le_to_cpu_16(resp->error_code);
2365 RTE_LOG(ERR, PMD, "hwrm_func_qcfg error %d\n", rc);
2368 rc = rte_le_to_cpu_16(resp->vlan);
2375 static int update_pf_resource_max(struct bnxt *bp)
2377 struct hwrm_func_qcfg_input req = {0};
2378 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2381 /* And copy the allocated numbers into the pf struct */
2382 HWRM_PREP(req, FUNC_QCFG);
2383 req.fid = rte_cpu_to_le_16(0xffff);
2384 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2385 HWRM_CHECK_RESULT();
2387 /* Only TX ring value reflects actual allocation? TODO */
2388 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2389 bp->pf.evb_mode = resp->evb_mode;
2396 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2401 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2405 rc = bnxt_hwrm_func_qcaps(bp);
2409 bp->pf.func_cfg_flags &=
2410 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2411 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2412 bp->pf.func_cfg_flags |=
2413 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2414 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2418 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2420 struct hwrm_func_cfg_input req = {0};
2421 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2428 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2432 rc = bnxt_hwrm_func_qcaps(bp);
2437 bp->pf.active_vfs = num_vfs;
2440 * First, configure the PF to only use one TX ring. This ensures that
2441 * there are enough rings for all VFs.
2443 * If we don't do this, when we call func_alloc() later, we will lock
2444 * extra rings to the PF that won't be available during func_cfg() of
2447 * This has been fixed with firmware versions above 20.6.54
2449 bp->pf.func_cfg_flags &=
2450 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2451 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2452 bp->pf.func_cfg_flags |=
2453 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2454 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2459 * Now, create and register a buffer to hold forwarded VF requests
2461 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2462 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2463 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2464 if (bp->pf.vf_req_buf == NULL) {
2468 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2469 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2470 for (i = 0; i < num_vfs; i++)
2471 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2472 (i * HWRM_MAX_REQ_LEN);
2474 rc = bnxt_hwrm_func_buf_rgtr(bp);
2478 populate_vf_func_cfg_req(bp, &req, num_vfs);
2480 bp->pf.active_vfs = 0;
2481 for (i = 0; i < num_vfs; i++) {
2482 add_random_mac_if_needed(bp, &req, i);
2484 HWRM_PREP(req, FUNC_CFG);
2485 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2486 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2487 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2489 /* Clear enable flag for next pass */
2490 req.enables &= ~rte_cpu_to_le_32(
2491 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2493 if (rc || resp->error_code) {
2495 "Failed to initizlie VF %d\n", i);
2497 "Not all VFs available. (%d, %d)\n",
2498 rc, resp->error_code);
2505 reserve_resources_from_vf(bp, &req, i);
2506 bp->pf.active_vfs++;
2507 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2511 * Now configure the PF to use "the rest" of the resources
2512 * We're using STD_TX_RING_MODE here though which will limit the TX
2513 * rings. This will allow QoS to function properly. Not setting this
2514 * will cause PF rings to break bandwidth settings.
2516 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2520 rc = update_pf_resource_max(bp);
2527 bnxt_hwrm_func_buf_unrgtr(bp);
2531 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2533 struct hwrm_func_cfg_input req = {0};
2534 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2537 HWRM_PREP(req, FUNC_CFG);
2539 req.fid = rte_cpu_to_le_16(0xffff);
2540 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2541 req.evb_mode = bp->pf.evb_mode;
2543 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2544 HWRM_CHECK_RESULT();
2550 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2551 uint8_t tunnel_type)
2553 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2554 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2557 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC);
2558 req.tunnel_type = tunnel_type;
2559 req.tunnel_dst_port_val = port;
2560 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2561 HWRM_CHECK_RESULT();
2563 switch (tunnel_type) {
2564 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2565 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2566 bp->vxlan_port = port;
2568 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2569 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2570 bp->geneve_port = port;
2581 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2582 uint8_t tunnel_type)
2584 struct hwrm_tunnel_dst_port_free_input req = {0};
2585 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2588 HWRM_PREP(req, TUNNEL_DST_PORT_FREE);
2590 req.tunnel_type = tunnel_type;
2591 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2592 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2594 HWRM_CHECK_RESULT();
2600 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2603 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2604 struct hwrm_func_cfg_input req = {0};
2607 HWRM_PREP(req, FUNC_CFG);
2609 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2610 req.flags = rte_cpu_to_le_32(flags);
2611 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2613 HWRM_CHECK_RESULT();
2619 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2621 uint32_t *flag = flagp;
2623 vnic->flags = *flag;
2626 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2628 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2631 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2634 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2635 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2637 HWRM_PREP(req, FUNC_BUF_RGTR);
2639 req.req_buf_num_pages = rte_cpu_to_le_16(1);
2640 req.req_buf_page_size = rte_cpu_to_le_16(
2641 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2642 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2643 req.req_buf_page_addr[0] =
2644 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
2645 if (req.req_buf_page_addr[0] == 0) {
2647 "unable to map buffer address to physical memory\n");
2651 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2653 HWRM_CHECK_RESULT();
2659 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2662 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2663 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2665 HWRM_PREP(req, FUNC_BUF_UNRGTR);
2667 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2669 HWRM_CHECK_RESULT();
2675 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2677 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2678 struct hwrm_func_cfg_input req = {0};
2681 HWRM_PREP(req, FUNC_CFG);
2683 req.fid = rte_cpu_to_le_16(0xffff);
2684 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2685 req.enables = rte_cpu_to_le_32(
2686 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2687 req.async_event_cr = rte_cpu_to_le_16(
2688 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2689 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2691 HWRM_CHECK_RESULT();
2697 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2699 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2700 struct hwrm_func_vf_cfg_input req = {0};
2703 HWRM_PREP(req, FUNC_VF_CFG);
2705 req.enables = rte_cpu_to_le_32(
2706 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2707 req.async_event_cr = rte_cpu_to_le_16(
2708 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2709 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2711 HWRM_CHECK_RESULT();
2717 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2719 struct hwrm_func_cfg_input req = {0};
2720 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2721 uint16_t dflt_vlan, fid;
2722 uint32_t func_cfg_flags;
2725 HWRM_PREP(req, FUNC_CFG);
2728 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2729 fid = bp->pf.vf_info[vf].fid;
2730 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2732 fid = rte_cpu_to_le_16(0xffff);
2733 func_cfg_flags = bp->pf.func_cfg_flags;
2734 dflt_vlan = bp->vlan;
2737 req.flags = rte_cpu_to_le_32(func_cfg_flags);
2738 req.fid = rte_cpu_to_le_16(fid);
2739 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2740 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2742 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2744 HWRM_CHECK_RESULT();
2750 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2751 uint16_t max_bw, uint16_t enables)
2753 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2754 struct hwrm_func_cfg_input req = {0};
2757 HWRM_PREP(req, FUNC_CFG);
2759 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2760 req.enables |= rte_cpu_to_le_32(enables);
2761 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2762 req.max_bw = rte_cpu_to_le_32(max_bw);
2763 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2765 HWRM_CHECK_RESULT();
2771 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2773 struct hwrm_func_cfg_input req = {0};
2774 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2777 HWRM_PREP(req, FUNC_CFG);
2779 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2780 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2781 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2782 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2784 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2786 HWRM_CHECK_RESULT();
2792 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2793 void *encaped, size_t ec_size)
2796 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2797 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2799 if (ec_size > sizeof(req.encap_request))
2802 HWRM_PREP(req, REJECT_FWD_RESP);
2804 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2805 memcpy(req.encap_request, encaped, ec_size);
2807 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2809 HWRM_CHECK_RESULT();
2815 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2816 struct ether_addr *mac)
2818 struct hwrm_func_qcfg_input req = {0};
2819 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2822 HWRM_PREP(req, FUNC_QCFG);
2824 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2825 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2827 HWRM_CHECK_RESULT();
2829 memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2836 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2837 void *encaped, size_t ec_size)
2840 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2841 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2843 if (ec_size > sizeof(req.encap_request))
2846 HWRM_PREP(req, EXEC_FWD_RESP);
2848 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2849 memcpy(req.encap_request, encaped, ec_size);
2851 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2853 HWRM_CHECK_RESULT();
2859 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2860 struct rte_eth_stats *stats, uint8_t rx)
2863 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2864 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2866 HWRM_PREP(req, STAT_CTX_QUERY);
2868 req.stat_ctx_id = rte_cpu_to_le_32(cid);
2870 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2872 HWRM_CHECK_RESULT();
2875 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2876 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2877 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2878 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2879 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2880 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2881 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2882 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2884 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2885 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2886 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2887 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2888 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2889 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2890 stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
2899 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2901 struct hwrm_port_qstats_input req = {0};
2902 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2903 struct bnxt_pf_info *pf = &bp->pf;
2906 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2909 HWRM_PREP(req, PORT_QSTATS);
2911 req.port_id = rte_cpu_to_le_16(pf->port_id);
2912 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
2913 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
2914 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2916 HWRM_CHECK_RESULT();
2922 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
2924 struct hwrm_port_clr_stats_input req = {0};
2925 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2926 struct bnxt_pf_info *pf = &bp->pf;
2929 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2932 HWRM_PREP(req, PORT_CLR_STATS);
2934 req.port_id = rte_cpu_to_le_16(pf->port_id);
2935 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2937 HWRM_CHECK_RESULT();
2943 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
2945 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2946 struct hwrm_port_led_qcaps_input req = {0};
2952 HWRM_PREP(req, PORT_LED_QCAPS);
2953 req.port_id = bp->pf.port_id;
2954 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2956 HWRM_CHECK_RESULT();
2958 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
2961 bp->num_leds = resp->num_leds;
2962 memcpy(bp->leds, &resp->led0_id,
2963 sizeof(bp->leds[0]) * bp->num_leds);
2964 for (i = 0; i < bp->num_leds; i++) {
2965 struct bnxt_led_info *led = &bp->leds[i];
2967 uint16_t caps = led->led_state_caps;
2969 if (!led->led_group_id ||
2970 !BNXT_LED_ALT_BLINK_CAP(caps)) {
2982 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
2984 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2985 struct hwrm_port_led_cfg_input req = {0};
2986 struct bnxt_led_cfg *led_cfg;
2987 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
2988 uint16_t duration = 0;
2991 if (!bp->num_leds || BNXT_VF(bp))
2994 HWRM_PREP(req, PORT_LED_CFG);
2997 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
2998 duration = rte_cpu_to_le_16(500);
3000 req.port_id = bp->pf.port_id;
3001 req.num_leds = bp->num_leds;
3002 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3003 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3004 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3005 led_cfg->led_id = bp->leds[i].led_id;
3006 led_cfg->led_state = led_state;
3007 led_cfg->led_blink_on = duration;
3008 led_cfg->led_blink_off = duration;
3009 led_cfg->led_group_id = bp->leds[i].led_group_id;
3012 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3014 HWRM_CHECK_RESULT();
3020 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3024 struct hwrm_nvm_get_dir_info_input req = {0};
3025 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3027 HWRM_PREP(req, NVM_GET_DIR_INFO);
3029 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3031 HWRM_CHECK_RESULT();
3035 *entries = rte_le_to_cpu_32(resp->entries);
3036 *length = rte_le_to_cpu_32(resp->entry_length);
3041 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3044 uint32_t dir_entries;
3045 uint32_t entry_length;
3048 rte_iova_t dma_handle;
3049 struct hwrm_nvm_get_dir_entries_input req = {0};
3050 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3052 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3056 *data++ = dir_entries;
3057 *data++ = entry_length;
3059 memset(data, 0xff, len);
3061 buflen = dir_entries * entry_length;
3062 buf = rte_malloc("nvm_dir", buflen, 0);
3063 rte_mem_lock_page(buf);
3066 dma_handle = rte_mem_virt2iova(buf);
3067 if (dma_handle == 0) {
3069 "unable to map response address to physical memory\n");
3072 HWRM_PREP(req, NVM_GET_DIR_ENTRIES);
3073 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3074 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3076 HWRM_CHECK_RESULT();
3080 memcpy(data, buf, len > buflen ? buflen : len);
3087 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3088 uint32_t offset, uint32_t length,
3093 rte_iova_t dma_handle;
3094 struct hwrm_nvm_read_input req = {0};
3095 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3097 buf = rte_malloc("nvm_item", length, 0);
3098 rte_mem_lock_page(buf);
3102 dma_handle = rte_mem_virt2iova(buf);
3103 if (dma_handle == 0) {
3105 "unable to map response address to physical memory\n");
3108 HWRM_PREP(req, NVM_READ);
3109 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3110 req.dir_idx = rte_cpu_to_le_16(index);
3111 req.offset = rte_cpu_to_le_32(offset);
3112 req.len = rte_cpu_to_le_32(length);
3113 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3114 HWRM_CHECK_RESULT();
3117 memcpy(data, buf, length);
3123 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3126 struct hwrm_nvm_erase_dir_entry_input req = {0};
3127 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3129 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY);
3130 req.dir_idx = rte_cpu_to_le_16(index);
3131 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3132 HWRM_CHECK_RESULT();
3139 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3140 uint16_t dir_ordinal, uint16_t dir_ext,
3141 uint16_t dir_attr, const uint8_t *data,
3145 struct hwrm_nvm_write_input req = {0};
3146 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3147 rte_iova_t dma_handle;
3150 HWRM_PREP(req, NVM_WRITE);
3152 req.dir_type = rte_cpu_to_le_16(dir_type);
3153 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3154 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3155 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3156 req.dir_data_length = rte_cpu_to_le_32(data_len);
3158 buf = rte_malloc("nvm_write", data_len, 0);
3159 rte_mem_lock_page(buf);
3163 dma_handle = rte_mem_virt2iova(buf);
3164 if (dma_handle == 0) {
3166 "unable to map response address to physical memory\n");
3169 memcpy(buf, data, data_len);
3170 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3172 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3174 HWRM_CHECK_RESULT();
3182 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3184 uint32_t *count = cbdata;
3186 *count = *count + 1;
3189 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3190 struct bnxt_vnic_info *vnic __rte_unused)
3195 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3199 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3200 &count, bnxt_vnic_count_hwrm_stub);
3205 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3208 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3209 struct hwrm_func_vf_vnic_ids_query_output *resp =
3210 bp->hwrm_cmd_resp_addr;
3213 /* First query all VNIC ids */
3214 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY);
3216 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3217 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3218 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3220 if (req.vnic_id_tbl_addr == 0) {
3223 "unable to map VNIC ID table address to physical memory\n");
3226 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3229 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3231 } else if (resp->error_code) {
3232 rc = rte_le_to_cpu_16(resp->error_code);
3234 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query error %d\n", rc);
3237 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3245 * This function queries the VNIC IDs for a specified VF. It then calls
3246 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3247 * Then it calls the hwrm_cb function to program this new vnic configuration.
3249 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3250 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3251 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3253 struct bnxt_vnic_info vnic;
3255 int i, num_vnic_ids;
3260 /* First query all VNIC ids */
3261 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3262 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3263 RTE_CACHE_LINE_SIZE);
3264 if (vnic_ids == NULL) {
3268 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3269 rte_mem_lock_page(((char *)vnic_ids) + sz);
3271 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3273 if (num_vnic_ids < 0)
3274 return num_vnic_ids;
3276 /* Retrieve VNIC, update bd_stall then update */
3278 for (i = 0; i < num_vnic_ids; i++) {
3279 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3280 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3281 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3284 if (vnic.mru <= 4) /* Indicates unallocated */
3287 vnic_cb(&vnic, cbdata);
3289 rc = hwrm_cb(bp, &vnic);
3299 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3302 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3303 struct hwrm_func_cfg_input req = {0};
3306 HWRM_PREP(req, FUNC_CFG);
3308 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3309 req.enables |= rte_cpu_to_le_32(
3310 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3311 req.vlan_antispoof_mode = on ?
3312 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3313 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3314 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3316 HWRM_CHECK_RESULT();
3322 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3324 struct bnxt_vnic_info vnic;
3327 int num_vnic_ids, i;
3331 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3332 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3333 RTE_CACHE_LINE_SIZE);
3334 if (vnic_ids == NULL) {
3339 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3340 rte_mem_lock_page(((char *)vnic_ids) + sz);
3342 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3348 * Loop through to find the default VNIC ID.
3349 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3350 * by sending the hwrm_func_qcfg command to the firmware.
3352 for (i = 0; i < num_vnic_ids; i++) {
3353 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3354 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3355 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3356 bp->pf.first_vf_id + vf);
3359 if (vnic.func_default) {
3361 return vnic.fw_vnic_id;
3364 /* Could not find a default VNIC. */
3365 RTE_LOG(ERR, PMD, "No default VNIC\n");
3371 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3373 struct bnxt_filter_info *filter)
3376 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3377 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3378 uint32_t enables = 0;
3380 if (filter->fw_em_filter_id != UINT64_MAX)
3381 bnxt_hwrm_clear_em_filter(bp, filter);
3383 HWRM_PREP(req, CFA_EM_FLOW_ALLOC);
3385 req.flags = rte_cpu_to_le_32(filter->flags);
3387 enables = filter->enables |
3388 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3389 req.dst_id = rte_cpu_to_le_16(dst_id);
3391 if (filter->ip_addr_type) {
3392 req.ip_addr_type = filter->ip_addr_type;
3393 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3396 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3397 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3399 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3400 memcpy(req.src_macaddr, filter->src_macaddr,
3403 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3404 memcpy(req.dst_macaddr, filter->dst_macaddr,
3407 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3408 req.ovlan_vid = filter->l2_ovlan;
3410 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3411 req.ivlan_vid = filter->l2_ivlan;
3413 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3414 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3416 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3417 req.ip_protocol = filter->ip_protocol;
3419 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3420 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3422 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3423 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3425 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3426 req.src_port = rte_cpu_to_be_16(filter->src_port);
3428 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3429 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3431 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3432 req.mirror_vnic_id = filter->mirror_vnic_id;
3434 req.enables = rte_cpu_to_le_32(enables);
3436 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3438 HWRM_CHECK_RESULT();
3440 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3446 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3449 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3450 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3452 if (filter->fw_em_filter_id == UINT64_MAX)
3455 RTE_LOG(ERR, PMD, "Clear EM filter\n");
3456 HWRM_PREP(req, CFA_EM_FLOW_FREE);
3458 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3460 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3462 HWRM_CHECK_RESULT();
3465 filter->fw_em_filter_id = -1;
3466 filter->fw_l2_filter_id = -1;
3471 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3473 struct bnxt_filter_info *filter)
3476 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3477 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3478 bp->hwrm_cmd_resp_addr;
3479 uint32_t enables = 0;
3481 if (filter->fw_ntuple_filter_id != UINT64_MAX)
3482 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3484 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC);
3486 req.flags = rte_cpu_to_le_32(filter->flags);
3488 enables = filter->enables |
3489 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3490 req.dst_id = rte_cpu_to_le_16(dst_id);
3493 if (filter->ip_addr_type) {
3494 req.ip_addr_type = filter->ip_addr_type;
3496 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3499 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3500 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3502 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3503 memcpy(req.src_macaddr, filter->src_macaddr,
3506 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3507 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3510 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3511 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3513 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3514 req.ip_protocol = filter->ip_protocol;
3516 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3517 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3519 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3520 req.src_ipaddr_mask[0] =
3521 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3523 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3524 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3526 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3527 req.dst_ipaddr_mask[0] =
3528 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3530 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3531 req.src_port = rte_cpu_to_le_16(filter->src_port);
3533 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3534 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3536 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3537 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3539 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3540 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3542 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3543 req.mirror_vnic_id = filter->mirror_vnic_id;
3545 req.enables = rte_cpu_to_le_32(enables);
3547 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3549 HWRM_CHECK_RESULT();
3551 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
3557 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
3558 struct bnxt_filter_info *filter)
3561 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
3562 struct hwrm_cfa_ntuple_filter_free_output *resp =
3563 bp->hwrm_cmd_resp_addr;
3565 if (filter->fw_ntuple_filter_id == UINT64_MAX)
3568 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE);
3570 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
3572 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3574 HWRM_CHECK_RESULT();
3577 filter->fw_ntuple_filter_id = -1;
3578 filter->fw_l2_filter_id = -1;