1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2021 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
30 #define HWRM_VERSION_1_10_2_13 0x10a020d
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(int) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
67 if (rmem->nr_pages == 0)
70 if (rmem->nr_pages > 1) {
72 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
74 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
78 static struct bnxt_cp_ring_info*
79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
81 struct bnxt_cp_ring_info *cp_ring = NULL;
85 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
86 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
88 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
89 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
91 if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
92 rte_cpu_to_le_16(rid)) {
97 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
98 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
99 struct bnxt_tx_queue *txq = bp->tx_queues[i];
101 if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
102 rte_cpu_to_le_16(rid)) {
113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
114 * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
115 * before timeout, we force the done bit for the cleanup to proceed.
116 * Also if cpr is null, do nothing.. The HWRM command is not for a
117 * Tx/Rx/AGG ring cleanup.
120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
121 bool tx, bool rx, bool timeout)
127 done = bnxt_flush_tx_cmp(cpr);
130 done = bnxt_flush_rx_cmp(cpr);
133 PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
136 /* We are about to timeout and still haven't seen the
137 * HWRM done for the Ring free. Force the cleanup.
139 if (!done && timeout) {
141 PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
145 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
146 * Otherwise the cpr would have been valid. So do nothing.
155 * HWRM Functions (sent to HWRM)
156 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
157 * HWRM command times out, or a negative error code if the HWRM
158 * command was failed by the FW.
161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
162 uint32_t msg_len, bool use_kong_mb)
165 struct input *req = msg;
166 struct output *resp = bp->hwrm_cmd_resp_addr;
167 uint32_t *data = msg;
170 uint16_t max_req_len = bp->max_req_len;
171 struct hwrm_short_input short_input = { 0 };
172 uint16_t bar_offset = use_kong_mb ?
173 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
174 uint16_t mb_trigger_offset = use_kong_mb ?
175 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
176 struct bnxt_cp_ring_info *cpr = NULL;
181 /* Do not send HWRM commands to firmware in error state */
182 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
185 timeout = bp->hwrm_cmd_timeout;
187 /* Update the message length for backing store config for new FW. */
188 if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
189 rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
190 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
192 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
193 msg_len > bp->max_req_len) {
194 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
196 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
197 memcpy(short_cmd_req, req, msg_len);
199 short_input.req_type = rte_cpu_to_le_16(req->req_type);
200 short_input.signature = rte_cpu_to_le_16(
201 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
202 short_input.size = rte_cpu_to_le_16(msg_len);
203 short_input.req_addr =
204 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
206 data = (uint32_t *)&short_input;
207 msg_len = sizeof(short_input);
209 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
212 /* Write request msg to hwrm channel */
213 for (i = 0; i < msg_len; i += 4) {
214 bar = (uint8_t *)bp->bar0 + bar_offset + i;
215 rte_write32(*data, bar);
219 /* Zero the rest of the request space */
220 for (; i < max_req_len; i += 4) {
221 bar = (uint8_t *)bp->bar0 + bar_offset + i;
225 /* Ring channel doorbell */
226 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
229 * Make sure the channel doorbell ring command complete before
230 * reading the response to avoid getting stale or invalid
235 /* Check ring flush is done.
236 * This is valid only for Tx and Rx rings (including AGG rings).
237 * The Tx and Rx rings should be freed once the HW confirms all
238 * the internal buffers and BDs associated with the rings are
239 * consumed and the corresponding DMA is handled.
241 if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
242 /* Check if the TxCQ matches. If that fails check if RxCQ
243 * matches. And if neither match, is_rx = false, is_tx = false.
245 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
246 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
248 /* Not a TxCQ. Check if the RxCQ matches. */
250 bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
251 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
259 /* Poll for the valid bit */
260 for (i = 0; i < timeout; i++) {
263 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
265 /* Sanity check on the resp->resp_len */
267 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
268 /* Last byte of resp contains the valid key */
269 valid = (uint8_t *)resp + resp->resp_len - 1;
270 if (*valid == HWRM_RESP_VALID_KEY && done)
277 /* Suppress VER_GET timeout messages during reset recovery */
278 if (bp->flags & BNXT_FLAG_FW_RESET &&
279 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
283 "Error(timeout) sending msg 0x%04x, seq_id %d\n",
284 req->req_type, req->seq_id);
291 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
292 * spinlock, and does initial processing.
294 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
295 * releases the spinlock only if it returns. If the regular int return codes
296 * are not used by the function, HWRM_CHECK_RESULT() should not be used
297 * directly, rather it should be copied and modified to suit the function.
299 * HWRM_UNLOCK() must be called after all response processing is completed.
301 #define HWRM_PREP(req, type, kong) do { \
302 rte_spinlock_lock(&bp->hwrm_lock); \
303 if (bp->hwrm_cmd_resp_addr == NULL) { \
304 rte_spinlock_unlock(&bp->hwrm_lock); \
307 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
308 (req)->req_type = rte_cpu_to_le_16(type); \
309 (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
310 (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
311 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
312 (req)->target_id = rte_cpu_to_le_16(0xffff); \
313 (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
316 #define HWRM_CHECK_RESULT_SILENT() do {\
318 rte_spinlock_unlock(&bp->hwrm_lock); \
321 if (resp->error_code) { \
322 rc = rte_le_to_cpu_16(resp->error_code); \
323 rte_spinlock_unlock(&bp->hwrm_lock); \
328 #define HWRM_CHECK_RESULT() do {\
330 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
331 rte_spinlock_unlock(&bp->hwrm_lock); \
332 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
334 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
336 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
338 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
340 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
346 if (resp->error_code) { \
347 rc = rte_le_to_cpu_16(resp->error_code); \
348 if (resp->resp_len >= 16) { \
349 struct hwrm_err_output *tmp_hwrm_err_op = \
352 "error %d:%d:%08x:%04x\n", \
353 rc, tmp_hwrm_err_op->cmd_err, \
355 tmp_hwrm_err_op->opaque_0), \
357 tmp_hwrm_err_op->opaque_1)); \
359 PMD_DRV_LOG(ERR, "error %d\n", rc); \
361 rte_spinlock_unlock(&bp->hwrm_lock); \
362 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
364 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
366 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
368 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
370 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
378 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
389 bool mailbox = BNXT_USE_CHIMP_MB;
390 struct input *req = msg;
391 struct output *resp = bp->hwrm_cmd_resp_addr;
394 mailbox = BNXT_USE_KONG(bp);
396 HWRM_PREP(req, msg_type, mailbox);
398 rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
403 memcpy(resp_msg, resp, resp_len);
410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
414 uint32_t *tf_response_code,
418 uint32_t response_len)
421 struct hwrm_cfa_tflib_input req = { .req_type = 0 };
422 struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
423 bool mailbox = BNXT_USE_CHIMP_MB;
425 if (msg_len > sizeof(req.tf_req))
429 mailbox = BNXT_USE_KONG(bp);
431 HWRM_PREP(&req, HWRM_TF, mailbox);
432 /* Build request using the user supplied request payload.
433 * TLV request size is checked at build time against HWRM
434 * request max size, thus no checking required.
436 req.tf_type = tf_type;
437 req.tf_subtype = tf_subtype;
438 memcpy(req.tf_req, msg, msg_len);
440 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
443 /* Copy the resp to user provided response buffer */
444 if (response != NULL)
445 /* Post process response data. We need to copy only
446 * the 'payload' as the HWRM data structure really is
447 * HWRM header + msg header + payload and the TFLIB
448 * only provided a payload place holder.
450 if (response_len != 0) {
456 /* Extract the internal tflib response code */
457 *tf_response_code = resp->tf_resp_code;
463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
466 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
467 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
469 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
470 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
473 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
482 struct bnxt_vnic_info *vnic,
484 struct bnxt_vlan_table_entry *vlan_table)
487 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
488 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
491 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
494 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
495 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
497 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
498 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
499 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
500 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
502 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
503 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
505 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
506 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
507 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
508 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
509 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
510 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
513 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
514 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
515 req.vlan_tag_tbl_addr =
516 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
517 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
519 req.mask = rte_cpu_to_le_32(mask);
521 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
531 struct bnxt_vlan_antispoof_table_entry *vlan_table)
534 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
535 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
536 bp->hwrm_cmd_resp_addr;
539 * Older HWRM versions did not support this command, and the set_rx_mask
540 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
541 * removed from set_rx_mask call, and this command was added.
543 * This command is also present from 1.7.8.11 and higher,
546 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
547 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
548 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
553 HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
554 req.fid = rte_cpu_to_le_16(fid);
556 req.vlan_tag_mask_tbl_addr =
557 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
558 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
560 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
569 struct bnxt_filter_info *filter)
572 struct bnxt_filter_info *l2_filter = filter;
573 struct bnxt_vnic_info *vnic = NULL;
574 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
575 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
577 if (filter->fw_l2_filter_id == UINT64_MAX)
580 if (filter->matching_l2_fltr_ptr)
581 l2_filter = filter->matching_l2_fltr_ptr;
583 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
584 filter, l2_filter, l2_filter->l2_ref_cnt);
586 if (l2_filter->l2_ref_cnt == 0)
589 if (l2_filter->l2_ref_cnt > 0)
590 l2_filter->l2_ref_cnt--;
592 if (l2_filter->l2_ref_cnt > 0)
595 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
597 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
599 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
604 filter->fw_l2_filter_id = UINT64_MAX;
605 if (l2_filter->l2_ref_cnt == 0) {
606 vnic = l2_filter->vnic;
608 STAILQ_REMOVE(&vnic->filter, l2_filter,
609 bnxt_filter_info, next);
610 bnxt_free_filter(bp, l2_filter);
617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
619 struct bnxt_filter_info *filter)
622 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
623 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
624 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
625 const struct rte_eth_vmdq_rx_conf *conf =
626 &dev_conf->rx_adv_conf.vmdq_rx_conf;
627 uint32_t enables = 0;
628 uint16_t j = dst_id - 1;
630 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
631 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
632 conf->pool_map[j].pools & (1UL << j)) {
634 "Add vlan %u to vmdq pool %u\n",
635 conf->pool_map[j].vlan_id, j);
637 filter->l2_ivlan = conf->pool_map[j].vlan_id;
639 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
640 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
643 if (filter->fw_l2_filter_id != UINT64_MAX)
644 bnxt_hwrm_clear_l2_filter(bp, filter);
646 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
648 /* PMD does not support XDP and RoCE */
649 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
650 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
651 req.flags = rte_cpu_to_le_32(filter->flags);
653 enables = filter->enables |
654 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
655 req.dst_id = rte_cpu_to_le_16(dst_id);
658 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
659 memcpy(req.l2_addr, filter->l2_addr,
662 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
663 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
666 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
667 req.l2_ovlan = filter->l2_ovlan;
669 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
670 req.l2_ivlan = filter->l2_ivlan;
672 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
673 req.l2_ovlan_mask = filter->l2_ovlan_mask;
675 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
676 req.l2_ivlan_mask = filter->l2_ivlan_mask;
677 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
678 req.src_id = rte_cpu_to_le_32(filter->src_id);
679 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
680 req.src_type = filter->src_type;
681 if (filter->pri_hint) {
682 req.pri_hint = filter->pri_hint;
683 req.l2_filter_id_hint =
684 rte_cpu_to_le_64(filter->l2_filter_id_hint);
687 req.enables = rte_cpu_to_le_32(enables);
689 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
693 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
694 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
697 filter->l2_ref_cnt++;
702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
704 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
705 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
712 HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
715 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
718 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
719 if (ptp->tx_tstamp_en)
720 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
723 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
724 req.flags = rte_cpu_to_le_32(flags);
725 req.enables = rte_cpu_to_le_32
726 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
727 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
729 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
738 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
739 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
740 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
745 HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
747 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
749 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
753 if (!BNXT_CHIP_P5(bp) &&
754 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
757 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
758 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
760 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
764 if (!BNXT_CHIP_P5(bp)) {
765 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
766 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
767 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
768 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
769 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
770 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
771 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
772 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
773 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
774 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
775 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
776 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
777 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
778 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
779 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
780 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
781 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
782 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
791 void bnxt_free_vf_info(struct bnxt *bp)
795 if (bp->pf->vf_info == NULL)
798 for (i = 0; i < bp->pf->max_vfs; i++) {
799 rte_free(bp->pf->vf_info[i].vlan_table);
800 bp->pf->vf_info[i].vlan_table = NULL;
801 rte_free(bp->pf->vf_info[i].vlan_as_table);
802 bp->pf->vf_info[i].vlan_as_table = NULL;
804 rte_free(bp->pf->vf_info);
805 bp->pf->vf_info = NULL;
808 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
810 struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
814 bnxt_free_vf_info(bp);
816 vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
817 if (vf_info == NULL) {
818 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
822 bp->pf->max_vfs = max_vfs;
823 for (i = 0; i < max_vfs; i++) {
824 vf_info[i].fid = bp->pf->first_vf_id + i;
825 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
826 getpagesize(), getpagesize());
827 if (vf_info[i].vlan_table == NULL) {
828 PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
831 rte_mem_lock_page(vf_info[i].vlan_table);
833 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
834 getpagesize(), getpagesize());
835 if (vf_info[i].vlan_as_table == NULL) {
836 PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
839 rte_mem_lock_page(vf_info[i].vlan_as_table);
841 STAILQ_INIT(&vf_info[i].filter);
844 bp->pf->vf_info = vf_info;
848 bnxt_free_vf_info(bp);
852 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
855 struct hwrm_func_qcaps_input req = {.req_type = 0 };
856 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
857 uint16_t new_max_vfs;
860 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
862 req.fid = rte_cpu_to_le_16(0xffff);
864 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
868 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
869 flags = rte_le_to_cpu_32(resp->flags);
871 bp->pf->port_id = resp->port_id;
872 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
873 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
874 new_max_vfs = bp->pdev->max_vfs;
875 if (new_max_vfs != bp->pf->max_vfs) {
876 rc = bnxt_alloc_vf_info(bp, new_max_vfs);
882 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
883 if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
884 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
885 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
887 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
889 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
890 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
891 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
892 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
893 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
894 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
895 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
896 if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
897 bp->max_l2_ctx += bp->max_rx_em_flows;
898 /* TODO: For now, do not support VMDq/RFS on VFs. */
903 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
907 PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
908 bp->max_l2_ctx, bp->max_vnics);
909 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
911 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
912 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
913 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
914 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
916 bnxt_hwrm_ptp_qcfg(bp);
920 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
921 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
923 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
924 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
925 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
928 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
929 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
931 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
932 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
934 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
935 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
943 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
947 rc = __bnxt_hwrm_func_qcaps(bp);
951 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
952 rc = bnxt_alloc_ctx_mem(bp);
957 * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
958 * But the error can be ignored. Return success.
960 rc = bnxt_hwrm_func_resc_qcaps(bp);
962 bp->flags |= BNXT_FLAG_NEW_RM;
968 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
969 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
973 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
974 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
976 HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
978 req.target_id = rte_cpu_to_le_16(0xffff);
980 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
984 flags = rte_le_to_cpu_32(resp->flags);
986 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
987 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
988 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
991 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
992 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
994 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
995 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
997 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
1004 int bnxt_hwrm_func_reset(struct bnxt *bp)
1007 struct hwrm_func_reset_input req = {.req_type = 0 };
1008 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1010 HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1012 req.enables = rte_cpu_to_le_32(0);
1014 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1016 HWRM_CHECK_RESULT();
1022 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1026 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1027 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1029 if (bp->flags & BNXT_FLAG_REGISTERED)
1032 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1033 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1034 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1035 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1037 /* PFs and trusted VFs should indicate the support of the
1038 * Master capability on non Stingray platform
1040 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1041 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1043 HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1044 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1045 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1046 req.ver_maj = RTE_VER_YEAR;
1047 req.ver_min = RTE_VER_MONTH;
1048 req.ver_upd = RTE_VER_MINOR;
1051 req.enables |= rte_cpu_to_le_32(
1052 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1053 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1054 RTE_MIN(sizeof(req.vf_req_fwd),
1055 sizeof(bp->pf->vf_req_fwd)));
1058 req.flags = rte_cpu_to_le_32(flags);
1060 req.async_event_fwd[0] |=
1061 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1062 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1063 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1064 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1065 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1066 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1067 req.async_event_fwd[0] |=
1068 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1069 req.async_event_fwd[1] |=
1070 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1071 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1073 req.async_event_fwd[1] |=
1074 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1076 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1077 req.async_event_fwd[1] |=
1078 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1080 req.async_event_fwd[2] |=
1081 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST);
1083 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1085 HWRM_CHECK_RESULT();
1087 flags = rte_le_to_cpu_32(resp->flags);
1088 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1089 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1093 bp->flags |= BNXT_FLAG_REGISTERED;
1098 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1100 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1103 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1106 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1111 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1112 struct hwrm_func_vf_cfg_input req = {0};
1114 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1116 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
1117 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
1118 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
1119 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1120 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1122 if (BNXT_HAS_RING_GRPS(bp)) {
1123 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1124 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1127 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1128 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1129 AGG_RING_MULTIPLIER);
1130 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1131 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1133 BNXT_NUM_ASYNC_CPR(bp));
1134 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1135 if (bp->vf_resv_strategy ==
1136 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1137 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1138 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1139 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1140 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1141 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1142 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1143 } else if (bp->vf_resv_strategy ==
1144 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1145 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1146 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1150 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1151 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1152 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1153 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1154 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1155 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1157 if (test && BNXT_HAS_RING_GRPS(bp))
1158 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1160 req.flags = rte_cpu_to_le_32(flags);
1161 req.enables |= rte_cpu_to_le_32(enables);
1163 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1166 HWRM_CHECK_RESULT_SILENT();
1168 HWRM_CHECK_RESULT();
1174 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1177 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1178 struct hwrm_func_resource_qcaps_input req = {0};
1180 HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1181 req.fid = rte_cpu_to_le_16(0xffff);
1183 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1185 HWRM_CHECK_RESULT_SILENT();
1187 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1188 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1189 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1190 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1191 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1192 /* func_resource_qcaps does not return max_rx_em_flows.
1193 * So use the value provided by func_qcaps.
1195 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1196 if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1197 bp->max_l2_ctx += bp->max_rx_em_flows;
1198 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1199 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1200 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1201 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1202 if (bp->vf_resv_strategy >
1203 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1204 bp->vf_resv_strategy =
1205 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1211 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1214 struct hwrm_ver_get_input req = {.req_type = 0 };
1215 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1216 uint32_t fw_version;
1217 uint16_t max_resp_len;
1218 char type[RTE_MEMZONE_NAMESIZE];
1219 uint32_t dev_caps_cfg;
1221 bp->max_req_len = HWRM_MAX_REQ_LEN;
1222 bp->hwrm_cmd_timeout = timeout;
1223 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1225 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1226 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1227 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1229 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1231 if (bp->flags & BNXT_FLAG_FW_RESET)
1232 HWRM_CHECK_RESULT_SILENT();
1234 HWRM_CHECK_RESULT();
1236 if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
1241 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1242 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1243 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1244 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1245 resp->hwrm_fw_rsvd_8b);
1246 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1247 (resp->hwrm_fw_min_8b << 16) |
1248 (resp->hwrm_fw_bld_8b << 8) |
1249 resp->hwrm_fw_rsvd_8b;
1250 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1251 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1253 fw_version = resp->hwrm_intf_maj_8b << 16;
1254 fw_version |= resp->hwrm_intf_min_8b << 8;
1255 fw_version |= resp->hwrm_intf_upd_8b;
1256 bp->hwrm_spec_code = fw_version;
1258 /* def_req_timeout value is in milliseconds */
1259 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1260 /* convert timeout to usec */
1261 bp->hwrm_cmd_timeout *= 1000;
1262 if (!bp->hwrm_cmd_timeout)
1263 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1265 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1266 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1271 if (bp->max_req_len > resp->max_req_win_len) {
1272 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1277 bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1279 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1280 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1281 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1282 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1284 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1285 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1287 if (bp->max_resp_len != max_resp_len) {
1288 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1289 bp->pdev->addr.domain, bp->pdev->addr.bus,
1290 bp->pdev->addr.devid, bp->pdev->addr.function);
1292 rte_free(bp->hwrm_cmd_resp_addr);
1294 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1295 if (bp->hwrm_cmd_resp_addr == NULL) {
1299 bp->hwrm_cmd_resp_dma_addr =
1300 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1301 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1303 "Unable to map response buffer to physical memory.\n");
1307 bp->max_resp_len = max_resp_len;
1311 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1313 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1314 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1315 bp->flags |= BNXT_FLAG_SHORT_CMD;
1318 if (((dev_caps_cfg &
1319 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1321 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1322 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1323 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1324 bp->pdev->addr.domain, bp->pdev->addr.bus,
1325 bp->pdev->addr.devid, bp->pdev->addr.function);
1327 rte_free(bp->hwrm_short_cmd_req_addr);
1329 bp->hwrm_short_cmd_req_addr =
1330 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1331 if (bp->hwrm_short_cmd_req_addr == NULL) {
1335 bp->hwrm_short_cmd_req_dma_addr =
1336 rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1337 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1338 rte_free(bp->hwrm_short_cmd_req_addr);
1340 "Unable to map buffer to physical memory.\n");
1346 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1347 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1348 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1351 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1352 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1354 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1355 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1356 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1360 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1361 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1362 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1370 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1373 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1374 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1376 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1379 HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1382 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1384 HWRM_CHECK_RESULT();
1390 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1393 struct hwrm_port_phy_cfg_input req = {0};
1394 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1395 uint32_t enables = 0;
1397 HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1399 if (conf->link_up) {
1400 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1401 if (bp->link_info->auto_mode && conf->link_speed) {
1402 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1403 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1406 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1408 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1409 * any auto mode, even "none".
1411 if (!conf->link_speed) {
1412 /* No speeds specified. Enable AutoNeg - all speeds */
1413 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1415 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1417 if (bp->link_info->link_signal_mode) {
1419 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1420 req.force_pam4_link_speed =
1421 rte_cpu_to_le_16(conf->link_speed);
1423 req.force_link_speed =
1424 rte_cpu_to_le_16(conf->link_speed);
1427 /* AutoNeg - Advertise speeds specified. */
1428 if (conf->auto_link_speed_mask &&
1429 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1431 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1432 req.auto_link_speed_mask =
1433 conf->auto_link_speed_mask;
1434 if (conf->auto_pam4_link_speeds) {
1436 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1437 req.auto_link_pam4_speed_mask =
1438 conf->auto_pam4_link_speeds;
1441 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1444 if (conf->auto_link_speed &&
1445 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1447 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1449 req.auto_duplex = conf->duplex;
1450 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1451 req.auto_pause = conf->auto_pause;
1452 req.force_pause = conf->force_pause;
1453 /* Set force_pause if there is no auto or if there is a force */
1454 if (req.auto_pause && !req.force_pause)
1455 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1457 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1459 req.enables = rte_cpu_to_le_32(enables);
1462 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1463 PMD_DRV_LOG(INFO, "Force Link Down\n");
1466 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1468 HWRM_CHECK_RESULT();
1471 PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1472 bp->eth_dev->data->port_id);
1476 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1477 struct bnxt_link_info *link_info)
1480 struct hwrm_port_phy_qcfg_input req = {0};
1481 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1483 HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1485 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1487 HWRM_CHECK_RESULT();
1489 link_info->phy_link_status = resp->link;
1490 link_info->link_up =
1491 (link_info->phy_link_status ==
1492 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1493 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1494 link_info->duplex = resp->duplex_cfg;
1495 link_info->pause = resp->pause;
1496 link_info->auto_pause = resp->auto_pause;
1497 link_info->force_pause = resp->force_pause;
1498 link_info->auto_mode = resp->auto_mode;
1499 link_info->phy_type = resp->phy_type;
1500 link_info->media_type = resp->media_type;
1502 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1503 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1504 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1505 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1506 link_info->phy_ver[0] = resp->phy_maj;
1507 link_info->phy_ver[1] = resp->phy_min;
1508 link_info->phy_ver[2] = resp->phy_bld;
1509 link_info->link_signal_mode =
1510 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1511 link_info->force_pam4_link_speed =
1512 rte_le_to_cpu_16(resp->force_pam4_link_speed);
1513 link_info->support_pam4_speeds =
1514 rte_le_to_cpu_16(resp->support_pam4_speeds);
1515 link_info->auto_pam4_link_speeds =
1516 rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1519 PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1520 link_info->link_speed, link_info->auto_mode,
1521 link_info->auto_link_speed, link_info->auto_link_speed_mask,
1522 link_info->support_speeds, link_info->force_link_speed);
1523 PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1524 link_info->link_signal_mode,
1525 link_info->auto_pam4_link_speeds,
1526 link_info->support_pam4_speeds,
1527 link_info->force_pam4_link_speed);
1531 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1534 struct hwrm_port_phy_qcaps_input req = {0};
1535 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1536 struct bnxt_link_info *link_info = bp->link_info;
1538 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1541 HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1543 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1545 HWRM_CHECK_RESULT_SILENT();
1547 bp->port_cnt = resp->port_cnt;
1548 if (resp->supported_speeds_auto_mode)
1549 link_info->support_auto_speeds =
1550 rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1551 if (resp->supported_pam4_speeds_auto_mode)
1552 link_info->support_pam4_auto_speeds =
1553 rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1560 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1564 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1565 if (bp->tx_cos_queue[i].profile ==
1566 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1567 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1574 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1578 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1579 if (bp->tx_cos_queue[i].profile !=
1580 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1581 bp->tx_cos_queue[i].id !=
1582 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1583 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1589 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1592 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1593 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1594 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1598 HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1600 req.flags = rte_cpu_to_le_32(dir);
1601 /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1602 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1603 !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1605 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1606 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1608 HWRM_CHECK_RESULT();
1610 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1611 GET_TX_QUEUE_INFO(0);
1612 GET_TX_QUEUE_INFO(1);
1613 GET_TX_QUEUE_INFO(2);
1614 GET_TX_QUEUE_INFO(3);
1615 GET_TX_QUEUE_INFO(4);
1616 GET_TX_QUEUE_INFO(5);
1617 GET_TX_QUEUE_INFO(6);
1618 GET_TX_QUEUE_INFO(7);
1620 GET_RX_QUEUE_INFO(0);
1621 GET_RX_QUEUE_INFO(1);
1622 GET_RX_QUEUE_INFO(2);
1623 GET_RX_QUEUE_INFO(3);
1624 GET_RX_QUEUE_INFO(4);
1625 GET_RX_QUEUE_INFO(5);
1626 GET_RX_QUEUE_INFO(6);
1627 GET_RX_QUEUE_INFO(7);
1632 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1635 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1636 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1640 /* iterate and find the COSq profile to use for Tx */
1641 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1642 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1643 if (bp->tx_cos_queue[i].id != 0xff)
1644 bp->tx_cosq_id[j++] =
1645 bp->tx_cos_queue[i].id;
1648 /* When CoS classification is disabled, for normal NIC
1649 * operations, ideally we should look to use LOSSY.
1650 * If not found, fallback to the first valid profile
1652 if (!bnxt_find_lossy_profile(bp))
1653 bnxt_find_first_valid_profile(bp);
1658 bp->max_tc = resp->max_configurable_queues;
1659 bp->max_lltc = resp->max_configurable_lossless_queues;
1660 if (bp->max_tc > BNXT_MAX_QUEUE)
1661 bp->max_tc = BNXT_MAX_QUEUE;
1662 bp->max_q = bp->max_tc;
1664 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1665 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1673 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1674 struct bnxt_ring *ring,
1675 uint32_t ring_type, uint32_t map_index,
1676 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1677 uint16_t tx_cosq_id)
1680 uint32_t enables = 0;
1681 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1682 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1683 struct rte_mempool *mb_pool;
1684 uint16_t rx_buf_size;
1686 HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1688 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1689 req.fbo = rte_cpu_to_le_32(0);
1690 /* Association of ring index with doorbell index */
1691 req.logical_id = rte_cpu_to_le_16(map_index);
1692 req.length = rte_cpu_to_le_32(ring->ring_size);
1694 switch (ring_type) {
1695 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1696 req.ring_type = ring_type;
1697 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1698 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1699 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1700 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1702 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1704 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1705 req.ring_type = ring_type;
1706 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1707 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1708 if (BNXT_CHIP_P5(bp)) {
1709 mb_pool = bp->rx_queues[0]->mb_pool;
1710 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1711 RTE_PKTMBUF_HEADROOM;
1712 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1713 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1715 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1717 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1719 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1721 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1722 req.ring_type = ring_type;
1723 if (BNXT_HAS_NQ(bp)) {
1724 /* Association of cp ring with nq */
1725 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1727 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1729 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1731 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1732 req.ring_type = ring_type;
1733 req.page_size = BNXT_PAGE_SHFT;
1734 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1736 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1737 req.ring_type = ring_type;
1738 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1740 mb_pool = bp->rx_queues[0]->mb_pool;
1741 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1742 RTE_PKTMBUF_HEADROOM;
1743 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1744 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1746 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1747 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1748 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1749 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1752 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1757 req.enables = rte_cpu_to_le_32(enables);
1759 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1761 if (rc || resp->error_code) {
1762 if (rc == 0 && resp->error_code)
1763 rc = rte_le_to_cpu_16(resp->error_code);
1764 switch (ring_type) {
1765 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1767 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1770 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1772 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1775 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1777 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1781 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1783 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1786 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1788 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1792 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1798 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1803 int bnxt_hwrm_ring_free(struct bnxt *bp,
1804 struct bnxt_ring *ring, uint32_t ring_type,
1805 uint16_t cp_ring_id)
1808 struct hwrm_ring_free_input req = {.req_type = 0 };
1809 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1811 HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1813 req.ring_type = ring_type;
1814 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1815 req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1817 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1819 if (rc || resp->error_code) {
1820 if (rc == 0 && resp->error_code)
1821 rc = rte_le_to_cpu_16(resp->error_code);
1824 switch (ring_type) {
1825 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1826 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1829 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1830 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1833 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1834 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1837 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1839 "hwrm_ring_free nq failed. rc:%d\n", rc);
1841 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1843 "hwrm_ring_free agg failed. rc:%d\n", rc);
1846 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1854 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1857 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1858 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1860 HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1862 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1863 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1864 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1865 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1867 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1869 HWRM_CHECK_RESULT();
1871 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1878 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1881 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1882 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1884 HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1886 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1888 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1890 HWRM_CHECK_RESULT();
1893 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1897 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1900 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1901 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1903 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1906 HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1908 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1910 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1912 HWRM_CHECK_RESULT();
1918 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1919 unsigned int idx __rte_unused)
1922 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1923 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1925 HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1927 req.update_period_ms = rte_cpu_to_le_32(0);
1929 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1931 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1933 HWRM_CHECK_RESULT();
1935 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1942 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1943 unsigned int idx __rte_unused)
1946 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1947 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1949 HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1951 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1953 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1955 HWRM_CHECK_RESULT();
1961 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1964 struct hwrm_vnic_alloc_input req = { 0 };
1965 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1967 if (!BNXT_HAS_RING_GRPS(bp))
1968 goto skip_ring_grps;
1970 /* map ring groups to this vnic */
1971 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1972 vnic->start_grp_id, vnic->end_grp_id);
1973 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1974 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1976 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1977 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1978 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1979 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1982 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1983 HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1985 if (vnic->func_default)
1987 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1988 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1990 HWRM_CHECK_RESULT();
1992 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1994 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1998 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1999 struct bnxt_vnic_info *vnic,
2000 struct bnxt_plcmodes_cfg *pmode)
2003 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
2004 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2006 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
2008 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2010 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2012 HWRM_CHECK_RESULT();
2014 pmode->flags = rte_le_to_cpu_32(resp->flags);
2015 /* dflt_vnic bit doesn't exist in the _cfg command */
2016 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
2017 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
2018 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2019 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2026 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2027 struct bnxt_vnic_info *vnic,
2028 struct bnxt_plcmodes_cfg *pmode)
2031 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2032 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2034 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2035 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2039 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2041 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2042 req.flags = rte_cpu_to_le_32(pmode->flags);
2043 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2044 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2045 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2046 req.enables = rte_cpu_to_le_32(
2047 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2048 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2049 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2052 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2054 HWRM_CHECK_RESULT();
2060 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2063 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2064 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2065 struct bnxt_plcmodes_cfg pmodes = { 0 };
2066 uint32_t ctx_enable_flag = 0;
2067 uint32_t enables = 0;
2069 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2070 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2074 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2078 HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2080 if (BNXT_CHIP_P5(bp)) {
2081 int dflt_rxq = vnic->start_grp_id;
2082 struct bnxt_rx_ring_info *rxr;
2083 struct bnxt_cp_ring_info *cpr;
2084 struct bnxt_rx_queue *rxq;
2088 * The first active receive ring is used as the VNIC
2089 * default receive ring. If there are no active receive
2090 * rings (all corresponding receive queues are stopped),
2091 * the first receive ring is used.
2093 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2094 rxq = bp->eth_dev->data->rx_queues[i];
2095 if (rxq->rx_started) {
2101 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2105 req.default_rx_ring_id =
2106 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2107 req.default_cmpl_ring_id =
2108 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2109 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2110 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2111 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2112 enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2113 req.rx_csum_v2_mode =
2114 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2119 /* Only RSS support for now TBD: COS & LB */
2120 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2121 if (vnic->lb_rule != 0xffff)
2122 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2123 if (vnic->cos_rule != 0xffff)
2124 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2125 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2126 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2127 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2129 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2130 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2131 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2134 enables |= ctx_enable_flag;
2135 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2136 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2137 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2138 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2141 req.enables = rte_cpu_to_le_32(enables);
2142 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2143 req.mru = rte_cpu_to_le_16(vnic->mru);
2144 /* Configure default VNIC only once. */
2145 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2147 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2148 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2150 if (vnic->vlan_strip)
2152 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2155 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2156 if (vnic->rss_dflt_cr)
2157 req.flags |= rte_cpu_to_le_32(
2158 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2160 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2162 HWRM_CHECK_RESULT();
2165 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2170 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2174 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2175 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2177 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2178 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2181 HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2184 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2185 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2186 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2188 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2190 HWRM_CHECK_RESULT();
2192 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2193 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2194 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2195 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2196 vnic->mru = rte_le_to_cpu_16(resp->mru);
2197 vnic->func_default = rte_le_to_cpu_32(
2198 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2199 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2200 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2201 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2202 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2203 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2204 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2211 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2212 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2216 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2217 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2218 bp->hwrm_cmd_resp_addr;
2220 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2222 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2223 HWRM_CHECK_RESULT();
2225 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2226 if (!BNXT_HAS_RING_GRPS(bp))
2227 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2228 else if (ctx_idx == 0)
2229 vnic->rss_rule = ctx_id;
2237 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2238 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2241 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2242 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2243 bp->hwrm_cmd_resp_addr;
2245 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2246 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2249 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2251 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2253 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2255 HWRM_CHECK_RESULT();
2261 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2265 if (BNXT_CHIP_P5(bp)) {
2268 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2269 rc = _bnxt_hwrm_vnic_ctx_free(bp,
2271 vnic->fw_grp_ids[j]);
2272 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2274 vnic->num_lb_ctxts = 0;
2276 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2277 vnic->rss_rule = INVALID_HW_RING_ID;
2283 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2286 struct hwrm_vnic_free_input req = {.req_type = 0 };
2287 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2289 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2290 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2294 HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2296 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2298 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2300 HWRM_CHECK_RESULT();
2303 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2304 /* Configure default VNIC again if necessary. */
2305 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2306 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2312 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2316 int nr_ctxs = vnic->num_lb_ctxts;
2317 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2318 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2320 for (i = 0; i < nr_ctxs; i++) {
2321 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2323 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2324 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2325 req.hash_mode_flags = vnic->hash_mode;
2327 req.hash_key_tbl_addr =
2328 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2330 req.ring_grp_tbl_addr =
2331 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2332 i * HW_HASH_INDEX_SIZE);
2333 req.ring_table_pair_index = i;
2334 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2336 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2339 HWRM_CHECK_RESULT();
2346 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2347 struct bnxt_vnic_info *vnic)
2350 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2351 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2353 if (!vnic->rss_table)
2356 if (BNXT_CHIP_P5(bp))
2357 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2359 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2361 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2362 req.hash_mode_flags = vnic->hash_mode;
2364 req.ring_grp_tbl_addr =
2365 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2366 req.hash_key_tbl_addr =
2367 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2368 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2369 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2371 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2373 HWRM_CHECK_RESULT();
2379 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2380 struct bnxt_vnic_info *vnic)
2383 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2384 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2387 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2388 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2392 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2394 req.flags = rte_cpu_to_le_32(
2395 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2397 req.enables = rte_cpu_to_le_32(
2398 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2400 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2401 size -= RTE_PKTMBUF_HEADROOM;
2402 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2404 req.jumbo_thresh = rte_cpu_to_le_16(size);
2405 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2407 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2409 HWRM_CHECK_RESULT();
2415 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2416 struct bnxt_vnic_info *vnic, bool enable)
2419 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2420 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2422 if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2424 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2428 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2429 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2433 HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2436 req.enables = rte_cpu_to_le_32(
2437 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2438 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2439 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2440 req.flags = rte_cpu_to_le_32(
2441 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2442 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2443 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2444 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2445 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2446 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2447 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2448 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2449 req.min_agg_len = rte_cpu_to_le_32(512);
2451 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2453 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2455 HWRM_CHECK_RESULT();
2461 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2463 struct hwrm_func_cfg_input req = {0};
2464 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2467 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2468 req.enables = rte_cpu_to_le_32(
2469 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2470 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2471 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2473 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2475 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2476 HWRM_CHECK_RESULT();
2479 bp->pf->vf_info[vf].random_mac = false;
2484 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2488 struct hwrm_func_qstats_input req = {.req_type = 0};
2489 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2491 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2493 req.fid = rte_cpu_to_le_16(fid);
2495 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2497 HWRM_CHECK_RESULT();
2500 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2507 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2508 struct rte_eth_stats *stats,
2509 struct hwrm_func_qstats_output *func_qstats)
2512 struct hwrm_func_qstats_input req = {.req_type = 0};
2513 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2515 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2517 req.fid = rte_cpu_to_le_16(fid);
2519 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2521 HWRM_CHECK_RESULT();
2523 memcpy(func_qstats, resp,
2524 sizeof(struct hwrm_func_qstats_output));
2529 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2530 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2531 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2532 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2533 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2534 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2536 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2537 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2538 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2539 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2540 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2541 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2543 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2544 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2545 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2553 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2556 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2557 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2559 HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2561 req.fid = rte_cpu_to_le_16(fid);
2563 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2565 HWRM_CHECK_RESULT();
2571 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2576 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2577 struct bnxt_tx_queue *txq;
2578 struct bnxt_rx_queue *rxq;
2579 struct bnxt_cp_ring_info *cpr;
2581 if (i >= bp->rx_cp_nr_rings) {
2582 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2585 rxq = bp->rx_queues[i];
2589 rc = bnxt_hwrm_stat_clear(bp, cpr);
2597 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2601 struct bnxt_cp_ring_info *cpr;
2603 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2605 if (i >= bp->rx_cp_nr_rings) {
2606 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2608 cpr = bp->rx_queues[i]->cp_ring;
2609 if (BNXT_HAS_RING_GRPS(bp))
2610 bp->grp_info[i].fw_stats_ctx = -1;
2612 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2613 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2614 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2622 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2627 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2628 struct bnxt_tx_queue *txq;
2629 struct bnxt_rx_queue *rxq;
2630 struct bnxt_cp_ring_info *cpr;
2632 if (i >= bp->rx_cp_nr_rings) {
2633 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2636 rxq = bp->rx_queues[i];
2640 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2649 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2654 if (!BNXT_HAS_RING_GRPS(bp))
2657 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2659 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2662 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2670 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2672 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2674 bnxt_hwrm_ring_free(bp, cp_ring,
2675 HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2676 INVALID_HW_RING_ID);
2677 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2678 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2679 sizeof(*cpr->cp_desc_ring));
2680 cpr->cp_raw_cons = 0;
2684 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2686 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2688 bnxt_hwrm_ring_free(bp, cp_ring,
2689 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2690 INVALID_HW_RING_ID);
2691 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2692 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2693 sizeof(*cpr->cp_desc_ring));
2694 cpr->cp_raw_cons = 0;
2698 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2700 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2701 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2702 struct bnxt_ring *ring = rxr->rx_ring_struct;
2703 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2705 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2706 bnxt_hwrm_ring_free(bp, ring,
2707 HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2708 cpr->cp_ring_struct->fw_ring_id);
2709 ring->fw_ring_id = INVALID_HW_RING_ID;
2710 if (BNXT_HAS_RING_GRPS(bp))
2711 bp->grp_info[queue_index].rx_fw_ring_id =
2714 ring = rxr->ag_ring_struct;
2715 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2716 bnxt_hwrm_ring_free(bp, ring,
2718 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2719 HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2720 cpr->cp_ring_struct->fw_ring_id);
2721 if (BNXT_HAS_RING_GRPS(bp))
2722 bp->grp_info[queue_index].ag_fw_ring_id =
2725 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2726 bnxt_free_cp_ring(bp, cpr);
2728 if (BNXT_HAS_RING_GRPS(bp))
2729 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2733 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2737 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2738 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2739 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2740 struct bnxt_ring *ring = txr->tx_ring_struct;
2741 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2743 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2744 bnxt_hwrm_ring_free(bp, ring,
2745 HWRM_RING_FREE_INPUT_RING_TYPE_TX,
2746 cpr->cp_ring_struct->fw_ring_id);
2747 ring->fw_ring_id = INVALID_HW_RING_ID;
2748 memset(txr->tx_desc_ring, 0,
2749 txr->tx_ring_struct->ring_size *
2750 sizeof(*txr->tx_desc_ring));
2751 memset(txr->tx_buf_ring, 0,
2752 txr->tx_ring_struct->ring_size *
2753 sizeof(*txr->tx_buf_ring));
2754 txr->tx_raw_prod = 0;
2755 txr->tx_raw_cons = 0;
2757 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2758 bnxt_free_cp_ring(bp, cpr);
2759 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2763 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2764 bnxt_free_hwrm_rx_ring(bp, i);
2769 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2774 if (!BNXT_HAS_RING_GRPS(bp))
2777 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2778 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2786 * HWRM utility functions
2789 void bnxt_free_hwrm_resources(struct bnxt *bp)
2791 /* Release memzone */
2792 rte_free(bp->hwrm_cmd_resp_addr);
2793 rte_free(bp->hwrm_short_cmd_req_addr);
2794 bp->hwrm_cmd_resp_addr = NULL;
2795 bp->hwrm_short_cmd_req_addr = NULL;
2796 bp->hwrm_cmd_resp_dma_addr = 0;
2797 bp->hwrm_short_cmd_req_dma_addr = 0;
2800 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2802 struct rte_pci_device *pdev = bp->pdev;
2803 char type[RTE_MEMZONE_NAMESIZE];
2805 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2806 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2807 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2808 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2809 if (bp->hwrm_cmd_resp_addr == NULL)
2811 bp->hwrm_cmd_resp_dma_addr =
2812 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2813 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2815 "unable to map response address to physical memory\n");
2818 rte_spinlock_init(&bp->hwrm_lock);
2824 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2828 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2829 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2832 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2833 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2838 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2843 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2845 struct bnxt_filter_info *filter;
2848 STAILQ_FOREACH(filter, &vnic->filter, next) {
2849 rc = bnxt_clear_one_vnic_filter(bp, filter);
2850 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2851 bnxt_free_filter(bp, filter);
2857 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2859 struct bnxt_filter_info *filter;
2860 struct rte_flow *flow;
2863 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2864 flow = STAILQ_FIRST(&vnic->flow_list);
2865 filter = flow->filter;
2866 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2867 rc = bnxt_clear_one_vnic_filter(bp, filter);
2869 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2875 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2877 struct bnxt_filter_info *filter;
2880 STAILQ_FOREACH(filter, &vnic->filter, next) {
2881 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2882 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2884 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2885 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2888 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2897 bnxt_free_tunnel_ports(struct bnxt *bp)
2899 if (bp->vxlan_port_cnt)
2900 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2901 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2903 if (bp->geneve_port_cnt)
2904 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2905 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2908 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2912 if (bp->vnic_info == NULL)
2916 * Cleanup VNICs in reverse order, to make sure the L2 filter
2917 * from vnic0 is last to be cleaned up.
2919 for (i = bp->max_vnics - 1; i >= 0; i--) {
2920 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2922 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2925 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2927 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2929 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2931 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2933 bnxt_hwrm_vnic_free(bp, vnic);
2935 rte_free(vnic->fw_grp_ids);
2937 /* Ring resources */
2938 bnxt_free_all_hwrm_rings(bp);
2939 bnxt_free_all_hwrm_ring_grps(bp);
2940 bnxt_free_all_hwrm_stat_ctxs(bp);
2941 bnxt_free_tunnel_ports(bp);
2944 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2946 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2948 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2949 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2951 switch (conf_link_speed) {
2952 case ETH_LINK_SPEED_10M_HD:
2953 case ETH_LINK_SPEED_100M_HD:
2955 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2957 return hw_link_duplex;
2960 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2965 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2968 uint16_t eth_link_speed = 0;
2970 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2971 return ETH_LINK_SPEED_AUTONEG;
2973 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2974 case ETH_LINK_SPEED_100M:
2975 case ETH_LINK_SPEED_100M_HD:
2978 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2980 case ETH_LINK_SPEED_1G:
2982 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2984 case ETH_LINK_SPEED_2_5G:
2986 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2988 case ETH_LINK_SPEED_10G:
2990 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2992 case ETH_LINK_SPEED_20G:
2994 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2996 case ETH_LINK_SPEED_25G:
2998 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
3000 case ETH_LINK_SPEED_40G:
3002 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
3004 case ETH_LINK_SPEED_50G:
3005 eth_link_speed = pam4_link ?
3006 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
3007 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
3009 case ETH_LINK_SPEED_100G:
3010 eth_link_speed = pam4_link ?
3011 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
3012 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
3014 case ETH_LINK_SPEED_200G:
3016 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3020 "Unsupported link speed %d; default to AUTO\n",
3024 return eth_link_speed;
3027 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
3028 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
3029 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
3030 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
3031 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
3033 static int bnxt_validate_link_speed(struct bnxt *bp)
3035 uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3036 uint16_t port_id = bp->eth_dev->data->port_id;
3037 uint32_t link_speed_capa;
3040 if (link_speed == ETH_LINK_SPEED_AUTONEG)
3043 link_speed_capa = bnxt_get_speed_capabilities(bp);
3045 if (link_speed & ETH_LINK_SPEED_FIXED) {
3046 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
3048 if (one_speed & (one_speed - 1)) {
3050 "Invalid advertised speeds (%u) for port %u\n",
3051 link_speed, port_id);
3054 if ((one_speed & link_speed_capa) != one_speed) {
3056 "Unsupported advertised speed (%u) for port %u\n",
3057 link_speed, port_id);
3061 if (!(link_speed & link_speed_capa)) {
3063 "Unsupported advertised speeds (%u) for port %u\n",
3064 link_speed, port_id);
3072 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3076 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
3077 if (bp->link_info->support_speeds)
3078 return bp->link_info->support_speeds;
3079 link_speed = BNXT_SUPPORTED_SPEEDS;
3082 if (link_speed & ETH_LINK_SPEED_100M)
3083 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3084 if (link_speed & ETH_LINK_SPEED_100M_HD)
3085 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3086 if (link_speed & ETH_LINK_SPEED_1G)
3087 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3088 if (link_speed & ETH_LINK_SPEED_2_5G)
3089 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3090 if (link_speed & ETH_LINK_SPEED_10G)
3091 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3092 if (link_speed & ETH_LINK_SPEED_20G)
3093 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3094 if (link_speed & ETH_LINK_SPEED_25G)
3095 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3096 if (link_speed & ETH_LINK_SPEED_40G)
3097 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3098 if (link_speed & ETH_LINK_SPEED_50G)
3099 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3100 if (link_speed & ETH_LINK_SPEED_100G)
3101 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3102 if (link_speed & ETH_LINK_SPEED_200G)
3103 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3107 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3109 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
3111 switch (hw_link_speed) {
3112 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3113 eth_link_speed = ETH_SPEED_NUM_100M;
3115 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3116 eth_link_speed = ETH_SPEED_NUM_1G;
3118 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3119 eth_link_speed = ETH_SPEED_NUM_2_5G;
3121 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3122 eth_link_speed = ETH_SPEED_NUM_10G;
3124 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3125 eth_link_speed = ETH_SPEED_NUM_20G;
3127 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3128 eth_link_speed = ETH_SPEED_NUM_25G;
3130 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3131 eth_link_speed = ETH_SPEED_NUM_40G;
3133 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3134 eth_link_speed = ETH_SPEED_NUM_50G;
3136 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3137 eth_link_speed = ETH_SPEED_NUM_100G;
3139 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3140 eth_link_speed = ETH_SPEED_NUM_200G;
3142 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3144 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3148 return eth_link_speed;
3151 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3153 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3155 switch (hw_link_duplex) {
3156 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3157 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3159 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3161 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3162 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3165 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3169 return eth_link_duplex;
3172 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3175 struct bnxt_link_info *link_info = bp->link_info;
3177 rc = bnxt_hwrm_port_phy_qcaps(bp);
3179 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3181 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3183 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3187 if (link_info->link_speed)
3189 bnxt_parse_hw_link_speed(link_info->link_speed);
3191 link->link_speed = ETH_SPEED_NUM_NONE;
3192 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3193 link->link_status = link_info->link_up;
3194 link->link_autoneg = link_info->auto_mode ==
3195 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3196 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3201 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3204 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3205 struct bnxt_link_info link_req;
3206 uint16_t speed, autoneg;
3208 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3211 rc = bnxt_validate_link_speed(bp);
3215 memset(&link_req, 0, sizeof(link_req));
3216 link_req.link_up = link_up;
3220 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3221 if (BNXT_CHIP_P5(bp) &&
3222 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3223 /* 40G is not supported as part of media auto detect.
3224 * The speed should be forced and autoneg disabled
3225 * to configure 40G speed.
3227 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3231 /* No auto speeds and no auto_pam4_link. Disable autoneg */
3232 if (bp->link_info->auto_link_speed == 0 &&
3233 bp->link_info->link_signal_mode &&
3234 bp->link_info->auto_pam4_link_speeds == 0)
3237 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3238 bp->link_info->link_signal_mode);
3239 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3240 /* Autoneg can be done only when the FW allows.
3241 * When user configures fixed speed of 40G and later changes to
3242 * any other speed, auto_link_speed/force_link_speed is still set
3243 * to 40G until link comes up at new speed.
3246 !(!BNXT_CHIP_P5(bp) &&
3247 (bp->link_info->auto_link_speed ||
3248 bp->link_info->force_link_speed))) {
3249 link_req.phy_flags |=
3250 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3251 link_req.auto_link_speed_mask =
3252 bnxt_parse_eth_link_speed_mask(bp,
3253 dev_conf->link_speeds);
3255 if (bp->link_info->phy_type ==
3256 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3257 bp->link_info->phy_type ==
3258 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3259 bp->link_info->media_type ==
3260 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3261 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3265 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3266 /* If user wants a particular speed try that first. */
3268 link_req.link_speed = speed;
3269 else if (bp->link_info->force_pam4_link_speed)
3270 link_req.link_speed =
3271 bp->link_info->force_pam4_link_speed;
3272 else if (bp->link_info->auto_pam4_link_speeds)
3273 link_req.link_speed =
3274 bp->link_info->auto_pam4_link_speeds;
3275 else if (bp->link_info->support_pam4_speeds)
3276 link_req.link_speed =
3277 bp->link_info->support_pam4_speeds;
3278 else if (bp->link_info->force_link_speed)
3279 link_req.link_speed = bp->link_info->force_link_speed;
3281 link_req.link_speed = bp->link_info->auto_link_speed;
3282 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3283 * zero. Use the auto_link_speed.
3285 if (bp->link_info->auto_link_speed != 0 &&
3286 bp->link_info->auto_pam4_link_speeds == 0)
3287 link_req.link_speed = bp->link_info->auto_link_speed;
3289 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3290 link_req.auto_pause = bp->link_info->auto_pause;
3291 link_req.force_pause = bp->link_info->force_pause;
3294 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3297 "Set link config failed with rc %d\n", rc);
3305 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3307 struct hwrm_func_qcfg_input req = {0};
3308 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3311 bp->func_svif = BNXT_SVIF_INVALID;
3314 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3315 req.fid = rte_cpu_to_le_16(0xffff);
3317 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3319 HWRM_CHECK_RESULT();
3321 /* Hard Coded.. 0xfff VLAN ID mask */
3322 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3324 svif_info = rte_le_to_cpu_16(resp->svif_info);
3325 if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3326 bp->func_svif = svif_info &
3327 HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3329 flags = rte_le_to_cpu_16(resp->flags);
3330 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3331 bp->flags |= BNXT_FLAG_MULTI_HOST;
3334 !BNXT_VF_IS_TRUSTED(bp) &&
3335 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3336 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3337 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3338 } else if (BNXT_VF(bp) &&
3339 BNXT_VF_IS_TRUSTED(bp) &&
3340 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3341 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3342 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3346 *mtu = rte_le_to_cpu_16(resp->mtu);
3348 switch (resp->port_partition_type) {
3349 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3350 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3351 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3353 bp->flags |= BNXT_FLAG_NPAR_PF;
3356 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3360 bp->legacy_db_size =
3361 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3368 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3370 struct hwrm_func_qcfg_input req = {0};
3371 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3374 if (!BNXT_VF_IS_TRUSTED(bp))
3380 bp->parent->fid = BNXT_PF_FID_INVALID;
3382 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3384 req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3386 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3388 HWRM_CHECK_RESULT_SILENT();
3390 memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3391 bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3392 bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3393 bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3395 /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3396 if (bp->parent->vnic == 0) {
3397 PMD_DRV_LOG(DEBUG, "parent VNIC unavailable.\n");
3398 /* Use hard-coded values appropriate for current Wh+ fw. */
3399 if (bp->parent->fid == 2)
3400 bp->parent->vnic = 0x100;
3402 bp->parent->vnic = 1;
3410 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3411 uint16_t *vnic_id, uint16_t *svif)
3413 struct hwrm_func_qcfg_input req = {0};
3414 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3418 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3419 req.fid = rte_cpu_to_le_16(fid);
3421 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3423 HWRM_CHECK_RESULT();
3426 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3428 svif_info = rte_le_to_cpu_16(resp->svif_info);
3429 if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3430 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3437 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3439 struct hwrm_port_mac_qcfg_input req = {0};
3440 struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3441 uint16_t port_svif_info;
3444 bp->port_svif = BNXT_SVIF_INVALID;
3446 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3449 HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3451 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3453 HWRM_CHECK_RESULT_SILENT();
3455 port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3456 if (port_svif_info &
3457 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3458 bp->port_svif = port_svif_info &
3459 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3466 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3467 struct bnxt_pf_resource_info *pf_resc)
3469 struct hwrm_func_cfg_input req = {0};
3470 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3474 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3475 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3476 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3477 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3478 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3479 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3480 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3481 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3482 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3484 if (BNXT_HAS_RING_GRPS(bp)) {
3485 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3486 req.num_hw_ring_grps =
3487 rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3488 } else if (BNXT_HAS_NQ(bp)) {
3489 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3490 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3493 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3494 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3495 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3496 req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3497 req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3498 req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3499 req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3500 req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3501 req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3502 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3503 req.fid = rte_cpu_to_le_16(0xffff);
3504 req.enables = rte_cpu_to_le_32(enables);
3506 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3508 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3510 HWRM_CHECK_RESULT();
3516 /* min values are the guaranteed resources and max values are subject
3517 * to availability. The strategy for now is to keep both min & max
3521 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3522 struct hwrm_func_vf_resource_cfg_input *req,
3525 req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3527 req->min_rsscos_ctx = req->max_rsscos_ctx;
3528 req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3529 req->min_stat_ctx = req->max_stat_ctx;
3530 req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3532 req->min_cmpl_rings = req->max_cmpl_rings;
3533 req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3534 req->min_tx_rings = req->max_tx_rings;
3535 req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3536 req->min_rx_rings = req->max_rx_rings;
3537 req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3538 req->min_l2_ctxs = req->max_l2_ctxs;
3539 /* TODO: For now, do not support VMDq/RFS on VFs. */
3540 req->max_vnics = rte_cpu_to_le_16(1);
3541 req->min_vnics = req->max_vnics;
3542 req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3544 req->min_hw_ring_grps = req->max_hw_ring_grps;
3546 rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3550 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3551 struct hwrm_func_cfg_input *req,
3554 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3555 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3556 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3557 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3558 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3559 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3560 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3561 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3562 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3563 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3565 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3566 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3568 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3569 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3571 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3572 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3574 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3575 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3576 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3577 /* TODO: For now, do not support VMDq/RFS on VFs. */
3578 req->num_vnics = rte_cpu_to_le_16(1);
3579 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3583 /* Update the port wide resource values based on how many resources
3584 * got allocated to the VF.
3586 static int bnxt_update_max_resources(struct bnxt *bp,
3589 struct hwrm_func_qcfg_input req = {0};
3590 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3593 /* Get the actual allocated values now */
3594 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3595 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3596 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3597 HWRM_CHECK_RESULT();
3599 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3600 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3601 bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3602 bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3603 bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3604 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3605 bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3612 /* Update the PF resource values based on how many resources
3613 * got allocated to it.
3615 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3617 struct hwrm_func_qcfg_input req = {0};
3618 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3621 /* Get the actual allocated values now */
3622 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3623 req.fid = rte_cpu_to_le_16(0xffff);
3624 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3625 HWRM_CHECK_RESULT();
3627 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3628 bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3629 bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3630 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3631 bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3632 bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3633 bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3634 bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3641 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3643 struct hwrm_func_qcfg_input req = {0};
3644 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3647 /* Check for zero MAC address */
3648 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3649 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3650 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3651 HWRM_CHECK_RESULT();
3652 rc = rte_le_to_cpu_16(resp->vlan);
3659 static int bnxt_query_pf_resources(struct bnxt *bp,
3660 struct bnxt_pf_resource_info *pf_resc)
3662 struct hwrm_func_qcfg_input req = {0};
3663 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3666 /* And copy the allocated numbers into the pf struct */
3667 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3668 req.fid = rte_cpu_to_le_16(0xffff);
3669 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3670 HWRM_CHECK_RESULT();
3672 pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3673 pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3674 pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3675 pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3676 pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3677 pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3678 pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3679 bp->pf->evb_mode = resp->evb_mode;
3687 bnxt_calculate_pf_resources(struct bnxt *bp,
3688 struct bnxt_pf_resource_info *pf_resc,
3692 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3693 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3694 pf_resc->num_cp_rings = bp->max_cp_rings;
3695 pf_resc->num_tx_rings = bp->max_tx_rings;
3696 pf_resc->num_rx_rings = bp->max_rx_rings;
3697 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3698 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3703 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3704 bp->max_rsscos_ctx % (num_vfs + 1);
3705 pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3706 bp->max_stat_ctx % (num_vfs + 1);
3707 pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3708 bp->max_cp_rings % (num_vfs + 1);
3709 pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3710 bp->max_tx_rings % (num_vfs + 1);
3711 pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3712 bp->max_rx_rings % (num_vfs + 1);
3713 pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3714 bp->max_l2_ctx % (num_vfs + 1);
3715 pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3716 bp->max_ring_grps % (num_vfs + 1);
3719 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3721 struct bnxt_pf_resource_info pf_resc = { 0 };
3725 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3729 rc = bnxt_hwrm_func_qcaps(bp);
3733 bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3735 bp->pf->func_cfg_flags &=
3736 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3737 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3738 bp->pf->func_cfg_flags |=
3739 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3741 rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3745 rc = bnxt_update_max_resources_pf_only(bp);
3751 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3753 size_t req_buf_sz, sz;
3756 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3757 bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3758 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3759 if (bp->pf->vf_req_buf == NULL) {
3763 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3764 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3766 for (i = 0; i < num_vfs; i++)
3767 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3768 (i * HWRM_MAX_REQ_LEN);
3770 rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3772 rte_free(bp->pf->vf_req_buf);
3778 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3780 struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3781 struct hwrm_func_vf_resource_cfg_input req = {0};
3784 bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3785 bp->pf->active_vfs = 0;
3786 for (i = 0; i < num_vfs; i++) {
3787 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3788 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3789 rc = bnxt_hwrm_send_message(bp,
3793 if (rc || resp->error_code) {
3795 "Failed to initialize VF %d\n", i);
3797 "Not all VFs available. (%d, %d)\n",
3798 rc, resp->error_code);
3801 /* If the first VF configuration itself fails,
3802 * unregister the vf_fwd_request buffer.
3805 bnxt_hwrm_func_buf_unrgtr(bp);
3810 /* Update the max resource values based on the resource values
3811 * allocated to the VF.
3813 bnxt_update_max_resources(bp, i);
3814 bp->pf->active_vfs++;
3815 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3822 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3824 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3825 struct hwrm_func_cfg_input req = {0};
3828 bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3830 bp->pf->active_vfs = 0;
3831 for (i = 0; i < num_vfs; i++) {
3832 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3833 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3834 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3835 rc = bnxt_hwrm_send_message(bp,
3840 /* Clear enable flag for next pass */
3841 req.enables &= ~rte_cpu_to_le_32(
3842 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3844 if (rc || resp->error_code) {
3846 "Failed to initialize VF %d\n", i);
3848 "Not all VFs available. (%d, %d)\n",
3849 rc, resp->error_code);
3852 /* If the first VF configuration itself fails,
3853 * unregister the vf_fwd_request buffer.
3856 bnxt_hwrm_func_buf_unrgtr(bp);
3862 /* Update the max resource values based on the resource values
3863 * allocated to the VF.
3865 bnxt_update_max_resources(bp, i);
3866 bp->pf->active_vfs++;
3867 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3874 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3876 if (bp->flags & BNXT_FLAG_NEW_RM)
3877 bnxt_process_vf_resc_config_new(bp, num_vfs);
3879 bnxt_process_vf_resc_config_old(bp, num_vfs);
3883 bnxt_update_pf_resources(struct bnxt *bp,
3884 struct bnxt_pf_resource_info *pf_resc)
3886 bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3887 bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3888 bp->max_cp_rings = pf_resc->num_cp_rings;
3889 bp->max_tx_rings = pf_resc->num_tx_rings;
3890 bp->max_rx_rings = pf_resc->num_rx_rings;
3891 bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3895 bnxt_configure_pf_resources(struct bnxt *bp,
3896 struct bnxt_pf_resource_info *pf_resc)
3899 * We're using STD_TX_RING_MODE here which will limit the TX
3900 * rings. This will allow QoS to function properly. Not setting this
3901 * will cause PF rings to break bandwidth settings.
3903 bp->pf->func_cfg_flags &=
3904 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3905 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3906 bp->pf->func_cfg_flags |=
3907 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3908 return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3911 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3913 struct bnxt_pf_resource_info pf_resc = { 0 };
3917 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3921 rc = bnxt_hwrm_func_qcaps(bp);
3925 bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3927 rc = bnxt_configure_pf_resources(bp, &pf_resc);
3931 rc = bnxt_query_pf_resources(bp, &pf_resc);
3936 * Now, create and register a buffer to hold forwarded VF requests
3938 rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3942 bnxt_configure_vf_resources(bp, num_vfs);
3944 bnxt_update_pf_resources(bp, &pf_resc);
3949 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3951 struct hwrm_func_cfg_input req = {0};
3952 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3955 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3957 req.fid = rte_cpu_to_le_16(0xffff);
3958 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3959 req.evb_mode = bp->pf->evb_mode;
3961 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3962 HWRM_CHECK_RESULT();
3968 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3969 uint8_t tunnel_type)
3971 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3972 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3975 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3976 req.tunnel_type = tunnel_type;
3977 req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3978 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3979 HWRM_CHECK_RESULT();
3981 switch (tunnel_type) {
3982 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3983 bp->vxlan_fw_dst_port_id =
3984 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3985 bp->vxlan_port = port;
3987 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3988 bp->geneve_fw_dst_port_id =
3989 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3990 bp->geneve_port = port;
4001 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
4002 uint8_t tunnel_type)
4004 struct hwrm_tunnel_dst_port_free_input req = {0};
4005 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
4008 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
4010 req.tunnel_type = tunnel_type;
4011 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
4012 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4014 HWRM_CHECK_RESULT();
4018 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4020 bp->vxlan_port_cnt = 0;
4024 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4025 bp->geneve_port = 0;
4026 bp->geneve_port_cnt = 0;
4032 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4035 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4036 struct hwrm_func_cfg_input req = {0};
4039 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4041 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4042 req.flags = rte_cpu_to_le_32(flags);
4043 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4045 HWRM_CHECK_RESULT();
4051 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4053 uint32_t *flag = flagp;
4055 vnic->flags = *flag;
4058 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4060 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4063 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4065 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4066 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4069 HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4071 req.req_buf_num_pages = rte_cpu_to_le_16(1);
4072 req.req_buf_page_size =
4073 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4074 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4075 req.req_buf_page_addr0 =
4076 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4077 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4079 "unable to map buffer address to physical memory\n");
4084 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4086 HWRM_CHECK_RESULT();
4092 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4095 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4096 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4098 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4101 HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4103 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4105 HWRM_CHECK_RESULT();
4111 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4113 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4114 struct hwrm_func_cfg_input req = {0};
4117 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4119 req.fid = rte_cpu_to_le_16(0xffff);
4120 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4121 req.enables = rte_cpu_to_le_32(
4122 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4123 req.async_event_cr = rte_cpu_to_le_16(
4124 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4125 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4127 HWRM_CHECK_RESULT();
4133 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4135 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4136 struct hwrm_func_vf_cfg_input req = {0};
4139 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4141 req.enables = rte_cpu_to_le_32(
4142 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4143 req.async_event_cr = rte_cpu_to_le_16(
4144 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4145 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4147 HWRM_CHECK_RESULT();
4153 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4155 struct hwrm_func_cfg_input req = {0};
4156 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4157 uint16_t dflt_vlan, fid;
4158 uint32_t func_cfg_flags;
4161 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4164 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4165 fid = bp->pf->vf_info[vf].fid;
4166 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4168 fid = rte_cpu_to_le_16(0xffff);
4169 func_cfg_flags = bp->pf->func_cfg_flags;
4170 dflt_vlan = bp->vlan;
4173 req.flags = rte_cpu_to_le_32(func_cfg_flags);
4174 req.fid = rte_cpu_to_le_16(fid);
4175 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4176 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4178 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4180 HWRM_CHECK_RESULT();
4186 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4187 uint16_t max_bw, uint16_t enables)
4189 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4190 struct hwrm_func_cfg_input req = {0};
4193 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4195 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4196 req.enables |= rte_cpu_to_le_32(enables);
4197 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4198 req.max_bw = rte_cpu_to_le_32(max_bw);
4199 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4201 HWRM_CHECK_RESULT();
4207 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4209 struct hwrm_func_cfg_input req = {0};
4210 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4213 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4215 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4216 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4217 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4218 req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4220 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4222 HWRM_CHECK_RESULT();
4228 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4233 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4235 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4240 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4241 void *encaped, size_t ec_size)
4244 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4245 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4247 if (ec_size > sizeof(req.encap_request))
4250 HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4252 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4253 memcpy(req.encap_request, encaped, ec_size);
4255 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4257 HWRM_CHECK_RESULT();
4263 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4264 struct rte_ether_addr *mac)
4266 struct hwrm_func_qcfg_input req = {0};
4267 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4270 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4272 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4273 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4275 HWRM_CHECK_RESULT();
4277 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4284 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4285 void *encaped, size_t ec_size)
4288 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4289 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4291 if (ec_size > sizeof(req.encap_request))
4294 HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4296 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4297 memcpy(req.encap_request, encaped, ec_size);
4299 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4301 HWRM_CHECK_RESULT();
4307 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
4308 struct rte_eth_stats *stats, uint8_t rx)
4311 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4312 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4314 HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4316 req.stat_ctx_id = rte_cpu_to_le_32(cid);
4318 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4320 HWRM_CHECK_RESULT();
4323 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4324 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
4325 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
4326 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4327 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
4328 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
4329 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_discard_pkts);
4330 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_error_pkts);
4332 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4333 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
4334 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
4335 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4336 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
4337 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
4345 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4347 struct hwrm_port_qstats_input req = {0};
4348 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4349 struct bnxt_pf_info *pf = bp->pf;
4352 HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4354 req.port_id = rte_cpu_to_le_16(pf->port_id);
4355 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4356 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4359 HWRM_CHECK_RESULT();
4365 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4367 struct hwrm_port_clr_stats_input req = {0};
4368 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4369 struct bnxt_pf_info *pf = bp->pf;
4372 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4373 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4374 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4377 HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4379 req.port_id = rte_cpu_to_le_16(pf->port_id);
4380 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4382 HWRM_CHECK_RESULT();
4388 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4390 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4391 struct hwrm_port_led_qcaps_input req = {0};
4397 HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4398 req.port_id = bp->pf->port_id;
4399 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4401 HWRM_CHECK_RESULT_SILENT();
4403 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4406 bp->leds->num_leds = resp->num_leds;
4407 memcpy(bp->leds, &resp->led0_id,
4408 sizeof(bp->leds[0]) * bp->leds->num_leds);
4409 for (i = 0; i < bp->leds->num_leds; i++) {
4410 struct bnxt_led_info *led = &bp->leds[i];
4412 uint16_t caps = led->led_state_caps;
4414 if (!led->led_group_id ||
4415 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4416 bp->leds->num_leds = 0;
4427 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4429 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4430 struct hwrm_port_led_cfg_input req = {0};
4431 struct bnxt_led_cfg *led_cfg;
4432 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4433 uint16_t duration = 0;
4436 if (!bp->leds->num_leds || BNXT_VF(bp))
4439 HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4442 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4443 duration = rte_cpu_to_le_16(500);
4445 req.port_id = bp->pf->port_id;
4446 req.num_leds = bp->leds->num_leds;
4447 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4448 for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4449 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4450 led_cfg->led_id = bp->leds[i].led_id;
4451 led_cfg->led_state = led_state;
4452 led_cfg->led_blink_on = duration;
4453 led_cfg->led_blink_off = duration;
4454 led_cfg->led_group_id = bp->leds[i].led_group_id;
4457 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4459 HWRM_CHECK_RESULT();
4465 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4469 struct hwrm_nvm_get_dir_info_input req = {0};
4470 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4472 HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4474 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4476 HWRM_CHECK_RESULT();
4478 *entries = rte_le_to_cpu_32(resp->entries);
4479 *length = rte_le_to_cpu_32(resp->entry_length);
4485 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4488 uint32_t dir_entries;
4489 uint32_t entry_length;
4492 rte_iova_t dma_handle;
4493 struct hwrm_nvm_get_dir_entries_input req = {0};
4494 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4496 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4500 *data++ = dir_entries;
4501 *data++ = entry_length;
4503 memset(data, 0xff, len);
4505 buflen = dir_entries * entry_length;
4506 buf = rte_malloc("nvm_dir", buflen, 0);
4509 dma_handle = rte_malloc_virt2iova(buf);
4510 if (dma_handle == RTE_BAD_IOVA) {
4513 "unable to map response address to physical memory\n");
4516 HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4517 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4518 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4521 memcpy(data, buf, len > buflen ? buflen : len);
4524 HWRM_CHECK_RESULT();
4530 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4531 uint32_t offset, uint32_t length,
4536 rte_iova_t dma_handle;
4537 struct hwrm_nvm_read_input req = {0};
4538 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4540 buf = rte_malloc("nvm_item", length, 0);
4544 dma_handle = rte_malloc_virt2iova(buf);
4545 if (dma_handle == RTE_BAD_IOVA) {
4548 "unable to map response address to physical memory\n");
4551 HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4552 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4553 req.dir_idx = rte_cpu_to_le_16(index);
4554 req.offset = rte_cpu_to_le_32(offset);
4555 req.len = rte_cpu_to_le_32(length);
4556 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4558 memcpy(data, buf, length);
4561 HWRM_CHECK_RESULT();
4567 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4570 struct hwrm_nvm_erase_dir_entry_input req = {0};
4571 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4573 HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4574 req.dir_idx = rte_cpu_to_le_16(index);
4575 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4576 HWRM_CHECK_RESULT();
4583 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4584 uint16_t dir_ordinal, uint16_t dir_ext,
4585 uint16_t dir_attr, const uint8_t *data,
4589 struct hwrm_nvm_write_input req = {0};
4590 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4591 rte_iova_t dma_handle;
4594 buf = rte_malloc("nvm_write", data_len, 0);
4598 dma_handle = rte_malloc_virt2iova(buf);
4599 if (dma_handle == RTE_BAD_IOVA) {
4602 "unable to map response address to physical memory\n");
4605 memcpy(buf, data, data_len);
4607 HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4609 req.dir_type = rte_cpu_to_le_16(dir_type);
4610 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4611 req.dir_ext = rte_cpu_to_le_16(dir_ext);
4612 req.dir_attr = rte_cpu_to_le_16(dir_attr);
4613 req.dir_data_length = rte_cpu_to_le_32(data_len);
4614 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4616 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4619 HWRM_CHECK_RESULT();
4626 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4628 uint32_t *count = cbdata;
4630 *count = *count + 1;
4633 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4634 struct bnxt_vnic_info *vnic __rte_unused)
4639 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4643 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4644 &count, bnxt_vnic_count_hwrm_stub);
4649 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4652 struct hwrm_func_vf_vnic_ids_query_input req = {0};
4653 struct hwrm_func_vf_vnic_ids_query_output *resp =
4654 bp->hwrm_cmd_resp_addr;
4657 /* First query all VNIC ids */
4658 HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4660 req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4661 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4662 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4664 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4667 "unable to map VNIC ID table address to physical memory\n");
4670 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4671 HWRM_CHECK_RESULT();
4672 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4680 * This function queries the VNIC IDs for a specified VF. It then calls
4681 * the vnic_cb to update the necessary field in vnic_info with cbdata.
4682 * Then it calls the hwrm_cb function to program this new vnic configuration.
4684 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4685 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4686 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4688 struct bnxt_vnic_info vnic;
4690 int i, num_vnic_ids;
4695 /* First query all VNIC ids */
4696 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4697 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4698 RTE_CACHE_LINE_SIZE);
4699 if (vnic_ids == NULL)
4702 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4703 rte_mem_lock_page(((char *)vnic_ids) + sz);
4705 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4707 if (num_vnic_ids < 0)
4708 return num_vnic_ids;
4710 /* Retrieve VNIC, update bd_stall then update */
4712 for (i = 0; i < num_vnic_ids; i++) {
4713 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4714 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4715 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4718 if (vnic.mru <= 4) /* Indicates unallocated */
4721 vnic_cb(&vnic, cbdata);
4723 rc = hwrm_cb(bp, &vnic);
4733 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4736 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4737 struct hwrm_func_cfg_input req = {0};
4740 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4742 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4743 req.enables |= rte_cpu_to_le_32(
4744 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4745 req.vlan_antispoof_mode = on ?
4746 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4747 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4748 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4750 HWRM_CHECK_RESULT();
4756 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4758 struct bnxt_vnic_info vnic;
4761 int num_vnic_ids, i;
4765 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4766 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4767 RTE_CACHE_LINE_SIZE);
4768 if (vnic_ids == NULL)
4771 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4772 rte_mem_lock_page(((char *)vnic_ids) + sz);
4774 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4780 * Loop through to find the default VNIC ID.
4781 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4782 * by sending the hwrm_func_qcfg command to the firmware.
4784 for (i = 0; i < num_vnic_ids; i++) {
4785 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4786 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4787 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4788 bp->pf->first_vf_id + vf);
4791 if (vnic.func_default) {
4793 return vnic.fw_vnic_id;
4796 /* Could not find a default VNIC. */
4797 PMD_DRV_LOG(ERR, "No default VNIC\n");
4803 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4805 struct bnxt_filter_info *filter)
4808 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4809 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4810 uint32_t enables = 0;
4812 if (filter->fw_em_filter_id != UINT64_MAX)
4813 bnxt_hwrm_clear_em_filter(bp, filter);
4815 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4817 req.flags = rte_cpu_to_le_32(filter->flags);
4819 enables = filter->enables |
4820 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4821 req.dst_id = rte_cpu_to_le_16(dst_id);
4823 if (filter->ip_addr_type) {
4824 req.ip_addr_type = filter->ip_addr_type;
4825 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4828 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4829 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4831 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4832 memcpy(req.src_macaddr, filter->src_macaddr,
4833 RTE_ETHER_ADDR_LEN);
4835 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4836 memcpy(req.dst_macaddr, filter->dst_macaddr,
4837 RTE_ETHER_ADDR_LEN);
4839 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4840 req.ovlan_vid = filter->l2_ovlan;
4842 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4843 req.ivlan_vid = filter->l2_ivlan;
4845 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4846 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4848 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4849 req.ip_protocol = filter->ip_protocol;
4851 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4852 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4854 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4855 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4857 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4858 req.src_port = rte_cpu_to_be_16(filter->src_port);
4860 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4861 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4863 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4864 req.mirror_vnic_id = filter->mirror_vnic_id;
4866 req.enables = rte_cpu_to_le_32(enables);
4868 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4870 HWRM_CHECK_RESULT();
4872 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4878 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4881 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4882 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4884 if (filter->fw_em_filter_id == UINT64_MAX)
4887 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4889 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4891 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4893 HWRM_CHECK_RESULT();
4896 filter->fw_em_filter_id = UINT64_MAX;
4897 filter->fw_l2_filter_id = UINT64_MAX;
4902 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4904 struct bnxt_filter_info *filter)
4907 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4908 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4909 bp->hwrm_cmd_resp_addr;
4910 uint32_t enables = 0;
4912 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4913 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4915 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4917 req.flags = rte_cpu_to_le_32(filter->flags);
4919 enables = filter->enables |
4920 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4921 req.dst_id = rte_cpu_to_le_16(dst_id);
4923 if (filter->ip_addr_type) {
4924 req.ip_addr_type = filter->ip_addr_type;
4926 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4929 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4930 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4932 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4933 memcpy(req.src_macaddr, filter->src_macaddr,
4934 RTE_ETHER_ADDR_LEN);
4936 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4937 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4939 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4940 req.ip_protocol = filter->ip_protocol;
4942 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4943 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4945 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4946 req.src_ipaddr_mask[0] =
4947 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4949 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4950 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4952 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4953 req.dst_ipaddr_mask[0] =
4954 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4956 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4957 req.src_port = rte_cpu_to_le_16(filter->src_port);
4959 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4960 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4962 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4963 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4965 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4966 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4968 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4969 req.mirror_vnic_id = filter->mirror_vnic_id;
4971 req.enables = rte_cpu_to_le_32(enables);
4973 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4975 HWRM_CHECK_RESULT();
4977 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4978 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4984 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4985 struct bnxt_filter_info *filter)
4988 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4989 struct hwrm_cfa_ntuple_filter_free_output *resp =
4990 bp->hwrm_cmd_resp_addr;
4992 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4995 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4997 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4999 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5001 HWRM_CHECK_RESULT();
5004 filter->fw_ntuple_filter_id = UINT64_MAX;
5010 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5012 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5013 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
5014 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
5015 struct bnxt_rx_queue **rxqs = bp->rx_queues;
5016 uint16_t *ring_tbl = vnic->rss_table;
5017 int nr_ctxs = vnic->num_lb_ctxts;
5018 int max_rings = bp->rx_nr_rings;
5022 for (i = 0, k = 0; i < nr_ctxs; i++) {
5023 struct bnxt_rx_ring_info *rxr;
5024 struct bnxt_cp_ring_info *cpr;
5026 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5028 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5029 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5030 req.hash_mode_flags = vnic->hash_mode;
5032 req.ring_grp_tbl_addr =
5033 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5034 i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5035 2 * sizeof(*ring_tbl));
5036 req.hash_key_tbl_addr =
5037 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5039 req.ring_table_pair_index = i;
5040 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5042 for (j = 0; j < 64; j++) {
5045 /* Find next active ring. */
5046 for (cnt = 0; cnt < max_rings; cnt++) {
5047 if (rx_queue_state[k] !=
5048 RTE_ETH_QUEUE_STATE_STOPPED)
5050 if (++k == max_rings)
5054 /* Return if no rings are active. */
5055 if (cnt == max_rings) {
5060 /* Add rx/cp ring pair to RSS table. */
5061 rxr = rxqs[k]->rx_ring;
5062 cpr = rxqs[k]->cp_ring;
5064 ring_id = rxr->rx_ring_struct->fw_ring_id;
5065 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5066 ring_id = cpr->cp_ring_struct->fw_ring_id;
5067 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5069 if (++k == max_rings)
5072 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5075 HWRM_CHECK_RESULT();
5082 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5084 unsigned int rss_idx, fw_idx, i;
5086 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5089 if (!(vnic->rss_table && vnic->hash_type))
5092 if (BNXT_CHIP_P5(bp))
5093 return bnxt_vnic_rss_configure_p5(bp, vnic);
5096 * Fill the RSS hash & redirection table with
5097 * ring group ids for all VNICs
5099 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5100 rss_idx++, fw_idx++) {
5101 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5102 fw_idx %= bp->rx_cp_nr_rings;
5103 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5108 if (i == bp->rx_cp_nr_rings)
5111 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5114 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5117 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5118 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5122 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5124 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5125 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5127 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5128 req->num_cmpl_dma_aggr_during_int =
5129 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5131 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5133 /* min timer set to 1/2 of interrupt timer */
5134 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5136 /* buf timer set to 1/4 of interrupt timer */
5137 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5139 req->cmpl_aggr_dma_tmr_during_int =
5140 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5142 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5143 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5144 req->flags = rte_cpu_to_le_16(flags);
5147 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5148 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5150 struct hwrm_ring_aggint_qcaps_input req = {0};
5151 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5156 HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5157 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5158 HWRM_CHECK_RESULT();
5160 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5161 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5163 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5164 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5165 agg_req->flags = rte_cpu_to_le_16(flags);
5167 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5168 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5169 agg_req->enables = rte_cpu_to_le_32(enables);
5175 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5176 struct bnxt_coal *coal, uint16_t ring_id)
5178 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5179 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5180 bp->hwrm_cmd_resp_addr;
5183 /* Set ring coalesce parameters only for 100G NICs */
5184 if (BNXT_CHIP_P5(bp)) {
5185 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5187 } else if (bnxt_stratus_device(bp)) {
5188 bnxt_hwrm_set_coal_params(coal, &req);
5194 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5196 req.ring_id = rte_cpu_to_le_16(ring_id);
5197 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5198 HWRM_CHECK_RESULT();
5203 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5204 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5206 struct hwrm_func_backing_store_qcaps_input req = {0};
5207 struct hwrm_func_backing_store_qcaps_output *resp =
5208 bp->hwrm_cmd_resp_addr;
5209 struct bnxt_ctx_pg_info *ctx_pg;
5210 struct bnxt_ctx_mem_info *ctx;
5211 int total_alloc_len;
5212 int rc, i, tqm_rings;
5214 if (!BNXT_CHIP_P5(bp) ||
5215 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5220 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5221 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5222 HWRM_CHECK_RESULT_SILENT();
5224 total_alloc_len = sizeof(*ctx);
5225 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5226 RTE_CACHE_LINE_SIZE);
5232 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5233 ctx->qp_min_qp1_entries =
5234 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5235 ctx->qp_max_l2_entries =
5236 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5237 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5238 ctx->srq_max_l2_entries =
5239 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5240 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5241 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5242 ctx->cq_max_l2_entries =
5243 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5244 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5245 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5246 ctx->vnic_max_vnic_entries =
5247 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5248 ctx->vnic_max_ring_table_entries =
5249 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5250 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5251 ctx->stat_max_entries =
5252 rte_le_to_cpu_32(resp->stat_max_entries);
5253 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5254 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5255 ctx->tqm_min_entries_per_ring =
5256 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5257 ctx->tqm_max_entries_per_ring =
5258 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5259 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5260 if (!ctx->tqm_entries_multiple)
5261 ctx->tqm_entries_multiple = 1;
5262 ctx->mrav_max_entries =
5263 rte_le_to_cpu_32(resp->mrav_max_entries);
5264 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5265 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5266 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5267 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5269 ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5270 RTE_MIN(ctx->tqm_fp_rings_count,
5271 BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5274 /* Check if the ext ring count needs to be counted.
5275 * Ext ring count is available only with new FW so we should not
5276 * look at the field on older FW.
5278 if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5279 bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5280 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5281 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5282 ctx->tqm_fp_rings_count);
5285 tqm_rings = ctx->tqm_fp_rings_count + 1;
5287 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5288 sizeof(*ctx_pg) * tqm_rings,
5289 RTE_CACHE_LINE_SIZE);
5294 for (i = 0; i < tqm_rings; i++, ctx_pg++)
5295 ctx->tqm_mem[i] = ctx_pg;
5303 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5305 struct hwrm_func_backing_store_cfg_input req = {0};
5306 struct hwrm_func_backing_store_cfg_output *resp =
5307 bp->hwrm_cmd_resp_addr;
5308 struct bnxt_ctx_mem_info *ctx = bp->ctx;
5309 struct bnxt_ctx_pg_info *ctx_pg;
5310 uint32_t *num_entries;
5319 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5320 req.enables = rte_cpu_to_le_32(enables);
5322 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5323 ctx_pg = &ctx->qp_mem;
5324 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5325 req.qp_num_qp1_entries =
5326 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5327 req.qp_num_l2_entries =
5328 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5329 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5330 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5331 &req.qpc_pg_size_qpc_lvl,
5335 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5336 ctx_pg = &ctx->srq_mem;
5337 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5338 req.srq_num_l2_entries =
5339 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5340 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5341 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5342 &req.srq_pg_size_srq_lvl,
5346 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5347 ctx_pg = &ctx->cq_mem;
5348 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5349 req.cq_num_l2_entries =
5350 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5351 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5352 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5353 &req.cq_pg_size_cq_lvl,
5357 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5358 ctx_pg = &ctx->vnic_mem;
5359 req.vnic_num_vnic_entries =
5360 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5361 req.vnic_num_ring_table_entries =
5362 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5363 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5364 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5365 &req.vnic_pg_size_vnic_lvl,
5366 &req.vnic_page_dir);
5369 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5370 ctx_pg = &ctx->stat_mem;
5371 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5372 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5373 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5374 &req.stat_pg_size_stat_lvl,
5375 &req.stat_page_dir);
5378 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5379 num_entries = &req.tqm_sp_num_entries;
5380 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5381 pg_dir = &req.tqm_sp_page_dir;
5382 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5383 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5384 if (!(enables & ena))
5387 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5389 ctx_pg = ctx->tqm_mem[i];
5390 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5391 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5394 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5395 /* DPDK does not need to configure MRAV and TIM type.
5396 * So we are skipping over MRAV and TIM. Skip to configure
5397 * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5399 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5400 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5401 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5402 &req.tqm_ring8_pg_size_tqm_ring_lvl,
5403 &req.tqm_ring8_page_dir);
5406 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5407 HWRM_CHECK_RESULT();
5413 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5415 struct hwrm_port_qstats_ext_input req = {0};
5416 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5417 struct bnxt_pf_info *pf = bp->pf;
5420 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5421 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5424 HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5426 req.port_id = rte_cpu_to_le_16(pf->port_id);
5427 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5428 req.tx_stat_host_addr =
5429 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5431 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5433 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5434 req.rx_stat_host_addr =
5435 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5437 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5439 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5442 bp->fw_rx_port_stats_ext_size = 0;
5443 bp->fw_tx_port_stats_ext_size = 0;
5445 bp->fw_rx_port_stats_ext_size =
5446 rte_le_to_cpu_16(resp->rx_stat_size);
5447 bp->fw_tx_port_stats_ext_size =
5448 rte_le_to_cpu_16(resp->tx_stat_size);
5451 HWRM_CHECK_RESULT();
5458 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5460 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5461 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5462 bp->hwrm_cmd_resp_addr;
5465 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5466 req.tunnel_type = type;
5467 req.dest_fid = bp->fw_fid;
5468 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5469 HWRM_CHECK_RESULT();
5477 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5479 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5480 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5481 bp->hwrm_cmd_resp_addr;
5484 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5485 req.tunnel_type = type;
5486 req.dest_fid = bp->fw_fid;
5487 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5488 HWRM_CHECK_RESULT();
5495 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5497 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5498 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5499 bp->hwrm_cmd_resp_addr;
5502 HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5503 req.src_fid = bp->fw_fid;
5504 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5505 HWRM_CHECK_RESULT();
5508 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5515 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5518 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5519 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5520 bp->hwrm_cmd_resp_addr;
5523 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5524 req.src_fid = bp->fw_fid;
5525 req.tunnel_type = tun_type;
5526 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5527 HWRM_CHECK_RESULT();
5530 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5532 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5539 int bnxt_hwrm_set_mac(struct bnxt *bp)
5541 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5542 struct hwrm_func_vf_cfg_input req = {0};
5548 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5551 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5552 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5554 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5556 HWRM_CHECK_RESULT();
5563 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5565 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5566 struct hwrm_func_drv_if_change_input req = {0};
5570 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5573 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5574 * If we issue FUNC_DRV_IF_CHANGE with flags down before
5575 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5577 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5580 HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5584 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5586 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5588 HWRM_CHECK_RESULT();
5589 flags = rte_le_to_cpu_32(resp->flags);
5595 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5596 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5597 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5603 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5605 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5606 struct bnxt_error_recovery_info *info = bp->recovery_info;
5607 struct hwrm_error_recovery_qcfg_input req = {0};
5612 /* Older FW does not have error recovery support */
5613 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5616 HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5618 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5620 HWRM_CHECK_RESULT();
5622 flags = rte_le_to_cpu_32(resp->flags);
5623 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5624 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5625 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5626 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5628 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5629 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5634 /* FW returned values are in units of 100msec */
5635 info->driver_polling_freq =
5636 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5637 info->master_func_wait_period =
5638 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5639 info->normal_func_wait_period =
5640 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5641 info->master_func_wait_period_after_reset =
5642 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5643 info->max_bailout_time_after_reset =
5644 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5645 info->status_regs[BNXT_FW_STATUS_REG] =
5646 rte_le_to_cpu_32(resp->fw_health_status_reg);
5647 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5648 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5649 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5650 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5651 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5652 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5653 info->reg_array_cnt =
5654 rte_le_to_cpu_32(resp->reg_array_cnt);
5656 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5661 for (i = 0; i < info->reg_array_cnt; i++) {
5662 info->reset_reg[i] =
5663 rte_le_to_cpu_32(resp->reset_reg[i]);
5664 info->reset_reg_val[i] =
5665 rte_le_to_cpu_32(resp->reset_reg_val[i]);
5666 info->delay_after_reset[i] =
5667 resp->delay_after_reset[i];
5672 /* Map the FW status registers */
5674 rc = bnxt_map_fw_health_status_regs(bp);
5677 rte_free(bp->recovery_info);
5678 bp->recovery_info = NULL;
5683 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5685 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5686 struct hwrm_fw_reset_input req = {0};
5692 HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5694 req.embedded_proc_type =
5695 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5696 req.selfrst_status =
5697 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5698 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5700 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5703 HWRM_CHECK_RESULT();
5709 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5711 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5712 struct hwrm_port_ts_query_input req = {0};
5713 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5720 HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5723 case BNXT_PTP_FLAGS_PATH_TX:
5724 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5726 case BNXT_PTP_FLAGS_PATH_RX:
5727 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5729 case BNXT_PTP_FLAGS_CURRENT_TIME:
5730 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5734 req.flags = rte_cpu_to_le_32(flags);
5735 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5737 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5739 HWRM_CHECK_RESULT();
5742 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5744 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5751 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5755 struct hwrm_cfa_counter_qcaps_input req = {0};
5756 struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5758 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5760 "Not a PF or trusted VF. Command not supported\n");
5764 HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5765 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5766 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5768 HWRM_CHECK_RESULT();
5770 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5776 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5779 struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5780 struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5782 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5784 "Not a PF or trusted VF. Command not supported\n");
5788 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5790 req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5791 req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5792 req.page_dir = rte_cpu_to_le_64(dma_addr);
5794 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5796 HWRM_CHECK_RESULT();
5798 *ctx_id = rte_le_to_cpu_16(resp->ctx_id);
5799 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5806 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5809 struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5810 struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5812 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5814 "Not a PF or trusted VF. Command not supported\n");
5818 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5820 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5822 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5824 HWRM_CHECK_RESULT();
5830 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5831 uint16_t cntr, uint16_t ctx_id,
5832 uint32_t num_entries, bool enable)
5834 struct hwrm_cfa_counter_cfg_input req = {0};
5835 struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5839 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5841 "Not a PF or trusted VF. Command not supported\n");
5845 HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5847 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5848 req.counter_type = rte_cpu_to_le_16(cntr);
5849 flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5850 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5851 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5852 if (dir == BNXT_DIR_RX)
5853 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5854 else if (dir == BNXT_DIR_TX)
5855 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5856 req.flags = rte_cpu_to_le_16(flags);
5857 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5858 req.num_entries = rte_cpu_to_le_32(num_entries);
5860 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5861 HWRM_CHECK_RESULT();
5867 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5868 enum bnxt_flow_dir dir,
5870 uint16_t num_entries)
5872 struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5873 struct hwrm_cfa_counter_qstats_input req = {0};
5874 uint16_t flow_ctx_id = 0;
5878 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5880 "Not a PF or trusted VF. Command not supported\n");
5884 if (dir == BNXT_DIR_RX) {
5885 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5886 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5887 } else if (dir == BNXT_DIR_TX) {
5888 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5889 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5892 HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5893 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5894 req.counter_type = rte_cpu_to_le_16(cntr);
5895 req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5896 req.num_entries = rte_cpu_to_le_16(num_entries);
5897 req.flags = rte_cpu_to_le_16(flags);
5898 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5900 HWRM_CHECK_RESULT();
5906 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5907 uint16_t *first_vf_id)
5910 struct hwrm_func_qcaps_input req = {.req_type = 0 };
5911 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5913 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5915 req.fid = rte_cpu_to_le_16(fid);
5917 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5919 HWRM_CHECK_RESULT();
5922 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
5929 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
5931 struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5932 struct hwrm_cfa_pair_alloc_input req = {0};
5935 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5937 "Not a PF or trusted VF. Command not supported\n");
5941 HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
5942 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5943 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5944 bp->eth_dev->data->name, rep_bp->vf_id);
5946 req.pf_b_id = rep_bp->parent_pf_idx;
5947 req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5948 rte_cpu_to_le_16(rep_bp->vf_id);
5949 req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
5950 req.host_b_id = 1; /* TBD - Confirm if this is OK */
5952 req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
5953 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
5954 req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
5955 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
5956 req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
5957 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
5958 req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
5959 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
5961 req.q_ab = rep_bp->rep_q_r2f;
5962 req.q_ba = rep_bp->rep_q_f2r;
5963 req.fc_ab = rep_bp->rep_fc_r2f;
5964 req.fc_ba = rep_bp->rep_fc_f2r;
5966 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5967 HWRM_CHECK_RESULT();
5970 PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
5971 BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
5975 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
5977 struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
5978 struct hwrm_cfa_pair_free_input req = {0};
5981 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5983 "Not a PF or trusted VF. Command not supported\n");
5987 HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
5988 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5989 bp->eth_dev->data->name, rep_bp->vf_id);
5990 req.pf_b_id = rep_bp->parent_pf_idx;
5991 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5992 req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5993 rte_cpu_to_le_16(rep_bp->vf_id);
5994 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5995 HWRM_CHECK_RESULT();
5997 PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
6002 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
6004 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
6005 bp->hwrm_cmd_resp_addr;
6006 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
6010 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
6013 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6015 "Not a PF or trusted VF. Command not supported\n");
6019 HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
6020 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6022 HWRM_CHECK_RESULT();
6023 flags = rte_le_to_cpu_32(resp->flags);
6026 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
6027 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
6029 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
6034 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6035 uint32_t echo_req_data2)
6037 struct hwrm_func_echo_response_input req = {0};
6038 struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6041 HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6042 req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6043 req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6045 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6047 HWRM_CHECK_RESULT();
6053 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6055 struct hwrm_ver_get_input req = {.req_type = 0 };
6056 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6059 bp->max_req_len = HWRM_MAX_REQ_LEN;
6060 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6062 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6063 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6064 req.hwrm_intf_min = HWRM_VERSION_MINOR;
6065 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6067 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6069 HWRM_CHECK_RESULT_SILENT();
6071 if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)