drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30 #define HWRM_VERSION_1_10_2_13          0x10a020d
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(int) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages == 0)
  68                 return;
  69
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 static struct bnxt_cp_ring_info*
  79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
  80 {
  81         struct bnxt_cp_ring_info *cp_ring = NULL;
  82         uint16_t i;
  83
  84         switch (type) {
  85         case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
  86         case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
  87                 /* FALLTHROUGH */
  88                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
  89                         struct bnxt_rx_queue *rxq = bp->rx_queues[i];
  90
  91                         if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
  92                             rte_cpu_to_le_16(rid)) {
  93                                 return rxq->cp_ring;
  94                         }
  95                 }
  96                 break;
  97         case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
  98                 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
  99                         struct bnxt_tx_queue *txq = bp->tx_queues[i];
 100
 101                         if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
 102                             rte_cpu_to_le_16(rid)) {
 103                                 return txq->cp_ring;
 104                         }
 105                 }
 106                 break;
 107         default:
 108                 return cp_ring;
 109         }
 110         return cp_ring;
 111 }
 112
 113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
 114  * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
 115  * before timeout, we force the done bit for the cleanup to proceed.
 116  * Also if cpr is null, do nothing.. The HWRM command is  not for a
 117  * Tx/Rx/AGG ring cleanup.
 118  */
 119 static int
 120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
 121                         bool tx, bool rx, bool timeout)
 122 {
 123         int done = 0;
 124
 125         if (cpr != NULL) {
 126                 if (tx)
 127                         done = bnxt_flush_tx_cmp(cpr);
 128
 129                 if (rx)
 130                         done = bnxt_flush_rx_cmp(cpr);
 131
 132                 if (done)
 133                         PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
 134                                     rx ? "Rx" : "Tx");
 135
 136                 /* We are about to timeout and still haven't seen the
 137                  * HWRM done for the Ring free. Force the cleanup.
 138                  */
 139                 if (!done && timeout) {
 140                         done = 1;
 141                         PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
 142                                     rx ? "Rx" : "Tx");
 143                 }
 144         } else {
 145                 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
 146                  * Otherwise the cpr would have been valid. So do nothing.
 147                  */
 148                 done = 1;
 149         }
 150
 151         return done;
 152 }
 153
 154 /*
 155  * HWRM Functions (sent to HWRM)
 156  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
 157  * HWRM command times out, or a negative error code if the HWRM
 158  * command was failed by the FW.
 159  */
 160
 161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
 162                                   uint32_t msg_len, bool use_kong_mb)
 163 {
 164         unsigned int i;
 165         struct input *req = msg;
 166         struct output *resp = bp->hwrm_cmd_resp_addr;
 167         uint32_t *data = msg;
 168         uint8_t *bar;
 169         uint8_t *valid;
 170         uint16_t max_req_len = bp->max_req_len;
 171         struct hwrm_short_input short_input = { 0 };
 172         uint16_t bar_offset = use_kong_mb ?
 173                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
 174         uint16_t mb_trigger_offset = use_kong_mb ?
 175                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 176         struct bnxt_cp_ring_info *cpr = NULL;
 177         bool is_rx = false;
 178         bool is_tx = false;
 179         uint32_t timeout;
 180
 181         /* Do not send HWRM commands to firmware in error state */
 182         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 183                 return 0;
 184
 185         timeout = bp->hwrm_cmd_timeout;
 186
 187         /* Update the message length for backing store config for new FW. */
 188         if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
 189             rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
 190                 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
 191
 192         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 193             msg_len > bp->max_req_len) {
 194                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 195
 196                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 197                 memcpy(short_cmd_req, req, msg_len);
 198
 199                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 200                 short_input.signature = rte_cpu_to_le_16(
 201                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 202                 short_input.size = rte_cpu_to_le_16(msg_len);
 203                 short_input.req_addr =
 204                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 205
 206                 data = (uint32_t *)&short_input;
 207                 msg_len = sizeof(short_input);
 208
 209                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 210         }
 211
 212         /* Write request msg to hwrm channel */
 213         for (i = 0; i < msg_len; i += 4) {
 214                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 215                 rte_write32(*data, bar);
 216                 data++;
 217         }
 218
 219         /* Zero the rest of the request space */
 220         for (; i < max_req_len; i += 4) {
 221                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 222                 rte_write32(0, bar);
 223         }
 224
 225         /* Ring channel doorbell */
 226         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 227         rte_write32(1, bar);
 228         /*
 229          * Make sure the channel doorbell ring command complete before
 230          * reading the response to avoid getting stale or invalid
 231          * responses.
 232          */
 233         rte_io_mb();
 234
 235         /* Check ring flush is done.
 236          * This is valid only for Tx and Rx rings (including AGG rings).
 237          * The Tx and Rx rings should be freed once the HW confirms all
 238          * the internal buffers and BDs associated with the rings are
 239          * consumed and the corresponding DMA is handled.
 240          */
 241         if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
 242                 /* Check if the TxCQ matches. If that fails check if RxCQ
 243                  * matches. And if neither match, is_rx = false, is_tx = false.
 244                  */
 245                 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 246                                                HWRM_RING_FREE_INPUT_RING_TYPE_TX);
 247                 if (cpr == NULL) {
 248                         /* Not a TxCQ. Check if the RxCQ matches. */
 249                         cpr =
 250                         bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 251                                                  HWRM_RING_FREE_INPUT_RING_TYPE_RX);
 252                         if (cpr != NULL)
 253                                 is_rx = true;
 254                 } else {
 255                         is_tx = true;
 256                 }
 257         }
 258
 259         /* Poll for the valid bit */
 260         for (i = 0; i < timeout; i++) {
 261                 int done;
 262
 263                 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
 264                                                i == timeout - 1);
 265                 /* Sanity check on the resp->resp_len */
 266                 rte_io_rmb();
 267                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 268                         /* Last byte of resp contains the valid key */
 269                         valid = (uint8_t *)resp + resp->resp_len - 1;
 270                         if (*valid == HWRM_RESP_VALID_KEY && done)
 271                                 break;
 272                 }
 273                 rte_delay_us(1);
 274         }
 275
 276         if (i >= timeout) {
 277                 /* Suppress VER_GET timeout messages during reset recovery */
 278                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 279                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 280                         return -ETIMEDOUT;
 281
 282                 PMD_DRV_LOG(ERR,
 283                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 284                             req->req_type, req->seq_id);
 285                 return -ETIMEDOUT;
 286         }
 287         return 0;
 288 }
 289
 290 /*
 291  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 292  * spinlock, and does initial processing.
 293  *
 294  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 295  * releases the spinlock only if it returns. If the regular int return codes
 296  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 297  * directly, rather it should be copied and modified to suit the function.
 298  *
 299  * HWRM_UNLOCK() must be called after all response processing is completed.
 300  */
 301 #define HWRM_PREP(req, type, kong) do { \
 302         rte_spinlock_lock(&bp->hwrm_lock); \
 303         if (bp->hwrm_cmd_resp_addr == NULL) { \
 304                 rte_spinlock_unlock(&bp->hwrm_lock); \
 305                 return -EACCES; \
 306         } \
 307         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 308         (req)->req_type = rte_cpu_to_le_16(type); \
 309         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 310         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 311                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 312         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 313         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 314 } while (0)
 315
 316 #define HWRM_CHECK_RESULT_SILENT() do {\
 317         if (rc) { \
 318                 rte_spinlock_unlock(&bp->hwrm_lock); \
 319                 return rc; \
 320         } \
 321         if (resp->error_code) { \
 322                 rc = rte_le_to_cpu_16(resp->error_code); \
 323                 rte_spinlock_unlock(&bp->hwrm_lock); \
 324                 return rc; \
 325         } \
 326 } while (0)
 327
 328 #define HWRM_CHECK_RESULT() do {\
 329         if (rc) { \
 330                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 331                 rte_spinlock_unlock(&bp->hwrm_lock); \
 332                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 333                         rc = -EACCES; \
 334                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 335                         rc = -ENOSPC; \
 336                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 337                         rc = -EINVAL; \
 338                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 339                         rc = -ENOTSUP; \
 340                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 341                         rc = -EAGAIN; \
 342                 else if (rc > 0) \
 343                         rc = -EIO; \
 344                 return rc; \
 345         } \
 346         if (resp->error_code) { \
 347                 rc = rte_le_to_cpu_16(resp->error_code); \
 348                 if (resp->resp_len >= 16) { \
 349                         struct hwrm_err_output *tmp_hwrm_err_op = \
 350                                                 (void *)resp; \
 351                         PMD_DRV_LOG(ERR, \
 352                                 "error %d:%d:%08x:%04x\n", \
 353                                 rc, tmp_hwrm_err_op->cmd_err, \
 354                                 rte_le_to_cpu_32(\
 355                                         tmp_hwrm_err_op->opaque_0), \
 356                                 rte_le_to_cpu_16(\
 357                                         tmp_hwrm_err_op->opaque_1)); \
 358                 } else { \
 359                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 360                 } \
 361                 rte_spinlock_unlock(&bp->hwrm_lock); \
 362                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 363                         rc = -EACCES; \
 364                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 365                         rc = -ENOSPC; \
 366                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 367                         rc = -EINVAL; \
 368                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 369                         rc = -ENOTSUP; \
 370                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 371                         rc = -EAGAIN; \
 372                 else if (rc > 0) \
 373                         rc = -EIO; \
 374                 return rc; \
 375         } \
 376 } while (0)
 377
 378 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 379
 380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 381                                 bool use_kong_mb,
 382                                 uint16_t msg_type,
 383                                 void *msg,
 384                                 uint32_t msg_len,
 385                                 void *resp_msg,
 386                                 uint32_t resp_len)
 387 {
 388         int rc = 0;
 389         bool mailbox = BNXT_USE_CHIMP_MB;
 390         struct input *req = msg;
 391         struct output *resp = bp->hwrm_cmd_resp_addr;
 392
 393         if (use_kong_mb)
 394                 mailbox = BNXT_USE_KONG(bp);
 395
 396         HWRM_PREP(req, msg_type, mailbox);
 397
 398         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 399
 400         HWRM_CHECK_RESULT();
 401
 402         if (resp_msg)
 403                 memcpy(resp_msg, resp, resp_len);
 404
 405         HWRM_UNLOCK();
 406
 407         return rc;
 408 }
 409
 410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 411                                   bool use_kong_mb,
 412                                   uint16_t tf_type,
 413                                   uint16_t tf_subtype,
 414                                   uint32_t *tf_response_code,
 415                                   void *msg,
 416                                   uint32_t msg_len,
 417                                   void *response,
 418                                   uint32_t response_len)
 419 {
 420         int rc = 0;
 421         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 422         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 423         bool mailbox = BNXT_USE_CHIMP_MB;
 424
 425         if (msg_len > sizeof(req.tf_req))
 426                 return -ENOMEM;
 427
 428         if (use_kong_mb)
 429                 mailbox = BNXT_USE_KONG(bp);
 430
 431         HWRM_PREP(&req, HWRM_TF, mailbox);
 432         /* Build request using the user supplied request payload.
 433          * TLV request size is checked at build time against HWRM
 434          * request max size, thus no checking required.
 435          */
 436         req.tf_type = tf_type;
 437         req.tf_subtype = tf_subtype;
 438         memcpy(req.tf_req, msg, msg_len);
 439
 440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 441         HWRM_CHECK_RESULT();
 442
 443         /* Copy the resp to user provided response buffer */
 444         if (response != NULL)
 445                 /* Post process response data. We need to copy only
 446                  * the 'payload' as the HWRM data structure really is
 447                  * HWRM header + msg header + payload and the TFLIB
 448                  * only provided a payload place holder.
 449                  */
 450                 if (response_len != 0) {
 451                         memcpy(response,
 452                                resp->tf_resp,
 453                                response_len);
 454                 }
 455
 456         /* Extract the internal tflib response code */
 457         *tf_response_code = resp->tf_resp_code;
 458         HWRM_UNLOCK();
 459
 460         return rc;
 461 }
 462
 463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 464 {
 465         int rc = 0;
 466         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 467         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 468
 469         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 470         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 471         req.mask = 0;
 472
 473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 474
 475         HWRM_CHECK_RESULT();
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 482                                  struct bnxt_vnic_info *vnic,
 483                                  uint16_t vlan_count,
 484                                  struct bnxt_vlan_table_entry *vlan_table)
 485 {
 486         int rc = 0;
 487         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 488         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 489         uint32_t mask = 0;
 490
 491         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 492                 return rc;
 493
 494         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 495         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 496
 497         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 498                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 499         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 500                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 501
 502         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 503                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 504
 505         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 506                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 507         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 508                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 509                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 510                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 511         }
 512         if (vlan_table) {
 513                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 514                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 515                 req.vlan_tag_tbl_addr =
 516                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 517                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 518         }
 519         req.mask = rte_cpu_to_le_32(mask);
 520
 521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 522
 523         HWRM_CHECK_RESULT();
 524         HWRM_UNLOCK();
 525
 526         return rc;
 527 }
 528
 529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 530                         uint16_t vlan_count,
 531                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 532 {
 533         int rc = 0;
 534         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 535         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 536                                                 bp->hwrm_cmd_resp_addr;
 537
 538         /*
 539          * Older HWRM versions did not support this command, and the set_rx_mask
 540          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 541          * removed from set_rx_mask call, and this command was added.
 542          *
 543          * This command is also present from 1.7.8.11 and higher,
 544          * as well as 1.7.8.0
 545          */
 546         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 547                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 548                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 549                                         (11)))
 550                                 return 0;
 551                 }
 552         }
 553         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 554         req.fid = rte_cpu_to_le_16(fid);
 555
 556         req.vlan_tag_mask_tbl_addr =
 557                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 558         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 559
 560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 561
 562         HWRM_CHECK_RESULT();
 563         HWRM_UNLOCK();
 564
 565         return rc;
 566 }
 567
 568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 569                              struct bnxt_filter_info *filter)
 570 {
 571         int rc = 0;
 572         struct bnxt_filter_info *l2_filter = filter;
 573         struct bnxt_vnic_info *vnic = NULL;
 574         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 575         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 576
 577         if (filter->fw_l2_filter_id == UINT64_MAX)
 578                 return 0;
 579
 580         if (filter->matching_l2_fltr_ptr)
 581                 l2_filter = filter->matching_l2_fltr_ptr;
 582
 583         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 584                     filter, l2_filter, l2_filter->l2_ref_cnt);
 585
 586         if (l2_filter->l2_ref_cnt == 0)
 587                 return 0;
 588
 589         if (l2_filter->l2_ref_cnt > 0)
 590                 l2_filter->l2_ref_cnt--;
 591
 592         if (l2_filter->l2_ref_cnt > 0)
 593                 return 0;
 594
 595         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 596
 597         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 598
 599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 600
 601         HWRM_CHECK_RESULT();
 602         HWRM_UNLOCK();
 603
 604         filter->fw_l2_filter_id = UINT64_MAX;
 605         if (l2_filter->l2_ref_cnt == 0) {
 606                 vnic = l2_filter->vnic;
 607                 if (vnic) {
 608                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 609                                       bnxt_filter_info, next);
 610                         bnxt_free_filter(bp, l2_filter);
 611                 }
 612         }
 613
 614         return 0;
 615 }
 616
 617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 618                          uint16_t dst_id,
 619                          struct bnxt_filter_info *filter)
 620 {
 621         int rc = 0;
 622         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 623         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 624         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 625         const struct rte_eth_vmdq_rx_conf *conf =
 626                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 627         uint32_t enables = 0;
 628         uint16_t j = dst_id - 1;
 629
 630         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 631         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 632             conf->pool_map[j].pools & (1UL << j)) {
 633                 PMD_DRV_LOG(DEBUG,
 634                         "Add vlan %u to vmdq pool %u\n",
 635                         conf->pool_map[j].vlan_id, j);
 636
 637                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 638                 filter->enables |=
 639                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 640                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 641         }
 642
 643         if (filter->fw_l2_filter_id != UINT64_MAX)
 644                 bnxt_hwrm_clear_l2_filter(bp, filter);
 645
 646         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 647
 648         /* PMD does not support XDP and RoCE */
 649         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
 650                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
 651         req.flags = rte_cpu_to_le_32(filter->flags);
 652
 653         enables = filter->enables |
 654               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 655         req.dst_id = rte_cpu_to_le_16(dst_id);
 656
 657         if (enables &
 658             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 659                 memcpy(req.l2_addr, filter->l2_addr,
 660                        RTE_ETHER_ADDR_LEN);
 661         if (enables &
 662             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 663                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 664                        RTE_ETHER_ADDR_LEN);
 665         if (enables &
 666             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 667                 req.l2_ovlan = filter->l2_ovlan;
 668         if (enables &
 669             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 670                 req.l2_ivlan = filter->l2_ivlan;
 671         if (enables &
 672             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 673                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 674         if (enables &
 675             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 676                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 677         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 678                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 679         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 680                 req.src_type = filter->src_type;
 681         if (filter->pri_hint) {
 682                 req.pri_hint = filter->pri_hint;
 683                 req.l2_filter_id_hint =
 684                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 685         }
 686
 687         req.enables = rte_cpu_to_le_32(enables);
 688
 689         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 690
 691         HWRM_CHECK_RESULT();
 692
 693         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 694         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 695         HWRM_UNLOCK();
 696
 697         filter->l2_ref_cnt++;
 698
 699         return rc;
 700 }
 701
 702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 703 {
 704         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 705         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 706         uint32_t flags = 0;
 707         int rc;
 708
 709         if (!ptp)
 710                 return 0;
 711
 712         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 713
 714         if (ptp->rx_filter)
 715                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 716         else
 717                 flags |=
 718                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 719         if (ptp->tx_tstamp_en)
 720                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 721         else
 722                 flags |=
 723                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 724         req.flags = rte_cpu_to_le_32(flags);
 725         req.enables = rte_cpu_to_le_32
 726                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 727         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 728
 729         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 730         HWRM_UNLOCK();
 731
 732         return rc;
 733 }
 734
 735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 736 {
 737         int rc = 0;
 738         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 739         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 740         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 741
 742         if (ptp)
 743                 return 0;
 744
 745         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 746
 747         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 748
 749         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 750
 751         HWRM_CHECK_RESULT();
 752
 753         if (BNXT_CHIP_P5(bp)) {
 754                 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS))
 755                         return 0;
 756         } else {
 757                 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 758                         return 0;
 759         }
 760
 761         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 762                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 763
 764         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 765         if (!ptp)
 766                 return -ENOMEM;
 767
 768         if (!BNXT_CHIP_P5(bp)) {
 769                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 770                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 771                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 772                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 773                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 774                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 775                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 776                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 777                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 778                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 779                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 780                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 781                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 782                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 783                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 784                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 785                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 786                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 787         }
 788
 789         ptp->bp = bp;
 790         bp->ptp_cfg = ptp;
 791
 792         return 0;
 793 }
 794
 795 void bnxt_free_vf_info(struct bnxt *bp)
 796 {
 797         int i;
 798
 799         if (bp->pf == NULL)
 800                 return;
 801
 802         if (bp->pf->vf_info == NULL)
 803                 return;
 804
 805         for (i = 0; i < bp->pf->max_vfs; i++) {
 806                 rte_free(bp->pf->vf_info[i].vlan_table);
 807                 bp->pf->vf_info[i].vlan_table = NULL;
 808                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 809                 bp->pf->vf_info[i].vlan_as_table = NULL;
 810         }
 811         rte_free(bp->pf->vf_info);
 812         bp->pf->vf_info = NULL;
 813 }
 814
 815 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
 816 {
 817         struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
 818         int i;
 819
 820         if (vf_info)
 821                 bnxt_free_vf_info(bp);
 822
 823         vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
 824         if (vf_info == NULL) {
 825                 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
 826                 return -ENOMEM;
 827         }
 828
 829         bp->pf->max_vfs = max_vfs;
 830         for (i = 0; i < max_vfs; i++) {
 831                 vf_info[i].fid = bp->pf->first_vf_id + i;
 832                 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
 833                                                     getpagesize(), getpagesize());
 834                 if (vf_info[i].vlan_table == NULL) {
 835                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
 836                         goto err;
 837                 }
 838                 rte_mem_lock_page(vf_info[i].vlan_table);
 839
 840                 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
 841                                                        getpagesize(), getpagesize());
 842                 if (vf_info[i].vlan_as_table == NULL) {
 843                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
 844                         goto err;
 845                 }
 846                 rte_mem_lock_page(vf_info[i].vlan_as_table);
 847
 848                 STAILQ_INIT(&vf_info[i].filter);
 849         }
 850
 851         bp->pf->vf_info = vf_info;
 852
 853         return 0;
 854 err:
 855         bnxt_free_vf_info(bp);
 856         return -ENOMEM;
 857 }
 858
 859 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 860 {
 861         int rc = 0;
 862         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 863         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 864         uint16_t new_max_vfs;
 865         uint32_t flags;
 866
 867         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 868
 869         req.fid = rte_cpu_to_le_16(0xffff);
 870
 871         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 872
 873         HWRM_CHECK_RESULT();
 874
 875         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 876         flags = rte_le_to_cpu_32(resp->flags);
 877         if (BNXT_PF(bp)) {
 878                 bp->pf->port_id = resp->port_id;
 879                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 880                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 881                 new_max_vfs = bp->pdev->max_vfs;
 882                 if (new_max_vfs != bp->pf->max_vfs) {
 883                         rc = bnxt_alloc_vf_info(bp, new_max_vfs);
 884                         if (rc)
 885                                 goto unlock;
 886                 }
 887         }
 888
 889         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 890         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 891                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 892                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 893         } else {
 894                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 895         }
 896         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 897         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 898         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 899         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 900         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 901         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 902         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 903         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
 904                 bp->max_l2_ctx += bp->max_rx_em_flows;
 905         /* TODO: For now, do not support VMDq/RFS on VFs. */
 906         if (BNXT_PF(bp)) {
 907                 if (bp->pf->max_vfs)
 908                         bp->max_vnics = 1;
 909                 else
 910                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 911         } else {
 912                 bp->max_vnics = 1;
 913         }
 914         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 915                     bp->max_l2_ctx, bp->max_vnics);
 916         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 917         if (BNXT_PF(bp)) {
 918                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 919                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 920                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 921                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 922                         HWRM_UNLOCK();
 923                         bnxt_hwrm_ptp_qcfg(bp);
 924                 }
 925         }
 926
 927         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 928                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 929
 930         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 931                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 932                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 933         }
 934
 935         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 936                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 937
 938         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 939                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 940
 941         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
 942                 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
 943
 944 unlock:
 945         HWRM_UNLOCK();
 946
 947         return rc;
 948 }
 949
 950 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 951 {
 952         int rc;
 953
 954         rc = __bnxt_hwrm_func_qcaps(bp);
 955         if (rc == -ENOMEM)
 956                 return rc;
 957
 958         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 959                 rc = bnxt_alloc_ctx_mem(bp);
 960                 if (rc)
 961                         return rc;
 962
 963                 /* On older FW,
 964                  * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 965                  * But the error can be ignored. Return success.
 966                  */
 967                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 968                 if (!rc)
 969                         bp->flags |= BNXT_FLAG_NEW_RM;
 970         }
 971
 972         return 0;
 973 }
 974
 975 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 976 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 977 {
 978         int rc = 0;
 979         uint32_t flags;
 980         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 981         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 982
 983         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 984
 985         req.target_id = rte_cpu_to_le_16(0xffff);
 986
 987         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 988
 989         HWRM_CHECK_RESULT();
 990
 991         flags = rte_le_to_cpu_32(resp->flags);
 992
 993         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 994                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 995                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 996         }
 997
 998         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
 999                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
1000
1001         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
1002                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
1003
1004         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
1005
1006         HWRM_UNLOCK();
1007
1008         return rc;
1009 }
1010
1011 int bnxt_hwrm_func_reset(struct bnxt *bp)
1012 {
1013         int rc = 0;
1014         struct hwrm_func_reset_input req = {.req_type = 0 };
1015         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1016
1017         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1018
1019         req.enables = rte_cpu_to_le_32(0);
1020
1021         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1022
1023         HWRM_CHECK_RESULT();
1024         HWRM_UNLOCK();
1025
1026         return rc;
1027 }
1028
1029 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1030 {
1031         int rc;
1032         uint32_t flags = 0;
1033         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1034         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1035
1036         if (bp->flags & BNXT_FLAG_REGISTERED)
1037                 return 0;
1038
1039         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1040                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1041         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1042                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1043
1044         /* PFs and trusted VFs should indicate the support of the
1045          * Master capability on non Stingray platform
1046          */
1047         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1048                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1049
1050         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1051         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1052                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1053         req.ver_maj = RTE_VER_YEAR;
1054         req.ver_min = RTE_VER_MONTH;
1055         req.ver_upd = RTE_VER_MINOR;
1056
1057         if (BNXT_PF(bp)) {
1058                 req.enables |= rte_cpu_to_le_32(
1059                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1060                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1061                        RTE_MIN(sizeof(req.vf_req_fwd),
1062                                sizeof(bp->pf->vf_req_fwd)));
1063         }
1064
1065         req.flags = rte_cpu_to_le_32(flags);
1066
1067         req.async_event_fwd[0] |=
1068                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1069                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1070                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1071                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1072                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1073         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1074                 req.async_event_fwd[0] |=
1075                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1076         req.async_event_fwd[1] |=
1077                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1078                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1079         if (BNXT_PF(bp))
1080                 req.async_event_fwd[1] |=
1081                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1082
1083         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1084                 req.async_event_fwd[1] |=
1085                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1086
1087         req.async_event_fwd[2] |=
1088                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST |
1089                                  ASYNC_CMPL_EVENT_ID_ERROR_REPORT);
1090
1091         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1092
1093         HWRM_CHECK_RESULT();
1094
1095         flags = rte_le_to_cpu_32(resp->flags);
1096         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1097                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1098
1099         HWRM_UNLOCK();
1100
1101         bp->flags |= BNXT_FLAG_REGISTERED;
1102
1103         return rc;
1104 }
1105
1106 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1107 {
1108         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1109                 return 0;
1110
1111         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1112 }
1113
1114 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1115 {
1116         int rc;
1117         uint32_t flags = 0;
1118         uint32_t enables;
1119         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1120         struct hwrm_func_vf_cfg_input req = {0};
1121
1122         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1123
1124         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
1125                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
1126                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
1127                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1128                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1129
1130         if (BNXT_HAS_RING_GRPS(bp)) {
1131                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1132                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1133         }
1134
1135         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1136         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1137                                             AGG_RING_MULTIPLIER);
1138         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1139         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1140                                               bp->tx_nr_rings +
1141                                               BNXT_NUM_ASYNC_CPR(bp));
1142         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1143         if (bp->vf_resv_strategy ==
1144             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1145                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1146                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1147                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1148                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1149                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1150                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1151         } else if (bp->vf_resv_strategy ==
1152                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1153                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1154                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1155         }
1156
1157         if (test)
1158                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1159                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1160                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1161                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1162                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1163                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1164
1165         if (test && BNXT_HAS_RING_GRPS(bp))
1166                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1167
1168         req.flags = rte_cpu_to_le_32(flags);
1169         req.enables |= rte_cpu_to_le_32(enables);
1170
1171         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1172
1173         if (test)
1174                 HWRM_CHECK_RESULT_SILENT();
1175         else
1176                 HWRM_CHECK_RESULT();
1177
1178         HWRM_UNLOCK();
1179         return rc;
1180 }
1181
1182 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1183 {
1184         int rc;
1185         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1186         struct hwrm_func_resource_qcaps_input req = {0};
1187
1188         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1189         req.fid = rte_cpu_to_le_16(0xffff);
1190
1191         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1192
1193         HWRM_CHECK_RESULT_SILENT();
1194
1195         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1196         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1197         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1198         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1199         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1200         /* func_resource_qcaps does not return max_rx_em_flows.
1201          * So use the value provided by func_qcaps.
1202          */
1203         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1204         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1205                 bp->max_l2_ctx += bp->max_rx_em_flows;
1206         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1207         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1208         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1209         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1210         if (bp->vf_resv_strategy >
1211             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1212                 bp->vf_resv_strategy =
1213                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1214
1215         HWRM_UNLOCK();
1216         return rc;
1217 }
1218
1219 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1220 {
1221         int rc = 0;
1222         struct hwrm_ver_get_input req = {.req_type = 0 };
1223         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1224         uint32_t fw_version;
1225         uint16_t max_resp_len;
1226         char type[RTE_MEMZONE_NAMESIZE];
1227         uint32_t dev_caps_cfg;
1228
1229         bp->max_req_len = HWRM_MAX_REQ_LEN;
1230         bp->hwrm_cmd_timeout = timeout;
1231         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1232
1233         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1234         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1235         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1236
1237         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1238
1239         if (bp->flags & BNXT_FLAG_FW_RESET)
1240                 HWRM_CHECK_RESULT_SILENT();
1241         else
1242                 HWRM_CHECK_RESULT();
1243
1244         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
1245                 rc = -EAGAIN;
1246                 goto error;
1247         }
1248
1249         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1250                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1251                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1252                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1253                 resp->hwrm_fw_rsvd_8b);
1254         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1255                      (resp->hwrm_fw_min_8b << 16) |
1256                      (resp->hwrm_fw_bld_8b << 8) |
1257                      resp->hwrm_fw_rsvd_8b;
1258         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1259                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1260
1261         fw_version = resp->hwrm_intf_maj_8b << 16;
1262         fw_version |= resp->hwrm_intf_min_8b << 8;
1263         fw_version |= resp->hwrm_intf_upd_8b;
1264         bp->hwrm_spec_code = fw_version;
1265
1266         /* def_req_timeout value is in milliseconds */
1267         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1268         /* convert timeout to usec */
1269         bp->hwrm_cmd_timeout *= 1000;
1270         if (!bp->hwrm_cmd_timeout)
1271                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1272
1273         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1274                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1275                 rc = -EINVAL;
1276                 goto error;
1277         }
1278
1279         if (bp->max_req_len > resp->max_req_win_len) {
1280                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1281                 rc = -EINVAL;
1282                 goto error;
1283         }
1284
1285         bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1286
1287         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1288         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1289         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1290                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1291
1292         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1293         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1294
1295         RTE_VERIFY(max_resp_len <= bp->max_resp_len);
1296         bp->max_resp_len = max_resp_len;
1297
1298         if ((dev_caps_cfg &
1299                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1300             (dev_caps_cfg &
1301              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1302                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1303                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1304         }
1305
1306         if (((dev_caps_cfg &
1307               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1308              (dev_caps_cfg &
1309               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1310             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1311                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1312                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1313                         bp->pdev->addr.devid, bp->pdev->addr.function);
1314
1315                 rte_free(bp->hwrm_short_cmd_req_addr);
1316
1317                 bp->hwrm_short_cmd_req_addr =
1318                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1319                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1320                         rc = -ENOMEM;
1321                         goto error;
1322                 }
1323                 bp->hwrm_short_cmd_req_dma_addr =
1324                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1325                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1326                         rte_free(bp->hwrm_short_cmd_req_addr);
1327                         PMD_DRV_LOG(ERR,
1328                                 "Unable to map buffer to physical memory.\n");
1329                         rc = -ENOMEM;
1330                         goto error;
1331                 }
1332         }
1333         if (dev_caps_cfg &
1334             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1335                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1336                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1337         }
1338         if (dev_caps_cfg &
1339             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1340                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1341         if (dev_caps_cfg &
1342             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1343                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1344                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1345         }
1346
1347         if (dev_caps_cfg &
1348             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1349                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1350                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1351         }
1352
1353         if (dev_caps_cfg &
1354             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED) {
1355                 PMD_DRV_LOG(DEBUG, "Host-based truflow feature enabled.\n");
1356                 bp->fw_cap |= BNXT_FW_CAP_TRUFLOW_EN;
1357         }
1358
1359 error:
1360         HWRM_UNLOCK();
1361         return rc;
1362 }
1363
1364 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1365 {
1366         int rc;
1367         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1368         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1369
1370         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1371                 return 0;
1372
1373         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1374         req.flags = flags;
1375
1376         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1377
1378         HWRM_CHECK_RESULT();
1379         HWRM_UNLOCK();
1380
1381         PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1382                     bp->eth_dev->data->port_id);
1383
1384         return rc;
1385 }
1386
1387 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1388 {
1389         int rc = 0;
1390         struct hwrm_port_phy_cfg_input req = {0};
1391         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1392         uint32_t enables = 0;
1393
1394         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1395
1396         if (conf->link_up) {
1397                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1398                 if (bp->link_info->auto_mode && conf->link_speed) {
1399                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1400                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1401                 }
1402
1403                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1404                 /*
1405                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1406                  * any auto mode, even "none".
1407                  */
1408                 if (!conf->link_speed) {
1409                         /* No speeds specified. Enable AutoNeg - all speeds */
1410                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1411                         req.auto_mode =
1412                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1413                 } else {
1414                         if (bp->link_info->link_signal_mode) {
1415                                 enables |=
1416                                 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1417                                 req.force_pam4_link_speed =
1418                                         rte_cpu_to_le_16(conf->link_speed);
1419                         } else {
1420                                 req.force_link_speed =
1421                                         rte_cpu_to_le_16(conf->link_speed);
1422                         }
1423                 }
1424                 /* AutoNeg - Advertise speeds specified. */
1425                 if (conf->auto_link_speed_mask &&
1426                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1427                         req.auto_mode =
1428                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1429                         req.auto_link_speed_mask =
1430                                 conf->auto_link_speed_mask;
1431                         if (conf->auto_pam4_link_speeds) {
1432                                 enables |=
1433                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1434                                 req.auto_link_pam4_speed_mask =
1435                                         conf->auto_pam4_link_speeds;
1436                         } else {
1437                                 enables |=
1438                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1439                         }
1440                 }
1441                 if (conf->auto_link_speed &&
1442                 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1443                         enables |=
1444                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1445
1446                 req.auto_duplex = conf->duplex;
1447                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1448                 req.auto_pause = conf->auto_pause;
1449                 req.force_pause = conf->force_pause;
1450                 /* Set force_pause if there is no auto or if there is a force */
1451                 if (req.auto_pause && !req.force_pause)
1452                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1453                 else
1454                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1455
1456                 req.enables = rte_cpu_to_le_32(enables);
1457         } else {
1458                 req.flags =
1459                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1460                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1461         }
1462
1463         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1464
1465         HWRM_CHECK_RESULT();
1466         HWRM_UNLOCK();
1467
1468         return rc;
1469 }
1470
1471 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1472                                    struct bnxt_link_info *link_info)
1473 {
1474         int rc = 0;
1475         struct hwrm_port_phy_qcfg_input req = {0};
1476         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1477
1478         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1479
1480         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1481
1482         HWRM_CHECK_RESULT();
1483
1484         link_info->phy_link_status = resp->link;
1485         link_info->link_up =
1486                 (link_info->phy_link_status ==
1487                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1488         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1489         link_info->duplex = resp->duplex_cfg;
1490         link_info->pause = resp->pause;
1491         link_info->auto_pause = resp->auto_pause;
1492         link_info->force_pause = resp->force_pause;
1493         link_info->auto_mode = resp->auto_mode;
1494         link_info->phy_type = resp->phy_type;
1495         link_info->media_type = resp->media_type;
1496
1497         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1498         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1499         link_info->auto_link_speed_mask = rte_le_to_cpu_16(resp->auto_link_speed_mask);
1500         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1501         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1502         link_info->phy_ver[0] = resp->phy_maj;
1503         link_info->phy_ver[1] = resp->phy_min;
1504         link_info->phy_ver[2] = resp->phy_bld;
1505         link_info->link_signal_mode =
1506                 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1507         link_info->force_pam4_link_speed =
1508                         rte_le_to_cpu_16(resp->force_pam4_link_speed);
1509         link_info->support_pam4_speeds =
1510                         rte_le_to_cpu_16(resp->support_pam4_speeds);
1511         link_info->auto_pam4_link_speeds =
1512                         rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1513         link_info->module_status = resp->module_status;
1514         HWRM_UNLOCK();
1515
1516         PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1517                     link_info->link_speed, link_info->auto_mode,
1518                     link_info->auto_link_speed, link_info->auto_link_speed_mask,
1519                     link_info->support_speeds, link_info->force_link_speed);
1520         PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1521                     link_info->link_signal_mode,
1522                     link_info->auto_pam4_link_speeds,
1523                     link_info->support_pam4_speeds,
1524                     link_info->force_pam4_link_speed);
1525         return rc;
1526 }
1527
1528 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1529 {
1530         int rc = 0;
1531         struct hwrm_port_phy_qcaps_input req = {0};
1532         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1533         struct bnxt_link_info *link_info = bp->link_info;
1534
1535         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1536                 return 0;
1537
1538         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1539
1540         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1541
1542         HWRM_CHECK_RESULT_SILENT();
1543
1544         bp->port_cnt = resp->port_cnt;
1545         if (resp->supported_speeds_auto_mode)
1546                 link_info->support_auto_speeds =
1547                         rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1548         if (resp->supported_pam4_speeds_auto_mode)
1549                 link_info->support_pam4_auto_speeds =
1550                         rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1551
1552         HWRM_UNLOCK();
1553
1554         /* Older firmware does not have supported_auto_speeds, so assume
1555          * that all supported speeds can be autonegotiated.
1556          */
1557         if (link_info->auto_link_speed_mask && !link_info->support_auto_speeds)
1558                 link_info->support_auto_speeds = link_info->support_speeds;
1559
1560         return 0;
1561 }
1562
1563 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1564 {
1565         int i = 0;
1566
1567         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1568                 if (bp->tx_cos_queue[i].profile ==
1569                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1570                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1571                         return true;
1572                 }
1573         }
1574         return false;
1575 }
1576
1577 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1578 {
1579         int i = 0;
1580
1581         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1582                 if (bp->tx_cos_queue[i].profile !=
1583                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1584                     bp->tx_cos_queue[i].id !=
1585                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1586                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1587                         break;
1588                 }
1589         }
1590 }
1591
1592 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1593 {
1594         int rc = 0;
1595         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1596         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1597         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1598         int i;
1599
1600 get_rx_info:
1601         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1602
1603         req.flags = rte_cpu_to_le_32(dir);
1604         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1605         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1606             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1607                 req.drv_qmap_cap =
1608                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1609         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1610
1611         HWRM_CHECK_RESULT();
1612
1613         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1614                 GET_TX_QUEUE_INFO(0);
1615                 GET_TX_QUEUE_INFO(1);
1616                 GET_TX_QUEUE_INFO(2);
1617                 GET_TX_QUEUE_INFO(3);
1618                 GET_TX_QUEUE_INFO(4);
1619                 GET_TX_QUEUE_INFO(5);
1620                 GET_TX_QUEUE_INFO(6);
1621                 GET_TX_QUEUE_INFO(7);
1622         } else  {
1623                 GET_RX_QUEUE_INFO(0);
1624                 GET_RX_QUEUE_INFO(1);
1625                 GET_RX_QUEUE_INFO(2);
1626                 GET_RX_QUEUE_INFO(3);
1627                 GET_RX_QUEUE_INFO(4);
1628                 GET_RX_QUEUE_INFO(5);
1629                 GET_RX_QUEUE_INFO(6);
1630                 GET_RX_QUEUE_INFO(7);
1631         }
1632
1633         HWRM_UNLOCK();
1634
1635         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1636                 goto done;
1637
1638         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1639                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1640         } else {
1641                 int j;
1642
1643                 /* iterate and find the COSq profile to use for Tx */
1644                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1645                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1646                                 if (bp->tx_cos_queue[i].id != 0xff)
1647                                         bp->tx_cosq_id[j++] =
1648                                                 bp->tx_cos_queue[i].id;
1649                         }
1650                 } else {
1651                         /* When CoS classification is disabled, for normal NIC
1652                          * operations, ideally we should look to use LOSSY.
1653                          * If not found, fallback to the first valid profile
1654                          */
1655                         if (!bnxt_find_lossy_profile(bp))
1656                                 bnxt_find_first_valid_profile(bp);
1657
1658                 }
1659         }
1660
1661         bp->max_tc = resp->max_configurable_queues;
1662         bp->max_lltc = resp->max_configurable_lossless_queues;
1663         if (bp->max_tc > BNXT_MAX_QUEUE)
1664                 bp->max_tc = BNXT_MAX_QUEUE;
1665         bp->max_q = bp->max_tc;
1666
1667         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1668                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1669                 goto get_rx_info;
1670         }
1671
1672 done:
1673         return rc;
1674 }
1675
1676 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1677                          struct bnxt_ring *ring,
1678                          uint32_t ring_type, uint32_t map_index,
1679                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1680                          uint16_t tx_cosq_id)
1681 {
1682         int rc = 0;
1683         uint32_t enables = 0;
1684         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1685         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1686         struct rte_mempool *mb_pool;
1687         uint16_t rx_buf_size;
1688
1689         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1690
1691         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1692         req.fbo = rte_cpu_to_le_32(0);
1693         /* Association of ring index with doorbell index */
1694         req.logical_id = rte_cpu_to_le_16(map_index);
1695         req.length = rte_cpu_to_le_32(ring->ring_size);
1696
1697         switch (ring_type) {
1698         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1699                 req.ring_type = ring_type;
1700                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1701                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1702                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1703                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1704                         enables |=
1705                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1706                 break;
1707         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1708                 req.ring_type = ring_type;
1709                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1710                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1711                 if (BNXT_CHIP_P5(bp)) {
1712                         mb_pool = bp->rx_queues[0]->mb_pool;
1713                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1714                                       RTE_PKTMBUF_HEADROOM;
1715                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1716                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1717                         enables |=
1718                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1719                 }
1720                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1721                         enables |=
1722                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1723                 break;
1724         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1725                 req.ring_type = ring_type;
1726                 if (BNXT_HAS_NQ(bp)) {
1727                         /* Association of cp ring with nq */
1728                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1729                         enables |=
1730                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1731                 }
1732                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1733                 break;
1734         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1735                 req.ring_type = ring_type;
1736                 req.page_size = BNXT_PAGE_SHFT;
1737                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1738                 break;
1739         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1740                 req.ring_type = ring_type;
1741                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1742
1743                 mb_pool = bp->rx_queues[0]->mb_pool;
1744                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1745                               RTE_PKTMBUF_HEADROOM;
1746                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1747                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1748
1749                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1750                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1751                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1752                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1753                 break;
1754         default:
1755                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1756                         ring_type);
1757                 HWRM_UNLOCK();
1758                 return -EINVAL;
1759         }
1760         req.enables = rte_cpu_to_le_32(enables);
1761
1762         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1763
1764         if (rc || resp->error_code) {
1765                 if (rc == 0 && resp->error_code)
1766                         rc = rte_le_to_cpu_16(resp->error_code);
1767                 switch (ring_type) {
1768                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1769                         PMD_DRV_LOG(ERR,
1770                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1771                         HWRM_UNLOCK();
1772                         return rc;
1773                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1774                         PMD_DRV_LOG(ERR,
1775                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1776                         HWRM_UNLOCK();
1777                         return rc;
1778                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1779                         PMD_DRV_LOG(ERR,
1780                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1781                                     rc);
1782                         HWRM_UNLOCK();
1783                         return rc;
1784                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1785                         PMD_DRV_LOG(ERR,
1786                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1787                         HWRM_UNLOCK();
1788                         return rc;
1789                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1790                         PMD_DRV_LOG(ERR,
1791                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1792                         HWRM_UNLOCK();
1793                         return rc;
1794                 default:
1795                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1796                         HWRM_UNLOCK();
1797                         return rc;
1798                 }
1799         }
1800
1801         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1802         HWRM_UNLOCK();
1803         return rc;
1804 }
1805
1806 int bnxt_hwrm_ring_free(struct bnxt *bp,
1807                         struct bnxt_ring *ring, uint32_t ring_type,
1808                         uint16_t cp_ring_id)
1809 {
1810         int rc;
1811         struct hwrm_ring_free_input req = {.req_type = 0 };
1812         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1813
1814         if (ring->fw_ring_id == INVALID_HW_RING_ID)
1815                 return -EINVAL;
1816
1817         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1818
1819         req.ring_type = ring_type;
1820         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1821         req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1822
1823         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1824         ring->fw_ring_id = INVALID_HW_RING_ID;
1825
1826         if (rc || resp->error_code) {
1827                 if (rc == 0 && resp->error_code)
1828                         rc = rte_le_to_cpu_16(resp->error_code);
1829                 HWRM_UNLOCK();
1830
1831                 switch (ring_type) {
1832                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1833                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1834                                 rc);
1835                         return rc;
1836                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1837                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1838                                 rc);
1839                         return rc;
1840                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1841                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1842                                 rc);
1843                         return rc;
1844                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1845                         PMD_DRV_LOG(ERR,
1846                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1847                         return rc;
1848                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1849                         PMD_DRV_LOG(ERR,
1850                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1851                         return rc;
1852                 default:
1853                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1854                         return rc;
1855                 }
1856         }
1857         HWRM_UNLOCK();
1858         return 0;
1859 }
1860
1861 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1862 {
1863         int rc = 0;
1864         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1865         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1866
1867         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1868
1869         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1870         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1871         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1872         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1873
1874         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1875
1876         HWRM_CHECK_RESULT();
1877
1878         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1879
1880         HWRM_UNLOCK();
1881
1882         return rc;
1883 }
1884
1885 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1886 {
1887         int rc;
1888         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1889         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1890
1891         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1892
1893         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1894
1895         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1896
1897         HWRM_CHECK_RESULT();
1898         HWRM_UNLOCK();
1899
1900         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1901         return rc;
1902 }
1903
1904 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1905 {
1906         int rc = 0;
1907         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1908         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1909
1910         if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
1911                 return rc;
1912
1913         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1914
1915         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1916
1917         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1918
1919         HWRM_CHECK_RESULT();
1920         HWRM_UNLOCK();
1921
1922         return rc;
1923 }
1924
1925 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1926 {
1927         int rc;
1928         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1929         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1930
1931         if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE)
1932                 return 0;
1933
1934         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1935
1936         req.update_period_ms = rte_cpu_to_le_32(0);
1937
1938         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1939
1940         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1941
1942         HWRM_CHECK_RESULT();
1943
1944         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1945
1946         HWRM_UNLOCK();
1947
1948         return rc;
1949 }
1950
1951 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1952 {
1953         int rc;
1954         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1955         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1956
1957         if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
1958                 return 0;
1959
1960         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1961
1962         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1963
1964         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1965
1966         HWRM_CHECK_RESULT();
1967         HWRM_UNLOCK();
1968
1969         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1970
1971         return rc;
1972 }
1973
1974 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1975 {
1976         int rc = 0, i, j;
1977         struct hwrm_vnic_alloc_input req = { 0 };
1978         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1979
1980         if (!BNXT_HAS_RING_GRPS(bp))
1981                 goto skip_ring_grps;
1982
1983         /* map ring groups to this vnic */
1984         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1985                 vnic->start_grp_id, vnic->end_grp_id);
1986         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1987                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1988
1989         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1990         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1991         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1992         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1993
1994 skip_ring_grps:
1995         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1996         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1997
1998         if (vnic->func_default)
1999                 req.flags =
2000                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
2001         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2002
2003         HWRM_CHECK_RESULT();
2004
2005         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
2006         HWRM_UNLOCK();
2007         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2008         return rc;
2009 }
2010
2011 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
2012                                         struct bnxt_vnic_info *vnic,
2013                                         struct bnxt_plcmodes_cfg *pmode)
2014 {
2015         int rc = 0;
2016         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
2017         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2018
2019         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
2020
2021         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2022
2023         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2024
2025         HWRM_CHECK_RESULT();
2026
2027         pmode->flags = rte_le_to_cpu_32(resp->flags);
2028         /* dflt_vnic bit doesn't exist in the _cfg command */
2029         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
2030         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
2031         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2032         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2033
2034         HWRM_UNLOCK();
2035
2036         return rc;
2037 }
2038
2039 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2040                                        struct bnxt_vnic_info *vnic,
2041                                        struct bnxt_plcmodes_cfg *pmode)
2042 {
2043         int rc = 0;
2044         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2045         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2046
2047         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2048                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2049                 return rc;
2050         }
2051
2052         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2053
2054         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2055         req.flags = rte_cpu_to_le_32(pmode->flags);
2056         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2057         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2058         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2059         req.enables = rte_cpu_to_le_32(
2060             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2061             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2062             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2063         );
2064
2065         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2066
2067         HWRM_CHECK_RESULT();
2068         HWRM_UNLOCK();
2069
2070         return rc;
2071 }
2072
2073 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2074 {
2075         int rc = 0;
2076         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2077         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2078         struct bnxt_plcmodes_cfg pmodes = { 0 };
2079         uint32_t ctx_enable_flag = 0;
2080         uint32_t enables = 0;
2081
2082         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2083                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2084                 return rc;
2085         }
2086
2087         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2088         if (rc)
2089                 return rc;
2090
2091         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2092
2093         if (BNXT_CHIP_P5(bp)) {
2094                 int dflt_rxq = vnic->start_grp_id;
2095                 struct bnxt_rx_ring_info *rxr;
2096                 struct bnxt_cp_ring_info *cpr;
2097                 struct bnxt_rx_queue *rxq;
2098                 int i;
2099
2100                 /*
2101                  * The first active receive ring is used as the VNIC
2102                  * default receive ring. If there are no active receive
2103                  * rings (all corresponding receive queues are stopped),
2104                  * the first receive ring is used.
2105                  */
2106                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2107                         rxq = bp->eth_dev->data->rx_queues[i];
2108                         if (rxq->rx_started) {
2109                                 dflt_rxq = i;
2110                                 break;
2111                         }
2112                 }
2113
2114                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2115                 rxr = rxq->rx_ring;
2116                 cpr = rxq->cp_ring;
2117
2118                 req.default_rx_ring_id =
2119                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2120                 req.default_cmpl_ring_id =
2121                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2122                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2123                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2124                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2125                         enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2126                         req.rx_csum_v2_mode =
2127                                 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2128                 }
2129                 goto config_mru;
2130         }
2131
2132         /* Only RSS support for now TBD: COS & LB */
2133         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2134         if (vnic->lb_rule != 0xffff)
2135                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2136         if (vnic->cos_rule != 0xffff)
2137                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2138         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2139                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2140                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2141         }
2142         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2143                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2144                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2145         }
2146
2147         enables |= ctx_enable_flag;
2148         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2149         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2150         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2151         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2152
2153 config_mru:
2154         req.enables = rte_cpu_to_le_32(enables);
2155         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2156         req.mru = rte_cpu_to_le_16(vnic->mru);
2157         /* Configure default VNIC only once. */
2158         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2159                 req.flags |=
2160                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2161                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2162         }
2163         if (vnic->vlan_strip)
2164                 req.flags |=
2165                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2166         if (vnic->bd_stall)
2167                 req.flags |=
2168                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2169         if (vnic->rss_dflt_cr)
2170                 req.flags |= rte_cpu_to_le_32(
2171                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2172
2173         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2174
2175         HWRM_CHECK_RESULT();
2176         HWRM_UNLOCK();
2177
2178         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2179
2180         return rc;
2181 }
2182
2183 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2184                 int16_t fw_vf_id)
2185 {
2186         int rc = 0;
2187         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2188         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2189
2190         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2191                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2192                 return rc;
2193         }
2194         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2195
2196         req.enables =
2197                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2198         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2199         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2200
2201         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2202
2203         HWRM_CHECK_RESULT();
2204
2205         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2206         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2207         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2208         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2209         vnic->mru = rte_le_to_cpu_16(resp->mru);
2210         vnic->func_default = rte_le_to_cpu_32(
2211                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2212         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2213                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2214         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2215                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2216         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2217                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2218
2219         HWRM_UNLOCK();
2220
2221         return rc;
2222 }
2223
2224 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2225                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2226 {
2227         int rc = 0;
2228         uint16_t ctx_id;
2229         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2230         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2231                                                 bp->hwrm_cmd_resp_addr;
2232
2233         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2234
2235         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2236         HWRM_CHECK_RESULT();
2237
2238         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2239         if (!BNXT_HAS_RING_GRPS(bp))
2240                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2241         else if (ctx_idx == 0)
2242                 vnic->rss_rule = ctx_id;
2243
2244         HWRM_UNLOCK();
2245
2246         return rc;
2247 }
2248
2249 static
2250 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2251                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2252 {
2253         int rc = 0;
2254         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2255         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2256                                                 bp->hwrm_cmd_resp_addr;
2257
2258         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2259                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2260                 return rc;
2261         }
2262         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2263
2264         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2265
2266         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2267
2268         HWRM_CHECK_RESULT();
2269         HWRM_UNLOCK();
2270
2271         return rc;
2272 }
2273
2274 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2275 {
2276         int rc = 0;
2277
2278         if (BNXT_CHIP_P5(bp)) {
2279                 int j;
2280
2281                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2282                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2283                                                       vnic,
2284                                                       vnic->fw_grp_ids[j]);
2285                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2286                 }
2287                 vnic->num_lb_ctxts = 0;
2288         } else {
2289                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2290                 vnic->rss_rule = INVALID_HW_RING_ID;
2291         }
2292
2293         return rc;
2294 }
2295
2296 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2297 {
2298         int rc = 0;
2299         struct hwrm_vnic_free_input req = {.req_type = 0 };
2300         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2301
2302         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2303                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2304                 return rc;
2305         }
2306
2307         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2308
2309         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2310
2311         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2312
2313         HWRM_CHECK_RESULT();
2314         HWRM_UNLOCK();
2315
2316         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2317         /* Configure default VNIC again if necessary. */
2318         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2319                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2320
2321         return rc;
2322 }
2323
2324 static int
2325 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2326 {
2327         int i;
2328         int rc = 0;
2329         int nr_ctxs = vnic->num_lb_ctxts;
2330         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2331         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2332
2333         for (i = 0; i < nr_ctxs; i++) {
2334                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2335
2336                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2337                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2338                 req.hash_mode_flags = vnic->hash_mode;
2339
2340                 req.hash_key_tbl_addr =
2341                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2342
2343                 req.ring_grp_tbl_addr =
2344                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2345                                          i * HW_HASH_INDEX_SIZE);
2346                 req.ring_table_pair_index = i;
2347                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2348
2349                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2350                                             BNXT_USE_CHIMP_MB);
2351
2352                 HWRM_CHECK_RESULT();
2353                 HWRM_UNLOCK();
2354         }
2355
2356         return rc;
2357 }
2358
2359 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2360                            struct bnxt_vnic_info *vnic)
2361 {
2362         int rc = 0;
2363         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2364         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2365
2366         if (!vnic->rss_table)
2367                 return 0;
2368
2369         if (BNXT_CHIP_P5(bp))
2370                 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2371
2372         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2373
2374         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2375         req.hash_mode_flags = vnic->hash_mode;
2376
2377         req.ring_grp_tbl_addr =
2378             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2379         req.hash_key_tbl_addr =
2380             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2381         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2382         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2383
2384         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2385
2386         HWRM_CHECK_RESULT();
2387         HWRM_UNLOCK();
2388
2389         return rc;
2390 }
2391
2392 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2393                         struct bnxt_vnic_info *vnic)
2394 {
2395         int rc = 0;
2396         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2397         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2398         uint16_t size;
2399
2400         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2401                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2402                 return rc;
2403         }
2404
2405         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2406
2407         req.flags = rte_cpu_to_le_32(
2408                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2409
2410         req.enables = rte_cpu_to_le_32(
2411                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2412
2413         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2414         size -= RTE_PKTMBUF_HEADROOM;
2415         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2416
2417         req.jumbo_thresh = rte_cpu_to_le_16(size);
2418         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2419
2420         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2421
2422         HWRM_CHECK_RESULT();
2423         HWRM_UNLOCK();
2424
2425         return rc;
2426 }
2427
2428 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2429                         struct bnxt_vnic_info *vnic, bool enable)
2430 {
2431         int rc = 0;
2432         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2433         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2434
2435         if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2436                 if (enable)
2437                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2438                 return -ENOTSUP;
2439         }
2440
2441         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2442                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2443                 return 0;
2444         }
2445
2446         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2447
2448         if (enable) {
2449                 req.enables = rte_cpu_to_le_32(
2450                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2451                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2452                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2453                 req.flags = rte_cpu_to_le_32(
2454                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2455                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2456                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2457                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2458                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2459                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2460                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2461                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2462                 req.min_agg_len = rte_cpu_to_le_32(512);
2463         }
2464         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2465
2466         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2467
2468         HWRM_CHECK_RESULT();
2469         HWRM_UNLOCK();
2470
2471         return rc;
2472 }
2473
2474 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2475 {
2476         struct hwrm_func_cfg_input req = {0};
2477         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2478         int rc;
2479
2480         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2481         req.enables = rte_cpu_to_le_32(
2482                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2483         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2484         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2485
2486         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2487
2488         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2489         HWRM_CHECK_RESULT();
2490         HWRM_UNLOCK();
2491
2492         bp->pf->vf_info[vf].random_mac = false;
2493
2494         return rc;
2495 }
2496
2497 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2498                                   uint64_t *dropped)
2499 {
2500         int rc = 0;
2501         struct hwrm_func_qstats_input req = {.req_type = 0};
2502         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2503
2504         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2505
2506         req.fid = rte_cpu_to_le_16(fid);
2507
2508         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2509
2510         HWRM_CHECK_RESULT();
2511
2512         if (dropped)
2513                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2514
2515         HWRM_UNLOCK();
2516
2517         return rc;
2518 }
2519
2520 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2521                           struct rte_eth_stats *stats,
2522                           struct hwrm_func_qstats_output *func_qstats)
2523 {
2524         int rc = 0;
2525         struct hwrm_func_qstats_input req = {.req_type = 0};
2526         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2527
2528         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2529
2530         req.fid = rte_cpu_to_le_16(fid);
2531
2532         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2533
2534         HWRM_CHECK_RESULT();
2535         if (func_qstats)
2536                 memcpy(func_qstats, resp,
2537                        sizeof(struct hwrm_func_qstats_output));
2538
2539         if (!stats)
2540                 goto exit;
2541
2542         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2543         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2544         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2545         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2546         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2547         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2548
2549         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2550         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2551         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2552         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2553         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2554         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2555
2556         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2557         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2558         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2559
2560 exit:
2561         HWRM_UNLOCK();
2562
2563         return rc;
2564 }
2565
2566 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2567 {
2568         int rc = 0;
2569         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2570         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2571
2572         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2573
2574         req.fid = rte_cpu_to_le_16(fid);
2575
2576         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2577
2578         HWRM_CHECK_RESULT();
2579         HWRM_UNLOCK();
2580
2581         return rc;
2582 }
2583
2584 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2585 {
2586         unsigned int i;
2587         int rc = 0;
2588
2589         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2590                 struct bnxt_tx_queue *txq;
2591                 struct bnxt_rx_queue *rxq;
2592                 struct bnxt_cp_ring_info *cpr;
2593
2594                 if (i >= bp->rx_cp_nr_rings) {
2595                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2596                         cpr = txq->cp_ring;
2597                 } else {
2598                         rxq = bp->rx_queues[i];
2599                         cpr = rxq->cp_ring;
2600                 }
2601
2602                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2603                 if (rc)
2604                         return rc;
2605         }
2606         return 0;
2607 }
2608
2609 static int
2610 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2611 {
2612         int rc;
2613         unsigned int i;
2614         struct bnxt_cp_ring_info *cpr;
2615
2616         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2617
2618                 cpr = bp->rx_queues[i]->cp_ring;
2619                 if (BNXT_HAS_RING_GRPS(bp))
2620                         bp->grp_info[i].fw_stats_ctx = -1;
2621                 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2622                 if (rc)
2623                         return rc;
2624         }
2625
2626         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2627                 cpr = bp->tx_queues[i]->cp_ring;
2628                 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2629                 if (rc)
2630                         return rc;
2631         }
2632
2633         return 0;
2634 }
2635
2636 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2637 {
2638         struct bnxt_cp_ring_info *cpr;
2639         unsigned int i;
2640         int rc = 0;
2641
2642         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2643                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
2644
2645                 cpr = rxq->cp_ring;
2646                 if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE) {
2647                         rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
2648                         if (rc)
2649                                 return rc;
2650                 }
2651         }
2652
2653         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2654                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2655
2656                 cpr = txq->cp_ring;
2657                 if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE) {
2658                         rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
2659                         if (rc)
2660                                 return rc;
2661                 }
2662         }
2663
2664         return rc;
2665 }
2666
2667 static int
2668 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2669 {
2670         uint16_t idx;
2671         uint32_t rc = 0;
2672
2673         if (!BNXT_HAS_RING_GRPS(bp))
2674                 return 0;
2675
2676         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2677
2678                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2679                         continue;
2680
2681                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2682
2683                 if (rc)
2684                         return rc;
2685         }
2686         return rc;
2687 }
2688
2689 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2690 {
2691         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2692
2693         bnxt_hwrm_ring_free(bp, cp_ring,
2694                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2695                             INVALID_HW_RING_ID);
2696         memset(cpr->cp_desc_ring, 0,
2697                cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
2698         cpr->cp_raw_cons = 0;
2699 }
2700
2701 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2702 {
2703         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2704
2705         bnxt_hwrm_ring_free(bp, cp_ring,
2706                             HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2707                             INVALID_HW_RING_ID);
2708         memset(cpr->cp_desc_ring, 0,
2709                cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
2710         cpr->cp_raw_cons = 0;
2711 }
2712
2713 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2714 {
2715         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2716         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2717         struct bnxt_ring *ring = rxr->rx_ring_struct;
2718         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2719
2720         bnxt_hwrm_ring_free(bp, ring,
2721                             HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2722                             cpr->cp_ring_struct->fw_ring_id);
2723         if (BNXT_HAS_RING_GRPS(bp))
2724                 bp->grp_info[queue_index].rx_fw_ring_id = INVALID_HW_RING_ID;
2725
2726         ring = rxr->ag_ring_struct;
2727         bnxt_hwrm_ring_free(bp, ring,
2728                             BNXT_CHIP_P5(bp) ?
2729                             HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2730                             HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2731                             cpr->cp_ring_struct->fw_ring_id);
2732         if (BNXT_HAS_RING_GRPS(bp))
2733                 bp->grp_info[queue_index].ag_fw_ring_id = INVALID_HW_RING_ID;
2734
2735         bnxt_hwrm_stat_ctx_free(bp, cpr);
2736
2737         bnxt_free_cp_ring(bp, cpr);
2738
2739         if (BNXT_HAS_RING_GRPS(bp))
2740                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2741 }
2742
2743 int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int queue_index)
2744 {
2745         int rc;
2746         struct hwrm_ring_reset_input req = {.req_type = 0 };
2747         struct hwrm_ring_reset_output *resp = bp->hwrm_cmd_resp_addr;
2748
2749         HWRM_PREP(&req, HWRM_RING_RESET, BNXT_USE_CHIMP_MB);
2750
2751         req.ring_type = HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP;
2752         req.ring_id = rte_cpu_to_le_16(bp->grp_info[queue_index].fw_grp_id);
2753         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2754
2755         HWRM_CHECK_RESULT();
2756
2757         HWRM_UNLOCK();
2758
2759         return rc;
2760 }
2761
2762 static int
2763 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2764 {
2765         unsigned int i;
2766
2767         for (i = 0; i < bp->tx_cp_nr_rings; i++)
2768                 bnxt_free_hwrm_tx_ring(bp, i);
2769
2770         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2771                 bnxt_free_hwrm_rx_ring(bp, i);
2772
2773         return 0;
2774 }
2775
2776 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2777 {
2778         uint16_t i;
2779         uint32_t rc = 0;
2780
2781         if (!BNXT_HAS_RING_GRPS(bp))
2782                 return 0;
2783
2784         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2785                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2786                 if (rc)
2787                         return rc;
2788         }
2789         return rc;
2790 }
2791
2792 /*
2793  * HWRM utility functions
2794  */
2795
2796 void bnxt_free_hwrm_resources(struct bnxt *bp)
2797 {
2798         /* Release memzone */
2799         rte_free(bp->hwrm_cmd_resp_addr);
2800         rte_free(bp->hwrm_short_cmd_req_addr);
2801         bp->hwrm_cmd_resp_addr = NULL;
2802         bp->hwrm_short_cmd_req_addr = NULL;
2803         bp->hwrm_cmd_resp_dma_addr = 0;
2804         bp->hwrm_short_cmd_req_dma_addr = 0;
2805 }
2806
2807 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2808 {
2809         struct rte_pci_device *pdev = bp->pdev;
2810         char type[RTE_MEMZONE_NAMESIZE];
2811
2812         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2813                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2814         bp->max_resp_len = BNXT_PAGE_SIZE;
2815         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2816         if (bp->hwrm_cmd_resp_addr == NULL)
2817                 return -ENOMEM;
2818         bp->hwrm_cmd_resp_dma_addr =
2819                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2820         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2821                 PMD_DRV_LOG(ERR,
2822                         "unable to map response address to physical memory\n");
2823                 return -ENOMEM;
2824         }
2825         rte_spinlock_init(&bp->hwrm_lock);
2826
2827         return 0;
2828 }
2829
2830 int
2831 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2832 {
2833         int rc = 0;
2834
2835         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2836                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2837                 if (rc)
2838                         return rc;
2839         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2840                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2841                 if (rc)
2842                         return rc;
2843         }
2844
2845         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2846         return rc;
2847 }
2848
2849 static int
2850 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2851 {
2852         struct bnxt_filter_info *filter;
2853         int rc = 0;
2854
2855         STAILQ_FOREACH(filter, &vnic->filter, next) {
2856                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2857                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2858                 bnxt_free_filter(bp, filter);
2859         }
2860         return rc;
2861 }
2862
2863 static int
2864 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2865 {
2866         struct bnxt_filter_info *filter;
2867         struct rte_flow *flow;
2868         int rc = 0;
2869
2870         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2871                 flow = STAILQ_FIRST(&vnic->flow_list);
2872                 filter = flow->filter;
2873                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2874                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2875
2876                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2877                 rte_free(flow);
2878         }
2879         return rc;
2880 }
2881
2882 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2883 {
2884         struct bnxt_filter_info *filter;
2885         int rc = 0;
2886
2887         STAILQ_FOREACH(filter, &vnic->filter, next) {
2888                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2889                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2890                                                      filter);
2891                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2892                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2893                                                          filter);
2894                 else
2895                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2896                                                      filter);
2897                 if (rc)
2898                         break;
2899         }
2900         return rc;
2901 }
2902
2903 static void
2904 bnxt_free_tunnel_ports(struct bnxt *bp)
2905 {
2906         if (bp->vxlan_port_cnt)
2907                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2908                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2909
2910         if (bp->geneve_port_cnt)
2911                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2912                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2913 }
2914
2915 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2916 {
2917         int i;
2918
2919         if (bp->vnic_info == NULL)
2920                 return;
2921
2922         /*
2923          * Cleanup VNICs in reverse order, to make sure the L2 filter
2924          * from vnic0 is last to be cleaned up.
2925          */
2926         for (i = bp->max_vnics - 1; i >= 0; i--) {
2927                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2928
2929                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2930                         continue;
2931
2932                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2933
2934                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2935
2936                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2937
2938                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2939
2940                 bnxt_hwrm_vnic_free(bp, vnic);
2941
2942                 rte_free(vnic->fw_grp_ids);
2943         }
2944         /* Ring resources */
2945         bnxt_free_all_hwrm_rings(bp);
2946         bnxt_free_all_hwrm_ring_grps(bp);
2947         bnxt_free_all_hwrm_stat_ctxs(bp);
2948         bnxt_free_tunnel_ports(bp);
2949 }
2950
2951 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2952 {
2953         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2954
2955         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2956                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2957
2958         switch (conf_link_speed) {
2959         case ETH_LINK_SPEED_10M_HD:
2960         case ETH_LINK_SPEED_100M_HD:
2961                 /* FALLTHROUGH */
2962                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2963         }
2964         return hw_link_duplex;
2965 }
2966
2967 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2968 {
2969         return !conf_link;
2970 }
2971
2972 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2973                                           uint16_t pam4_link)
2974 {
2975         uint16_t eth_link_speed = 0;
2976
2977         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2978                 return ETH_LINK_SPEED_AUTONEG;
2979
2980         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2981         case ETH_LINK_SPEED_100M:
2982         case ETH_LINK_SPEED_100M_HD:
2983                 /* FALLTHROUGH */
2984                 eth_link_speed =
2985                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2986                 break;
2987         case ETH_LINK_SPEED_1G:
2988                 eth_link_speed =
2989                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2990                 break;
2991         case ETH_LINK_SPEED_2_5G:
2992                 eth_link_speed =
2993                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2994                 break;
2995         case ETH_LINK_SPEED_10G:
2996                 eth_link_speed =
2997                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2998                 break;
2999         case ETH_LINK_SPEED_20G:
3000                 eth_link_speed =
3001                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
3002                 break;
3003         case ETH_LINK_SPEED_25G:
3004                 eth_link_speed =
3005                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
3006                 break;
3007         case ETH_LINK_SPEED_40G:
3008                 eth_link_speed =
3009                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
3010                 break;
3011         case ETH_LINK_SPEED_50G:
3012                 eth_link_speed = pam4_link ?
3013                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
3014                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
3015                 break;
3016         case ETH_LINK_SPEED_100G:
3017                 eth_link_speed = pam4_link ?
3018                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
3019                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
3020                 break;
3021         case ETH_LINK_SPEED_200G:
3022                 eth_link_speed =
3023                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3024                 break;
3025         default:
3026                 PMD_DRV_LOG(ERR,
3027                         "Unsupported link speed %d; default to AUTO\n",
3028                         conf_link_speed);
3029                 break;
3030         }
3031         return eth_link_speed;
3032 }
3033
3034 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
3035                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
3036                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
3037                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
3038                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
3039
3040 static int bnxt_validate_link_speed(struct bnxt *bp)
3041 {
3042         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3043         uint16_t port_id = bp->eth_dev->data->port_id;
3044         uint32_t link_speed_capa;
3045         uint32_t one_speed;
3046
3047         if (link_speed == ETH_LINK_SPEED_AUTONEG)
3048                 return 0;
3049
3050         link_speed_capa = bnxt_get_speed_capabilities(bp);
3051
3052         if (link_speed & ETH_LINK_SPEED_FIXED) {
3053                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
3054
3055                 if (one_speed & (one_speed - 1)) {
3056                         PMD_DRV_LOG(ERR,
3057                                 "Invalid advertised speeds (%u) for port %u\n",
3058                                 link_speed, port_id);
3059                         return -EINVAL;
3060                 }
3061                 if ((one_speed & link_speed_capa) != one_speed) {
3062                         PMD_DRV_LOG(ERR,
3063                                 "Unsupported advertised speed (%u) for port %u\n",
3064                                 link_speed, port_id);
3065                         return -EINVAL;
3066                 }
3067         } else {
3068                 if (!(link_speed & link_speed_capa)) {
3069                         PMD_DRV_LOG(ERR,
3070                                 "Unsupported advertised speeds (%u) for port %u\n",
3071                                 link_speed, port_id);
3072                         return -EINVAL;
3073                 }
3074         }
3075         return 0;
3076 }
3077
3078 static uint16_t
3079 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3080 {
3081         uint16_t ret = 0;
3082
3083         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
3084                 if (bp->link_info->support_speeds)
3085                         return bp->link_info->support_speeds;
3086                 link_speed = BNXT_SUPPORTED_SPEEDS;
3087         }
3088
3089         if (link_speed & ETH_LINK_SPEED_100M)
3090                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3091         if (link_speed & ETH_LINK_SPEED_100M_HD)
3092                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3093         if (link_speed & ETH_LINK_SPEED_1G)
3094                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3095         if (link_speed & ETH_LINK_SPEED_2_5G)
3096                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3097         if (link_speed & ETH_LINK_SPEED_10G)
3098                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3099         if (link_speed & ETH_LINK_SPEED_20G)
3100                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3101         if (link_speed & ETH_LINK_SPEED_25G)
3102                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3103         if (link_speed & ETH_LINK_SPEED_40G)
3104                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3105         if (link_speed & ETH_LINK_SPEED_50G)
3106                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3107         if (link_speed & ETH_LINK_SPEED_100G)
3108                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3109         if (link_speed & ETH_LINK_SPEED_200G)
3110                 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3111         return ret;
3112 }
3113
3114 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3115 {
3116         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
3117
3118         switch (hw_link_speed) {
3119         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3120                 eth_link_speed = ETH_SPEED_NUM_100M;
3121                 break;
3122         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3123                 eth_link_speed = ETH_SPEED_NUM_1G;
3124                 break;
3125         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3126                 eth_link_speed = ETH_SPEED_NUM_2_5G;
3127                 break;
3128         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3129                 eth_link_speed = ETH_SPEED_NUM_10G;
3130                 break;
3131         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3132                 eth_link_speed = ETH_SPEED_NUM_20G;
3133                 break;
3134         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3135                 eth_link_speed = ETH_SPEED_NUM_25G;
3136                 break;
3137         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3138                 eth_link_speed = ETH_SPEED_NUM_40G;
3139                 break;
3140         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3141                 eth_link_speed = ETH_SPEED_NUM_50G;
3142                 break;
3143         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3144                 eth_link_speed = ETH_SPEED_NUM_100G;
3145                 break;
3146         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3147                 eth_link_speed = ETH_SPEED_NUM_200G;
3148                 break;
3149         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3150         default:
3151                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3152                         hw_link_speed);
3153                 break;
3154         }
3155         return eth_link_speed;
3156 }
3157
3158 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3159 {
3160         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3161
3162         switch (hw_link_duplex) {
3163         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3164         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3165                 /* FALLTHROUGH */
3166                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3167                 break;
3168         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3169                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3170                 break;
3171         default:
3172                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3173                         hw_link_duplex);
3174                 break;
3175         }
3176         return eth_link_duplex;
3177 }
3178
3179 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3180 {
3181         int rc = 0;
3182         struct bnxt_link_info *link_info = bp->link_info;
3183
3184         rc = bnxt_hwrm_port_phy_qcaps(bp);
3185         if (rc)
3186                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3187
3188         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3189         if (rc) {
3190                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3191                 goto exit;
3192         }
3193
3194         if (link_info->link_speed)
3195                 link->link_speed =
3196                         bnxt_parse_hw_link_speed(link_info->link_speed);
3197         else
3198                 link->link_speed = ETH_SPEED_NUM_NONE;
3199         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3200         link->link_status = link_info->link_up;
3201         link->link_autoneg = link_info->auto_mode ==
3202                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3203                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3204 exit:
3205         return rc;
3206 }
3207
3208 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3209 {
3210         int rc = 0;
3211         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3212         struct bnxt_link_info link_req;
3213         uint16_t speed, autoneg;
3214
3215         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3216                 return 0;
3217
3218         rc = bnxt_validate_link_speed(bp);
3219         if (rc)
3220                 goto error;
3221
3222         memset(&link_req, 0, sizeof(link_req));
3223         link_req.link_up = link_up;
3224         if (!link_up)
3225                 goto port_phy_cfg;
3226
3227         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3228         if (BNXT_CHIP_P5(bp) &&
3229             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3230                 /* 40G is not supported as part of media auto detect.
3231                  * The speed should be forced and autoneg disabled
3232                  * to configure 40G speed.
3233                  */
3234                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3235                 autoneg = 0;
3236         }
3237
3238         /* No auto speeds and no auto_pam4_link. Disable autoneg */
3239         if (bp->link_info->auto_link_speed == 0 &&
3240             bp->link_info->link_signal_mode &&
3241             bp->link_info->auto_pam4_link_speeds == 0)
3242                 autoneg = 0;
3243
3244         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3245                                           bp->link_info->link_signal_mode);
3246         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3247         /* Autoneg can be done only when the FW allows. */
3248         if (autoneg == 1 && bp->link_info->support_auto_speeds) {
3249                 link_req.phy_flags |=
3250                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3251                 link_req.auto_link_speed_mask =
3252                         bnxt_parse_eth_link_speed_mask(bp,
3253                                                        dev_conf->link_speeds);
3254         } else {
3255                 if (bp->link_info->phy_type ==
3256                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3257                     bp->link_info->phy_type ==
3258                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3259                     bp->link_info->media_type ==
3260                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3261                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3262                         return -EINVAL;
3263                 }
3264
3265                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3266                 /* If user wants a particular speed try that first. */
3267                 if (speed)
3268                         link_req.link_speed = speed;
3269                 else if (bp->link_info->force_pam4_link_speed)
3270                         link_req.link_speed =
3271                                 bp->link_info->force_pam4_link_speed;
3272                 else if (bp->link_info->auto_pam4_link_speeds)
3273                         link_req.link_speed =
3274                                 bp->link_info->auto_pam4_link_speeds;
3275                 else if (bp->link_info->support_pam4_speeds)
3276                         link_req.link_speed =
3277                                 bp->link_info->support_pam4_speeds;
3278                 else if (bp->link_info->force_link_speed)
3279                         link_req.link_speed = bp->link_info->force_link_speed;
3280                 else
3281                         link_req.link_speed = bp->link_info->auto_link_speed;
3282                 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3283                  * zero. Use the auto_link_speed.
3284                  */
3285                 if (bp->link_info->auto_link_speed != 0 &&
3286                     bp->link_info->auto_pam4_link_speeds == 0)
3287                         link_req.link_speed = bp->link_info->auto_link_speed;
3288         }
3289         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3290         link_req.auto_pause = bp->link_info->auto_pause;
3291         link_req.force_pause = bp->link_info->force_pause;
3292
3293 port_phy_cfg:
3294         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3295         if (rc) {
3296                 PMD_DRV_LOG(ERR,
3297                         "Set link config failed with rc %d\n", rc);
3298         }
3299
3300 error:
3301         return rc;
3302 }
3303
3304 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3305 {
3306         struct hwrm_func_qcfg_input req = {0};
3307         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3308         uint16_t flags;
3309         int rc = 0;
3310         bp->func_svif = BNXT_SVIF_INVALID;
3311         uint16_t svif_info;
3312
3313         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3314         req.fid = rte_cpu_to_le_16(0xffff);
3315
3316         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3317
3318         HWRM_CHECK_RESULT();
3319
3320         bp->vlan = rte_le_to_cpu_16(resp->vlan) & ETH_VLAN_ID_MAX;
3321
3322         svif_info = rte_le_to_cpu_16(resp->svif_info);
3323         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3324                 bp->func_svif = svif_info &
3325                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3326
3327         flags = rte_le_to_cpu_16(resp->flags);
3328         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3329                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3330
3331         if (BNXT_VF(bp) &&
3332             !BNXT_VF_IS_TRUSTED(bp) &&
3333             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3334                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3335                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3336         } else if (BNXT_VF(bp) &&
3337                    BNXT_VF_IS_TRUSTED(bp) &&
3338                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3339                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3340                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3341         }
3342
3343         if (mtu)
3344                 *mtu = rte_le_to_cpu_16(resp->admin_mtu);
3345
3346         switch (resp->port_partition_type) {
3347         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3348         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3349         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3350                 /* FALLTHROUGH */
3351                 bp->flags |= BNXT_FLAG_NPAR_PF;
3352                 break;
3353         default:
3354                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3355                 break;
3356         }
3357
3358         bp->legacy_db_size =
3359                 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3360
3361         HWRM_UNLOCK();
3362
3363         return rc;
3364 }
3365
3366 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3367 {
3368         struct hwrm_func_qcfg_input req = {0};
3369         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3370         int rc;
3371
3372         if (!BNXT_VF_IS_TRUSTED(bp))
3373                 return 0;
3374
3375         if (!bp->parent)
3376                 return -EINVAL;
3377
3378         bp->parent->fid = BNXT_PF_FID_INVALID;
3379
3380         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3381
3382         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3383
3384         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3385
3386         HWRM_CHECK_RESULT_SILENT();
3387
3388         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3389         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3390         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3391         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3392
3393         /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3394         if (bp->parent->vnic == 0) {
3395                 PMD_DRV_LOG(DEBUG, "parent VNIC unavailable.\n");
3396                 /* Use hard-coded values appropriate for current Wh+ fw. */
3397                 if (bp->parent->fid == 2)
3398                         bp->parent->vnic = 0x100;
3399                 else
3400                         bp->parent->vnic = 1;
3401         }
3402
3403         HWRM_UNLOCK();
3404
3405         return 0;
3406 }
3407
3408 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3409                                  uint16_t *vnic_id, uint16_t *svif)
3410 {
3411         struct hwrm_func_qcfg_input req = {0};
3412         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3413         uint16_t svif_info;
3414         int rc = 0;
3415
3416         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3417         req.fid = rte_cpu_to_le_16(fid);
3418
3419         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3420
3421         HWRM_CHECK_RESULT();
3422
3423         if (vnic_id)
3424                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3425
3426         svif_info = rte_le_to_cpu_16(resp->svif_info);
3427         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3428                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3429
3430         HWRM_UNLOCK();
3431
3432         return rc;
3433 }
3434
3435 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3436 {
3437         struct hwrm_port_mac_qcfg_input req = {0};
3438         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3439         uint16_t port_svif_info;
3440         int rc;
3441
3442         bp->port_svif = BNXT_SVIF_INVALID;
3443
3444         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3445                 return 0;
3446
3447         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3448
3449         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3450
3451         HWRM_CHECK_RESULT_SILENT();
3452
3453         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3454         if (port_svif_info &
3455             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3456                 bp->port_svif = port_svif_info &
3457                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3458
3459         HWRM_UNLOCK();
3460
3461         return 0;
3462 }
3463
3464 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3465                                  struct bnxt_pf_resource_info *pf_resc)
3466 {
3467         struct hwrm_func_cfg_input req = {0};
3468         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3469         uint32_t enables;
3470         int rc;
3471
3472         enables = HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
3473                   HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU |
3474                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3475                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3476                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3477                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3478                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3479                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3480                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3481                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3482
3483         if (BNXT_HAS_RING_GRPS(bp)) {
3484                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3485                 req.num_hw_ring_grps =
3486                         rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3487         } else if (BNXT_HAS_NQ(bp)) {
3488                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3489                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3490         }
3491
3492         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3493         req.admin_mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3494         req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
3495         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3496         req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3497         req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3498         req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3499         req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3500         req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3501         req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3502         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3503         req.fid = rte_cpu_to_le_16(0xffff);
3504         req.enables = rte_cpu_to_le_32(enables);
3505
3506         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3507
3508         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3509
3510         HWRM_CHECK_RESULT();
3511         HWRM_UNLOCK();
3512
3513         return rc;
3514 }
3515
3516 /* min values are the guaranteed resources and max values are subject
3517  * to availability. The strategy for now is to keep both min & max
3518  * values the same.
3519  */
3520 static void
3521 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3522                               struct hwrm_func_vf_resource_cfg_input *req,
3523                               int num_vfs)
3524 {
3525         req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3526                                                (num_vfs + 1));
3527         req->min_rsscos_ctx = req->max_rsscos_ctx;
3528         req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3529         req->min_stat_ctx = req->max_stat_ctx;
3530         req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3531                                                (num_vfs + 1));
3532         req->min_cmpl_rings = req->max_cmpl_rings;
3533         req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3534         req->min_tx_rings = req->max_tx_rings;
3535         req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3536         req->min_rx_rings = req->max_rx_rings;
3537         req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3538         req->min_l2_ctxs = req->max_l2_ctxs;
3539         /* TODO: For now, do not support VMDq/RFS on VFs. */
3540         req->max_vnics = rte_cpu_to_le_16(1);
3541         req->min_vnics = req->max_vnics;
3542         req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3543                                                  (num_vfs + 1));
3544         req->min_hw_ring_grps = req->max_hw_ring_grps;
3545         req->flags =
3546          rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3547 }
3548
3549 static void
3550 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3551                               struct hwrm_func_cfg_input *req,
3552                               int num_vfs)
3553 {
3554         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
3555                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3556                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3557                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3558                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3559                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3560                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3561                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3562                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3563                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3564
3565         req->admin_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3566                                           RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3567                                           BNXT_NUM_VLANS);
3568         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3569         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3570                                                 (num_vfs + 1));
3571         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3572         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3573                                                (num_vfs + 1));
3574         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3575         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3576         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3577         /* TODO: For now, do not support VMDq/RFS on VFs. */
3578         req->num_vnics = rte_cpu_to_le_16(1);
3579         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3580                                                  (num_vfs + 1));
3581 }
3582
3583 /* Update the port wide resource values based on how many resources
3584  * got allocated to the VF.
3585  */
3586 static int bnxt_update_max_resources(struct bnxt *bp,
3587                                      int vf)
3588 {
3589         struct hwrm_func_qcfg_input req = {0};
3590         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3591         int rc;
3592
3593         /* Get the actual allocated values now */
3594         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3595         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3596         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3597         HWRM_CHECK_RESULT();
3598
3599         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3600         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3601         bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3602         bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3603         bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3604         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3605         bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3606
3607         HWRM_UNLOCK();
3608
3609         return 0;
3610 }
3611
3612 /* Update the PF resource values based on how many resources
3613  * got allocated to it.
3614  */
3615 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3616 {
3617         struct hwrm_func_qcfg_input req = {0};
3618         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3619         int rc;
3620
3621         /* Get the actual allocated values now */
3622         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3623         req.fid = rte_cpu_to_le_16(0xffff);
3624         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3625         HWRM_CHECK_RESULT();
3626
3627         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3628         bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3629         bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3630         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3631         bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3632         bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3633         bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3634         bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3635
3636         HWRM_UNLOCK();
3637
3638         return 0;
3639 }
3640
3641 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3642 {
3643         struct hwrm_func_qcfg_input req = {0};
3644         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3645         int rc;
3646
3647         /* Check for zero MAC address */
3648         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3649         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3650         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3651         HWRM_CHECK_RESULT();
3652         rc = rte_le_to_cpu_16(resp->vlan);
3653
3654         HWRM_UNLOCK();
3655
3656         return rc;
3657 }
3658
3659 static int bnxt_query_pf_resources(struct bnxt *bp,
3660                                    struct bnxt_pf_resource_info *pf_resc)
3661 {
3662         struct hwrm_func_qcfg_input req = {0};
3663         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3664         int rc;
3665
3666         /* And copy the allocated numbers into the pf struct */
3667         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3668         req.fid = rte_cpu_to_le_16(0xffff);
3669         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3670         HWRM_CHECK_RESULT();
3671
3672         pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3673         pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3674         pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3675         pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3676         pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3677         pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3678         pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3679         bp->pf->evb_mode = resp->evb_mode;
3680
3681         HWRM_UNLOCK();
3682
3683         return rc;
3684 }
3685
3686 static void
3687 bnxt_calculate_pf_resources(struct bnxt *bp,
3688                             struct bnxt_pf_resource_info *pf_resc,
3689                             int num_vfs)
3690 {
3691         if (!num_vfs) {
3692                 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3693                 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3694                 pf_resc->num_cp_rings = bp->max_cp_rings;
3695                 pf_resc->num_tx_rings = bp->max_tx_rings;
3696                 pf_resc->num_rx_rings = bp->max_rx_rings;
3697                 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3698                 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3699
3700                 return;
3701         }
3702
3703         pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3704                                    bp->max_rsscos_ctx % (num_vfs + 1);
3705         pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3706                                  bp->max_stat_ctx % (num_vfs + 1);
3707         pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3708                                 bp->max_cp_rings % (num_vfs + 1);
3709         pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3710                                 bp->max_tx_rings % (num_vfs + 1);
3711         pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3712                                 bp->max_rx_rings % (num_vfs + 1);
3713         pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3714                                bp->max_l2_ctx % (num_vfs + 1);
3715         pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3716                                     bp->max_ring_grps % (num_vfs + 1);
3717 }
3718
3719 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3720 {
3721         struct bnxt_pf_resource_info pf_resc = { 0 };
3722         int rc;
3723
3724         if (!BNXT_PF(bp)) {
3725                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3726                 return -EINVAL;
3727         }
3728
3729         rc = bnxt_hwrm_func_qcaps(bp);
3730         if (rc)
3731                 return rc;
3732
3733         bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3734
3735         bp->pf->func_cfg_flags &=
3736                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3737                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3738         bp->pf->func_cfg_flags |=
3739                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3740
3741         rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3742         if (rc)
3743                 return rc;
3744
3745         rc = bnxt_update_max_resources_pf_only(bp);
3746
3747         return rc;
3748 }
3749
3750 static int
3751 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3752 {
3753         size_t req_buf_sz, sz;
3754         int i, rc;
3755
3756         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3757         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3758                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3759         if (bp->pf->vf_req_buf == NULL) {
3760                 return -ENOMEM;
3761         }
3762
3763         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3764                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3765
3766         for (i = 0; i < num_vfs; i++)
3767                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3768                                              (i * HWRM_MAX_REQ_LEN);
3769
3770         rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3771         if (rc)
3772                 rte_free(bp->pf->vf_req_buf);
3773
3774         return rc;
3775 }
3776
3777 static int
3778 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3779 {
3780         struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3781         struct hwrm_func_vf_resource_cfg_input req = {0};
3782         int i, rc = 0;
3783
3784         bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3785         bp->pf->active_vfs = 0;
3786         for (i = 0; i < num_vfs; i++) {
3787                 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3788                 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3789                 rc = bnxt_hwrm_send_message(bp,
3790                                             &req,
3791                                             sizeof(req),
3792                                             BNXT_USE_CHIMP_MB);
3793                 if (rc || resp->error_code) {
3794                         PMD_DRV_LOG(ERR,
3795                                 "Failed to initialize VF %d\n", i);
3796                         PMD_DRV_LOG(ERR,
3797                                 "Not all VFs available. (%d, %d)\n",
3798                                 rc, resp->error_code);
3799                         HWRM_UNLOCK();
3800
3801                         /* If the first VF configuration itself fails,
3802                          * unregister the vf_fwd_request buffer.
3803                          */
3804                         if (i == 0)
3805                                 bnxt_hwrm_func_buf_unrgtr(bp);
3806                         break;
3807                 }
3808                 HWRM_UNLOCK();
3809
3810                 /* Update the max resource values based on the resource values
3811                  * allocated to the VF.
3812                  */
3813                 bnxt_update_max_resources(bp, i);
3814                 bp->pf->active_vfs++;
3815                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3816         }
3817
3818         return 0;
3819 }
3820
3821 static int
3822 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3823 {
3824         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3825         struct hwrm_func_cfg_input req = {0};
3826         int i, rc;
3827
3828         bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3829
3830         bp->pf->active_vfs = 0;
3831         for (i = 0; i < num_vfs; i++) {
3832                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3833                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3834                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3835                 rc = bnxt_hwrm_send_message(bp,
3836                                             &req,
3837                                             sizeof(req),
3838                                             BNXT_USE_CHIMP_MB);
3839
3840                 /* Clear enable flag for next pass */
3841                 req.enables &= ~rte_cpu_to_le_32(
3842                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3843
3844                 if (rc || resp->error_code) {
3845                         PMD_DRV_LOG(ERR,
3846                                 "Failed to initialize VF %d\n", i);
3847                         PMD_DRV_LOG(ERR,
3848                                 "Not all VFs available. (%d, %d)\n",
3849                                 rc, resp->error_code);
3850                         HWRM_UNLOCK();
3851
3852                         /* If the first VF configuration itself fails,
3853                          * unregister the vf_fwd_request buffer.
3854                          */
3855                         if (i == 0)
3856                                 bnxt_hwrm_func_buf_unrgtr(bp);
3857                         break;
3858                 }
3859
3860                 HWRM_UNLOCK();
3861
3862                 /* Update the max resource values based on the resource values
3863                  * allocated to the VF.
3864                  */
3865                 bnxt_update_max_resources(bp, i);
3866                 bp->pf->active_vfs++;
3867                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3868         }
3869
3870         return 0;
3871 }
3872
3873 static void
3874 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3875 {
3876         if (bp->flags & BNXT_FLAG_NEW_RM)
3877                 bnxt_process_vf_resc_config_new(bp, num_vfs);
3878         else
3879                 bnxt_process_vf_resc_config_old(bp, num_vfs);
3880 }
3881
3882 static void
3883 bnxt_update_pf_resources(struct bnxt *bp,
3884                          struct bnxt_pf_resource_info *pf_resc)
3885 {
3886         bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3887         bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3888         bp->max_cp_rings = pf_resc->num_cp_rings;
3889         bp->max_tx_rings = pf_resc->num_tx_rings;
3890         bp->max_rx_rings = pf_resc->num_rx_rings;
3891         bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3892 }
3893
3894 static int32_t
3895 bnxt_configure_pf_resources(struct bnxt *bp,
3896                             struct bnxt_pf_resource_info *pf_resc)
3897 {
3898         /*
3899          * We're using STD_TX_RING_MODE here which will limit the TX
3900          * rings. This will allow QoS to function properly. Not setting this
3901          * will cause PF rings to break bandwidth settings.
3902          */
3903         bp->pf->func_cfg_flags &=
3904                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3905                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3906         bp->pf->func_cfg_flags |=
3907                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3908         return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3909 }
3910
3911 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3912 {
3913         struct bnxt_pf_resource_info pf_resc = { 0 };
3914         int rc;
3915
3916         if (!BNXT_PF(bp)) {
3917                 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3918                 return -EINVAL;
3919         }
3920
3921         rc = bnxt_hwrm_func_qcaps(bp);
3922         if (rc)
3923                 return rc;
3924
3925         bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3926
3927         rc = bnxt_configure_pf_resources(bp, &pf_resc);
3928         if (rc)
3929                 return rc;
3930
3931         rc = bnxt_query_pf_resources(bp, &pf_resc);
3932         if (rc)
3933                 return rc;
3934
3935         /*
3936          * Now, create and register a buffer to hold forwarded VF requests
3937          */
3938         rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3939         if (rc)
3940                 return rc;
3941
3942         bnxt_configure_vf_resources(bp, num_vfs);
3943
3944         bnxt_update_pf_resources(bp, &pf_resc);
3945
3946         return 0;
3947 }
3948
3949 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3950 {
3951         struct hwrm_func_cfg_input req = {0};
3952         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3953         int rc;
3954
3955         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3956
3957         req.fid = rte_cpu_to_le_16(0xffff);
3958         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3959         req.evb_mode = bp->pf->evb_mode;
3960
3961         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3962         HWRM_CHECK_RESULT();
3963         HWRM_UNLOCK();
3964
3965         return rc;
3966 }
3967
3968 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3969                                 uint8_t tunnel_type)
3970 {
3971         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3972         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3973         int rc = 0;
3974
3975         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3976         req.tunnel_type = tunnel_type;
3977         req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3978         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3979         HWRM_CHECK_RESULT();
3980
3981         switch (tunnel_type) {
3982         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3983                 bp->vxlan_fw_dst_port_id =
3984                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3985                 bp->vxlan_port = port;
3986                 break;
3987         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3988                 bp->geneve_fw_dst_port_id =
3989                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3990                 bp->geneve_port = port;
3991                 break;
3992         default:
3993                 break;
3994         }
3995
3996         HWRM_UNLOCK();
3997
3998         return rc;
3999 }
4000
4001 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
4002                                 uint8_t tunnel_type)
4003 {
4004         struct hwrm_tunnel_dst_port_free_input req = {0};
4005         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
4006         int rc = 0;
4007
4008         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
4009
4010         req.tunnel_type = tunnel_type;
4011         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
4012         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4013
4014         HWRM_CHECK_RESULT();
4015         HWRM_UNLOCK();
4016
4017         if (tunnel_type ==
4018             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4019                 bp->vxlan_port = 0;
4020                 bp->vxlan_port_cnt = 0;
4021         }
4022
4023         if (tunnel_type ==
4024             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4025                 bp->geneve_port = 0;
4026                 bp->geneve_port_cnt = 0;
4027         }
4028
4029         return rc;
4030 }
4031
4032 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4033                                         uint32_t flags)
4034 {
4035         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4036         struct hwrm_func_cfg_input req = {0};
4037         int rc;
4038
4039         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4040
4041         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4042         req.flags = rte_cpu_to_le_32(flags);
4043         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4044
4045         HWRM_CHECK_RESULT();
4046         HWRM_UNLOCK();
4047
4048         return rc;
4049 }
4050
4051 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4052 {
4053         uint32_t *flag = flagp;
4054
4055         vnic->flags = *flag;
4056 }
4057
4058 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4059 {
4060         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4061 }
4062
4063 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4064 {
4065         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4066         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4067         int rc;
4068
4069         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4070
4071         req.req_buf_num_pages = rte_cpu_to_le_16(1);
4072         req.req_buf_page_size =
4073                 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4074         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4075         req.req_buf_page_addr0 =
4076                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4077         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4078                 PMD_DRV_LOG(ERR,
4079                         "unable to map buffer address to physical memory\n");
4080                 HWRM_UNLOCK();
4081                 return -ENOMEM;
4082         }
4083
4084         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4085
4086         HWRM_CHECK_RESULT();
4087         HWRM_UNLOCK();
4088
4089         return rc;
4090 }
4091
4092 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4093 {
4094         int rc = 0;
4095         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4096         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4097
4098         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4099                 return 0;
4100
4101         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4102
4103         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4104
4105         HWRM_CHECK_RESULT();
4106         HWRM_UNLOCK();
4107
4108         return rc;
4109 }
4110
4111 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4112 {
4113         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4114         struct hwrm_func_cfg_input req = {0};
4115         int rc;
4116
4117         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4118
4119         req.fid = rte_cpu_to_le_16(0xffff);
4120         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4121         req.enables = rte_cpu_to_le_32(
4122                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4123         req.async_event_cr = rte_cpu_to_le_16(
4124                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4125         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4126
4127         HWRM_CHECK_RESULT();
4128         HWRM_UNLOCK();
4129
4130         return rc;
4131 }
4132
4133 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4134 {
4135         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4136         struct hwrm_func_vf_cfg_input req = {0};
4137         int rc;
4138
4139         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4140
4141         req.enables = rte_cpu_to_le_32(
4142                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4143         req.async_event_cr = rte_cpu_to_le_16(
4144                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4145         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4146
4147         HWRM_CHECK_RESULT();
4148         HWRM_UNLOCK();
4149
4150         return rc;
4151 }
4152
4153 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4154 {
4155         struct hwrm_func_cfg_input req = {0};
4156         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4157         uint16_t dflt_vlan, fid;
4158         uint32_t func_cfg_flags;
4159         int rc = 0;
4160
4161         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4162
4163         if (is_vf) {
4164                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4165                 fid = bp->pf->vf_info[vf].fid;
4166                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4167         } else {
4168                 fid = rte_cpu_to_le_16(0xffff);
4169                 func_cfg_flags = bp->pf->func_cfg_flags;
4170                 dflt_vlan = bp->vlan;
4171         }
4172
4173         req.flags = rte_cpu_to_le_32(func_cfg_flags);
4174         req.fid = rte_cpu_to_le_16(fid);
4175         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4176         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4177
4178         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4179
4180         HWRM_CHECK_RESULT();
4181         HWRM_UNLOCK();
4182
4183         return rc;
4184 }
4185
4186 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4187                         uint16_t max_bw, uint16_t enables)
4188 {
4189         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4190         struct hwrm_func_cfg_input req = {0};
4191         int rc;
4192
4193         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4194
4195         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4196         req.enables |= rte_cpu_to_le_32(enables);
4197         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4198         req.max_bw = rte_cpu_to_le_32(max_bw);
4199         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4200
4201         HWRM_CHECK_RESULT();
4202         HWRM_UNLOCK();
4203
4204         return rc;
4205 }
4206
4207 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4208 {
4209         struct hwrm_func_cfg_input req = {0};
4210         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4211         int rc = 0;
4212
4213         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4214
4215         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4216         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4217         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4218         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4219
4220         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4221
4222         HWRM_CHECK_RESULT();
4223         HWRM_UNLOCK();
4224
4225         return rc;
4226 }
4227
4228 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4229 {
4230         int rc;
4231
4232         if (BNXT_PF(bp))
4233                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4234         else
4235                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4236
4237         return rc;
4238 }
4239
4240 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4241                               void *encaped, size_t ec_size)
4242 {
4243         int rc = 0;
4244         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4245         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4246
4247         if (ec_size > sizeof(req.encap_request))
4248                 return -1;
4249
4250         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4251
4252         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4253         memcpy(req.encap_request, encaped, ec_size);
4254
4255         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4256
4257         HWRM_CHECK_RESULT();
4258         HWRM_UNLOCK();
4259
4260         return rc;
4261 }
4262
4263 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4264                                        struct rte_ether_addr *mac)
4265 {
4266         struct hwrm_func_qcfg_input req = {0};
4267         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4268         int rc;
4269
4270         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4271
4272         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4273         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4274
4275         HWRM_CHECK_RESULT();
4276
4277         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4278
4279         HWRM_UNLOCK();
4280
4281         return rc;
4282 }
4283
4284 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4285                             void *encaped, size_t ec_size)
4286 {
4287         int rc = 0;
4288         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4289         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4290
4291         if (ec_size > sizeof(req.encap_request))
4292                 return -1;
4293
4294         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4295
4296         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4297         memcpy(req.encap_request, encaped, ec_size);
4298
4299         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4300
4301         HWRM_CHECK_RESULT();
4302         HWRM_UNLOCK();
4303
4304         return rc;
4305 }
4306
4307 static void bnxt_update_prev_stat(uint64_t *cntr, uint64_t *prev_cntr)
4308 {
4309         /* One of the HW stat values that make up this counter was zero as
4310          * returned by HW in this iteration, so use the previous
4311          * iteration's counter value
4312          */
4313         if (*prev_cntr && *cntr == 0)
4314                 *cntr = *prev_cntr;
4315         else
4316                 *prev_cntr = *cntr;
4317 }
4318
4319 int bnxt_hwrm_ring_stats(struct bnxt *bp, uint32_t cid, int idx,
4320                          struct bnxt_ring_stats *ring_stats, bool rx)
4321 {
4322         int rc = 0;
4323         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4324         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4325
4326         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4327
4328         req.stat_ctx_id = rte_cpu_to_le_32(cid);
4329
4330         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4331
4332         HWRM_CHECK_RESULT();
4333
4334         if (rx) {
4335                 struct bnxt_ring_stats *prev_stats = &bp->prev_rx_ring_stats[idx];
4336
4337                 ring_stats->rx_ucast_pkts = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4338                 bnxt_update_prev_stat(&ring_stats->rx_ucast_pkts,
4339                                       &prev_stats->rx_ucast_pkts);
4340
4341                 ring_stats->rx_mcast_pkts = rte_le_to_cpu_64(resp->rx_mcast_pkts);
4342                 bnxt_update_prev_stat(&ring_stats->rx_mcast_pkts,
4343                                       &prev_stats->rx_mcast_pkts);
4344
4345                 ring_stats->rx_bcast_pkts = rte_le_to_cpu_64(resp->rx_bcast_pkts);
4346                 bnxt_update_prev_stat(&ring_stats->rx_bcast_pkts,
4347                                       &prev_stats->rx_bcast_pkts);
4348
4349                 ring_stats->rx_ucast_bytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4350                 bnxt_update_prev_stat(&ring_stats->rx_ucast_bytes,
4351                                       &prev_stats->rx_ucast_bytes);
4352
4353                 ring_stats->rx_mcast_bytes = rte_le_to_cpu_64(resp->rx_mcast_bytes);
4354                 bnxt_update_prev_stat(&ring_stats->rx_mcast_bytes,
4355                                       &prev_stats->rx_mcast_bytes);
4356
4357                 ring_stats->rx_bcast_bytes = rte_le_to_cpu_64(resp->rx_bcast_bytes);
4358                 bnxt_update_prev_stat(&ring_stats->rx_bcast_bytes,
4359                                       &prev_stats->rx_bcast_bytes);
4360
4361                 ring_stats->rx_discard_pkts = rte_le_to_cpu_64(resp->rx_discard_pkts);
4362                 bnxt_update_prev_stat(&ring_stats->rx_discard_pkts,
4363                                       &prev_stats->rx_discard_pkts);
4364
4365                 ring_stats->rx_error_pkts = rte_le_to_cpu_64(resp->rx_error_pkts);
4366                 bnxt_update_prev_stat(&ring_stats->rx_error_pkts,
4367                                       &prev_stats->rx_error_pkts);
4368
4369                 ring_stats->rx_agg_pkts = rte_le_to_cpu_64(resp->rx_agg_pkts);
4370                 bnxt_update_prev_stat(&ring_stats->rx_agg_pkts,
4371                                       &prev_stats->rx_agg_pkts);
4372
4373                 ring_stats->rx_agg_bytes = rte_le_to_cpu_64(resp->rx_agg_bytes);
4374                 bnxt_update_prev_stat(&ring_stats->rx_agg_bytes,
4375                                       &prev_stats->rx_agg_bytes);
4376
4377                 ring_stats->rx_agg_events = rte_le_to_cpu_64(resp->rx_agg_events);
4378                 bnxt_update_prev_stat(&ring_stats->rx_agg_events,
4379                                       &prev_stats->rx_agg_events);
4380
4381                 ring_stats->rx_agg_aborts = rte_le_to_cpu_64(resp->rx_agg_aborts);
4382                 bnxt_update_prev_stat(&ring_stats->rx_agg_aborts,
4383                                       &prev_stats->rx_agg_aborts);
4384         } else {
4385                 struct bnxt_ring_stats *prev_stats = &bp->prev_tx_ring_stats[idx];
4386
4387                 ring_stats->tx_ucast_pkts = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4388                 bnxt_update_prev_stat(&ring_stats->tx_ucast_pkts,
4389                                       &prev_stats->tx_ucast_pkts);
4390
4391                 ring_stats->tx_mcast_pkts = rte_le_to_cpu_64(resp->tx_mcast_pkts);
4392                 bnxt_update_prev_stat(&ring_stats->tx_mcast_pkts,
4393                                       &prev_stats->tx_mcast_pkts);
4394
4395                 ring_stats->tx_bcast_pkts = rte_le_to_cpu_64(resp->tx_bcast_pkts);
4396                 bnxt_update_prev_stat(&ring_stats->tx_bcast_pkts,
4397                                       &prev_stats->tx_bcast_pkts);
4398
4399                 ring_stats->tx_ucast_bytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4400                 bnxt_update_prev_stat(&ring_stats->tx_ucast_bytes,
4401                                       &prev_stats->tx_ucast_bytes);
4402
4403                 ring_stats->tx_mcast_bytes = rte_le_to_cpu_64(resp->tx_mcast_bytes);
4404                 bnxt_update_prev_stat(&ring_stats->tx_mcast_bytes,
4405                                       &prev_stats->tx_mcast_bytes);
4406
4407                 ring_stats->tx_bcast_bytes = rte_le_to_cpu_64(resp->tx_bcast_bytes);
4408                 bnxt_update_prev_stat(&ring_stats->tx_bcast_bytes,
4409                                       &prev_stats->tx_bcast_bytes);
4410
4411                 ring_stats->tx_discard_pkts = rte_le_to_cpu_64(resp->tx_discard_pkts);
4412                 bnxt_update_prev_stat(&ring_stats->tx_discard_pkts,
4413                                       &prev_stats->tx_discard_pkts);
4414         }
4415
4416         HWRM_UNLOCK();
4417
4418         return rc;
4419 }
4420
4421 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4422 {
4423         struct hwrm_port_qstats_input req = {0};
4424         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4425         struct bnxt_pf_info *pf = bp->pf;
4426         int rc;
4427
4428         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4429
4430         req.port_id = rte_cpu_to_le_16(pf->port_id);
4431         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4432         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4433         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4434
4435         HWRM_CHECK_RESULT();
4436         HWRM_UNLOCK();
4437
4438         return rc;
4439 }
4440
4441 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4442 {
4443         struct hwrm_port_clr_stats_input req = {0};
4444         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4445         struct bnxt_pf_info *pf = bp->pf;
4446         int rc;
4447
4448         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4449         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4450             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4451                 return 0;
4452
4453         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4454
4455         req.port_id = rte_cpu_to_le_16(pf->port_id);
4456         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4457
4458         HWRM_CHECK_RESULT();
4459         HWRM_UNLOCK();
4460
4461         return rc;
4462 }
4463
4464 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4465 {
4466         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4467         struct hwrm_port_led_qcaps_input req = {0};
4468         int rc;
4469
4470         if (BNXT_VF(bp))
4471                 return 0;
4472
4473         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4474         req.port_id = bp->pf->port_id;
4475         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4476
4477         HWRM_CHECK_RESULT_SILENT();
4478
4479         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4480                 unsigned int i;
4481
4482                 bp->leds->num_leds = resp->num_leds;
4483                 memcpy(bp->leds, &resp->led0_id,
4484                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4485                 for (i = 0; i < bp->leds->num_leds; i++) {
4486                         struct bnxt_led_info *led = &bp->leds[i];
4487
4488                         uint16_t caps = led->led_state_caps;
4489
4490                         if (!led->led_group_id ||
4491                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4492                                 bp->leds->num_leds = 0;
4493                                 break;
4494                         }
4495                 }
4496         }
4497
4498         HWRM_UNLOCK();
4499
4500         return rc;
4501 }
4502
4503 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4504 {
4505         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4506         struct hwrm_port_led_cfg_input req = {0};
4507         struct bnxt_led_cfg *led_cfg;
4508         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4509         uint16_t duration = 0;
4510         int rc, i;
4511
4512         if (!bp->leds->num_leds || BNXT_VF(bp))
4513                 return -EOPNOTSUPP;
4514
4515         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4516
4517         if (led_on) {
4518                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4519                 duration = rte_cpu_to_le_16(500);
4520         }
4521         req.port_id = bp->pf->port_id;
4522         req.num_leds = bp->leds->num_leds;
4523         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4524         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4525                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4526                 led_cfg->led_id = bp->leds[i].led_id;
4527                 led_cfg->led_state = led_state;
4528                 led_cfg->led_blink_on = duration;
4529                 led_cfg->led_blink_off = duration;
4530                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4531         }
4532
4533         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4534
4535         HWRM_CHECK_RESULT();
4536         HWRM_UNLOCK();
4537
4538         return rc;
4539 }
4540
4541 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4542                                uint32_t *length)
4543 {
4544         int rc;
4545         struct hwrm_nvm_get_dir_info_input req = {0};
4546         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4547
4548         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4549
4550         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4551
4552         HWRM_CHECK_RESULT();
4553
4554         *entries = rte_le_to_cpu_32(resp->entries);
4555         *length = rte_le_to_cpu_32(resp->entry_length);
4556
4557         HWRM_UNLOCK();
4558         return rc;
4559 }
4560
4561 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4562 {
4563         int rc;
4564         uint32_t dir_entries;
4565         uint32_t entry_length;
4566         uint8_t *buf;
4567         size_t buflen;
4568         rte_iova_t dma_handle;
4569         struct hwrm_nvm_get_dir_entries_input req = {0};
4570         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4571
4572         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4573         if (rc != 0)
4574                 return rc;
4575
4576         *data++ = dir_entries;
4577         *data++ = entry_length;
4578         len -= 2;
4579         memset(data, 0xff, len);
4580
4581         buflen = dir_entries * entry_length;
4582         buf = rte_malloc("nvm_dir", buflen, 0);
4583         if (buf == NULL)
4584                 return -ENOMEM;
4585         dma_handle = rte_malloc_virt2iova(buf);
4586         if (dma_handle == RTE_BAD_IOVA) {
4587                 rte_free(buf);
4588                 PMD_DRV_LOG(ERR,
4589                         "unable to map response address to physical memory\n");
4590                 return -ENOMEM;
4591         }
4592         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4593         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4594         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4595
4596         if (rc == 0)
4597                 memcpy(data, buf, len > buflen ? buflen : len);
4598
4599         rte_free(buf);
4600         HWRM_CHECK_RESULT();
4601         HWRM_UNLOCK();
4602
4603         return rc;
4604 }
4605
4606 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4607                              uint32_t offset, uint32_t length,
4608                              uint8_t *data)
4609 {
4610         int rc;
4611         uint8_t *buf;
4612         rte_iova_t dma_handle;
4613         struct hwrm_nvm_read_input req = {0};
4614         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4615
4616         buf = rte_malloc("nvm_item", length, 0);
4617         if (!buf)
4618                 return -ENOMEM;
4619
4620         dma_handle = rte_malloc_virt2iova(buf);
4621         if (dma_handle == RTE_BAD_IOVA) {
4622                 rte_free(buf);
4623                 PMD_DRV_LOG(ERR,
4624                         "unable to map response address to physical memory\n");
4625                 return -ENOMEM;
4626         }
4627         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4628         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4629         req.dir_idx = rte_cpu_to_le_16(index);
4630         req.offset = rte_cpu_to_le_32(offset);
4631         req.len = rte_cpu_to_le_32(length);
4632         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4633         if (rc == 0)
4634                 memcpy(data, buf, length);
4635
4636         rte_free(buf);
4637         HWRM_CHECK_RESULT();
4638         HWRM_UNLOCK();
4639
4640         return rc;
4641 }
4642
4643 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4644 {
4645         int rc;
4646         struct hwrm_nvm_erase_dir_entry_input req = {0};
4647         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4648
4649         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4650         req.dir_idx = rte_cpu_to_le_16(index);
4651         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4652         HWRM_CHECK_RESULT();
4653         HWRM_UNLOCK();
4654
4655         return rc;
4656 }
4657
4658 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4659                           uint16_t dir_ordinal, uint16_t dir_ext,
4660                           uint16_t dir_attr, const uint8_t *data,
4661                           size_t data_len)
4662 {
4663         int rc;
4664         struct hwrm_nvm_write_input req = {0};
4665         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4666         rte_iova_t dma_handle;
4667         uint8_t *buf;
4668
4669         buf = rte_malloc("nvm_write", data_len, 0);
4670         if (!buf)
4671                 return -ENOMEM;
4672
4673         dma_handle = rte_malloc_virt2iova(buf);
4674         if (dma_handle == RTE_BAD_IOVA) {
4675                 rte_free(buf);
4676                 PMD_DRV_LOG(ERR,
4677                         "unable to map response address to physical memory\n");
4678                 return -ENOMEM;
4679         }
4680         memcpy(buf, data, data_len);
4681
4682         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4683
4684         req.dir_type = rte_cpu_to_le_16(dir_type);
4685         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4686         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4687         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4688         req.dir_data_length = rte_cpu_to_le_32(data_len);
4689         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4690
4691         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4692
4693         rte_free(buf);
4694         HWRM_CHECK_RESULT();
4695         HWRM_UNLOCK();
4696
4697         return rc;
4698 }
4699
4700 static void
4701 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4702 {
4703         uint32_t *count = cbdata;
4704
4705         *count = *count + 1;
4706 }
4707
4708 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4709                                      struct bnxt_vnic_info *vnic __rte_unused)
4710 {
4711         return 0;
4712 }
4713
4714 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4715 {
4716         uint32_t count = 0;
4717
4718         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4719             &count, bnxt_vnic_count_hwrm_stub);
4720
4721         return count;
4722 }
4723
4724 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4725                                         uint16_t *vnic_ids)
4726 {
4727         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4728         struct hwrm_func_vf_vnic_ids_query_output *resp =
4729                                                 bp->hwrm_cmd_resp_addr;
4730         int rc;
4731
4732         /* First query all VNIC ids */
4733         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4734
4735         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4736         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4737         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4738
4739         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4740                 HWRM_UNLOCK();
4741                 PMD_DRV_LOG(ERR,
4742                 "unable to map VNIC ID table address to physical memory\n");
4743                 return -ENOMEM;
4744         }
4745         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4746         HWRM_CHECK_RESULT();
4747         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4748
4749         HWRM_UNLOCK();
4750
4751         return rc;
4752 }
4753
4754 /*
4755  * This function queries the VNIC IDs  for a specified VF. It then calls
4756  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4757  * Then it calls the hwrm_cb function to program this new vnic configuration.
4758  */
4759 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4760         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4761         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4762 {
4763         struct bnxt_vnic_info vnic;
4764         int rc = 0;
4765         int i, num_vnic_ids;
4766         uint16_t *vnic_ids;
4767         size_t vnic_id_sz;
4768         size_t sz;
4769
4770         /* First query all VNIC ids */
4771         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4772         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4773                         RTE_CACHE_LINE_SIZE);
4774         if (vnic_ids == NULL)
4775                 return -ENOMEM;
4776
4777         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4778                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4779
4780         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4781
4782         if (num_vnic_ids < 0)
4783                 return num_vnic_ids;
4784
4785         /* Retrieve VNIC, update bd_stall then update */
4786
4787         for (i = 0; i < num_vnic_ids; i++) {
4788                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4789                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4790                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4791                 if (rc)
4792                         break;
4793                 if (vnic.mru <= 4)      /* Indicates unallocated */
4794                         continue;
4795
4796                 vnic_cb(&vnic, cbdata);
4797
4798                 rc = hwrm_cb(bp, &vnic);
4799                 if (rc)
4800                         break;
4801         }
4802
4803         rte_free(vnic_ids);
4804
4805         return rc;
4806 }
4807
4808 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4809                                               bool on)
4810 {
4811         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4812         struct hwrm_func_cfg_input req = {0};
4813         int rc;
4814
4815         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4816
4817         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4818         req.enables |= rte_cpu_to_le_32(
4819                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4820         req.vlan_antispoof_mode = on ?
4821                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4822                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4823         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4824
4825         HWRM_CHECK_RESULT();
4826         HWRM_UNLOCK();
4827
4828         return rc;
4829 }
4830
4831 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4832 {
4833         struct bnxt_vnic_info vnic;
4834         uint16_t *vnic_ids;
4835         size_t vnic_id_sz;
4836         int num_vnic_ids, i;
4837         size_t sz;
4838         int rc;
4839
4840         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4841         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4842                         RTE_CACHE_LINE_SIZE);
4843         if (vnic_ids == NULL)
4844                 return -ENOMEM;
4845
4846         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4847                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4848
4849         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4850         if (rc <= 0)
4851                 goto exit;
4852         num_vnic_ids = rc;
4853
4854         /*
4855          * Loop through to find the default VNIC ID.
4856          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4857          * by sending the hwrm_func_qcfg command to the firmware.
4858          */
4859         for (i = 0; i < num_vnic_ids; i++) {
4860                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4861                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4862                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4863                                         bp->pf->first_vf_id + vf);
4864                 if (rc)
4865                         goto exit;
4866                 if (vnic.func_default) {
4867                         rte_free(vnic_ids);
4868                         return vnic.fw_vnic_id;
4869                 }
4870         }
4871         /* Could not find a default VNIC. */
4872         PMD_DRV_LOG(ERR, "No default VNIC\n");
4873 exit:
4874         rte_free(vnic_ids);
4875         return rc;
4876 }
4877
4878 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4879                          uint16_t dst_id,
4880                          struct bnxt_filter_info *filter)
4881 {
4882         int rc = 0;
4883         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4884         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4885         uint32_t enables = 0;
4886
4887         if (filter->fw_em_filter_id != UINT64_MAX)
4888                 bnxt_hwrm_clear_em_filter(bp, filter);
4889
4890         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4891
4892         req.flags = rte_cpu_to_le_32(filter->flags);
4893
4894         enables = filter->enables |
4895               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4896         req.dst_id = rte_cpu_to_le_16(dst_id);
4897
4898         if (filter->ip_addr_type) {
4899                 req.ip_addr_type = filter->ip_addr_type;
4900                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4901         }
4902         if (enables &
4903             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4904                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4905         if (enables &
4906             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4907                 memcpy(req.src_macaddr, filter->src_macaddr,
4908                        RTE_ETHER_ADDR_LEN);
4909         if (enables &
4910             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4911                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4912                        RTE_ETHER_ADDR_LEN);
4913         if (enables &
4914             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4915                 req.ovlan_vid = filter->l2_ovlan;
4916         if (enables &
4917             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4918                 req.ivlan_vid = filter->l2_ivlan;
4919         if (enables &
4920             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4921                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4922         if (enables &
4923             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4924                 req.ip_protocol = filter->ip_protocol;
4925         if (enables &
4926             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4927                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4928         if (enables &
4929             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4930                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4931         if (enables &
4932             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4933                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4934         if (enables &
4935             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4936                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4937         if (enables &
4938             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4939                 req.mirror_vnic_id = filter->mirror_vnic_id;
4940
4941         req.enables = rte_cpu_to_le_32(enables);
4942
4943         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4944
4945         HWRM_CHECK_RESULT();
4946
4947         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4948         HWRM_UNLOCK();
4949
4950         return rc;
4951 }
4952
4953 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4954 {
4955         int rc = 0;
4956         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4957         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4958
4959         if (filter->fw_em_filter_id == UINT64_MAX)
4960                 return 0;
4961
4962         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4963
4964         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4965
4966         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4967
4968         HWRM_CHECK_RESULT();
4969         HWRM_UNLOCK();
4970
4971         filter->fw_em_filter_id = UINT64_MAX;
4972         filter->fw_l2_filter_id = UINT64_MAX;
4973
4974         return 0;
4975 }
4976
4977 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4978                          uint16_t dst_id,
4979                          struct bnxt_filter_info *filter)
4980 {
4981         int rc = 0;
4982         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4983         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4984                                                 bp->hwrm_cmd_resp_addr;
4985         uint32_t enables = 0;
4986
4987         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4988                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4989
4990         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4991
4992         req.flags = rte_cpu_to_le_32(filter->flags);
4993
4994         enables = filter->enables |
4995               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4996         req.dst_id = rte_cpu_to_le_16(dst_id);
4997
4998         if (filter->ip_addr_type) {
4999                 req.ip_addr_type = filter->ip_addr_type;
5000                 enables |=
5001                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
5002         }
5003         if (enables &
5004             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
5005                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
5006         if (enables &
5007             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
5008                 memcpy(req.src_macaddr, filter->src_macaddr,
5009                        RTE_ETHER_ADDR_LEN);
5010         if (enables &
5011             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
5012                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
5013         if (enables &
5014             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
5015                 req.ip_protocol = filter->ip_protocol;
5016         if (enables &
5017             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
5018                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
5019         if (enables &
5020             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
5021                 req.src_ipaddr_mask[0] =
5022                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
5023         if (enables &
5024             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
5025                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
5026         if (enables &
5027             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
5028                 req.dst_ipaddr_mask[0] =
5029                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
5030         if (enables &
5031             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
5032                 req.src_port = rte_cpu_to_le_16(filter->src_port);
5033         if (enables &
5034             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
5035                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
5036         if (enables &
5037             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
5038                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
5039         if (enables &
5040             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
5041                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
5042         if (enables &
5043             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
5044                 req.mirror_vnic_id = filter->mirror_vnic_id;
5045
5046         req.enables = rte_cpu_to_le_32(enables);
5047
5048         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5049
5050         HWRM_CHECK_RESULT();
5051
5052         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
5053         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
5054         HWRM_UNLOCK();
5055
5056         return rc;
5057 }
5058
5059 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
5060                                 struct bnxt_filter_info *filter)
5061 {
5062         int rc = 0;
5063         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
5064         struct hwrm_cfa_ntuple_filter_free_output *resp =
5065                                                 bp->hwrm_cmd_resp_addr;
5066
5067         if (filter->fw_ntuple_filter_id == UINT64_MAX)
5068                 return 0;
5069
5070         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
5071
5072         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
5073
5074         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5075
5076         HWRM_CHECK_RESULT();
5077         HWRM_UNLOCK();
5078
5079         filter->fw_ntuple_filter_id = UINT64_MAX;
5080
5081         return 0;
5082 }
5083
5084 static int
5085 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5086 {
5087         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5088         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
5089         struct bnxt_rx_queue **rxqs = bp->rx_queues;
5090         uint16_t *ring_tbl = vnic->rss_table;
5091         int nr_ctxs = vnic->num_lb_ctxts;
5092         int max_rings = bp->rx_nr_rings;
5093         int i, j, k, cnt;
5094         int rc = 0;
5095
5096         for (i = 0, k = 0; i < nr_ctxs; i++) {
5097                 struct bnxt_rx_ring_info *rxr;
5098                 struct bnxt_cp_ring_info *cpr;
5099
5100                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5101
5102                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5103                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5104                 req.hash_mode_flags = vnic->hash_mode;
5105
5106                 req.ring_grp_tbl_addr =
5107                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5108                                      i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5109                                      2 * sizeof(*ring_tbl));
5110                 req.hash_key_tbl_addr =
5111                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5112
5113                 req.ring_table_pair_index = i;
5114                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5115
5116                 for (j = 0; j < 64; j++) {
5117                         uint16_t ring_id;
5118
5119                         /* Find next active ring. */
5120                         for (cnt = 0; cnt < max_rings; cnt++) {
5121                                 if (rxqs[k]->rx_started)
5122                                         break;
5123                                 if (++k == max_rings)
5124                                         k = 0;
5125                         }
5126
5127                         /* Return if no rings are active. */
5128                         if (cnt == max_rings) {
5129                                 HWRM_UNLOCK();
5130                                 return 0;
5131                         }
5132
5133                         /* Add rx/cp ring pair to RSS table. */
5134                         rxr = rxqs[k]->rx_ring;
5135                         cpr = rxqs[k]->cp_ring;
5136
5137                         ring_id = rxr->rx_ring_struct->fw_ring_id;
5138                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5139                         ring_id = cpr->cp_ring_struct->fw_ring_id;
5140                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5141
5142                         if (++k == max_rings)
5143                                 k = 0;
5144                 }
5145                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5146                                             BNXT_USE_CHIMP_MB);
5147
5148                 HWRM_CHECK_RESULT();
5149                 HWRM_UNLOCK();
5150         }
5151
5152         return rc;
5153 }
5154
5155 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5156 {
5157         unsigned int rss_idx, fw_idx, i;
5158
5159         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5160                 return 0;
5161
5162         if (!(vnic->rss_table && vnic->hash_type))
5163                 return 0;
5164
5165         if (BNXT_CHIP_P5(bp))
5166                 return bnxt_vnic_rss_configure_p5(bp, vnic);
5167
5168         /*
5169          * Fill the RSS hash & redirection table with
5170          * ring group ids for all VNICs
5171          */
5172         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5173              rss_idx++, fw_idx++) {
5174                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5175                         fw_idx %= bp->rx_cp_nr_rings;
5176                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5177                                 break;
5178                         fw_idx++;
5179                 }
5180
5181                 if (i == bp->rx_cp_nr_rings)
5182                         return 0;
5183
5184                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5185         }
5186
5187         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5188 }
5189
5190 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5191         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5192 {
5193         uint16_t flags;
5194
5195         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5196
5197         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5198         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5199
5200         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5201         req->num_cmpl_dma_aggr_during_int =
5202                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5203
5204         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5205
5206         /* min timer set to 1/2 of interrupt timer */
5207         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5208
5209         /* buf timer set to 1/4 of interrupt timer */
5210         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5211
5212         req->cmpl_aggr_dma_tmr_during_int =
5213                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5214
5215         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5216                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5217         req->flags = rte_cpu_to_le_16(flags);
5218 }
5219
5220 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5221                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5222 {
5223         struct hwrm_ring_aggint_qcaps_input req = {0};
5224         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5225         uint32_t enables;
5226         uint16_t flags;
5227         int rc;
5228
5229         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5230         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5231         HWRM_CHECK_RESULT();
5232
5233         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5234         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5235
5236         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5237                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5238         agg_req->flags = rte_cpu_to_le_16(flags);
5239         enables =
5240          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5241          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5242         agg_req->enables = rte_cpu_to_le_32(enables);
5243
5244         HWRM_UNLOCK();
5245         return rc;
5246 }
5247
5248 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5249                         struct bnxt_coal *coal, uint16_t ring_id)
5250 {
5251         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5252         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5253                                                 bp->hwrm_cmd_resp_addr;
5254         int rc;
5255
5256         /* Set ring coalesce parameters only for 100G NICs */
5257         if (BNXT_CHIP_P5(bp)) {
5258                 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5259                         return -1;
5260         } else if (bnxt_stratus_device(bp)) {
5261                 bnxt_hwrm_set_coal_params(coal, &req);
5262         } else {
5263                 return 0;
5264         }
5265
5266         HWRM_PREP(&req,
5267                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5268                   BNXT_USE_CHIMP_MB);
5269         req.ring_id = rte_cpu_to_le_16(ring_id);
5270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5271         HWRM_CHECK_RESULT();
5272         HWRM_UNLOCK();
5273         return 0;
5274 }
5275
5276 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5277 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5278 {
5279         struct hwrm_func_backing_store_qcaps_input req = {0};
5280         struct hwrm_func_backing_store_qcaps_output *resp =
5281                 bp->hwrm_cmd_resp_addr;
5282         struct bnxt_ctx_pg_info *ctx_pg;
5283         struct bnxt_ctx_mem_info *ctx;
5284         int total_alloc_len;
5285         int rc, i, tqm_rings;
5286
5287         if (!BNXT_CHIP_P5(bp) ||
5288             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5289             BNXT_VF(bp) ||
5290             bp->ctx)
5291                 return 0;
5292
5293         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5294         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5295         HWRM_CHECK_RESULT_SILENT();
5296
5297         total_alloc_len = sizeof(*ctx);
5298         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5299                           RTE_CACHE_LINE_SIZE);
5300         if (!ctx) {
5301                 rc = -ENOMEM;
5302                 goto ctx_err;
5303         }
5304
5305         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5306         ctx->qp_min_qp1_entries =
5307                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5308         ctx->qp_max_l2_entries =
5309                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5310         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5311         ctx->srq_max_l2_entries =
5312                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5313         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5314         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5315         ctx->cq_max_l2_entries =
5316                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5317         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5318         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5319         ctx->vnic_max_vnic_entries =
5320                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5321         ctx->vnic_max_ring_table_entries =
5322                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5323         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5324         ctx->stat_max_entries =
5325                 rte_le_to_cpu_32(resp->stat_max_entries);
5326         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5327         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5328         ctx->tqm_min_entries_per_ring =
5329                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5330         ctx->tqm_max_entries_per_ring =
5331                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5332         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5333         if (!ctx->tqm_entries_multiple)
5334                 ctx->tqm_entries_multiple = 1;
5335         ctx->mrav_max_entries =
5336                 rte_le_to_cpu_32(resp->mrav_max_entries);
5337         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5338         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5339         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5340         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5341
5342         ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5343                                   RTE_MIN(ctx->tqm_fp_rings_count,
5344                                           BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5345                                   bp->max_q;
5346
5347         /* Check if the ext ring count needs to be counted.
5348          * Ext ring count is available only with new FW so we should not
5349          * look at the field on older FW.
5350          */
5351         if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5352             bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5353                 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5354                 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5355                                                   ctx->tqm_fp_rings_count);
5356         }
5357
5358         tqm_rings = ctx->tqm_fp_rings_count + 1;
5359
5360         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5361                             sizeof(*ctx_pg) * tqm_rings,
5362                             RTE_CACHE_LINE_SIZE);
5363         if (!ctx_pg) {
5364                 rc = -ENOMEM;
5365                 goto ctx_err;
5366         }
5367         for (i = 0; i < tqm_rings; i++, ctx_pg++)
5368                 ctx->tqm_mem[i] = ctx_pg;
5369
5370         bp->ctx = ctx;
5371 ctx_err:
5372         HWRM_UNLOCK();
5373         return rc;
5374 }
5375
5376 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5377 {
5378         struct hwrm_func_backing_store_cfg_input req = {0};
5379         struct hwrm_func_backing_store_cfg_output *resp =
5380                 bp->hwrm_cmd_resp_addr;
5381         struct bnxt_ctx_mem_info *ctx = bp->ctx;
5382         struct bnxt_ctx_pg_info *ctx_pg;
5383         uint32_t *num_entries;
5384         uint64_t *pg_dir;
5385         uint8_t *pg_attr;
5386         uint32_t ena;
5387         int i, rc;
5388
5389         if (!ctx)
5390                 return 0;
5391
5392         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5393         req.enables = rte_cpu_to_le_32(enables);
5394
5395         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5396                 ctx_pg = &ctx->qp_mem;
5397                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5398                 req.qp_num_qp1_entries =
5399                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5400                 req.qp_num_l2_entries =
5401                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5402                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5403                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5404                                       &req.qpc_pg_size_qpc_lvl,
5405                                       &req.qpc_page_dir);
5406         }
5407
5408         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5409                 ctx_pg = &ctx->srq_mem;
5410                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5411                 req.srq_num_l2_entries =
5412                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5413                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5414                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5415                                       &req.srq_pg_size_srq_lvl,
5416                                       &req.srq_page_dir);
5417         }
5418
5419         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5420                 ctx_pg = &ctx->cq_mem;
5421                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5422                 req.cq_num_l2_entries =
5423                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5424                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5425                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5426                                       &req.cq_pg_size_cq_lvl,
5427                                       &req.cq_page_dir);
5428         }
5429
5430         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5431                 ctx_pg = &ctx->vnic_mem;
5432                 req.vnic_num_vnic_entries =
5433                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5434                 req.vnic_num_ring_table_entries =
5435                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5436                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5437                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5438                                       &req.vnic_pg_size_vnic_lvl,
5439                                       &req.vnic_page_dir);
5440         }
5441
5442         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5443                 ctx_pg = &ctx->stat_mem;
5444                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5445                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5446                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5447                                       &req.stat_pg_size_stat_lvl,
5448                                       &req.stat_page_dir);
5449         }
5450
5451         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5452         num_entries = &req.tqm_sp_num_entries;
5453         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5454         pg_dir = &req.tqm_sp_page_dir;
5455         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5456         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5457                 if (!(enables & ena))
5458                         continue;
5459
5460                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5461
5462                 ctx_pg = ctx->tqm_mem[i];
5463                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5464                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5465         }
5466
5467         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5468                 /* DPDK does not need to configure MRAV and TIM type.
5469                  * So we are skipping over MRAV and TIM. Skip to configure
5470                  * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5471                  */
5472                 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5473                 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5474                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5475                                       &req.tqm_ring8_pg_size_tqm_ring_lvl,
5476                                       &req.tqm_ring8_page_dir);
5477         }
5478
5479         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5480         HWRM_CHECK_RESULT();
5481         HWRM_UNLOCK();
5482
5483         return rc;
5484 }
5485
5486 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5487 {
5488         struct hwrm_port_qstats_ext_input req = {0};
5489         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5490         struct bnxt_pf_info *pf = bp->pf;
5491         int rc;
5492
5493         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5494               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5495                 return 0;
5496
5497         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5498
5499         req.port_id = rte_cpu_to_le_16(pf->port_id);
5500         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5501                 req.tx_stat_host_addr =
5502                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5503                 req.tx_stat_size =
5504                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5505         }
5506         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5507                 req.rx_stat_host_addr =
5508                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5509                 req.rx_stat_size =
5510                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5511         }
5512         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5513
5514         if (rc) {
5515                 bp->fw_rx_port_stats_ext_size = 0;
5516                 bp->fw_tx_port_stats_ext_size = 0;
5517         } else {
5518                 bp->fw_rx_port_stats_ext_size =
5519                         rte_le_to_cpu_16(resp->rx_stat_size);
5520                 bp->fw_tx_port_stats_ext_size =
5521                         rte_le_to_cpu_16(resp->tx_stat_size);
5522         }
5523
5524         HWRM_CHECK_RESULT();
5525         HWRM_UNLOCK();
5526
5527         return rc;
5528 }
5529
5530 int
5531 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5532 {
5533         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5534         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5535                 bp->hwrm_cmd_resp_addr;
5536         int rc = 0;
5537
5538         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5539         req.tunnel_type = type;
5540         req.dest_fid = bp->fw_fid;
5541         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5542         HWRM_CHECK_RESULT();
5543
5544         HWRM_UNLOCK();
5545
5546         return rc;
5547 }
5548
5549 int
5550 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5551 {
5552         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5553         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5554                 bp->hwrm_cmd_resp_addr;
5555         int rc = 0;
5556
5557         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5558         req.tunnel_type = type;
5559         req.dest_fid = bp->fw_fid;
5560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5561         HWRM_CHECK_RESULT();
5562
5563         HWRM_UNLOCK();
5564
5565         return rc;
5566 }
5567
5568 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5569 {
5570         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5571         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5572                 bp->hwrm_cmd_resp_addr;
5573         int rc = 0;
5574
5575         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5576         req.src_fid = bp->fw_fid;
5577         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5578         HWRM_CHECK_RESULT();
5579
5580         if (type)
5581                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5582
5583         HWRM_UNLOCK();
5584
5585         return rc;
5586 }
5587
5588 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5589                                    uint16_t *dst_fid)
5590 {
5591         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5592         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5593                 bp->hwrm_cmd_resp_addr;
5594         int rc = 0;
5595
5596         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5597         req.src_fid = bp->fw_fid;
5598         req.tunnel_type = tun_type;
5599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5600         HWRM_CHECK_RESULT();
5601
5602         if (dst_fid)
5603                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5604
5605         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5606
5607         HWRM_UNLOCK();
5608
5609         return rc;
5610 }
5611
5612 int bnxt_hwrm_set_mac(struct bnxt *bp)
5613 {
5614         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5615         struct hwrm_func_vf_cfg_input req = {0};
5616         int rc = 0;
5617
5618         if (!BNXT_VF(bp))
5619                 return 0;
5620
5621         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5622
5623         req.enables =
5624                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5625         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5626
5627         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5628
5629         HWRM_CHECK_RESULT();
5630
5631         HWRM_UNLOCK();
5632
5633         return rc;
5634 }
5635
5636 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5637 {
5638         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5639         struct hwrm_func_drv_if_change_input req = {0};
5640         uint32_t flags;
5641         int rc;
5642
5643         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5644                 return 0;
5645
5646         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5647          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5648          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5649          */
5650         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5651                 return 0;
5652
5653         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5654
5655         if (up)
5656                 req.flags =
5657                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5658
5659         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5660
5661         HWRM_CHECK_RESULT();
5662         flags = rte_le_to_cpu_32(resp->flags);
5663         HWRM_UNLOCK();
5664
5665         if (!up)
5666                 return 0;
5667
5668         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5669                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5670                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5671         }
5672
5673         return 0;
5674 }
5675
5676 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5677 {
5678         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5679         struct bnxt_error_recovery_info *info = bp->recovery_info;
5680         struct hwrm_error_recovery_qcfg_input req = {0};
5681         uint32_t flags = 0;
5682         unsigned int i;
5683         int rc;
5684
5685         /* Older FW does not have error recovery support */
5686         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5687                 return 0;
5688
5689         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5690
5691         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5692
5693         HWRM_CHECK_RESULT();
5694
5695         flags = rte_le_to_cpu_32(resp->flags);
5696         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5697                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5698         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5699                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5700
5701         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5702             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5703                 rc = -EINVAL;
5704                 goto err;
5705         }
5706
5707         /* FW returned values are in units of 100msec */
5708         info->driver_polling_freq =
5709                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5710         info->master_func_wait_period =
5711                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5712         info->normal_func_wait_period =
5713                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5714         info->master_func_wait_period_after_reset =
5715                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5716         info->max_bailout_time_after_reset =
5717                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5718         info->status_regs[BNXT_FW_STATUS_REG] =
5719                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5720         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5721                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5722         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5723                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5724         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5725                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5726         info->reg_array_cnt =
5727                 rte_le_to_cpu_32(resp->reg_array_cnt);
5728
5729         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5730                 rc = -EINVAL;
5731                 goto err;
5732         }
5733
5734         for (i = 0; i < info->reg_array_cnt; i++) {
5735                 info->reset_reg[i] =
5736                         rte_le_to_cpu_32(resp->reset_reg[i]);
5737                 info->reset_reg_val[i] =
5738                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5739                 info->delay_after_reset[i] =
5740                         resp->delay_after_reset[i];
5741         }
5742 err:
5743         HWRM_UNLOCK();
5744
5745         /* Map the FW status registers */
5746         if (!rc)
5747                 rc = bnxt_map_fw_health_status_regs(bp);
5748
5749         if (rc) {
5750                 rte_free(bp->recovery_info);
5751                 bp->recovery_info = NULL;
5752         }
5753         return rc;
5754 }
5755
5756 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5757 {
5758         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5759         struct hwrm_fw_reset_input req = {0};
5760         int rc;
5761
5762         if (!BNXT_PF(bp))
5763                 return -EOPNOTSUPP;
5764
5765         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5766
5767         req.embedded_proc_type =
5768                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5769         req.selfrst_status =
5770                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5771         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5772
5773         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5774                                     BNXT_USE_KONG(bp));
5775
5776         HWRM_CHECK_RESULT();
5777         HWRM_UNLOCK();
5778
5779         return rc;
5780 }
5781
5782 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5783 {
5784         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5785         struct hwrm_port_ts_query_input req = {0};
5786         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5787         uint32_t flags = 0;
5788         int rc;
5789
5790         if (!ptp)
5791                 return 0;
5792
5793         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5794
5795         switch (path) {
5796         case BNXT_PTP_FLAGS_PATH_TX:
5797                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5798                 break;
5799         case BNXT_PTP_FLAGS_PATH_RX:
5800                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5801                 break;
5802         case BNXT_PTP_FLAGS_CURRENT_TIME:
5803                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5804                 break;
5805         }
5806
5807         req.flags = rte_cpu_to_le_32(flags);
5808         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5809
5810         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5811
5812         HWRM_CHECK_RESULT();
5813
5814         if (timestamp) {
5815                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5816                 *timestamp |=
5817                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5818         }
5819         HWRM_UNLOCK();
5820
5821         return rc;
5822 }
5823
5824 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5825 {
5826         int rc = 0;
5827
5828         struct hwrm_cfa_counter_qcaps_input req = {0};
5829         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5830
5831         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5832                 PMD_DRV_LOG(DEBUG,
5833                             "Not a PF or trusted VF. Command not supported\n");
5834                 return 0;
5835         }
5836
5837         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5838         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5839         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5840
5841         HWRM_CHECK_RESULT();
5842         if (max_fc)
5843                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5844         HWRM_UNLOCK();
5845
5846         return 0;
5847 }
5848
5849 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5850 {
5851         int rc = 0;
5852         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5853         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5854
5855         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5856                 PMD_DRV_LOG(DEBUG,
5857                             "Not a PF or trusted VF. Command not supported\n");
5858                 return 0;
5859         }
5860
5861         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5862
5863         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5864         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5865         req.page_dir = rte_cpu_to_le_64(dma_addr);
5866
5867         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5868
5869         HWRM_CHECK_RESULT();
5870         if (ctx_id) {
5871                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5872                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5873         }
5874         HWRM_UNLOCK();
5875
5876         return 0;
5877 }
5878
5879 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5880 {
5881         int rc = 0;
5882         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5883         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5884
5885         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5886                 PMD_DRV_LOG(DEBUG,
5887                             "Not a PF or trusted VF. Command not supported\n");
5888                 return 0;
5889         }
5890
5891         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5892
5893         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5894
5895         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5896
5897         HWRM_CHECK_RESULT();
5898         HWRM_UNLOCK();
5899
5900         return rc;
5901 }
5902
5903 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5904                               uint16_t cntr, uint16_t ctx_id,
5905                               uint32_t num_entries, bool enable)
5906 {
5907         struct hwrm_cfa_counter_cfg_input req = {0};
5908         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5909         uint16_t flags = 0;
5910         int rc;
5911
5912         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5913                 PMD_DRV_LOG(DEBUG,
5914                             "Not a PF or trusted VF. Command not supported\n");
5915                 return 0;
5916         }
5917
5918         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5919
5920         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5921         req.counter_type = rte_cpu_to_le_16(cntr);
5922         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5923                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5924         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5925         if (dir == BNXT_DIR_RX)
5926                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5927         else if (dir == BNXT_DIR_TX)
5928                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5929         req.flags = rte_cpu_to_le_16(flags);
5930         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5931         req.num_entries = rte_cpu_to_le_32(num_entries);
5932
5933         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5934         HWRM_CHECK_RESULT();
5935         HWRM_UNLOCK();
5936
5937         return 0;
5938 }
5939
5940 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5941                                  enum bnxt_flow_dir dir,
5942                                  uint16_t cntr,
5943                                  uint16_t num_entries)
5944 {
5945         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5946         struct hwrm_cfa_counter_qstats_input req = {0};
5947         uint16_t flow_ctx_id = 0;
5948         uint16_t flags = 0;
5949         int rc = 0;
5950
5951         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5952                 PMD_DRV_LOG(DEBUG,
5953                             "Not a PF or trusted VF. Command not supported\n");
5954                 return 0;
5955         }
5956
5957         if (dir == BNXT_DIR_RX) {
5958                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5959                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5960         } else if (dir == BNXT_DIR_TX) {
5961                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5962                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5963         }
5964
5965         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5966         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5967         req.counter_type = rte_cpu_to_le_16(cntr);
5968         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5969         req.num_entries = rte_cpu_to_le_16(num_entries);
5970         req.flags = rte_cpu_to_le_16(flags);
5971         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5972
5973         HWRM_CHECK_RESULT();
5974         HWRM_UNLOCK();
5975
5976         return 0;
5977 }
5978
5979 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5980                                 uint16_t *first_vf_id)
5981 {
5982         int rc = 0;
5983         struct hwrm_func_qcaps_input req = {.req_type = 0 };
5984         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5985
5986         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5987
5988         req.fid = rte_cpu_to_le_16(fid);
5989
5990         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5991
5992         HWRM_CHECK_RESULT();
5993
5994         if (first_vf_id)
5995                 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
5996
5997         HWRM_UNLOCK();
5998
5999         return rc;
6000 }
6001
6002 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
6003 {
6004         struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6005         struct hwrm_cfa_pair_alloc_input req = {0};
6006         int rc;
6007
6008         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6009                 PMD_DRV_LOG(DEBUG,
6010                             "Not a PF or trusted VF. Command not supported\n");
6011                 return 0;
6012         }
6013
6014         HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
6015         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6016         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6017                  bp->eth_dev->data->name, rep_bp->vf_id);
6018
6019         req.pf_b_id = rep_bp->parent_pf_idx;
6020         req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6021                                                 rte_cpu_to_le_16(rep_bp->vf_id);
6022         req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
6023         req.host_b_id = 1; /* TBD - Confirm if this is OK */
6024
6025         req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
6026                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
6027         req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
6028                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
6029         req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
6030                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
6031         req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
6032                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
6033
6034         req.q_ab = rep_bp->rep_q_r2f;
6035         req.q_ba = rep_bp->rep_q_f2r;
6036         req.fc_ab = rep_bp->rep_fc_r2f;
6037         req.fc_ba = rep_bp->rep_fc_f2r;
6038
6039         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6040         HWRM_CHECK_RESULT();
6041
6042         HWRM_UNLOCK();
6043         PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
6044                     BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
6045         return rc;
6046 }
6047
6048 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
6049 {
6050         struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
6051         struct hwrm_cfa_pair_free_input req = {0};
6052         int rc;
6053
6054         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6055                 PMD_DRV_LOG(DEBUG,
6056                             "Not a PF or trusted VF. Command not supported\n");
6057                 return 0;
6058         }
6059
6060         HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
6061         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6062                  bp->eth_dev->data->name, rep_bp->vf_id);
6063         req.pf_b_id = rep_bp->parent_pf_idx;
6064         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6065         req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6066                                                 rte_cpu_to_le_16(rep_bp->vf_id);
6067         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6068         HWRM_CHECK_RESULT();
6069         HWRM_UNLOCK();
6070         PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
6071                     rep_bp->vf_id);
6072         return rc;
6073 }
6074
6075 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
6076 {
6077         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
6078                                         bp->hwrm_cmd_resp_addr;
6079         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
6080         uint32_t flags = 0;
6081         int rc = 0;
6082
6083         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
6084                 return 0;
6085
6086         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6087                 PMD_DRV_LOG(DEBUG,
6088                             "Not a PF or trusted VF. Command not supported\n");
6089                 return 0;
6090         }
6091
6092         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
6093         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6094
6095         HWRM_CHECK_RESULT();
6096         flags = rte_le_to_cpu_32(resp->flags);
6097         HWRM_UNLOCK();
6098
6099         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
6100                 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
6101         else
6102                 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
6103
6104         return rc;
6105 }
6106
6107 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6108                             uint32_t echo_req_data2)
6109 {
6110         struct hwrm_func_echo_response_input req = {0};
6111         struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6112         int rc;
6113
6114         HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6115         req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6116         req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6117
6118         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6119
6120         HWRM_CHECK_RESULT();
6121         HWRM_UNLOCK();
6122
6123         return rc;
6124 }
6125
6126 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6127 {
6128         struct hwrm_ver_get_input req = {.req_type = 0 };
6129         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6130         int rc = 0;
6131
6132         bp->max_req_len = HWRM_MAX_REQ_LEN;
6133         bp->max_resp_len = BNXT_PAGE_SIZE;
6134         bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6135
6136         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6137         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6138         req.hwrm_intf_min = HWRM_VERSION_MINOR;
6139         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6140
6141         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6142
6143         HWRM_CHECK_RESULT_SILENT();
6144
6145         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)
6146                 rc = -EAGAIN;
6147
6148         HWRM_UNLOCK();
6149
6150         return rc;
6151 }
6152
6153 int bnxt_hwrm_read_sfp_module_eeprom_info(struct bnxt *bp, uint16_t i2c_addr,
6154                                           uint16_t page_number, uint16_t start_addr,
6155                                           uint16_t data_length, uint8_t *buf)
6156 {
6157         struct hwrm_port_phy_i2c_read_output *resp = bp->hwrm_cmd_resp_addr;
6158         struct hwrm_port_phy_i2c_read_input req = {0};
6159         uint32_t enables = HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET;
6160         int rc, byte_offset = 0;
6161
6162         do {
6163                 uint16_t xfer_size;
6164
6165                 HWRM_PREP(&req, HWRM_PORT_PHY_I2C_READ, BNXT_USE_CHIMP_MB);
6166                 req.i2c_slave_addr = i2c_addr;
6167                 req.page_number = rte_cpu_to_le_16(page_number);
6168                 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
6169
6170                 xfer_size = RTE_MIN(data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
6171                 req.page_offset = rte_cpu_to_le_16(start_addr + byte_offset);
6172                 req.data_length = xfer_size;
6173                 req.enables = rte_cpu_to_le_32(start_addr + byte_offset ? enables : 0);
6174                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6175                 HWRM_CHECK_RESULT();
6176
6177                 memcpy(buf + byte_offset, resp->data, xfer_size);
6178
6179                 data_length -= xfer_size;
6180                 byte_offset += xfer_size;
6181
6182                 HWRM_UNLOCK();
6183         } while (data_length > 0);
6184
6185         return rc;
6186 }
6187
6188 void bnxt_free_hwrm_tx_ring(struct bnxt *bp, int queue_index)
6189 {
6190         struct bnxt_tx_queue *txq = bp->tx_queues[queue_index];
6191         struct bnxt_tx_ring_info *txr = txq->tx_ring;
6192         struct bnxt_ring *ring = txr->tx_ring_struct;
6193         struct bnxt_cp_ring_info *cpr = txq->cp_ring;
6194
6195         bnxt_hwrm_ring_free(bp, ring,
6196                             HWRM_RING_FREE_INPUT_RING_TYPE_TX,
6197                             cpr->cp_ring_struct->fw_ring_id);
6198         txr->tx_raw_prod = 0;
6199         txr->tx_raw_cons = 0;
6200         memset(txr->tx_desc_ring, 0,
6201                 txr->tx_ring_struct->ring_size * sizeof(*txr->tx_desc_ring));
6202         memset(txr->tx_buf_ring, 0,
6203                 txr->tx_ring_struct->ring_size * sizeof(*txr->tx_buf_ring));
6204
6205         bnxt_hwrm_stat_ctx_free(bp, cpr);
6206
6207         bnxt_free_cp_ring(bp, cpr);
6208 }
6209
6210 int bnxt_hwrm_config_host_mtu(struct bnxt *bp)
6211 {
6212         struct hwrm_func_cfg_input req = {0};
6213         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
6214         int rc;
6215
6216         if (!BNXT_PF(bp))
6217                 return 0;
6218
6219         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
6220
6221         req.fid = rte_cpu_to_le_16(0xffff);
6222         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU);
6223         req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
6224
6225         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6226         HWRM_CHECK_RESULT();
6227         HWRM_UNLOCK();
6228
6229         return rc;
6230 }