drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30 #define HWRM_VERSION_1_10_2_13          0x10a020d
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(int) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages == 0)
  68                 return;
  69
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 static struct bnxt_cp_ring_info*
  79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
  80 {
  81         struct bnxt_cp_ring_info *cp_ring = NULL;
  82         uint16_t i;
  83
  84         switch (type) {
  85         case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
  86         case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
  87                 /* FALLTHROUGH */
  88                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
  89                         struct bnxt_rx_queue *rxq = bp->rx_queues[i];
  90
  91                         if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
  92                             rte_cpu_to_le_16(rid)) {
  93                                 return rxq->cp_ring;
  94                         }
  95                 }
  96                 break;
  97         case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
  98                 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
  99                         struct bnxt_tx_queue *txq = bp->tx_queues[i];
 100
 101                         if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
 102                             rte_cpu_to_le_16(rid)) {
 103                                 return txq->cp_ring;
 104                         }
 105                 }
 106                 break;
 107         default:
 108                 return cp_ring;
 109         }
 110         return cp_ring;
 111 }
 112
 113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
 114  * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
 115  * before timeout, we force the done bit for the cleanup to proceed.
 116  * Also if cpr is null, do nothing.. The HWRM command is  not for a
 117  * Tx/Rx/AGG ring cleanup.
 118  */
 119 static int
 120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
 121                         bool tx, bool rx, bool timeout)
 122 {
 123         int done = 0;
 124
 125         if (cpr != NULL) {
 126                 if (tx)
 127                         done = bnxt_flush_tx_cmp(cpr);
 128
 129                 if (rx)
 130                         done = bnxt_flush_rx_cmp(cpr);
 131
 132                 if (done)
 133                         PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
 134                                     rx ? "Rx" : "Tx");
 135
 136                 /* We are about to timeout and still haven't seen the
 137                  * HWRM done for the Ring free. Force the cleanup.
 138                  */
 139                 if (!done && timeout) {
 140                         done = 1;
 141                         PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
 142                                     rx ? "Rx" : "Tx");
 143                 }
 144         } else {
 145                 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
 146                  * Otherwise the cpr would have been valid. So do nothing.
 147                  */
 148                 done = 1;
 149         }
 150
 151         return done;
 152 }
 153
 154 /*
 155  * HWRM Functions (sent to HWRM)
 156  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
 157  * HWRM command times out, or a negative error code if the HWRM
 158  * command was failed by the FW.
 159  */
 160
 161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
 162                                   uint32_t msg_len, bool use_kong_mb)
 163 {
 164         unsigned int i;
 165         struct input *req = msg;
 166         struct output *resp = bp->hwrm_cmd_resp_addr;
 167         uint32_t *data = msg;
 168         uint8_t *bar;
 169         uint8_t *valid;
 170         uint16_t max_req_len = bp->max_req_len;
 171         struct hwrm_short_input short_input = { 0 };
 172         uint16_t bar_offset = use_kong_mb ?
 173                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
 174         uint16_t mb_trigger_offset = use_kong_mb ?
 175                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 176         struct bnxt_cp_ring_info *cpr = NULL;
 177         bool is_rx = false;
 178         bool is_tx = false;
 179         uint32_t timeout;
 180
 181         /* Do not send HWRM commands to firmware in error state */
 182         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 183                 return 0;
 184
 185         timeout = bp->hwrm_cmd_timeout;
 186
 187         /* Update the message length for backing store config for new FW. */
 188         if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
 189             rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
 190                 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
 191
 192         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 193             msg_len > bp->max_req_len) {
 194                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 195
 196                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 197                 memcpy(short_cmd_req, req, msg_len);
 198
 199                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 200                 short_input.signature = rte_cpu_to_le_16(
 201                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 202                 short_input.size = rte_cpu_to_le_16(msg_len);
 203                 short_input.req_addr =
 204                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 205
 206                 data = (uint32_t *)&short_input;
 207                 msg_len = sizeof(short_input);
 208
 209                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 210         }
 211
 212         /* Write request msg to hwrm channel */
 213         for (i = 0; i < msg_len; i += 4) {
 214                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 215                 rte_write32(*data, bar);
 216                 data++;
 217         }
 218
 219         /* Zero the rest of the request space */
 220         for (; i < max_req_len; i += 4) {
 221                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 222                 rte_write32(0, bar);
 223         }
 224
 225         /* Ring channel doorbell */
 226         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 227         rte_write32(1, bar);
 228         /*
 229          * Make sure the channel doorbell ring command complete before
 230          * reading the response to avoid getting stale or invalid
 231          * responses.
 232          */
 233         rte_io_mb();
 234
 235         /* Check ring flush is done.
 236          * This is valid only for Tx and Rx rings (including AGG rings).
 237          * The Tx and Rx rings should be freed once the HW confirms all
 238          * the internal buffers and BDs associated with the rings are
 239          * consumed and the corresponding DMA is handled.
 240          */
 241         if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
 242                 /* Check if the TxCQ matches. If that fails check if RxCQ
 243                  * matches. And if neither match, is_rx = false, is_tx = false.
 244                  */
 245                 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 246                                                HWRM_RING_FREE_INPUT_RING_TYPE_TX);
 247                 if (cpr == NULL) {
 248                         /* Not a TxCQ. Check if the RxCQ matches. */
 249                         cpr =
 250                         bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 251                                                  HWRM_RING_FREE_INPUT_RING_TYPE_RX);
 252                         if (cpr != NULL)
 253                                 is_rx = true;
 254                 } else {
 255                         is_tx = true;
 256                 }
 257         }
 258
 259         /* Poll for the valid bit */
 260         for (i = 0; i < timeout; i++) {
 261                 int done;
 262
 263                 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
 264                                                i == timeout - 1);
 265                 /* Sanity check on the resp->resp_len */
 266                 rte_io_rmb();
 267                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 268                         /* Last byte of resp contains the valid key */
 269                         valid = (uint8_t *)resp + resp->resp_len - 1;
 270                         if (*valid == HWRM_RESP_VALID_KEY && done)
 271                                 break;
 272                 }
 273                 rte_delay_us(1);
 274         }
 275
 276         if (i >= timeout) {
 277                 /* Suppress VER_GET timeout messages during reset recovery */
 278                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 279                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 280                         return -ETIMEDOUT;
 281
 282                 PMD_DRV_LOG(ERR,
 283                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 284                             req->req_type, req->seq_id);
 285                 return -ETIMEDOUT;
 286         }
 287         return 0;
 288 }
 289
 290 /*
 291  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 292  * spinlock, and does initial processing.
 293  *
 294  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 295  * releases the spinlock only if it returns. If the regular int return codes
 296  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 297  * directly, rather it should be copied and modified to suit the function.
 298  *
 299  * HWRM_UNLOCK() must be called after all response processing is completed.
 300  */
 301 #define HWRM_PREP(req, type, kong) do { \
 302         rte_spinlock_lock(&bp->hwrm_lock); \
 303         if (bp->hwrm_cmd_resp_addr == NULL) { \
 304                 rte_spinlock_unlock(&bp->hwrm_lock); \
 305                 return -EACCES; \
 306         } \
 307         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 308         (req)->req_type = rte_cpu_to_le_16(type); \
 309         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 310         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 311                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 312         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 313         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 314 } while (0)
 315
 316 #define HWRM_CHECK_RESULT_SILENT() do {\
 317         if (rc) { \
 318                 rte_spinlock_unlock(&bp->hwrm_lock); \
 319                 return rc; \
 320         } \
 321         if (resp->error_code) { \
 322                 rc = rte_le_to_cpu_16(resp->error_code); \
 323                 rte_spinlock_unlock(&bp->hwrm_lock); \
 324                 return rc; \
 325         } \
 326 } while (0)
 327
 328 #define HWRM_CHECK_RESULT() do {\
 329         if (rc) { \
 330                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 331                 rte_spinlock_unlock(&bp->hwrm_lock); \
 332                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 333                         rc = -EACCES; \
 334                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 335                         rc = -ENOSPC; \
 336                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 337                         rc = -EINVAL; \
 338                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 339                         rc = -ENOTSUP; \
 340                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 341                         rc = -EAGAIN; \
 342                 else if (rc > 0) \
 343                         rc = -EIO; \
 344                 return rc; \
 345         } \
 346         if (resp->error_code) { \
 347                 rc = rte_le_to_cpu_16(resp->error_code); \
 348                 if (resp->resp_len >= 16) { \
 349                         struct hwrm_err_output *tmp_hwrm_err_op = \
 350                                                 (void *)resp; \
 351                         PMD_DRV_LOG(ERR, \
 352                                 "error %d:%d:%08x:%04x\n", \
 353                                 rc, tmp_hwrm_err_op->cmd_err, \
 354                                 rte_le_to_cpu_32(\
 355                                         tmp_hwrm_err_op->opaque_0), \
 356                                 rte_le_to_cpu_16(\
 357                                         tmp_hwrm_err_op->opaque_1)); \
 358                 } else { \
 359                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 360                 } \
 361                 rte_spinlock_unlock(&bp->hwrm_lock); \
 362                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 363                         rc = -EACCES; \
 364                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 365                         rc = -ENOSPC; \
 366                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 367                         rc = -EINVAL; \
 368                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 369                         rc = -ENOTSUP; \
 370                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 371                         rc = -EAGAIN; \
 372                 else if (rc > 0) \
 373                         rc = -EIO; \
 374                 return rc; \
 375         } \
 376 } while (0)
 377
 378 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 379
 380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 381                                 bool use_kong_mb,
 382                                 uint16_t msg_type,
 383                                 void *msg,
 384                                 uint32_t msg_len,
 385                                 void *resp_msg,
 386                                 uint32_t resp_len)
 387 {
 388         int rc = 0;
 389         bool mailbox = BNXT_USE_CHIMP_MB;
 390         struct input *req = msg;
 391         struct output *resp = bp->hwrm_cmd_resp_addr;
 392
 393         if (use_kong_mb)
 394                 mailbox = BNXT_USE_KONG(bp);
 395
 396         HWRM_PREP(req, msg_type, mailbox);
 397
 398         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 399
 400         HWRM_CHECK_RESULT();
 401
 402         if (resp_msg)
 403                 memcpy(resp_msg, resp, resp_len);
 404
 405         HWRM_UNLOCK();
 406
 407         return rc;
 408 }
 409
 410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 411                                   bool use_kong_mb,
 412                                   uint16_t tf_type,
 413                                   uint16_t tf_subtype,
 414                                   uint32_t *tf_response_code,
 415                                   void *msg,
 416                                   uint32_t msg_len,
 417                                   void *response,
 418                                   uint32_t response_len)
 419 {
 420         int rc = 0;
 421         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 422         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 423         bool mailbox = BNXT_USE_CHIMP_MB;
 424
 425         if (msg_len > sizeof(req.tf_req))
 426                 return -ENOMEM;
 427
 428         if (use_kong_mb)
 429                 mailbox = BNXT_USE_KONG(bp);
 430
 431         HWRM_PREP(&req, HWRM_TF, mailbox);
 432         /* Build request using the user supplied request payload.
 433          * TLV request size is checked at build time against HWRM
 434          * request max size, thus no checking required.
 435          */
 436         req.tf_type = tf_type;
 437         req.tf_subtype = tf_subtype;
 438         memcpy(req.tf_req, msg, msg_len);
 439
 440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 441         HWRM_CHECK_RESULT();
 442
 443         /* Copy the resp to user provided response buffer */
 444         if (response != NULL)
 445                 /* Post process response data. We need to copy only
 446                  * the 'payload' as the HWRM data structure really is
 447                  * HWRM header + msg header + payload and the TFLIB
 448                  * only provided a payload place holder.
 449                  */
 450                 if (response_len != 0) {
 451                         memcpy(response,
 452                                resp->tf_resp,
 453                                response_len);
 454                 }
 455
 456         /* Extract the internal tflib response code */
 457         *tf_response_code = resp->tf_resp_code;
 458         HWRM_UNLOCK();
 459
 460         return rc;
 461 }
 462
 463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 464 {
 465         int rc = 0;
 466         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 467         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 468
 469         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 470         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 471         req.mask = 0;
 472
 473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 474
 475         HWRM_CHECK_RESULT();
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 482                                  struct bnxt_vnic_info *vnic,
 483                                  uint16_t vlan_count,
 484                                  struct bnxt_vlan_table_entry *vlan_table)
 485 {
 486         int rc = 0;
 487         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 488         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 489         uint32_t mask = 0;
 490
 491         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 492                 return rc;
 493
 494         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 495         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 496
 497         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 498                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 499         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 500                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 501
 502         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 503                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 504
 505         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 506                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 507         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 508                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 509                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 510                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 511         }
 512         if (vlan_table) {
 513                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 514                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 515                 req.vlan_tag_tbl_addr =
 516                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 517                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 518         }
 519         req.mask = rte_cpu_to_le_32(mask);
 520
 521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 522
 523         HWRM_CHECK_RESULT();
 524         HWRM_UNLOCK();
 525
 526         return rc;
 527 }
 528
 529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 530                         uint16_t vlan_count,
 531                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 532 {
 533         int rc = 0;
 534         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 535         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 536                                                 bp->hwrm_cmd_resp_addr;
 537
 538         /*
 539          * Older HWRM versions did not support this command, and the set_rx_mask
 540          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 541          * removed from set_rx_mask call, and this command was added.
 542          *
 543          * This command is also present from 1.7.8.11 and higher,
 544          * as well as 1.7.8.0
 545          */
 546         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 547                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 548                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 549                                         (11)))
 550                                 return 0;
 551                 }
 552         }
 553         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 554         req.fid = rte_cpu_to_le_16(fid);
 555
 556         req.vlan_tag_mask_tbl_addr =
 557                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 558         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 559
 560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 561
 562         HWRM_CHECK_RESULT();
 563         HWRM_UNLOCK();
 564
 565         return rc;
 566 }
 567
 568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 569                              struct bnxt_filter_info *filter)
 570 {
 571         int rc = 0;
 572         struct bnxt_filter_info *l2_filter = filter;
 573         struct bnxt_vnic_info *vnic = NULL;
 574         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 575         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 576
 577         if (filter->fw_l2_filter_id == UINT64_MAX)
 578                 return 0;
 579
 580         if (filter->matching_l2_fltr_ptr)
 581                 l2_filter = filter->matching_l2_fltr_ptr;
 582
 583         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 584                     filter, l2_filter, l2_filter->l2_ref_cnt);
 585
 586         if (l2_filter->l2_ref_cnt == 0)
 587                 return 0;
 588
 589         if (l2_filter->l2_ref_cnt > 0)
 590                 l2_filter->l2_ref_cnt--;
 591
 592         if (l2_filter->l2_ref_cnt > 0)
 593                 return 0;
 594
 595         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 596
 597         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 598
 599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 600
 601         HWRM_CHECK_RESULT();
 602         HWRM_UNLOCK();
 603
 604         filter->fw_l2_filter_id = UINT64_MAX;
 605         if (l2_filter->l2_ref_cnt == 0) {
 606                 vnic = l2_filter->vnic;
 607                 if (vnic) {
 608                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 609                                       bnxt_filter_info, next);
 610                         bnxt_free_filter(bp, l2_filter);
 611                 }
 612         }
 613
 614         return 0;
 615 }
 616
 617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 618                          uint16_t dst_id,
 619                          struct bnxt_filter_info *filter)
 620 {
 621         int rc = 0;
 622         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 623         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 624         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 625         const struct rte_eth_vmdq_rx_conf *conf =
 626                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 627         uint32_t enables = 0;
 628         uint16_t j = dst_id - 1;
 629
 630         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 631         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 632             conf->pool_map[j].pools & (1UL << j)) {
 633                 PMD_DRV_LOG(DEBUG,
 634                         "Add vlan %u to vmdq pool %u\n",
 635                         conf->pool_map[j].vlan_id, j);
 636
 637                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 638                 filter->enables |=
 639                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 640                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 641         }
 642
 643         if (filter->fw_l2_filter_id != UINT64_MAX)
 644                 bnxt_hwrm_clear_l2_filter(bp, filter);
 645
 646         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 647
 648         /* PMD does not support XDP and RoCE */
 649         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
 650                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
 651         req.flags = rte_cpu_to_le_32(filter->flags);
 652
 653         enables = filter->enables |
 654               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 655         req.dst_id = rte_cpu_to_le_16(dst_id);
 656
 657         if (enables &
 658             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 659                 memcpy(req.l2_addr, filter->l2_addr,
 660                        RTE_ETHER_ADDR_LEN);
 661         if (enables &
 662             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 663                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 664                        RTE_ETHER_ADDR_LEN);
 665         if (enables &
 666             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 667                 req.l2_ovlan = filter->l2_ovlan;
 668         if (enables &
 669             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 670                 req.l2_ivlan = filter->l2_ivlan;
 671         if (enables &
 672             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 673                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 674         if (enables &
 675             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 676                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 677         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 678                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 679         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 680                 req.src_type = filter->src_type;
 681         if (filter->pri_hint) {
 682                 req.pri_hint = filter->pri_hint;
 683                 req.l2_filter_id_hint =
 684                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 685         }
 686
 687         req.enables = rte_cpu_to_le_32(enables);
 688
 689         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 690
 691         HWRM_CHECK_RESULT();
 692
 693         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 694         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 695         HWRM_UNLOCK();
 696
 697         filter->l2_ref_cnt++;
 698
 699         return rc;
 700 }
 701
 702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 703 {
 704         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 705         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 706         uint32_t flags = 0;
 707         int rc;
 708
 709         if (!ptp)
 710                 return 0;
 711
 712         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 713
 714         if (ptp->rx_filter)
 715                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 716         else
 717                 flags |=
 718                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 719         if (ptp->tx_tstamp_en)
 720                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 721         else
 722                 flags |=
 723                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 724         req.flags = rte_cpu_to_le_32(flags);
 725         req.enables = rte_cpu_to_le_32
 726                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 727         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 728
 729         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 730         HWRM_UNLOCK();
 731
 732         return rc;
 733 }
 734
 735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 736 {
 737         int rc = 0;
 738         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 739         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 740         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 741
 742         if (ptp)
 743                 return 0;
 744
 745         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 746
 747         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 748
 749         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 750
 751         HWRM_CHECK_RESULT();
 752
 753         if (BNXT_CHIP_P5(bp)) {
 754                 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS))
 755                         return 0;
 756         } else {
 757                 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 758                         return 0;
 759         }
 760
 761         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 762                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 763
 764         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 765         if (!ptp)
 766                 return -ENOMEM;
 767
 768         if (!BNXT_CHIP_P5(bp)) {
 769                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 770                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 771                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 772                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 773                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 774                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 775                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 776                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 777                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 778                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 779                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 780                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 781                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 782                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 783                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 784                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 785                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 786                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 787         }
 788
 789         ptp->bp = bp;
 790         bp->ptp_cfg = ptp;
 791
 792         return 0;
 793 }
 794
 795 void bnxt_free_vf_info(struct bnxt *bp)
 796 {
 797         int i;
 798
 799         if (bp->pf == NULL)
 800                 return;
 801
 802         if (bp->pf->vf_info == NULL)
 803                 return;
 804
 805         for (i = 0; i < bp->pf->max_vfs; i++) {
 806                 rte_free(bp->pf->vf_info[i].vlan_table);
 807                 bp->pf->vf_info[i].vlan_table = NULL;
 808                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 809                 bp->pf->vf_info[i].vlan_as_table = NULL;
 810         }
 811         rte_free(bp->pf->vf_info);
 812         bp->pf->vf_info = NULL;
 813 }
 814
 815 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
 816 {
 817         struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
 818         int i;
 819
 820         if (vf_info)
 821                 bnxt_free_vf_info(bp);
 822
 823         vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
 824         if (vf_info == NULL) {
 825                 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
 826                 return -ENOMEM;
 827         }
 828
 829         bp->pf->max_vfs = max_vfs;
 830         for (i = 0; i < max_vfs; i++) {
 831                 vf_info[i].fid = bp->pf->first_vf_id + i;
 832                 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
 833                                                     getpagesize(), getpagesize());
 834                 if (vf_info[i].vlan_table == NULL) {
 835                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
 836                         goto err;
 837                 }
 838                 rte_mem_lock_page(vf_info[i].vlan_table);
 839
 840                 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
 841                                                        getpagesize(), getpagesize());
 842                 if (vf_info[i].vlan_as_table == NULL) {
 843                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
 844                         goto err;
 845                 }
 846                 rte_mem_lock_page(vf_info[i].vlan_as_table);
 847
 848                 STAILQ_INIT(&vf_info[i].filter);
 849         }
 850
 851         bp->pf->vf_info = vf_info;
 852
 853         return 0;
 854 err:
 855         bnxt_free_vf_info(bp);
 856         return -ENOMEM;
 857 }
 858
 859 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 860 {
 861         int rc = 0;
 862         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 863         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 864         uint16_t new_max_vfs;
 865         uint32_t flags;
 866
 867         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 868
 869         req.fid = rte_cpu_to_le_16(0xffff);
 870
 871         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 872
 873         HWRM_CHECK_RESULT();
 874
 875         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 876         flags = rte_le_to_cpu_32(resp->flags);
 877         if (BNXT_PF(bp)) {
 878                 bp->pf->port_id = resp->port_id;
 879                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 880                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 881                 new_max_vfs = bp->pdev->max_vfs;
 882                 if (new_max_vfs != bp->pf->max_vfs) {
 883                         rc = bnxt_alloc_vf_info(bp, new_max_vfs);
 884                         if (rc)
 885                                 goto unlock;
 886                 }
 887         }
 888
 889         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 890         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 891                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 892                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 893         } else {
 894                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 895         }
 896         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 897         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 898         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 899         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 900         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 901         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 902         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 903         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
 904                 bp->max_l2_ctx += bp->max_rx_em_flows;
 905         /* TODO: For now, do not support VMDq/RFS on VFs. */
 906         if (BNXT_PF(bp)) {
 907                 if (bp->pf->max_vfs)
 908                         bp->max_vnics = 1;
 909                 else
 910                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 911         } else {
 912                 bp->max_vnics = 1;
 913         }
 914         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 915                     bp->max_l2_ctx, bp->max_vnics);
 916         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 917         if (BNXT_PF(bp)) {
 918                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 919                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 920                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 921                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 922                         HWRM_UNLOCK();
 923                         bnxt_hwrm_ptp_qcfg(bp);
 924                 }
 925         }
 926
 927         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 928                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 929
 930         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 931                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 932                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 933         }
 934
 935         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 936                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 937
 938         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 939                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 940
 941         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
 942                 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
 943
 944 unlock:
 945         HWRM_UNLOCK();
 946
 947         return rc;
 948 }
 949
 950 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 951 {
 952         int rc;
 953
 954         rc = __bnxt_hwrm_func_qcaps(bp);
 955         if (rc == -ENOMEM)
 956                 return rc;
 957
 958         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 959                 rc = bnxt_alloc_ctx_mem(bp);
 960                 if (rc)
 961                         return rc;
 962
 963                 /* On older FW,
 964                  * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 965                  * But the error can be ignored. Return success.
 966                  */
 967                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 968                 if (!rc)
 969                         bp->flags |= BNXT_FLAG_NEW_RM;
 970         }
 971
 972         return 0;
 973 }
 974
 975 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 976 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 977 {
 978         int rc = 0;
 979         uint32_t flags;
 980         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 981         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 982
 983         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 984
 985         req.target_id = rte_cpu_to_le_16(0xffff);
 986
 987         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 988
 989         HWRM_CHECK_RESULT();
 990
 991         flags = rte_le_to_cpu_32(resp->flags);
 992
 993         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 994                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 995                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 996         }
 997
 998         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
 999                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
1000
1001         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
1002                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
1003
1004         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
1005
1006         HWRM_UNLOCK();
1007
1008         return rc;
1009 }
1010
1011 int bnxt_hwrm_func_reset(struct bnxt *bp)
1012 {
1013         int rc = 0;
1014         struct hwrm_func_reset_input req = {.req_type = 0 };
1015         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1016
1017         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1018
1019         req.enables = rte_cpu_to_le_32(0);
1020
1021         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1022
1023         HWRM_CHECK_RESULT();
1024         HWRM_UNLOCK();
1025
1026         return rc;
1027 }
1028
1029 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1030 {
1031         int rc;
1032         uint32_t flags = 0;
1033         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1034         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1035
1036         if (bp->flags & BNXT_FLAG_REGISTERED)
1037                 return 0;
1038
1039         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1040                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1041         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1042                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1043
1044         /* PFs and trusted VFs should indicate the support of the
1045          * Master capability on non Stingray platform
1046          */
1047         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1048                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1049
1050         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1051         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1052                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1053         req.ver_maj = RTE_VER_YEAR;
1054         req.ver_min = RTE_VER_MONTH;
1055         req.ver_upd = RTE_VER_MINOR;
1056
1057         if (BNXT_PF(bp)) {
1058                 req.enables |= rte_cpu_to_le_32(
1059                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1060                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1061                        RTE_MIN(sizeof(req.vf_req_fwd),
1062                                sizeof(bp->pf->vf_req_fwd)));
1063         }
1064
1065         req.flags = rte_cpu_to_le_32(flags);
1066
1067         req.async_event_fwd[0] |=
1068                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1069                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1070                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1071                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1072                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1073         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1074                 req.async_event_fwd[0] |=
1075                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1076         req.async_event_fwd[1] |=
1077                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1078                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1079         if (BNXT_PF(bp))
1080                 req.async_event_fwd[1] |=
1081                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1082
1083         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1084                 req.async_event_fwd[1] |=
1085                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1086
1087         req.async_event_fwd[2] |=
1088                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST |
1089                                  ASYNC_CMPL_EVENT_ID_ERROR_REPORT);
1090
1091         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1092
1093         HWRM_CHECK_RESULT();
1094
1095         flags = rte_le_to_cpu_32(resp->flags);
1096         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1097                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1098
1099         HWRM_UNLOCK();
1100
1101         bp->flags |= BNXT_FLAG_REGISTERED;
1102
1103         return rc;
1104 }
1105
1106 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1107 {
1108         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1109                 return 0;
1110
1111         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1112 }
1113
1114 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1115 {
1116         int rc;
1117         uint32_t flags = 0;
1118         uint32_t enables;
1119         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1120         struct hwrm_func_vf_cfg_input req = {0};
1121
1122         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1123
1124         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
1125                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
1126                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
1127                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1128                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1129
1130         if (BNXT_HAS_RING_GRPS(bp)) {
1131                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1132                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1133         }
1134
1135         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1136         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1137                                             AGG_RING_MULTIPLIER);
1138         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1139         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1140                                               bp->tx_nr_rings +
1141                                               BNXT_NUM_ASYNC_CPR(bp));
1142         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1143         if (bp->vf_resv_strategy ==
1144             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1145                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1146                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1147                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1148                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1149                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1150                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1151         } else if (bp->vf_resv_strategy ==
1152                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1153                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1154                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1155         }
1156
1157         if (test)
1158                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1159                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1160                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1161                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1162                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1163                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1164
1165         if (test && BNXT_HAS_RING_GRPS(bp))
1166                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1167
1168         req.flags = rte_cpu_to_le_32(flags);
1169         req.enables |= rte_cpu_to_le_32(enables);
1170
1171         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1172
1173         if (test)
1174                 HWRM_CHECK_RESULT_SILENT();
1175         else
1176                 HWRM_CHECK_RESULT();
1177
1178         HWRM_UNLOCK();
1179         return rc;
1180 }
1181
1182 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1183 {
1184         int rc;
1185         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1186         struct hwrm_func_resource_qcaps_input req = {0};
1187
1188         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1189         req.fid = rte_cpu_to_le_16(0xffff);
1190
1191         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1192
1193         HWRM_CHECK_RESULT_SILENT();
1194
1195         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1196         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1197         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1198         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1199         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1200         /* func_resource_qcaps does not return max_rx_em_flows.
1201          * So use the value provided by func_qcaps.
1202          */
1203         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1204         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1205                 bp->max_l2_ctx += bp->max_rx_em_flows;
1206         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1207         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1208         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1209         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1210         if (bp->vf_resv_strategy >
1211             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1212                 bp->vf_resv_strategy =
1213                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1214
1215         HWRM_UNLOCK();
1216         return rc;
1217 }
1218
1219 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1220 {
1221         int rc = 0;
1222         struct hwrm_ver_get_input req = {.req_type = 0 };
1223         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1224         uint32_t fw_version;
1225         uint16_t max_resp_len;
1226         char type[RTE_MEMZONE_NAMESIZE];
1227         uint32_t dev_caps_cfg;
1228
1229         bp->max_req_len = HWRM_MAX_REQ_LEN;
1230         bp->hwrm_cmd_timeout = timeout;
1231         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1232
1233         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1234         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1235         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1236
1237         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1238
1239         if (bp->flags & BNXT_FLAG_FW_RESET)
1240                 HWRM_CHECK_RESULT_SILENT();
1241         else
1242                 HWRM_CHECK_RESULT();
1243
1244         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
1245                 rc = -EAGAIN;
1246                 goto error;
1247         }
1248
1249         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1250                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1251                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1252                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1253                 resp->hwrm_fw_rsvd_8b);
1254         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1255                      (resp->hwrm_fw_min_8b << 16) |
1256                      (resp->hwrm_fw_bld_8b << 8) |
1257                      resp->hwrm_fw_rsvd_8b;
1258         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1259                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1260
1261         fw_version = resp->hwrm_intf_maj_8b << 16;
1262         fw_version |= resp->hwrm_intf_min_8b << 8;
1263         fw_version |= resp->hwrm_intf_upd_8b;
1264         bp->hwrm_spec_code = fw_version;
1265
1266         /* def_req_timeout value is in milliseconds */
1267         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1268         /* convert timeout to usec */
1269         bp->hwrm_cmd_timeout *= 1000;
1270         if (!bp->hwrm_cmd_timeout)
1271                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1272
1273         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1274                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1275                 rc = -EINVAL;
1276                 goto error;
1277         }
1278
1279         if (bp->max_req_len > resp->max_req_win_len) {
1280                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1281                 rc = -EINVAL;
1282                 goto error;
1283         }
1284
1285         bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1286
1287         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1288         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1289         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1290                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1291
1292         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1293         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1294
1295         RTE_VERIFY(max_resp_len <= bp->max_resp_len);
1296         bp->max_resp_len = max_resp_len;
1297
1298         if ((dev_caps_cfg &
1299                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1300             (dev_caps_cfg &
1301              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1302                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1303                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1304         }
1305
1306         if (((dev_caps_cfg &
1307               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1308              (dev_caps_cfg &
1309               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1310             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1311                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1312                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1313                         bp->pdev->addr.devid, bp->pdev->addr.function);
1314
1315                 rte_free(bp->hwrm_short_cmd_req_addr);
1316
1317                 bp->hwrm_short_cmd_req_addr =
1318                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1319                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1320                         rc = -ENOMEM;
1321                         goto error;
1322                 }
1323                 bp->hwrm_short_cmd_req_dma_addr =
1324                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1325                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1326                         rte_free(bp->hwrm_short_cmd_req_addr);
1327                         PMD_DRV_LOG(ERR,
1328                                 "Unable to map buffer to physical memory.\n");
1329                         rc = -ENOMEM;
1330                         goto error;
1331                 }
1332         }
1333         if (dev_caps_cfg &
1334             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1335                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1336                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1337         }
1338         if (dev_caps_cfg &
1339             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1340                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1341         if (dev_caps_cfg &
1342             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1343                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1344                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1345         }
1346
1347         if (dev_caps_cfg &
1348             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1349                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1350                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1351         }
1352
1353         if (dev_caps_cfg &
1354             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED) {
1355                 PMD_DRV_LOG(DEBUG, "Host-based truflow feature enabled.\n");
1356                 bp->fw_cap |= BNXT_FW_CAP_TRUFLOW_EN;
1357         }
1358
1359 error:
1360         HWRM_UNLOCK();
1361         return rc;
1362 }
1363
1364 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1365 {
1366         int rc;
1367         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1368         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1369
1370         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1371                 return 0;
1372
1373         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1374         req.flags = flags;
1375
1376         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1377
1378         HWRM_CHECK_RESULT();
1379         HWRM_UNLOCK();
1380
1381         PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1382                     bp->eth_dev->data->port_id);
1383
1384         return rc;
1385 }
1386
1387 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1388 {
1389         int rc = 0;
1390         struct hwrm_port_phy_cfg_input req = {0};
1391         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1392         uint32_t enables = 0;
1393
1394         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1395
1396         if (conf->link_up) {
1397                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1398                 if (bp->link_info->auto_mode && conf->link_speed) {
1399                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1400                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1401                 }
1402
1403                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1404                 /*
1405                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1406                  * any auto mode, even "none".
1407                  */
1408                 if (!conf->link_speed) {
1409                         /* No speeds specified. Enable AutoNeg - all speeds */
1410                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1411                         req.auto_mode =
1412                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1413                 } else {
1414                         if (bp->link_info->link_signal_mode) {
1415                                 enables |=
1416                                 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1417                                 req.force_pam4_link_speed =
1418                                         rte_cpu_to_le_16(conf->link_speed);
1419                         } else {
1420                                 req.force_link_speed =
1421                                         rte_cpu_to_le_16(conf->link_speed);
1422                         }
1423                 }
1424                 /* AutoNeg - Advertise speeds specified. */
1425                 if (conf->auto_link_speed_mask &&
1426                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1427                         req.auto_mode =
1428                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1429                         req.auto_link_speed_mask =
1430                                 conf->auto_link_speed_mask;
1431                         if (conf->auto_pam4_link_speeds) {
1432                                 enables |=
1433                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1434                                 req.auto_link_pam4_speed_mask =
1435                                         conf->auto_pam4_link_speeds;
1436                         } else {
1437                                 enables |=
1438                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1439                         }
1440                 }
1441                 if (conf->auto_link_speed &&
1442                 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1443                         enables |=
1444                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1445
1446                 req.auto_duplex = conf->duplex;
1447                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1448                 req.auto_pause = conf->auto_pause;
1449                 req.force_pause = conf->force_pause;
1450                 /* Set force_pause if there is no auto or if there is a force */
1451                 if (req.auto_pause && !req.force_pause)
1452                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1453                 else
1454                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1455
1456                 req.enables = rte_cpu_to_le_32(enables);
1457         } else {
1458                 req.flags =
1459                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1460                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1461         }
1462
1463         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1464
1465         HWRM_CHECK_RESULT();
1466         HWRM_UNLOCK();
1467
1468         return rc;
1469 }
1470
1471 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1472                                    struct bnxt_link_info *link_info)
1473 {
1474         int rc = 0;
1475         struct hwrm_port_phy_qcfg_input req = {0};
1476         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1477
1478         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1479
1480         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1481
1482         HWRM_CHECK_RESULT();
1483
1484         link_info->phy_link_status = resp->link;
1485         link_info->link_up =
1486                 (link_info->phy_link_status ==
1487                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1488         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1489         link_info->duplex = resp->duplex_cfg;
1490         link_info->pause = resp->pause;
1491         link_info->auto_pause = resp->auto_pause;
1492         link_info->force_pause = resp->force_pause;
1493         link_info->auto_mode = resp->auto_mode;
1494         link_info->phy_type = resp->phy_type;
1495         link_info->media_type = resp->media_type;
1496
1497         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1498         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1499         link_info->auto_link_speed_mask = rte_le_to_cpu_16(resp->auto_link_speed_mask);
1500         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1501         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1502         link_info->phy_ver[0] = resp->phy_maj;
1503         link_info->phy_ver[1] = resp->phy_min;
1504         link_info->phy_ver[2] = resp->phy_bld;
1505         link_info->link_signal_mode =
1506                 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1507         link_info->force_pam4_link_speed =
1508                         rte_le_to_cpu_16(resp->force_pam4_link_speed);
1509         link_info->support_pam4_speeds =
1510                         rte_le_to_cpu_16(resp->support_pam4_speeds);
1511         link_info->auto_pam4_link_speeds =
1512                         rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1513         link_info->module_status = resp->module_status;
1514         HWRM_UNLOCK();
1515
1516         PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1517                     link_info->link_speed, link_info->auto_mode,
1518                     link_info->auto_link_speed, link_info->auto_link_speed_mask,
1519                     link_info->support_speeds, link_info->force_link_speed);
1520         PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1521                     link_info->link_signal_mode,
1522                     link_info->auto_pam4_link_speeds,
1523                     link_info->support_pam4_speeds,
1524                     link_info->force_pam4_link_speed);
1525         return rc;
1526 }
1527
1528 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1529 {
1530         int rc = 0;
1531         struct hwrm_port_phy_qcaps_input req = {0};
1532         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1533         struct bnxt_link_info *link_info = bp->link_info;
1534
1535         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1536                 return 0;
1537
1538         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1539
1540         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1541
1542         HWRM_CHECK_RESULT_SILENT();
1543
1544         bp->port_cnt = resp->port_cnt;
1545         if (resp->supported_speeds_auto_mode)
1546                 link_info->support_auto_speeds =
1547                         rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1548         if (resp->supported_pam4_speeds_auto_mode)
1549                 link_info->support_pam4_auto_speeds =
1550                         rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1551
1552         HWRM_UNLOCK();
1553
1554         /* Older firmware does not have supported_auto_speeds, so assume
1555          * that all supported speeds can be autonegotiated.
1556          */
1557         if (link_info->auto_link_speed_mask && !link_info->support_auto_speeds)
1558                 link_info->support_auto_speeds = link_info->support_speeds;
1559
1560         return 0;
1561 }
1562
1563 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1564 {
1565         int i = 0;
1566
1567         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1568                 if (bp->tx_cos_queue[i].profile ==
1569                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1570                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1571                         return true;
1572                 }
1573         }
1574         return false;
1575 }
1576
1577 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1578 {
1579         int i = 0;
1580
1581         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1582                 if (bp->tx_cos_queue[i].profile !=
1583                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1584                     bp->tx_cos_queue[i].id !=
1585                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1586                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1587                         break;
1588                 }
1589         }
1590 }
1591
1592 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1593 {
1594         int rc = 0;
1595         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1596         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1597         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1598         int i;
1599
1600 get_rx_info:
1601         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1602
1603         req.flags = rte_cpu_to_le_32(dir);
1604         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1605         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1606             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1607                 req.drv_qmap_cap =
1608                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1609         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1610
1611         HWRM_CHECK_RESULT();
1612
1613         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1614                 GET_TX_QUEUE_INFO(0);
1615                 GET_TX_QUEUE_INFO(1);
1616                 GET_TX_QUEUE_INFO(2);
1617                 GET_TX_QUEUE_INFO(3);
1618                 GET_TX_QUEUE_INFO(4);
1619                 GET_TX_QUEUE_INFO(5);
1620                 GET_TX_QUEUE_INFO(6);
1621                 GET_TX_QUEUE_INFO(7);
1622         } else  {
1623                 GET_RX_QUEUE_INFO(0);
1624                 GET_RX_QUEUE_INFO(1);
1625                 GET_RX_QUEUE_INFO(2);
1626                 GET_RX_QUEUE_INFO(3);
1627                 GET_RX_QUEUE_INFO(4);
1628                 GET_RX_QUEUE_INFO(5);
1629                 GET_RX_QUEUE_INFO(6);
1630                 GET_RX_QUEUE_INFO(7);
1631         }
1632
1633         HWRM_UNLOCK();
1634
1635         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1636                 goto done;
1637
1638         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1639                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1640         } else {
1641                 int j;
1642
1643                 /* iterate and find the COSq profile to use for Tx */
1644                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1645                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1646                                 if (bp->tx_cos_queue[i].id != 0xff)
1647                                         bp->tx_cosq_id[j++] =
1648                                                 bp->tx_cos_queue[i].id;
1649                         }
1650                 } else {
1651                         /* When CoS classification is disabled, for normal NIC
1652                          * operations, ideally we should look to use LOSSY.
1653                          * If not found, fallback to the first valid profile
1654                          */
1655                         if (!bnxt_find_lossy_profile(bp))
1656                                 bnxt_find_first_valid_profile(bp);
1657
1658                 }
1659         }
1660
1661         bp->max_tc = resp->max_configurable_queues;
1662         bp->max_lltc = resp->max_configurable_lossless_queues;
1663         if (bp->max_tc > BNXT_MAX_QUEUE)
1664                 bp->max_tc = BNXT_MAX_QUEUE;
1665         bp->max_q = bp->max_tc;
1666
1667         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1668                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1669                 goto get_rx_info;
1670         }
1671
1672 done:
1673         return rc;
1674 }
1675
1676 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1677                          struct bnxt_ring *ring,
1678                          uint32_t ring_type, uint32_t map_index,
1679                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1680                          uint16_t tx_cosq_id)
1681 {
1682         int rc = 0;
1683         uint32_t enables = 0;
1684         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1685         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1686         struct rte_mempool *mb_pool;
1687         uint16_t rx_buf_size;
1688
1689         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1690
1691         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1692         req.fbo = rte_cpu_to_le_32(0);
1693         /* Association of ring index with doorbell index */
1694         req.logical_id = rte_cpu_to_le_16(map_index);
1695         req.length = rte_cpu_to_le_32(ring->ring_size);
1696
1697         switch (ring_type) {
1698         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1699                 req.ring_type = ring_type;
1700                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1701                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1702                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1703                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1704                         enables |=
1705                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1706                 break;
1707         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1708                 req.ring_type = ring_type;
1709                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1710                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1711                 if (BNXT_CHIP_P5(bp)) {
1712                         mb_pool = bp->rx_queues[0]->mb_pool;
1713                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1714                                       RTE_PKTMBUF_HEADROOM;
1715                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1716                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1717                         enables |=
1718                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1719                 }
1720                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1721                         enables |=
1722                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1723                 break;
1724         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1725                 req.ring_type = ring_type;
1726                 if (BNXT_HAS_NQ(bp)) {
1727                         /* Association of cp ring with nq */
1728                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1729                         enables |=
1730                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1731                 }
1732                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1733                 break;
1734         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1735                 req.ring_type = ring_type;
1736                 req.page_size = BNXT_PAGE_SHFT;
1737                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1738                 break;
1739         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1740                 req.ring_type = ring_type;
1741                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1742
1743                 mb_pool = bp->rx_queues[0]->mb_pool;
1744                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1745                               RTE_PKTMBUF_HEADROOM;
1746                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1747                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1748
1749                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1750                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1751                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1752                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1753                 break;
1754         default:
1755                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1756                         ring_type);
1757                 HWRM_UNLOCK();
1758                 return -EINVAL;
1759         }
1760         req.enables = rte_cpu_to_le_32(enables);
1761
1762         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1763
1764         if (rc || resp->error_code) {
1765                 if (rc == 0 && resp->error_code)
1766                         rc = rte_le_to_cpu_16(resp->error_code);
1767                 switch (ring_type) {
1768                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1769                         PMD_DRV_LOG(ERR,
1770                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1771                         HWRM_UNLOCK();
1772                         return rc;
1773                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1774                         PMD_DRV_LOG(ERR,
1775                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1776                         HWRM_UNLOCK();
1777                         return rc;
1778                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1779                         PMD_DRV_LOG(ERR,
1780                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1781                                     rc);
1782                         HWRM_UNLOCK();
1783                         return rc;
1784                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1785                         PMD_DRV_LOG(ERR,
1786                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1787                         HWRM_UNLOCK();
1788                         return rc;
1789                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1790                         PMD_DRV_LOG(ERR,
1791                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1792                         HWRM_UNLOCK();
1793                         return rc;
1794                 default:
1795                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1796                         HWRM_UNLOCK();
1797                         return rc;
1798                 }
1799         }
1800
1801         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1802         HWRM_UNLOCK();
1803         return rc;
1804 }
1805
1806 int bnxt_hwrm_ring_free(struct bnxt *bp,
1807                         struct bnxt_ring *ring, uint32_t ring_type,
1808                         uint16_t cp_ring_id)
1809 {
1810         int rc;
1811         struct hwrm_ring_free_input req = {.req_type = 0 };
1812         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1813
1814         if (ring->fw_ring_id == INVALID_HW_RING_ID)
1815                 return -EINVAL;
1816
1817         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1818
1819         req.ring_type = ring_type;
1820         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1821         req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1822
1823         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1824         ring->fw_ring_id = INVALID_HW_RING_ID;
1825
1826         if (rc || resp->error_code) {
1827                 if (rc == 0 && resp->error_code)
1828                         rc = rte_le_to_cpu_16(resp->error_code);
1829                 HWRM_UNLOCK();
1830
1831                 switch (ring_type) {
1832                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1833                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1834                                 rc);
1835                         return rc;
1836                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1837                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1838                                 rc);
1839                         return rc;
1840                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1841                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1842                                 rc);
1843                         return rc;
1844                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1845                         PMD_DRV_LOG(ERR,
1846                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1847                         return rc;
1848                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1849                         PMD_DRV_LOG(ERR,
1850                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1851                         return rc;
1852                 default:
1853                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1854                         return rc;
1855                 }
1856         }
1857         HWRM_UNLOCK();
1858         return 0;
1859 }
1860
1861 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1862 {
1863         int rc = 0;
1864         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1865         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1866
1867         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1868
1869         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1870         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1871         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1872         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1873
1874         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1875
1876         HWRM_CHECK_RESULT();
1877
1878         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1879
1880         HWRM_UNLOCK();
1881
1882         return rc;
1883 }
1884
1885 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1886 {
1887         int rc;
1888         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1889         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1890
1891         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1892
1893         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1894
1895         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1896
1897         HWRM_CHECK_RESULT();
1898         HWRM_UNLOCK();
1899
1900         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1901         return rc;
1902 }
1903
1904 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1905 {
1906         int rc = 0;
1907         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1908         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1909
1910         if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
1911                 return rc;
1912
1913         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1914
1915         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1916
1917         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1918
1919         HWRM_CHECK_RESULT();
1920         HWRM_UNLOCK();
1921
1922         return rc;
1923 }
1924
1925 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1926 {
1927         int rc;
1928         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1929         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1930
1931         if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE)
1932                 return 0;
1933
1934         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1935
1936         req.update_period_ms = rte_cpu_to_le_32(0);
1937
1938         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1939
1940         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1941
1942         HWRM_CHECK_RESULT();
1943
1944         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1945
1946         HWRM_UNLOCK();
1947
1948         return rc;
1949 }
1950
1951 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1952 {
1953         int rc;
1954         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1955         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1956
1957         if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
1958                 return 0;
1959
1960         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1961
1962         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1963
1964         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1965
1966         HWRM_CHECK_RESULT();
1967         HWRM_UNLOCK();
1968
1969         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1970
1971         return rc;
1972 }
1973
1974 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1975 {
1976         int rc = 0, i, j;
1977         struct hwrm_vnic_alloc_input req = { 0 };
1978         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1979
1980         if (!BNXT_HAS_RING_GRPS(bp))
1981                 goto skip_ring_grps;
1982
1983         /* map ring groups to this vnic */
1984         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1985                 vnic->start_grp_id, vnic->end_grp_id);
1986         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1987                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1988
1989         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1990         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1991         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1992         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1993
1994 skip_ring_grps:
1995         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1996         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1997
1998         if (vnic->func_default)
1999                 req.flags =
2000                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
2001         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2002
2003         HWRM_CHECK_RESULT();
2004
2005         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
2006         HWRM_UNLOCK();
2007         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2008         return rc;
2009 }
2010
2011 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
2012                                         struct bnxt_vnic_info *vnic,
2013                                         struct bnxt_plcmodes_cfg *pmode)
2014 {
2015         int rc = 0;
2016         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
2017         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2018
2019         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
2020
2021         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2022
2023         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2024
2025         HWRM_CHECK_RESULT();
2026
2027         pmode->flags = rte_le_to_cpu_32(resp->flags);
2028         /* dflt_vnic bit doesn't exist in the _cfg command */
2029         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
2030         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
2031         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2032         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2033
2034         HWRM_UNLOCK();
2035
2036         return rc;
2037 }
2038
2039 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2040                                        struct bnxt_vnic_info *vnic,
2041                                        struct bnxt_plcmodes_cfg *pmode)
2042 {
2043         int rc = 0;
2044         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2045         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2046
2047         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2048                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2049                 return rc;
2050         }
2051
2052         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2053
2054         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2055         req.flags = rte_cpu_to_le_32(pmode->flags);
2056         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2057         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2058         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2059         req.enables = rte_cpu_to_le_32(
2060             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2061             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2062             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2063         );
2064
2065         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2066
2067         HWRM_CHECK_RESULT();
2068         HWRM_UNLOCK();
2069
2070         return rc;
2071 }
2072
2073 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2074 {
2075         int rc = 0;
2076         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2077         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2078         struct bnxt_plcmodes_cfg pmodes = { 0 };
2079         uint32_t ctx_enable_flag = 0;
2080         uint32_t enables = 0;
2081
2082         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2083                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2084                 return rc;
2085         }
2086
2087         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2088         if (rc)
2089                 return rc;
2090
2091         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2092
2093         if (BNXT_CHIP_P5(bp)) {
2094                 int dflt_rxq = vnic->start_grp_id;
2095                 struct bnxt_rx_ring_info *rxr;
2096                 struct bnxt_cp_ring_info *cpr;
2097                 struct bnxt_rx_queue *rxq;
2098                 int i;
2099
2100                 /*
2101                  * The first active receive ring is used as the VNIC
2102                  * default receive ring. If there are no active receive
2103                  * rings (all corresponding receive queues are stopped),
2104                  * the first receive ring is used.
2105                  */
2106                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2107                         rxq = bp->eth_dev->data->rx_queues[i];
2108                         if (rxq->rx_started) {
2109                                 dflt_rxq = i;
2110                                 break;
2111                         }
2112                 }
2113
2114                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2115                 rxr = rxq->rx_ring;
2116                 cpr = rxq->cp_ring;
2117
2118                 req.default_rx_ring_id =
2119                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2120                 req.default_cmpl_ring_id =
2121                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2122                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2123                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2124                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2125                         enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2126                         req.rx_csum_v2_mode =
2127                                 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2128                 }
2129                 goto config_mru;
2130         }
2131
2132         /* Only RSS support for now TBD: COS & LB */
2133         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2134         if (vnic->lb_rule != 0xffff)
2135                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2136         if (vnic->cos_rule != 0xffff)
2137                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2138         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2139                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2140                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2141         }
2142         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2143                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2144                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2145         }
2146
2147         enables |= ctx_enable_flag;
2148         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2149         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2150         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2151         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2152
2153 config_mru:
2154         req.enables = rte_cpu_to_le_32(enables);
2155         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2156         req.mru = rte_cpu_to_le_16(vnic->mru);
2157         /* Configure default VNIC only once. */
2158         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2159                 req.flags |=
2160                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2161                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2162         }
2163         if (vnic->vlan_strip)
2164                 req.flags |=
2165                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2166         if (vnic->bd_stall)
2167                 req.flags |=
2168                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2169         if (vnic->rss_dflt_cr)
2170                 req.flags |= rte_cpu_to_le_32(
2171                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2172
2173         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2174
2175         HWRM_CHECK_RESULT();
2176         HWRM_UNLOCK();
2177
2178         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2179
2180         return rc;
2181 }
2182
2183 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2184                 int16_t fw_vf_id)
2185 {
2186         int rc = 0;
2187         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2188         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2189
2190         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2191                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2192                 return rc;
2193         }
2194         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2195
2196         req.enables =
2197                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2198         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2199         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2200
2201         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2202
2203         HWRM_CHECK_RESULT();
2204
2205         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2206         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2207         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2208         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2209         vnic->mru = rte_le_to_cpu_16(resp->mru);
2210         vnic->func_default = rte_le_to_cpu_32(
2211                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2212         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2213                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2214         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2215                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2216         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2217                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2218
2219         HWRM_UNLOCK();
2220
2221         return rc;
2222 }
2223
2224 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2225                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2226 {
2227         int rc = 0;
2228         uint16_t ctx_id;
2229         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2230         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2231                                                 bp->hwrm_cmd_resp_addr;
2232
2233         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2234
2235         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2236         HWRM_CHECK_RESULT();
2237
2238         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2239         if (!BNXT_HAS_RING_GRPS(bp))
2240                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2241         else if (ctx_idx == 0)
2242                 vnic->rss_rule = ctx_id;
2243
2244         HWRM_UNLOCK();
2245
2246         return rc;
2247 }
2248
2249 static
2250 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2251                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2252 {
2253         int rc = 0;
2254         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2255         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2256                                                 bp->hwrm_cmd_resp_addr;
2257
2258         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2259                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2260                 return rc;
2261         }
2262         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2263
2264         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2265
2266         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2267
2268         HWRM_CHECK_RESULT();
2269         HWRM_UNLOCK();
2270
2271         return rc;
2272 }
2273
2274 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2275 {
2276         int rc = 0;
2277
2278         if (BNXT_CHIP_P5(bp)) {
2279                 int j;
2280
2281                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2282                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2283                                                       vnic,
2284                                                       vnic->fw_grp_ids[j]);
2285                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2286                 }
2287                 vnic->num_lb_ctxts = 0;
2288         } else {
2289                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2290                 vnic->rss_rule = INVALID_HW_RING_ID;
2291         }
2292
2293         return rc;
2294 }
2295
2296 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2297 {
2298         int rc = 0;
2299         struct hwrm_vnic_free_input req = {.req_type = 0 };
2300         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2301
2302         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2303                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2304                 return rc;
2305         }
2306
2307         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2308
2309         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2310
2311         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2312
2313         HWRM_CHECK_RESULT();
2314         HWRM_UNLOCK();
2315
2316         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2317         /* Configure default VNIC again if necessary. */
2318         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2319                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2320
2321         return rc;
2322 }
2323
2324 static int
2325 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2326 {
2327         int i;
2328         int rc = 0;
2329         int nr_ctxs = vnic->num_lb_ctxts;
2330         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2331         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2332
2333         for (i = 0; i < nr_ctxs; i++) {
2334                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2335
2336                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2337                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2338                 req.hash_mode_flags = vnic->hash_mode;
2339
2340                 req.hash_key_tbl_addr =
2341                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2342
2343                 req.ring_grp_tbl_addr =
2344                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2345                                          i * HW_HASH_INDEX_SIZE);
2346                 req.ring_table_pair_index = i;
2347                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2348
2349                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2350                                             BNXT_USE_CHIMP_MB);
2351
2352                 HWRM_CHECK_RESULT();
2353                 HWRM_UNLOCK();
2354         }
2355
2356         return rc;
2357 }
2358
2359 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2360                            struct bnxt_vnic_info *vnic)
2361 {
2362         int rc = 0;
2363         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2364         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2365
2366         if (!vnic->rss_table)
2367                 return 0;
2368
2369         if (BNXT_CHIP_P5(bp))
2370                 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2371
2372         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2373
2374         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2375         req.hash_mode_flags = vnic->hash_mode;
2376
2377         req.ring_grp_tbl_addr =
2378             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2379         req.hash_key_tbl_addr =
2380             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2381         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2382         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2383
2384         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2385
2386         HWRM_CHECK_RESULT();
2387         HWRM_UNLOCK();
2388
2389         return rc;
2390 }
2391
2392 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2393                         struct bnxt_vnic_info *vnic)
2394 {
2395         int rc = 0;
2396         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2397         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2398         uint16_t size;
2399
2400         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2401                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2402                 return rc;
2403         }
2404
2405         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2406
2407         req.flags = rte_cpu_to_le_32(
2408                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2409
2410         req.enables = rte_cpu_to_le_32(
2411                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2412
2413         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2414         size -= RTE_PKTMBUF_HEADROOM;
2415         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2416
2417         req.jumbo_thresh = rte_cpu_to_le_16(size);
2418         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2419
2420         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2421
2422         HWRM_CHECK_RESULT();
2423         HWRM_UNLOCK();
2424
2425         return rc;
2426 }
2427
2428 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2429                         struct bnxt_vnic_info *vnic, bool enable)
2430 {
2431         int rc = 0;
2432         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2433         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2434
2435         if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2436                 if (enable)
2437                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2438                 return -ENOTSUP;
2439         }
2440
2441         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2442                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2443                 return 0;
2444         }
2445
2446         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2447
2448         if (enable) {
2449                 req.enables = rte_cpu_to_le_32(
2450                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2451                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2452                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2453                 req.flags = rte_cpu_to_le_32(
2454                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2455                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2456                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2457                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2458                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2459                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2460                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2461                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2462                 req.min_agg_len = rte_cpu_to_le_32(512);
2463         }
2464         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2465
2466         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2467
2468         HWRM_CHECK_RESULT();
2469         HWRM_UNLOCK();
2470
2471         return rc;
2472 }
2473
2474 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2475 {
2476         struct hwrm_func_cfg_input req = {0};
2477         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2478         int rc;
2479
2480         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2481         req.enables = rte_cpu_to_le_32(
2482                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2483         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2484         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2485
2486         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2487
2488         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2489         HWRM_CHECK_RESULT();
2490         HWRM_UNLOCK();
2491
2492         bp->pf->vf_info[vf].random_mac = false;
2493
2494         return rc;
2495 }
2496
2497 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2498                                   uint64_t *dropped)
2499 {
2500         int rc = 0;
2501         struct hwrm_func_qstats_input req = {.req_type = 0};
2502         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2503
2504         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2505
2506         req.fid = rte_cpu_to_le_16(fid);
2507
2508         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2509
2510         HWRM_CHECK_RESULT();
2511
2512         if (dropped)
2513                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2514
2515         HWRM_UNLOCK();
2516
2517         return rc;
2518 }
2519
2520 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2521                           struct rte_eth_stats *stats,
2522                           struct hwrm_func_qstats_output *func_qstats)
2523 {
2524         int rc = 0;
2525         struct hwrm_func_qstats_input req = {.req_type = 0};
2526         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2527
2528         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2529
2530         req.fid = rte_cpu_to_le_16(fid);
2531
2532         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2533
2534         HWRM_CHECK_RESULT();
2535         if (func_qstats)
2536                 memcpy(func_qstats, resp,
2537                        sizeof(struct hwrm_func_qstats_output));
2538
2539         if (!stats)
2540                 goto exit;
2541
2542         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2543         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2544         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2545         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2546         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2547         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2548
2549         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2550         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2551         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2552         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2553         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2554         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2555
2556         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2557         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2558         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2559
2560 exit:
2561         HWRM_UNLOCK();
2562
2563         return rc;
2564 }
2565
2566 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2567 {
2568         int rc = 0;
2569         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2570         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2571
2572         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2573
2574         req.fid = rte_cpu_to_le_16(fid);
2575
2576         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2577
2578         HWRM_CHECK_RESULT();
2579         HWRM_UNLOCK();
2580
2581         return rc;
2582 }
2583
2584 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2585 {
2586         unsigned int i;
2587         int rc = 0;
2588
2589         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2590                 struct bnxt_tx_queue *txq;
2591                 struct bnxt_rx_queue *rxq;
2592                 struct bnxt_cp_ring_info *cpr;
2593
2594                 if (i >= bp->rx_cp_nr_rings) {
2595                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2596                         cpr = txq->cp_ring;
2597                 } else {
2598                         rxq = bp->rx_queues[i];
2599                         cpr = rxq->cp_ring;
2600                 }
2601
2602                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2603                 if (rc)
2604                         return rc;
2605         }
2606         return 0;
2607 }
2608
2609 static int
2610 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2611 {
2612         int rc;
2613         unsigned int i;
2614         struct bnxt_cp_ring_info *cpr;
2615
2616         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2617
2618                 cpr = bp->rx_queues[i]->cp_ring;
2619                 if (BNXT_HAS_RING_GRPS(bp))
2620                         bp->grp_info[i].fw_stats_ctx = -1;
2621                 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2622                 if (rc)
2623                         return rc;
2624         }
2625
2626         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2627                 cpr = bp->tx_queues[i]->cp_ring;
2628                 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2629                 if (rc)
2630                         return rc;
2631         }
2632
2633         return 0;
2634 }
2635
2636 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2637 {
2638         struct bnxt_cp_ring_info *cpr;
2639         unsigned int i;
2640         int rc = 0;
2641
2642         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2643                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
2644
2645                 cpr = rxq->cp_ring;
2646                 if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE) {
2647                         rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
2648                         if (rc)
2649                                 return rc;
2650                 }
2651         }
2652
2653         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2654                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2655
2656                 cpr = txq->cp_ring;
2657                 if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE) {
2658                         rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
2659                         if (rc)
2660                                 return rc;
2661                 }
2662         }
2663
2664         return rc;
2665 }
2666
2667 static int
2668 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2669 {
2670         uint16_t idx;
2671         uint32_t rc = 0;
2672
2673         if (!BNXT_HAS_RING_GRPS(bp))
2674                 return 0;
2675
2676         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2677
2678                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2679                         continue;
2680
2681                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2682
2683                 if (rc)
2684                         return rc;
2685         }
2686         return rc;
2687 }
2688
2689 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2690 {
2691         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2692
2693         bnxt_hwrm_ring_free(bp, cp_ring,
2694                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2695                             INVALID_HW_RING_ID);
2696         memset(cpr->cp_desc_ring, 0,
2697                cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
2698         cpr->cp_raw_cons = 0;
2699 }
2700
2701 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2702 {
2703         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2704
2705         bnxt_hwrm_ring_free(bp, cp_ring,
2706                             HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2707                             INVALID_HW_RING_ID);
2708         memset(cpr->cp_desc_ring, 0,
2709                cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
2710         cpr->cp_raw_cons = 0;
2711 }
2712
2713 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2714 {
2715         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2716         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2717         struct bnxt_ring *ring = rxr->rx_ring_struct;
2718         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2719
2720         if (BNXT_HAS_RING_GRPS(bp))
2721                 bnxt_hwrm_ring_grp_free(bp, queue_index);
2722
2723         bnxt_hwrm_ring_free(bp, ring,
2724                             HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2725                             cpr->cp_ring_struct->fw_ring_id);
2726         if (BNXT_HAS_RING_GRPS(bp))
2727                 bp->grp_info[queue_index].rx_fw_ring_id = INVALID_HW_RING_ID;
2728
2729         ring = rxr->ag_ring_struct;
2730         bnxt_hwrm_ring_free(bp, ring,
2731                             BNXT_CHIP_P5(bp) ?
2732                             HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2733                             HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2734                             cpr->cp_ring_struct->fw_ring_id);
2735         if (BNXT_HAS_RING_GRPS(bp))
2736                 bp->grp_info[queue_index].ag_fw_ring_id = INVALID_HW_RING_ID;
2737
2738         bnxt_hwrm_stat_ctx_free(bp, cpr);
2739
2740         bnxt_free_cp_ring(bp, cpr);
2741
2742         if (BNXT_HAS_RING_GRPS(bp))
2743                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2744 }
2745
2746 int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int queue_index)
2747 {
2748         int rc;
2749         struct hwrm_ring_reset_input req = {.req_type = 0 };
2750         struct hwrm_ring_reset_output *resp = bp->hwrm_cmd_resp_addr;
2751
2752         HWRM_PREP(&req, HWRM_RING_RESET, BNXT_USE_CHIMP_MB);
2753
2754         req.ring_type = HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP;
2755         req.ring_id = rte_cpu_to_le_16(bp->grp_info[queue_index].fw_grp_id);
2756         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2757
2758         HWRM_CHECK_RESULT();
2759
2760         HWRM_UNLOCK();
2761
2762         return rc;
2763 }
2764
2765 static int
2766 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2767 {
2768         unsigned int i;
2769
2770         for (i = 0; i < bp->tx_cp_nr_rings; i++)
2771                 bnxt_free_hwrm_tx_ring(bp, i);
2772
2773         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2774                 bnxt_free_hwrm_rx_ring(bp, i);
2775
2776         return 0;
2777 }
2778
2779 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2780 {
2781         uint16_t i;
2782         uint32_t rc = 0;
2783
2784         if (!BNXT_HAS_RING_GRPS(bp))
2785                 return 0;
2786
2787         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2788                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2789                 if (rc)
2790                         return rc;
2791         }
2792         return rc;
2793 }
2794
2795 /*
2796  * HWRM utility functions
2797  */
2798
2799 void bnxt_free_hwrm_resources(struct bnxt *bp)
2800 {
2801         /* Release memzone */
2802         rte_free(bp->hwrm_cmd_resp_addr);
2803         rte_free(bp->hwrm_short_cmd_req_addr);
2804         bp->hwrm_cmd_resp_addr = NULL;
2805         bp->hwrm_short_cmd_req_addr = NULL;
2806         bp->hwrm_cmd_resp_dma_addr = 0;
2807         bp->hwrm_short_cmd_req_dma_addr = 0;
2808 }
2809
2810 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2811 {
2812         struct rte_pci_device *pdev = bp->pdev;
2813         char type[RTE_MEMZONE_NAMESIZE];
2814
2815         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2816                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2817         bp->max_resp_len = BNXT_PAGE_SIZE;
2818         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2819         if (bp->hwrm_cmd_resp_addr == NULL)
2820                 return -ENOMEM;
2821         bp->hwrm_cmd_resp_dma_addr =
2822                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2823         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2824                 PMD_DRV_LOG(ERR,
2825                         "unable to map response address to physical memory\n");
2826                 return -ENOMEM;
2827         }
2828         rte_spinlock_init(&bp->hwrm_lock);
2829
2830         return 0;
2831 }
2832
2833 int
2834 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2835 {
2836         int rc = 0;
2837
2838         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2839                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2840                 if (rc)
2841                         return rc;
2842         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2843                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2844                 if (rc)
2845                         return rc;
2846         }
2847
2848         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2849         return rc;
2850 }
2851
2852 static int
2853 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2854 {
2855         struct bnxt_filter_info *filter;
2856         int rc = 0;
2857
2858         STAILQ_FOREACH(filter, &vnic->filter, next) {
2859                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2860                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2861                 bnxt_free_filter(bp, filter);
2862         }
2863         return rc;
2864 }
2865
2866 static int
2867 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2868 {
2869         struct bnxt_filter_info *filter;
2870         struct rte_flow *flow;
2871         int rc = 0;
2872
2873         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2874                 flow = STAILQ_FIRST(&vnic->flow_list);
2875                 filter = flow->filter;
2876                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2877                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2878
2879                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2880                 rte_free(flow);
2881         }
2882         return rc;
2883 }
2884
2885 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2886 {
2887         struct bnxt_filter_info *filter;
2888         int rc = 0;
2889
2890         STAILQ_FOREACH(filter, &vnic->filter, next) {
2891                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2892                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2893                                                      filter);
2894                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2895                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2896                                                          filter);
2897                 else
2898                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2899                                                      filter);
2900                 if (rc)
2901                         break;
2902         }
2903         return rc;
2904 }
2905
2906 static void
2907 bnxt_free_tunnel_ports(struct bnxt *bp)
2908 {
2909         if (bp->vxlan_port_cnt)
2910                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2911                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2912
2913         if (bp->geneve_port_cnt)
2914                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2915                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2916 }
2917
2918 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2919 {
2920         int i;
2921
2922         if (bp->vnic_info == NULL)
2923                 return;
2924
2925         /*
2926          * Cleanup VNICs in reverse order, to make sure the L2 filter
2927          * from vnic0 is last to be cleaned up.
2928          */
2929         for (i = bp->max_vnics - 1; i >= 0; i--) {
2930                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2931
2932                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2933                         continue;
2934
2935                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2936
2937                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2938
2939                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2940
2941                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2942
2943                 bnxt_hwrm_vnic_free(bp, vnic);
2944
2945                 rte_free(vnic->fw_grp_ids);
2946         }
2947         /* Ring resources */
2948         bnxt_free_all_hwrm_rings(bp);
2949         bnxt_free_all_hwrm_ring_grps(bp);
2950         bnxt_free_all_hwrm_stat_ctxs(bp);
2951         bnxt_free_tunnel_ports(bp);
2952 }
2953
2954 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2955 {
2956         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2957
2958         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2959                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2960
2961         switch (conf_link_speed) {
2962         case ETH_LINK_SPEED_10M_HD:
2963         case ETH_LINK_SPEED_100M_HD:
2964                 /* FALLTHROUGH */
2965                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2966         }
2967         return hw_link_duplex;
2968 }
2969
2970 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2971 {
2972         return !conf_link;
2973 }
2974
2975 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2976                                           uint16_t pam4_link)
2977 {
2978         uint16_t eth_link_speed = 0;
2979
2980         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2981                 return ETH_LINK_SPEED_AUTONEG;
2982
2983         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2984         case ETH_LINK_SPEED_100M:
2985         case ETH_LINK_SPEED_100M_HD:
2986                 /* FALLTHROUGH */
2987                 eth_link_speed =
2988                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2989                 break;
2990         case ETH_LINK_SPEED_1G:
2991                 eth_link_speed =
2992                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2993                 break;
2994         case ETH_LINK_SPEED_2_5G:
2995                 eth_link_speed =
2996                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2997                 break;
2998         case ETH_LINK_SPEED_10G:
2999                 eth_link_speed =
3000                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
3001                 break;
3002         case ETH_LINK_SPEED_20G:
3003                 eth_link_speed =
3004                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
3005                 break;
3006         case ETH_LINK_SPEED_25G:
3007                 eth_link_speed =
3008                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
3009                 break;
3010         case ETH_LINK_SPEED_40G:
3011                 eth_link_speed =
3012                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
3013                 break;
3014         case ETH_LINK_SPEED_50G:
3015                 eth_link_speed = pam4_link ?
3016                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
3017                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
3018                 break;
3019         case ETH_LINK_SPEED_100G:
3020                 eth_link_speed = pam4_link ?
3021                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
3022                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
3023                 break;
3024         case ETH_LINK_SPEED_200G:
3025                 eth_link_speed =
3026                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3027                 break;
3028         default:
3029                 PMD_DRV_LOG(ERR,
3030                         "Unsupported link speed %d; default to AUTO\n",
3031                         conf_link_speed);
3032                 break;
3033         }
3034         return eth_link_speed;
3035 }
3036
3037 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
3038                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
3039                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
3040                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
3041                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
3042
3043 static int bnxt_validate_link_speed(struct bnxt *bp)
3044 {
3045         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3046         uint16_t port_id = bp->eth_dev->data->port_id;
3047         uint32_t link_speed_capa;
3048         uint32_t one_speed;
3049
3050         if (link_speed == ETH_LINK_SPEED_AUTONEG)
3051                 return 0;
3052
3053         link_speed_capa = bnxt_get_speed_capabilities(bp);
3054
3055         if (link_speed & ETH_LINK_SPEED_FIXED) {
3056                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
3057
3058                 if (one_speed & (one_speed - 1)) {
3059                         PMD_DRV_LOG(ERR,
3060                                 "Invalid advertised speeds (%u) for port %u\n",
3061                                 link_speed, port_id);
3062                         return -EINVAL;
3063                 }
3064                 if ((one_speed & link_speed_capa) != one_speed) {
3065                         PMD_DRV_LOG(ERR,
3066                                 "Unsupported advertised speed (%u) for port %u\n",
3067                                 link_speed, port_id);
3068                         return -EINVAL;
3069                 }
3070         } else {
3071                 if (!(link_speed & link_speed_capa)) {
3072                         PMD_DRV_LOG(ERR,
3073                                 "Unsupported advertised speeds (%u) for port %u\n",
3074                                 link_speed, port_id);
3075                         return -EINVAL;
3076                 }
3077         }
3078         return 0;
3079 }
3080
3081 static uint16_t
3082 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3083 {
3084         uint16_t ret = 0;
3085
3086         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
3087                 if (bp->link_info->support_speeds)
3088                         return bp->link_info->support_speeds;
3089                 link_speed = BNXT_SUPPORTED_SPEEDS;
3090         }
3091
3092         if (link_speed & ETH_LINK_SPEED_100M)
3093                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3094         if (link_speed & ETH_LINK_SPEED_100M_HD)
3095                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3096         if (link_speed & ETH_LINK_SPEED_1G)
3097                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3098         if (link_speed & ETH_LINK_SPEED_2_5G)
3099                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3100         if (link_speed & ETH_LINK_SPEED_10G)
3101                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3102         if (link_speed & ETH_LINK_SPEED_20G)
3103                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3104         if (link_speed & ETH_LINK_SPEED_25G)
3105                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3106         if (link_speed & ETH_LINK_SPEED_40G)
3107                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3108         if (link_speed & ETH_LINK_SPEED_50G)
3109                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3110         if (link_speed & ETH_LINK_SPEED_100G)
3111                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3112         if (link_speed & ETH_LINK_SPEED_200G)
3113                 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3114         return ret;
3115 }
3116
3117 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3118 {
3119         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
3120
3121         switch (hw_link_speed) {
3122         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3123                 eth_link_speed = ETH_SPEED_NUM_100M;
3124                 break;
3125         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3126                 eth_link_speed = ETH_SPEED_NUM_1G;
3127                 break;
3128         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3129                 eth_link_speed = ETH_SPEED_NUM_2_5G;
3130                 break;
3131         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3132                 eth_link_speed = ETH_SPEED_NUM_10G;
3133                 break;
3134         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3135                 eth_link_speed = ETH_SPEED_NUM_20G;
3136                 break;
3137         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3138                 eth_link_speed = ETH_SPEED_NUM_25G;
3139                 break;
3140         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3141                 eth_link_speed = ETH_SPEED_NUM_40G;
3142                 break;
3143         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3144                 eth_link_speed = ETH_SPEED_NUM_50G;
3145                 break;
3146         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3147                 eth_link_speed = ETH_SPEED_NUM_100G;
3148                 break;
3149         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3150                 eth_link_speed = ETH_SPEED_NUM_200G;
3151                 break;
3152         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3153         default:
3154                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3155                         hw_link_speed);
3156                 break;
3157         }
3158         return eth_link_speed;
3159 }
3160
3161 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3162 {
3163         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3164
3165         switch (hw_link_duplex) {
3166         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3167         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3168                 /* FALLTHROUGH */
3169                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3170                 break;
3171         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3172                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3173                 break;
3174         default:
3175                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3176                         hw_link_duplex);
3177                 break;
3178         }
3179         return eth_link_duplex;
3180 }
3181
3182 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3183 {
3184         int rc = 0;
3185         struct bnxt_link_info *link_info = bp->link_info;
3186
3187         rc = bnxt_hwrm_port_phy_qcaps(bp);
3188         if (rc)
3189                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3190
3191         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3192         if (rc) {
3193                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3194                 goto exit;
3195         }
3196
3197         if (link_info->link_speed)
3198                 link->link_speed =
3199                         bnxt_parse_hw_link_speed(link_info->link_speed);
3200         else
3201                 link->link_speed = ETH_SPEED_NUM_NONE;
3202         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3203         link->link_status = link_info->link_up;
3204         link->link_autoneg = link_info->auto_mode ==
3205                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3206                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3207 exit:
3208         return rc;
3209 }
3210
3211 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3212 {
3213         int rc = 0;
3214         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3215         struct bnxt_link_info link_req;
3216         uint16_t speed, autoneg;
3217
3218         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3219                 return 0;
3220
3221         rc = bnxt_validate_link_speed(bp);
3222         if (rc)
3223                 goto error;
3224
3225         memset(&link_req, 0, sizeof(link_req));
3226         link_req.link_up = link_up;
3227         if (!link_up)
3228                 goto port_phy_cfg;
3229
3230         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3231         if (BNXT_CHIP_P5(bp) &&
3232             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3233                 /* 40G is not supported as part of media auto detect.
3234                  * The speed should be forced and autoneg disabled
3235                  * to configure 40G speed.
3236                  */
3237                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3238                 autoneg = 0;
3239         }
3240
3241         /* No auto speeds and no auto_pam4_link. Disable autoneg */
3242         if (bp->link_info->auto_link_speed == 0 &&
3243             bp->link_info->link_signal_mode &&
3244             bp->link_info->auto_pam4_link_speeds == 0)
3245                 autoneg = 0;
3246
3247         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3248                                           bp->link_info->link_signal_mode);
3249         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3250         /* Autoneg can be done only when the FW allows. */
3251         if (autoneg == 1 && bp->link_info->support_auto_speeds) {
3252                 link_req.phy_flags |=
3253                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3254                 link_req.auto_link_speed_mask =
3255                         bnxt_parse_eth_link_speed_mask(bp,
3256                                                        dev_conf->link_speeds);
3257         } else {
3258                 if (bp->link_info->phy_type ==
3259                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3260                     bp->link_info->phy_type ==
3261                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3262                     bp->link_info->media_type ==
3263                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3264                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3265                         return -EINVAL;
3266                 }
3267
3268                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3269                 /* If user wants a particular speed try that first. */
3270                 if (speed)
3271                         link_req.link_speed = speed;
3272                 else if (bp->link_info->force_pam4_link_speed)
3273                         link_req.link_speed =
3274                                 bp->link_info->force_pam4_link_speed;
3275                 else if (bp->link_info->auto_pam4_link_speeds)
3276                         link_req.link_speed =
3277                                 bp->link_info->auto_pam4_link_speeds;
3278                 else if (bp->link_info->support_pam4_speeds)
3279                         link_req.link_speed =
3280                                 bp->link_info->support_pam4_speeds;
3281                 else if (bp->link_info->force_link_speed)
3282                         link_req.link_speed = bp->link_info->force_link_speed;
3283                 else
3284                         link_req.link_speed = bp->link_info->auto_link_speed;
3285                 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3286                  * zero. Use the auto_link_speed.
3287                  */
3288                 if (bp->link_info->auto_link_speed != 0 &&
3289                     bp->link_info->auto_pam4_link_speeds == 0)
3290                         link_req.link_speed = bp->link_info->auto_link_speed;
3291         }
3292         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3293         link_req.auto_pause = bp->link_info->auto_pause;
3294         link_req.force_pause = bp->link_info->force_pause;
3295
3296 port_phy_cfg:
3297         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3298         if (rc) {
3299                 PMD_DRV_LOG(ERR,
3300                         "Set link config failed with rc %d\n", rc);
3301         }
3302
3303 error:
3304         return rc;
3305 }
3306
3307 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3308 {
3309         struct hwrm_func_qcfg_input req = {0};
3310         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3311         uint16_t flags;
3312         int rc = 0;
3313         bp->func_svif = BNXT_SVIF_INVALID;
3314         uint16_t svif_info;
3315
3316         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3317         req.fid = rte_cpu_to_le_16(0xffff);
3318
3319         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3320
3321         HWRM_CHECK_RESULT();
3322
3323         bp->vlan = rte_le_to_cpu_16(resp->vlan) & ETH_VLAN_ID_MAX;
3324
3325         svif_info = rte_le_to_cpu_16(resp->svif_info);
3326         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3327                 bp->func_svif = svif_info &
3328                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3329
3330         flags = rte_le_to_cpu_16(resp->flags);
3331         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3332                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3333
3334         if (BNXT_VF(bp) &&
3335             !BNXT_VF_IS_TRUSTED(bp) &&
3336             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3337                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3338                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3339         } else if (BNXT_VF(bp) &&
3340                    BNXT_VF_IS_TRUSTED(bp) &&
3341                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3342                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3343                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3344         }
3345
3346         if (mtu)
3347                 *mtu = rte_le_to_cpu_16(resp->admin_mtu);
3348
3349         switch (resp->port_partition_type) {
3350         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3351         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3352         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3353                 /* FALLTHROUGH */
3354                 bp->flags |= BNXT_FLAG_NPAR_PF;
3355                 break;
3356         default:
3357                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3358                 break;
3359         }
3360
3361         bp->legacy_db_size =
3362                 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3363
3364         HWRM_UNLOCK();
3365
3366         return rc;
3367 }
3368
3369 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3370 {
3371         struct hwrm_func_qcfg_input req = {0};
3372         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3373         int rc;
3374
3375         if (!BNXT_VF_IS_TRUSTED(bp))
3376                 return 0;
3377
3378         if (!bp->parent)
3379                 return -EINVAL;
3380
3381         bp->parent->fid = BNXT_PF_FID_INVALID;
3382
3383         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3384
3385         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3386
3387         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3388
3389         HWRM_CHECK_RESULT_SILENT();
3390
3391         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3392         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3393         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3394         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3395
3396         HWRM_UNLOCK();
3397
3398         return 0;
3399 }
3400
3401 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3402                                  uint16_t *vnic_id, uint16_t *svif)
3403 {
3404         struct hwrm_func_qcfg_input req = {0};
3405         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3406         uint16_t svif_info;
3407         int rc = 0;
3408
3409         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3410         req.fid = rte_cpu_to_le_16(fid);
3411
3412         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3413
3414         HWRM_CHECK_RESULT();
3415
3416         if (vnic_id)
3417                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3418
3419         svif_info = rte_le_to_cpu_16(resp->svif_info);
3420         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3421                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3422
3423         HWRM_UNLOCK();
3424
3425         return rc;
3426 }
3427
3428 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3429 {
3430         struct hwrm_port_mac_qcfg_input req = {0};
3431         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3432         uint16_t port_svif_info;
3433         int rc;
3434
3435         bp->port_svif = BNXT_SVIF_INVALID;
3436
3437         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3438                 return 0;
3439
3440         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3441
3442         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3443
3444         HWRM_CHECK_RESULT_SILENT();
3445
3446         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3447         if (port_svif_info &
3448             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3449                 bp->port_svif = port_svif_info &
3450                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3451
3452         HWRM_UNLOCK();
3453
3454         return 0;
3455 }
3456
3457 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3458                                  struct bnxt_pf_resource_info *pf_resc)
3459 {
3460         struct hwrm_func_cfg_input req = {0};
3461         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3462         uint32_t enables;
3463         int rc;
3464
3465         enables = HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
3466                   HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU |
3467                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3468                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3469                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3470                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3471                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3472                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3473                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3474                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3475
3476         if (BNXT_HAS_RING_GRPS(bp)) {
3477                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3478                 req.num_hw_ring_grps =
3479                         rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3480         } else if (BNXT_HAS_NQ(bp)) {
3481                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3482                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3483         }
3484
3485         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3486         req.admin_mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3487         req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
3488         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3489         req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3490         req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3491         req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3492         req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3493         req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3494         req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3495         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3496         req.fid = rte_cpu_to_le_16(0xffff);
3497         req.enables = rte_cpu_to_le_32(enables);
3498
3499         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3500
3501         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3502
3503         HWRM_CHECK_RESULT();
3504         HWRM_UNLOCK();
3505
3506         return rc;
3507 }
3508
3509 /* min values are the guaranteed resources and max values are subject
3510  * to availability. The strategy for now is to keep both min & max
3511  * values the same.
3512  */
3513 static void
3514 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3515                               struct hwrm_func_vf_resource_cfg_input *req,
3516                               int num_vfs)
3517 {
3518         req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3519                                                (num_vfs + 1));
3520         req->min_rsscos_ctx = req->max_rsscos_ctx;
3521         req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3522         req->min_stat_ctx = req->max_stat_ctx;
3523         req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3524                                                (num_vfs + 1));
3525         req->min_cmpl_rings = req->max_cmpl_rings;
3526         req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3527         req->min_tx_rings = req->max_tx_rings;
3528         req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3529         req->min_rx_rings = req->max_rx_rings;
3530         req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3531         req->min_l2_ctxs = req->max_l2_ctxs;
3532         /* TODO: For now, do not support VMDq/RFS on VFs. */
3533         req->max_vnics = rte_cpu_to_le_16(1);
3534         req->min_vnics = req->max_vnics;
3535         req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3536                                                  (num_vfs + 1));
3537         req->min_hw_ring_grps = req->max_hw_ring_grps;
3538         req->flags =
3539          rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3540 }
3541
3542 static void
3543 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3544                               struct hwrm_func_cfg_input *req,
3545                               int num_vfs)
3546 {
3547         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
3548                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3549                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3550                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3551                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3552                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3553                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3554                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3555                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3556                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3557
3558         req->admin_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3559                                           RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3560                                           BNXT_NUM_VLANS);
3561         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3562         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3563                                                 (num_vfs + 1));
3564         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3565         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3566                                                (num_vfs + 1));
3567         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3568         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3569         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3570         /* TODO: For now, do not support VMDq/RFS on VFs. */
3571         req->num_vnics = rte_cpu_to_le_16(1);
3572         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3573                                                  (num_vfs + 1));
3574 }
3575
3576 /* Update the port wide resource values based on how many resources
3577  * got allocated to the VF.
3578  */
3579 static int bnxt_update_max_resources(struct bnxt *bp,
3580                                      int vf)
3581 {
3582         struct hwrm_func_qcfg_input req = {0};
3583         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3584         int rc;
3585
3586         /* Get the actual allocated values now */
3587         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3588         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3589         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3590         HWRM_CHECK_RESULT();
3591
3592         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3593         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3594         bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3595         bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3596         bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3597         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3598         bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3599
3600         HWRM_UNLOCK();
3601
3602         return 0;
3603 }
3604
3605 /* Update the PF resource values based on how many resources
3606  * got allocated to it.
3607  */
3608 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3609 {
3610         struct hwrm_func_qcfg_input req = {0};
3611         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3612         int rc;
3613
3614         /* Get the actual allocated values now */
3615         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3616         req.fid = rte_cpu_to_le_16(0xffff);
3617         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3618         HWRM_CHECK_RESULT();
3619
3620         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3621         bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3622         bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3623         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3624         bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3625         bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3626         bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3627         bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3628
3629         HWRM_UNLOCK();
3630
3631         return 0;
3632 }
3633
3634 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3635 {
3636         struct hwrm_func_qcfg_input req = {0};
3637         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3638         int rc;
3639
3640         /* Check for zero MAC address */
3641         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3642         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3643         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3644         HWRM_CHECK_RESULT();
3645         rc = rte_le_to_cpu_16(resp->vlan);
3646
3647         HWRM_UNLOCK();
3648
3649         return rc;
3650 }
3651
3652 static int bnxt_query_pf_resources(struct bnxt *bp,
3653                                    struct bnxt_pf_resource_info *pf_resc)
3654 {
3655         struct hwrm_func_qcfg_input req = {0};
3656         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3657         int rc;
3658
3659         /* And copy the allocated numbers into the pf struct */
3660         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3661         req.fid = rte_cpu_to_le_16(0xffff);
3662         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3663         HWRM_CHECK_RESULT();
3664
3665         pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3666         pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3667         pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3668         pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3669         pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3670         pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3671         pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3672         bp->pf->evb_mode = resp->evb_mode;
3673
3674         HWRM_UNLOCK();
3675
3676         return rc;
3677 }
3678
3679 static void
3680 bnxt_calculate_pf_resources(struct bnxt *bp,
3681                             struct bnxt_pf_resource_info *pf_resc,
3682                             int num_vfs)
3683 {
3684         if (!num_vfs) {
3685                 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3686                 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3687                 pf_resc->num_cp_rings = bp->max_cp_rings;
3688                 pf_resc->num_tx_rings = bp->max_tx_rings;
3689                 pf_resc->num_rx_rings = bp->max_rx_rings;
3690                 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3691                 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3692
3693                 return;
3694         }
3695
3696         pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3697                                    bp->max_rsscos_ctx % (num_vfs + 1);
3698         pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3699                                  bp->max_stat_ctx % (num_vfs + 1);
3700         pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3701                                 bp->max_cp_rings % (num_vfs + 1);
3702         pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3703                                 bp->max_tx_rings % (num_vfs + 1);
3704         pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3705                                 bp->max_rx_rings % (num_vfs + 1);
3706         pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3707                                bp->max_l2_ctx % (num_vfs + 1);
3708         pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3709                                     bp->max_ring_grps % (num_vfs + 1);
3710 }
3711
3712 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3713 {
3714         struct bnxt_pf_resource_info pf_resc = { 0 };
3715         int rc;
3716
3717         if (!BNXT_PF(bp)) {
3718                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3719                 return -EINVAL;
3720         }
3721
3722         rc = bnxt_hwrm_func_qcaps(bp);
3723         if (rc)
3724                 return rc;
3725
3726         bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3727
3728         bp->pf->func_cfg_flags &=
3729                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3730                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3731         bp->pf->func_cfg_flags |=
3732                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3733
3734         rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3735         if (rc)
3736                 return rc;
3737
3738         rc = bnxt_update_max_resources_pf_only(bp);
3739
3740         return rc;
3741 }
3742
3743 static int
3744 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3745 {
3746         size_t req_buf_sz, sz;
3747         int i, rc;
3748
3749         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3750         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3751                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3752         if (bp->pf->vf_req_buf == NULL) {
3753                 return -ENOMEM;
3754         }
3755
3756         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3757                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3758
3759         for (i = 0; i < num_vfs; i++)
3760                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3761                                              (i * HWRM_MAX_REQ_LEN);
3762
3763         rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3764         if (rc)
3765                 rte_free(bp->pf->vf_req_buf);
3766
3767         return rc;
3768 }
3769
3770 static int
3771 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3772 {
3773         struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3774         struct hwrm_func_vf_resource_cfg_input req = {0};
3775         int i, rc = 0;
3776
3777         bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3778         bp->pf->active_vfs = 0;
3779         for (i = 0; i < num_vfs; i++) {
3780                 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3781                 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3782                 rc = bnxt_hwrm_send_message(bp,
3783                                             &req,
3784                                             sizeof(req),
3785                                             BNXT_USE_CHIMP_MB);
3786                 if (rc || resp->error_code) {
3787                         PMD_DRV_LOG(ERR,
3788                                 "Failed to initialize VF %d\n", i);
3789                         PMD_DRV_LOG(ERR,
3790                                 "Not all VFs available. (%d, %d)\n",
3791                                 rc, resp->error_code);
3792                         HWRM_UNLOCK();
3793
3794                         /* If the first VF configuration itself fails,
3795                          * unregister the vf_fwd_request buffer.
3796                          */
3797                         if (i == 0)
3798                                 bnxt_hwrm_func_buf_unrgtr(bp);
3799                         break;
3800                 }
3801                 HWRM_UNLOCK();
3802
3803                 /* Update the max resource values based on the resource values
3804                  * allocated to the VF.
3805                  */
3806                 bnxt_update_max_resources(bp, i);
3807                 bp->pf->active_vfs++;
3808                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3809         }
3810
3811         return 0;
3812 }
3813
3814 static int
3815 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3816 {
3817         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3818         struct hwrm_func_cfg_input req = {0};
3819         int i, rc;
3820
3821         bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3822
3823         bp->pf->active_vfs = 0;
3824         for (i = 0; i < num_vfs; i++) {
3825                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3826                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3827                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3828                 rc = bnxt_hwrm_send_message(bp,
3829                                             &req,
3830                                             sizeof(req),
3831                                             BNXT_USE_CHIMP_MB);
3832
3833                 /* Clear enable flag for next pass */
3834                 req.enables &= ~rte_cpu_to_le_32(
3835                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3836
3837                 if (rc || resp->error_code) {
3838                         PMD_DRV_LOG(ERR,
3839                                 "Failed to initialize VF %d\n", i);
3840                         PMD_DRV_LOG(ERR,
3841                                 "Not all VFs available. (%d, %d)\n",
3842                                 rc, resp->error_code);
3843                         HWRM_UNLOCK();
3844
3845                         /* If the first VF configuration itself fails,
3846                          * unregister the vf_fwd_request buffer.
3847                          */
3848                         if (i == 0)
3849                                 bnxt_hwrm_func_buf_unrgtr(bp);
3850                         break;
3851                 }
3852
3853                 HWRM_UNLOCK();
3854
3855                 /* Update the max resource values based on the resource values
3856                  * allocated to the VF.
3857                  */
3858                 bnxt_update_max_resources(bp, i);
3859                 bp->pf->active_vfs++;
3860                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3861         }
3862
3863         return 0;
3864 }
3865
3866 static void
3867 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3868 {
3869         if (bp->flags & BNXT_FLAG_NEW_RM)
3870                 bnxt_process_vf_resc_config_new(bp, num_vfs);
3871         else
3872                 bnxt_process_vf_resc_config_old(bp, num_vfs);
3873 }
3874
3875 static void
3876 bnxt_update_pf_resources(struct bnxt *bp,
3877                          struct bnxt_pf_resource_info *pf_resc)
3878 {
3879         bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3880         bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3881         bp->max_cp_rings = pf_resc->num_cp_rings;
3882         bp->max_tx_rings = pf_resc->num_tx_rings;
3883         bp->max_rx_rings = pf_resc->num_rx_rings;
3884         bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3885 }
3886
3887 static int32_t
3888 bnxt_configure_pf_resources(struct bnxt *bp,
3889                             struct bnxt_pf_resource_info *pf_resc)
3890 {
3891         /*
3892          * We're using STD_TX_RING_MODE here which will limit the TX
3893          * rings. This will allow QoS to function properly. Not setting this
3894          * will cause PF rings to break bandwidth settings.
3895          */
3896         bp->pf->func_cfg_flags &=
3897                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3898                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3899         bp->pf->func_cfg_flags |=
3900                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3901         return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3902 }
3903
3904 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3905 {
3906         struct bnxt_pf_resource_info pf_resc = { 0 };
3907         int rc;
3908
3909         if (!BNXT_PF(bp)) {
3910                 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3911                 return -EINVAL;
3912         }
3913
3914         rc = bnxt_hwrm_func_qcaps(bp);
3915         if (rc)
3916                 return rc;
3917
3918         bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3919
3920         rc = bnxt_configure_pf_resources(bp, &pf_resc);
3921         if (rc)
3922                 return rc;
3923
3924         rc = bnxt_query_pf_resources(bp, &pf_resc);
3925         if (rc)
3926                 return rc;
3927
3928         /*
3929          * Now, create and register a buffer to hold forwarded VF requests
3930          */
3931         rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3932         if (rc)
3933                 return rc;
3934
3935         bnxt_configure_vf_resources(bp, num_vfs);
3936
3937         bnxt_update_pf_resources(bp, &pf_resc);
3938
3939         return 0;
3940 }
3941
3942 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3943 {
3944         struct hwrm_func_cfg_input req = {0};
3945         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3946         int rc;
3947
3948         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3949
3950         req.fid = rte_cpu_to_le_16(0xffff);
3951         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3952         req.evb_mode = bp->pf->evb_mode;
3953
3954         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3955         HWRM_CHECK_RESULT();
3956         HWRM_UNLOCK();
3957
3958         return rc;
3959 }
3960
3961 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3962                                 uint8_t tunnel_type)
3963 {
3964         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3965         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3966         int rc = 0;
3967
3968         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3969         req.tunnel_type = tunnel_type;
3970         req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3971         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3972         HWRM_CHECK_RESULT();
3973
3974         switch (tunnel_type) {
3975         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3976                 bp->vxlan_fw_dst_port_id =
3977                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3978                 bp->vxlan_port = port;
3979                 break;
3980         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3981                 bp->geneve_fw_dst_port_id =
3982                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3983                 bp->geneve_port = port;
3984                 break;
3985         default:
3986                 break;
3987         }
3988
3989         HWRM_UNLOCK();
3990
3991         return rc;
3992 }
3993
3994 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3995                                 uint8_t tunnel_type)
3996 {
3997         struct hwrm_tunnel_dst_port_free_input req = {0};
3998         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3999         int rc = 0;
4000
4001         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
4002
4003         req.tunnel_type = tunnel_type;
4004         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
4005         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4006
4007         HWRM_CHECK_RESULT();
4008         HWRM_UNLOCK();
4009
4010         if (tunnel_type ==
4011             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4012                 bp->vxlan_port = 0;
4013                 bp->vxlan_port_cnt = 0;
4014         }
4015
4016         if (tunnel_type ==
4017             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4018                 bp->geneve_port = 0;
4019                 bp->geneve_port_cnt = 0;
4020         }
4021
4022         return rc;
4023 }
4024
4025 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4026                                         uint32_t flags)
4027 {
4028         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4029         struct hwrm_func_cfg_input req = {0};
4030         int rc;
4031
4032         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4033
4034         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4035         req.flags = rte_cpu_to_le_32(flags);
4036         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4037
4038         HWRM_CHECK_RESULT();
4039         HWRM_UNLOCK();
4040
4041         return rc;
4042 }
4043
4044 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4045 {
4046         uint32_t *flag = flagp;
4047
4048         vnic->flags = *flag;
4049 }
4050
4051 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4052 {
4053         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4054 }
4055
4056 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4057 {
4058         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4059         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4060         int rc;
4061
4062         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4063
4064         req.req_buf_num_pages = rte_cpu_to_le_16(1);
4065         req.req_buf_page_size =
4066                 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4067         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4068         req.req_buf_page_addr0 =
4069                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4070         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4071                 PMD_DRV_LOG(ERR,
4072                         "unable to map buffer address to physical memory\n");
4073                 HWRM_UNLOCK();
4074                 return -ENOMEM;
4075         }
4076
4077         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4078
4079         HWRM_CHECK_RESULT();
4080         HWRM_UNLOCK();
4081
4082         return rc;
4083 }
4084
4085 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4086 {
4087         int rc = 0;
4088         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4089         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4090
4091         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4092                 return 0;
4093
4094         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4095
4096         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4097
4098         HWRM_CHECK_RESULT();
4099         HWRM_UNLOCK();
4100
4101         return rc;
4102 }
4103
4104 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4105 {
4106         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4107         struct hwrm_func_cfg_input req = {0};
4108         int rc;
4109
4110         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4111
4112         req.fid = rte_cpu_to_le_16(0xffff);
4113         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4114         req.enables = rte_cpu_to_le_32(
4115                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4116         req.async_event_cr = rte_cpu_to_le_16(
4117                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4118         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4119
4120         HWRM_CHECK_RESULT();
4121         HWRM_UNLOCK();
4122
4123         return rc;
4124 }
4125
4126 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4127 {
4128         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4129         struct hwrm_func_vf_cfg_input req = {0};
4130         int rc;
4131
4132         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4133
4134         req.enables = rte_cpu_to_le_32(
4135                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4136         req.async_event_cr = rte_cpu_to_le_16(
4137                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4138         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4139
4140         HWRM_CHECK_RESULT();
4141         HWRM_UNLOCK();
4142
4143         return rc;
4144 }
4145
4146 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4147 {
4148         struct hwrm_func_cfg_input req = {0};
4149         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4150         uint16_t dflt_vlan, fid;
4151         uint32_t func_cfg_flags;
4152         int rc = 0;
4153
4154         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4155
4156         if (is_vf) {
4157                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4158                 fid = bp->pf->vf_info[vf].fid;
4159                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4160         } else {
4161                 fid = rte_cpu_to_le_16(0xffff);
4162                 func_cfg_flags = bp->pf->func_cfg_flags;
4163                 dflt_vlan = bp->vlan;
4164         }
4165
4166         req.flags = rte_cpu_to_le_32(func_cfg_flags);
4167         req.fid = rte_cpu_to_le_16(fid);
4168         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4169         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4170
4171         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4172
4173         HWRM_CHECK_RESULT();
4174         HWRM_UNLOCK();
4175
4176         return rc;
4177 }
4178
4179 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4180                         uint16_t max_bw, uint16_t enables)
4181 {
4182         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4183         struct hwrm_func_cfg_input req = {0};
4184         int rc;
4185
4186         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4187
4188         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4189         req.enables |= rte_cpu_to_le_32(enables);
4190         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4191         req.max_bw = rte_cpu_to_le_32(max_bw);
4192         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4193
4194         HWRM_CHECK_RESULT();
4195         HWRM_UNLOCK();
4196
4197         return rc;
4198 }
4199
4200 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4201 {
4202         struct hwrm_func_cfg_input req = {0};
4203         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4204         int rc = 0;
4205
4206         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4207
4208         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4209         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4210         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4211         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4212
4213         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4214
4215         HWRM_CHECK_RESULT();
4216         HWRM_UNLOCK();
4217
4218         return rc;
4219 }
4220
4221 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4222 {
4223         int rc;
4224
4225         if (BNXT_PF(bp))
4226                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4227         else
4228                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4229
4230         return rc;
4231 }
4232
4233 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4234                               void *encaped, size_t ec_size)
4235 {
4236         int rc = 0;
4237         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4238         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4239
4240         if (ec_size > sizeof(req.encap_request))
4241                 return -1;
4242
4243         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4244
4245         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4246         memcpy(req.encap_request, encaped, ec_size);
4247
4248         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4249
4250         HWRM_CHECK_RESULT();
4251         HWRM_UNLOCK();
4252
4253         return rc;
4254 }
4255
4256 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4257                                        struct rte_ether_addr *mac)
4258 {
4259         struct hwrm_func_qcfg_input req = {0};
4260         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4261         int rc;
4262
4263         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4264
4265         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4266         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4267
4268         HWRM_CHECK_RESULT();
4269
4270         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4271
4272         HWRM_UNLOCK();
4273
4274         return rc;
4275 }
4276
4277 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4278                             void *encaped, size_t ec_size)
4279 {
4280         int rc = 0;
4281         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4282         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4283
4284         if (ec_size > sizeof(req.encap_request))
4285                 return -1;
4286
4287         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4288
4289         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4290         memcpy(req.encap_request, encaped, ec_size);
4291
4292         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4293
4294         HWRM_CHECK_RESULT();
4295         HWRM_UNLOCK();
4296
4297         return rc;
4298 }
4299
4300 static void bnxt_update_prev_stat(uint64_t *cntr, uint64_t *prev_cntr)
4301 {
4302         /* One of the HW stat values that make up this counter was zero as
4303          * returned by HW in this iteration, so use the previous
4304          * iteration's counter value
4305          */
4306         if (*prev_cntr && *cntr == 0)
4307                 *cntr = *prev_cntr;
4308         else
4309                 *prev_cntr = *cntr;
4310 }
4311
4312 int bnxt_hwrm_ring_stats(struct bnxt *bp, uint32_t cid, int idx,
4313                          struct bnxt_ring_stats *ring_stats, bool rx)
4314 {
4315         int rc = 0;
4316         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4317         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4318
4319         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4320
4321         req.stat_ctx_id = rte_cpu_to_le_32(cid);
4322
4323         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4324
4325         HWRM_CHECK_RESULT();
4326
4327         if (rx) {
4328                 struct bnxt_ring_stats *prev_stats = &bp->prev_rx_ring_stats[idx];
4329
4330                 ring_stats->rx_ucast_pkts = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4331                 bnxt_update_prev_stat(&ring_stats->rx_ucast_pkts,
4332                                       &prev_stats->rx_ucast_pkts);
4333
4334                 ring_stats->rx_mcast_pkts = rte_le_to_cpu_64(resp->rx_mcast_pkts);
4335                 bnxt_update_prev_stat(&ring_stats->rx_mcast_pkts,
4336                                       &prev_stats->rx_mcast_pkts);
4337
4338                 ring_stats->rx_bcast_pkts = rte_le_to_cpu_64(resp->rx_bcast_pkts);
4339                 bnxt_update_prev_stat(&ring_stats->rx_bcast_pkts,
4340                                       &prev_stats->rx_bcast_pkts);
4341
4342                 ring_stats->rx_ucast_bytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4343                 bnxt_update_prev_stat(&ring_stats->rx_ucast_bytes,
4344                                       &prev_stats->rx_ucast_bytes);
4345
4346                 ring_stats->rx_mcast_bytes = rte_le_to_cpu_64(resp->rx_mcast_bytes);
4347                 bnxt_update_prev_stat(&ring_stats->rx_mcast_bytes,
4348                                       &prev_stats->rx_mcast_bytes);
4349
4350                 ring_stats->rx_bcast_bytes = rte_le_to_cpu_64(resp->rx_bcast_bytes);
4351                 bnxt_update_prev_stat(&ring_stats->rx_bcast_bytes,
4352                                       &prev_stats->rx_bcast_bytes);
4353
4354                 ring_stats->rx_discard_pkts = rte_le_to_cpu_64(resp->rx_discard_pkts);
4355                 bnxt_update_prev_stat(&ring_stats->rx_discard_pkts,
4356                                       &prev_stats->rx_discard_pkts);
4357
4358                 ring_stats->rx_error_pkts = rte_le_to_cpu_64(resp->rx_error_pkts);
4359                 bnxt_update_prev_stat(&ring_stats->rx_error_pkts,
4360                                       &prev_stats->rx_error_pkts);
4361
4362                 ring_stats->rx_agg_pkts = rte_le_to_cpu_64(resp->rx_agg_pkts);
4363                 bnxt_update_prev_stat(&ring_stats->rx_agg_pkts,
4364                                       &prev_stats->rx_agg_pkts);
4365
4366                 ring_stats->rx_agg_bytes = rte_le_to_cpu_64(resp->rx_agg_bytes);
4367                 bnxt_update_prev_stat(&ring_stats->rx_agg_bytes,
4368                                       &prev_stats->rx_agg_bytes);
4369
4370                 ring_stats->rx_agg_events = rte_le_to_cpu_64(resp->rx_agg_events);
4371                 bnxt_update_prev_stat(&ring_stats->rx_agg_events,
4372                                       &prev_stats->rx_agg_events);
4373
4374                 ring_stats->rx_agg_aborts = rte_le_to_cpu_64(resp->rx_agg_aborts);
4375                 bnxt_update_prev_stat(&ring_stats->rx_agg_aborts,
4376                                       &prev_stats->rx_agg_aborts);
4377         } else {
4378                 struct bnxt_ring_stats *prev_stats = &bp->prev_tx_ring_stats[idx];
4379
4380                 ring_stats->tx_ucast_pkts = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4381                 bnxt_update_prev_stat(&ring_stats->tx_ucast_pkts,
4382                                       &prev_stats->tx_ucast_pkts);
4383
4384                 ring_stats->tx_mcast_pkts = rte_le_to_cpu_64(resp->tx_mcast_pkts);
4385                 bnxt_update_prev_stat(&ring_stats->tx_mcast_pkts,
4386                                       &prev_stats->tx_mcast_pkts);
4387
4388                 ring_stats->tx_bcast_pkts = rte_le_to_cpu_64(resp->tx_bcast_pkts);
4389                 bnxt_update_prev_stat(&ring_stats->tx_bcast_pkts,
4390                                       &prev_stats->tx_bcast_pkts);
4391
4392                 ring_stats->tx_ucast_bytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4393                 bnxt_update_prev_stat(&ring_stats->tx_ucast_bytes,
4394                                       &prev_stats->tx_ucast_bytes);
4395
4396                 ring_stats->tx_mcast_bytes = rte_le_to_cpu_64(resp->tx_mcast_bytes);
4397                 bnxt_update_prev_stat(&ring_stats->tx_mcast_bytes,
4398                                       &prev_stats->tx_mcast_bytes);
4399
4400                 ring_stats->tx_bcast_bytes = rte_le_to_cpu_64(resp->tx_bcast_bytes);
4401                 bnxt_update_prev_stat(&ring_stats->tx_bcast_bytes,
4402                                       &prev_stats->tx_bcast_bytes);
4403
4404                 ring_stats->tx_discard_pkts = rte_le_to_cpu_64(resp->tx_discard_pkts);
4405                 bnxt_update_prev_stat(&ring_stats->tx_discard_pkts,
4406                                       &prev_stats->tx_discard_pkts);
4407         }
4408
4409         HWRM_UNLOCK();
4410
4411         return rc;
4412 }
4413
4414 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4415 {
4416         struct hwrm_port_qstats_input req = {0};
4417         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4418         struct bnxt_pf_info *pf = bp->pf;
4419         int rc;
4420
4421         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4422
4423         req.port_id = rte_cpu_to_le_16(pf->port_id);
4424         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4425         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4426         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4427
4428         HWRM_CHECK_RESULT();
4429         HWRM_UNLOCK();
4430
4431         return rc;
4432 }
4433
4434 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4435 {
4436         struct hwrm_port_clr_stats_input req = {0};
4437         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4438         struct bnxt_pf_info *pf = bp->pf;
4439         int rc;
4440
4441         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4442         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4443             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4444                 return 0;
4445
4446         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4447
4448         req.port_id = rte_cpu_to_le_16(pf->port_id);
4449         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4450
4451         HWRM_CHECK_RESULT();
4452         HWRM_UNLOCK();
4453
4454         return rc;
4455 }
4456
4457 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4458 {
4459         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4460         struct hwrm_port_led_qcaps_input req = {0};
4461         int rc;
4462
4463         if (BNXT_VF(bp))
4464                 return 0;
4465
4466         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4467         req.port_id = bp->pf->port_id;
4468         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4469
4470         HWRM_CHECK_RESULT_SILENT();
4471
4472         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4473                 unsigned int i;
4474
4475                 bp->leds->num_leds = resp->num_leds;
4476                 memcpy(bp->leds, &resp->led0_id,
4477                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4478                 for (i = 0; i < bp->leds->num_leds; i++) {
4479                         struct bnxt_led_info *led = &bp->leds[i];
4480
4481                         uint16_t caps = led->led_state_caps;
4482
4483                         if (!led->led_group_id ||
4484                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4485                                 bp->leds->num_leds = 0;
4486                                 break;
4487                         }
4488                 }
4489         }
4490
4491         HWRM_UNLOCK();
4492
4493         return rc;
4494 }
4495
4496 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4497 {
4498         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4499         struct hwrm_port_led_cfg_input req = {0};
4500         struct bnxt_led_cfg *led_cfg;
4501         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4502         uint16_t duration = 0;
4503         int rc, i;
4504
4505         if (!bp->leds->num_leds || BNXT_VF(bp))
4506                 return -EOPNOTSUPP;
4507
4508         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4509
4510         if (led_on) {
4511                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4512                 duration = rte_cpu_to_le_16(500);
4513         }
4514         req.port_id = bp->pf->port_id;
4515         req.num_leds = bp->leds->num_leds;
4516         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4517         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4518                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4519                 led_cfg->led_id = bp->leds[i].led_id;
4520                 led_cfg->led_state = led_state;
4521                 led_cfg->led_blink_on = duration;
4522                 led_cfg->led_blink_off = duration;
4523                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4524         }
4525
4526         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4527
4528         HWRM_CHECK_RESULT();
4529         HWRM_UNLOCK();
4530
4531         return rc;
4532 }
4533
4534 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4535                                uint32_t *length)
4536 {
4537         int rc;
4538         struct hwrm_nvm_get_dir_info_input req = {0};
4539         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4540
4541         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4542
4543         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4544
4545         HWRM_CHECK_RESULT();
4546
4547         *entries = rte_le_to_cpu_32(resp->entries);
4548         *length = rte_le_to_cpu_32(resp->entry_length);
4549
4550         HWRM_UNLOCK();
4551         return rc;
4552 }
4553
4554 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4555 {
4556         int rc;
4557         uint32_t dir_entries;
4558         uint32_t entry_length;
4559         uint8_t *buf;
4560         size_t buflen;
4561         rte_iova_t dma_handle;
4562         struct hwrm_nvm_get_dir_entries_input req = {0};
4563         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4564
4565         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4566         if (rc != 0)
4567                 return rc;
4568
4569         *data++ = dir_entries;
4570         *data++ = entry_length;
4571         len -= 2;
4572         memset(data, 0xff, len);
4573
4574         buflen = dir_entries * entry_length;
4575         buf = rte_malloc("nvm_dir", buflen, 0);
4576         if (buf == NULL)
4577                 return -ENOMEM;
4578         dma_handle = rte_malloc_virt2iova(buf);
4579         if (dma_handle == RTE_BAD_IOVA) {
4580                 rte_free(buf);
4581                 PMD_DRV_LOG(ERR,
4582                         "unable to map response address to physical memory\n");
4583                 return -ENOMEM;
4584         }
4585         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4586         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4587         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4588
4589         if (rc == 0)
4590                 memcpy(data, buf, len > buflen ? buflen : len);
4591
4592         rte_free(buf);
4593         HWRM_CHECK_RESULT();
4594         HWRM_UNLOCK();
4595
4596         return rc;
4597 }
4598
4599 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4600                              uint32_t offset, uint32_t length,
4601                              uint8_t *data)
4602 {
4603         int rc;
4604         uint8_t *buf;
4605         rte_iova_t dma_handle;
4606         struct hwrm_nvm_read_input req = {0};
4607         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4608
4609         buf = rte_malloc("nvm_item", length, 0);
4610         if (!buf)
4611                 return -ENOMEM;
4612
4613         dma_handle = rte_malloc_virt2iova(buf);
4614         if (dma_handle == RTE_BAD_IOVA) {
4615                 rte_free(buf);
4616                 PMD_DRV_LOG(ERR,
4617                         "unable to map response address to physical memory\n");
4618                 return -ENOMEM;
4619         }
4620         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4621         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4622         req.dir_idx = rte_cpu_to_le_16(index);
4623         req.offset = rte_cpu_to_le_32(offset);
4624         req.len = rte_cpu_to_le_32(length);
4625         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4626         if (rc == 0)
4627                 memcpy(data, buf, length);
4628
4629         rte_free(buf);
4630         HWRM_CHECK_RESULT();
4631         HWRM_UNLOCK();
4632
4633         return rc;
4634 }
4635
4636 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4637 {
4638         int rc;
4639         struct hwrm_nvm_erase_dir_entry_input req = {0};
4640         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4641
4642         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4643         req.dir_idx = rte_cpu_to_le_16(index);
4644         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4645         HWRM_CHECK_RESULT();
4646         HWRM_UNLOCK();
4647
4648         return rc;
4649 }
4650
4651 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4652                           uint16_t dir_ordinal, uint16_t dir_ext,
4653                           uint16_t dir_attr, const uint8_t *data,
4654                           size_t data_len)
4655 {
4656         int rc;
4657         struct hwrm_nvm_write_input req = {0};
4658         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4659         rte_iova_t dma_handle;
4660         uint8_t *buf;
4661
4662         buf = rte_malloc("nvm_write", data_len, 0);
4663         if (!buf)
4664                 return -ENOMEM;
4665
4666         dma_handle = rte_malloc_virt2iova(buf);
4667         if (dma_handle == RTE_BAD_IOVA) {
4668                 rte_free(buf);
4669                 PMD_DRV_LOG(ERR,
4670                         "unable to map response address to physical memory\n");
4671                 return -ENOMEM;
4672         }
4673         memcpy(buf, data, data_len);
4674
4675         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4676
4677         req.dir_type = rte_cpu_to_le_16(dir_type);
4678         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4679         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4680         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4681         req.dir_data_length = rte_cpu_to_le_32(data_len);
4682         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4683
4684         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4685
4686         rte_free(buf);
4687         HWRM_CHECK_RESULT();
4688         HWRM_UNLOCK();
4689
4690         return rc;
4691 }
4692
4693 static void
4694 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4695 {
4696         uint32_t *count = cbdata;
4697
4698         *count = *count + 1;
4699 }
4700
4701 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4702                                      struct bnxt_vnic_info *vnic __rte_unused)
4703 {
4704         return 0;
4705 }
4706
4707 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4708 {
4709         uint32_t count = 0;
4710
4711         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4712             &count, bnxt_vnic_count_hwrm_stub);
4713
4714         return count;
4715 }
4716
4717 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4718                                         uint16_t *vnic_ids)
4719 {
4720         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4721         struct hwrm_func_vf_vnic_ids_query_output *resp =
4722                                                 bp->hwrm_cmd_resp_addr;
4723         int rc;
4724
4725         /* First query all VNIC ids */
4726         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4727
4728         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4729         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4730         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4731
4732         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4733                 HWRM_UNLOCK();
4734                 PMD_DRV_LOG(ERR,
4735                 "unable to map VNIC ID table address to physical memory\n");
4736                 return -ENOMEM;
4737         }
4738         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4739         HWRM_CHECK_RESULT();
4740         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4741
4742         HWRM_UNLOCK();
4743
4744         return rc;
4745 }
4746
4747 /*
4748  * This function queries the VNIC IDs  for a specified VF. It then calls
4749  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4750  * Then it calls the hwrm_cb function to program this new vnic configuration.
4751  */
4752 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4753         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4754         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4755 {
4756         struct bnxt_vnic_info vnic;
4757         int rc = 0;
4758         int i, num_vnic_ids;
4759         uint16_t *vnic_ids;
4760         size_t vnic_id_sz;
4761         size_t sz;
4762
4763         /* First query all VNIC ids */
4764         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4765         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4766                         RTE_CACHE_LINE_SIZE);
4767         if (vnic_ids == NULL)
4768                 return -ENOMEM;
4769
4770         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4771                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4772
4773         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4774
4775         if (num_vnic_ids < 0)
4776                 return num_vnic_ids;
4777
4778         /* Retrieve VNIC, update bd_stall then update */
4779
4780         for (i = 0; i < num_vnic_ids; i++) {
4781                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4782                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4783                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4784                 if (rc)
4785                         break;
4786                 if (vnic.mru <= 4)      /* Indicates unallocated */
4787                         continue;
4788
4789                 vnic_cb(&vnic, cbdata);
4790
4791                 rc = hwrm_cb(bp, &vnic);
4792                 if (rc)
4793                         break;
4794         }
4795
4796         rte_free(vnic_ids);
4797
4798         return rc;
4799 }
4800
4801 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4802                                               bool on)
4803 {
4804         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4805         struct hwrm_func_cfg_input req = {0};
4806         int rc;
4807
4808         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4809
4810         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4811         req.enables |= rte_cpu_to_le_32(
4812                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4813         req.vlan_antispoof_mode = on ?
4814                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4815                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4816         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4817
4818         HWRM_CHECK_RESULT();
4819         HWRM_UNLOCK();
4820
4821         return rc;
4822 }
4823
4824 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4825 {
4826         struct bnxt_vnic_info vnic;
4827         uint16_t *vnic_ids;
4828         size_t vnic_id_sz;
4829         int num_vnic_ids, i;
4830         size_t sz;
4831         int rc;
4832
4833         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4834         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4835                         RTE_CACHE_LINE_SIZE);
4836         if (vnic_ids == NULL)
4837                 return -ENOMEM;
4838
4839         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4840                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4841
4842         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4843         if (rc <= 0)
4844                 goto exit;
4845         num_vnic_ids = rc;
4846
4847         /*
4848          * Loop through to find the default VNIC ID.
4849          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4850          * by sending the hwrm_func_qcfg command to the firmware.
4851          */
4852         for (i = 0; i < num_vnic_ids; i++) {
4853                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4854                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4855                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4856                                         bp->pf->first_vf_id + vf);
4857                 if (rc)
4858                         goto exit;
4859                 if (vnic.func_default) {
4860                         rte_free(vnic_ids);
4861                         return vnic.fw_vnic_id;
4862                 }
4863         }
4864         /* Could not find a default VNIC. */
4865         PMD_DRV_LOG(ERR, "No default VNIC\n");
4866 exit:
4867         rte_free(vnic_ids);
4868         return rc;
4869 }
4870
4871 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4872                          uint16_t dst_id,
4873                          struct bnxt_filter_info *filter)
4874 {
4875         int rc = 0;
4876         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4877         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4878         uint32_t enables = 0;
4879
4880         if (filter->fw_em_filter_id != UINT64_MAX)
4881                 bnxt_hwrm_clear_em_filter(bp, filter);
4882
4883         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4884
4885         req.flags = rte_cpu_to_le_32(filter->flags);
4886
4887         enables = filter->enables |
4888               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4889         req.dst_id = rte_cpu_to_le_16(dst_id);
4890
4891         if (filter->ip_addr_type) {
4892                 req.ip_addr_type = filter->ip_addr_type;
4893                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4894         }
4895         if (enables &
4896             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4897                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4898         if (enables &
4899             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4900                 memcpy(req.src_macaddr, filter->src_macaddr,
4901                        RTE_ETHER_ADDR_LEN);
4902         if (enables &
4903             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4904                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4905                        RTE_ETHER_ADDR_LEN);
4906         if (enables &
4907             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4908                 req.ovlan_vid = filter->l2_ovlan;
4909         if (enables &
4910             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4911                 req.ivlan_vid = filter->l2_ivlan;
4912         if (enables &
4913             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4914                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4915         if (enables &
4916             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4917                 req.ip_protocol = filter->ip_protocol;
4918         if (enables &
4919             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4920                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4921         if (enables &
4922             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4923                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4924         if (enables &
4925             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4926                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4927         if (enables &
4928             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4929                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4930         if (enables &
4931             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4932                 req.mirror_vnic_id = filter->mirror_vnic_id;
4933
4934         req.enables = rte_cpu_to_le_32(enables);
4935
4936         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4937
4938         HWRM_CHECK_RESULT();
4939
4940         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4941         HWRM_UNLOCK();
4942
4943         return rc;
4944 }
4945
4946 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4947 {
4948         int rc = 0;
4949         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4950         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4951
4952         if (filter->fw_em_filter_id == UINT64_MAX)
4953                 return 0;
4954
4955         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4956
4957         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4958
4959         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4960
4961         HWRM_CHECK_RESULT();
4962         HWRM_UNLOCK();
4963
4964         filter->fw_em_filter_id = UINT64_MAX;
4965         filter->fw_l2_filter_id = UINT64_MAX;
4966
4967         return 0;
4968 }
4969
4970 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4971                          uint16_t dst_id,
4972                          struct bnxt_filter_info *filter)
4973 {
4974         int rc = 0;
4975         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4976         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4977                                                 bp->hwrm_cmd_resp_addr;
4978         uint32_t enables = 0;
4979
4980         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4981                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4982
4983         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4984
4985         req.flags = rte_cpu_to_le_32(filter->flags);
4986
4987         enables = filter->enables |
4988               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4989         req.dst_id = rte_cpu_to_le_16(dst_id);
4990
4991         if (filter->ip_addr_type) {
4992                 req.ip_addr_type = filter->ip_addr_type;
4993                 enables |=
4994                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4995         }
4996         if (enables &
4997             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4998                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4999         if (enables &
5000             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
5001                 memcpy(req.src_macaddr, filter->src_macaddr,
5002                        RTE_ETHER_ADDR_LEN);
5003         if (enables &
5004             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
5005                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
5006         if (enables &
5007             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
5008                 req.ip_protocol = filter->ip_protocol;
5009         if (enables &
5010             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
5011                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
5012         if (enables &
5013             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
5014                 req.src_ipaddr_mask[0] =
5015                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
5016         if (enables &
5017             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
5018                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
5019         if (enables &
5020             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
5021                 req.dst_ipaddr_mask[0] =
5022                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
5023         if (enables &
5024             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
5025                 req.src_port = rte_cpu_to_le_16(filter->src_port);
5026         if (enables &
5027             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
5028                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
5029         if (enables &
5030             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
5031                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
5032         if (enables &
5033             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
5034                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
5035         if (enables &
5036             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
5037                 req.mirror_vnic_id = filter->mirror_vnic_id;
5038
5039         req.enables = rte_cpu_to_le_32(enables);
5040
5041         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5042
5043         HWRM_CHECK_RESULT();
5044
5045         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
5046         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
5047         HWRM_UNLOCK();
5048
5049         return rc;
5050 }
5051
5052 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
5053                                 struct bnxt_filter_info *filter)
5054 {
5055         int rc = 0;
5056         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
5057         struct hwrm_cfa_ntuple_filter_free_output *resp =
5058                                                 bp->hwrm_cmd_resp_addr;
5059
5060         if (filter->fw_ntuple_filter_id == UINT64_MAX)
5061                 return 0;
5062
5063         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
5064
5065         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
5066
5067         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5068
5069         HWRM_CHECK_RESULT();
5070         HWRM_UNLOCK();
5071
5072         filter->fw_ntuple_filter_id = UINT64_MAX;
5073
5074         return 0;
5075 }
5076
5077 static int
5078 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5079 {
5080         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5081         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
5082         struct bnxt_rx_queue **rxqs = bp->rx_queues;
5083         uint16_t *ring_tbl = vnic->rss_table;
5084         int nr_ctxs = vnic->num_lb_ctxts;
5085         int max_rings = bp->rx_nr_rings;
5086         int i, j, k, cnt;
5087         int rc = 0;
5088
5089         for (i = 0, k = 0; i < nr_ctxs; i++) {
5090                 struct bnxt_rx_ring_info *rxr;
5091                 struct bnxt_cp_ring_info *cpr;
5092
5093                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5094
5095                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5096                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5097                 req.hash_mode_flags = vnic->hash_mode;
5098
5099                 req.ring_grp_tbl_addr =
5100                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5101                                      i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5102                                      2 * sizeof(*ring_tbl));
5103                 req.hash_key_tbl_addr =
5104                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5105
5106                 req.ring_table_pair_index = i;
5107                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5108
5109                 for (j = 0; j < 64; j++) {
5110                         uint16_t ring_id;
5111
5112                         /* Find next active ring. */
5113                         for (cnt = 0; cnt < max_rings; cnt++) {
5114                                 if (rxqs[k]->rx_started)
5115                                         break;
5116                                 if (++k == max_rings)
5117                                         k = 0;
5118                         }
5119
5120                         /* Return if no rings are active. */
5121                         if (cnt == max_rings) {
5122                                 HWRM_UNLOCK();
5123                                 return 0;
5124                         }
5125
5126                         /* Add rx/cp ring pair to RSS table. */
5127                         rxr = rxqs[k]->rx_ring;
5128                         cpr = rxqs[k]->cp_ring;
5129
5130                         ring_id = rxr->rx_ring_struct->fw_ring_id;
5131                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5132                         ring_id = cpr->cp_ring_struct->fw_ring_id;
5133                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5134
5135                         if (++k == max_rings)
5136                                 k = 0;
5137                 }
5138                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5139                                             BNXT_USE_CHIMP_MB);
5140
5141                 HWRM_CHECK_RESULT();
5142                 HWRM_UNLOCK();
5143         }
5144
5145         return rc;
5146 }
5147
5148 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5149 {
5150         unsigned int rss_idx, fw_idx, i;
5151
5152         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5153                 return 0;
5154
5155         if (!(vnic->rss_table && vnic->hash_type))
5156                 return 0;
5157
5158         if (BNXT_CHIP_P5(bp))
5159                 return bnxt_vnic_rss_configure_p5(bp, vnic);
5160
5161         /*
5162          * Fill the RSS hash & redirection table with
5163          * ring group ids for all VNICs
5164          */
5165         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5166              rss_idx++, fw_idx++) {
5167                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5168                         fw_idx %= bp->rx_cp_nr_rings;
5169                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5170                                 break;
5171                         fw_idx++;
5172                 }
5173
5174                 if (i == bp->rx_cp_nr_rings)
5175                         return 0;
5176
5177                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5178         }
5179
5180         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5181 }
5182
5183 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5184         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5185 {
5186         uint16_t flags;
5187
5188         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5189
5190         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5191         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5192
5193         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5194         req->num_cmpl_dma_aggr_during_int =
5195                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5196
5197         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5198
5199         /* min timer set to 1/2 of interrupt timer */
5200         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5201
5202         /* buf timer set to 1/4 of interrupt timer */
5203         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5204
5205         req->cmpl_aggr_dma_tmr_during_int =
5206                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5207
5208         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5209                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5210         req->flags = rte_cpu_to_le_16(flags);
5211 }
5212
5213 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5214                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5215 {
5216         struct hwrm_ring_aggint_qcaps_input req = {0};
5217         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5218         uint32_t enables;
5219         uint16_t flags;
5220         int rc;
5221
5222         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5223         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5224         HWRM_CHECK_RESULT();
5225
5226         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5227         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5228
5229         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5230                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5231         agg_req->flags = rte_cpu_to_le_16(flags);
5232         enables =
5233          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5234          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5235         agg_req->enables = rte_cpu_to_le_32(enables);
5236
5237         HWRM_UNLOCK();
5238         return rc;
5239 }
5240
5241 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5242                         struct bnxt_coal *coal, uint16_t ring_id)
5243 {
5244         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5245         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5246                                                 bp->hwrm_cmd_resp_addr;
5247         int rc;
5248
5249         /* Set ring coalesce parameters only for 100G NICs */
5250         if (BNXT_CHIP_P5(bp)) {
5251                 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5252                         return -1;
5253         } else if (bnxt_stratus_device(bp)) {
5254                 bnxt_hwrm_set_coal_params(coal, &req);
5255         } else {
5256                 return 0;
5257         }
5258
5259         HWRM_PREP(&req,
5260                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5261                   BNXT_USE_CHIMP_MB);
5262         req.ring_id = rte_cpu_to_le_16(ring_id);
5263         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5264         HWRM_CHECK_RESULT();
5265         HWRM_UNLOCK();
5266         return 0;
5267 }
5268
5269 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5270 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5271 {
5272         struct hwrm_func_backing_store_qcaps_input req = {0};
5273         struct hwrm_func_backing_store_qcaps_output *resp =
5274                 bp->hwrm_cmd_resp_addr;
5275         struct bnxt_ctx_pg_info *ctx_pg;
5276         struct bnxt_ctx_mem_info *ctx;
5277         int total_alloc_len;
5278         int rc, i, tqm_rings;
5279
5280         if (!BNXT_CHIP_P5(bp) ||
5281             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5282             BNXT_VF(bp) ||
5283             bp->ctx)
5284                 return 0;
5285
5286         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5287         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5288         HWRM_CHECK_RESULT_SILENT();
5289
5290         total_alloc_len = sizeof(*ctx);
5291         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5292                           RTE_CACHE_LINE_SIZE);
5293         if (!ctx) {
5294                 rc = -ENOMEM;
5295                 goto ctx_err;
5296         }
5297
5298         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5299         ctx->qp_min_qp1_entries =
5300                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5301         ctx->qp_max_l2_entries =
5302                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5303         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5304         ctx->srq_max_l2_entries =
5305                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5306         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5307         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5308         ctx->cq_max_l2_entries =
5309                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5310         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5311         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5312         ctx->vnic_max_vnic_entries =
5313                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5314         ctx->vnic_max_ring_table_entries =
5315                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5316         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5317         ctx->stat_max_entries =
5318                 rte_le_to_cpu_32(resp->stat_max_entries);
5319         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5320         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5321         ctx->tqm_min_entries_per_ring =
5322                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5323         ctx->tqm_max_entries_per_ring =
5324                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5325         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5326         if (!ctx->tqm_entries_multiple)
5327                 ctx->tqm_entries_multiple = 1;
5328         ctx->mrav_max_entries =
5329                 rte_le_to_cpu_32(resp->mrav_max_entries);
5330         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5331         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5332         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5333         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5334
5335         ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5336                                   RTE_MIN(ctx->tqm_fp_rings_count,
5337                                           BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5338                                   bp->max_q;
5339
5340         /* Check if the ext ring count needs to be counted.
5341          * Ext ring count is available only with new FW so we should not
5342          * look at the field on older FW.
5343          */
5344         if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5345             bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5346                 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5347                 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5348                                                   ctx->tqm_fp_rings_count);
5349         }
5350
5351         tqm_rings = ctx->tqm_fp_rings_count + 1;
5352
5353         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5354                             sizeof(*ctx_pg) * tqm_rings,
5355                             RTE_CACHE_LINE_SIZE);
5356         if (!ctx_pg) {
5357                 rc = -ENOMEM;
5358                 goto ctx_err;
5359         }
5360         for (i = 0; i < tqm_rings; i++, ctx_pg++)
5361                 ctx->tqm_mem[i] = ctx_pg;
5362
5363         bp->ctx = ctx;
5364 ctx_err:
5365         HWRM_UNLOCK();
5366         return rc;
5367 }
5368
5369 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5370 {
5371         struct hwrm_func_backing_store_cfg_input req = {0};
5372         struct hwrm_func_backing_store_cfg_output *resp =
5373                 bp->hwrm_cmd_resp_addr;
5374         struct bnxt_ctx_mem_info *ctx = bp->ctx;
5375         struct bnxt_ctx_pg_info *ctx_pg;
5376         uint32_t *num_entries;
5377         uint64_t *pg_dir;
5378         uint8_t *pg_attr;
5379         uint32_t ena;
5380         int i, rc;
5381
5382         if (!ctx)
5383                 return 0;
5384
5385         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5386         req.enables = rte_cpu_to_le_32(enables);
5387
5388         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5389                 ctx_pg = &ctx->qp_mem;
5390                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5391                 req.qp_num_qp1_entries =
5392                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5393                 req.qp_num_l2_entries =
5394                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5395                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5396                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5397                                       &req.qpc_pg_size_qpc_lvl,
5398                                       &req.qpc_page_dir);
5399         }
5400
5401         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5402                 ctx_pg = &ctx->srq_mem;
5403                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5404                 req.srq_num_l2_entries =
5405                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5406                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5407                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5408                                       &req.srq_pg_size_srq_lvl,
5409                                       &req.srq_page_dir);
5410         }
5411
5412         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5413                 ctx_pg = &ctx->cq_mem;
5414                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5415                 req.cq_num_l2_entries =
5416                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5417                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5418                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5419                                       &req.cq_pg_size_cq_lvl,
5420                                       &req.cq_page_dir);
5421         }
5422
5423         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5424                 ctx_pg = &ctx->vnic_mem;
5425                 req.vnic_num_vnic_entries =
5426                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5427                 req.vnic_num_ring_table_entries =
5428                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5429                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5430                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5431                                       &req.vnic_pg_size_vnic_lvl,
5432                                       &req.vnic_page_dir);
5433         }
5434
5435         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5436                 ctx_pg = &ctx->stat_mem;
5437                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5438                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5439                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5440                                       &req.stat_pg_size_stat_lvl,
5441                                       &req.stat_page_dir);
5442         }
5443
5444         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5445         num_entries = &req.tqm_sp_num_entries;
5446         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5447         pg_dir = &req.tqm_sp_page_dir;
5448         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5449         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5450                 if (!(enables & ena))
5451                         continue;
5452
5453                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5454
5455                 ctx_pg = ctx->tqm_mem[i];
5456                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5457                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5458         }
5459
5460         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5461                 /* DPDK does not need to configure MRAV and TIM type.
5462                  * So we are skipping over MRAV and TIM. Skip to configure
5463                  * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5464                  */
5465                 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5466                 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5467                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5468                                       &req.tqm_ring8_pg_size_tqm_ring_lvl,
5469                                       &req.tqm_ring8_page_dir);
5470         }
5471
5472         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5473         HWRM_CHECK_RESULT();
5474         HWRM_UNLOCK();
5475
5476         return rc;
5477 }
5478
5479 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5480 {
5481         struct hwrm_port_qstats_ext_input req = {0};
5482         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5483         struct bnxt_pf_info *pf = bp->pf;
5484         int rc;
5485
5486         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5487               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5488                 return 0;
5489
5490         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5491
5492         req.port_id = rte_cpu_to_le_16(pf->port_id);
5493         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5494                 req.tx_stat_host_addr =
5495                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5496                 req.tx_stat_size =
5497                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5498         }
5499         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5500                 req.rx_stat_host_addr =
5501                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5502                 req.rx_stat_size =
5503                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5504         }
5505         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5506
5507         if (rc) {
5508                 bp->fw_rx_port_stats_ext_size = 0;
5509                 bp->fw_tx_port_stats_ext_size = 0;
5510         } else {
5511                 bp->fw_rx_port_stats_ext_size =
5512                         rte_le_to_cpu_16(resp->rx_stat_size);
5513                 bp->fw_tx_port_stats_ext_size =
5514                         rte_le_to_cpu_16(resp->tx_stat_size);
5515         }
5516
5517         HWRM_CHECK_RESULT();
5518         HWRM_UNLOCK();
5519
5520         return rc;
5521 }
5522
5523 int
5524 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5525 {
5526         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5527         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5528                 bp->hwrm_cmd_resp_addr;
5529         int rc = 0;
5530
5531         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5532         req.tunnel_type = type;
5533         req.dest_fid = bp->fw_fid;
5534         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5535         HWRM_CHECK_RESULT();
5536
5537         HWRM_UNLOCK();
5538
5539         return rc;
5540 }
5541
5542 int
5543 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5544 {
5545         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5546         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5547                 bp->hwrm_cmd_resp_addr;
5548         int rc = 0;
5549
5550         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5551         req.tunnel_type = type;
5552         req.dest_fid = bp->fw_fid;
5553         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5554         HWRM_CHECK_RESULT();
5555
5556         HWRM_UNLOCK();
5557
5558         return rc;
5559 }
5560
5561 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5562 {
5563         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5564         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5565                 bp->hwrm_cmd_resp_addr;
5566         int rc = 0;
5567
5568         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5569         req.src_fid = bp->fw_fid;
5570         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5571         HWRM_CHECK_RESULT();
5572
5573         if (type)
5574                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5575
5576         HWRM_UNLOCK();
5577
5578         return rc;
5579 }
5580
5581 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5582                                    uint16_t *dst_fid)
5583 {
5584         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5585         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5586                 bp->hwrm_cmd_resp_addr;
5587         int rc = 0;
5588
5589         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5590         req.src_fid = bp->fw_fid;
5591         req.tunnel_type = tun_type;
5592         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5593         HWRM_CHECK_RESULT();
5594
5595         if (dst_fid)
5596                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5597
5598         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5599
5600         HWRM_UNLOCK();
5601
5602         return rc;
5603 }
5604
5605 int bnxt_hwrm_set_mac(struct bnxt *bp)
5606 {
5607         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5608         struct hwrm_func_vf_cfg_input req = {0};
5609         int rc = 0;
5610
5611         if (!BNXT_VF(bp))
5612                 return 0;
5613
5614         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5615
5616         req.enables =
5617                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5618         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5619
5620         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5621
5622         HWRM_CHECK_RESULT();
5623
5624         HWRM_UNLOCK();
5625
5626         return rc;
5627 }
5628
5629 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5630 {
5631         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5632         struct hwrm_func_drv_if_change_input req = {0};
5633         uint32_t flags;
5634         int rc;
5635
5636         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5637                 return 0;
5638
5639         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5640          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5641          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5642          */
5643         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5644                 return 0;
5645
5646         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5647
5648         if (up)
5649                 req.flags =
5650                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5651
5652         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5653
5654         HWRM_CHECK_RESULT();
5655         flags = rte_le_to_cpu_32(resp->flags);
5656         HWRM_UNLOCK();
5657
5658         if (!up)
5659                 return 0;
5660
5661         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5662                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5663                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5664         }
5665
5666         return 0;
5667 }
5668
5669 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5670 {
5671         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5672         struct bnxt_error_recovery_info *info = bp->recovery_info;
5673         struct hwrm_error_recovery_qcfg_input req = {0};
5674         uint32_t flags = 0;
5675         unsigned int i;
5676         int rc;
5677
5678         /* Older FW does not have error recovery support */
5679         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5680                 return 0;
5681
5682         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5683
5684         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5685
5686         HWRM_CHECK_RESULT();
5687
5688         flags = rte_le_to_cpu_32(resp->flags);
5689         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5690                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5691         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5692                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5693
5694         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5695             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5696                 rc = -EINVAL;
5697                 goto err;
5698         }
5699
5700         /* FW returned values are in units of 100msec */
5701         info->driver_polling_freq =
5702                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5703         info->master_func_wait_period =
5704                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5705         info->normal_func_wait_period =
5706                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5707         info->master_func_wait_period_after_reset =
5708                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5709         info->max_bailout_time_after_reset =
5710                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5711         info->status_regs[BNXT_FW_STATUS_REG] =
5712                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5713         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5714                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5715         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5716                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5717         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5718                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5719         info->reg_array_cnt =
5720                 rte_le_to_cpu_32(resp->reg_array_cnt);
5721
5722         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5723                 rc = -EINVAL;
5724                 goto err;
5725         }
5726
5727         for (i = 0; i < info->reg_array_cnt; i++) {
5728                 info->reset_reg[i] =
5729                         rte_le_to_cpu_32(resp->reset_reg[i]);
5730                 info->reset_reg_val[i] =
5731                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5732                 info->delay_after_reset[i] =
5733                         resp->delay_after_reset[i];
5734         }
5735 err:
5736         HWRM_UNLOCK();
5737
5738         /* Map the FW status registers */
5739         if (!rc)
5740                 rc = bnxt_map_fw_health_status_regs(bp);
5741
5742         if (rc) {
5743                 rte_free(bp->recovery_info);
5744                 bp->recovery_info = NULL;
5745         }
5746         return rc;
5747 }
5748
5749 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5750 {
5751         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5752         struct hwrm_fw_reset_input req = {0};
5753         int rc;
5754
5755         if (!BNXT_PF(bp))
5756                 return -EOPNOTSUPP;
5757
5758         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5759
5760         req.embedded_proc_type =
5761                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5762         req.selfrst_status =
5763                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5764         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5765
5766         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5767                                     BNXT_USE_KONG(bp));
5768
5769         HWRM_CHECK_RESULT();
5770         HWRM_UNLOCK();
5771
5772         return rc;
5773 }
5774
5775 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5776 {
5777         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5778         struct hwrm_port_ts_query_input req = {0};
5779         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5780         uint32_t flags = 0;
5781         int rc;
5782
5783         if (!ptp)
5784                 return 0;
5785
5786         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5787
5788         switch (path) {
5789         case BNXT_PTP_FLAGS_PATH_TX:
5790                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5791                 break;
5792         case BNXT_PTP_FLAGS_PATH_RX:
5793                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5794                 break;
5795         case BNXT_PTP_FLAGS_CURRENT_TIME:
5796                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5797                 break;
5798         }
5799
5800         req.flags = rte_cpu_to_le_32(flags);
5801         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5802
5803         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5804
5805         HWRM_CHECK_RESULT();
5806
5807         if (timestamp) {
5808                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5809                 *timestamp |=
5810                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5811         }
5812         HWRM_UNLOCK();
5813
5814         return rc;
5815 }
5816
5817 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5818 {
5819         int rc = 0;
5820
5821         struct hwrm_cfa_counter_qcaps_input req = {0};
5822         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5823
5824         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5825                 PMD_DRV_LOG(DEBUG,
5826                             "Not a PF or trusted VF. Command not supported\n");
5827                 return 0;
5828         }
5829
5830         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5831         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5832         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5833
5834         HWRM_CHECK_RESULT();
5835         if (max_fc)
5836                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5837         HWRM_UNLOCK();
5838
5839         return 0;
5840 }
5841
5842 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5843 {
5844         int rc = 0;
5845         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5846         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5847
5848         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5849                 PMD_DRV_LOG(DEBUG,
5850                             "Not a PF or trusted VF. Command not supported\n");
5851                 return 0;
5852         }
5853
5854         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5855
5856         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5857         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5858         req.page_dir = rte_cpu_to_le_64(dma_addr);
5859
5860         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5861
5862         HWRM_CHECK_RESULT();
5863         if (ctx_id) {
5864                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5865                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5866         }
5867         HWRM_UNLOCK();
5868
5869         return 0;
5870 }
5871
5872 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5873 {
5874         int rc = 0;
5875         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5876         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5877
5878         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5879                 PMD_DRV_LOG(DEBUG,
5880                             "Not a PF or trusted VF. Command not supported\n");
5881                 return 0;
5882         }
5883
5884         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5885
5886         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5887
5888         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5889
5890         HWRM_CHECK_RESULT();
5891         HWRM_UNLOCK();
5892
5893         return rc;
5894 }
5895
5896 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5897                               uint16_t cntr, uint16_t ctx_id,
5898                               uint32_t num_entries, bool enable)
5899 {
5900         struct hwrm_cfa_counter_cfg_input req = {0};
5901         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5902         uint16_t flags = 0;
5903         int rc;
5904
5905         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5906                 PMD_DRV_LOG(DEBUG,
5907                             "Not a PF or trusted VF. Command not supported\n");
5908                 return 0;
5909         }
5910
5911         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5912
5913         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5914         req.counter_type = rte_cpu_to_le_16(cntr);
5915         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5916                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5917         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5918         if (dir == BNXT_DIR_RX)
5919                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5920         else if (dir == BNXT_DIR_TX)
5921                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5922         req.flags = rte_cpu_to_le_16(flags);
5923         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5924         req.num_entries = rte_cpu_to_le_32(num_entries);
5925
5926         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5927         HWRM_CHECK_RESULT();
5928         HWRM_UNLOCK();
5929
5930         return 0;
5931 }
5932
5933 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5934                                  enum bnxt_flow_dir dir,
5935                                  uint16_t cntr,
5936                                  uint16_t num_entries)
5937 {
5938         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5939         struct hwrm_cfa_counter_qstats_input req = {0};
5940         uint16_t flow_ctx_id = 0;
5941         uint16_t flags = 0;
5942         int rc = 0;
5943
5944         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5945                 PMD_DRV_LOG(DEBUG,
5946                             "Not a PF or trusted VF. Command not supported\n");
5947                 return 0;
5948         }
5949
5950         if (dir == BNXT_DIR_RX) {
5951                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5952                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5953         } else if (dir == BNXT_DIR_TX) {
5954                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5955                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5956         }
5957
5958         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5959         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5960         req.counter_type = rte_cpu_to_le_16(cntr);
5961         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5962         req.num_entries = rte_cpu_to_le_16(num_entries);
5963         req.flags = rte_cpu_to_le_16(flags);
5964         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5965
5966         HWRM_CHECK_RESULT();
5967         HWRM_UNLOCK();
5968
5969         return 0;
5970 }
5971
5972 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5973                                 uint16_t *first_vf_id)
5974 {
5975         int rc = 0;
5976         struct hwrm_func_qcaps_input req = {.req_type = 0 };
5977         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5978
5979         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5980
5981         req.fid = rte_cpu_to_le_16(fid);
5982
5983         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5984
5985         HWRM_CHECK_RESULT();
5986
5987         if (first_vf_id)
5988                 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
5989
5990         HWRM_UNLOCK();
5991
5992         return rc;
5993 }
5994
5995 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
5996 {
5997         struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5998         struct hwrm_cfa_pair_alloc_input req = {0};
5999         int rc;
6000
6001         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6002                 PMD_DRV_LOG(DEBUG,
6003                             "Not a PF or trusted VF. Command not supported\n");
6004                 return 0;
6005         }
6006
6007         HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
6008         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6009         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6010                  bp->eth_dev->data->name, rep_bp->vf_id);
6011
6012         req.pf_b_id = rep_bp->parent_pf_idx;
6013         req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6014                                                 rte_cpu_to_le_16(rep_bp->vf_id);
6015         req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
6016         req.host_b_id = 1; /* TBD - Confirm if this is OK */
6017
6018         req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
6019                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
6020         req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
6021                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
6022         req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
6023                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
6024         req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
6025                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
6026
6027         req.q_ab = rep_bp->rep_q_r2f;
6028         req.q_ba = rep_bp->rep_q_f2r;
6029         req.fc_ab = rep_bp->rep_fc_r2f;
6030         req.fc_ba = rep_bp->rep_fc_f2r;
6031
6032         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6033         HWRM_CHECK_RESULT();
6034
6035         HWRM_UNLOCK();
6036         PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
6037                     BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
6038         return rc;
6039 }
6040
6041 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
6042 {
6043         struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
6044         struct hwrm_cfa_pair_free_input req = {0};
6045         int rc;
6046
6047         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6048                 PMD_DRV_LOG(DEBUG,
6049                             "Not a PF or trusted VF. Command not supported\n");
6050                 return 0;
6051         }
6052
6053         HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
6054         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6055                  bp->eth_dev->data->name, rep_bp->vf_id);
6056         req.pf_b_id = rep_bp->parent_pf_idx;
6057         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6058         req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6059                                                 rte_cpu_to_le_16(rep_bp->vf_id);
6060         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6061         HWRM_CHECK_RESULT();
6062         HWRM_UNLOCK();
6063         PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
6064                     rep_bp->vf_id);
6065         return rc;
6066 }
6067
6068 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
6069 {
6070         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
6071                                         bp->hwrm_cmd_resp_addr;
6072         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
6073         uint32_t flags = 0;
6074         int rc = 0;
6075
6076         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
6077                 return 0;
6078
6079         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6080                 PMD_DRV_LOG(DEBUG,
6081                             "Not a PF or trusted VF. Command not supported\n");
6082                 return 0;
6083         }
6084
6085         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
6086         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6087
6088         HWRM_CHECK_RESULT();
6089         flags = rte_le_to_cpu_32(resp->flags);
6090         HWRM_UNLOCK();
6091
6092         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
6093                 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
6094         else
6095                 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
6096
6097         return rc;
6098 }
6099
6100 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6101                             uint32_t echo_req_data2)
6102 {
6103         struct hwrm_func_echo_response_input req = {0};
6104         struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6105         int rc;
6106
6107         HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6108         req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6109         req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6110
6111         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6112
6113         HWRM_CHECK_RESULT();
6114         HWRM_UNLOCK();
6115
6116         return rc;
6117 }
6118
6119 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6120 {
6121         struct hwrm_ver_get_input req = {.req_type = 0 };
6122         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6123         int rc = 0;
6124
6125         bp->max_req_len = HWRM_MAX_REQ_LEN;
6126         bp->max_resp_len = BNXT_PAGE_SIZE;
6127         bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6128
6129         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6130         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6131         req.hwrm_intf_min = HWRM_VERSION_MINOR;
6132         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6133
6134         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6135
6136         HWRM_CHECK_RESULT_SILENT();
6137
6138         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)
6139                 rc = -EAGAIN;
6140
6141         HWRM_UNLOCK();
6142
6143         return rc;
6144 }
6145
6146 int bnxt_hwrm_read_sfp_module_eeprom_info(struct bnxt *bp, uint16_t i2c_addr,
6147                                           uint16_t page_number, uint16_t start_addr,
6148                                           uint16_t data_length, uint8_t *buf)
6149 {
6150         struct hwrm_port_phy_i2c_read_output *resp = bp->hwrm_cmd_resp_addr;
6151         struct hwrm_port_phy_i2c_read_input req = {0};
6152         uint32_t enables = HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET;
6153         int rc, byte_offset = 0;
6154
6155         do {
6156                 uint16_t xfer_size;
6157
6158                 HWRM_PREP(&req, HWRM_PORT_PHY_I2C_READ, BNXT_USE_CHIMP_MB);
6159                 req.i2c_slave_addr = i2c_addr;
6160                 req.page_number = rte_cpu_to_le_16(page_number);
6161                 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
6162
6163                 xfer_size = RTE_MIN(data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
6164                 req.page_offset = rte_cpu_to_le_16(start_addr + byte_offset);
6165                 req.data_length = xfer_size;
6166                 req.enables = rte_cpu_to_le_32(start_addr + byte_offset ? enables : 0);
6167                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6168                 HWRM_CHECK_RESULT();
6169
6170                 memcpy(buf + byte_offset, resp->data, xfer_size);
6171
6172                 data_length -= xfer_size;
6173                 byte_offset += xfer_size;
6174
6175                 HWRM_UNLOCK();
6176         } while (data_length > 0);
6177
6178         return rc;
6179 }
6180
6181 void bnxt_free_hwrm_tx_ring(struct bnxt *bp, int queue_index)
6182 {
6183         struct bnxt_tx_queue *txq = bp->tx_queues[queue_index];
6184         struct bnxt_tx_ring_info *txr = txq->tx_ring;
6185         struct bnxt_ring *ring = txr->tx_ring_struct;
6186         struct bnxt_cp_ring_info *cpr = txq->cp_ring;
6187
6188         bnxt_hwrm_ring_free(bp, ring,
6189                             HWRM_RING_FREE_INPUT_RING_TYPE_TX,
6190                             cpr->cp_ring_struct->fw_ring_id);
6191         txr->tx_raw_prod = 0;
6192         txr->tx_raw_cons = 0;
6193         memset(txr->tx_desc_ring, 0,
6194                 txr->tx_ring_struct->ring_size * sizeof(*txr->tx_desc_ring));
6195         memset(txr->tx_buf_ring, 0,
6196                 txr->tx_ring_struct->ring_size * sizeof(*txr->tx_buf_ring));
6197
6198         bnxt_hwrm_stat_ctx_free(bp, cpr);
6199
6200         bnxt_free_cp_ring(bp, cpr);
6201 }
6202
6203 int bnxt_hwrm_config_host_mtu(struct bnxt *bp)
6204 {
6205         struct hwrm_func_cfg_input req = {0};
6206         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
6207         int rc;
6208
6209         if (!BNXT_PF(bp))
6210                 return 0;
6211
6212         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
6213
6214         req.fid = rte_cpu_to_le_16(0xffff);
6215         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU);
6216         req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
6217
6218         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6219         HWRM_CHECK_RESULT();
6220         HWRM_UNLOCK();
6221
6222         return rc;
6223 }