drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         timeout = bp->hwrm_cmd_timeout;
 104
 105         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 106             msg_len > bp->max_req_len) {
 107                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 108
 109                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 110                 memcpy(short_cmd_req, req, msg_len);
 111
 112                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 113                 short_input.signature = rte_cpu_to_le_16(
 114                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 115                 short_input.size = rte_cpu_to_le_16(msg_len);
 116                 short_input.req_addr =
 117                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 118
 119                 data = (uint32_t *)&short_input;
 120                 msg_len = sizeof(short_input);
 121
 122                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 123         }
 124
 125         /* Write request msg to hwrm channel */
 126         for (i = 0; i < msg_len; i += 4) {
 127                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 128                 rte_write32(*data, bar);
 129                 data++;
 130         }
 131
 132         /* Zero the rest of the request space */
 133         for (; i < max_req_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 135                 rte_write32(0, bar);
 136         }
 137
 138         /* Ring channel doorbell */
 139         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 140         rte_write32(1, bar);
 141         /*
 142          * Make sure the channel doorbell ring command complete before
 143          * reading the response to avoid getting stale or invalid
 144          * responses.
 145          */
 146         rte_io_mb();
 147
 148         /* Poll for the valid bit */
 149         for (i = 0; i < timeout; i++) {
 150                 /* Sanity check on the resp->resp_len */
 151                 rte_cio_rmb();
 152                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 153                         /* Last byte of resp contains the valid key */
 154                         valid = (uint8_t *)resp + resp->resp_len - 1;
 155                         if (*valid == HWRM_RESP_VALID_KEY)
 156                                 break;
 157                 }
 158                 rte_delay_us(1);
 159         }
 160
 161         if (i >= timeout) {
 162                 /* Suppress VER_GET timeout messages during reset recovery */
 163                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 164                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 165                         return -ETIMEDOUT;
 166
 167                 PMD_DRV_LOG(ERR,
 168                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 169                             req->req_type, req->seq_id);
 170                 return -ETIMEDOUT;
 171         }
 172         return 0;
 173 }
 174
 175 /*
 176  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 177  * spinlock, and does initial processing.
 178  *
 179  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 180  * releases the spinlock only if it returns. If the regular int return codes
 181  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 182  * directly, rather it should be copied and modified to suit the function.
 183  *
 184  * HWRM_UNLOCK() must be called after all response processing is completed.
 185  */
 186 #define HWRM_PREP(req, type, kong) do { \
 187         rte_spinlock_lock(&bp->hwrm_lock); \
 188         if (bp->hwrm_cmd_resp_addr == NULL) { \
 189                 rte_spinlock_unlock(&bp->hwrm_lock); \
 190                 return -EACCES; \
 191         } \
 192         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 193         (req)->req_type = rte_cpu_to_le_16(type); \
 194         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 195         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 196                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 197         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 198         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 199 } while (0)
 200
 201 #define HWRM_CHECK_RESULT_SILENT() do {\
 202         if (rc) { \
 203                 rte_spinlock_unlock(&bp->hwrm_lock); \
 204                 return rc; \
 205         } \
 206         if (resp->error_code) { \
 207                 rc = rte_le_to_cpu_16(resp->error_code); \
 208                 rte_spinlock_unlock(&bp->hwrm_lock); \
 209                 return rc; \
 210         } \
 211 } while (0)
 212
 213 #define HWRM_CHECK_RESULT() do {\
 214         if (rc) { \
 215                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 216                 rte_spinlock_unlock(&bp->hwrm_lock); \
 217                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 218                         rc = -EACCES; \
 219                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 220                         rc = -ENOSPC; \
 221                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 222                         rc = -EINVAL; \
 223                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 224                         rc = -ENOTSUP; \
 225                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 226                         rc = -EAGAIN; \
 227                 else if (rc > 0) \
 228                         rc = -EIO; \
 229                 return rc; \
 230         } \
 231         if (resp->error_code) { \
 232                 rc = rte_le_to_cpu_16(resp->error_code); \
 233                 if (resp->resp_len >= 16) { \
 234                         struct hwrm_err_output *tmp_hwrm_err_op = \
 235                                                 (void *)resp; \
 236                         PMD_DRV_LOG(ERR, \
 237                                 "error %d:%d:%08x:%04x\n", \
 238                                 rc, tmp_hwrm_err_op->cmd_err, \
 239                                 rte_le_to_cpu_32(\
 240                                         tmp_hwrm_err_op->opaque_0), \
 241                                 rte_le_to_cpu_16(\
 242                                         tmp_hwrm_err_op->opaque_1)); \
 243                 } else { \
 244                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 245                 } \
 246                 rte_spinlock_unlock(&bp->hwrm_lock); \
 247                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 248                         rc = -EACCES; \
 249                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 250                         rc = -ENOSPC; \
 251                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 252                         rc = -EINVAL; \
 253                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 254                         rc = -ENOTSUP; \
 255                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 256                         rc = -EAGAIN; \
 257                 else if (rc > 0) \
 258                         rc = -EIO; \
 259                 return rc; \
 260         } \
 261 } while (0)
 262
 263 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 264
 265 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 266                                 bool use_kong_mb,
 267                                 uint16_t msg_type,
 268                                 void *msg,
 269                                 uint32_t msg_len,
 270                                 void *resp_msg,
 271                                 uint32_t resp_len)
 272 {
 273         int rc = 0;
 274         bool mailbox = BNXT_USE_CHIMP_MB;
 275         struct input *req = msg;
 276         struct output *resp = bp->hwrm_cmd_resp_addr;
 277
 278         if (use_kong_mb)
 279                 mailbox = BNXT_USE_KONG(bp);
 280
 281         HWRM_PREP(req, msg_type, mailbox);
 282
 283         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 284
 285         HWRM_CHECK_RESULT();
 286
 287         if (resp_msg)
 288                 memcpy(resp_msg, resp, resp_len);
 289
 290         HWRM_UNLOCK();
 291
 292         return rc;
 293 }
 294
 295 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 296                                   bool use_kong_mb,
 297                                   uint16_t tf_type,
 298                                   uint16_t tf_subtype,
 299                                   uint32_t *tf_response_code,
 300                                   void *msg,
 301                                   uint32_t msg_len,
 302                                   void *response,
 303                                   uint32_t response_len)
 304 {
 305         int rc = 0;
 306         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 307         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 308         bool mailbox = BNXT_USE_CHIMP_MB;
 309
 310         if (msg_len > sizeof(req.tf_req))
 311                 return -ENOMEM;
 312
 313         if (use_kong_mb)
 314                 mailbox = BNXT_USE_KONG(bp);
 315
 316         HWRM_PREP(&req, HWRM_TF, mailbox);
 317         /* Build request using the user supplied request payload.
 318          * TLV request size is checked at build time against HWRM
 319          * request max size, thus no checking required.
 320          */
 321         req.tf_type = tf_type;
 322         req.tf_subtype = tf_subtype;
 323         memcpy(req.tf_req, msg, msg_len);
 324
 325         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 326         HWRM_CHECK_RESULT();
 327
 328         /* Copy the resp to user provided response buffer */
 329         if (response != NULL)
 330                 /* Post process response data. We need to copy only
 331                  * the 'payload' as the HWRM data structure really is
 332                  * HWRM header + msg header + payload and the TFLIB
 333                  * only provided a payload place holder.
 334                  */
 335                 if (response_len != 0) {
 336                         memcpy(response,
 337                                resp->tf_resp,
 338                                response_len);
 339                 }
 340
 341         /* Extract the internal tflib response code */
 342         *tf_response_code = resp->tf_resp_code;
 343         HWRM_UNLOCK();
 344
 345         return rc;
 346 }
 347
 348 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 349 {
 350         int rc = 0;
 351         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 352         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 353
 354         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 355         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 356         req.mask = 0;
 357
 358         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 359
 360         HWRM_CHECK_RESULT();
 361         HWRM_UNLOCK();
 362
 363         return rc;
 364 }
 365
 366 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 367                                  struct bnxt_vnic_info *vnic,
 368                                  uint16_t vlan_count,
 369                                  struct bnxt_vlan_table_entry *vlan_table)
 370 {
 371         int rc = 0;
 372         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 373         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 374         uint32_t mask = 0;
 375
 376         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 377                 return rc;
 378
 379         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 380         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 381
 382         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 383                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 384         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 385                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 386
 387         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 388                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 389
 390         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 391                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 392         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 393                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 394                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 395                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 396         }
 397         if (vlan_table) {
 398                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 399                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 400                 req.vlan_tag_tbl_addr =
 401                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 402                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 403         }
 404         req.mask = rte_cpu_to_le_32(mask);
 405
 406         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 407
 408         HWRM_CHECK_RESULT();
 409         HWRM_UNLOCK();
 410
 411         return rc;
 412 }
 413
 414 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 415                         uint16_t vlan_count,
 416                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 417 {
 418         int rc = 0;
 419         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 420         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 421                                                 bp->hwrm_cmd_resp_addr;
 422
 423         /*
 424          * Older HWRM versions did not support this command, and the set_rx_mask
 425          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 426          * removed from set_rx_mask call, and this command was added.
 427          *
 428          * This command is also present from 1.7.8.11 and higher,
 429          * as well as 1.7.8.0
 430          */
 431         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 432                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 433                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 434                                         (11)))
 435                                 return 0;
 436                 }
 437         }
 438         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 439         req.fid = rte_cpu_to_le_16(fid);
 440
 441         req.vlan_tag_mask_tbl_addr =
 442                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 443         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 444
 445         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 446
 447         HWRM_CHECK_RESULT();
 448         HWRM_UNLOCK();
 449
 450         return rc;
 451 }
 452
 453 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 454                              struct bnxt_filter_info *filter)
 455 {
 456         int rc = 0;
 457         struct bnxt_filter_info *l2_filter = filter;
 458         struct bnxt_vnic_info *vnic = NULL;
 459         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 460         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 461
 462         if (filter->fw_l2_filter_id == UINT64_MAX)
 463                 return 0;
 464
 465         if (filter->matching_l2_fltr_ptr)
 466                 l2_filter = filter->matching_l2_fltr_ptr;
 467
 468         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 469                     filter, l2_filter, l2_filter->l2_ref_cnt);
 470
 471         if (l2_filter->l2_ref_cnt == 0)
 472                 return 0;
 473
 474         if (l2_filter->l2_ref_cnt > 0)
 475                 l2_filter->l2_ref_cnt--;
 476
 477         if (l2_filter->l2_ref_cnt > 0)
 478                 return 0;
 479
 480         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 481
 482         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 483
 484         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 485
 486         HWRM_CHECK_RESULT();
 487         HWRM_UNLOCK();
 488
 489         filter->fw_l2_filter_id = UINT64_MAX;
 490         if (l2_filter->l2_ref_cnt == 0) {
 491                 vnic = l2_filter->vnic;
 492                 if (vnic) {
 493                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 494                                       bnxt_filter_info, next);
 495                         bnxt_free_filter(bp, l2_filter);
 496                 }
 497         }
 498
 499         return 0;
 500 }
 501
 502 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 503                          uint16_t dst_id,
 504                          struct bnxt_filter_info *filter)
 505 {
 506         int rc = 0;
 507         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 508         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 509         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 510         const struct rte_eth_vmdq_rx_conf *conf =
 511                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 512         uint32_t enables = 0;
 513         uint16_t j = dst_id - 1;
 514
 515         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 516         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 517             conf->pool_map[j].pools & (1UL << j)) {
 518                 PMD_DRV_LOG(DEBUG,
 519                         "Add vlan %u to vmdq pool %u\n",
 520                         conf->pool_map[j].vlan_id, j);
 521
 522                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 523                 filter->enables |=
 524                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 525                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 526         }
 527
 528         if (filter->fw_l2_filter_id != UINT64_MAX)
 529                 bnxt_hwrm_clear_l2_filter(bp, filter);
 530
 531         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 532
 533         req.flags = rte_cpu_to_le_32(filter->flags);
 534
 535         enables = filter->enables |
 536               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 537         req.dst_id = rte_cpu_to_le_16(dst_id);
 538
 539         if (enables &
 540             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 541                 memcpy(req.l2_addr, filter->l2_addr,
 542                        RTE_ETHER_ADDR_LEN);
 543         if (enables &
 544             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 545                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 546                        RTE_ETHER_ADDR_LEN);
 547         if (enables &
 548             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 549                 req.l2_ovlan = filter->l2_ovlan;
 550         if (enables &
 551             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 552                 req.l2_ivlan = filter->l2_ivlan;
 553         if (enables &
 554             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 555                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 556         if (enables &
 557             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 558                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 559         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 560                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 561         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 562                 req.src_type = filter->src_type;
 563         if (filter->pri_hint) {
 564                 req.pri_hint = filter->pri_hint;
 565                 req.l2_filter_id_hint =
 566                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 567         }
 568
 569         req.enables = rte_cpu_to_le_32(enables);
 570
 571         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 572
 573         HWRM_CHECK_RESULT();
 574
 575         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 576         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 577         HWRM_UNLOCK();
 578
 579         filter->l2_ref_cnt++;
 580
 581         return rc;
 582 }
 583
 584 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 585 {
 586         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 587         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 588         uint32_t flags = 0;
 589         int rc;
 590
 591         if (!ptp)
 592                 return 0;
 593
 594         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 595
 596         if (ptp->rx_filter)
 597                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 598         else
 599                 flags |=
 600                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 601         if (ptp->tx_tstamp_en)
 602                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 603         else
 604                 flags |=
 605                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 606         req.flags = rte_cpu_to_le_32(flags);
 607         req.enables = rte_cpu_to_le_32
 608                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 609         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 610
 611         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 612         HWRM_UNLOCK();
 613
 614         return rc;
 615 }
 616
 617 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 618 {
 619         int rc = 0;
 620         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 621         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 622         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 623
 624         if (ptp)
 625                 return 0;
 626
 627         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 628
 629         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 630
 631         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 632
 633         HWRM_CHECK_RESULT();
 634
 635         if (!BNXT_CHIP_THOR(bp) &&
 636             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 637                 return 0;
 638
 639         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 640                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 641
 642         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 643         if (!ptp)
 644                 return -ENOMEM;
 645
 646         if (!BNXT_CHIP_THOR(bp)) {
 647                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 648                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 649                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 650                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 651                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 652                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 653                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 654                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 655                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 656                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 657                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 658                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 659                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 660                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 661                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 662                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 663                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 664                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 665         }
 666
 667         ptp->bp = bp;
 668         bp->ptp_cfg = ptp;
 669
 670         return 0;
 671 }
 672
 673 void bnxt_hwrm_free_vf_info(struct bnxt *bp)
 674 {
 675         int i;
 676
 677         for (i = 0; i < bp->pf->max_vfs; i++) {
 678                 rte_free(bp->pf->vf_info[i].vlan_table);
 679                 bp->pf->vf_info[i].vlan_table = NULL;
 680                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 681                 bp->pf->vf_info[i].vlan_as_table = NULL;
 682         }
 683         rte_free(bp->pf->vf_info);
 684         bp->pf->vf_info = NULL;
 685 }
 686
 687 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 688 {
 689         int rc = 0;
 690         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 691         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 692         uint16_t new_max_vfs;
 693         uint32_t flags;
 694         int i;
 695
 696         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 697
 698         req.fid = rte_cpu_to_le_16(0xffff);
 699
 700         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 701
 702         HWRM_CHECK_RESULT();
 703
 704         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 705         flags = rte_le_to_cpu_32(resp->flags);
 706         if (BNXT_PF(bp)) {
 707                 bp->pf->port_id = resp->port_id;
 708                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 709                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 710                 new_max_vfs = bp->pdev->max_vfs;
 711                 if (new_max_vfs != bp->pf->max_vfs) {
 712                         if (bp->pf->vf_info)
 713                                 bnxt_hwrm_free_vf_info(bp);
 714                         bp->pf->vf_info = rte_zmalloc("bnxt_vf_info",
 715                             sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
 716                         if (bp->pf->vf_info == NULL) {
 717                                 PMD_DRV_LOG(ERR, "Alloc vf info fail\n");
 718                                 return -ENOMEM;
 719                         }
 720                         bp->pf->max_vfs = new_max_vfs;
 721                         for (i = 0; i < new_max_vfs; i++) {
 722                                 bp->pf->vf_info[i].fid =
 723                                         bp->pf->first_vf_id + i;
 724                                 bp->pf->vf_info[i].vlan_table =
 725                                         rte_zmalloc("VF VLAN table",
 726                                                     getpagesize(),
 727                                                     getpagesize());
 728                                 if (bp->pf->vf_info[i].vlan_table == NULL)
 729                                         PMD_DRV_LOG(ERR,
 730                                         "Fail to alloc VLAN table for VF %d\n",
 731                                         i);
 732                                 else
 733                                         rte_mem_lock_page(
 734                                                 bp->pf->vf_info[i].vlan_table);
 735                                 bp->pf->vf_info[i].vlan_as_table =
 736                                         rte_zmalloc("VF VLAN AS table",
 737                                                     getpagesize(),
 738                                                     getpagesize());
 739                                 if (bp->pf->vf_info[i].vlan_as_table == NULL)
 740                                         PMD_DRV_LOG(ERR,
 741                                         "Alloc VLAN AS table for VF %d fail\n",
 742                                         i);
 743                                 else
 744                                         rte_mem_lock_page(
 745                                               bp->pf->vf_info[i].vlan_as_table);
 746                                 STAILQ_INIT(&bp->pf->vf_info[i].filter);
 747                         }
 748                 }
 749         }
 750
 751         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 752         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 753                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 754                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 755         } else {
 756                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 757         }
 758         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 759         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 760         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 761         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 762         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 763         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 764         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 765         if (!BNXT_CHIP_THOR(bp))
 766                 bp->max_l2_ctx += bp->max_rx_em_flows;
 767         /* TODO: For now, do not support VMDq/RFS on VFs. */
 768         if (BNXT_PF(bp)) {
 769                 if (bp->pf->max_vfs)
 770                         bp->max_vnics = 1;
 771                 else
 772                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 773         } else {
 774                 bp->max_vnics = 1;
 775         }
 776         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 777                     bp->max_l2_ctx, bp->max_vnics);
 778         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 779         if (BNXT_PF(bp)) {
 780                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 781                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 782                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 783                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 784                         HWRM_UNLOCK();
 785                         bnxt_hwrm_ptp_qcfg(bp);
 786                 }
 787         }
 788
 789         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 790                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 791
 792         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 793                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 794                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 795         }
 796
 797         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 798                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 799
 800         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 801                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 802
 803         HWRM_UNLOCK();
 804
 805         return rc;
 806 }
 807
 808 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 809 {
 810         int rc;
 811
 812         rc = __bnxt_hwrm_func_qcaps(bp);
 813         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 814                 rc = bnxt_alloc_ctx_mem(bp);
 815                 if (rc)
 816                         return rc;
 817
 818                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 819                 if (!rc)
 820                         bp->flags |= BNXT_FLAG_NEW_RM;
 821         }
 822
 823         /* On older FW,
 824          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 825          * But the error can be ignored. Return success.
 826          */
 827
 828         return 0;
 829 }
 830
 831 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 832 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 833 {
 834         int rc = 0;
 835         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 836         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 837
 838         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 839
 840         req.target_id = rte_cpu_to_le_16(0xffff);
 841
 842         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 843
 844         HWRM_CHECK_RESULT();
 845
 846         if (rte_le_to_cpu_32(resp->flags) &
 847             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 848                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 849                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 850         }
 851
 852         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 853
 854         HWRM_UNLOCK();
 855
 856         return rc;
 857 }
 858
 859 int bnxt_hwrm_func_reset(struct bnxt *bp)
 860 {
 861         int rc = 0;
 862         struct hwrm_func_reset_input req = {.req_type = 0 };
 863         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 864
 865         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
 866
 867         req.enables = rte_cpu_to_le_32(0);
 868
 869         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 870
 871         HWRM_CHECK_RESULT();
 872         HWRM_UNLOCK();
 873
 874         return rc;
 875 }
 876
 877 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 878 {
 879         int rc;
 880         uint32_t flags = 0;
 881         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 882         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 883
 884         if (bp->flags & BNXT_FLAG_REGISTERED)
 885                 return 0;
 886
 887         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 888                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 889         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 890                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 891
 892         /* PFs and trusted VFs should indicate the support of the
 893          * Master capability on non Stingray platform
 894          */
 895         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 896                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 897
 898         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 899         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 900                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 901         req.ver_maj = RTE_VER_YEAR;
 902         req.ver_min = RTE_VER_MONTH;
 903         req.ver_upd = RTE_VER_MINOR;
 904
 905         if (BNXT_PF(bp)) {
 906                 req.enables |= rte_cpu_to_le_32(
 907                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 908                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
 909                        RTE_MIN(sizeof(req.vf_req_fwd),
 910                                sizeof(bp->pf->vf_req_fwd)));
 911
 912                 /*
 913                  * PF can sniff HWRM API issued by VF. This can be set up by
 914                  * linux driver and inherited by the DPDK PF driver. Clear
 915                  * this HWRM sniffer list in FW because DPDK PF driver does
 916                  * not support this.
 917                  */
 918                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 919         }
 920
 921         req.flags = rte_cpu_to_le_32(flags);
 922
 923         req.async_event_fwd[0] |=
 924                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 925                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 926                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 927                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 928                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 929         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 930                 req.async_event_fwd[0] |=
 931                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 932         req.async_event_fwd[1] |=
 933                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 934                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 935         if (BNXT_PF(bp))
 936                 req.async_event_fwd[1] |=
 937                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
 938
 939         if (BNXT_VF_IS_TRUSTED(bp))
 940                 req.async_event_fwd[1] |=
 941                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
 942
 943         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 944
 945         HWRM_CHECK_RESULT();
 946
 947         flags = rte_le_to_cpu_32(resp->flags);
 948         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 949                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 950
 951         HWRM_UNLOCK();
 952
 953         bp->flags |= BNXT_FLAG_REGISTERED;
 954
 955         return rc;
 956 }
 957
 958 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 959 {
 960         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 961                 return 0;
 962
 963         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 964 }
 965
 966 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 967 {
 968         int rc;
 969         uint32_t flags = 0;
 970         uint32_t enables;
 971         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 972         struct hwrm_func_vf_cfg_input req = {0};
 973
 974         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 975
 976         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 977                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 978                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 979                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 980                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 981
 982         if (BNXT_HAS_RING_GRPS(bp)) {
 983                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 984                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 985         }
 986
 987         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 988         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 989                                             AGG_RING_MULTIPLIER);
 990         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 991         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 992                                               bp->tx_nr_rings +
 993                                               BNXT_NUM_ASYNC_CPR(bp));
 994         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 995         if (bp->vf_resv_strategy ==
 996             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 997                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 998                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 999                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1000                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1001                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1002                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1003         } else if (bp->vf_resv_strategy ==
1004                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1005                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1006                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1007         }
1008
1009         if (test)
1010                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1011                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1012                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1013                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1014                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1015                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1016
1017         if (test && BNXT_HAS_RING_GRPS(bp))
1018                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1019
1020         req.flags = rte_cpu_to_le_32(flags);
1021         req.enables |= rte_cpu_to_le_32(enables);
1022
1023         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1024
1025         if (test)
1026                 HWRM_CHECK_RESULT_SILENT();
1027         else
1028                 HWRM_CHECK_RESULT();
1029
1030         HWRM_UNLOCK();
1031         return rc;
1032 }
1033
1034 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1035 {
1036         int rc;
1037         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1038         struct hwrm_func_resource_qcaps_input req = {0};
1039
1040         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1041         req.fid = rte_cpu_to_le_16(0xffff);
1042
1043         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1044
1045         HWRM_CHECK_RESULT_SILENT();
1046
1047         if (BNXT_VF(bp)) {
1048                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1049                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1050                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1051                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1052                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1053                 /* func_resource_qcaps does not return max_rx_em_flows.
1054                  * So use the value provided by func_qcaps.
1055                  */
1056                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1057                 if (!BNXT_CHIP_THOR(bp))
1058                         bp->max_l2_ctx += bp->max_rx_em_flows;
1059                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1060                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1061         }
1062         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1063         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1064         if (bp->vf_resv_strategy >
1065             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1066                 bp->vf_resv_strategy =
1067                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1068
1069         HWRM_UNLOCK();
1070         return rc;
1071 }
1072
1073 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1074 {
1075         int rc = 0;
1076         struct hwrm_ver_get_input req = {.req_type = 0 };
1077         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1078         uint32_t fw_version;
1079         uint16_t max_resp_len;
1080         char type[RTE_MEMZONE_NAMESIZE];
1081         uint32_t dev_caps_cfg;
1082
1083         bp->max_req_len = HWRM_MAX_REQ_LEN;
1084         bp->hwrm_cmd_timeout = timeout;
1085         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1086
1087         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1088         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1089         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1090
1091         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1092
1093         if (bp->flags & BNXT_FLAG_FW_RESET)
1094                 HWRM_CHECK_RESULT_SILENT();
1095         else
1096                 HWRM_CHECK_RESULT();
1097
1098         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1099                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1100                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1101                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1102         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1103                      (resp->hwrm_fw_min_8b << 16) |
1104                      (resp->hwrm_fw_bld_8b << 8) |
1105                      resp->hwrm_fw_rsvd_8b;
1106         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1107                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1108
1109         fw_version = resp->hwrm_intf_maj_8b << 16;
1110         fw_version |= resp->hwrm_intf_min_8b << 8;
1111         fw_version |= resp->hwrm_intf_upd_8b;
1112         bp->hwrm_spec_code = fw_version;
1113
1114         /* def_req_timeout value is in milliseconds */
1115         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1116         /* convert timeout to usec */
1117         bp->hwrm_cmd_timeout *= 1000;
1118         if (!bp->hwrm_cmd_timeout)
1119                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1120
1121         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1122                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1123                 rc = -EINVAL;
1124                 goto error;
1125         }
1126
1127         if (bp->max_req_len > resp->max_req_win_len) {
1128                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1129                 rc = -EINVAL;
1130         }
1131         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1132         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1133         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1134                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1135
1136         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1137         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1138
1139         if (bp->max_resp_len != max_resp_len) {
1140                 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1141                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1142                         bp->pdev->addr.devid, bp->pdev->addr.function);
1143
1144                 rte_free(bp->hwrm_cmd_resp_addr);
1145
1146                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1147                 if (bp->hwrm_cmd_resp_addr == NULL) {
1148                         rc = -ENOMEM;
1149                         goto error;
1150                 }
1151                 bp->hwrm_cmd_resp_dma_addr =
1152                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1153                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1154                         PMD_DRV_LOG(ERR,
1155                         "Unable to map response buffer to physical memory.\n");
1156                         rc = -ENOMEM;
1157                         goto error;
1158                 }
1159                 bp->max_resp_len = max_resp_len;
1160         }
1161
1162         if ((dev_caps_cfg &
1163                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1164             (dev_caps_cfg &
1165              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1166                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1167                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1168         }
1169
1170         if (((dev_caps_cfg &
1171               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1172              (dev_caps_cfg &
1173               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1174             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1175                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1176                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1177                         bp->pdev->addr.devid, bp->pdev->addr.function);
1178
1179                 rte_free(bp->hwrm_short_cmd_req_addr);
1180
1181                 bp->hwrm_short_cmd_req_addr =
1182                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1183                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1184                         rc = -ENOMEM;
1185                         goto error;
1186                 }
1187                 bp->hwrm_short_cmd_req_dma_addr =
1188                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1189                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1190                         rte_free(bp->hwrm_short_cmd_req_addr);
1191                         PMD_DRV_LOG(ERR,
1192                                 "Unable to map buffer to physical memory.\n");
1193                         rc = -ENOMEM;
1194                         goto error;
1195                 }
1196         }
1197         if (dev_caps_cfg &
1198             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1199                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1200                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1201         }
1202         if (dev_caps_cfg &
1203             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1204                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1205         if (dev_caps_cfg &
1206             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1207                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1208                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1209         }
1210
1211         if (dev_caps_cfg &
1212             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1213                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1214                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1215         }
1216
1217
1218 error:
1219         HWRM_UNLOCK();
1220         return rc;
1221 }
1222
1223 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1224 {
1225         int rc;
1226         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1227         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1228
1229         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1230                 return 0;
1231
1232         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1233         req.flags = flags;
1234
1235         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1236
1237         HWRM_CHECK_RESULT();
1238         HWRM_UNLOCK();
1239
1240         return rc;
1241 }
1242
1243 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1244 {
1245         int rc = 0;
1246         struct hwrm_port_phy_cfg_input req = {0};
1247         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1248         uint32_t enables = 0;
1249
1250         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1251
1252         if (conf->link_up) {
1253                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1254                 if (bp->link_info->auto_mode && conf->link_speed) {
1255                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1256                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1257                 }
1258
1259                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1260                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1261                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1262                 /*
1263                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1264                  * any auto mode, even "none".
1265                  */
1266                 if (!conf->link_speed) {
1267                         /* No speeds specified. Enable AutoNeg - all speeds */
1268                         req.auto_mode =
1269                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1270                 }
1271                 /* AutoNeg - Advertise speeds specified. */
1272                 if (conf->auto_link_speed_mask &&
1273                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1274                         req.auto_mode =
1275                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1276                         req.auto_link_speed_mask =
1277                                 conf->auto_link_speed_mask;
1278                         enables |=
1279                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1280                 }
1281
1282                 req.auto_duplex = conf->duplex;
1283                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1284                 req.auto_pause = conf->auto_pause;
1285                 req.force_pause = conf->force_pause;
1286                 /* Set force_pause if there is no auto or if there is a force */
1287                 if (req.auto_pause && !req.force_pause)
1288                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1289                 else
1290                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1291
1292                 req.enables = rte_cpu_to_le_32(enables);
1293         } else {
1294                 req.flags =
1295                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1296                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1297         }
1298
1299         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1300
1301         HWRM_CHECK_RESULT();
1302         HWRM_UNLOCK();
1303
1304         return rc;
1305 }
1306
1307 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1308                                    struct bnxt_link_info *link_info)
1309 {
1310         int rc = 0;
1311         struct hwrm_port_phy_qcfg_input req = {0};
1312         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1313
1314         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1315
1316         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1317
1318         HWRM_CHECK_RESULT();
1319
1320         link_info->phy_link_status = resp->link;
1321         link_info->link_up =
1322                 (link_info->phy_link_status ==
1323                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1324         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1325         link_info->duplex = resp->duplex_cfg;
1326         link_info->pause = resp->pause;
1327         link_info->auto_pause = resp->auto_pause;
1328         link_info->force_pause = resp->force_pause;
1329         link_info->auto_mode = resp->auto_mode;
1330         link_info->phy_type = resp->phy_type;
1331         link_info->media_type = resp->media_type;
1332
1333         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1334         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1335         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1336         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1337         link_info->phy_ver[0] = resp->phy_maj;
1338         link_info->phy_ver[1] = resp->phy_min;
1339         link_info->phy_ver[2] = resp->phy_bld;
1340
1341         HWRM_UNLOCK();
1342
1343         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1344         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1345         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1346         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1347         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1348                     link_info->auto_link_speed_mask);
1349         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1350                     link_info->force_link_speed);
1351
1352         return rc;
1353 }
1354
1355 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1356 {
1357         int rc = 0;
1358         struct hwrm_port_phy_qcaps_input req = {0};
1359         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1360
1361         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1362                 return 0;
1363
1364         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1365
1366         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1367
1368         HWRM_CHECK_RESULT();
1369
1370         bp->port_cnt = resp->port_cnt;
1371
1372         HWRM_UNLOCK();
1373
1374         return 0;
1375 }
1376
1377 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1378 {
1379         int i = 0;
1380
1381         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1382                 if (bp->tx_cos_queue[i].profile ==
1383                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1384                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1385                         return true;
1386                 }
1387         }
1388         return false;
1389 }
1390
1391 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1392 {
1393         int i = 0;
1394
1395         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1396                 if (bp->tx_cos_queue[i].profile !=
1397                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1398                     bp->tx_cos_queue[i].id !=
1399                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1400                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1401                         break;
1402                 }
1403         }
1404 }
1405
1406 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1407 {
1408         int rc = 0;
1409         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1410         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1411         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1412         int i;
1413
1414 get_rx_info:
1415         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1416
1417         req.flags = rte_cpu_to_le_32(dir);
1418         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1419         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1420             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1421                 req.drv_qmap_cap =
1422                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1423         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1424
1425         HWRM_CHECK_RESULT();
1426
1427         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1428                 GET_TX_QUEUE_INFO(0);
1429                 GET_TX_QUEUE_INFO(1);
1430                 GET_TX_QUEUE_INFO(2);
1431                 GET_TX_QUEUE_INFO(3);
1432                 GET_TX_QUEUE_INFO(4);
1433                 GET_TX_QUEUE_INFO(5);
1434                 GET_TX_QUEUE_INFO(6);
1435                 GET_TX_QUEUE_INFO(7);
1436         } else  {
1437                 GET_RX_QUEUE_INFO(0);
1438                 GET_RX_QUEUE_INFO(1);
1439                 GET_RX_QUEUE_INFO(2);
1440                 GET_RX_QUEUE_INFO(3);
1441                 GET_RX_QUEUE_INFO(4);
1442                 GET_RX_QUEUE_INFO(5);
1443                 GET_RX_QUEUE_INFO(6);
1444                 GET_RX_QUEUE_INFO(7);
1445         }
1446
1447         HWRM_UNLOCK();
1448
1449         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1450                 goto done;
1451
1452         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1453                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1454         } else {
1455                 int j;
1456
1457                 /* iterate and find the COSq profile to use for Tx */
1458                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1459                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1460                                 if (bp->tx_cos_queue[i].id != 0xff)
1461                                         bp->tx_cosq_id[j++] =
1462                                                 bp->tx_cos_queue[i].id;
1463                         }
1464                 } else {
1465                         /* When CoS classification is disabled, for normal NIC
1466                          * operations, ideally we should look to use LOSSY.
1467                          * If not found, fallback to the first valid profile
1468                          */
1469                         if (!bnxt_find_lossy_profile(bp))
1470                                 bnxt_find_first_valid_profile(bp);
1471
1472                 }
1473         }
1474
1475         bp->max_tc = resp->max_configurable_queues;
1476         bp->max_lltc = resp->max_configurable_lossless_queues;
1477         if (bp->max_tc > BNXT_MAX_QUEUE)
1478                 bp->max_tc = BNXT_MAX_QUEUE;
1479         bp->max_q = bp->max_tc;
1480
1481         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1482                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1483                 goto get_rx_info;
1484         }
1485
1486 done:
1487         return rc;
1488 }
1489
1490 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1491                          struct bnxt_ring *ring,
1492                          uint32_t ring_type, uint32_t map_index,
1493                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1494                          uint16_t tx_cosq_id)
1495 {
1496         int rc = 0;
1497         uint32_t enables = 0;
1498         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1499         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1500         struct rte_mempool *mb_pool;
1501         uint16_t rx_buf_size;
1502
1503         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1504
1505         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1506         req.fbo = rte_cpu_to_le_32(0);
1507         /* Association of ring index with doorbell index */
1508         req.logical_id = rte_cpu_to_le_16(map_index);
1509         req.length = rte_cpu_to_le_32(ring->ring_size);
1510
1511         switch (ring_type) {
1512         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1513                 req.ring_type = ring_type;
1514                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1515                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1516                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1517                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1518                         enables |=
1519                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1520                 break;
1521         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1522                 req.ring_type = ring_type;
1523                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1524                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1525                 if (BNXT_CHIP_THOR(bp)) {
1526                         mb_pool = bp->rx_queues[0]->mb_pool;
1527                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1528                                       RTE_PKTMBUF_HEADROOM;
1529                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1530                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1531                         enables |=
1532                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1533                 }
1534                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1535                         enables |=
1536                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1537                 break;
1538         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1539                 req.ring_type = ring_type;
1540                 if (BNXT_HAS_NQ(bp)) {
1541                         /* Association of cp ring with nq */
1542                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1543                         enables |=
1544                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1545                 }
1546                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1547                 break;
1548         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1549                 req.ring_type = ring_type;
1550                 req.page_size = BNXT_PAGE_SHFT;
1551                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1552                 break;
1553         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1554                 req.ring_type = ring_type;
1555                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1556
1557                 mb_pool = bp->rx_queues[0]->mb_pool;
1558                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1559                               RTE_PKTMBUF_HEADROOM;
1560                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1561                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1562
1563                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1564                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1565                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1566                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1567                 break;
1568         default:
1569                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1570                         ring_type);
1571                 HWRM_UNLOCK();
1572                 return -EINVAL;
1573         }
1574         req.enables = rte_cpu_to_le_32(enables);
1575
1576         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1577
1578         if (rc || resp->error_code) {
1579                 if (rc == 0 && resp->error_code)
1580                         rc = rte_le_to_cpu_16(resp->error_code);
1581                 switch (ring_type) {
1582                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1583                         PMD_DRV_LOG(ERR,
1584                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1585                         HWRM_UNLOCK();
1586                         return rc;
1587                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1588                         PMD_DRV_LOG(ERR,
1589                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1590                         HWRM_UNLOCK();
1591                         return rc;
1592                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1593                         PMD_DRV_LOG(ERR,
1594                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1595                                     rc);
1596                         HWRM_UNLOCK();
1597                         return rc;
1598                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1599                         PMD_DRV_LOG(ERR,
1600                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1601                         HWRM_UNLOCK();
1602                         return rc;
1603                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1604                         PMD_DRV_LOG(ERR,
1605                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1606                         HWRM_UNLOCK();
1607                         return rc;
1608                 default:
1609                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1610                         HWRM_UNLOCK();
1611                         return rc;
1612                 }
1613         }
1614
1615         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1616         HWRM_UNLOCK();
1617         return rc;
1618 }
1619
1620 int bnxt_hwrm_ring_free(struct bnxt *bp,
1621                         struct bnxt_ring *ring, uint32_t ring_type)
1622 {
1623         int rc;
1624         struct hwrm_ring_free_input req = {.req_type = 0 };
1625         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1626
1627         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1628
1629         req.ring_type = ring_type;
1630         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1631
1632         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1633
1634         if (rc || resp->error_code) {
1635                 if (rc == 0 && resp->error_code)
1636                         rc = rte_le_to_cpu_16(resp->error_code);
1637                 HWRM_UNLOCK();
1638
1639                 switch (ring_type) {
1640                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1641                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1642                                 rc);
1643                         return rc;
1644                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1645                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1646                                 rc);
1647                         return rc;
1648                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1649                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1650                                 rc);
1651                         return rc;
1652                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1653                         PMD_DRV_LOG(ERR,
1654                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1655                         return rc;
1656                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1657                         PMD_DRV_LOG(ERR,
1658                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1659                         return rc;
1660                 default:
1661                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1662                         return rc;
1663                 }
1664         }
1665         HWRM_UNLOCK();
1666         return 0;
1667 }
1668
1669 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1670 {
1671         int rc = 0;
1672         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1673         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1674
1675         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1676
1677         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1678         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1679         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1680         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1681
1682         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1683
1684         HWRM_CHECK_RESULT();
1685
1686         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1687
1688         HWRM_UNLOCK();
1689
1690         return rc;
1691 }
1692
1693 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1694 {
1695         int rc;
1696         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1697         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1698
1699         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1700
1701         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1702
1703         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1704
1705         HWRM_CHECK_RESULT();
1706         HWRM_UNLOCK();
1707
1708         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1709         return rc;
1710 }
1711
1712 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1713 {
1714         int rc = 0;
1715         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1716         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1717
1718         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1719                 return rc;
1720
1721         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1722
1723         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1724
1725         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1726
1727         HWRM_CHECK_RESULT();
1728         HWRM_UNLOCK();
1729
1730         return rc;
1731 }
1732
1733 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1734                                 unsigned int idx __rte_unused)
1735 {
1736         int rc;
1737         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1738         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1739
1740         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1741
1742         req.update_period_ms = rte_cpu_to_le_32(0);
1743
1744         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1745
1746         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1747
1748         HWRM_CHECK_RESULT();
1749
1750         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1751
1752         HWRM_UNLOCK();
1753
1754         return rc;
1755 }
1756
1757 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1758                                 unsigned int idx __rte_unused)
1759 {
1760         int rc;
1761         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1762         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1763
1764         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1765
1766         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1767
1768         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1769
1770         HWRM_CHECK_RESULT();
1771         HWRM_UNLOCK();
1772
1773         return rc;
1774 }
1775
1776 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1777 {
1778         int rc = 0, i, j;
1779         struct hwrm_vnic_alloc_input req = { 0 };
1780         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1781
1782         if (!BNXT_HAS_RING_GRPS(bp))
1783                 goto skip_ring_grps;
1784
1785         /* map ring groups to this vnic */
1786         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1787                 vnic->start_grp_id, vnic->end_grp_id);
1788         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1789                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1790
1791         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1792         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1793         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1794         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1795
1796 skip_ring_grps:
1797         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1798         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1799
1800         if (vnic->func_default)
1801                 req.flags =
1802                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1803         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1804
1805         HWRM_CHECK_RESULT();
1806
1807         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1808         HWRM_UNLOCK();
1809         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1810         return rc;
1811 }
1812
1813 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1814                                         struct bnxt_vnic_info *vnic,
1815                                         struct bnxt_plcmodes_cfg *pmode)
1816 {
1817         int rc = 0;
1818         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1819         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1820
1821         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1822
1823         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1824
1825         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1826
1827         HWRM_CHECK_RESULT();
1828
1829         pmode->flags = rte_le_to_cpu_32(resp->flags);
1830         /* dflt_vnic bit doesn't exist in the _cfg command */
1831         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1832         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1833         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1834         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1835
1836         HWRM_UNLOCK();
1837
1838         return rc;
1839 }
1840
1841 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1842                                        struct bnxt_vnic_info *vnic,
1843                                        struct bnxt_plcmodes_cfg *pmode)
1844 {
1845         int rc = 0;
1846         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1847         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1848
1849         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1850                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1851                 return rc;
1852         }
1853
1854         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1855
1856         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1857         req.flags = rte_cpu_to_le_32(pmode->flags);
1858         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1859         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1860         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1861         req.enables = rte_cpu_to_le_32(
1862             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1863             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1864             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1865         );
1866
1867         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1868
1869         HWRM_CHECK_RESULT();
1870         HWRM_UNLOCK();
1871
1872         return rc;
1873 }
1874
1875 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1876 {
1877         int rc = 0;
1878         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1879         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1880         struct bnxt_plcmodes_cfg pmodes = { 0 };
1881         uint32_t ctx_enable_flag = 0;
1882         uint32_t enables = 0;
1883
1884         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1885                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1886                 return rc;
1887         }
1888
1889         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1890         if (rc)
1891                 return rc;
1892
1893         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1894
1895         if (BNXT_CHIP_THOR(bp)) {
1896                 int dflt_rxq = vnic->start_grp_id;
1897                 struct bnxt_rx_ring_info *rxr;
1898                 struct bnxt_cp_ring_info *cpr;
1899                 struct bnxt_rx_queue *rxq;
1900                 int i;
1901
1902                 /*
1903                  * The first active receive ring is used as the VNIC
1904                  * default receive ring. If there are no active receive
1905                  * rings (all corresponding receive queues are stopped),
1906                  * the first receive ring is used.
1907                  */
1908                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1909                         rxq = bp->eth_dev->data->rx_queues[i];
1910                         if (rxq->rx_started) {
1911                                 dflt_rxq = i;
1912                                 break;
1913                         }
1914                 }
1915
1916                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1917                 rxr = rxq->rx_ring;
1918                 cpr = rxq->cp_ring;
1919
1920                 req.default_rx_ring_id =
1921                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1922                 req.default_cmpl_ring_id =
1923                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1924                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1925                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1926                 goto config_mru;
1927         }
1928
1929         /* Only RSS support for now TBD: COS & LB */
1930         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1931         if (vnic->lb_rule != 0xffff)
1932                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1933         if (vnic->cos_rule != 0xffff)
1934                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1935         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1936                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1937                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1938         }
1939         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1940                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1941                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1942         }
1943
1944         enables |= ctx_enable_flag;
1945         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1946         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1947         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1948         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1949
1950 config_mru:
1951         req.enables = rte_cpu_to_le_32(enables);
1952         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1953         req.mru = rte_cpu_to_le_16(vnic->mru);
1954         /* Configure default VNIC only once. */
1955         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1956                 req.flags |=
1957                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1958                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1959         }
1960         if (vnic->vlan_strip)
1961                 req.flags |=
1962                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1963         if (vnic->bd_stall)
1964                 req.flags |=
1965                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1966         if (vnic->roce_dual)
1967                 req.flags |= rte_cpu_to_le_32(
1968                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1969         if (vnic->roce_only)
1970                 req.flags |= rte_cpu_to_le_32(
1971                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1972         if (vnic->rss_dflt_cr)
1973                 req.flags |= rte_cpu_to_le_32(
1974                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1975
1976         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1977
1978         HWRM_CHECK_RESULT();
1979         HWRM_UNLOCK();
1980
1981         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1982
1983         return rc;
1984 }
1985
1986 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1987                 int16_t fw_vf_id)
1988 {
1989         int rc = 0;
1990         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1991         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1992
1993         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1994                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1995                 return rc;
1996         }
1997         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
1998
1999         req.enables =
2000                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2001         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2002         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2003
2004         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2005
2006         HWRM_CHECK_RESULT();
2007
2008         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2009         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2010         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2011         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2012         vnic->mru = rte_le_to_cpu_16(resp->mru);
2013         vnic->func_default = rte_le_to_cpu_32(
2014                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2015         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2016                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2017         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2018                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2019         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
2020                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
2021         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
2022                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
2023         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2024                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2025
2026         HWRM_UNLOCK();
2027
2028         return rc;
2029 }
2030
2031 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2032                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2033 {
2034         int rc = 0;
2035         uint16_t ctx_id;
2036         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2037         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2038                                                 bp->hwrm_cmd_resp_addr;
2039
2040         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2041
2042         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2043         HWRM_CHECK_RESULT();
2044
2045         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2046         if (!BNXT_HAS_RING_GRPS(bp))
2047                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2048         else if (ctx_idx == 0)
2049                 vnic->rss_rule = ctx_id;
2050
2051         HWRM_UNLOCK();
2052
2053         return rc;
2054 }
2055
2056 static
2057 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2058                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2059 {
2060         int rc = 0;
2061         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2062         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2063                                                 bp->hwrm_cmd_resp_addr;
2064
2065         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2066                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2067                 return rc;
2068         }
2069         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2070
2071         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2072
2073         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2074
2075         HWRM_CHECK_RESULT();
2076         HWRM_UNLOCK();
2077
2078         return rc;
2079 }
2080
2081 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2082 {
2083         int rc = 0;
2084
2085         if (BNXT_CHIP_THOR(bp)) {
2086                 int j;
2087
2088                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2089                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2090                                                       vnic,
2091                                                       vnic->fw_grp_ids[j]);
2092                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2093                 }
2094                 vnic->num_lb_ctxts = 0;
2095         } else {
2096                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2097                 vnic->rss_rule = INVALID_HW_RING_ID;
2098         }
2099
2100         return rc;
2101 }
2102
2103 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2104 {
2105         int rc = 0;
2106         struct hwrm_vnic_free_input req = {.req_type = 0 };
2107         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2108
2109         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2110                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2111                 return rc;
2112         }
2113
2114         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2115
2116         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2117
2118         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2119
2120         HWRM_CHECK_RESULT();
2121         HWRM_UNLOCK();
2122
2123         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2124         /* Configure default VNIC again if necessary. */
2125         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2126                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2127
2128         return rc;
2129 }
2130
2131 static int
2132 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2133 {
2134         int i;
2135         int rc = 0;
2136         int nr_ctxs = vnic->num_lb_ctxts;
2137         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2138         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2139
2140         for (i = 0; i < nr_ctxs; i++) {
2141                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2142
2143                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2144                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2145                 req.hash_mode_flags = vnic->hash_mode;
2146
2147                 req.hash_key_tbl_addr =
2148                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2149
2150                 req.ring_grp_tbl_addr =
2151                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2152                                          i * HW_HASH_INDEX_SIZE);
2153                 req.ring_table_pair_index = i;
2154                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2155
2156                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2157                                             BNXT_USE_CHIMP_MB);
2158
2159                 HWRM_CHECK_RESULT();
2160                 HWRM_UNLOCK();
2161         }
2162
2163         return rc;
2164 }
2165
2166 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2167                            struct bnxt_vnic_info *vnic)
2168 {
2169         int rc = 0;
2170         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2171         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2172
2173         if (!vnic->rss_table)
2174                 return 0;
2175
2176         if (BNXT_CHIP_THOR(bp))
2177                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2178
2179         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2180
2181         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2182         req.hash_mode_flags = vnic->hash_mode;
2183
2184         req.ring_grp_tbl_addr =
2185             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2186         req.hash_key_tbl_addr =
2187             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2188         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2189         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2190
2191         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2192
2193         HWRM_CHECK_RESULT();
2194         HWRM_UNLOCK();
2195
2196         return rc;
2197 }
2198
2199 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2200                         struct bnxt_vnic_info *vnic)
2201 {
2202         int rc = 0;
2203         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2204         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2205         uint16_t size;
2206
2207         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2208                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2209                 return rc;
2210         }
2211
2212         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2213
2214         req.flags = rte_cpu_to_le_32(
2215                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2216
2217         req.enables = rte_cpu_to_le_32(
2218                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2219
2220         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2221         size -= RTE_PKTMBUF_HEADROOM;
2222         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2223
2224         req.jumbo_thresh = rte_cpu_to_le_16(size);
2225         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2226
2227         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2228
2229         HWRM_CHECK_RESULT();
2230         HWRM_UNLOCK();
2231
2232         return rc;
2233 }
2234
2235 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2236                         struct bnxt_vnic_info *vnic, bool enable)
2237 {
2238         int rc = 0;
2239         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2240         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2241
2242         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2243                 if (enable)
2244                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2245                 return -ENOTSUP;
2246         }
2247
2248         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2249                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2250                 return 0;
2251         }
2252
2253         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2254
2255         if (enable) {
2256                 req.enables = rte_cpu_to_le_32(
2257                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2258                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2259                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2260                 req.flags = rte_cpu_to_le_32(
2261                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2262                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2263                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2264                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2265                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2266                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2267                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2268                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2269                 req.min_agg_len = rte_cpu_to_le_32(512);
2270         }
2271         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2272
2273         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2274
2275         HWRM_CHECK_RESULT();
2276         HWRM_UNLOCK();
2277
2278         return rc;
2279 }
2280
2281 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2282 {
2283         struct hwrm_func_cfg_input req = {0};
2284         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2285         int rc;
2286
2287         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2288         req.enables = rte_cpu_to_le_32(
2289                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2290         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2291         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2292
2293         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2294
2295         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2296         HWRM_CHECK_RESULT();
2297         HWRM_UNLOCK();
2298
2299         bp->pf->vf_info[vf].random_mac = false;
2300
2301         return rc;
2302 }
2303
2304 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2305                                   uint64_t *dropped)
2306 {
2307         int rc = 0;
2308         struct hwrm_func_qstats_input req = {.req_type = 0};
2309         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2310
2311         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2312
2313         req.fid = rte_cpu_to_le_16(fid);
2314
2315         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2316
2317         HWRM_CHECK_RESULT();
2318
2319         if (dropped)
2320                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2321
2322         HWRM_UNLOCK();
2323
2324         return rc;
2325 }
2326
2327 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2328                           struct rte_eth_stats *stats,
2329                           struct hwrm_func_qstats_output *func_qstats)
2330 {
2331         int rc = 0;
2332         struct hwrm_func_qstats_input req = {.req_type = 0};
2333         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2334
2335         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2336
2337         req.fid = rte_cpu_to_le_16(fid);
2338
2339         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2340
2341         HWRM_CHECK_RESULT();
2342         if (func_qstats)
2343                 memcpy(func_qstats, resp,
2344                        sizeof(struct hwrm_func_qstats_output));
2345
2346         if (!stats)
2347                 goto exit;
2348
2349         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2350         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2351         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2352         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2353         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2354         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2355
2356         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2357         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2358         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2359         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2360         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2361         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2362
2363         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2364         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2365         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2366
2367 exit:
2368         HWRM_UNLOCK();
2369
2370         return rc;
2371 }
2372
2373 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2374 {
2375         int rc = 0;
2376         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2377         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2378
2379         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2380
2381         req.fid = rte_cpu_to_le_16(fid);
2382
2383         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2384
2385         HWRM_CHECK_RESULT();
2386         HWRM_UNLOCK();
2387
2388         return rc;
2389 }
2390
2391 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2392 {
2393         unsigned int i;
2394         int rc = 0;
2395
2396         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2397                 struct bnxt_tx_queue *txq;
2398                 struct bnxt_rx_queue *rxq;
2399                 struct bnxt_cp_ring_info *cpr;
2400
2401                 if (i >= bp->rx_cp_nr_rings) {
2402                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2403                         cpr = txq->cp_ring;
2404                 } else {
2405                         rxq = bp->rx_queues[i];
2406                         cpr = rxq->cp_ring;
2407                 }
2408
2409                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2410                 if (rc)
2411                         return rc;
2412         }
2413         return 0;
2414 }
2415
2416 static int
2417 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2418 {
2419         int rc;
2420         unsigned int i;
2421         struct bnxt_cp_ring_info *cpr;
2422
2423         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2424
2425                 if (i >= bp->rx_cp_nr_rings) {
2426                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2427                 } else {
2428                         cpr = bp->rx_queues[i]->cp_ring;
2429                         if (BNXT_HAS_RING_GRPS(bp))
2430                                 bp->grp_info[i].fw_stats_ctx = -1;
2431                 }
2432                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2433                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2434                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2435                         if (rc)
2436                                 return rc;
2437                 }
2438         }
2439         return 0;
2440 }
2441
2442 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2443 {
2444         unsigned int i;
2445         int rc = 0;
2446
2447         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2448                 struct bnxt_tx_queue *txq;
2449                 struct bnxt_rx_queue *rxq;
2450                 struct bnxt_cp_ring_info *cpr;
2451
2452                 if (i >= bp->rx_cp_nr_rings) {
2453                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2454                         cpr = txq->cp_ring;
2455                 } else {
2456                         rxq = bp->rx_queues[i];
2457                         cpr = rxq->cp_ring;
2458                 }
2459
2460                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2461
2462                 if (rc)
2463                         return rc;
2464         }
2465         return rc;
2466 }
2467
2468 static int
2469 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2470 {
2471         uint16_t idx;
2472         uint32_t rc = 0;
2473
2474         if (!BNXT_HAS_RING_GRPS(bp))
2475                 return 0;
2476
2477         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2478
2479                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2480                         continue;
2481
2482                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2483
2484                 if (rc)
2485                         return rc;
2486         }
2487         return rc;
2488 }
2489
2490 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2491 {
2492         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2493
2494         bnxt_hwrm_ring_free(bp, cp_ring,
2495                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2496         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2497         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2498                                      sizeof(*cpr->cp_desc_ring));
2499         cpr->cp_raw_cons = 0;
2500         cpr->valid = 0;
2501 }
2502
2503 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2504 {
2505         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2506
2507         bnxt_hwrm_ring_free(bp, cp_ring,
2508                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2509         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2510         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2511                         sizeof(*cpr->cp_desc_ring));
2512         cpr->cp_raw_cons = 0;
2513         cpr->valid = 0;
2514 }
2515
2516 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2517 {
2518         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2519         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2520         struct bnxt_ring *ring = rxr->rx_ring_struct;
2521         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2522
2523         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2524                 bnxt_hwrm_ring_free(bp, ring,
2525                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2526                 ring->fw_ring_id = INVALID_HW_RING_ID;
2527                 if (BNXT_HAS_RING_GRPS(bp))
2528                         bp->grp_info[queue_index].rx_fw_ring_id =
2529                                                         INVALID_HW_RING_ID;
2530         }
2531         ring = rxr->ag_ring_struct;
2532         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2533                 bnxt_hwrm_ring_free(bp, ring,
2534                                     BNXT_CHIP_THOR(bp) ?
2535                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2536                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2537                 if (BNXT_HAS_RING_GRPS(bp))
2538                         bp->grp_info[queue_index].ag_fw_ring_id =
2539                                                         INVALID_HW_RING_ID;
2540         }
2541         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2542                 bnxt_free_cp_ring(bp, cpr);
2543
2544         if (BNXT_HAS_RING_GRPS(bp))
2545                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2546 }
2547
2548 static int
2549 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2550 {
2551         unsigned int i;
2552
2553         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2554                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2555                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2556                 struct bnxt_ring *ring = txr->tx_ring_struct;
2557                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2558
2559                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2560                         bnxt_hwrm_ring_free(bp, ring,
2561                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2562                         ring->fw_ring_id = INVALID_HW_RING_ID;
2563                         memset(txr->tx_desc_ring, 0,
2564                                         txr->tx_ring_struct->ring_size *
2565                                         sizeof(*txr->tx_desc_ring));
2566                         memset(txr->tx_buf_ring, 0,
2567                                         txr->tx_ring_struct->ring_size *
2568                                         sizeof(*txr->tx_buf_ring));
2569                         txr->tx_prod = 0;
2570                         txr->tx_cons = 0;
2571                 }
2572                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2573                         bnxt_free_cp_ring(bp, cpr);
2574                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2575                 }
2576         }
2577
2578         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2579                 bnxt_free_hwrm_rx_ring(bp, i);
2580
2581         return 0;
2582 }
2583
2584 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2585 {
2586         uint16_t i;
2587         uint32_t rc = 0;
2588
2589         if (!BNXT_HAS_RING_GRPS(bp))
2590                 return 0;
2591
2592         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2593                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2594                 if (rc)
2595                         return rc;
2596         }
2597         return rc;
2598 }
2599
2600 /*
2601  * HWRM utility functions
2602  */
2603
2604 void bnxt_free_hwrm_resources(struct bnxt *bp)
2605 {
2606         /* Release memzone */
2607         rte_free(bp->hwrm_cmd_resp_addr);
2608         rte_free(bp->hwrm_short_cmd_req_addr);
2609         bp->hwrm_cmd_resp_addr = NULL;
2610         bp->hwrm_short_cmd_req_addr = NULL;
2611         bp->hwrm_cmd_resp_dma_addr = 0;
2612         bp->hwrm_short_cmd_req_dma_addr = 0;
2613 }
2614
2615 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2616 {
2617         struct rte_pci_device *pdev = bp->pdev;
2618         char type[RTE_MEMZONE_NAMESIZE];
2619
2620         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2621                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2622         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2623         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2624         if (bp->hwrm_cmd_resp_addr == NULL)
2625                 return -ENOMEM;
2626         bp->hwrm_cmd_resp_dma_addr =
2627                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2628         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2629                 PMD_DRV_LOG(ERR,
2630                         "unable to map response address to physical memory\n");
2631                 return -ENOMEM;
2632         }
2633         rte_spinlock_init(&bp->hwrm_lock);
2634
2635         return 0;
2636 }
2637
2638 int
2639 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2640 {
2641         int rc = 0;
2642
2643         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2644                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2645                 if (rc)
2646                         return rc;
2647         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2648                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2649                 if (rc)
2650                         return rc;
2651         }
2652
2653         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2654         return rc;
2655 }
2656
2657 static int
2658 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2659 {
2660         struct bnxt_filter_info *filter;
2661         int rc = 0;
2662
2663         STAILQ_FOREACH(filter, &vnic->filter, next) {
2664                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2665                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2666                 bnxt_free_filter(bp, filter);
2667         }
2668         return rc;
2669 }
2670
2671 static int
2672 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2673 {
2674         struct bnxt_filter_info *filter;
2675         struct rte_flow *flow;
2676         int rc = 0;
2677
2678         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2679                 flow = STAILQ_FIRST(&vnic->flow_list);
2680                 filter = flow->filter;
2681                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2682                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2683
2684                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2685                 rte_free(flow);
2686         }
2687         return rc;
2688 }
2689
2690 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2691 {
2692         struct bnxt_filter_info *filter;
2693         int rc = 0;
2694
2695         STAILQ_FOREACH(filter, &vnic->filter, next) {
2696                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2697                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2698                                                      filter);
2699                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2700                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2701                                                          filter);
2702                 else
2703                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2704                                                      filter);
2705                 if (rc)
2706                         break;
2707         }
2708         return rc;
2709 }
2710
2711 static void
2712 bnxt_free_tunnel_ports(struct bnxt *bp)
2713 {
2714         if (bp->vxlan_port_cnt)
2715                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2716                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2717         bp->vxlan_port = 0;
2718         if (bp->geneve_port_cnt)
2719                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2720                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2721         bp->geneve_port = 0;
2722 }
2723
2724 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2725 {
2726         int i;
2727
2728         if (bp->vnic_info == NULL)
2729                 return;
2730
2731         /*
2732          * Cleanup VNICs in reverse order, to make sure the L2 filter
2733          * from vnic0 is last to be cleaned up.
2734          */
2735         for (i = bp->max_vnics - 1; i >= 0; i--) {
2736                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2737
2738                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2739                         continue;
2740
2741                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2742
2743                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2744
2745                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2746
2747                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2748
2749                 bnxt_hwrm_vnic_free(bp, vnic);
2750
2751                 rte_free(vnic->fw_grp_ids);
2752         }
2753         /* Ring resources */
2754         bnxt_free_all_hwrm_rings(bp);
2755         bnxt_free_all_hwrm_ring_grps(bp);
2756         bnxt_free_all_hwrm_stat_ctxs(bp);
2757         bnxt_free_tunnel_ports(bp);
2758 }
2759
2760 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2761 {
2762         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2763
2764         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2765                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2766
2767         switch (conf_link_speed) {
2768         case ETH_LINK_SPEED_10M_HD:
2769         case ETH_LINK_SPEED_100M_HD:
2770                 /* FALLTHROUGH */
2771                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2772         }
2773         return hw_link_duplex;
2774 }
2775
2776 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2777 {
2778         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2779 }
2780
2781 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2782 {
2783         uint16_t eth_link_speed = 0;
2784
2785         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2786                 return ETH_LINK_SPEED_AUTONEG;
2787
2788         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2789         case ETH_LINK_SPEED_100M:
2790         case ETH_LINK_SPEED_100M_HD:
2791                 /* FALLTHROUGH */
2792                 eth_link_speed =
2793                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2794                 break;
2795         case ETH_LINK_SPEED_1G:
2796                 eth_link_speed =
2797                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2798                 break;
2799         case ETH_LINK_SPEED_2_5G:
2800                 eth_link_speed =
2801                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2802                 break;
2803         case ETH_LINK_SPEED_10G:
2804                 eth_link_speed =
2805                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2806                 break;
2807         case ETH_LINK_SPEED_20G:
2808                 eth_link_speed =
2809                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2810                 break;
2811         case ETH_LINK_SPEED_25G:
2812                 eth_link_speed =
2813                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2814                 break;
2815         case ETH_LINK_SPEED_40G:
2816                 eth_link_speed =
2817                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2818                 break;
2819         case ETH_LINK_SPEED_50G:
2820                 eth_link_speed =
2821                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2822                 break;
2823         case ETH_LINK_SPEED_100G:
2824                 eth_link_speed =
2825                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2826                 break;
2827         case ETH_LINK_SPEED_200G:
2828                 eth_link_speed =
2829                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB;
2830                 break;
2831         default:
2832                 PMD_DRV_LOG(ERR,
2833                         "Unsupported link speed %d; default to AUTO\n",
2834                         conf_link_speed);
2835                 break;
2836         }
2837         return eth_link_speed;
2838 }
2839
2840 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2841                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2842                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2843                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2844                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2845
2846 static int bnxt_validate_link_speed(struct bnxt *bp)
2847 {
2848         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
2849         uint16_t port_id = bp->eth_dev->data->port_id;
2850         uint32_t link_speed_capa;
2851         uint32_t one_speed;
2852
2853         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2854                 return 0;
2855
2856         link_speed_capa = bnxt_get_speed_capabilities(bp);
2857
2858         if (link_speed & ETH_LINK_SPEED_FIXED) {
2859                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2860
2861                 if (one_speed & (one_speed - 1)) {
2862                         PMD_DRV_LOG(ERR,
2863                                 "Invalid advertised speeds (%u) for port %u\n",
2864                                 link_speed, port_id);
2865                         return -EINVAL;
2866                 }
2867                 if ((one_speed & link_speed_capa) != one_speed) {
2868                         PMD_DRV_LOG(ERR,
2869                                 "Unsupported advertised speed (%u) for port %u\n",
2870                                 link_speed, port_id);
2871                         return -EINVAL;
2872                 }
2873         } else {
2874                 if (!(link_speed & link_speed_capa)) {
2875                         PMD_DRV_LOG(ERR,
2876                                 "Unsupported advertised speeds (%u) for port %u\n",
2877                                 link_speed, port_id);
2878                         return -EINVAL;
2879                 }
2880         }
2881         return 0;
2882 }
2883
2884 static uint16_t
2885 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2886 {
2887         uint16_t ret = 0;
2888
2889         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2890                 if (bp->link_info->support_speeds)
2891                         return bp->link_info->support_speeds;
2892                 link_speed = BNXT_SUPPORTED_SPEEDS;
2893         }
2894
2895         if (link_speed & ETH_LINK_SPEED_100M)
2896                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2897         if (link_speed & ETH_LINK_SPEED_100M_HD)
2898                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2899         if (link_speed & ETH_LINK_SPEED_1G)
2900                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2901         if (link_speed & ETH_LINK_SPEED_2_5G)
2902                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2903         if (link_speed & ETH_LINK_SPEED_10G)
2904                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2905         if (link_speed & ETH_LINK_SPEED_20G)
2906                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2907         if (link_speed & ETH_LINK_SPEED_25G)
2908                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2909         if (link_speed & ETH_LINK_SPEED_40G)
2910                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2911         if (link_speed & ETH_LINK_SPEED_50G)
2912                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2913         if (link_speed & ETH_LINK_SPEED_100G)
2914                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2915         if (link_speed & ETH_LINK_SPEED_200G)
2916                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB;
2917         return ret;
2918 }
2919
2920 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2921 {
2922         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2923
2924         switch (hw_link_speed) {
2925         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2926                 eth_link_speed = ETH_SPEED_NUM_100M;
2927                 break;
2928         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2929                 eth_link_speed = ETH_SPEED_NUM_1G;
2930                 break;
2931         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2932                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2933                 break;
2934         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2935                 eth_link_speed = ETH_SPEED_NUM_10G;
2936                 break;
2937         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2938                 eth_link_speed = ETH_SPEED_NUM_20G;
2939                 break;
2940         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2941                 eth_link_speed = ETH_SPEED_NUM_25G;
2942                 break;
2943         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2944                 eth_link_speed = ETH_SPEED_NUM_40G;
2945                 break;
2946         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2947                 eth_link_speed = ETH_SPEED_NUM_50G;
2948                 break;
2949         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2950                 eth_link_speed = ETH_SPEED_NUM_100G;
2951                 break;
2952         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
2953                 eth_link_speed = ETH_SPEED_NUM_200G;
2954                 break;
2955         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2956         default:
2957                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2958                         hw_link_speed);
2959                 break;
2960         }
2961         return eth_link_speed;
2962 }
2963
2964 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2965 {
2966         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2967
2968         switch (hw_link_duplex) {
2969         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2970         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2971                 /* FALLTHROUGH */
2972                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2973                 break;
2974         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2975                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2976                 break;
2977         default:
2978                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2979                         hw_link_duplex);
2980                 break;
2981         }
2982         return eth_link_duplex;
2983 }
2984
2985 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2986 {
2987         int rc = 0;
2988         struct bnxt_link_info *link_info = bp->link_info;
2989
2990         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2991         if (rc) {
2992                 PMD_DRV_LOG(ERR,
2993                         "Get link config failed with rc %d\n", rc);
2994                 goto exit;
2995         }
2996         if (link_info->link_speed)
2997                 link->link_speed =
2998                         bnxt_parse_hw_link_speed(link_info->link_speed);
2999         else
3000                 link->link_speed = ETH_SPEED_NUM_NONE;
3001         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3002         link->link_status = link_info->link_up;
3003         link->link_autoneg = link_info->auto_mode ==
3004                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3005                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3006 exit:
3007         return rc;
3008 }
3009
3010 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3011 {
3012         int rc = 0;
3013         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3014         struct bnxt_link_info link_req;
3015         uint16_t speed, autoneg;
3016
3017         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3018                 return 0;
3019
3020         rc = bnxt_validate_link_speed(bp);
3021         if (rc)
3022                 goto error;
3023
3024         memset(&link_req, 0, sizeof(link_req));
3025         link_req.link_up = link_up;
3026         if (!link_up)
3027                 goto port_phy_cfg;
3028
3029         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3030         if (BNXT_CHIP_THOR(bp) &&
3031             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3032                 /* 40G is not supported as part of media auto detect.
3033                  * The speed should be forced and autoneg disabled
3034                  * to configure 40G speed.
3035                  */
3036                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3037                 autoneg = 0;
3038         }
3039
3040         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
3041         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3042         /* Autoneg can be done only when the FW allows.
3043          * When user configures fixed speed of 40G and later changes to
3044          * any other speed, auto_link_speed/force_link_speed is still set
3045          * to 40G until link comes up at new speed.
3046          */
3047         if (autoneg == 1 &&
3048             !(!BNXT_CHIP_THOR(bp) &&
3049               (bp->link_info->auto_link_speed ||
3050                bp->link_info->force_link_speed))) {
3051                 link_req.phy_flags |=
3052                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3053                 link_req.auto_link_speed_mask =
3054                         bnxt_parse_eth_link_speed_mask(bp,
3055                                                        dev_conf->link_speeds);
3056         } else {
3057                 if (bp->link_info->phy_type ==
3058                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3059                     bp->link_info->phy_type ==
3060                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3061                     bp->link_info->media_type ==
3062                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3063                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3064                         return -EINVAL;
3065                 }
3066
3067                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3068                 /* If user wants a particular speed try that first. */
3069                 if (speed)
3070                         link_req.link_speed = speed;
3071                 else if (bp->link_info->force_link_speed)
3072                         link_req.link_speed = bp->link_info->force_link_speed;
3073                 else
3074                         link_req.link_speed = bp->link_info->auto_link_speed;
3075         }
3076         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3077         link_req.auto_pause = bp->link_info->auto_pause;
3078         link_req.force_pause = bp->link_info->force_pause;
3079
3080 port_phy_cfg:
3081         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3082         if (rc) {
3083                 PMD_DRV_LOG(ERR,
3084                         "Set link config failed with rc %d\n", rc);
3085         }
3086
3087 error:
3088         return rc;
3089 }
3090
3091 /* JIRA 22088 */
3092 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3093 {
3094         struct hwrm_func_qcfg_input req = {0};
3095         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3096         uint16_t flags;
3097         int rc = 0;
3098         bp->func_svif = BNXT_SVIF_INVALID;
3099         uint16_t svif_info;
3100
3101         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3102         req.fid = rte_cpu_to_le_16(0xffff);
3103
3104         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3105
3106         HWRM_CHECK_RESULT();
3107
3108         /* Hard Coded.. 0xfff VLAN ID mask */
3109         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3110
3111         svif_info = rte_le_to_cpu_16(resp->svif_info);
3112         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3113                 bp->func_svif = svif_info &
3114                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3115
3116         flags = rte_le_to_cpu_16(resp->flags);
3117         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3118                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3119
3120         if (BNXT_VF(bp) &&
3121             !BNXT_VF_IS_TRUSTED(bp) &&
3122             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3123                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3124                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3125         } else if (BNXT_VF(bp) &&
3126                    BNXT_VF_IS_TRUSTED(bp) &&
3127                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3128                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3129                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3130         }
3131
3132         if (mtu)
3133                 *mtu = rte_le_to_cpu_16(resp->mtu);
3134
3135         switch (resp->port_partition_type) {
3136         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3137         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3138         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3139                 /* FALLTHROUGH */
3140                 bp->flags |= BNXT_FLAG_NPAR_PF;
3141                 break;
3142         default:
3143                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3144                 break;
3145         }
3146
3147         HWRM_UNLOCK();
3148
3149         return rc;
3150 }
3151
3152 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3153 {
3154         struct hwrm_func_qcfg_input req = {0};
3155         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3156         int rc;
3157
3158         if (!BNXT_VF_IS_TRUSTED(bp))
3159                 return 0;
3160
3161         if (!bp->parent)
3162                 return -EINVAL;
3163
3164         bp->parent->fid = BNXT_PF_FID_INVALID;
3165
3166         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3167
3168         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3169
3170         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3171
3172         HWRM_CHECK_RESULT();
3173
3174         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3175         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3176         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3177         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3178
3179         /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3180         if (bp->parent->vnic == 0) {
3181                 PMD_DRV_LOG(ERR, "Error: parent VNIC unavailable.\n");
3182                 /* Use hard-coded values appropriate for current Wh+ fw. */
3183                 if (bp->parent->fid == 2)
3184                         bp->parent->vnic = 0x100;
3185                 else
3186                         bp->parent->vnic = 1;
3187         }
3188
3189         HWRM_UNLOCK();
3190
3191         return 0;
3192 }
3193
3194 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3195                                  uint16_t *vnic_id, uint16_t *svif)
3196 {
3197         struct hwrm_func_qcfg_input req = {0};
3198         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3199         uint16_t svif_info;
3200         int rc = 0;
3201
3202         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3203         req.fid = rte_cpu_to_le_16(fid);
3204
3205         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3206
3207         HWRM_CHECK_RESULT();
3208
3209         if (vnic_id)
3210                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3211
3212         svif_info = rte_le_to_cpu_16(resp->svif_info);
3213         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3214                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3215
3216         HWRM_UNLOCK();
3217
3218         return rc;
3219 }
3220
3221 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3222 {
3223         struct hwrm_port_mac_qcfg_input req = {0};
3224         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3225         uint16_t port_svif_info;
3226         int rc;
3227
3228         bp->port_svif = BNXT_SVIF_INVALID;
3229
3230         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3231                 return 0;
3232
3233         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3234
3235         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3236
3237         HWRM_CHECK_RESULT_SILENT();
3238
3239         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3240         if (port_svif_info &
3241             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3242                 bp->port_svif = port_svif_info &
3243                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3244
3245         HWRM_UNLOCK();
3246
3247         return 0;
3248 }
3249
3250 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
3251                                    struct hwrm_func_qcaps_output *qcaps)
3252 {
3253         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
3254         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
3255                sizeof(qcaps->mac_address));
3256         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
3257         qcaps->max_rx_rings = fcfg->num_rx_rings;
3258         qcaps->max_tx_rings = fcfg->num_tx_rings;
3259         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
3260         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
3261         qcaps->max_vfs = 0;
3262         qcaps->first_vf_id = 0;
3263         qcaps->max_vnics = fcfg->num_vnics;
3264         qcaps->max_decap_records = 0;
3265         qcaps->max_encap_records = 0;
3266         qcaps->max_tx_wm_flows = 0;
3267         qcaps->max_tx_em_flows = 0;
3268         qcaps->max_rx_wm_flows = 0;
3269         qcaps->max_rx_em_flows = 0;
3270         qcaps->max_flow_id = 0;
3271         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
3272         qcaps->max_sp_tx_rings = 0;
3273         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3274 }
3275
3276 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3277 {
3278         struct hwrm_func_cfg_input req = {0};
3279         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3280         uint32_t enables;
3281         int rc;
3282
3283         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3284                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3285                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3286                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3287                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3288                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3289                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3290                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3291                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3292
3293         if (BNXT_HAS_RING_GRPS(bp)) {
3294                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3295                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3296         } else if (BNXT_HAS_NQ(bp)) {
3297                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3298                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3299         }
3300
3301         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3302         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3303         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3304         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3305         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3306         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3307         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3308         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3309         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3310         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3311         req.fid = rte_cpu_to_le_16(0xffff);
3312         req.enables = rte_cpu_to_le_32(enables);
3313
3314         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3315
3316         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3317
3318         HWRM_CHECK_RESULT();
3319         HWRM_UNLOCK();
3320
3321         return rc;
3322 }
3323
3324 static void populate_vf_func_cfg_req(struct bnxt *bp,
3325                                      struct hwrm_func_cfg_input *req,
3326                                      int num_vfs)
3327 {
3328         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3329                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3330                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3331                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3332                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3333                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3334                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3335                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3336                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3337                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3338
3339         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3340                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3341                                     BNXT_NUM_VLANS);
3342         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3343         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3344                                                 (num_vfs + 1));
3345         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3346         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3347                                                (num_vfs + 1));
3348         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3349         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3350         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3351         /* TODO: For now, do not support VMDq/RFS on VFs. */
3352         req->num_vnics = rte_cpu_to_le_16(1);
3353         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3354                                                  (num_vfs + 1));
3355 }
3356
3357 static void add_random_mac_if_needed(struct bnxt *bp,
3358                                      struct hwrm_func_cfg_input *cfg_req,
3359                                      int vf)
3360 {
3361         struct rte_ether_addr mac;
3362
3363         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3364                 return;
3365
3366         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3367                 cfg_req->enables |=
3368                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3369                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3370                 bp->pf->vf_info[vf].random_mac = true;
3371         } else {
3372                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3373                         RTE_ETHER_ADDR_LEN);
3374         }
3375 }
3376
3377 static int reserve_resources_from_vf(struct bnxt *bp,
3378                                      struct hwrm_func_cfg_input *cfg_req,
3379                                      int vf)
3380 {
3381         struct hwrm_func_qcaps_input req = {0};
3382         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3383         int rc;
3384
3385         /* Get the actual allocated values now */
3386         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3387         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3388         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3389
3390         if (rc) {
3391                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3392                 copy_func_cfg_to_qcaps(cfg_req, resp);
3393         } else if (resp->error_code) {
3394                 rc = rte_le_to_cpu_16(resp->error_code);
3395                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3396                 copy_func_cfg_to_qcaps(cfg_req, resp);
3397         }
3398
3399         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3400         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3401         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3402         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3403         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3404         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3405         /*
3406          * TODO: While not supporting VMDq with VFs, max_vnics is always
3407          * forced to 1 in this case
3408          */
3409         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3410         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3411
3412         HWRM_UNLOCK();
3413
3414         return 0;
3415 }
3416
3417 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3418 {
3419         struct hwrm_func_qcfg_input req = {0};
3420         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3421         int rc;
3422
3423         /* Check for zero MAC address */
3424         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3425         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3426         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3427         HWRM_CHECK_RESULT();
3428         rc = rte_le_to_cpu_16(resp->vlan);
3429
3430         HWRM_UNLOCK();
3431
3432         return rc;
3433 }
3434
3435 static int update_pf_resource_max(struct bnxt *bp)
3436 {
3437         struct hwrm_func_qcfg_input req = {0};
3438         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3439         int rc;
3440
3441         /* And copy the allocated numbers into the pf struct */
3442         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3443         req.fid = rte_cpu_to_le_16(0xffff);
3444         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3445         HWRM_CHECK_RESULT();
3446
3447         /* Only TX ring value reflects actual allocation? TODO */
3448         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3449         bp->pf->evb_mode = resp->evb_mode;
3450
3451         HWRM_UNLOCK();
3452
3453         return rc;
3454 }
3455
3456 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3457 {
3458         int rc;
3459
3460         if (!BNXT_PF(bp)) {
3461                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3462                 return -EINVAL;
3463         }
3464
3465         rc = bnxt_hwrm_func_qcaps(bp);
3466         if (rc)
3467                 return rc;
3468
3469         bp->pf->func_cfg_flags &=
3470                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3471                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3472         bp->pf->func_cfg_flags |=
3473                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3474         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3475         rc = __bnxt_hwrm_func_qcaps(bp);
3476         return rc;
3477 }
3478
3479 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3480 {
3481         struct hwrm_func_cfg_input req = {0};
3482         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3483         int i;
3484         size_t sz;
3485         int rc = 0;
3486         size_t req_buf_sz;
3487
3488         if (!BNXT_PF(bp)) {
3489                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3490                 return -EINVAL;
3491         }
3492
3493         rc = bnxt_hwrm_func_qcaps(bp);
3494
3495         if (rc)
3496                 return rc;
3497
3498         bp->pf->active_vfs = num_vfs;
3499
3500         /*
3501          * First, configure the PF to only use one TX ring.  This ensures that
3502          * there are enough rings for all VFs.
3503          *
3504          * If we don't do this, when we call func_alloc() later, we will lock
3505          * extra rings to the PF that won't be available during func_cfg() of
3506          * the VFs.
3507          *
3508          * This has been fixed with firmware versions above 20.6.54
3509          */
3510         bp->pf->func_cfg_flags &=
3511                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3512                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3513         bp->pf->func_cfg_flags |=
3514                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3515         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3516         if (rc)
3517                 return rc;
3518
3519         /*
3520          * Now, create and register a buffer to hold forwarded VF requests
3521          */
3522         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3523         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3524                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3525         if (bp->pf->vf_req_buf == NULL) {
3526                 rc = -ENOMEM;
3527                 goto error_free;
3528         }
3529         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3530                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3531         for (i = 0; i < num_vfs; i++)
3532                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3533                                         (i * HWRM_MAX_REQ_LEN);
3534
3535         rc = bnxt_hwrm_func_buf_rgtr(bp);
3536         if (rc)
3537                 goto error_free;
3538
3539         populate_vf_func_cfg_req(bp, &req, num_vfs);
3540
3541         bp->pf->active_vfs = 0;
3542         for (i = 0; i < num_vfs; i++) {
3543                 add_random_mac_if_needed(bp, &req, i);
3544
3545                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3546                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3547                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3548                 rc = bnxt_hwrm_send_message(bp,
3549                                             &req,
3550                                             sizeof(req),
3551                                             BNXT_USE_CHIMP_MB);
3552
3553                 /* Clear enable flag for next pass */
3554                 req.enables &= ~rte_cpu_to_le_32(
3555                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3556
3557                 if (rc || resp->error_code) {
3558                         PMD_DRV_LOG(ERR,
3559                                 "Failed to initizlie VF %d\n", i);
3560                         PMD_DRV_LOG(ERR,
3561                                 "Not all VFs available. (%d, %d)\n",
3562                                 rc, resp->error_code);
3563                         HWRM_UNLOCK();
3564                         break;
3565                 }
3566
3567                 HWRM_UNLOCK();
3568
3569                 reserve_resources_from_vf(bp, &req, i);
3570                 bp->pf->active_vfs++;
3571                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3572         }
3573
3574         /*
3575          * Now configure the PF to use "the rest" of the resources
3576          * We're using STD_TX_RING_MODE here though which will limit the TX
3577          * rings.  This will allow QoS to function properly.  Not setting this
3578          * will cause PF rings to break bandwidth settings.
3579          */
3580         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3581         if (rc)
3582                 goto error_free;
3583
3584         rc = update_pf_resource_max(bp);
3585         if (rc)
3586                 goto error_free;
3587
3588         return rc;
3589
3590 error_free:
3591         bnxt_hwrm_func_buf_unrgtr(bp);
3592         return rc;
3593 }
3594
3595 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3596 {
3597         struct hwrm_func_cfg_input req = {0};
3598         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3599         int rc;
3600
3601         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3602
3603         req.fid = rte_cpu_to_le_16(0xffff);
3604         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3605         req.evb_mode = bp->pf->evb_mode;
3606
3607         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3608         HWRM_CHECK_RESULT();
3609         HWRM_UNLOCK();
3610
3611         return rc;
3612 }
3613
3614 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3615                                 uint8_t tunnel_type)
3616 {
3617         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3618         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3619         int rc = 0;
3620
3621         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3622         req.tunnel_type = tunnel_type;
3623         req.tunnel_dst_port_val = port;
3624         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3625         HWRM_CHECK_RESULT();
3626
3627         switch (tunnel_type) {
3628         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3629                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3630                 bp->vxlan_port = port;
3631                 break;
3632         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3633                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3634                 bp->geneve_port = port;
3635                 break;
3636         default:
3637                 break;
3638         }
3639
3640         HWRM_UNLOCK();
3641
3642         return rc;
3643 }
3644
3645 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3646                                 uint8_t tunnel_type)
3647 {
3648         struct hwrm_tunnel_dst_port_free_input req = {0};
3649         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3650         int rc = 0;
3651
3652         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3653
3654         req.tunnel_type = tunnel_type;
3655         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3656         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3657
3658         HWRM_CHECK_RESULT();
3659         HWRM_UNLOCK();
3660
3661         return rc;
3662 }
3663
3664 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3665                                         uint32_t flags)
3666 {
3667         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3668         struct hwrm_func_cfg_input req = {0};
3669         int rc;
3670
3671         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3672
3673         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3674         req.flags = rte_cpu_to_le_32(flags);
3675         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3676
3677         HWRM_CHECK_RESULT();
3678         HWRM_UNLOCK();
3679
3680         return rc;
3681 }
3682
3683 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3684 {
3685         uint32_t *flag = flagp;
3686
3687         vnic->flags = *flag;
3688 }
3689
3690 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3691 {
3692         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3693 }
3694
3695 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3696 {
3697         int rc = 0;
3698         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3699         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3700
3701         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3702
3703         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3704         req.req_buf_page_size = rte_cpu_to_le_16(
3705                          page_getenum(bp->pf->active_vfs * HWRM_MAX_REQ_LEN));
3706         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3707         req.req_buf_page_addr0 =
3708                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3709         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3710                 PMD_DRV_LOG(ERR,
3711                         "unable to map buffer address to physical memory\n");
3712                 return -ENOMEM;
3713         }
3714
3715         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3716
3717         HWRM_CHECK_RESULT();
3718         HWRM_UNLOCK();
3719
3720         return rc;
3721 }
3722
3723 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3724 {
3725         int rc = 0;
3726         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3727         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3728
3729         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3730                 return 0;
3731
3732         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3733
3734         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3735
3736         HWRM_CHECK_RESULT();
3737         HWRM_UNLOCK();
3738
3739         return rc;
3740 }
3741
3742 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3743 {
3744         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3745         struct hwrm_func_cfg_input req = {0};
3746         int rc;
3747
3748         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3749
3750         req.fid = rte_cpu_to_le_16(0xffff);
3751         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3752         req.enables = rte_cpu_to_le_32(
3753                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3754         req.async_event_cr = rte_cpu_to_le_16(
3755                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3756         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3757
3758         HWRM_CHECK_RESULT();
3759         HWRM_UNLOCK();
3760
3761         return rc;
3762 }
3763
3764 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3765 {
3766         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3767         struct hwrm_func_vf_cfg_input req = {0};
3768         int rc;
3769
3770         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3771
3772         req.enables = rte_cpu_to_le_32(
3773                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3774         req.async_event_cr = rte_cpu_to_le_16(
3775                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3776         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3777
3778         HWRM_CHECK_RESULT();
3779         HWRM_UNLOCK();
3780
3781         return rc;
3782 }
3783
3784 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3785 {
3786         struct hwrm_func_cfg_input req = {0};
3787         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3788         uint16_t dflt_vlan, fid;
3789         uint32_t func_cfg_flags;
3790         int rc = 0;
3791
3792         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3793
3794         if (is_vf) {
3795                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
3796                 fid = bp->pf->vf_info[vf].fid;
3797                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
3798         } else {
3799                 fid = rte_cpu_to_le_16(0xffff);
3800                 func_cfg_flags = bp->pf->func_cfg_flags;
3801                 dflt_vlan = bp->vlan;
3802         }
3803
3804         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3805         req.fid = rte_cpu_to_le_16(fid);
3806         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3807         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3808
3809         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3810
3811         HWRM_CHECK_RESULT();
3812         HWRM_UNLOCK();
3813
3814         return rc;
3815 }
3816
3817 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3818                         uint16_t max_bw, uint16_t enables)
3819 {
3820         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3821         struct hwrm_func_cfg_input req = {0};
3822         int rc;
3823
3824         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3825
3826         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3827         req.enables |= rte_cpu_to_le_32(enables);
3828         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3829         req.max_bw = rte_cpu_to_le_32(max_bw);
3830         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3831
3832         HWRM_CHECK_RESULT();
3833         HWRM_UNLOCK();
3834
3835         return rc;
3836 }
3837
3838 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3839 {
3840         struct hwrm_func_cfg_input req = {0};
3841         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3842         int rc = 0;
3843
3844         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3845
3846         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3847         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3848         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3849         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
3850
3851         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3852
3853         HWRM_CHECK_RESULT();
3854         HWRM_UNLOCK();
3855
3856         return rc;
3857 }
3858
3859 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3860 {
3861         int rc;
3862
3863         if (BNXT_PF(bp))
3864                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3865         else
3866                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3867
3868         return rc;
3869 }
3870
3871 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3872                               void *encaped, size_t ec_size)
3873 {
3874         int rc = 0;
3875         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3876         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3877
3878         if (ec_size > sizeof(req.encap_request))
3879                 return -1;
3880
3881         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3882
3883         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3884         memcpy(req.encap_request, encaped, ec_size);
3885
3886         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3887
3888         HWRM_CHECK_RESULT();
3889         HWRM_UNLOCK();
3890
3891         return rc;
3892 }
3893
3894 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3895                                        struct rte_ether_addr *mac)
3896 {
3897         struct hwrm_func_qcfg_input req = {0};
3898         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3899         int rc;
3900
3901         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3902
3903         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3904         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3905
3906         HWRM_CHECK_RESULT();
3907
3908         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3909
3910         HWRM_UNLOCK();
3911
3912         return rc;
3913 }
3914
3915 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3916                             void *encaped, size_t ec_size)
3917 {
3918         int rc = 0;
3919         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3920         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3921
3922         if (ec_size > sizeof(req.encap_request))
3923                 return -1;
3924
3925         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3926
3927         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3928         memcpy(req.encap_request, encaped, ec_size);
3929
3930         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3931
3932         HWRM_CHECK_RESULT();
3933         HWRM_UNLOCK();
3934
3935         return rc;
3936 }
3937
3938 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3939                          struct rte_eth_stats *stats, uint8_t rx)
3940 {
3941         int rc = 0;
3942         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3943         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3944
3945         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3946
3947         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3948
3949         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3950
3951         HWRM_CHECK_RESULT();
3952
3953         if (rx) {
3954                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3955                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3956                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3957                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3958                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3959                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3960                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3961                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3962         } else {
3963                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3964                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3965                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3966                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3967                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3968                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3969         }
3970
3971         HWRM_UNLOCK();
3972
3973         return rc;
3974 }
3975
3976 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3977 {
3978         struct hwrm_port_qstats_input req = {0};
3979         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3980         struct bnxt_pf_info *pf = bp->pf;
3981         int rc;
3982
3983         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
3984
3985         req.port_id = rte_cpu_to_le_16(pf->port_id);
3986         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3987         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3988         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3989
3990         HWRM_CHECK_RESULT();
3991         HWRM_UNLOCK();
3992
3993         return rc;
3994 }
3995
3996 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3997 {
3998         struct hwrm_port_clr_stats_input req = {0};
3999         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4000         struct bnxt_pf_info *pf = bp->pf;
4001         int rc;
4002
4003         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4004         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4005             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4006                 return 0;
4007
4008         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4009
4010         req.port_id = rte_cpu_to_le_16(pf->port_id);
4011         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4012
4013         HWRM_CHECK_RESULT();
4014         HWRM_UNLOCK();
4015
4016         return rc;
4017 }
4018
4019 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4020 {
4021         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4022         struct hwrm_port_led_qcaps_input req = {0};
4023         int rc;
4024
4025         if (BNXT_VF(bp))
4026                 return 0;
4027
4028         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4029         req.port_id = bp->pf->port_id;
4030         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4031
4032         HWRM_CHECK_RESULT();
4033
4034         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4035                 unsigned int i;
4036
4037                 bp->leds->num_leds = resp->num_leds;
4038                 memcpy(bp->leds, &resp->led0_id,
4039                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4040                 for (i = 0; i < bp->leds->num_leds; i++) {
4041                         struct bnxt_led_info *led = &bp->leds[i];
4042
4043                         uint16_t caps = led->led_state_caps;
4044
4045                         if (!led->led_group_id ||
4046                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4047                                 bp->leds->num_leds = 0;
4048                                 break;
4049                         }
4050                 }
4051         }
4052
4053         HWRM_UNLOCK();
4054
4055         return rc;
4056 }
4057
4058 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4059 {
4060         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4061         struct hwrm_port_led_cfg_input req = {0};
4062         struct bnxt_led_cfg *led_cfg;
4063         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4064         uint16_t duration = 0;
4065         int rc, i;
4066
4067         if (!bp->leds->num_leds || BNXT_VF(bp))
4068                 return -EOPNOTSUPP;
4069
4070         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4071
4072         if (led_on) {
4073                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4074                 duration = rte_cpu_to_le_16(500);
4075         }
4076         req.port_id = bp->pf->port_id;
4077         req.num_leds = bp->leds->num_leds;
4078         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4079         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4080                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4081                 led_cfg->led_id = bp->leds[i].led_id;
4082                 led_cfg->led_state = led_state;
4083                 led_cfg->led_blink_on = duration;
4084                 led_cfg->led_blink_off = duration;
4085                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4086         }
4087
4088         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4089
4090         HWRM_CHECK_RESULT();
4091         HWRM_UNLOCK();
4092
4093         return rc;
4094 }
4095
4096 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4097                                uint32_t *length)
4098 {
4099         int rc;
4100         struct hwrm_nvm_get_dir_info_input req = {0};
4101         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4102
4103         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4104
4105         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4106
4107         HWRM_CHECK_RESULT();
4108
4109         *entries = rte_le_to_cpu_32(resp->entries);
4110         *length = rte_le_to_cpu_32(resp->entry_length);
4111
4112         HWRM_UNLOCK();
4113         return rc;
4114 }
4115
4116 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4117 {
4118         int rc;
4119         uint32_t dir_entries;
4120         uint32_t entry_length;
4121         uint8_t *buf;
4122         size_t buflen;
4123         rte_iova_t dma_handle;
4124         struct hwrm_nvm_get_dir_entries_input req = {0};
4125         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4126
4127         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4128         if (rc != 0)
4129                 return rc;
4130
4131         *data++ = dir_entries;
4132         *data++ = entry_length;
4133         len -= 2;
4134         memset(data, 0xff, len);
4135
4136         buflen = dir_entries * entry_length;
4137         buf = rte_malloc("nvm_dir", buflen, 0);
4138         if (buf == NULL)
4139                 return -ENOMEM;
4140         dma_handle = rte_malloc_virt2iova(buf);
4141         if (dma_handle == RTE_BAD_IOVA) {
4142                 PMD_DRV_LOG(ERR,
4143                         "unable to map response address to physical memory\n");
4144                 return -ENOMEM;
4145         }
4146         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4147         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4148         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4149
4150         if (rc == 0)
4151                 memcpy(data, buf, len > buflen ? buflen : len);
4152
4153         rte_free(buf);
4154         HWRM_CHECK_RESULT();
4155         HWRM_UNLOCK();
4156
4157         return rc;
4158 }
4159
4160 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4161                              uint32_t offset, uint32_t length,
4162                              uint8_t *data)
4163 {
4164         int rc;
4165         uint8_t *buf;
4166         rte_iova_t dma_handle;
4167         struct hwrm_nvm_read_input req = {0};
4168         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4169
4170         buf = rte_malloc("nvm_item", length, 0);
4171         if (!buf)
4172                 return -ENOMEM;
4173
4174         dma_handle = rte_malloc_virt2iova(buf);
4175         if (dma_handle == RTE_BAD_IOVA) {
4176                 PMD_DRV_LOG(ERR,
4177                         "unable to map response address to physical memory\n");
4178                 return -ENOMEM;
4179         }
4180         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4181         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4182         req.dir_idx = rte_cpu_to_le_16(index);
4183         req.offset = rte_cpu_to_le_32(offset);
4184         req.len = rte_cpu_to_le_32(length);
4185         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4186         if (rc == 0)
4187                 memcpy(data, buf, length);
4188
4189         rte_free(buf);
4190         HWRM_CHECK_RESULT();
4191         HWRM_UNLOCK();
4192
4193         return rc;
4194 }
4195
4196 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4197 {
4198         int rc;
4199         struct hwrm_nvm_erase_dir_entry_input req = {0};
4200         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4201
4202         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4203         req.dir_idx = rte_cpu_to_le_16(index);
4204         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4205         HWRM_CHECK_RESULT();
4206         HWRM_UNLOCK();
4207
4208         return rc;
4209 }
4210
4211
4212 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4213                           uint16_t dir_ordinal, uint16_t dir_ext,
4214                           uint16_t dir_attr, const uint8_t *data,
4215                           size_t data_len)
4216 {
4217         int rc;
4218         struct hwrm_nvm_write_input req = {0};
4219         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4220         rte_iova_t dma_handle;
4221         uint8_t *buf;
4222
4223         buf = rte_malloc("nvm_write", data_len, 0);
4224         if (!buf)
4225                 return -ENOMEM;
4226
4227         dma_handle = rte_malloc_virt2iova(buf);
4228         if (dma_handle == RTE_BAD_IOVA) {
4229                 PMD_DRV_LOG(ERR,
4230                         "unable to map response address to physical memory\n");
4231                 return -ENOMEM;
4232         }
4233         memcpy(buf, data, data_len);
4234
4235         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4236
4237         req.dir_type = rte_cpu_to_le_16(dir_type);
4238         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4239         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4240         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4241         req.dir_data_length = rte_cpu_to_le_32(data_len);
4242         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4243
4244         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4245
4246         rte_free(buf);
4247         HWRM_CHECK_RESULT();
4248         HWRM_UNLOCK();
4249
4250         return rc;
4251 }
4252
4253 static void
4254 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4255 {
4256         uint32_t *count = cbdata;
4257
4258         *count = *count + 1;
4259 }
4260
4261 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4262                                      struct bnxt_vnic_info *vnic __rte_unused)
4263 {
4264         return 0;
4265 }
4266
4267 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4268 {
4269         uint32_t count = 0;
4270
4271         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4272             &count, bnxt_vnic_count_hwrm_stub);
4273
4274         return count;
4275 }
4276
4277 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4278                                         uint16_t *vnic_ids)
4279 {
4280         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4281         struct hwrm_func_vf_vnic_ids_query_output *resp =
4282                                                 bp->hwrm_cmd_resp_addr;
4283         int rc;
4284
4285         /* First query all VNIC ids */
4286         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4287
4288         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4289         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4290         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4291
4292         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4293                 HWRM_UNLOCK();
4294                 PMD_DRV_LOG(ERR,
4295                 "unable to map VNIC ID table address to physical memory\n");
4296                 return -ENOMEM;
4297         }
4298         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4299         HWRM_CHECK_RESULT();
4300         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4301
4302         HWRM_UNLOCK();
4303
4304         return rc;
4305 }
4306
4307 /*
4308  * This function queries the VNIC IDs  for a specified VF. It then calls
4309  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4310  * Then it calls the hwrm_cb function to program this new vnic configuration.
4311  */
4312 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4313         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4314         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4315 {
4316         struct bnxt_vnic_info vnic;
4317         int rc = 0;
4318         int i, num_vnic_ids;
4319         uint16_t *vnic_ids;
4320         size_t vnic_id_sz;
4321         size_t sz;
4322
4323         /* First query all VNIC ids */
4324         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4325         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4326                         RTE_CACHE_LINE_SIZE);
4327         if (vnic_ids == NULL)
4328                 return -ENOMEM;
4329
4330         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4331                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4332
4333         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4334
4335         if (num_vnic_ids < 0)
4336                 return num_vnic_ids;
4337
4338         /* Retrieve VNIC, update bd_stall then update */
4339
4340         for (i = 0; i < num_vnic_ids; i++) {
4341                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4342                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4343                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4344                 if (rc)
4345                         break;
4346                 if (vnic.mru <= 4)      /* Indicates unallocated */
4347                         continue;
4348
4349                 vnic_cb(&vnic, cbdata);
4350
4351                 rc = hwrm_cb(bp, &vnic);
4352                 if (rc)
4353                         break;
4354         }
4355
4356         rte_free(vnic_ids);
4357
4358         return rc;
4359 }
4360
4361 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4362                                               bool on)
4363 {
4364         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4365         struct hwrm_func_cfg_input req = {0};
4366         int rc;
4367
4368         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4369
4370         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4371         req.enables |= rte_cpu_to_le_32(
4372                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4373         req.vlan_antispoof_mode = on ?
4374                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4375                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4376         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4377
4378         HWRM_CHECK_RESULT();
4379         HWRM_UNLOCK();
4380
4381         return rc;
4382 }
4383
4384 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4385 {
4386         struct bnxt_vnic_info vnic;
4387         uint16_t *vnic_ids;
4388         size_t vnic_id_sz;
4389         int num_vnic_ids, i;
4390         size_t sz;
4391         int rc;
4392
4393         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4394         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4395                         RTE_CACHE_LINE_SIZE);
4396         if (vnic_ids == NULL)
4397                 return -ENOMEM;
4398
4399         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4400                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4401
4402         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4403         if (rc <= 0)
4404                 goto exit;
4405         num_vnic_ids = rc;
4406
4407         /*
4408          * Loop through to find the default VNIC ID.
4409          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4410          * by sending the hwrm_func_qcfg command to the firmware.
4411          */
4412         for (i = 0; i < num_vnic_ids; i++) {
4413                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4414                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4415                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4416                                         bp->pf->first_vf_id + vf);
4417                 if (rc)
4418                         goto exit;
4419                 if (vnic.func_default) {
4420                         rte_free(vnic_ids);
4421                         return vnic.fw_vnic_id;
4422                 }
4423         }
4424         /* Could not find a default VNIC. */
4425         PMD_DRV_LOG(ERR, "No default VNIC\n");
4426 exit:
4427         rte_free(vnic_ids);
4428         return rc;
4429 }
4430
4431 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4432                          uint16_t dst_id,
4433                          struct bnxt_filter_info *filter)
4434 {
4435         int rc = 0;
4436         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4437         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4438         uint32_t enables = 0;
4439
4440         if (filter->fw_em_filter_id != UINT64_MAX)
4441                 bnxt_hwrm_clear_em_filter(bp, filter);
4442
4443         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4444
4445         req.flags = rte_cpu_to_le_32(filter->flags);
4446
4447         enables = filter->enables |
4448               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4449         req.dst_id = rte_cpu_to_le_16(dst_id);
4450
4451         if (filter->ip_addr_type) {
4452                 req.ip_addr_type = filter->ip_addr_type;
4453                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4454         }
4455         if (enables &
4456             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4457                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4458         if (enables &
4459             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4460                 memcpy(req.src_macaddr, filter->src_macaddr,
4461                        RTE_ETHER_ADDR_LEN);
4462         if (enables &
4463             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4464                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4465                        RTE_ETHER_ADDR_LEN);
4466         if (enables &
4467             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4468                 req.ovlan_vid = filter->l2_ovlan;
4469         if (enables &
4470             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4471                 req.ivlan_vid = filter->l2_ivlan;
4472         if (enables &
4473             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4474                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4475         if (enables &
4476             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4477                 req.ip_protocol = filter->ip_protocol;
4478         if (enables &
4479             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4480                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4481         if (enables &
4482             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4483                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4484         if (enables &
4485             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4486                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4487         if (enables &
4488             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4489                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4490         if (enables &
4491             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4492                 req.mirror_vnic_id = filter->mirror_vnic_id;
4493
4494         req.enables = rte_cpu_to_le_32(enables);
4495
4496         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4497
4498         HWRM_CHECK_RESULT();
4499
4500         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4501         HWRM_UNLOCK();
4502
4503         return rc;
4504 }
4505
4506 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4507 {
4508         int rc = 0;
4509         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4510         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4511
4512         if (filter->fw_em_filter_id == UINT64_MAX)
4513                 return 0;
4514
4515         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4516
4517         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4518
4519         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4520
4521         HWRM_CHECK_RESULT();
4522         HWRM_UNLOCK();
4523
4524         filter->fw_em_filter_id = UINT64_MAX;
4525         filter->fw_l2_filter_id = UINT64_MAX;
4526
4527         return 0;
4528 }
4529
4530 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4531                          uint16_t dst_id,
4532                          struct bnxt_filter_info *filter)
4533 {
4534         int rc = 0;
4535         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4536         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4537                                                 bp->hwrm_cmd_resp_addr;
4538         uint32_t enables = 0;
4539
4540         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4541                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4542
4543         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4544
4545         req.flags = rte_cpu_to_le_32(filter->flags);
4546
4547         enables = filter->enables |
4548               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4549         req.dst_id = rte_cpu_to_le_16(dst_id);
4550
4551         if (filter->ip_addr_type) {
4552                 req.ip_addr_type = filter->ip_addr_type;
4553                 enables |=
4554                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4555         }
4556         if (enables &
4557             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4558                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4559         if (enables &
4560             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4561                 memcpy(req.src_macaddr, filter->src_macaddr,
4562                        RTE_ETHER_ADDR_LEN);
4563         if (enables &
4564             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4565                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4566         if (enables &
4567             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4568                 req.ip_protocol = filter->ip_protocol;
4569         if (enables &
4570             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4571                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4572         if (enables &
4573             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4574                 req.src_ipaddr_mask[0] =
4575                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4576         if (enables &
4577             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4578                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4579         if (enables &
4580             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4581                 req.dst_ipaddr_mask[0] =
4582                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4583         if (enables &
4584             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4585                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4586         if (enables &
4587             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4588                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4589         if (enables &
4590             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4591                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4592         if (enables &
4593             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4594                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4595         if (enables &
4596             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4597                 req.mirror_vnic_id = filter->mirror_vnic_id;
4598
4599         req.enables = rte_cpu_to_le_32(enables);
4600
4601         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4602
4603         HWRM_CHECK_RESULT();
4604
4605         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4606         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4607         HWRM_UNLOCK();
4608
4609         return rc;
4610 }
4611
4612 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4613                                 struct bnxt_filter_info *filter)
4614 {
4615         int rc = 0;
4616         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4617         struct hwrm_cfa_ntuple_filter_free_output *resp =
4618                                                 bp->hwrm_cmd_resp_addr;
4619
4620         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4621                 return 0;
4622
4623         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4624
4625         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4626
4627         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4628
4629         HWRM_CHECK_RESULT();
4630         HWRM_UNLOCK();
4631
4632         filter->fw_ntuple_filter_id = UINT64_MAX;
4633
4634         return 0;
4635 }
4636
4637 static int
4638 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4639 {
4640         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4641         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4642         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4643         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4644         uint16_t *ring_tbl = vnic->rss_table;
4645         int nr_ctxs = vnic->num_lb_ctxts;
4646         int max_rings = bp->rx_nr_rings;
4647         int i, j, k, cnt;
4648         int rc = 0;
4649
4650         for (i = 0, k = 0; i < nr_ctxs; i++) {
4651                 struct bnxt_rx_ring_info *rxr;
4652                 struct bnxt_cp_ring_info *cpr;
4653
4654                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4655
4656                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4657                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4658                 req.hash_mode_flags = vnic->hash_mode;
4659
4660                 req.ring_grp_tbl_addr =
4661                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4662                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4663                                      2 * sizeof(*ring_tbl));
4664                 req.hash_key_tbl_addr =
4665                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4666
4667                 req.ring_table_pair_index = i;
4668                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4669
4670                 for (j = 0; j < 64; j++) {
4671                         uint16_t ring_id;
4672
4673                         /* Find next active ring. */
4674                         for (cnt = 0; cnt < max_rings; cnt++) {
4675                                 if (rx_queue_state[k] !=
4676                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4677                                         break;
4678                                 if (++k == max_rings)
4679                                         k = 0;
4680                         }
4681
4682                         /* Return if no rings are active. */
4683                         if (cnt == max_rings) {
4684                                 HWRM_UNLOCK();
4685                                 return 0;
4686                         }
4687
4688                         /* Add rx/cp ring pair to RSS table. */
4689                         rxr = rxqs[k]->rx_ring;
4690                         cpr = rxqs[k]->cp_ring;
4691
4692                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4693                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4694                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4695                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4696
4697                         if (++k == max_rings)
4698                                 k = 0;
4699                 }
4700                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4701                                             BNXT_USE_CHIMP_MB);
4702
4703                 HWRM_CHECK_RESULT();
4704                 HWRM_UNLOCK();
4705         }
4706
4707         return rc;
4708 }
4709
4710 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4711 {
4712         unsigned int rss_idx, fw_idx, i;
4713
4714         if (!(vnic->rss_table && vnic->hash_type))
4715                 return 0;
4716
4717         if (BNXT_CHIP_THOR(bp))
4718                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4719
4720         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4721                 return 0;
4722
4723         if (vnic->rss_table && vnic->hash_type) {
4724                 /*
4725                  * Fill the RSS hash & redirection table with
4726                  * ring group ids for all VNICs
4727                  */
4728                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4729                         rss_idx++, fw_idx++) {
4730                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4731                                 fw_idx %= bp->rx_cp_nr_rings;
4732                                 if (vnic->fw_grp_ids[fw_idx] !=
4733                                     INVALID_HW_RING_ID)
4734                                         break;
4735                                 fw_idx++;
4736                         }
4737                         if (i == bp->rx_cp_nr_rings)
4738                                 return 0;
4739                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4740                 }
4741                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4742         }
4743
4744         return 0;
4745 }
4746
4747 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4748         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4749 {
4750         uint16_t flags;
4751
4752         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4753
4754         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4755         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4756
4757         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4758         req->num_cmpl_dma_aggr_during_int =
4759                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4760
4761         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4762
4763         /* min timer set to 1/2 of interrupt timer */
4764         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4765
4766         /* buf timer set to 1/4 of interrupt timer */
4767         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4768
4769         req->cmpl_aggr_dma_tmr_during_int =
4770                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4771
4772         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4773                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4774         req->flags = rte_cpu_to_le_16(flags);
4775 }
4776
4777 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4778                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4779 {
4780         struct hwrm_ring_aggint_qcaps_input req = {0};
4781         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4782         uint32_t enables;
4783         uint16_t flags;
4784         int rc;
4785
4786         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4787         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4788         HWRM_CHECK_RESULT();
4789
4790         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4791         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4792
4793         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4794                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4795         agg_req->flags = rte_cpu_to_le_16(flags);
4796         enables =
4797          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4798          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4799         agg_req->enables = rte_cpu_to_le_32(enables);
4800
4801         HWRM_UNLOCK();
4802         return rc;
4803 }
4804
4805 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4806                         struct bnxt_coal *coal, uint16_t ring_id)
4807 {
4808         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4809         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4810                                                 bp->hwrm_cmd_resp_addr;
4811         int rc;
4812
4813         /* Set ring coalesce parameters only for 100G NICs */
4814         if (BNXT_CHIP_THOR(bp)) {
4815                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4816                         return -1;
4817         } else if (bnxt_stratus_device(bp)) {
4818                 bnxt_hwrm_set_coal_params(coal, &req);
4819         } else {
4820                 return 0;
4821         }
4822
4823         HWRM_PREP(&req,
4824                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4825                   BNXT_USE_CHIMP_MB);
4826         req.ring_id = rte_cpu_to_le_16(ring_id);
4827         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4828         HWRM_CHECK_RESULT();
4829         HWRM_UNLOCK();
4830         return 0;
4831 }
4832
4833 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4834 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4835 {
4836         struct hwrm_func_backing_store_qcaps_input req = {0};
4837         struct hwrm_func_backing_store_qcaps_output *resp =
4838                 bp->hwrm_cmd_resp_addr;
4839         struct bnxt_ctx_pg_info *ctx_pg;
4840         struct bnxt_ctx_mem_info *ctx;
4841         int total_alloc_len;
4842         int rc, i, tqm_rings;
4843
4844         if (!BNXT_CHIP_THOR(bp) ||
4845             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4846             BNXT_VF(bp) ||
4847             bp->ctx)
4848                 return 0;
4849
4850         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4851         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4852         HWRM_CHECK_RESULT_SILENT();
4853
4854         total_alloc_len = sizeof(*ctx);
4855         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4856                           RTE_CACHE_LINE_SIZE);
4857         if (!ctx) {
4858                 rc = -ENOMEM;
4859                 goto ctx_err;
4860         }
4861
4862         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4863         ctx->qp_min_qp1_entries =
4864                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4865         ctx->qp_max_l2_entries =
4866                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4867         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4868         ctx->srq_max_l2_entries =
4869                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4870         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4871         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4872         ctx->cq_max_l2_entries =
4873                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4874         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4875         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4876         ctx->vnic_max_vnic_entries =
4877                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4878         ctx->vnic_max_ring_table_entries =
4879                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4880         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4881         ctx->stat_max_entries =
4882                 rte_le_to_cpu_32(resp->stat_max_entries);
4883         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4884         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4885         ctx->tqm_min_entries_per_ring =
4886                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4887         ctx->tqm_max_entries_per_ring =
4888                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4889         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4890         if (!ctx->tqm_entries_multiple)
4891                 ctx->tqm_entries_multiple = 1;
4892         ctx->mrav_max_entries =
4893                 rte_le_to_cpu_32(resp->mrav_max_entries);
4894         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4895         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4896         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4897         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
4898
4899         if (!ctx->tqm_fp_rings_count)
4900                 ctx->tqm_fp_rings_count = bp->max_q;
4901
4902         tqm_rings = ctx->tqm_fp_rings_count + 1;
4903
4904         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4905                             sizeof(*ctx_pg) * tqm_rings,
4906                             RTE_CACHE_LINE_SIZE);
4907         if (!ctx_pg) {
4908                 rc = -ENOMEM;
4909                 goto ctx_err;
4910         }
4911         for (i = 0; i < tqm_rings; i++, ctx_pg++)
4912                 ctx->tqm_mem[i] = ctx_pg;
4913
4914         bp->ctx = ctx;
4915 ctx_err:
4916         HWRM_UNLOCK();
4917         return rc;
4918 }
4919
4920 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4921 {
4922         struct hwrm_func_backing_store_cfg_input req = {0};
4923         struct hwrm_func_backing_store_cfg_output *resp =
4924                 bp->hwrm_cmd_resp_addr;
4925         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4926         struct bnxt_ctx_pg_info *ctx_pg;
4927         uint32_t *num_entries;
4928         uint64_t *pg_dir;
4929         uint8_t *pg_attr;
4930         uint32_t ena;
4931         int i, rc;
4932
4933         if (!ctx)
4934                 return 0;
4935
4936         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4937         req.enables = rte_cpu_to_le_32(enables);
4938
4939         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4940                 ctx_pg = &ctx->qp_mem;
4941                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4942                 req.qp_num_qp1_entries =
4943                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4944                 req.qp_num_l2_entries =
4945                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4946                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4947                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4948                                       &req.qpc_pg_size_qpc_lvl,
4949                                       &req.qpc_page_dir);
4950         }
4951
4952         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4953                 ctx_pg = &ctx->srq_mem;
4954                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4955                 req.srq_num_l2_entries =
4956                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4957                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4958                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4959                                       &req.srq_pg_size_srq_lvl,
4960                                       &req.srq_page_dir);
4961         }
4962
4963         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4964                 ctx_pg = &ctx->cq_mem;
4965                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4966                 req.cq_num_l2_entries =
4967                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4968                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4969                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4970                                       &req.cq_pg_size_cq_lvl,
4971                                       &req.cq_page_dir);
4972         }
4973
4974         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4975                 ctx_pg = &ctx->vnic_mem;
4976                 req.vnic_num_vnic_entries =
4977                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4978                 req.vnic_num_ring_table_entries =
4979                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4980                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4981                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4982                                       &req.vnic_pg_size_vnic_lvl,
4983                                       &req.vnic_page_dir);
4984         }
4985
4986         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4987                 ctx_pg = &ctx->stat_mem;
4988                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4989                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4990                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4991                                       &req.stat_pg_size_stat_lvl,
4992                                       &req.stat_page_dir);
4993         }
4994
4995         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4996         num_entries = &req.tqm_sp_num_entries;
4997         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4998         pg_dir = &req.tqm_sp_page_dir;
4999         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5000         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5001                 if (!(enables & ena))
5002                         continue;
5003
5004                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5005
5006                 ctx_pg = ctx->tqm_mem[i];
5007                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5008                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5009         }
5010
5011         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5012         HWRM_CHECK_RESULT();
5013         HWRM_UNLOCK();
5014
5015         return rc;
5016 }
5017
5018 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5019 {
5020         struct hwrm_port_qstats_ext_input req = {0};
5021         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5022         struct bnxt_pf_info *pf = bp->pf;
5023         int rc;
5024
5025         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5026               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5027                 return 0;
5028
5029         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5030
5031         req.port_id = rte_cpu_to_le_16(pf->port_id);
5032         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5033                 req.tx_stat_host_addr =
5034                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5035                 req.tx_stat_size =
5036                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5037         }
5038         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5039                 req.rx_stat_host_addr =
5040                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5041                 req.rx_stat_size =
5042                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5043         }
5044         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5045
5046         if (rc) {
5047                 bp->fw_rx_port_stats_ext_size = 0;
5048                 bp->fw_tx_port_stats_ext_size = 0;
5049         } else {
5050                 bp->fw_rx_port_stats_ext_size =
5051                         rte_le_to_cpu_16(resp->rx_stat_size);
5052                 bp->fw_tx_port_stats_ext_size =
5053                         rte_le_to_cpu_16(resp->tx_stat_size);
5054         }
5055
5056         HWRM_CHECK_RESULT();
5057         HWRM_UNLOCK();
5058
5059         return rc;
5060 }
5061
5062 int
5063 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5064 {
5065         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5066         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5067                 bp->hwrm_cmd_resp_addr;
5068         int rc = 0;
5069
5070         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5071         req.tunnel_type = type;
5072         req.dest_fid = bp->fw_fid;
5073         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5074         HWRM_CHECK_RESULT();
5075
5076         HWRM_UNLOCK();
5077
5078         return rc;
5079 }
5080
5081 int
5082 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5083 {
5084         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5085         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5086                 bp->hwrm_cmd_resp_addr;
5087         int rc = 0;
5088
5089         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5090         req.tunnel_type = type;
5091         req.dest_fid = bp->fw_fid;
5092         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5093         HWRM_CHECK_RESULT();
5094
5095         HWRM_UNLOCK();
5096
5097         return rc;
5098 }
5099
5100 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5101 {
5102         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5103         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5104                 bp->hwrm_cmd_resp_addr;
5105         int rc = 0;
5106
5107         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5108         req.src_fid = bp->fw_fid;
5109         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5110         HWRM_CHECK_RESULT();
5111
5112         if (type)
5113                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5114
5115         HWRM_UNLOCK();
5116
5117         return rc;
5118 }
5119
5120 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5121                                    uint16_t *dst_fid)
5122 {
5123         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5124         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5125                 bp->hwrm_cmd_resp_addr;
5126         int rc = 0;
5127
5128         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5129         req.src_fid = bp->fw_fid;
5130         req.tunnel_type = tun_type;
5131         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5132         HWRM_CHECK_RESULT();
5133
5134         if (dst_fid)
5135                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5136
5137         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5138
5139         HWRM_UNLOCK();
5140
5141         return rc;
5142 }
5143
5144 int bnxt_hwrm_set_mac(struct bnxt *bp)
5145 {
5146         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5147         struct hwrm_func_vf_cfg_input req = {0};
5148         int rc = 0;
5149
5150         if (!BNXT_VF(bp))
5151                 return 0;
5152
5153         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5154
5155         req.enables =
5156                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5157         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5158
5159         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5160
5161         HWRM_CHECK_RESULT();
5162
5163         HWRM_UNLOCK();
5164
5165         return rc;
5166 }
5167
5168 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5169 {
5170         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5171         struct hwrm_func_drv_if_change_input req = {0};
5172         uint32_t flags;
5173         int rc;
5174
5175         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5176                 return 0;
5177
5178         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5179          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5180          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5181          */
5182         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5183                 return 0;
5184
5185         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5186
5187         if (up)
5188                 req.flags =
5189                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5190
5191         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5192
5193         HWRM_CHECK_RESULT();
5194         flags = rte_le_to_cpu_32(resp->flags);
5195         HWRM_UNLOCK();
5196
5197         if (!up)
5198                 return 0;
5199
5200         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5201                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5202                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5203         }
5204
5205         return 0;
5206 }
5207
5208 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5209 {
5210         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5211         struct bnxt_error_recovery_info *info = bp->recovery_info;
5212         struct hwrm_error_recovery_qcfg_input req = {0};
5213         uint32_t flags = 0;
5214         unsigned int i;
5215         int rc;
5216
5217         /* Older FW does not have error recovery support */
5218         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5219                 return 0;
5220
5221         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5222
5223         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5224
5225         HWRM_CHECK_RESULT();
5226
5227         flags = rte_le_to_cpu_32(resp->flags);
5228         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5229                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5230         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5231                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5232
5233         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5234             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5235                 rc = -EINVAL;
5236                 goto err;
5237         }
5238
5239         /* FW returned values are in units of 100msec */
5240         info->driver_polling_freq =
5241                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5242         info->master_func_wait_period =
5243                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5244         info->normal_func_wait_period =
5245                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5246         info->master_func_wait_period_after_reset =
5247                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5248         info->max_bailout_time_after_reset =
5249                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5250         info->status_regs[BNXT_FW_STATUS_REG] =
5251                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5252         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5253                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5254         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5255                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5256         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5257                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5258         info->reg_array_cnt =
5259                 rte_le_to_cpu_32(resp->reg_array_cnt);
5260
5261         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5262                 rc = -EINVAL;
5263                 goto err;
5264         }
5265
5266         for (i = 0; i < info->reg_array_cnt; i++) {
5267                 info->reset_reg[i] =
5268                         rte_le_to_cpu_32(resp->reset_reg[i]);
5269                 info->reset_reg_val[i] =
5270                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5271                 info->delay_after_reset[i] =
5272                         resp->delay_after_reset[i];
5273         }
5274 err:
5275         HWRM_UNLOCK();
5276
5277         /* Map the FW status registers */
5278         if (!rc)
5279                 rc = bnxt_map_fw_health_status_regs(bp);
5280
5281         if (rc) {
5282                 rte_free(bp->recovery_info);
5283                 bp->recovery_info = NULL;
5284         }
5285         return rc;
5286 }
5287
5288 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5289 {
5290         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5291         struct hwrm_fw_reset_input req = {0};
5292         int rc;
5293
5294         if (!BNXT_PF(bp))
5295                 return -EOPNOTSUPP;
5296
5297         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5298
5299         req.embedded_proc_type =
5300                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5301         req.selfrst_status =
5302                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5303         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5304
5305         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5306                                     BNXT_USE_KONG(bp));
5307
5308         HWRM_CHECK_RESULT();
5309         HWRM_UNLOCK();
5310
5311         return rc;
5312 }
5313
5314 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5315 {
5316         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5317         struct hwrm_port_ts_query_input req = {0};
5318         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5319         uint32_t flags = 0;
5320         int rc;
5321
5322         if (!ptp)
5323                 return 0;
5324
5325         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5326
5327         switch (path) {
5328         case BNXT_PTP_FLAGS_PATH_TX:
5329                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5330                 break;
5331         case BNXT_PTP_FLAGS_PATH_RX:
5332                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5333                 break;
5334         case BNXT_PTP_FLAGS_CURRENT_TIME:
5335                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5336                 break;
5337         }
5338
5339         req.flags = rte_cpu_to_le_32(flags);
5340         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5341
5342         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5343
5344         HWRM_CHECK_RESULT();
5345
5346         if (timestamp) {
5347                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5348                 *timestamp |=
5349                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5350         }
5351         HWRM_UNLOCK();
5352
5353         return rc;
5354 }
5355
5356 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5357 {
5358         int rc = 0;
5359
5360         struct hwrm_cfa_counter_qcaps_input req = {0};
5361         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5362
5363         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5364                 PMD_DRV_LOG(DEBUG,
5365                             "Not a PF or trusted VF. Command not supported\n");
5366                 return 0;
5367         }
5368
5369         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5370         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5371         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5372
5373         HWRM_CHECK_RESULT();
5374         if (max_fc)
5375                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5376         HWRM_UNLOCK();
5377
5378         return 0;
5379 }
5380
5381 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5382 {
5383         int rc = 0;
5384         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5385         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5386
5387         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5388                 PMD_DRV_LOG(DEBUG,
5389                             "Not a PF or trusted VF. Command not supported\n");
5390                 return 0;
5391         }
5392
5393         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5394
5395         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5396         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5397         req.page_dir = rte_cpu_to_le_64(dma_addr);
5398
5399         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5400
5401         HWRM_CHECK_RESULT();
5402         if (ctx_id) {
5403                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5404                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5405         }
5406         HWRM_UNLOCK();
5407
5408         return 0;
5409 }
5410
5411 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5412 {
5413         int rc = 0;
5414         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5415         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5416
5417         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5418                 PMD_DRV_LOG(DEBUG,
5419                             "Not a PF or trusted VF. Command not supported\n");
5420                 return 0;
5421         }
5422
5423         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5424
5425         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5426
5427         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5428
5429         HWRM_CHECK_RESULT();
5430         HWRM_UNLOCK();
5431
5432         return rc;
5433 }
5434
5435 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5436                               uint16_t cntr, uint16_t ctx_id,
5437                               uint32_t num_entries, bool enable)
5438 {
5439         struct hwrm_cfa_counter_cfg_input req = {0};
5440         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5441         uint16_t flags = 0;
5442         int rc;
5443
5444         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5445                 PMD_DRV_LOG(DEBUG,
5446                             "Not a PF or trusted VF. Command not supported\n");
5447                 return 0;
5448         }
5449
5450         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5451
5452         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5453         req.counter_type = rte_cpu_to_le_16(cntr);
5454         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5455                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5456         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5457         if (dir == BNXT_DIR_RX)
5458                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5459         else if (dir == BNXT_DIR_TX)
5460                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5461         req.flags = rte_cpu_to_le_16(flags);
5462         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5463         req.num_entries = rte_cpu_to_le_32(num_entries);
5464
5465         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5466         HWRM_CHECK_RESULT();
5467         HWRM_UNLOCK();
5468
5469         return 0;
5470 }
5471
5472 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5473                                  enum bnxt_flow_dir dir,
5474                                  uint16_t cntr,
5475                                  uint16_t num_entries)
5476 {
5477         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5478         struct hwrm_cfa_counter_qstats_input req = {0};
5479         uint16_t flow_ctx_id = 0;
5480         uint16_t flags = 0;
5481         int rc = 0;
5482
5483         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5484                 PMD_DRV_LOG(DEBUG,
5485                             "Not a PF or trusted VF. Command not supported\n");
5486                 return 0;
5487         }
5488
5489         if (dir == BNXT_DIR_RX) {
5490                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5491                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5492         } else if (dir == BNXT_DIR_TX) {
5493                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5494                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5495         }
5496
5497         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5498         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5499         req.counter_type = rte_cpu_to_le_16(cntr);
5500         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5501         req.num_entries = rte_cpu_to_le_16(num_entries);
5502         req.flags = rte_cpu_to_le_16(flags);
5503         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5504
5505         HWRM_CHECK_RESULT();
5506         HWRM_UNLOCK();
5507
5508         return 0;
5509 }
5510
5511 int bnxt_hwrm_cfa_vfr_alloc(struct bnxt *bp, uint16_t vf_idx)
5512 {
5513         struct hwrm_cfa_vfr_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5514         struct hwrm_cfa_vfr_alloc_input req = {0};
5515         int rc;
5516
5517         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5518                 PMD_DRV_LOG(DEBUG,
5519                             "Not a PF or trusted VF. Command not supported\n");
5520                 return 0;
5521         }
5522
5523         HWRM_PREP(&req, HWRM_CFA_VFR_ALLOC, BNXT_USE_CHIMP_MB);
5524         req.vf_id = rte_cpu_to_le_16(vf_idx);
5525         snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
5526                  bp->eth_dev->data->name, vf_idx);
5527
5528         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5529         HWRM_CHECK_RESULT();
5530
5531         HWRM_UNLOCK();
5532         PMD_DRV_LOG(DEBUG, "VFR %d allocated\n", vf_idx);
5533         return rc;
5534 }
5535
5536 int bnxt_hwrm_cfa_vfr_free(struct bnxt *bp, uint16_t vf_idx)
5537 {
5538         struct hwrm_cfa_vfr_free_output *resp = bp->hwrm_cmd_resp_addr;
5539         struct hwrm_cfa_vfr_free_input req = {0};
5540         int rc;
5541
5542         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5543                 PMD_DRV_LOG(DEBUG,
5544                             "Not a PF or trusted VF. Command not supported\n");
5545                 return 0;
5546         }
5547
5548         HWRM_PREP(&req, HWRM_CFA_VFR_FREE, BNXT_USE_CHIMP_MB);
5549         req.vf_id = rte_cpu_to_le_16(vf_idx);
5550         snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
5551                  bp->eth_dev->data->name, vf_idx);
5552
5553         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5554         HWRM_CHECK_RESULT();
5555         HWRM_UNLOCK();
5556         PMD_DRV_LOG(DEBUG, "VFR %d freed\n", vf_idx);
5557         return rc;
5558 }