drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30 #define HWRM_VERSION_1_10_2_13          0x10a020d
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(int) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages == 0)
  68                 return;
  69
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 static struct bnxt_cp_ring_info*
  79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
  80 {
  81         struct bnxt_cp_ring_info *cp_ring = NULL;
  82         uint16_t i;
  83
  84         switch (type) {
  85         case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
  86         case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
  87                 /* FALLTHROUGH */
  88                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
  89                         struct bnxt_rx_queue *rxq = bp->rx_queues[i];
  90
  91                         if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
  92                             rte_cpu_to_le_16(rid)) {
  93                                 return rxq->cp_ring;
  94                         }
  95                 }
  96                 break;
  97         case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
  98                 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
  99                         struct bnxt_tx_queue *txq = bp->tx_queues[i];
 100
 101                         if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
 102                             rte_cpu_to_le_16(rid)) {
 103                                 return txq->cp_ring;
 104                         }
 105                 }
 106                 break;
 107         default:
 108                 return cp_ring;
 109         }
 110         return cp_ring;
 111 }
 112
 113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
 114  * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
 115  * before timeout, we force the done bit for the cleanup to proceed.
 116  * Also if cpr is null, do nothing.. The HWRM command is  not for a
 117  * Tx/Rx/AGG ring cleanup.
 118  */
 119 static int
 120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
 121                         bool tx, bool rx, bool timeout)
 122 {
 123         int done = 0;
 124
 125         if (cpr != NULL) {
 126                 if (tx)
 127                         done = bnxt_flush_tx_cmp(cpr);
 128
 129                 if (rx)
 130                         done = bnxt_flush_rx_cmp(cpr);
 131
 132                 if (done)
 133                         PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
 134                                     rx ? "Rx" : "Tx");
 135
 136                 /* We are about to timeout and still haven't seen the
 137                  * HWRM done for the Ring free. Force the cleanup.
 138                  */
 139                 if (!done && timeout) {
 140                         done = 1;
 141                         PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
 142                                     rx ? "Rx" : "Tx");
 143                 }
 144         } else {
 145                 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
 146                  * Otherwise the cpr would have been valid. So do nothing.
 147                  */
 148                 done = 1;
 149         }
 150
 151         return done;
 152 }
 153
 154 /*
 155  * HWRM Functions (sent to HWRM)
 156  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
 157  * HWRM command times out, or a negative error code if the HWRM
 158  * command was failed by the FW.
 159  */
 160
 161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
 162                                   uint32_t msg_len, bool use_kong_mb)
 163 {
 164         unsigned int i;
 165         struct input *req = msg;
 166         struct output *resp = bp->hwrm_cmd_resp_addr;
 167         uint32_t *data = msg;
 168         uint8_t *bar;
 169         uint8_t *valid;
 170         uint16_t max_req_len = bp->max_req_len;
 171         struct hwrm_short_input short_input = { 0 };
 172         uint16_t bar_offset = use_kong_mb ?
 173                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
 174         uint16_t mb_trigger_offset = use_kong_mb ?
 175                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 176         struct bnxt_cp_ring_info *cpr = NULL;
 177         bool is_rx = false;
 178         bool is_tx = false;
 179         uint32_t timeout;
 180
 181         /* Do not send HWRM commands to firmware in error state */
 182         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 183                 return 0;
 184
 185         timeout = bp->hwrm_cmd_timeout;
 186
 187         /* Update the message length for backing store config for new FW. */
 188         if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
 189             rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
 190                 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
 191
 192         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 193             msg_len > bp->max_req_len) {
 194                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 195
 196                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 197                 memcpy(short_cmd_req, req, msg_len);
 198
 199                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 200                 short_input.signature = rte_cpu_to_le_16(
 201                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 202                 short_input.size = rte_cpu_to_le_16(msg_len);
 203                 short_input.req_addr =
 204                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 205
 206                 data = (uint32_t *)&short_input;
 207                 msg_len = sizeof(short_input);
 208
 209                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 210         }
 211
 212         /* Write request msg to hwrm channel */
 213         for (i = 0; i < msg_len; i += 4) {
 214                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 215                 rte_write32(*data, bar);
 216                 data++;
 217         }
 218
 219         /* Zero the rest of the request space */
 220         for (; i < max_req_len; i += 4) {
 221                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 222                 rte_write32(0, bar);
 223         }
 224
 225         /* Ring channel doorbell */
 226         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 227         rte_write32(1, bar);
 228         /*
 229          * Make sure the channel doorbell ring command complete before
 230          * reading the response to avoid getting stale or invalid
 231          * responses.
 232          */
 233         rte_io_mb();
 234
 235         /* Check ring flush is done.
 236          * This is valid only for Tx and Rx rings (including AGG rings).
 237          * The Tx and Rx rings should be freed once the HW confirms all
 238          * the internal buffers and BDs associated with the rings are
 239          * consumed and the corresponding DMA is handled.
 240          */
 241         if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
 242                 /* Check if the TxCQ matches. If that fails check if RxCQ
 243                  * matches. And if neither match, is_rx = false, is_tx = false.
 244                  */
 245                 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 246                                                HWRM_RING_FREE_INPUT_RING_TYPE_TX);
 247                 if (cpr == NULL) {
 248                         /* Not a TxCQ. Check if the RxCQ matches. */
 249                         cpr =
 250                         bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 251                                                  HWRM_RING_FREE_INPUT_RING_TYPE_RX);
 252                         if (cpr != NULL)
 253                                 is_rx = true;
 254                 } else {
 255                         is_tx = true;
 256                 }
 257         }
 258
 259         /* Poll for the valid bit */
 260         for (i = 0; i < timeout; i++) {
 261                 int done;
 262
 263                 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
 264                                                i == timeout - 1);
 265                 /* Sanity check on the resp->resp_len */
 266                 rte_io_rmb();
 267                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 268                         /* Last byte of resp contains the valid key */
 269                         valid = (uint8_t *)resp + resp->resp_len - 1;
 270                         if (*valid == HWRM_RESP_VALID_KEY && done)
 271                                 break;
 272                 }
 273                 rte_delay_us(1);
 274         }
 275
 276         if (i >= timeout) {
 277                 /* Suppress VER_GET timeout messages during reset recovery */
 278                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 279                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 280                         return -ETIMEDOUT;
 281
 282                 PMD_DRV_LOG(ERR,
 283                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 284                             req->req_type, req->seq_id);
 285                 return -ETIMEDOUT;
 286         }
 287         return 0;
 288 }
 289
 290 /*
 291  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 292  * spinlock, and does initial processing.
 293  *
 294  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 295  * releases the spinlock only if it returns. If the regular int return codes
 296  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 297  * directly, rather it should be copied and modified to suit the function.
 298  *
 299  * HWRM_UNLOCK() must be called after all response processing is completed.
 300  */
 301 #define HWRM_PREP(req, type, kong) do { \
 302         rte_spinlock_lock(&bp->hwrm_lock); \
 303         if (bp->hwrm_cmd_resp_addr == NULL) { \
 304                 rte_spinlock_unlock(&bp->hwrm_lock); \
 305                 return -EACCES; \
 306         } \
 307         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 308         (req)->req_type = rte_cpu_to_le_16(type); \
 309         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 310         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 311                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 312         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 313         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 314 } while (0)
 315
 316 #define HWRM_CHECK_RESULT_SILENT() do {\
 317         if (rc) { \
 318                 rte_spinlock_unlock(&bp->hwrm_lock); \
 319                 return rc; \
 320         } \
 321         if (resp->error_code) { \
 322                 rc = rte_le_to_cpu_16(resp->error_code); \
 323                 rte_spinlock_unlock(&bp->hwrm_lock); \
 324                 return rc; \
 325         } \
 326 } while (0)
 327
 328 #define HWRM_CHECK_RESULT() do {\
 329         if (rc) { \
 330                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 331                 rte_spinlock_unlock(&bp->hwrm_lock); \
 332                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 333                         rc = -EACCES; \
 334                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 335                         rc = -ENOSPC; \
 336                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 337                         rc = -EINVAL; \
 338                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 339                         rc = -ENOTSUP; \
 340                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 341                         rc = -EAGAIN; \
 342                 else if (rc > 0) \
 343                         rc = -EIO; \
 344                 return rc; \
 345         } \
 346         if (resp->error_code) { \
 347                 rc = rte_le_to_cpu_16(resp->error_code); \
 348                 if (resp->resp_len >= 16) { \
 349                         struct hwrm_err_output *tmp_hwrm_err_op = \
 350                                                 (void *)resp; \
 351                         PMD_DRV_LOG(ERR, \
 352                                 "error %d:%d:%08x:%04x\n", \
 353                                 rc, tmp_hwrm_err_op->cmd_err, \
 354                                 rte_le_to_cpu_32(\
 355                                         tmp_hwrm_err_op->opaque_0), \
 356                                 rte_le_to_cpu_16(\
 357                                         tmp_hwrm_err_op->opaque_1)); \
 358                 } else { \
 359                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 360                 } \
 361                 rte_spinlock_unlock(&bp->hwrm_lock); \
 362                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 363                         rc = -EACCES; \
 364                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 365                         rc = -ENOSPC; \
 366                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 367                         rc = -EINVAL; \
 368                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 369                         rc = -ENOTSUP; \
 370                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 371                         rc = -EAGAIN; \
 372                 else if (rc > 0) \
 373                         rc = -EIO; \
 374                 return rc; \
 375         } \
 376 } while (0)
 377
 378 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 379
 380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 381                                 bool use_kong_mb,
 382                                 uint16_t msg_type,
 383                                 void *msg,
 384                                 uint32_t msg_len,
 385                                 void *resp_msg,
 386                                 uint32_t resp_len)
 387 {
 388         int rc = 0;
 389         bool mailbox = BNXT_USE_CHIMP_MB;
 390         struct input *req = msg;
 391         struct output *resp = bp->hwrm_cmd_resp_addr;
 392
 393         if (use_kong_mb)
 394                 mailbox = BNXT_USE_KONG(bp);
 395
 396         HWRM_PREP(req, msg_type, mailbox);
 397
 398         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 399
 400         HWRM_CHECK_RESULT();
 401
 402         if (resp_msg)
 403                 memcpy(resp_msg, resp, resp_len);
 404
 405         HWRM_UNLOCK();
 406
 407         return rc;
 408 }
 409
 410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 411                                   bool use_kong_mb,
 412                                   uint16_t tf_type,
 413                                   uint16_t tf_subtype,
 414                                   uint32_t *tf_response_code,
 415                                   void *msg,
 416                                   uint32_t msg_len,
 417                                   void *response,
 418                                   uint32_t response_len)
 419 {
 420         int rc = 0;
 421         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 422         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 423         bool mailbox = BNXT_USE_CHIMP_MB;
 424
 425         if (msg_len > sizeof(req.tf_req))
 426                 return -ENOMEM;
 427
 428         if (use_kong_mb)
 429                 mailbox = BNXT_USE_KONG(bp);
 430
 431         HWRM_PREP(&req, HWRM_TF, mailbox);
 432         /* Build request using the user supplied request payload.
 433          * TLV request size is checked at build time against HWRM
 434          * request max size, thus no checking required.
 435          */
 436         req.tf_type = tf_type;
 437         req.tf_subtype = tf_subtype;
 438         memcpy(req.tf_req, msg, msg_len);
 439
 440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 441         HWRM_CHECK_RESULT();
 442
 443         /* Copy the resp to user provided response buffer */
 444         if (response != NULL)
 445                 /* Post process response data. We need to copy only
 446                  * the 'payload' as the HWRM data structure really is
 447                  * HWRM header + msg header + payload and the TFLIB
 448                  * only provided a payload place holder.
 449                  */
 450                 if (response_len != 0) {
 451                         memcpy(response,
 452                                resp->tf_resp,
 453                                response_len);
 454                 }
 455
 456         /* Extract the internal tflib response code */
 457         *tf_response_code = resp->tf_resp_code;
 458         HWRM_UNLOCK();
 459
 460         return rc;
 461 }
 462
 463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 464 {
 465         int rc = 0;
 466         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 467         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 468
 469         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 470         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 471         req.mask = 0;
 472
 473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 474
 475         HWRM_CHECK_RESULT();
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 482                                  struct bnxt_vnic_info *vnic,
 483                                  uint16_t vlan_count,
 484                                  struct bnxt_vlan_table_entry *vlan_table)
 485 {
 486         int rc = 0;
 487         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 488         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 489         uint32_t mask = 0;
 490
 491         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 492                 return rc;
 493
 494         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 495         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 496
 497         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 498                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 499         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 500                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 501
 502         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 503                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 504
 505         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 506                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 507         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 508                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 509                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 510                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 511         }
 512         if (vlan_table) {
 513                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 514                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 515                 req.vlan_tag_tbl_addr =
 516                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 517                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 518         }
 519         req.mask = rte_cpu_to_le_32(mask);
 520
 521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 522
 523         HWRM_CHECK_RESULT();
 524         HWRM_UNLOCK();
 525
 526         return rc;
 527 }
 528
 529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 530                         uint16_t vlan_count,
 531                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 532 {
 533         int rc = 0;
 534         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 535         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 536                                                 bp->hwrm_cmd_resp_addr;
 537
 538         /*
 539          * Older HWRM versions did not support this command, and the set_rx_mask
 540          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 541          * removed from set_rx_mask call, and this command was added.
 542          *
 543          * This command is also present from 1.7.8.11 and higher,
 544          * as well as 1.7.8.0
 545          */
 546         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 547                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 548                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 549                                         (11)))
 550                                 return 0;
 551                 }
 552         }
 553         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 554         req.fid = rte_cpu_to_le_16(fid);
 555
 556         req.vlan_tag_mask_tbl_addr =
 557                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 558         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 559
 560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 561
 562         HWRM_CHECK_RESULT();
 563         HWRM_UNLOCK();
 564
 565         return rc;
 566 }
 567
 568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 569                              struct bnxt_filter_info *filter)
 570 {
 571         int rc = 0;
 572         struct bnxt_filter_info *l2_filter = filter;
 573         struct bnxt_vnic_info *vnic = NULL;
 574         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 575         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 576
 577         if (filter->fw_l2_filter_id == UINT64_MAX)
 578                 return 0;
 579
 580         if (filter->matching_l2_fltr_ptr)
 581                 l2_filter = filter->matching_l2_fltr_ptr;
 582
 583         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 584                     filter, l2_filter, l2_filter->l2_ref_cnt);
 585
 586         if (l2_filter->l2_ref_cnt == 0)
 587                 return 0;
 588
 589         if (l2_filter->l2_ref_cnt > 0)
 590                 l2_filter->l2_ref_cnt--;
 591
 592         if (l2_filter->l2_ref_cnt > 0)
 593                 return 0;
 594
 595         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 596
 597         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 598
 599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 600
 601         HWRM_CHECK_RESULT();
 602         HWRM_UNLOCK();
 603
 604         filter->fw_l2_filter_id = UINT64_MAX;
 605         if (l2_filter->l2_ref_cnt == 0) {
 606                 vnic = l2_filter->vnic;
 607                 if (vnic) {
 608                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 609                                       bnxt_filter_info, next);
 610                         bnxt_free_filter(bp, l2_filter);
 611                 }
 612         }
 613
 614         return 0;
 615 }
 616
 617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 618                          uint16_t dst_id,
 619                          struct bnxt_filter_info *filter)
 620 {
 621         int rc = 0;
 622         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 623         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 624         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 625         const struct rte_eth_vmdq_rx_conf *conf =
 626                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 627         uint32_t enables = 0;
 628         uint16_t j = dst_id - 1;
 629
 630         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 631         if ((dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) &&
 632             conf->pool_map[j].pools & (1UL << j)) {
 633                 PMD_DRV_LOG(DEBUG,
 634                         "Add vlan %u to vmdq pool %u\n",
 635                         conf->pool_map[j].vlan_id, j);
 636
 637                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 638                 filter->enables |=
 639                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 640                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 641         }
 642
 643         if (filter->fw_l2_filter_id != UINT64_MAX)
 644                 bnxt_hwrm_clear_l2_filter(bp, filter);
 645
 646         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 647
 648         /* PMD does not support XDP and RoCE */
 649         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
 650                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
 651         req.flags = rte_cpu_to_le_32(filter->flags);
 652
 653         enables = filter->enables |
 654               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 655         req.dst_id = rte_cpu_to_le_16(dst_id);
 656
 657         if (enables &
 658             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 659                 memcpy(req.l2_addr, filter->l2_addr,
 660                        RTE_ETHER_ADDR_LEN);
 661         if (enables &
 662             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 663                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 664                        RTE_ETHER_ADDR_LEN);
 665         if (enables &
 666             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 667                 req.l2_ovlan = filter->l2_ovlan;
 668         if (enables &
 669             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 670                 req.l2_ivlan = filter->l2_ivlan;
 671         if (enables &
 672             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 673                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 674         if (enables &
 675             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 676                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 677         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 678                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 679         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 680                 req.src_type = filter->src_type;
 681         if (filter->pri_hint) {
 682                 req.pri_hint = filter->pri_hint;
 683                 req.l2_filter_id_hint =
 684                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 685         }
 686
 687         req.enables = rte_cpu_to_le_32(enables);
 688
 689         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 690
 691         HWRM_CHECK_RESULT();
 692
 693         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 694         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 695         HWRM_UNLOCK();
 696
 697         filter->l2_ref_cnt++;
 698
 699         return rc;
 700 }
 701
 702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 703 {
 704         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 705         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 706         uint32_t flags = 0;
 707         int rc;
 708
 709         if (!ptp)
 710                 return 0;
 711
 712         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 713
 714         if (ptp->rx_filter)
 715                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 716         else
 717                 flags |=
 718                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 719         if (ptp->tx_tstamp_en)
 720                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 721         else
 722                 flags |=
 723                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 724         req.flags = rte_cpu_to_le_32(flags);
 725         req.enables = rte_cpu_to_le_32
 726                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 727         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 728
 729         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 730         HWRM_UNLOCK();
 731
 732         return rc;
 733 }
 734
 735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 736 {
 737         int rc = 0;
 738         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 739         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 740         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 741
 742         if (ptp)
 743                 return 0;
 744
 745         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 746
 747         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 748
 749         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 750
 751         HWRM_CHECK_RESULT();
 752
 753         if (BNXT_CHIP_P5(bp)) {
 754                 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS))
 755                         return 0;
 756         } else {
 757                 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 758                         return 0;
 759         }
 760
 761         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 762                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 763
 764         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 765         if (!ptp)
 766                 return -ENOMEM;
 767
 768         if (!BNXT_CHIP_P5(bp)) {
 769                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 770                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 771                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 772                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 773                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 774                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 775                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 776                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 777                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 778                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 779                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 780                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 781                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 782                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 783                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 784                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 785                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 786                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 787         }
 788
 789         ptp->bp = bp;
 790         bp->ptp_cfg = ptp;
 791
 792         return 0;
 793 }
 794
 795 void bnxt_free_vf_info(struct bnxt *bp)
 796 {
 797         int i;
 798
 799         if (bp->pf == NULL)
 800                 return;
 801
 802         if (bp->pf->vf_info == NULL)
 803                 return;
 804
 805         for (i = 0; i < bp->pf->max_vfs; i++) {
 806                 rte_free(bp->pf->vf_info[i].vlan_table);
 807                 bp->pf->vf_info[i].vlan_table = NULL;
 808                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 809                 bp->pf->vf_info[i].vlan_as_table = NULL;
 810         }
 811         rte_free(bp->pf->vf_info);
 812         bp->pf->vf_info = NULL;
 813 }
 814
 815 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
 816 {
 817         struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
 818         int i;
 819
 820         if (vf_info)
 821                 bnxt_free_vf_info(bp);
 822
 823         vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
 824         if (vf_info == NULL) {
 825                 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
 826                 return -ENOMEM;
 827         }
 828
 829         bp->pf->max_vfs = max_vfs;
 830         for (i = 0; i < max_vfs; i++) {
 831                 vf_info[i].fid = bp->pf->first_vf_id + i;
 832                 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
 833                                                     getpagesize(), getpagesize());
 834                 if (vf_info[i].vlan_table == NULL) {
 835                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
 836                         goto err;
 837                 }
 838                 rte_mem_lock_page(vf_info[i].vlan_table);
 839
 840                 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
 841                                                        getpagesize(), getpagesize());
 842                 if (vf_info[i].vlan_as_table == NULL) {
 843                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
 844                         goto err;
 845                 }
 846                 rte_mem_lock_page(vf_info[i].vlan_as_table);
 847
 848                 STAILQ_INIT(&vf_info[i].filter);
 849         }
 850
 851         bp->pf->vf_info = vf_info;
 852
 853         return 0;
 854 err:
 855         bnxt_free_vf_info(bp);
 856         return -ENOMEM;
 857 }
 858
 859 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 860 {
 861         int rc = 0;
 862         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 863         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 864         uint16_t new_max_vfs;
 865         uint32_t flags;
 866
 867         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 868
 869         req.fid = rte_cpu_to_le_16(0xffff);
 870
 871         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 872
 873         HWRM_CHECK_RESULT();
 874
 875         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 876         flags = rte_le_to_cpu_32(resp->flags);
 877         if (BNXT_PF(bp)) {
 878                 bp->pf->port_id = resp->port_id;
 879                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 880                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 881                 new_max_vfs = bp->pdev->max_vfs;
 882                 if (new_max_vfs != bp->pf->max_vfs) {
 883                         rc = bnxt_alloc_vf_info(bp, new_max_vfs);
 884                         if (rc)
 885                                 goto unlock;
 886                 }
 887         }
 888
 889         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 890         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 891                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 892                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 893         } else {
 894                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 895         }
 896         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 897         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 898         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 899         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 900         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 901         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 902         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 903         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
 904                 bp->max_l2_ctx += bp->max_rx_em_flows;
 905         /* TODO: For now, do not support VMDq/RFS on VFs. */
 906         if (BNXT_PF(bp)) {
 907                 if (bp->pf->max_vfs)
 908                         bp->max_vnics = 1;
 909                 else
 910                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 911         } else {
 912                 bp->max_vnics = 1;
 913         }
 914         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 915                     bp->max_l2_ctx, bp->max_vnics);
 916         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 917         if (BNXT_PF(bp)) {
 918                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 919                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 920                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 921                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 922                         HWRM_UNLOCK();
 923                         bnxt_hwrm_ptp_qcfg(bp);
 924                 }
 925         }
 926
 927         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 928                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 929
 930         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 931                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 932                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 933         }
 934
 935         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 936                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 937
 938         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 939                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 940
 941         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
 942                 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
 943
 944         if (!(flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED)) {
 945                 bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
 946                 PMD_DRV_LOG(DEBUG, "VLAN acceleration for TX is enabled\n");
 947         }
 948 unlock:
 949         HWRM_UNLOCK();
 950
 951         return rc;
 952 }
 953
 954 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 955 {
 956         int rc;
 957
 958         rc = __bnxt_hwrm_func_qcaps(bp);
 959         if (rc == -ENOMEM)
 960                 return rc;
 961
 962         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 963                 rc = bnxt_alloc_ctx_mem(bp);
 964                 if (rc)
 965                         return rc;
 966
 967                 /* On older FW,
 968                  * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 969                  * But the error can be ignored. Return success.
 970                  */
 971                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 972                 if (!rc)
 973                         bp->flags |= BNXT_FLAG_NEW_RM;
 974         }
 975
 976         return 0;
 977 }
 978
 979 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 980 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 981 {
 982         int rc = 0;
 983         uint32_t flags;
 984         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 985         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 986
 987         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 988
 989         req.target_id = rte_cpu_to_le_16(0xffff);
 990
 991         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 992
 993         HWRM_CHECK_RESULT();
 994
 995         flags = rte_le_to_cpu_32(resp->flags);
 996
 997         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 998                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 999                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
1000         }
1001
1002         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
1003                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
1004
1005         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
1006                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
1007
1008         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP) {
1009                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_VLAN_RX_STRIP;
1010                 PMD_DRV_LOG(DEBUG, "Rx VLAN strip capability enabled\n");
1011         }
1012
1013         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
1014
1015         HWRM_UNLOCK();
1016
1017         return rc;
1018 }
1019
1020 int bnxt_hwrm_func_reset(struct bnxt *bp)
1021 {
1022         int rc = 0;
1023         struct hwrm_func_reset_input req = {.req_type = 0 };
1024         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1025
1026         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1027
1028         req.enables = rte_cpu_to_le_32(0);
1029
1030         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1031
1032         HWRM_CHECK_RESULT();
1033         HWRM_UNLOCK();
1034
1035         return rc;
1036 }
1037
1038 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1039 {
1040         int rc;
1041         uint32_t flags = 0;
1042         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1043         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1044
1045         if (bp->flags & BNXT_FLAG_REGISTERED)
1046                 return 0;
1047
1048         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1049                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1050         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1051                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1052
1053         /* PFs and trusted VFs should indicate the support of the
1054          * Master capability on non Stingray platform
1055          */
1056         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1057                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1058
1059         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1060         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1061                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1062         req.ver_maj_8b = RTE_VER_YEAR;
1063         req.ver_min_8b = RTE_VER_MONTH;
1064         req.ver_upd_8b = RTE_VER_MINOR;
1065
1066         if (BNXT_PF(bp)) {
1067                 req.enables |= rte_cpu_to_le_32(
1068                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1069                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1070                        RTE_MIN(sizeof(req.vf_req_fwd),
1071                                sizeof(bp->pf->vf_req_fwd)));
1072         }
1073
1074         req.flags = rte_cpu_to_le_32(flags);
1075
1076         req.async_event_fwd[0] |=
1077                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1078                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1079                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1080                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1081                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1082         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1083                 req.async_event_fwd[0] |=
1084                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1085         req.async_event_fwd[1] |=
1086                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1087                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1088         if (BNXT_PF(bp))
1089                 req.async_event_fwd[1] |=
1090                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1091
1092         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1093                 req.async_event_fwd[1] |=
1094                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1095
1096         req.async_event_fwd[2] |=
1097                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST |
1098                                  ASYNC_CMPL_EVENT_ID_ERROR_REPORT);
1099
1100         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1101
1102         HWRM_CHECK_RESULT();
1103
1104         flags = rte_le_to_cpu_32(resp->flags);
1105         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1106                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1107
1108         HWRM_UNLOCK();
1109
1110         bp->flags |= BNXT_FLAG_REGISTERED;
1111
1112         return rc;
1113 }
1114
1115 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1116 {
1117         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1118                 return 0;
1119
1120         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1121 }
1122
1123 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1124 {
1125         int rc;
1126         uint32_t flags = 0;
1127         uint32_t enables;
1128         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1129         struct hwrm_func_vf_cfg_input req = {0};
1130
1131         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1132
1133         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
1134                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
1135                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
1136                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1137                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1138
1139         if (BNXT_HAS_RING_GRPS(bp)) {
1140                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1141                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1142         }
1143
1144         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1145         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1146                                             AGG_RING_MULTIPLIER);
1147         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1148         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1149                                               bp->tx_nr_rings +
1150                                               BNXT_NUM_ASYNC_CPR(bp));
1151         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1152         if (bp->vf_resv_strategy ==
1153             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1154                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1155                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1156                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1157                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1158                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1159                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1160         } else if (bp->vf_resv_strategy ==
1161                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1162                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1163                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1164         }
1165
1166         if (test)
1167                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1168                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1169                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1170                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1171                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1172                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1173
1174         if (test && BNXT_HAS_RING_GRPS(bp))
1175                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1176
1177         req.flags = rte_cpu_to_le_32(flags);
1178         req.enables |= rte_cpu_to_le_32(enables);
1179
1180         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1181
1182         if (test)
1183                 HWRM_CHECK_RESULT_SILENT();
1184         else
1185                 HWRM_CHECK_RESULT();
1186
1187         HWRM_UNLOCK();
1188         return rc;
1189 }
1190
1191 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1192 {
1193         int rc;
1194         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1195         struct hwrm_func_resource_qcaps_input req = {0};
1196
1197         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1198         req.fid = rte_cpu_to_le_16(0xffff);
1199
1200         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1201
1202         HWRM_CHECK_RESULT_SILENT();
1203
1204         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1205         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1206         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1207         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1208         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1209         /* func_resource_qcaps does not return max_rx_em_flows.
1210          * So use the value provided by func_qcaps.
1211          */
1212         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1213         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1214                 bp->max_l2_ctx += bp->max_rx_em_flows;
1215         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1216         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1217         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1218         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1219         if (bp->vf_resv_strategy >
1220             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1221                 bp->vf_resv_strategy =
1222                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1223
1224         HWRM_UNLOCK();
1225         return rc;
1226 }
1227
1228 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1229 {
1230         int rc = 0;
1231         struct hwrm_ver_get_input req = {.req_type = 0 };
1232         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1233         uint32_t fw_version;
1234         uint16_t max_resp_len;
1235         char type[RTE_MEMZONE_NAMESIZE];
1236         uint32_t dev_caps_cfg;
1237
1238         bp->max_req_len = HWRM_MAX_REQ_LEN;
1239         bp->hwrm_cmd_timeout = timeout;
1240         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1241
1242         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1243         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1244         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1245
1246         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1247
1248         if (bp->flags & BNXT_FLAG_FW_RESET)
1249                 HWRM_CHECK_RESULT_SILENT();
1250         else
1251                 HWRM_CHECK_RESULT();
1252
1253         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
1254                 rc = -EAGAIN;
1255                 goto error;
1256         }
1257
1258         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1259                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1260                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1261                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1262                 resp->hwrm_fw_rsvd_8b);
1263         bp->fw_ver = ((uint32_t)resp->hwrm_fw_maj_8b << 24) |
1264                      ((uint32_t)resp->hwrm_fw_min_8b << 16) |
1265                      ((uint32_t)resp->hwrm_fw_bld_8b << 8) |
1266                      resp->hwrm_fw_rsvd_8b;
1267         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1268                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1269
1270         fw_version = resp->hwrm_intf_maj_8b << 16;
1271         fw_version |= resp->hwrm_intf_min_8b << 8;
1272         fw_version |= resp->hwrm_intf_upd_8b;
1273         bp->hwrm_spec_code = fw_version;
1274
1275         /* def_req_timeout value is in milliseconds */
1276         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1277         /* convert timeout to usec */
1278         bp->hwrm_cmd_timeout *= 1000;
1279         if (!bp->hwrm_cmd_timeout)
1280                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1281
1282         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1283                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1284                 rc = -EINVAL;
1285                 goto error;
1286         }
1287
1288         if (bp->max_req_len > resp->max_req_win_len) {
1289                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1290                 rc = -EINVAL;
1291                 goto error;
1292         }
1293
1294         bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1295
1296         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1297         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1298         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1299                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1300
1301         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1302         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1303
1304         RTE_VERIFY(max_resp_len <= bp->max_resp_len);
1305         bp->max_resp_len = max_resp_len;
1306
1307         if ((dev_caps_cfg &
1308                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1309             (dev_caps_cfg &
1310              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1311                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1312                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1313         }
1314
1315         if (((dev_caps_cfg &
1316               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1317              (dev_caps_cfg &
1318               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1319             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1320                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1321                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1322                         bp->pdev->addr.devid, bp->pdev->addr.function);
1323
1324                 rte_free(bp->hwrm_short_cmd_req_addr);
1325
1326                 bp->hwrm_short_cmd_req_addr =
1327                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1328                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1329                         rc = -ENOMEM;
1330                         goto error;
1331                 }
1332                 bp->hwrm_short_cmd_req_dma_addr =
1333                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1334                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1335                         rte_free(bp->hwrm_short_cmd_req_addr);
1336                         PMD_DRV_LOG(ERR,
1337                                 "Unable to map buffer to physical memory.\n");
1338                         rc = -ENOMEM;
1339                         goto error;
1340                 }
1341         }
1342         if (dev_caps_cfg &
1343             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1344                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1345                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1346         }
1347         if (dev_caps_cfg &
1348             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1349                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1350         if (dev_caps_cfg &
1351             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1352                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1353                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1354         }
1355
1356         if (dev_caps_cfg &
1357             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1358                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1359                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1360         }
1361
1362         if (dev_caps_cfg &
1363             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED) {
1364                 PMD_DRV_LOG(DEBUG, "Host-based truflow feature enabled.\n");
1365                 bp->fw_cap |= BNXT_FW_CAP_TRUFLOW_EN;
1366         }
1367
1368 error:
1369         HWRM_UNLOCK();
1370         return rc;
1371 }
1372
1373 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp)
1374 {
1375         int rc;
1376         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1377         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1378
1379         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1380                 return 0;
1381
1382         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1383
1384         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1385
1386         HWRM_CHECK_RESULT();
1387         HWRM_UNLOCK();
1388
1389         PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1390                     bp->eth_dev->data->port_id);
1391
1392         return rc;
1393 }
1394
1395 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1396 {
1397         int rc = 0;
1398         struct hwrm_port_phy_cfg_input req = {0};
1399         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1400         uint32_t enables = 0;
1401
1402         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1403
1404         if (conf->link_up) {
1405                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1406                 if (bp->link_info->auto_mode && conf->link_speed) {
1407                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1408                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1409                 }
1410
1411                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1412                 /*
1413                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1414                  * any auto mode, even "none".
1415                  */
1416                 if (!conf->link_speed) {
1417                         /* No speeds specified. Enable AutoNeg - all speeds */
1418                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1419                         req.auto_mode =
1420                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1421                 } else {
1422                         if (bp->link_info->link_signal_mode) {
1423                                 enables |=
1424                                 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1425                                 req.force_pam4_link_speed =
1426                                         rte_cpu_to_le_16(conf->link_speed);
1427                         } else {
1428                                 req.force_link_speed =
1429                                         rte_cpu_to_le_16(conf->link_speed);
1430                         }
1431                 }
1432                 /* AutoNeg - Advertise speeds specified. */
1433                 if (conf->auto_link_speed_mask &&
1434                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1435                         req.auto_mode =
1436                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1437                         req.auto_link_speed_mask =
1438                                 conf->auto_link_speed_mask;
1439                         if (conf->auto_pam4_link_speeds) {
1440                                 enables |=
1441                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1442                                 req.auto_link_pam4_speed_mask =
1443                                         conf->auto_pam4_link_speeds;
1444                         } else {
1445                                 enables |=
1446                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1447                         }
1448                 }
1449                 if (conf->auto_link_speed &&
1450                 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1451                         enables |=
1452                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1453
1454                 req.auto_duplex = conf->duplex;
1455                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1456                 req.auto_pause = conf->auto_pause;
1457                 req.force_pause = conf->force_pause;
1458                 /* Set force_pause if there is no auto or if there is a force */
1459                 if (req.auto_pause && !req.force_pause)
1460                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1461                 else
1462                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1463
1464                 req.enables = rte_cpu_to_le_32(enables);
1465         } else {
1466                 req.flags =
1467                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1468                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1469         }
1470
1471         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1472
1473         HWRM_CHECK_RESULT();
1474         HWRM_UNLOCK();
1475
1476         return rc;
1477 }
1478
1479 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1480                                    struct bnxt_link_info *link_info)
1481 {
1482         int rc = 0;
1483         struct hwrm_port_phy_qcfg_input req = {0};
1484         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1485
1486         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1487
1488         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1489
1490         HWRM_CHECK_RESULT();
1491
1492         link_info->phy_link_status = resp->link;
1493         link_info->link_up =
1494                 (link_info->phy_link_status ==
1495                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1496         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1497         link_info->duplex = resp->duplex_cfg;
1498         link_info->pause = resp->pause;
1499         link_info->auto_pause = resp->auto_pause;
1500         link_info->force_pause = resp->force_pause;
1501         link_info->auto_mode = resp->auto_mode;
1502         link_info->phy_type = resp->phy_type;
1503         link_info->media_type = resp->media_type;
1504
1505         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1506         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1507         link_info->auto_link_speed_mask = rte_le_to_cpu_16(resp->auto_link_speed_mask);
1508         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1509         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1510         link_info->phy_ver[0] = resp->phy_maj;
1511         link_info->phy_ver[1] = resp->phy_min;
1512         link_info->phy_ver[2] = resp->phy_bld;
1513         link_info->link_signal_mode =
1514                 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1515         link_info->force_pam4_link_speed =
1516                         rte_le_to_cpu_16(resp->force_pam4_link_speed);
1517         link_info->support_pam4_speeds =
1518                         rte_le_to_cpu_16(resp->support_pam4_speeds);
1519         link_info->auto_pam4_link_speeds =
1520                         rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1521         link_info->module_status = resp->module_status;
1522         HWRM_UNLOCK();
1523
1524         PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1525                     link_info->link_speed, link_info->auto_mode,
1526                     link_info->auto_link_speed, link_info->auto_link_speed_mask,
1527                     link_info->support_speeds, link_info->force_link_speed);
1528         PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1529                     link_info->link_signal_mode,
1530                     link_info->auto_pam4_link_speeds,
1531                     link_info->support_pam4_speeds,
1532                     link_info->force_pam4_link_speed);
1533         return rc;
1534 }
1535
1536 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1537 {
1538         int rc = 0;
1539         struct hwrm_port_phy_qcaps_input req = {0};
1540         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1541         struct bnxt_link_info *link_info = bp->link_info;
1542
1543         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1544                 return 0;
1545
1546         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1547
1548         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1549
1550         HWRM_CHECK_RESULT_SILENT();
1551
1552         bp->port_cnt = resp->port_cnt;
1553         if (resp->supported_speeds_auto_mode)
1554                 link_info->support_auto_speeds =
1555                         rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1556         if (resp->supported_pam4_speeds_auto_mode)
1557                 link_info->support_pam4_auto_speeds =
1558                         rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1559
1560         HWRM_UNLOCK();
1561
1562         /* Older firmware does not have supported_auto_speeds, so assume
1563          * that all supported speeds can be autonegotiated.
1564          */
1565         if (link_info->auto_link_speed_mask && !link_info->support_auto_speeds)
1566                 link_info->support_auto_speeds = link_info->support_speeds;
1567
1568         return 0;
1569 }
1570
1571 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1572 {
1573         int i = 0;
1574
1575         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1576                 if (bp->tx_cos_queue[i].profile ==
1577                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1578                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1579                         return true;
1580                 }
1581         }
1582         return false;
1583 }
1584
1585 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1586 {
1587         int i = 0;
1588
1589         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1590                 if (bp->tx_cos_queue[i].profile !=
1591                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1592                     bp->tx_cos_queue[i].id !=
1593                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1594                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1595                         break;
1596                 }
1597         }
1598 }
1599
1600 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1601 {
1602         int rc = 0;
1603         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1604         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1605         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1606         int i;
1607
1608 get_rx_info:
1609         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1610
1611         req.flags = rte_cpu_to_le_32(dir);
1612         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1613         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1614             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1615                 req.drv_qmap_cap =
1616                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1617         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1618
1619         HWRM_CHECK_RESULT();
1620
1621         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1622                 GET_TX_QUEUE_INFO(0);
1623                 GET_TX_QUEUE_INFO(1);
1624                 GET_TX_QUEUE_INFO(2);
1625                 GET_TX_QUEUE_INFO(3);
1626                 GET_TX_QUEUE_INFO(4);
1627                 GET_TX_QUEUE_INFO(5);
1628                 GET_TX_QUEUE_INFO(6);
1629                 GET_TX_QUEUE_INFO(7);
1630         } else  {
1631                 GET_RX_QUEUE_INFO(0);
1632                 GET_RX_QUEUE_INFO(1);
1633                 GET_RX_QUEUE_INFO(2);
1634                 GET_RX_QUEUE_INFO(3);
1635                 GET_RX_QUEUE_INFO(4);
1636                 GET_RX_QUEUE_INFO(5);
1637                 GET_RX_QUEUE_INFO(6);
1638                 GET_RX_QUEUE_INFO(7);
1639         }
1640
1641         HWRM_UNLOCK();
1642
1643         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1644                 goto done;
1645
1646         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1647                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1648         } else {
1649                 int j;
1650
1651                 /* iterate and find the COSq profile to use for Tx */
1652                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1653                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1654                                 if (bp->tx_cos_queue[i].id != 0xff)
1655                                         bp->tx_cosq_id[j++] =
1656                                                 bp->tx_cos_queue[i].id;
1657                         }
1658                 } else {
1659                         /* When CoS classification is disabled, for normal NIC
1660                          * operations, ideally we should look to use LOSSY.
1661                          * If not found, fallback to the first valid profile
1662                          */
1663                         if (!bnxt_find_lossy_profile(bp))
1664                                 bnxt_find_first_valid_profile(bp);
1665
1666                 }
1667         }
1668
1669         bp->max_tc = resp->max_configurable_queues;
1670         bp->max_lltc = resp->max_configurable_lossless_queues;
1671         if (bp->max_tc > BNXT_MAX_QUEUE)
1672                 bp->max_tc = BNXT_MAX_QUEUE;
1673         bp->max_q = bp->max_tc;
1674
1675         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1676                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1677                 goto get_rx_info;
1678         }
1679
1680 done:
1681         return rc;
1682 }
1683
1684 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1685                          struct bnxt_ring *ring,
1686                          uint32_t ring_type, uint32_t map_index,
1687                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1688                          uint16_t tx_cosq_id)
1689 {
1690         int rc = 0;
1691         uint32_t enables = 0;
1692         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1693         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1694         struct rte_mempool *mb_pool;
1695         uint16_t rx_buf_size;
1696
1697         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1698
1699         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1700         req.fbo = rte_cpu_to_le_32(0);
1701         /* Association of ring index with doorbell index */
1702         req.logical_id = rte_cpu_to_le_16(map_index);
1703         req.length = rte_cpu_to_le_32(ring->ring_size);
1704
1705         switch (ring_type) {
1706         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1707                 req.ring_type = ring_type;
1708                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1709                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1710                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1711                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1712                         enables |=
1713                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1714                 break;
1715         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1716                 req.ring_type = ring_type;
1717                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1718                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1719                 if (BNXT_CHIP_P5(bp)) {
1720                         mb_pool = bp->rx_queues[0]->mb_pool;
1721                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1722                                       RTE_PKTMBUF_HEADROOM;
1723                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1724                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1725                         enables |=
1726                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1727                 }
1728                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1729                         enables |=
1730                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1731                 break;
1732         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1733                 req.ring_type = ring_type;
1734                 if (BNXT_HAS_NQ(bp)) {
1735                         /* Association of cp ring with nq */
1736                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1737                         enables |=
1738                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1739                 }
1740                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1741                 break;
1742         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1743                 req.ring_type = ring_type;
1744                 req.page_size = BNXT_PAGE_SHFT;
1745                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1746                 break;
1747         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1748                 req.ring_type = ring_type;
1749                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1750
1751                 mb_pool = bp->rx_queues[0]->mb_pool;
1752                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1753                               RTE_PKTMBUF_HEADROOM;
1754                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1755                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1756
1757                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1758                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1759                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1760                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1761                 break;
1762         default:
1763                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1764                         ring_type);
1765                 HWRM_UNLOCK();
1766                 return -EINVAL;
1767         }
1768         req.enables = rte_cpu_to_le_32(enables);
1769
1770         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1771
1772         if (rc || resp->error_code) {
1773                 if (rc == 0 && resp->error_code)
1774                         rc = rte_le_to_cpu_16(resp->error_code);
1775                 switch (ring_type) {
1776                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1777                         PMD_DRV_LOG(ERR,
1778                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1779                         HWRM_UNLOCK();
1780                         return rc;
1781                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1782                         PMD_DRV_LOG(ERR,
1783                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1784                         HWRM_UNLOCK();
1785                         return rc;
1786                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1787                         PMD_DRV_LOG(ERR,
1788                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1789                                     rc);
1790                         HWRM_UNLOCK();
1791                         return rc;
1792                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1793                         PMD_DRV_LOG(ERR,
1794                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1795                         HWRM_UNLOCK();
1796                         return rc;
1797                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1798                         PMD_DRV_LOG(ERR,
1799                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1800                         HWRM_UNLOCK();
1801                         return rc;
1802                 default:
1803                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1804                         HWRM_UNLOCK();
1805                         return rc;
1806                 }
1807         }
1808
1809         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1810         HWRM_UNLOCK();
1811         return rc;
1812 }
1813
1814 int bnxt_hwrm_ring_free(struct bnxt *bp,
1815                         struct bnxt_ring *ring, uint32_t ring_type,
1816                         uint16_t cp_ring_id)
1817 {
1818         int rc;
1819         struct hwrm_ring_free_input req = {.req_type = 0 };
1820         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1821
1822         if (ring->fw_ring_id == INVALID_HW_RING_ID)
1823                 return -EINVAL;
1824
1825         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1826
1827         req.ring_type = ring_type;
1828         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1829         req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1830
1831         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1832         ring->fw_ring_id = INVALID_HW_RING_ID;
1833
1834         if (rc || resp->error_code) {
1835                 if (rc == 0 && resp->error_code)
1836                         rc = rte_le_to_cpu_16(resp->error_code);
1837                 HWRM_UNLOCK();
1838
1839                 switch (ring_type) {
1840                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1841                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1842                                 rc);
1843                         return rc;
1844                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1845                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1846                                 rc);
1847                         return rc;
1848                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1849                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1850                                 rc);
1851                         return rc;
1852                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1853                         PMD_DRV_LOG(ERR,
1854                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1855                         return rc;
1856                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1857                         PMD_DRV_LOG(ERR,
1858                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1859                         return rc;
1860                 default:
1861                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1862                         return rc;
1863                 }
1864         }
1865         HWRM_UNLOCK();
1866         return 0;
1867 }
1868
1869 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1870 {
1871         int rc = 0;
1872         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1873         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1874
1875         /* Don't attempt to re-create the ring group if it is already created */
1876         if (bp->grp_info[idx].fw_grp_id != INVALID_HW_RING_ID)
1877                 return 0;
1878
1879         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1880
1881         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1882         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1883         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1884         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1885
1886         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1887
1888         HWRM_CHECK_RESULT();
1889
1890         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1891
1892         HWRM_UNLOCK();
1893
1894         return rc;
1895 }
1896
1897 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1898 {
1899         int rc;
1900         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1901         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1902
1903         if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1904                 return 0;
1905
1906         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1907
1908         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1909
1910         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1911
1912         HWRM_CHECK_RESULT();
1913         HWRM_UNLOCK();
1914
1915         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1916         return rc;
1917 }
1918
1919 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1920 {
1921         int rc = 0;
1922         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1923         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1924
1925         if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
1926                 return rc;
1927
1928         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1929
1930         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1931
1932         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1933
1934         HWRM_CHECK_RESULT();
1935         HWRM_UNLOCK();
1936
1937         return rc;
1938 }
1939
1940 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1941 {
1942         int rc;
1943         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1944         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1945
1946         if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE)
1947                 return 0;
1948
1949         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1950
1951         req.update_period_ms = rte_cpu_to_le_32(0);
1952
1953         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1954
1955         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1956
1957         HWRM_CHECK_RESULT();
1958
1959         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1960
1961         HWRM_UNLOCK();
1962
1963         return rc;
1964 }
1965
1966 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1967 {
1968         int rc;
1969         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1970         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1971
1972         if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
1973                 return 0;
1974
1975         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1976
1977         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1978
1979         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1980
1981         HWRM_CHECK_RESULT();
1982         HWRM_UNLOCK();
1983
1984         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1985
1986         return rc;
1987 }
1988
1989 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1990 {
1991         int rc = 0, i, j;
1992         struct hwrm_vnic_alloc_input req = { 0 };
1993         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1994
1995         if (!BNXT_HAS_RING_GRPS(bp))
1996                 goto skip_ring_grps;
1997
1998         /* map ring groups to this vnic */
1999         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
2000                 vnic->start_grp_id, vnic->end_grp_id);
2001         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
2002                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
2003
2004         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
2005         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
2006         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
2007         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
2008
2009 skip_ring_grps:
2010         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
2011         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
2012
2013         if (vnic->func_default)
2014                 req.flags =
2015                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
2016         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2017
2018         HWRM_CHECK_RESULT();
2019
2020         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
2021         HWRM_UNLOCK();
2022         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2023         return rc;
2024 }
2025
2026 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
2027                                         struct bnxt_vnic_info *vnic,
2028                                         struct bnxt_plcmodes_cfg *pmode)
2029 {
2030         int rc = 0;
2031         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
2032         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2033
2034         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
2035
2036         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2037
2038         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2039
2040         HWRM_CHECK_RESULT();
2041
2042         pmode->flags = rte_le_to_cpu_32(resp->flags);
2043         /* dflt_vnic bit doesn't exist in the _cfg command */
2044         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
2045         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
2046         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2047         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2048
2049         HWRM_UNLOCK();
2050
2051         return rc;
2052 }
2053
2054 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2055                                        struct bnxt_vnic_info *vnic,
2056                                        struct bnxt_plcmodes_cfg *pmode)
2057 {
2058         int rc = 0;
2059         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2060         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2061
2062         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2063                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2064                 return rc;
2065         }
2066
2067         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2068
2069         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2070         req.flags = rte_cpu_to_le_32(pmode->flags);
2071         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2072         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2073         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2074         req.enables = rte_cpu_to_le_32(
2075             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2076             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2077             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2078         );
2079
2080         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2081
2082         HWRM_CHECK_RESULT();
2083         HWRM_UNLOCK();
2084
2085         return rc;
2086 }
2087
2088 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2089 {
2090         int rc = 0;
2091         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2092         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2093         struct bnxt_plcmodes_cfg pmodes = { 0 };
2094         uint32_t ctx_enable_flag = 0;
2095         uint32_t enables = 0;
2096
2097         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2098                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2099                 return rc;
2100         }
2101
2102         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2103         if (rc)
2104                 return rc;
2105
2106         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2107
2108         if (BNXT_CHIP_P5(bp)) {
2109                 int dflt_rxq = vnic->start_grp_id;
2110                 struct bnxt_rx_ring_info *rxr;
2111                 struct bnxt_cp_ring_info *cpr;
2112                 struct bnxt_rx_queue *rxq;
2113                 int i;
2114
2115                 /*
2116                  * The first active receive ring is used as the VNIC
2117                  * default receive ring. If there are no active receive
2118                  * rings (all corresponding receive queues are stopped),
2119                  * the first receive ring is used.
2120                  */
2121                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2122                         rxq = bp->eth_dev->data->rx_queues[i];
2123                         if (rxq->rx_started) {
2124                                 dflt_rxq = i;
2125                                 break;
2126                         }
2127                 }
2128
2129                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2130                 rxr = rxq->rx_ring;
2131                 cpr = rxq->cp_ring;
2132
2133                 req.default_rx_ring_id =
2134                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2135                 req.default_cmpl_ring_id =
2136                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2137                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2138                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2139                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2140                         enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2141                         req.rx_csum_v2_mode =
2142                                 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2143                 }
2144                 goto config_mru;
2145         }
2146
2147         /* Only RSS support for now TBD: COS & LB */
2148         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2149         if (vnic->lb_rule != 0xffff)
2150                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2151         if (vnic->cos_rule != 0xffff)
2152                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2153         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2154                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2155                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2156         }
2157         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2158                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2159                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2160         }
2161
2162         enables |= ctx_enable_flag;
2163         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2164         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2165         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2166         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2167
2168 config_mru:
2169         req.enables = rte_cpu_to_le_32(enables);
2170         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2171         req.mru = rte_cpu_to_le_16(vnic->mru);
2172         /* Configure default VNIC only once. */
2173         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2174                 req.flags |=
2175                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2176                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2177         }
2178         if (vnic->vlan_strip)
2179                 req.flags |=
2180                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2181         if (vnic->bd_stall)
2182                 req.flags |=
2183                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2184         if (vnic->rss_dflt_cr)
2185                 req.flags |= rte_cpu_to_le_32(
2186                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2187
2188         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2189
2190         HWRM_CHECK_RESULT();
2191         HWRM_UNLOCK();
2192
2193         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2194
2195         return rc;
2196 }
2197
2198 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2199                 int16_t fw_vf_id)
2200 {
2201         int rc = 0;
2202         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2203         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2204
2205         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2206                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2207                 return rc;
2208         }
2209         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2210
2211         req.enables =
2212                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2213         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2214         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2215
2216         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2217
2218         HWRM_CHECK_RESULT();
2219
2220         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2221         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2222         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2223         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2224         vnic->mru = rte_le_to_cpu_16(resp->mru);
2225         vnic->func_default = rte_le_to_cpu_32(
2226                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2227         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2228                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2229         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2230                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2231         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2232                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2233
2234         HWRM_UNLOCK();
2235
2236         return rc;
2237 }
2238
2239 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2240                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2241 {
2242         int rc = 0;
2243         uint16_t ctx_id;
2244         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2245         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2246                                                 bp->hwrm_cmd_resp_addr;
2247
2248         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2249
2250         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2251         HWRM_CHECK_RESULT();
2252
2253         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2254         if (!BNXT_HAS_RING_GRPS(bp))
2255                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2256         else if (ctx_idx == 0)
2257                 vnic->rss_rule = ctx_id;
2258
2259         HWRM_UNLOCK();
2260
2261         return rc;
2262 }
2263
2264 static
2265 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2266                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2267 {
2268         int rc = 0;
2269         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2270         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2271                                                 bp->hwrm_cmd_resp_addr;
2272
2273         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2274                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2275                 return rc;
2276         }
2277         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2278
2279         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2280
2281         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2282
2283         HWRM_CHECK_RESULT();
2284         HWRM_UNLOCK();
2285
2286         return rc;
2287 }
2288
2289 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2290 {
2291         int rc = 0;
2292
2293         if (BNXT_CHIP_P5(bp)) {
2294                 int j;
2295
2296                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2297                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2298                                                       vnic,
2299                                                       vnic->fw_grp_ids[j]);
2300                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2301                 }
2302                 vnic->num_lb_ctxts = 0;
2303         } else {
2304                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2305                 vnic->rss_rule = INVALID_HW_RING_ID;
2306         }
2307
2308         return rc;
2309 }
2310
2311 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2312 {
2313         int rc = 0;
2314         struct hwrm_vnic_free_input req = {.req_type = 0 };
2315         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2316
2317         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2318                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2319                 return rc;
2320         }
2321
2322         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2323
2324         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2325
2326         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2327
2328         HWRM_CHECK_RESULT();
2329         HWRM_UNLOCK();
2330
2331         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2332         /* Configure default VNIC again if necessary. */
2333         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2334                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2335
2336         return rc;
2337 }
2338
2339 static int
2340 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2341 {
2342         int i;
2343         int rc = 0;
2344         int nr_ctxs = vnic->num_lb_ctxts;
2345         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2346         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2347
2348         for (i = 0; i < nr_ctxs; i++) {
2349                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2350
2351                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2352                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2353                 req.hash_mode_flags = vnic->hash_mode;
2354
2355                 req.hash_key_tbl_addr =
2356                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2357
2358                 req.ring_grp_tbl_addr =
2359                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2360                                          i * HW_HASH_INDEX_SIZE);
2361                 req.ring_table_pair_index = i;
2362                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2363
2364                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2365                                             BNXT_USE_CHIMP_MB);
2366
2367                 HWRM_CHECK_RESULT();
2368                 HWRM_UNLOCK();
2369         }
2370
2371         return rc;
2372 }
2373
2374 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2375                            struct bnxt_vnic_info *vnic)
2376 {
2377         int rc = 0;
2378         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2379         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2380
2381         if (!vnic->rss_table)
2382                 return 0;
2383
2384         if (BNXT_CHIP_P5(bp))
2385                 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2386
2387         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2388
2389         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2390         req.hash_mode_flags = vnic->hash_mode;
2391
2392         req.ring_grp_tbl_addr =
2393             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2394         req.hash_key_tbl_addr =
2395             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2396         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2397         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2398
2399         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2400
2401         HWRM_CHECK_RESULT();
2402         HWRM_UNLOCK();
2403
2404         return rc;
2405 }
2406
2407 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2408                         struct bnxt_vnic_info *vnic)
2409 {
2410         int rc = 0;
2411         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2412         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2413         uint16_t size;
2414
2415         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2416                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2417                 return rc;
2418         }
2419
2420         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2421
2422         req.flags = rte_cpu_to_le_32(
2423                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2424
2425         req.enables = rte_cpu_to_le_32(
2426                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2427
2428         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2429         size -= RTE_PKTMBUF_HEADROOM;
2430         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2431
2432         req.jumbo_thresh = rte_cpu_to_le_16(size);
2433         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2434
2435         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2436
2437         HWRM_CHECK_RESULT();
2438         HWRM_UNLOCK();
2439
2440         return rc;
2441 }
2442
2443 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2444                         struct bnxt_vnic_info *vnic, bool enable)
2445 {
2446         int rc = 0;
2447         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2448         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2449
2450         if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2451                 if (enable)
2452                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2453                 return -ENOTSUP;
2454         }
2455
2456         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2457                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2458                 return 0;
2459         }
2460
2461         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2462
2463         if (enable) {
2464                 req.enables = rte_cpu_to_le_32(
2465                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2466                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2467                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2468                 req.flags = rte_cpu_to_le_32(
2469                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2470                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2471                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2472                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2473                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2474                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2475                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2476                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2477                 req.min_agg_len = rte_cpu_to_le_32(512);
2478         }
2479         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2480
2481         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2482
2483         HWRM_CHECK_RESULT();
2484         HWRM_UNLOCK();
2485
2486         return rc;
2487 }
2488
2489 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2490 {
2491         struct hwrm_func_cfg_input req = {0};
2492         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2493         int rc;
2494
2495         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2496         req.enables = rte_cpu_to_le_32(
2497                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2498         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2499         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2500
2501         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2502
2503         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2504         HWRM_CHECK_RESULT();
2505         HWRM_UNLOCK();
2506
2507         bp->pf->vf_info[vf].random_mac = false;
2508
2509         return rc;
2510 }
2511
2512 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2513                                   uint64_t *dropped)
2514 {
2515         int rc = 0;
2516         struct hwrm_func_qstats_input req = {.req_type = 0};
2517         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2518
2519         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2520
2521         req.fid = rte_cpu_to_le_16(fid);
2522
2523         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2524
2525         HWRM_CHECK_RESULT();
2526
2527         if (dropped)
2528                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2529
2530         HWRM_UNLOCK();
2531
2532         return rc;
2533 }
2534
2535 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2536                           struct rte_eth_stats *stats,
2537                           struct hwrm_func_qstats_output *func_qstats)
2538 {
2539         int rc = 0;
2540         struct hwrm_func_qstats_input req = {.req_type = 0};
2541         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2542
2543         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2544
2545         req.fid = rte_cpu_to_le_16(fid);
2546
2547         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2548
2549         HWRM_CHECK_RESULT();
2550         if (func_qstats)
2551                 memcpy(func_qstats, resp,
2552                        sizeof(struct hwrm_func_qstats_output));
2553
2554         if (!stats)
2555                 goto exit;
2556
2557         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2558         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2559         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2560         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2561         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2562         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2563
2564         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2565         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2566         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2567         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2568         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2569         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2570
2571         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2572         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2573         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2574
2575 exit:
2576         HWRM_UNLOCK();
2577
2578         return rc;
2579 }
2580
2581 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2582 {
2583         int rc = 0;
2584         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2585         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2586
2587         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2588
2589         req.fid = rte_cpu_to_le_16(fid);
2590
2591         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2592
2593         HWRM_CHECK_RESULT();
2594         HWRM_UNLOCK();
2595
2596         return rc;
2597 }
2598
2599 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2600 {
2601         unsigned int i;
2602         int rc = 0;
2603
2604         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2605                 struct bnxt_tx_queue *txq;
2606                 struct bnxt_rx_queue *rxq;
2607                 struct bnxt_cp_ring_info *cpr;
2608
2609                 if (i >= bp->rx_cp_nr_rings) {
2610                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2611                         cpr = txq->cp_ring;
2612                 } else {
2613                         rxq = bp->rx_queues[i];
2614                         cpr = rxq->cp_ring;
2615                 }
2616
2617                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2618                 if (rc)
2619                         return rc;
2620         }
2621         return 0;
2622 }
2623
2624 static int
2625 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2626 {
2627         int rc;
2628         unsigned int i;
2629         struct bnxt_cp_ring_info *cpr;
2630
2631         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2632
2633                 cpr = bp->rx_queues[i]->cp_ring;
2634                 if (BNXT_HAS_RING_GRPS(bp))
2635                         bp->grp_info[i].fw_stats_ctx = -1;
2636                 if (cpr == NULL)
2637                         continue;
2638                 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2639                 if (rc)
2640                         return rc;
2641         }
2642
2643         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2644                 cpr = bp->tx_queues[i]->cp_ring;
2645                 if (cpr == NULL)
2646                         continue;
2647                 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2648                 if (rc)
2649                         return rc;
2650         }
2651
2652         return 0;
2653 }
2654
2655 static int
2656 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2657 {
2658         uint16_t idx;
2659         uint32_t rc = 0;
2660
2661         if (!BNXT_HAS_RING_GRPS(bp))
2662                 return 0;
2663
2664         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2665
2666                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2667                         continue;
2668
2669                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2670
2671                 if (rc)
2672                         return rc;
2673         }
2674         return rc;
2675 }
2676
2677 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2678 {
2679         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2680
2681         bnxt_hwrm_ring_free(bp, cp_ring,
2682                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2683                             INVALID_HW_RING_ID);
2684         memset(cpr->cp_desc_ring, 0,
2685                cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
2686         cpr->cp_raw_cons = 0;
2687 }
2688
2689 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2690 {
2691         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2692
2693         bnxt_hwrm_ring_free(bp, cp_ring,
2694                             HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2695                             INVALID_HW_RING_ID);
2696         memset(cpr->cp_desc_ring, 0,
2697                cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
2698         cpr->cp_raw_cons = 0;
2699 }
2700
2701 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2702 {
2703         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2704         struct bnxt_rx_ring_info *rxr = rxq ? rxq->rx_ring : NULL;
2705         struct bnxt_ring *ring = rxr ? rxr->rx_ring_struct : NULL;
2706         struct bnxt_cp_ring_info *cpr = rxq ? rxq->cp_ring : NULL;
2707
2708         if (BNXT_HAS_RING_GRPS(bp))
2709                 bnxt_hwrm_ring_grp_free(bp, queue_index);
2710
2711         if (ring != NULL && cpr != NULL)
2712                 bnxt_hwrm_ring_free(bp, ring,
2713                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2714                                     cpr->cp_ring_struct->fw_ring_id);
2715         if (BNXT_HAS_RING_GRPS(bp))
2716                 bp->grp_info[queue_index].rx_fw_ring_id = INVALID_HW_RING_ID;
2717
2718         /* Check agg ring struct explicitly.
2719          * bnxt_need_agg_ring() returns the current state of offload flags,
2720          * but we may have to deal with agg ring struct before the offload
2721          * flags are updated.
2722          */
2723         if (!bnxt_need_agg_ring(bp->eth_dev) ||
2724             (rxr && rxr->ag_ring_struct == NULL))
2725                 goto no_agg;
2726
2727         ring = rxr ? rxr->ag_ring_struct : NULL;
2728         if (ring != NULL && cpr != NULL) {
2729                 bnxt_hwrm_ring_free(bp, ring,
2730                                     BNXT_CHIP_P5(bp) ?
2731                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2732                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2733                                     cpr->cp_ring_struct->fw_ring_id);
2734         }
2735         if (BNXT_HAS_RING_GRPS(bp))
2736                 bp->grp_info[queue_index].ag_fw_ring_id = INVALID_HW_RING_ID;
2737
2738 no_agg:
2739         if (cpr != NULL) {
2740                 bnxt_hwrm_stat_ctx_free(bp, cpr);
2741                 bnxt_free_cp_ring(bp, cpr);
2742         }
2743
2744         if (BNXT_HAS_RING_GRPS(bp))
2745                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2746 }
2747
2748 int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int queue_index)
2749 {
2750         int rc;
2751         struct hwrm_ring_reset_input req = {.req_type = 0 };
2752         struct hwrm_ring_reset_output *resp = bp->hwrm_cmd_resp_addr;
2753
2754         HWRM_PREP(&req, HWRM_RING_RESET, BNXT_USE_CHIMP_MB);
2755
2756         req.ring_type = HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP;
2757         req.ring_id = rte_cpu_to_le_16(bp->grp_info[queue_index].fw_grp_id);
2758         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2759
2760         HWRM_CHECK_RESULT();
2761
2762         HWRM_UNLOCK();
2763
2764         return rc;
2765 }
2766
2767 static int
2768 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2769 {
2770         unsigned int i;
2771
2772         for (i = 0; i < bp->tx_cp_nr_rings; i++)
2773                 bnxt_free_hwrm_tx_ring(bp, i);
2774
2775         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2776                 bnxt_free_hwrm_rx_ring(bp, i);
2777
2778         return 0;
2779 }
2780
2781 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2782 {
2783         uint16_t i;
2784         uint32_t rc = 0;
2785
2786         if (!BNXT_HAS_RING_GRPS(bp))
2787                 return 0;
2788
2789         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2790                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2791                 if (rc)
2792                         return rc;
2793         }
2794         return rc;
2795 }
2796
2797 /*
2798  * HWRM utility functions
2799  */
2800
2801 void bnxt_free_hwrm_resources(struct bnxt *bp)
2802 {
2803         /* Release memzone */
2804         rte_free(bp->hwrm_cmd_resp_addr);
2805         rte_free(bp->hwrm_short_cmd_req_addr);
2806         bp->hwrm_cmd_resp_addr = NULL;
2807         bp->hwrm_short_cmd_req_addr = NULL;
2808         bp->hwrm_cmd_resp_dma_addr = 0;
2809         bp->hwrm_short_cmd_req_dma_addr = 0;
2810 }
2811
2812 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2813 {
2814         struct rte_pci_device *pdev = bp->pdev;
2815         char type[RTE_MEMZONE_NAMESIZE];
2816
2817         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2818                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2819         bp->max_resp_len = BNXT_PAGE_SIZE;
2820         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2821         if (bp->hwrm_cmd_resp_addr == NULL)
2822                 return -ENOMEM;
2823         bp->hwrm_cmd_resp_dma_addr =
2824                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2825         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2826                 PMD_DRV_LOG(ERR,
2827                         "unable to map response address to physical memory\n");
2828                 return -ENOMEM;
2829         }
2830         rte_spinlock_init(&bp->hwrm_lock);
2831
2832         return 0;
2833 }
2834
2835 int
2836 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2837 {
2838         int rc = 0;
2839
2840         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2841                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2842                 if (rc)
2843                         return rc;
2844         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2845                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2846                 if (rc)
2847                         return rc;
2848         }
2849
2850         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2851         return rc;
2852 }
2853
2854 static int
2855 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2856 {
2857         struct bnxt_filter_info *filter;
2858         int rc = 0;
2859
2860         STAILQ_FOREACH(filter, &vnic->filter, next) {
2861                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2862                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2863                 bnxt_free_filter(bp, filter);
2864         }
2865         return rc;
2866 }
2867
2868 static int
2869 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2870 {
2871         struct bnxt_filter_info *filter;
2872         struct rte_flow *flow;
2873         int rc = 0;
2874
2875         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2876                 flow = STAILQ_FIRST(&vnic->flow_list);
2877                 filter = flow->filter;
2878                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2879                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2880
2881                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2882                 rte_free(flow);
2883         }
2884         return rc;
2885 }
2886
2887 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2888 {
2889         struct bnxt_filter_info *filter;
2890         int rc = 0;
2891
2892         STAILQ_FOREACH(filter, &vnic->filter, next) {
2893                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2894                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2895                                                      filter);
2896                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2897                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2898                                                          filter);
2899                 else
2900                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2901                                                      filter);
2902                 if (rc)
2903                         break;
2904         }
2905         return rc;
2906 }
2907
2908 static void
2909 bnxt_free_tunnel_ports(struct bnxt *bp)
2910 {
2911         if (bp->vxlan_port_cnt)
2912                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2913                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2914
2915         if (bp->geneve_port_cnt)
2916                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2917                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2918 }
2919
2920 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2921 {
2922         int i;
2923
2924         if (bp->vnic_info == NULL)
2925                 return;
2926
2927         /*
2928          * Cleanup VNICs in reverse order, to make sure the L2 filter
2929          * from vnic0 is last to be cleaned up.
2930          */
2931         for (i = bp->max_vnics - 1; i >= 0; i--) {
2932                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2933
2934                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2935                         continue;
2936
2937                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2938
2939                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2940
2941                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2942
2943                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2944
2945                 bnxt_hwrm_vnic_free(bp, vnic);
2946
2947                 rte_free(vnic->fw_grp_ids);
2948         }
2949         /* Ring resources */
2950         bnxt_free_all_hwrm_rings(bp);
2951         bnxt_free_all_hwrm_ring_grps(bp);
2952         bnxt_free_all_hwrm_stat_ctxs(bp);
2953         bnxt_free_tunnel_ports(bp);
2954 }
2955
2956 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2957 {
2958         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2959
2960         if ((conf_link_speed & RTE_ETH_LINK_SPEED_FIXED) == RTE_ETH_LINK_SPEED_AUTONEG)
2961                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2962
2963         switch (conf_link_speed) {
2964         case RTE_ETH_LINK_SPEED_10M_HD:
2965         case RTE_ETH_LINK_SPEED_100M_HD:
2966                 /* FALLTHROUGH */
2967                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2968         }
2969         return hw_link_duplex;
2970 }
2971
2972 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2973 {
2974         return !conf_link;
2975 }
2976
2977 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2978                                           uint16_t pam4_link)
2979 {
2980         uint16_t eth_link_speed = 0;
2981
2982         if (conf_link_speed == RTE_ETH_LINK_SPEED_AUTONEG)
2983                 return RTE_ETH_LINK_SPEED_AUTONEG;
2984
2985         switch (conf_link_speed & ~RTE_ETH_LINK_SPEED_FIXED) {
2986         case RTE_ETH_LINK_SPEED_100M:
2987         case RTE_ETH_LINK_SPEED_100M_HD:
2988                 /* FALLTHROUGH */
2989                 eth_link_speed =
2990                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2991                 break;
2992         case RTE_ETH_LINK_SPEED_1G:
2993                 eth_link_speed =
2994                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2995                 break;
2996         case RTE_ETH_LINK_SPEED_2_5G:
2997                 eth_link_speed =
2998                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2999                 break;
3000         case RTE_ETH_LINK_SPEED_10G:
3001                 eth_link_speed =
3002                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
3003                 break;
3004         case RTE_ETH_LINK_SPEED_20G:
3005                 eth_link_speed =
3006                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
3007                 break;
3008         case RTE_ETH_LINK_SPEED_25G:
3009                 eth_link_speed =
3010                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
3011                 break;
3012         case RTE_ETH_LINK_SPEED_40G:
3013                 eth_link_speed =
3014                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
3015                 break;
3016         case RTE_ETH_LINK_SPEED_50G:
3017                 eth_link_speed = pam4_link ?
3018                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
3019                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
3020                 break;
3021         case RTE_ETH_LINK_SPEED_100G:
3022                 eth_link_speed = pam4_link ?
3023                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
3024                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
3025                 break;
3026         case RTE_ETH_LINK_SPEED_200G:
3027                 eth_link_speed =
3028                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3029                 break;
3030         default:
3031                 PMD_DRV_LOG(ERR,
3032                         "Unsupported link speed %d; default to AUTO\n",
3033                         conf_link_speed);
3034                 break;
3035         }
3036         return eth_link_speed;
3037 }
3038
3039 #define BNXT_SUPPORTED_SPEEDS (RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_100M_HD | \
3040                 RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_2_5G | \
3041                 RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_20G | RTE_ETH_LINK_SPEED_25G | \
3042                 RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_50G | \
3043                 RTE_ETH_LINK_SPEED_100G | RTE_ETH_LINK_SPEED_200G)
3044
3045 static int bnxt_validate_link_speed(struct bnxt *bp)
3046 {
3047         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3048         uint16_t port_id = bp->eth_dev->data->port_id;
3049         uint32_t link_speed_capa;
3050         uint32_t one_speed;
3051
3052         if (link_speed == RTE_ETH_LINK_SPEED_AUTONEG)
3053                 return 0;
3054
3055         link_speed_capa = bnxt_get_speed_capabilities(bp);
3056
3057         if (link_speed & RTE_ETH_LINK_SPEED_FIXED) {
3058                 one_speed = link_speed & ~RTE_ETH_LINK_SPEED_FIXED;
3059
3060                 if (one_speed & (one_speed - 1)) {
3061                         PMD_DRV_LOG(ERR,
3062                                 "Invalid advertised speeds (%u) for port %u\n",
3063                                 link_speed, port_id);
3064                         return -EINVAL;
3065                 }
3066                 if ((one_speed & link_speed_capa) != one_speed) {
3067                         PMD_DRV_LOG(ERR,
3068                                 "Unsupported advertised speed (%u) for port %u\n",
3069                                 link_speed, port_id);
3070                         return -EINVAL;
3071                 }
3072         } else {
3073                 if (!(link_speed & link_speed_capa)) {
3074                         PMD_DRV_LOG(ERR,
3075                                 "Unsupported advertised speeds (%u) for port %u\n",
3076                                 link_speed, port_id);
3077                         return -EINVAL;
3078                 }
3079         }
3080         return 0;
3081 }
3082
3083 static uint16_t
3084 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3085 {
3086         uint16_t ret = 0;
3087
3088         if (link_speed == RTE_ETH_LINK_SPEED_AUTONEG) {
3089                 if (bp->link_info->support_speeds)
3090                         return bp->link_info->support_speeds;
3091                 link_speed = BNXT_SUPPORTED_SPEEDS;
3092         }
3093
3094         if (link_speed & RTE_ETH_LINK_SPEED_100M)
3095                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3096         if (link_speed & RTE_ETH_LINK_SPEED_100M_HD)
3097                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3098         if (link_speed & RTE_ETH_LINK_SPEED_1G)
3099                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3100         if (link_speed & RTE_ETH_LINK_SPEED_2_5G)
3101                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3102         if (link_speed & RTE_ETH_LINK_SPEED_10G)
3103                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3104         if (link_speed & RTE_ETH_LINK_SPEED_20G)
3105                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3106         if (link_speed & RTE_ETH_LINK_SPEED_25G)
3107                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3108         if (link_speed & RTE_ETH_LINK_SPEED_40G)
3109                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3110         if (link_speed & RTE_ETH_LINK_SPEED_50G)
3111                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3112         if (link_speed & RTE_ETH_LINK_SPEED_100G)
3113                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3114         if (link_speed & RTE_ETH_LINK_SPEED_200G)
3115                 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3116         return ret;
3117 }
3118
3119 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3120 {
3121         uint32_t eth_link_speed = RTE_ETH_SPEED_NUM_NONE;
3122
3123         switch (hw_link_speed) {
3124         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3125                 eth_link_speed = RTE_ETH_SPEED_NUM_100M;
3126                 break;
3127         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3128                 eth_link_speed = RTE_ETH_SPEED_NUM_1G;
3129                 break;
3130         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3131                 eth_link_speed = RTE_ETH_SPEED_NUM_2_5G;
3132                 break;
3133         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3134                 eth_link_speed = RTE_ETH_SPEED_NUM_10G;
3135                 break;
3136         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3137                 eth_link_speed = RTE_ETH_SPEED_NUM_20G;
3138                 break;
3139         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3140                 eth_link_speed = RTE_ETH_SPEED_NUM_25G;
3141                 break;
3142         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3143                 eth_link_speed = RTE_ETH_SPEED_NUM_40G;
3144                 break;
3145         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3146                 eth_link_speed = RTE_ETH_SPEED_NUM_50G;
3147                 break;
3148         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3149                 eth_link_speed = RTE_ETH_SPEED_NUM_100G;
3150                 break;
3151         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3152                 eth_link_speed = RTE_ETH_SPEED_NUM_200G;
3153                 break;
3154         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3155         default:
3156                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3157                         hw_link_speed);
3158                 break;
3159         }
3160         return eth_link_speed;
3161 }
3162
3163 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3164 {
3165         uint16_t eth_link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
3166
3167         switch (hw_link_duplex) {
3168         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3169         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3170                 /* FALLTHROUGH */
3171                 eth_link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
3172                 break;
3173         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3174                 eth_link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
3175                 break;
3176         default:
3177                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3178                         hw_link_duplex);
3179                 break;
3180         }
3181         return eth_link_duplex;
3182 }
3183
3184 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3185 {
3186         int rc = 0;
3187         struct bnxt_link_info *link_info = bp->link_info;
3188
3189         rc = bnxt_hwrm_port_phy_qcaps(bp);
3190         if (rc)
3191                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3192
3193         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3194         if (rc) {
3195                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3196                 goto exit;
3197         }
3198
3199         if (link_info->link_speed)
3200                 link->link_speed =
3201                         bnxt_parse_hw_link_speed(link_info->link_speed);
3202         else
3203                 link->link_speed = RTE_ETH_SPEED_NUM_NONE;
3204         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3205         link->link_status = link_info->link_up;
3206         link->link_autoneg = link_info->auto_mode ==
3207                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3208                 RTE_ETH_LINK_FIXED : RTE_ETH_LINK_AUTONEG;
3209 exit:
3210         return rc;
3211 }
3212
3213 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3214 {
3215         int rc = 0;
3216         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3217         struct bnxt_link_info link_req;
3218         uint16_t speed, autoneg;
3219
3220         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3221                 return 0;
3222
3223         rc = bnxt_validate_link_speed(bp);
3224         if (rc)
3225                 goto error;
3226
3227         memset(&link_req, 0, sizeof(link_req));
3228         link_req.link_up = link_up;
3229         if (!link_up)
3230                 goto port_phy_cfg;
3231
3232         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3233         if (BNXT_CHIP_P5(bp) &&
3234             dev_conf->link_speeds == RTE_ETH_LINK_SPEED_40G) {
3235                 /* 40G is not supported as part of media auto detect.
3236                  * The speed should be forced and autoneg disabled
3237                  * to configure 40G speed.
3238                  */
3239                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3240                 autoneg = 0;
3241         }
3242
3243         /* No auto speeds and no auto_pam4_link. Disable autoneg */
3244         if (bp->link_info->auto_link_speed == 0 &&
3245             bp->link_info->link_signal_mode &&
3246             bp->link_info->auto_pam4_link_speeds == 0)
3247                 autoneg = 0;
3248
3249         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3250                                           bp->link_info->link_signal_mode);
3251         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3252         /* Autoneg can be done only when the FW allows. */
3253         if (autoneg == 1 && bp->link_info->support_auto_speeds) {
3254                 link_req.phy_flags |=
3255                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3256                 link_req.auto_link_speed_mask =
3257                         bnxt_parse_eth_link_speed_mask(bp,
3258                                                        dev_conf->link_speeds);
3259                 link_req.auto_pam4_link_speeds =
3260                         bp->link_info->auto_pam4_link_speeds;
3261         } else {
3262                 if (bp->link_info->phy_type ==
3263                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3264                     bp->link_info->phy_type ==
3265                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3266                     bp->link_info->media_type ==
3267                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3268                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3269                         return -EINVAL;
3270                 }
3271
3272                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3273                 /* If user wants a particular speed try that first. */
3274                 if (speed)
3275                         link_req.link_speed = speed;
3276                 else if (bp->link_info->force_pam4_link_speed)
3277                         link_req.link_speed =
3278                                 bp->link_info->force_pam4_link_speed;
3279                 else if (bp->link_info->auto_pam4_link_speeds)
3280                         link_req.link_speed =
3281                                 bp->link_info->auto_pam4_link_speeds;
3282                 else if (bp->link_info->support_pam4_speeds)
3283                         link_req.link_speed =
3284                                 bp->link_info->support_pam4_speeds;
3285                 else if (bp->link_info->force_link_speed)
3286                         link_req.link_speed = bp->link_info->force_link_speed;
3287                 else
3288                         link_req.link_speed = bp->link_info->auto_link_speed;
3289                 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3290                  * zero. Use the auto_link_speed.
3291                  */
3292                 if (bp->link_info->auto_link_speed != 0 &&
3293                     bp->link_info->auto_pam4_link_speeds == 0)
3294                         link_req.link_speed = bp->link_info->auto_link_speed;
3295         }
3296         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3297         link_req.auto_pause = bp->link_info->auto_pause;
3298         link_req.force_pause = bp->link_info->force_pause;
3299
3300 port_phy_cfg:
3301         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3302         if (rc) {
3303                 PMD_DRV_LOG(ERR,
3304                         "Set link config failed with rc %d\n", rc);
3305         }
3306
3307 error:
3308         return rc;
3309 }
3310
3311 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3312 {
3313         struct hwrm_func_qcfg_input req = {0};
3314         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3315         uint16_t flags;
3316         int rc = 0;
3317         bp->func_svif = BNXT_SVIF_INVALID;
3318         uint16_t svif_info;
3319
3320         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3321         req.fid = rte_cpu_to_le_16(0xffff);
3322
3323         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3324
3325         HWRM_CHECK_RESULT();
3326
3327         bp->vlan = rte_le_to_cpu_16(resp->vlan) & RTE_ETH_VLAN_ID_MAX;
3328
3329         svif_info = rte_le_to_cpu_16(resp->svif_info);
3330         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3331                 bp->func_svif = svif_info &
3332                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3333
3334         flags = rte_le_to_cpu_16(resp->flags);
3335         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3336                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3337
3338         if (BNXT_VF(bp) &&
3339             !BNXT_VF_IS_TRUSTED(bp) &&
3340             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3341                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3342                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3343         } else if (BNXT_VF(bp) &&
3344                    BNXT_VF_IS_TRUSTED(bp) &&
3345                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3346                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3347                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3348         }
3349
3350         if (mtu)
3351                 *mtu = rte_le_to_cpu_16(resp->admin_mtu);
3352
3353         switch (resp->port_partition_type) {
3354         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3355         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3356         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3357                 /* FALLTHROUGH */
3358                 bp->flags |= BNXT_FLAG_NPAR_PF;
3359                 break;
3360         default:
3361                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3362                 break;
3363         }
3364
3365         bp->legacy_db_size =
3366                 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3367
3368         HWRM_UNLOCK();
3369
3370         return rc;
3371 }
3372
3373 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3374 {
3375         struct hwrm_func_qcfg_input req = {0};
3376         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3377         uint16_t flags;
3378         int rc;
3379
3380         if (!BNXT_VF_IS_TRUSTED(bp))
3381                 return 0;
3382
3383         if (!bp->parent)
3384                 return -EINVAL;
3385
3386         bp->parent->fid = BNXT_PF_FID_INVALID;
3387
3388         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3389
3390         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3391
3392         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3393
3394         HWRM_CHECK_RESULT_SILENT();
3395
3396         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3397         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3398         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3399         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3400
3401         flags = rte_le_to_cpu_16(resp->flags);
3402         /* check for the multi-root support */
3403         if (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT) {
3404                 bp->flags2 |= BNXT_FLAGS2_MULTIROOT_EN;
3405                 PMD_DRV_LOG(DEBUG, "PF enabled with multi root capability\n");
3406         }
3407
3408         HWRM_UNLOCK();
3409
3410         return 0;
3411 }
3412
3413 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3414                                  uint16_t *vnic_id, uint16_t *svif)
3415 {
3416         struct hwrm_func_qcfg_input req = {0};
3417         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3418         uint16_t svif_info;
3419         int rc = 0;
3420
3421         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3422         req.fid = rte_cpu_to_le_16(fid);
3423
3424         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3425
3426         HWRM_CHECK_RESULT();
3427
3428         if (vnic_id)
3429                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3430
3431         svif_info = rte_le_to_cpu_16(resp->svif_info);
3432         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3433                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3434
3435         HWRM_UNLOCK();
3436
3437         return rc;
3438 }
3439
3440 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3441 {
3442         struct hwrm_port_mac_qcfg_input req = {0};
3443         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3444         uint16_t port_svif_info;
3445         int rc;
3446
3447         bp->port_svif = BNXT_SVIF_INVALID;
3448
3449         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3450                 return 0;
3451
3452         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3453
3454         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3455
3456         HWRM_CHECK_RESULT_SILENT();
3457
3458         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3459         if (port_svif_info &
3460             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3461                 bp->port_svif = port_svif_info &
3462                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3463
3464         HWRM_UNLOCK();
3465
3466         return 0;
3467 }
3468
3469 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3470                                  struct bnxt_pf_resource_info *pf_resc)
3471 {
3472         struct hwrm_func_cfg_input req = {0};
3473         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3474         uint32_t enables;
3475         int rc;
3476
3477         enables = HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
3478                   HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU |
3479                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3480                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3481                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3482                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3483                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3484                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3485                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3486                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3487
3488         if (BNXT_HAS_RING_GRPS(bp)) {
3489                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3490                 req.num_hw_ring_grps =
3491                         rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3492         } else if (BNXT_HAS_NQ(bp)) {
3493                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3494                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3495         }
3496
3497         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3498         req.admin_mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3499         req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
3500         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3501         req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3502         req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3503         req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3504         req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3505         req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3506         req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3507         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3508         req.fid = rte_cpu_to_le_16(0xffff);
3509         req.enables = rte_cpu_to_le_32(enables);
3510
3511         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3512
3513         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3514
3515         HWRM_CHECK_RESULT();
3516         HWRM_UNLOCK();
3517
3518         return rc;
3519 }
3520
3521 /* min values are the guaranteed resources and max values are subject
3522  * to availability. The strategy for now is to keep both min & max
3523  * values the same.
3524  */
3525 static void
3526 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3527                               struct hwrm_func_vf_resource_cfg_input *req,
3528                               int num_vfs)
3529 {
3530         req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3531                                                (num_vfs + 1));
3532         req->min_rsscos_ctx = req->max_rsscos_ctx;
3533         req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3534         req->min_stat_ctx = req->max_stat_ctx;
3535         req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3536                                                (num_vfs + 1));
3537         req->min_cmpl_rings = req->max_cmpl_rings;
3538         req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3539         req->min_tx_rings = req->max_tx_rings;
3540         req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3541         req->min_rx_rings = req->max_rx_rings;
3542         req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3543         req->min_l2_ctxs = req->max_l2_ctxs;
3544         /* TODO: For now, do not support VMDq/RFS on VFs. */
3545         req->max_vnics = rte_cpu_to_le_16(1);
3546         req->min_vnics = req->max_vnics;
3547         req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3548                                                  (num_vfs + 1));
3549         req->min_hw_ring_grps = req->max_hw_ring_grps;
3550         req->flags =
3551          rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3552 }
3553
3554 static void
3555 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3556                               struct hwrm_func_cfg_input *req,
3557                               int num_vfs)
3558 {
3559         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
3560                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3561                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3562                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3563                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3564                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3565                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3566                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3567                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3568                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3569
3570         req->admin_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3571                                           RTE_ETHER_CRC_LEN + RTE_VLAN_HLEN *
3572                                           BNXT_NUM_VLANS);
3573         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3574         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3575                                                 (num_vfs + 1));
3576         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3577         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3578                                                (num_vfs + 1));
3579         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3580         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3581         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3582         /* TODO: For now, do not support VMDq/RFS on VFs. */
3583         req->num_vnics = rte_cpu_to_le_16(1);
3584         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3585                                                  (num_vfs + 1));
3586 }
3587
3588 /* Update the port wide resource values based on how many resources
3589  * got allocated to the VF.
3590  */
3591 static int bnxt_update_max_resources(struct bnxt *bp,
3592                                      int vf)
3593 {
3594         struct hwrm_func_qcfg_input req = {0};
3595         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3596         int rc;
3597
3598         /* Get the actual allocated values now */
3599         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3600         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3601         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3602         HWRM_CHECK_RESULT();
3603
3604         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3605         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3606         bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3607         bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3608         bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3609         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3610         bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3611
3612         HWRM_UNLOCK();
3613
3614         return 0;
3615 }
3616
3617 /* Update the PF resource values based on how many resources
3618  * got allocated to it.
3619  */
3620 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3621 {
3622         struct hwrm_func_qcfg_input req = {0};
3623         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3624         int rc;
3625
3626         /* Get the actual allocated values now */
3627         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3628         req.fid = rte_cpu_to_le_16(0xffff);
3629         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3630         HWRM_CHECK_RESULT();
3631
3632         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3633         bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3634         bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3635         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3636         bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3637         bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3638         bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3639         bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3640
3641         HWRM_UNLOCK();
3642
3643         return 0;
3644 }
3645
3646 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3647 {
3648         struct hwrm_func_qcfg_input req = {0};
3649         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3650         int rc;
3651
3652         /* Check for zero MAC address */
3653         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3654         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3655         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3656         HWRM_CHECK_RESULT();
3657         rc = rte_le_to_cpu_16(resp->vlan);
3658
3659         HWRM_UNLOCK();
3660
3661         return rc;
3662 }
3663
3664 static int bnxt_query_pf_resources(struct bnxt *bp,
3665                                    struct bnxt_pf_resource_info *pf_resc)
3666 {
3667         struct hwrm_func_qcfg_input req = {0};
3668         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3669         int rc;
3670
3671         /* And copy the allocated numbers into the pf struct */
3672         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3673         req.fid = rte_cpu_to_le_16(0xffff);
3674         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3675         HWRM_CHECK_RESULT();
3676
3677         pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3678         pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3679         pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3680         pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3681         pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3682         pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3683         pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3684         bp->pf->evb_mode = resp->evb_mode;
3685
3686         HWRM_UNLOCK();
3687
3688         return rc;
3689 }
3690
3691 static void
3692 bnxt_calculate_pf_resources(struct bnxt *bp,
3693                             struct bnxt_pf_resource_info *pf_resc,
3694                             int num_vfs)
3695 {
3696         if (!num_vfs) {
3697                 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3698                 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3699                 pf_resc->num_cp_rings = bp->max_cp_rings;
3700                 pf_resc->num_tx_rings = bp->max_tx_rings;
3701                 pf_resc->num_rx_rings = bp->max_rx_rings;
3702                 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3703                 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3704
3705                 return;
3706         }
3707
3708         pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3709                                    bp->max_rsscos_ctx % (num_vfs + 1);
3710         pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3711                                  bp->max_stat_ctx % (num_vfs + 1);
3712         pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3713                                 bp->max_cp_rings % (num_vfs + 1);
3714         pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3715                                 bp->max_tx_rings % (num_vfs + 1);
3716         pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3717                                 bp->max_rx_rings % (num_vfs + 1);
3718         pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3719                                bp->max_l2_ctx % (num_vfs + 1);
3720         pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3721                                     bp->max_ring_grps % (num_vfs + 1);
3722 }
3723
3724 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3725 {
3726         struct bnxt_pf_resource_info pf_resc = { 0 };
3727         int rc;
3728
3729         if (!BNXT_PF(bp)) {
3730                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3731                 return -EINVAL;
3732         }
3733
3734         rc = bnxt_hwrm_func_qcaps(bp);
3735         if (rc)
3736                 return rc;
3737
3738         bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3739
3740         bp->pf->func_cfg_flags &=
3741                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3742                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3743         bp->pf->func_cfg_flags |=
3744                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3745
3746         rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3747         if (rc)
3748                 return rc;
3749
3750         rc = bnxt_update_max_resources_pf_only(bp);
3751
3752         return rc;
3753 }
3754
3755 static int
3756 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3757 {
3758         size_t req_buf_sz, sz;
3759         int i, rc;
3760
3761         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3762         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3763                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3764         if (bp->pf->vf_req_buf == NULL) {
3765                 return -ENOMEM;
3766         }
3767
3768         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3769                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3770
3771         for (i = 0; i < num_vfs; i++)
3772                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3773                                              (i * HWRM_MAX_REQ_LEN);
3774
3775         rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3776         if (rc)
3777                 rte_free(bp->pf->vf_req_buf);
3778
3779         return rc;
3780 }
3781
3782 static int
3783 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3784 {
3785         struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3786         struct hwrm_func_vf_resource_cfg_input req = {0};
3787         int i, rc = 0;
3788
3789         bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3790         bp->pf->active_vfs = 0;
3791         for (i = 0; i < num_vfs; i++) {
3792                 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3793                 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3794                 rc = bnxt_hwrm_send_message(bp,
3795                                             &req,
3796                                             sizeof(req),
3797                                             BNXT_USE_CHIMP_MB);
3798                 if (rc || resp->error_code) {
3799                         PMD_DRV_LOG(ERR,
3800                                 "Failed to initialize VF %d\n", i);
3801                         PMD_DRV_LOG(ERR,
3802                                 "Not all VFs available. (%d, %d)\n",
3803                                 rc, resp->error_code);
3804                         HWRM_UNLOCK();
3805
3806                         /* If the first VF configuration itself fails,
3807                          * unregister the vf_fwd_request buffer.
3808                          */
3809                         if (i == 0)
3810                                 bnxt_hwrm_func_buf_unrgtr(bp);
3811                         break;
3812                 }
3813                 HWRM_UNLOCK();
3814
3815                 /* Update the max resource values based on the resource values
3816                  * allocated to the VF.
3817                  */
3818                 bnxt_update_max_resources(bp, i);
3819                 bp->pf->active_vfs++;
3820                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3821         }
3822
3823         return 0;
3824 }
3825
3826 static int
3827 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3828 {
3829         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3830         struct hwrm_func_cfg_input req = {0};
3831         int i, rc;
3832
3833         bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3834
3835         bp->pf->active_vfs = 0;
3836         for (i = 0; i < num_vfs; i++) {
3837                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3838                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3839                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3840                 rc = bnxt_hwrm_send_message(bp,
3841                                             &req,
3842                                             sizeof(req),
3843                                             BNXT_USE_CHIMP_MB);
3844
3845                 /* Clear enable flag for next pass */
3846                 req.enables &= ~rte_cpu_to_le_32(
3847                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3848
3849                 if (rc || resp->error_code) {
3850                         PMD_DRV_LOG(ERR,
3851                                 "Failed to initialize VF %d\n", i);
3852                         PMD_DRV_LOG(ERR,
3853                                 "Not all VFs available. (%d, %d)\n",
3854                                 rc, resp->error_code);
3855                         HWRM_UNLOCK();
3856
3857                         /* If the first VF configuration itself fails,
3858                          * unregister the vf_fwd_request buffer.
3859                          */
3860                         if (i == 0)
3861                                 bnxt_hwrm_func_buf_unrgtr(bp);
3862                         break;
3863                 }
3864
3865                 HWRM_UNLOCK();
3866
3867                 /* Update the max resource values based on the resource values
3868                  * allocated to the VF.
3869                  */
3870                 bnxt_update_max_resources(bp, i);
3871                 bp->pf->active_vfs++;
3872                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3873         }
3874
3875         return 0;
3876 }
3877
3878 static void
3879 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3880 {
3881         if (bp->flags & BNXT_FLAG_NEW_RM)
3882                 bnxt_process_vf_resc_config_new(bp, num_vfs);
3883         else
3884                 bnxt_process_vf_resc_config_old(bp, num_vfs);
3885 }
3886
3887 static void
3888 bnxt_update_pf_resources(struct bnxt *bp,
3889                          struct bnxt_pf_resource_info *pf_resc)
3890 {
3891         bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3892         bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3893         bp->max_cp_rings = pf_resc->num_cp_rings;
3894         bp->max_tx_rings = pf_resc->num_tx_rings;
3895         bp->max_rx_rings = pf_resc->num_rx_rings;
3896         bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3897 }
3898
3899 static int32_t
3900 bnxt_configure_pf_resources(struct bnxt *bp,
3901                             struct bnxt_pf_resource_info *pf_resc)
3902 {
3903         /*
3904          * We're using STD_TX_RING_MODE here which will limit the TX
3905          * rings. This will allow QoS to function properly. Not setting this
3906          * will cause PF rings to break bandwidth settings.
3907          */
3908         bp->pf->func_cfg_flags &=
3909                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3910                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3911         bp->pf->func_cfg_flags |=
3912                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3913         return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3914 }
3915
3916 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3917 {
3918         struct bnxt_pf_resource_info pf_resc = { 0 };
3919         int rc;
3920
3921         if (!BNXT_PF(bp)) {
3922                 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3923                 return -EINVAL;
3924         }
3925
3926         rc = bnxt_hwrm_func_qcaps(bp);
3927         if (rc)
3928                 return rc;
3929
3930         bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3931
3932         rc = bnxt_configure_pf_resources(bp, &pf_resc);
3933         if (rc)
3934                 return rc;
3935
3936         rc = bnxt_query_pf_resources(bp, &pf_resc);
3937         if (rc)
3938                 return rc;
3939
3940         /*
3941          * Now, create and register a buffer to hold forwarded VF requests
3942          */
3943         rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3944         if (rc)
3945                 return rc;
3946
3947         bnxt_configure_vf_resources(bp, num_vfs);
3948
3949         bnxt_update_pf_resources(bp, &pf_resc);
3950
3951         return 0;
3952 }
3953
3954 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3955 {
3956         struct hwrm_func_cfg_input req = {0};
3957         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3958         int rc;
3959
3960         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3961
3962         req.fid = rte_cpu_to_le_16(0xffff);
3963         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3964         req.evb_mode = bp->pf->evb_mode;
3965
3966         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3967         HWRM_CHECK_RESULT();
3968         HWRM_UNLOCK();
3969
3970         return rc;
3971 }
3972
3973 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3974                                 uint8_t tunnel_type)
3975 {
3976         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3977         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3978         int rc = 0;
3979
3980         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3981         req.tunnel_type = tunnel_type;
3982         req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3983         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3984         HWRM_CHECK_RESULT();
3985
3986         switch (tunnel_type) {
3987         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3988                 bp->vxlan_fw_dst_port_id =
3989                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3990                 bp->vxlan_port = port;
3991                 break;
3992         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3993                 bp->geneve_fw_dst_port_id =
3994                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3995                 bp->geneve_port = port;
3996                 break;
3997         default:
3998                 break;
3999         }
4000
4001         HWRM_UNLOCK();
4002
4003         return rc;
4004 }
4005
4006 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
4007                                 uint8_t tunnel_type)
4008 {
4009         struct hwrm_tunnel_dst_port_free_input req = {0};
4010         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
4011         int rc = 0;
4012
4013         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
4014
4015         req.tunnel_type = tunnel_type;
4016         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
4017         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4018
4019         HWRM_CHECK_RESULT();
4020         HWRM_UNLOCK();
4021
4022         if (tunnel_type ==
4023             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4024                 bp->vxlan_port = 0;
4025                 bp->vxlan_port_cnt = 0;
4026         }
4027
4028         if (tunnel_type ==
4029             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4030                 bp->geneve_port = 0;
4031                 bp->geneve_port_cnt = 0;
4032         }
4033
4034         return rc;
4035 }
4036
4037 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4038                                         uint32_t flags)
4039 {
4040         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4041         struct hwrm_func_cfg_input req = {0};
4042         int rc;
4043
4044         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4045
4046         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4047         req.flags = rte_cpu_to_le_32(flags);
4048         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4049
4050         HWRM_CHECK_RESULT();
4051         HWRM_UNLOCK();
4052
4053         return rc;
4054 }
4055
4056 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4057 {
4058         uint32_t *flag = flagp;
4059
4060         vnic->flags = *flag;
4061 }
4062
4063 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4064 {
4065         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4066 }
4067
4068 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4069 {
4070         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4071         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4072         int rc;
4073
4074         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4075
4076         req.req_buf_num_pages = rte_cpu_to_le_16(1);
4077         req.req_buf_page_size =
4078                 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4079         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4080         req.req_buf_page_addr0 =
4081                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4082         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4083                 PMD_DRV_LOG(ERR,
4084                         "unable to map buffer address to physical memory\n");
4085                 HWRM_UNLOCK();
4086                 return -ENOMEM;
4087         }
4088
4089         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4090
4091         HWRM_CHECK_RESULT();
4092         HWRM_UNLOCK();
4093
4094         return rc;
4095 }
4096
4097 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4098 {
4099         int rc = 0;
4100         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4101         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4102
4103         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4104                 return 0;
4105
4106         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4107
4108         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4109
4110         HWRM_CHECK_RESULT();
4111         HWRM_UNLOCK();
4112
4113         return rc;
4114 }
4115
4116 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4117 {
4118         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4119         struct hwrm_func_cfg_input req = {0};
4120         int rc;
4121
4122         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4123
4124         req.fid = rte_cpu_to_le_16(0xffff);
4125         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4126         req.enables = rte_cpu_to_le_32(
4127                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4128         req.async_event_cr = rte_cpu_to_le_16(
4129                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4130         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4131
4132         HWRM_CHECK_RESULT();
4133         HWRM_UNLOCK();
4134
4135         return rc;
4136 }
4137
4138 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4139 {
4140         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4141         struct hwrm_func_vf_cfg_input req = {0};
4142         int rc;
4143
4144         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4145
4146         req.enables = rte_cpu_to_le_32(
4147                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4148         req.async_event_cr = rte_cpu_to_le_16(
4149                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4150         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4151
4152         HWRM_CHECK_RESULT();
4153         HWRM_UNLOCK();
4154
4155         return rc;
4156 }
4157
4158 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4159 {
4160         struct hwrm_func_cfg_input req = {0};
4161         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4162         uint16_t dflt_vlan, fid;
4163         uint32_t func_cfg_flags;
4164         int rc = 0;
4165
4166         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4167
4168         if (is_vf) {
4169                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4170                 fid = bp->pf->vf_info[vf].fid;
4171                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4172         } else {
4173                 fid = rte_cpu_to_le_16(0xffff);
4174                 func_cfg_flags = bp->pf->func_cfg_flags;
4175                 dflt_vlan = bp->vlan;
4176         }
4177
4178         req.flags = rte_cpu_to_le_32(func_cfg_flags);
4179         req.fid = rte_cpu_to_le_16(fid);
4180         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4181         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4182
4183         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4184
4185         HWRM_CHECK_RESULT();
4186         HWRM_UNLOCK();
4187
4188         return rc;
4189 }
4190
4191 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4192                         uint16_t max_bw, uint16_t enables)
4193 {
4194         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4195         struct hwrm_func_cfg_input req = {0};
4196         int rc;
4197
4198         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4199
4200         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4201         req.enables |= rte_cpu_to_le_32(enables);
4202         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4203         req.max_bw = rte_cpu_to_le_32(max_bw);
4204         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4205
4206         HWRM_CHECK_RESULT();
4207         HWRM_UNLOCK();
4208
4209         return rc;
4210 }
4211
4212 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4213 {
4214         struct hwrm_func_cfg_input req = {0};
4215         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4216         int rc = 0;
4217
4218         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4219
4220         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4221         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4222         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4223         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4224
4225         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4226
4227         HWRM_CHECK_RESULT();
4228         HWRM_UNLOCK();
4229
4230         return rc;
4231 }
4232
4233 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4234 {
4235         int rc;
4236
4237         if (BNXT_PF(bp))
4238                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4239         else
4240                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4241
4242         return rc;
4243 }
4244
4245 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4246                               void *encaped, size_t ec_size)
4247 {
4248         int rc = 0;
4249         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4250         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4251
4252         if (ec_size > sizeof(req.encap_request))
4253                 return -1;
4254
4255         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4256
4257         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4258         memcpy(req.encap_request, encaped, ec_size);
4259
4260         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4261
4262         HWRM_CHECK_RESULT();
4263         HWRM_UNLOCK();
4264
4265         return rc;
4266 }
4267
4268 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4269                                        struct rte_ether_addr *mac)
4270 {
4271         struct hwrm_func_qcfg_input req = {0};
4272         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4273         int rc;
4274
4275         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4276
4277         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4278         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4279
4280         HWRM_CHECK_RESULT();
4281
4282         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4283
4284         HWRM_UNLOCK();
4285
4286         return rc;
4287 }
4288
4289 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4290                             void *encaped, size_t ec_size)
4291 {
4292         int rc = 0;
4293         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4294         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4295
4296         if (ec_size > sizeof(req.encap_request))
4297                 return -1;
4298
4299         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4300
4301         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4302         memcpy(req.encap_request, encaped, ec_size);
4303
4304         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4305
4306         HWRM_CHECK_RESULT();
4307         HWRM_UNLOCK();
4308
4309         return rc;
4310 }
4311
4312 static void bnxt_update_prev_stat(uint64_t *cntr, uint64_t *prev_cntr)
4313 {
4314         /* One of the HW stat values that make up this counter was zero as
4315          * returned by HW in this iteration, so use the previous
4316          * iteration's counter value
4317          */
4318         if (*prev_cntr && *cntr == 0)
4319                 *cntr = *prev_cntr;
4320         else
4321                 *prev_cntr = *cntr;
4322 }
4323
4324 int bnxt_hwrm_ring_stats(struct bnxt *bp, uint32_t cid, int idx,
4325                          struct bnxt_ring_stats *ring_stats, bool rx)
4326 {
4327         int rc = 0;
4328         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4329         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4330
4331         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4332
4333         req.stat_ctx_id = rte_cpu_to_le_32(cid);
4334
4335         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4336
4337         HWRM_CHECK_RESULT();
4338
4339         if (rx) {
4340                 struct bnxt_ring_stats *prev_stats = &bp->prev_rx_ring_stats[idx];
4341
4342                 ring_stats->rx_ucast_pkts = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4343                 bnxt_update_prev_stat(&ring_stats->rx_ucast_pkts,
4344                                       &prev_stats->rx_ucast_pkts);
4345
4346                 ring_stats->rx_mcast_pkts = rte_le_to_cpu_64(resp->rx_mcast_pkts);
4347                 bnxt_update_prev_stat(&ring_stats->rx_mcast_pkts,
4348                                       &prev_stats->rx_mcast_pkts);
4349
4350                 ring_stats->rx_bcast_pkts = rte_le_to_cpu_64(resp->rx_bcast_pkts);
4351                 bnxt_update_prev_stat(&ring_stats->rx_bcast_pkts,
4352                                       &prev_stats->rx_bcast_pkts);
4353
4354                 ring_stats->rx_ucast_bytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4355                 bnxt_update_prev_stat(&ring_stats->rx_ucast_bytes,
4356                                       &prev_stats->rx_ucast_bytes);
4357
4358                 ring_stats->rx_mcast_bytes = rte_le_to_cpu_64(resp->rx_mcast_bytes);
4359                 bnxt_update_prev_stat(&ring_stats->rx_mcast_bytes,
4360                                       &prev_stats->rx_mcast_bytes);
4361
4362                 ring_stats->rx_bcast_bytes = rte_le_to_cpu_64(resp->rx_bcast_bytes);
4363                 bnxt_update_prev_stat(&ring_stats->rx_bcast_bytes,
4364                                       &prev_stats->rx_bcast_bytes);
4365
4366                 ring_stats->rx_discard_pkts = rte_le_to_cpu_64(resp->rx_discard_pkts);
4367                 bnxt_update_prev_stat(&ring_stats->rx_discard_pkts,
4368                                       &prev_stats->rx_discard_pkts);
4369
4370                 ring_stats->rx_error_pkts = rte_le_to_cpu_64(resp->rx_error_pkts);
4371                 bnxt_update_prev_stat(&ring_stats->rx_error_pkts,
4372                                       &prev_stats->rx_error_pkts);
4373
4374                 ring_stats->rx_agg_pkts = rte_le_to_cpu_64(resp->rx_agg_pkts);
4375                 bnxt_update_prev_stat(&ring_stats->rx_agg_pkts,
4376                                       &prev_stats->rx_agg_pkts);
4377
4378                 ring_stats->rx_agg_bytes = rte_le_to_cpu_64(resp->rx_agg_bytes);
4379                 bnxt_update_prev_stat(&ring_stats->rx_agg_bytes,
4380                                       &prev_stats->rx_agg_bytes);
4381
4382                 ring_stats->rx_agg_events = rte_le_to_cpu_64(resp->rx_agg_events);
4383                 bnxt_update_prev_stat(&ring_stats->rx_agg_events,
4384                                       &prev_stats->rx_agg_events);
4385
4386                 ring_stats->rx_agg_aborts = rte_le_to_cpu_64(resp->rx_agg_aborts);
4387                 bnxt_update_prev_stat(&ring_stats->rx_agg_aborts,
4388                                       &prev_stats->rx_agg_aborts);
4389         } else {
4390                 struct bnxt_ring_stats *prev_stats = &bp->prev_tx_ring_stats[idx];
4391
4392                 ring_stats->tx_ucast_pkts = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4393                 bnxt_update_prev_stat(&ring_stats->tx_ucast_pkts,
4394                                       &prev_stats->tx_ucast_pkts);
4395
4396                 ring_stats->tx_mcast_pkts = rte_le_to_cpu_64(resp->tx_mcast_pkts);
4397                 bnxt_update_prev_stat(&ring_stats->tx_mcast_pkts,
4398                                       &prev_stats->tx_mcast_pkts);
4399
4400                 ring_stats->tx_bcast_pkts = rte_le_to_cpu_64(resp->tx_bcast_pkts);
4401                 bnxt_update_prev_stat(&ring_stats->tx_bcast_pkts,
4402                                       &prev_stats->tx_bcast_pkts);
4403
4404                 ring_stats->tx_ucast_bytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4405                 bnxt_update_prev_stat(&ring_stats->tx_ucast_bytes,
4406                                       &prev_stats->tx_ucast_bytes);
4407
4408                 ring_stats->tx_mcast_bytes = rte_le_to_cpu_64(resp->tx_mcast_bytes);
4409                 bnxt_update_prev_stat(&ring_stats->tx_mcast_bytes,
4410                                       &prev_stats->tx_mcast_bytes);
4411
4412                 ring_stats->tx_bcast_bytes = rte_le_to_cpu_64(resp->tx_bcast_bytes);
4413                 bnxt_update_prev_stat(&ring_stats->tx_bcast_bytes,
4414                                       &prev_stats->tx_bcast_bytes);
4415
4416                 ring_stats->tx_discard_pkts = rte_le_to_cpu_64(resp->tx_discard_pkts);
4417                 bnxt_update_prev_stat(&ring_stats->tx_discard_pkts,
4418                                       &prev_stats->tx_discard_pkts);
4419         }
4420
4421         HWRM_UNLOCK();
4422
4423         return rc;
4424 }
4425
4426 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4427 {
4428         struct hwrm_port_qstats_input req = {0};
4429         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4430         struct bnxt_pf_info *pf = bp->pf;
4431         int rc;
4432
4433         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4434
4435         req.port_id = rte_cpu_to_le_16(pf->port_id);
4436         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4437         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4438         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4439
4440         HWRM_CHECK_RESULT();
4441         HWRM_UNLOCK();
4442
4443         return rc;
4444 }
4445
4446 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4447 {
4448         struct hwrm_port_clr_stats_input req = {0};
4449         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4450         struct bnxt_pf_info *pf = bp->pf;
4451         int rc;
4452
4453         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4454         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4455             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4456                 return 0;
4457
4458         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4459
4460         req.port_id = rte_cpu_to_le_16(pf->port_id);
4461         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4462
4463         HWRM_CHECK_RESULT();
4464         HWRM_UNLOCK();
4465
4466         return rc;
4467 }
4468
4469 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4470 {
4471         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4472         struct hwrm_port_led_qcaps_input req = {0};
4473         int rc;
4474
4475         if (BNXT_VF(bp))
4476                 return 0;
4477
4478         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4479         req.port_id = bp->pf->port_id;
4480         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4481
4482         HWRM_CHECK_RESULT_SILENT();
4483
4484         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4485                 unsigned int i;
4486
4487                 bp->leds->num_leds = resp->num_leds;
4488                 memcpy(bp->leds, &resp->led0_id,
4489                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4490                 for (i = 0; i < bp->leds->num_leds; i++) {
4491                         struct bnxt_led_info *led = &bp->leds[i];
4492
4493                         uint16_t caps = led->led_state_caps;
4494
4495                         if (!led->led_group_id ||
4496                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4497                                 bp->leds->num_leds = 0;
4498                                 break;
4499                         }
4500                 }
4501         }
4502
4503         HWRM_UNLOCK();
4504
4505         return rc;
4506 }
4507
4508 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4509 {
4510         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4511         struct hwrm_port_led_cfg_input req = {0};
4512         struct bnxt_led_cfg *led_cfg;
4513         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4514         uint16_t duration = 0;
4515         int rc, i;
4516
4517         if (!bp->leds->num_leds || BNXT_VF(bp))
4518                 return -EOPNOTSUPP;
4519
4520         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4521
4522         if (led_on) {
4523                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4524                 duration = rte_cpu_to_le_16(500);
4525         }
4526         req.port_id = bp->pf->port_id;
4527         req.num_leds = bp->leds->num_leds;
4528         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4529         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4530                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4531                 led_cfg->led_id = bp->leds[i].led_id;
4532                 led_cfg->led_state = led_state;
4533                 led_cfg->led_blink_on = duration;
4534                 led_cfg->led_blink_off = duration;
4535                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4536         }
4537
4538         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4539
4540         HWRM_CHECK_RESULT();
4541         HWRM_UNLOCK();
4542
4543         return rc;
4544 }
4545
4546 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4547                                uint32_t *length)
4548 {
4549         int rc;
4550         struct hwrm_nvm_get_dir_info_input req = {0};
4551         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4552
4553         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4554
4555         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4556
4557         HWRM_CHECK_RESULT();
4558
4559         *entries = rte_le_to_cpu_32(resp->entries);
4560         *length = rte_le_to_cpu_32(resp->entry_length);
4561
4562         HWRM_UNLOCK();
4563         return rc;
4564 }
4565
4566 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4567 {
4568         int rc;
4569         uint32_t dir_entries;
4570         uint32_t entry_length;
4571         uint8_t *buf;
4572         size_t buflen;
4573         rte_iova_t dma_handle;
4574         struct hwrm_nvm_get_dir_entries_input req = {0};
4575         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4576
4577         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4578         if (rc != 0)
4579                 return rc;
4580
4581         *data++ = dir_entries;
4582         *data++ = entry_length;
4583         len -= 2;
4584         memset(data, 0xff, len);
4585
4586         buflen = dir_entries * entry_length;
4587         buf = rte_malloc("nvm_dir", buflen, 0);
4588         if (buf == NULL)
4589                 return -ENOMEM;
4590         dma_handle = rte_malloc_virt2iova(buf);
4591         if (dma_handle == RTE_BAD_IOVA) {
4592                 rte_free(buf);
4593                 PMD_DRV_LOG(ERR,
4594                         "unable to map response address to physical memory\n");
4595                 return -ENOMEM;
4596         }
4597         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4598         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4600
4601         if (rc == 0)
4602                 memcpy(data, buf, len > buflen ? buflen : len);
4603
4604         rte_free(buf);
4605         HWRM_CHECK_RESULT();
4606         HWRM_UNLOCK();
4607
4608         return rc;
4609 }
4610
4611 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4612                              uint32_t offset, uint32_t length,
4613                              uint8_t *data)
4614 {
4615         int rc;
4616         uint8_t *buf;
4617         rte_iova_t dma_handle;
4618         struct hwrm_nvm_read_input req = {0};
4619         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4620
4621         buf = rte_malloc("nvm_item", length, 0);
4622         if (!buf)
4623                 return -ENOMEM;
4624
4625         dma_handle = rte_malloc_virt2iova(buf);
4626         if (dma_handle == RTE_BAD_IOVA) {
4627                 rte_free(buf);
4628                 PMD_DRV_LOG(ERR,
4629                         "unable to map response address to physical memory\n");
4630                 return -ENOMEM;
4631         }
4632         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4633         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4634         req.dir_idx = rte_cpu_to_le_16(index);
4635         req.offset = rte_cpu_to_le_32(offset);
4636         req.len = rte_cpu_to_le_32(length);
4637         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4638         if (rc == 0)
4639                 memcpy(data, buf, length);
4640
4641         rte_free(buf);
4642         HWRM_CHECK_RESULT();
4643         HWRM_UNLOCK();
4644
4645         return rc;
4646 }
4647
4648 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4649 {
4650         int rc;
4651         struct hwrm_nvm_erase_dir_entry_input req = {0};
4652         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4653
4654         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4655         req.dir_idx = rte_cpu_to_le_16(index);
4656         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4657         HWRM_CHECK_RESULT();
4658         HWRM_UNLOCK();
4659
4660         return rc;
4661 }
4662
4663 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4664                           uint16_t dir_ordinal, uint16_t dir_ext,
4665                           uint16_t dir_attr, const uint8_t *data,
4666                           size_t data_len)
4667 {
4668         int rc;
4669         struct hwrm_nvm_write_input req = {0};
4670         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4671         rte_iova_t dma_handle;
4672         uint8_t *buf;
4673
4674         buf = rte_malloc("nvm_write", data_len, 0);
4675         if (!buf)
4676                 return -ENOMEM;
4677
4678         dma_handle = rte_malloc_virt2iova(buf);
4679         if (dma_handle == RTE_BAD_IOVA) {
4680                 rte_free(buf);
4681                 PMD_DRV_LOG(ERR,
4682                         "unable to map response address to physical memory\n");
4683                 return -ENOMEM;
4684         }
4685         memcpy(buf, data, data_len);
4686
4687         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4688
4689         req.dir_type = rte_cpu_to_le_16(dir_type);
4690         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4691         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4692         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4693         req.dir_data_length = rte_cpu_to_le_32(data_len);
4694         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4695
4696         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4697
4698         rte_free(buf);
4699         HWRM_CHECK_RESULT();
4700         HWRM_UNLOCK();
4701
4702         return rc;
4703 }
4704
4705 static void
4706 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4707 {
4708         uint32_t *count = cbdata;
4709
4710         *count = *count + 1;
4711 }
4712
4713 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4714                                      struct bnxt_vnic_info *vnic __rte_unused)
4715 {
4716         return 0;
4717 }
4718
4719 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4720 {
4721         uint32_t count = 0;
4722
4723         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4724             &count, bnxt_vnic_count_hwrm_stub);
4725
4726         return count;
4727 }
4728
4729 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4730                                         uint16_t *vnic_ids)
4731 {
4732         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4733         struct hwrm_func_vf_vnic_ids_query_output *resp =
4734                                                 bp->hwrm_cmd_resp_addr;
4735         int rc;
4736
4737         /* First query all VNIC ids */
4738         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4739
4740         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4741         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4742         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4743
4744         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4745                 HWRM_UNLOCK();
4746                 PMD_DRV_LOG(ERR,
4747                 "unable to map VNIC ID table address to physical memory\n");
4748                 return -ENOMEM;
4749         }
4750         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4751         HWRM_CHECK_RESULT();
4752         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4753
4754         HWRM_UNLOCK();
4755
4756         return rc;
4757 }
4758
4759 /*
4760  * This function queries the VNIC IDs  for a specified VF. It then calls
4761  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4762  * Then it calls the hwrm_cb function to program this new vnic configuration.
4763  */
4764 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4765         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4766         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4767 {
4768         struct bnxt_vnic_info vnic;
4769         int rc = 0;
4770         int i, num_vnic_ids;
4771         uint16_t *vnic_ids;
4772         size_t vnic_id_sz;
4773         size_t sz;
4774
4775         /* First query all VNIC ids */
4776         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4777         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4778                         RTE_CACHE_LINE_SIZE);
4779         if (vnic_ids == NULL)
4780                 return -ENOMEM;
4781
4782         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4783                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4784
4785         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4786
4787         if (num_vnic_ids < 0)
4788                 return num_vnic_ids;
4789
4790         /* Retrieve VNIC, update bd_stall then update */
4791
4792         for (i = 0; i < num_vnic_ids; i++) {
4793                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4794                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4795                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4796                 if (rc)
4797                         break;
4798                 if (vnic.mru <= 4)      /* Indicates unallocated */
4799                         continue;
4800
4801                 vnic_cb(&vnic, cbdata);
4802
4803                 rc = hwrm_cb(bp, &vnic);
4804                 if (rc)
4805                         break;
4806         }
4807
4808         rte_free(vnic_ids);
4809
4810         return rc;
4811 }
4812
4813 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4814                                               bool on)
4815 {
4816         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4817         struct hwrm_func_cfg_input req = {0};
4818         int rc;
4819
4820         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4821
4822         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4823         req.enables |= rte_cpu_to_le_32(
4824                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4825         req.vlan_antispoof_mode = on ?
4826                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4827                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4828         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4829
4830         HWRM_CHECK_RESULT();
4831         HWRM_UNLOCK();
4832
4833         return rc;
4834 }
4835
4836 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4837 {
4838         struct bnxt_vnic_info vnic;
4839         uint16_t *vnic_ids;
4840         size_t vnic_id_sz;
4841         int num_vnic_ids, i;
4842         size_t sz;
4843         int rc;
4844
4845         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4846         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4847                         RTE_CACHE_LINE_SIZE);
4848         if (vnic_ids == NULL)
4849                 return -ENOMEM;
4850
4851         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4852                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4853
4854         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4855         if (rc <= 0)
4856                 goto exit;
4857         num_vnic_ids = rc;
4858
4859         /*
4860          * Loop through to find the default VNIC ID.
4861          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4862          * by sending the hwrm_func_qcfg command to the firmware.
4863          */
4864         for (i = 0; i < num_vnic_ids; i++) {
4865                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4866                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4867                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4868                                         bp->pf->first_vf_id + vf);
4869                 if (rc)
4870                         goto exit;
4871                 if (vnic.func_default) {
4872                         rte_free(vnic_ids);
4873                         return vnic.fw_vnic_id;
4874                 }
4875         }
4876         /* Could not find a default VNIC. */
4877         PMD_DRV_LOG(ERR, "No default VNIC\n");
4878 exit:
4879         rte_free(vnic_ids);
4880         return rc;
4881 }
4882
4883 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4884                          uint16_t dst_id,
4885                          struct bnxt_filter_info *filter)
4886 {
4887         int rc = 0;
4888         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4889         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4890         uint32_t enables = 0;
4891
4892         if (filter->fw_em_filter_id != UINT64_MAX)
4893                 bnxt_hwrm_clear_em_filter(bp, filter);
4894
4895         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4896
4897         req.flags = rte_cpu_to_le_32(filter->flags);
4898
4899         enables = filter->enables |
4900               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4901         req.dst_id = rte_cpu_to_le_16(dst_id);
4902
4903         if (filter->ip_addr_type) {
4904                 req.ip_addr_type = filter->ip_addr_type;
4905                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4906         }
4907         if (enables &
4908             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4909                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4910         if (enables &
4911             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4912                 memcpy(req.src_macaddr, filter->src_macaddr,
4913                        RTE_ETHER_ADDR_LEN);
4914         if (enables &
4915             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4916                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4917                        RTE_ETHER_ADDR_LEN);
4918         if (enables &
4919             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4920                 req.ovlan_vid = filter->l2_ovlan;
4921         if (enables &
4922             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4923                 req.ivlan_vid = filter->l2_ivlan;
4924         if (enables &
4925             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4926                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4927         if (enables &
4928             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4929                 req.ip_protocol = filter->ip_protocol;
4930         if (enables &
4931             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4932                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4933         if (enables &
4934             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4935                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4936         if (enables &
4937             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4938                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4939         if (enables &
4940             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4941                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4942         if (enables &
4943             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4944                 req.mirror_vnic_id = filter->mirror_vnic_id;
4945
4946         req.enables = rte_cpu_to_le_32(enables);
4947
4948         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4949
4950         HWRM_CHECK_RESULT();
4951
4952         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4953         HWRM_UNLOCK();
4954
4955         return rc;
4956 }
4957
4958 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4959 {
4960         int rc = 0;
4961         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4962         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4963
4964         if (filter->fw_em_filter_id == UINT64_MAX)
4965                 return 0;
4966
4967         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4968
4969         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4970
4971         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4972
4973         HWRM_CHECK_RESULT();
4974         HWRM_UNLOCK();
4975
4976         filter->fw_em_filter_id = UINT64_MAX;
4977         filter->fw_l2_filter_id = UINT64_MAX;
4978
4979         return 0;
4980 }
4981
4982 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4983                          uint16_t dst_id,
4984                          struct bnxt_filter_info *filter)
4985 {
4986         int rc = 0;
4987         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4988         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4989                                                 bp->hwrm_cmd_resp_addr;
4990         uint32_t enables = 0;
4991
4992         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4993                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4994
4995         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4996
4997         req.flags = rte_cpu_to_le_32(filter->flags);
4998
4999         enables = filter->enables |
5000               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
5001         req.dst_id = rte_cpu_to_le_16(dst_id);
5002
5003         if (filter->ip_addr_type) {
5004                 req.ip_addr_type = filter->ip_addr_type;
5005                 enables |=
5006                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
5007         }
5008         if (enables &
5009             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
5010                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
5011         if (enables &
5012             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
5013                 memcpy(req.src_macaddr, filter->src_macaddr,
5014                        RTE_ETHER_ADDR_LEN);
5015         if (enables &
5016             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
5017                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
5018         if (enables &
5019             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
5020                 req.ip_protocol = filter->ip_protocol;
5021         if (enables &
5022             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
5023                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
5024         if (enables &
5025             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
5026                 req.src_ipaddr_mask[0] =
5027                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
5028         if (enables &
5029             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
5030                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
5031         if (enables &
5032             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
5033                 req.dst_ipaddr_mask[0] =
5034                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
5035         if (enables &
5036             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
5037                 req.src_port = rte_cpu_to_le_16(filter->src_port);
5038         if (enables &
5039             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
5040                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
5041         if (enables &
5042             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
5043                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
5044         if (enables &
5045             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
5046                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
5047         if (enables &
5048             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
5049                 req.mirror_vnic_id = filter->mirror_vnic_id;
5050
5051         req.enables = rte_cpu_to_le_32(enables);
5052
5053         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5054
5055         HWRM_CHECK_RESULT();
5056
5057         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
5058         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
5059         HWRM_UNLOCK();
5060
5061         return rc;
5062 }
5063
5064 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
5065                                 struct bnxt_filter_info *filter)
5066 {
5067         int rc = 0;
5068         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
5069         struct hwrm_cfa_ntuple_filter_free_output *resp =
5070                                                 bp->hwrm_cmd_resp_addr;
5071
5072         if (filter->fw_ntuple_filter_id == UINT64_MAX)
5073                 return 0;
5074
5075         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
5076
5077         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
5078
5079         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5080
5081         HWRM_CHECK_RESULT();
5082         HWRM_UNLOCK();
5083
5084         filter->fw_ntuple_filter_id = UINT64_MAX;
5085
5086         return 0;
5087 }
5088
5089 static int
5090 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5091 {
5092         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5093         uint8_t *rxq_state = bp->eth_dev->data->rx_queue_state;
5094         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
5095         struct bnxt_rx_queue **rxqs = bp->rx_queues;
5096         uint16_t *ring_tbl = vnic->rss_table;
5097         int nr_ctxs = vnic->num_lb_ctxts;
5098         int max_rings = bp->rx_nr_rings;
5099         int i, j, k, cnt;
5100         int rc = 0;
5101
5102         for (i = 0, k = 0; i < nr_ctxs; i++) {
5103                 struct bnxt_rx_ring_info *rxr;
5104                 struct bnxt_cp_ring_info *cpr;
5105
5106                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5107
5108                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5109                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5110                 req.hash_mode_flags = vnic->hash_mode;
5111
5112                 req.ring_grp_tbl_addr =
5113                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5114                                      i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5115                                      2 * sizeof(*ring_tbl));
5116                 req.hash_key_tbl_addr =
5117                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5118
5119                 req.ring_table_pair_index = i;
5120                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5121
5122                 for (j = 0; j < 64; j++) {
5123                         uint16_t ring_id;
5124
5125                         /* Find next active ring. */
5126                         for (cnt = 0; cnt < max_rings; cnt++) {
5127                                 if (rxq_state[k] != RTE_ETH_QUEUE_STATE_STOPPED)
5128                                         break;
5129                                 if (++k == max_rings)
5130                                         k = 0;
5131                         }
5132
5133                         /* Return if no rings are active. */
5134                         if (cnt == max_rings) {
5135                                 HWRM_UNLOCK();
5136                                 return 0;
5137                         }
5138
5139                         /* Add rx/cp ring pair to RSS table. */
5140                         rxr = rxqs[k]->rx_ring;
5141                         cpr = rxqs[k]->cp_ring;
5142
5143                         ring_id = rxr->rx_ring_struct->fw_ring_id;
5144                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5145                         ring_id = cpr->cp_ring_struct->fw_ring_id;
5146                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5147
5148                         if (++k == max_rings)
5149                                 k = 0;
5150                 }
5151                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5152                                             BNXT_USE_CHIMP_MB);
5153
5154                 HWRM_CHECK_RESULT();
5155                 HWRM_UNLOCK();
5156         }
5157
5158         return rc;
5159 }
5160
5161 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5162 {
5163         unsigned int rss_idx, fw_idx, i;
5164
5165         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5166                 return 0;
5167
5168         if (!(vnic->rss_table && vnic->hash_type))
5169                 return 0;
5170
5171         if (BNXT_CHIP_P5(bp))
5172                 return bnxt_vnic_rss_configure_p5(bp, vnic);
5173
5174         /*
5175          * Fill the RSS hash & redirection table with
5176          * ring group ids for all VNICs
5177          */
5178         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5179              rss_idx++, fw_idx++) {
5180                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5181                         fw_idx %= bp->rx_cp_nr_rings;
5182                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5183                                 break;
5184                         fw_idx++;
5185                 }
5186
5187                 if (i == bp->rx_cp_nr_rings)
5188                         return 0;
5189
5190                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5191         }
5192
5193         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5194 }
5195
5196 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5197         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5198 {
5199         uint16_t flags;
5200
5201         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5202
5203         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5204         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5205
5206         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5207         req->num_cmpl_dma_aggr_during_int =
5208                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5209
5210         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5211
5212         /* min timer set to 1/2 of interrupt timer */
5213         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5214
5215         /* buf timer set to 1/4 of interrupt timer */
5216         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5217
5218         req->cmpl_aggr_dma_tmr_during_int =
5219                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5220
5221         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5222                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5223         req->flags = rte_cpu_to_le_16(flags);
5224 }
5225
5226 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5227                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5228 {
5229         struct hwrm_ring_aggint_qcaps_input req = {0};
5230         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5231         uint32_t enables;
5232         uint16_t flags;
5233         int rc;
5234
5235         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5236         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5237         HWRM_CHECK_RESULT();
5238
5239         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5240         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5241
5242         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5243                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5244         agg_req->flags = rte_cpu_to_le_16(flags);
5245         enables =
5246          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5247          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5248         agg_req->enables = rte_cpu_to_le_32(enables);
5249
5250         HWRM_UNLOCK();
5251         return rc;
5252 }
5253
5254 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5255                         struct bnxt_coal *coal, uint16_t ring_id)
5256 {
5257         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5258         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5259                                                 bp->hwrm_cmd_resp_addr;
5260         int rc;
5261
5262         /* Set ring coalesce parameters only for 100G NICs */
5263         if (BNXT_CHIP_P5(bp)) {
5264                 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5265                         return -1;
5266         } else if (bnxt_stratus_device(bp)) {
5267                 bnxt_hwrm_set_coal_params(coal, &req);
5268         } else {
5269                 return 0;
5270         }
5271
5272         HWRM_PREP(&req,
5273                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5274                   BNXT_USE_CHIMP_MB);
5275         req.ring_id = rte_cpu_to_le_16(ring_id);
5276         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5277         HWRM_CHECK_RESULT();
5278         HWRM_UNLOCK();
5279         return 0;
5280 }
5281
5282 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5283 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5284 {
5285         struct hwrm_func_backing_store_qcaps_input req = {0};
5286         struct hwrm_func_backing_store_qcaps_output *resp =
5287                 bp->hwrm_cmd_resp_addr;
5288         struct bnxt_ctx_pg_info *ctx_pg;
5289         struct bnxt_ctx_mem_info *ctx;
5290         int total_alloc_len;
5291         int rc, i, tqm_rings;
5292
5293         if (!BNXT_CHIP_P5(bp) ||
5294             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5295             BNXT_VF(bp) ||
5296             bp->ctx)
5297                 return 0;
5298
5299         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5300         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5301         HWRM_CHECK_RESULT_SILENT();
5302
5303         total_alloc_len = sizeof(*ctx);
5304         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5305                           RTE_CACHE_LINE_SIZE);
5306         if (!ctx) {
5307                 rc = -ENOMEM;
5308                 goto ctx_err;
5309         }
5310
5311         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5312         ctx->qp_min_qp1_entries =
5313                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5314         ctx->qp_max_l2_entries =
5315                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5316         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5317         ctx->srq_max_l2_entries =
5318                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5319         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5320         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5321         ctx->cq_max_l2_entries =
5322                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5323         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5324         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5325         ctx->vnic_max_vnic_entries =
5326                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5327         ctx->vnic_max_ring_table_entries =
5328                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5329         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5330         ctx->stat_max_entries =
5331                 rte_le_to_cpu_32(resp->stat_max_entries);
5332         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5333         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5334         ctx->tqm_min_entries_per_ring =
5335                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5336         ctx->tqm_max_entries_per_ring =
5337                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5338         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5339         if (!ctx->tqm_entries_multiple)
5340                 ctx->tqm_entries_multiple = 1;
5341         ctx->mrav_max_entries =
5342                 rte_le_to_cpu_32(resp->mrav_max_entries);
5343         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5344         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5345         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5346         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5347
5348         ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5349                                   RTE_MIN(ctx->tqm_fp_rings_count,
5350                                           BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5351                                   bp->max_q;
5352
5353         /* Check if the ext ring count needs to be counted.
5354          * Ext ring count is available only with new FW so we should not
5355          * look at the field on older FW.
5356          */
5357         if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5358             bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5359                 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5360                 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5361                                                   ctx->tqm_fp_rings_count);
5362         }
5363
5364         tqm_rings = ctx->tqm_fp_rings_count + 1;
5365
5366         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5367                             sizeof(*ctx_pg) * tqm_rings,
5368                             RTE_CACHE_LINE_SIZE);
5369         if (!ctx_pg) {
5370                 rc = -ENOMEM;
5371                 goto ctx_err;
5372         }
5373         for (i = 0; i < tqm_rings; i++, ctx_pg++)
5374                 ctx->tqm_mem[i] = ctx_pg;
5375
5376         bp->ctx = ctx;
5377 ctx_err:
5378         HWRM_UNLOCK();
5379         return rc;
5380 }
5381
5382 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5383 {
5384         struct hwrm_func_backing_store_cfg_input req = {0};
5385         struct hwrm_func_backing_store_cfg_output *resp =
5386                 bp->hwrm_cmd_resp_addr;
5387         struct bnxt_ctx_mem_info *ctx = bp->ctx;
5388         struct bnxt_ctx_pg_info *ctx_pg;
5389         uint32_t *num_entries;
5390         uint64_t *pg_dir;
5391         uint8_t *pg_attr;
5392         uint32_t ena;
5393         int i, rc;
5394
5395         if (!ctx)
5396                 return 0;
5397
5398         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5399         req.enables = rte_cpu_to_le_32(enables);
5400
5401         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5402                 ctx_pg = &ctx->qp_mem;
5403                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5404                 req.qp_num_qp1_entries =
5405                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5406                 req.qp_num_l2_entries =
5407                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5408                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5409                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5410                                       &req.qpc_pg_size_qpc_lvl,
5411                                       &req.qpc_page_dir);
5412         }
5413
5414         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5415                 ctx_pg = &ctx->srq_mem;
5416                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5417                 req.srq_num_l2_entries =
5418                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5419                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5420                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5421                                       &req.srq_pg_size_srq_lvl,
5422                                       &req.srq_page_dir);
5423         }
5424
5425         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5426                 ctx_pg = &ctx->cq_mem;
5427                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5428                 req.cq_num_l2_entries =
5429                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5430                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5431                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5432                                       &req.cq_pg_size_cq_lvl,
5433                                       &req.cq_page_dir);
5434         }
5435
5436         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5437                 ctx_pg = &ctx->vnic_mem;
5438                 req.vnic_num_vnic_entries =
5439                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5440                 req.vnic_num_ring_table_entries =
5441                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5442                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5443                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5444                                       &req.vnic_pg_size_vnic_lvl,
5445                                       &req.vnic_page_dir);
5446         }
5447
5448         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5449                 ctx_pg = &ctx->stat_mem;
5450                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5451                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5452                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5453                                       &req.stat_pg_size_stat_lvl,
5454                                       &req.stat_page_dir);
5455         }
5456
5457         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5458         num_entries = &req.tqm_sp_num_entries;
5459         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5460         pg_dir = &req.tqm_sp_page_dir;
5461         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5462         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5463                 if (!(enables & ena))
5464                         continue;
5465
5466                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5467
5468                 ctx_pg = ctx->tqm_mem[i];
5469                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5470                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5471         }
5472
5473         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5474                 /* DPDK does not need to configure MRAV and TIM type.
5475                  * So we are skipping over MRAV and TIM. Skip to configure
5476                  * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5477                  */
5478                 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5479                 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5480                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5481                                       &req.tqm_ring8_pg_size_tqm_ring_lvl,
5482                                       &req.tqm_ring8_page_dir);
5483         }
5484
5485         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5486         HWRM_CHECK_RESULT();
5487         HWRM_UNLOCK();
5488
5489         return rc;
5490 }
5491
5492 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5493 {
5494         struct hwrm_port_qstats_ext_input req = {0};
5495         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5496         struct bnxt_pf_info *pf = bp->pf;
5497         int rc;
5498
5499         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5500               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5501                 return 0;
5502
5503         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5504
5505         req.port_id = rte_cpu_to_le_16(pf->port_id);
5506         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5507                 req.tx_stat_host_addr =
5508                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5509                 req.tx_stat_size =
5510                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5511         }
5512         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5513                 req.rx_stat_host_addr =
5514                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5515                 req.rx_stat_size =
5516                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5517         }
5518         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5519
5520         if (rc) {
5521                 bp->fw_rx_port_stats_ext_size = 0;
5522                 bp->fw_tx_port_stats_ext_size = 0;
5523         } else {
5524                 bp->fw_rx_port_stats_ext_size =
5525                         rte_le_to_cpu_16(resp->rx_stat_size);
5526                 bp->fw_tx_port_stats_ext_size =
5527                         rte_le_to_cpu_16(resp->tx_stat_size);
5528         }
5529
5530         HWRM_CHECK_RESULT();
5531         HWRM_UNLOCK();
5532
5533         return rc;
5534 }
5535
5536 int
5537 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5538 {
5539         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5540         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5541                 bp->hwrm_cmd_resp_addr;
5542         int rc = 0;
5543
5544         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5545         req.tunnel_type = type;
5546         req.dest_fid = bp->fw_fid;
5547         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5548         HWRM_CHECK_RESULT();
5549
5550         HWRM_UNLOCK();
5551
5552         return rc;
5553 }
5554
5555 int
5556 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5557 {
5558         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5559         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5560                 bp->hwrm_cmd_resp_addr;
5561         int rc = 0;
5562
5563         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5564         req.tunnel_type = type;
5565         req.dest_fid = bp->fw_fid;
5566         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5567         HWRM_CHECK_RESULT();
5568
5569         HWRM_UNLOCK();
5570
5571         return rc;
5572 }
5573
5574 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5575 {
5576         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5577         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5578                 bp->hwrm_cmd_resp_addr;
5579         int rc = 0;
5580
5581         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5582         req.src_fid = bp->fw_fid;
5583         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5584         HWRM_CHECK_RESULT();
5585
5586         if (type)
5587                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5588
5589         HWRM_UNLOCK();
5590
5591         return rc;
5592 }
5593
5594 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5595                                    uint16_t *dst_fid)
5596 {
5597         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5598         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5599                 bp->hwrm_cmd_resp_addr;
5600         int rc = 0;
5601
5602         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5603         req.src_fid = bp->fw_fid;
5604         req.tunnel_type = tun_type;
5605         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5606         HWRM_CHECK_RESULT();
5607
5608         if (dst_fid)
5609                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5610
5611         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5612
5613         HWRM_UNLOCK();
5614
5615         return rc;
5616 }
5617
5618 int bnxt_hwrm_set_mac(struct bnxt *bp)
5619 {
5620         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5621         struct hwrm_func_vf_cfg_input req = {0};
5622         int rc = 0;
5623
5624         if (!BNXT_VF(bp))
5625                 return 0;
5626
5627         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5628
5629         req.enables =
5630                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5631         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5632
5633         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5634
5635         HWRM_CHECK_RESULT();
5636
5637         HWRM_UNLOCK();
5638
5639         return rc;
5640 }
5641
5642 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5643 {
5644         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5645         struct hwrm_func_drv_if_change_input req = {0};
5646         uint32_t flags;
5647         int rc;
5648
5649         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5650                 return 0;
5651
5652         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5653          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5654          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5655          */
5656         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5657                 return 0;
5658
5659         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5660
5661         if (up)
5662                 req.flags =
5663                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5664
5665         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5666
5667         HWRM_CHECK_RESULT();
5668         flags = rte_le_to_cpu_32(resp->flags);
5669         HWRM_UNLOCK();
5670
5671         if (!up)
5672                 return 0;
5673
5674         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5675                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5676                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5677         }
5678
5679         return 0;
5680 }
5681
5682 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5683 {
5684         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5685         struct bnxt_error_recovery_info *info = bp->recovery_info;
5686         struct hwrm_error_recovery_qcfg_input req = {0};
5687         uint32_t flags = 0;
5688         unsigned int i;
5689         int rc;
5690
5691         /* Older FW does not have error recovery support */
5692         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5693                 return 0;
5694
5695         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5696
5697         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5698
5699         HWRM_CHECK_RESULT();
5700
5701         flags = rte_le_to_cpu_32(resp->flags);
5702         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5703                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5704         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5705                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5706
5707         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5708             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5709                 rc = -EINVAL;
5710                 goto err;
5711         }
5712
5713         /* FW returned values are in units of 100msec */
5714         info->driver_polling_freq =
5715                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5716         info->primary_func_wait_period =
5717                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5718         info->normal_func_wait_period =
5719                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5720         info->primary_func_wait_period_after_reset =
5721                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5722         info->max_bailout_time_after_reset =
5723                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5724         info->status_regs[BNXT_FW_STATUS_REG] =
5725                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5726         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5727                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5728         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5729                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5730         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5731                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5732         info->reg_array_cnt =
5733                 rte_le_to_cpu_32(resp->reg_array_cnt);
5734
5735         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5736                 rc = -EINVAL;
5737                 goto err;
5738         }
5739
5740         for (i = 0; i < info->reg_array_cnt; i++) {
5741                 info->reset_reg[i] =
5742                         rte_le_to_cpu_32(resp->reset_reg[i]);
5743                 info->reset_reg_val[i] =
5744                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5745                 info->delay_after_reset[i] =
5746                         resp->delay_after_reset[i];
5747         }
5748 err:
5749         HWRM_UNLOCK();
5750
5751         /* Map the FW status registers */
5752         if (!rc)
5753                 rc = bnxt_map_fw_health_status_regs(bp);
5754
5755         if (rc) {
5756                 rte_free(bp->recovery_info);
5757                 bp->recovery_info = NULL;
5758         }
5759         return rc;
5760 }
5761
5762 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5763 {
5764         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5765         struct hwrm_fw_reset_input req = {0};
5766         int rc;
5767
5768         if (!BNXT_PF(bp))
5769                 return -EOPNOTSUPP;
5770
5771         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5772
5773         req.embedded_proc_type =
5774                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5775         req.selfrst_status =
5776                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5777         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5778
5779         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5780                                     BNXT_USE_KONG(bp));
5781
5782         HWRM_CHECK_RESULT();
5783         HWRM_UNLOCK();
5784
5785         return rc;
5786 }
5787
5788 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5789 {
5790         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5791         struct hwrm_port_ts_query_input req = {0};
5792         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5793         uint32_t flags = 0;
5794         int rc;
5795
5796         if (!ptp)
5797                 return 0;
5798
5799         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5800
5801         switch (path) {
5802         case BNXT_PTP_FLAGS_PATH_TX:
5803                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5804                 break;
5805         case BNXT_PTP_FLAGS_PATH_RX:
5806                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5807                 break;
5808         case BNXT_PTP_FLAGS_CURRENT_TIME:
5809                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5810                 break;
5811         }
5812
5813         req.flags = rte_cpu_to_le_32(flags);
5814         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5815
5816         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5817
5818         HWRM_CHECK_RESULT();
5819
5820         if (timestamp) {
5821                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5822                 *timestamp |=
5823                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5824         }
5825         HWRM_UNLOCK();
5826
5827         return rc;
5828 }
5829
5830 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5831 {
5832         int rc = 0;
5833
5834         struct hwrm_cfa_counter_qcaps_input req = {0};
5835         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5836
5837         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5838                 PMD_DRV_LOG(DEBUG,
5839                             "Not a PF or trusted VF. Command not supported\n");
5840                 return 0;
5841         }
5842
5843         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5844         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5845         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5846
5847         HWRM_CHECK_RESULT();
5848         if (max_fc)
5849                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5850         HWRM_UNLOCK();
5851
5852         return 0;
5853 }
5854
5855 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5856 {
5857         int rc = 0;
5858         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5859         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5860
5861         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5862                 PMD_DRV_LOG(DEBUG,
5863                             "Not a PF or trusted VF. Command not supported\n");
5864                 return 0;
5865         }
5866
5867         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5868
5869         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5870         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5871         req.page_dir = rte_cpu_to_le_64(dma_addr);
5872
5873         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5874
5875         HWRM_CHECK_RESULT();
5876         if (ctx_id) {
5877                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5878                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5879         }
5880         HWRM_UNLOCK();
5881
5882         return 0;
5883 }
5884
5885 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5886 {
5887         int rc = 0;
5888         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5889         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5890
5891         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5892                 PMD_DRV_LOG(DEBUG,
5893                             "Not a PF or trusted VF. Command not supported\n");
5894                 return 0;
5895         }
5896
5897         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5898
5899         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5900
5901         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5902
5903         HWRM_CHECK_RESULT();
5904         HWRM_UNLOCK();
5905
5906         return rc;
5907 }
5908
5909 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5910                               uint16_t cntr, uint16_t ctx_id,
5911                               uint32_t num_entries, bool enable)
5912 {
5913         struct hwrm_cfa_counter_cfg_input req = {0};
5914         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5915         uint16_t flags = 0;
5916         int rc;
5917
5918         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5919                 PMD_DRV_LOG(DEBUG,
5920                             "Not a PF or trusted VF. Command not supported\n");
5921                 return 0;
5922         }
5923
5924         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5925
5926         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5927         req.counter_type = rte_cpu_to_le_16(cntr);
5928         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5929                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5930         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5931         if (dir == BNXT_DIR_RX)
5932                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5933         else if (dir == BNXT_DIR_TX)
5934                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5935         req.flags = rte_cpu_to_le_16(flags);
5936         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5937         req.num_entries = rte_cpu_to_le_32(num_entries);
5938
5939         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5940         HWRM_CHECK_RESULT();
5941         HWRM_UNLOCK();
5942
5943         return 0;
5944 }
5945
5946 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5947                                  enum bnxt_flow_dir dir,
5948                                  uint16_t cntr,
5949                                  uint16_t num_entries)
5950 {
5951         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5952         struct hwrm_cfa_counter_qstats_input req = {0};
5953         uint16_t flow_ctx_id = 0;
5954         uint16_t flags = 0;
5955         int rc = 0;
5956
5957         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5958                 PMD_DRV_LOG(DEBUG,
5959                             "Not a PF or trusted VF. Command not supported\n");
5960                 return 0;
5961         }
5962
5963         if (dir == BNXT_DIR_RX) {
5964                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5965                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5966         } else if (dir == BNXT_DIR_TX) {
5967                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5968                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5969         }
5970
5971         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5972         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5973         req.counter_type = rte_cpu_to_le_16(cntr);
5974         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5975         req.num_entries = rte_cpu_to_le_16(num_entries);
5976         req.flags = rte_cpu_to_le_16(flags);
5977         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5978
5979         HWRM_CHECK_RESULT();
5980         HWRM_UNLOCK();
5981
5982         return 0;
5983 }
5984
5985 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5986                                 uint16_t *first_vf_id)
5987 {
5988         int rc = 0;
5989         struct hwrm_func_qcaps_input req = {.req_type = 0 };
5990         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5991
5992         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5993
5994         req.fid = rte_cpu_to_le_16(fid);
5995
5996         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5997
5998         HWRM_CHECK_RESULT();
5999
6000         if (first_vf_id)
6001                 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
6002
6003         HWRM_UNLOCK();
6004
6005         return rc;
6006 }
6007
6008 int bnxt_hwrm_cfa_pair_exists(struct bnxt *bp, struct bnxt_representor *rep_bp)
6009 {
6010         struct hwrm_cfa_pair_info_output *resp = bp->hwrm_cmd_resp_addr;
6011         struct hwrm_cfa_pair_info_input req = {0};
6012         int rc = 0;
6013
6014         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6015                 PMD_DRV_LOG(DEBUG,
6016                             "Not a PF or trusted VF. Command not supported\n");
6017                 return 0;
6018         }
6019
6020         HWRM_PREP(&req, HWRM_CFA_PAIR_INFO, BNXT_USE_CHIMP_MB);
6021         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6022                  bp->eth_dev->data->name, rep_bp->vf_id);
6023         req.flags =
6024                 rte_cpu_to_le_32(HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE);
6025
6026         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6027         HWRM_CHECK_RESULT();
6028         if (rc == HWRM_ERR_CODE_SUCCESS && strlen(resp->pair_name)) {
6029                 HWRM_UNLOCK();
6030                 return !rc;
6031         }
6032         HWRM_UNLOCK();
6033         return rc;
6034 }
6035
6036 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
6037 {
6038         struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6039         struct hwrm_cfa_pair_alloc_input req = {0};
6040         int rc;
6041
6042         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6043                 PMD_DRV_LOG(DEBUG,
6044                             "Not a PF or trusted VF. Command not supported\n");
6045                 return 0;
6046         }
6047
6048         HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
6049         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6050         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6051                  bp->eth_dev->data->name, rep_bp->vf_id);
6052
6053         req.pf_b_id = rep_bp->parent_pf_idx;
6054         req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6055                                                 rte_cpu_to_le_16(rep_bp->vf_id);
6056         req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
6057         req.host_b_id = 1; /* TBD - Confirm if this is OK */
6058
6059         req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
6060                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
6061         req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
6062                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
6063         req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
6064                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
6065         req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
6066                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
6067
6068         req.q_ab = rep_bp->rep_q_r2f;
6069         req.q_ba = rep_bp->rep_q_f2r;
6070         req.fc_ab = rep_bp->rep_fc_r2f;
6071         req.fc_ba = rep_bp->rep_fc_f2r;
6072
6073         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6074         HWRM_CHECK_RESULT();
6075
6076         HWRM_UNLOCK();
6077         PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
6078                     BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
6079         return rc;
6080 }
6081
6082 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
6083 {
6084         struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
6085         struct hwrm_cfa_pair_free_input req = {0};
6086         int rc;
6087
6088         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6089                 PMD_DRV_LOG(DEBUG,
6090                             "Not a PF or trusted VF. Command not supported\n");
6091                 return 0;
6092         }
6093
6094         HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
6095         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6096                  bp->eth_dev->data->name, rep_bp->vf_id);
6097         req.pf_b_id = rep_bp->parent_pf_idx;
6098         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6099         req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6100                                                 rte_cpu_to_le_16(rep_bp->vf_id);
6101         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6102         HWRM_CHECK_RESULT();
6103         HWRM_UNLOCK();
6104         PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
6105                     rep_bp->vf_id);
6106         return rc;
6107 }
6108
6109 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
6110 {
6111         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
6112                                         bp->hwrm_cmd_resp_addr;
6113         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
6114         uint32_t flags = 0;
6115         int rc = 0;
6116
6117         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
6118                 return 0;
6119
6120         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6121                 PMD_DRV_LOG(DEBUG,
6122                             "Not a PF or trusted VF. Command not supported\n");
6123                 return 0;
6124         }
6125
6126         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
6127         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6128
6129         HWRM_CHECK_RESULT();
6130         flags = rte_le_to_cpu_32(resp->flags);
6131         HWRM_UNLOCK();
6132
6133         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
6134                 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
6135         else
6136                 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
6137
6138         return rc;
6139 }
6140
6141 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6142                             uint32_t echo_req_data2)
6143 {
6144         struct hwrm_func_echo_response_input req = {0};
6145         struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6146         int rc;
6147
6148         HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6149         req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6150         req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6151
6152         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6153
6154         HWRM_CHECK_RESULT();
6155         HWRM_UNLOCK();
6156
6157         return rc;
6158 }
6159
6160 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6161 {
6162         struct hwrm_ver_get_input req = {.req_type = 0 };
6163         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6164         int rc = 0;
6165
6166         bp->max_req_len = HWRM_MAX_REQ_LEN;
6167         bp->max_resp_len = BNXT_PAGE_SIZE;
6168         bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6169
6170         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6171         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6172         req.hwrm_intf_min = HWRM_VERSION_MINOR;
6173         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6174
6175         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6176
6177         HWRM_CHECK_RESULT_SILENT();
6178
6179         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)
6180                 rc = -EAGAIN;
6181
6182         HWRM_UNLOCK();
6183
6184         return rc;
6185 }
6186
6187 int bnxt_hwrm_read_sfp_module_eeprom_info(struct bnxt *bp, uint16_t i2c_addr,
6188                                           uint16_t page_number, uint16_t start_addr,
6189                                           uint16_t data_length, uint8_t *buf)
6190 {
6191         struct hwrm_port_phy_i2c_read_output *resp = bp->hwrm_cmd_resp_addr;
6192         struct hwrm_port_phy_i2c_read_input req = {0};
6193         uint32_t enables = HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET;
6194         int rc, byte_offset = 0;
6195
6196         do {
6197                 uint16_t xfer_size;
6198
6199                 HWRM_PREP(&req, HWRM_PORT_PHY_I2C_READ, BNXT_USE_CHIMP_MB);
6200                 req.i2c_slave_addr = i2c_addr;
6201                 req.page_number = rte_cpu_to_le_16(page_number);
6202                 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
6203
6204                 xfer_size = RTE_MIN(data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
6205                 req.page_offset = rte_cpu_to_le_16(start_addr + byte_offset);
6206                 req.data_length = xfer_size;
6207                 req.enables = rte_cpu_to_le_32(start_addr + byte_offset ? enables : 0);
6208                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6209                 HWRM_CHECK_RESULT();
6210
6211                 memcpy(buf + byte_offset, resp->data, xfer_size);
6212
6213                 data_length -= xfer_size;
6214                 byte_offset += xfer_size;
6215
6216                 HWRM_UNLOCK();
6217         } while (data_length > 0);
6218
6219         return rc;
6220 }
6221
6222 void bnxt_free_hwrm_tx_ring(struct bnxt *bp, int queue_index)
6223 {
6224         struct bnxt_tx_queue *txq = bp->tx_queues[queue_index];
6225         struct bnxt_tx_ring_info *txr = txq->tx_ring;
6226         struct bnxt_ring *ring = txr->tx_ring_struct;
6227         struct bnxt_cp_ring_info *cpr = txq->cp_ring;
6228
6229         bnxt_hwrm_ring_free(bp, ring,
6230                             HWRM_RING_FREE_INPUT_RING_TYPE_TX,
6231                             cpr->cp_ring_struct->fw_ring_id);
6232         txr->tx_raw_prod = 0;
6233         txr->tx_raw_cons = 0;
6234         memset(txr->tx_desc_ring, 0,
6235                 txr->tx_ring_struct->ring_size * sizeof(*txr->tx_desc_ring));
6236         memset(txr->tx_buf_ring, 0,
6237                 txr->tx_ring_struct->ring_size * sizeof(*txr->tx_buf_ring));
6238
6239         bnxt_hwrm_stat_ctx_free(bp, cpr);
6240
6241         bnxt_free_cp_ring(bp, cpr);
6242 }
6243
6244 int bnxt_hwrm_config_host_mtu(struct bnxt *bp)
6245 {
6246         struct hwrm_func_cfg_input req = {0};
6247         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
6248         int rc;
6249
6250         if (!BNXT_PF(bp))
6251                 return 0;
6252
6253         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
6254
6255         req.fid = rte_cpu_to_le_16(0xffff);
6256         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU);
6257         req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
6258
6259         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6260         HWRM_CHECK_RESULT();
6261         HWRM_UNLOCK();
6262
6263         return rc;
6264 }