1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SPEC_CODE_1_8_3 0x10803
31 #define HWRM_VERSION_1_9_1 0x10901
32 #define HWRM_VERSION_1_9_2 0x10903
34 struct bnxt_plcmodes_cfg {
36 uint16_t jumbo_thresh;
38 uint16_t hds_threshold;
41 static int page_getenum(size_t size)
57 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
58 return sizeof(void *) * 8 - 1;
61 static int page_roundup(size_t size)
63 return 1 << page_getenum(size);
66 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
70 if (rmem->nr_pages > 1) {
72 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
74 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
79 * HWRM Functions (sent to HWRM)
80 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
81 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
82 * command was failed by the ChiMP.
85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
86 uint32_t msg_len, bool use_kong_mb)
89 struct input *req = msg;
90 struct output *resp = bp->hwrm_cmd_resp_addr;
94 uint16_t max_req_len = bp->max_req_len;
95 struct hwrm_short_input short_input = { 0 };
96 uint16_t bar_offset = use_kong_mb ?
97 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
98 uint16_t mb_trigger_offset = use_kong_mb ?
99 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
101 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
102 msg_len > bp->max_req_len) {
103 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
105 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
106 memcpy(short_cmd_req, req, msg_len);
108 short_input.req_type = rte_cpu_to_le_16(req->req_type);
109 short_input.signature = rte_cpu_to_le_16(
110 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
111 short_input.size = rte_cpu_to_le_16(msg_len);
112 short_input.req_addr =
113 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
115 data = (uint32_t *)&short_input;
116 msg_len = sizeof(short_input);
118 /* Sync memory write before updating doorbell */
121 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
124 /* Write request msg to hwrm channel */
125 for (i = 0; i < msg_len; i += 4) {
126 bar = (uint8_t *)bp->bar0 + bar_offset + i;
127 rte_write32(*data, bar);
131 /* Zero the rest of the request space */
132 for (; i < max_req_len; i += 4) {
133 bar = (uint8_t *)bp->bar0 + bar_offset + i;
137 /* Ring channel doorbell */
138 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
141 /* Poll for the valid bit */
142 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
143 /* Sanity check on the resp->resp_len */
145 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
146 /* Last byte of resp contains the valid key */
147 valid = (uint8_t *)resp + resp->resp_len - 1;
148 if (*valid == HWRM_RESP_VALID_KEY)
154 if (i >= HWRM_CMD_TIMEOUT) {
155 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
166 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
167 * spinlock, and does initial processing.
169 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
170 * releases the spinlock only if it returns. If the regular int return codes
171 * are not used by the function, HWRM_CHECK_RESULT() should not be used
172 * directly, rather it should be copied and modified to suit the function.
174 * HWRM_UNLOCK() must be called after all response processing is completed.
176 #define HWRM_PREP(req, type, kong) do { \
177 rte_spinlock_lock(&bp->hwrm_lock); \
178 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
179 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
180 req.cmpl_ring = rte_cpu_to_le_16(-1); \
181 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
182 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
183 req.target_id = rte_cpu_to_le_16(0xffff); \
184 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
187 #define HWRM_CHECK_RESULT_SILENT() do {\
189 rte_spinlock_unlock(&bp->hwrm_lock); \
192 if (resp->error_code) { \
193 rc = rte_le_to_cpu_16(resp->error_code); \
194 rte_spinlock_unlock(&bp->hwrm_lock); \
199 #define HWRM_CHECK_RESULT() do {\
201 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
202 rte_spinlock_unlock(&bp->hwrm_lock); \
203 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
209 if (resp->error_code) { \
210 rc = rte_le_to_cpu_16(resp->error_code); \
211 if (resp->resp_len >= 16) { \
212 struct hwrm_err_output *tmp_hwrm_err_op = \
215 "error %d:%d:%08x:%04x\n", \
216 rc, tmp_hwrm_err_op->cmd_err, \
218 tmp_hwrm_err_op->opaque_0), \
220 tmp_hwrm_err_op->opaque_1)); \
222 PMD_DRV_LOG(ERR, "error %d\n", rc); \
224 rte_spinlock_unlock(&bp->hwrm_lock); \
225 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
233 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
235 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
238 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
239 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
241 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
242 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
245 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
253 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
254 struct bnxt_vnic_info *vnic,
256 struct bnxt_vlan_table_entry *vlan_table)
259 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
260 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
263 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
266 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
267 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
269 /* FIXME add multicast flag, when multicast adding options is supported
272 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
273 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
274 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
275 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
276 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
277 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
278 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
279 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
280 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
281 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
282 if (vnic->mc_addr_cnt) {
283 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
284 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
285 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
288 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
289 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
290 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
291 rte_mem_virt2iova(vlan_table));
292 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
294 req.mask = rte_cpu_to_le_32(mask);
296 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
304 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
306 struct bnxt_vlan_antispoof_table_entry *vlan_table)
309 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
310 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
311 bp->hwrm_cmd_resp_addr;
314 * Older HWRM versions did not support this command, and the set_rx_mask
315 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
316 * removed from set_rx_mask call, and this command was added.
318 * This command is also present from 1.7.8.11 and higher,
321 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
322 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
323 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
328 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
329 req.fid = rte_cpu_to_le_16(fid);
331 req.vlan_tag_mask_tbl_addr =
332 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
333 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
335 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
343 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
344 struct bnxt_filter_info *filter)
347 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
348 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
350 if (filter->fw_l2_filter_id == UINT64_MAX)
353 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
355 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
362 filter->fw_l2_filter_id = UINT64_MAX;
367 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
369 struct bnxt_filter_info *filter)
372 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
373 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
374 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
375 const struct rte_eth_vmdq_rx_conf *conf =
376 &dev_conf->rx_adv_conf.vmdq_rx_conf;
377 uint32_t enables = 0;
378 uint16_t j = dst_id - 1;
380 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
381 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
382 conf->pool_map[j].pools & (1UL << j)) {
384 "Add vlan %u to vmdq pool %u\n",
385 conf->pool_map[j].vlan_id, j);
387 filter->l2_ivlan = conf->pool_map[j].vlan_id;
389 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
390 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
393 if (filter->fw_l2_filter_id != UINT64_MAX)
394 bnxt_hwrm_clear_l2_filter(bp, filter);
396 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
398 req.flags = rte_cpu_to_le_32(filter->flags);
400 rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
402 enables = filter->enables |
403 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
404 req.dst_id = rte_cpu_to_le_16(dst_id);
407 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
408 memcpy(req.l2_addr, filter->l2_addr,
411 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
412 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
415 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
416 req.l2_ovlan = filter->l2_ovlan;
418 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
419 req.l2_ivlan = filter->l2_ivlan;
421 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
422 req.l2_ovlan_mask = filter->l2_ovlan_mask;
424 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
425 req.l2_ivlan_mask = filter->l2_ivlan_mask;
426 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
427 req.src_id = rte_cpu_to_le_32(filter->src_id);
428 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
429 req.src_type = filter->src_type;
431 req.enables = rte_cpu_to_le_32(enables);
433 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
437 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
443 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
445 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
446 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
453 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
456 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
459 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
460 if (ptp->tx_tstamp_en)
461 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
464 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
465 req.flags = rte_cpu_to_le_32(flags);
466 req.enables = rte_cpu_to_le_32
467 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
468 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
470 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
476 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
479 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
480 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
481 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
483 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
487 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
489 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
491 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
495 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
498 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
502 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
503 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
504 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
505 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
506 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
507 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
508 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
509 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
510 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
511 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
512 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
513 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
514 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
515 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
516 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
517 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
518 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
519 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
527 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
530 struct hwrm_func_qcaps_input req = {.req_type = 0 };
531 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
532 uint16_t new_max_vfs;
536 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
538 req.fid = rte_cpu_to_le_16(0xffff);
540 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
544 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
545 flags = rte_le_to_cpu_32(resp->flags);
547 bp->pf.port_id = resp->port_id;
548 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
549 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
550 new_max_vfs = bp->pdev->max_vfs;
551 if (new_max_vfs != bp->pf.max_vfs) {
553 rte_free(bp->pf.vf_info);
554 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
555 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
556 bp->pf.max_vfs = new_max_vfs;
557 for (i = 0; i < new_max_vfs; i++) {
558 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
559 bp->pf.vf_info[i].vlan_table =
560 rte_zmalloc("VF VLAN table",
563 if (bp->pf.vf_info[i].vlan_table == NULL)
565 "Fail to alloc VLAN table for VF %d\n",
569 bp->pf.vf_info[i].vlan_table);
570 bp->pf.vf_info[i].vlan_as_table =
571 rte_zmalloc("VF VLAN AS table",
574 if (bp->pf.vf_info[i].vlan_as_table == NULL)
576 "Alloc VLAN AS table for VF %d fail\n",
580 bp->pf.vf_info[i].vlan_as_table);
581 STAILQ_INIT(&bp->pf.vf_info[i].filter);
586 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
587 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
588 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
589 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
590 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
591 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
592 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
593 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
594 /* TODO: For now, do not support VMDq/RFS on VFs. */
599 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
603 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
605 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
606 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
607 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
608 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
610 bnxt_hwrm_ptp_qcfg(bp);
614 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
615 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
622 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
626 rc = __bnxt_hwrm_func_qcaps(bp);
627 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
628 rc = bnxt_alloc_ctx_mem(bp);
632 rc = bnxt_hwrm_func_resc_qcaps(bp);
634 bp->flags |= BNXT_FLAG_NEW_RM;
640 int bnxt_hwrm_func_reset(struct bnxt *bp)
643 struct hwrm_func_reset_input req = {.req_type = 0 };
644 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
646 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
648 req.enables = rte_cpu_to_le_32(0);
650 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
658 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
661 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
662 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
664 if (bp->flags & BNXT_FLAG_REGISTERED)
667 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
668 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
669 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
670 req.ver_maj = RTE_VER_YEAR;
671 req.ver_min = RTE_VER_MONTH;
672 req.ver_upd = RTE_VER_MINOR;
675 req.enables |= rte_cpu_to_le_32(
676 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
677 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
678 RTE_MIN(sizeof(req.vf_req_fwd),
679 sizeof(bp->pf.vf_req_fwd)));
682 * PF can sniff HWRM API issued by VF. This can be set up by
683 * linux driver and inherited by the DPDK PF driver. Clear
684 * this HWRM sniffer list in FW because DPDK PF driver does
688 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
691 req.async_event_fwd[0] |=
692 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
693 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
694 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
695 req.async_event_fwd[1] |=
696 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
697 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
699 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
704 bp->flags |= BNXT_FLAG_REGISTERED;
709 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
711 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
714 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
717 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
722 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
723 struct hwrm_func_vf_cfg_input req = {0};
725 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
727 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
728 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
729 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
730 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
731 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
733 if (BNXT_HAS_RING_GRPS(bp)) {
734 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
735 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
738 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
739 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
740 AGG_RING_MULTIPLIER);
741 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
742 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
744 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
745 if (bp->vf_resv_strategy ==
746 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
747 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
748 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
749 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
750 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
751 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
752 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
756 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
757 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
758 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
759 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
760 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
761 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
763 if (test && BNXT_HAS_RING_GRPS(bp))
764 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
766 req.flags = rte_cpu_to_le_32(flags);
767 req.enables |= rte_cpu_to_le_32(enables);
769 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
772 HWRM_CHECK_RESULT_SILENT();
780 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
783 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
784 struct hwrm_func_resource_qcaps_input req = {0};
786 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
787 req.fid = rte_cpu_to_le_16(0xffff);
789 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
794 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
795 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
796 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
797 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
798 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
799 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
800 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
801 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
803 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
804 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
805 if (bp->vf_resv_strategy >
806 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
807 bp->vf_resv_strategy =
808 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
814 int bnxt_hwrm_ver_get(struct bnxt *bp)
817 struct hwrm_ver_get_input req = {.req_type = 0 };
818 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
820 uint16_t max_resp_len;
821 char type[RTE_MEMZONE_NAMESIZE];
822 uint32_t dev_caps_cfg;
824 bp->max_req_len = HWRM_MAX_REQ_LEN;
825 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
827 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
828 req.hwrm_intf_min = HWRM_VERSION_MINOR;
829 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
831 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
835 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
836 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
837 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
838 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
839 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
840 (resp->hwrm_fw_min_8b << 16) |
841 (resp->hwrm_fw_bld_8b << 8) |
842 resp->hwrm_fw_rsvd_8b;
843 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
844 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
846 fw_version = resp->hwrm_intf_maj_8b << 16;
847 fw_version |= resp->hwrm_intf_min_8b << 8;
848 fw_version |= resp->hwrm_intf_upd_8b;
849 bp->hwrm_spec_code = fw_version;
851 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
852 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
857 if (bp->max_req_len > resp->max_req_win_len) {
858 PMD_DRV_LOG(ERR, "Unsupported request length\n");
861 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
862 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
863 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
864 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
866 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
867 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
869 if (bp->max_resp_len != max_resp_len) {
870 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
871 bp->pdev->addr.domain, bp->pdev->addr.bus,
872 bp->pdev->addr.devid, bp->pdev->addr.function);
874 rte_free(bp->hwrm_cmd_resp_addr);
876 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
877 if (bp->hwrm_cmd_resp_addr == NULL) {
881 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
882 bp->hwrm_cmd_resp_dma_addr =
883 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
884 if (bp->hwrm_cmd_resp_dma_addr == 0) {
886 "Unable to map response buffer to physical memory.\n");
890 bp->max_resp_len = max_resp_len;
894 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
896 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
897 PMD_DRV_LOG(DEBUG, "Short command supported\n");
898 bp->flags |= BNXT_FLAG_SHORT_CMD;
902 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
904 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
905 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
906 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
907 bp->pdev->addr.domain, bp->pdev->addr.bus,
908 bp->pdev->addr.devid, bp->pdev->addr.function);
910 rte_free(bp->hwrm_short_cmd_req_addr);
912 bp->hwrm_short_cmd_req_addr =
913 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
914 if (bp->hwrm_short_cmd_req_addr == NULL) {
918 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
919 bp->hwrm_short_cmd_req_dma_addr =
920 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
921 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
922 rte_free(bp->hwrm_short_cmd_req_addr);
924 "Unable to map buffer to physical memory.\n");
930 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
931 bp->flags |= BNXT_FLAG_KONG_MB_EN;
932 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
935 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
936 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
943 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
946 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
947 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
949 if (!(bp->flags & BNXT_FLAG_REGISTERED))
952 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
955 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
960 bp->flags &= ~BNXT_FLAG_REGISTERED;
965 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
968 struct hwrm_port_phy_cfg_input req = {0};
969 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
970 uint32_t enables = 0;
972 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
975 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
976 if (bp->link_info.auto_mode && conf->link_speed) {
977 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
978 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
981 req.flags = rte_cpu_to_le_32(conf->phy_flags);
982 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
983 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
985 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
986 * any auto mode, even "none".
988 if (!conf->link_speed) {
989 /* No speeds specified. Enable AutoNeg - all speeds */
991 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
993 /* AutoNeg - Advertise speeds specified. */
994 if (conf->auto_link_speed_mask &&
995 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
997 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
998 req.auto_link_speed_mask =
999 conf->auto_link_speed_mask;
1001 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1004 req.auto_duplex = conf->duplex;
1005 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1006 req.auto_pause = conf->auto_pause;
1007 req.force_pause = conf->force_pause;
1008 /* Set force_pause if there is no auto or if there is a force */
1009 if (req.auto_pause && !req.force_pause)
1010 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1012 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1014 req.enables = rte_cpu_to_le_32(enables);
1017 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1018 PMD_DRV_LOG(INFO, "Force Link Down\n");
1021 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1023 HWRM_CHECK_RESULT();
1029 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1030 struct bnxt_link_info *link_info)
1033 struct hwrm_port_phy_qcfg_input req = {0};
1034 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1036 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1038 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1040 HWRM_CHECK_RESULT();
1042 link_info->phy_link_status = resp->link;
1043 link_info->link_up =
1044 (link_info->phy_link_status ==
1045 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1046 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1047 link_info->duplex = resp->duplex_cfg;
1048 link_info->pause = resp->pause;
1049 link_info->auto_pause = resp->auto_pause;
1050 link_info->force_pause = resp->force_pause;
1051 link_info->auto_mode = resp->auto_mode;
1052 link_info->phy_type = resp->phy_type;
1053 link_info->media_type = resp->media_type;
1055 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1056 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1057 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1058 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1059 link_info->phy_ver[0] = resp->phy_maj;
1060 link_info->phy_ver[1] = resp->phy_min;
1061 link_info->phy_ver[2] = resp->phy_bld;
1065 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1066 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1067 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1068 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1069 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1070 link_info->auto_link_speed_mask);
1071 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1072 link_info->force_link_speed);
1077 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1080 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1081 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1084 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1086 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1087 /* HWRM Version >= 1.9.1 */
1088 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1090 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1091 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1093 HWRM_CHECK_RESULT();
1095 #define GET_QUEUE_INFO(x) \
1096 bp->cos_queue[x].id = resp->queue_id##x; \
1097 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1110 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1111 bp->tx_cosq_id = bp->cos_queue[0].id;
1113 /* iterate and find the COSq profile to use for Tx */
1114 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1115 if (bp->cos_queue[i].profile ==
1116 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1117 bp->tx_cosq_id = bp->cos_queue[i].id;
1123 bp->max_tc = resp->max_configurable_queues;
1124 bp->max_lltc = resp->max_configurable_lossless_queues;
1125 if (bp->max_tc > BNXT_MAX_QUEUE)
1126 bp->max_tc = BNXT_MAX_QUEUE;
1127 bp->max_q = bp->max_tc;
1129 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1134 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1135 struct bnxt_ring *ring,
1136 uint32_t ring_type, uint32_t map_index,
1137 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1140 uint32_t enables = 0;
1141 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1142 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1143 struct rte_mempool *mb_pool;
1144 uint16_t rx_buf_size;
1146 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1148 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1149 req.fbo = rte_cpu_to_le_32(0);
1150 /* Association of ring index with doorbell index */
1151 req.logical_id = rte_cpu_to_le_16(map_index);
1152 req.length = rte_cpu_to_le_32(ring->ring_size);
1154 switch (ring_type) {
1155 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1156 req.ring_type = ring_type;
1157 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1158 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1159 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1160 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1162 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1164 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1165 req.ring_type = ring_type;
1166 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1167 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1168 if (BNXT_CHIP_THOR(bp)) {
1169 mb_pool = bp->rx_queues[0]->mb_pool;
1170 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1171 RTE_PKTMBUF_HEADROOM;
1172 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1174 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1176 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1178 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1180 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1181 req.ring_type = ring_type;
1182 if (BNXT_HAS_NQ(bp)) {
1183 /* Association of cp ring with nq */
1184 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1186 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1188 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1190 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1191 req.ring_type = ring_type;
1192 req.page_size = BNXT_PAGE_SHFT;
1193 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1195 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1196 req.ring_type = ring_type;
1197 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1199 mb_pool = bp->rx_queues[0]->mb_pool;
1200 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1201 RTE_PKTMBUF_HEADROOM;
1202 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1204 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1205 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1206 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1207 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1210 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1215 req.enables = rte_cpu_to_le_32(enables);
1217 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1219 if (rc || resp->error_code) {
1220 if (rc == 0 && resp->error_code)
1221 rc = rte_le_to_cpu_16(resp->error_code);
1222 switch (ring_type) {
1223 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1225 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1228 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1230 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1233 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1235 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1239 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1241 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1244 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1246 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1250 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1256 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1261 int bnxt_hwrm_ring_free(struct bnxt *bp,
1262 struct bnxt_ring *ring, uint32_t ring_type)
1265 struct hwrm_ring_free_input req = {.req_type = 0 };
1266 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1268 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1270 req.ring_type = ring_type;
1271 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1273 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1275 if (rc || resp->error_code) {
1276 if (rc == 0 && resp->error_code)
1277 rc = rte_le_to_cpu_16(resp->error_code);
1280 switch (ring_type) {
1281 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1282 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1285 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1286 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1289 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1290 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1293 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1295 "hwrm_ring_free nq failed. rc:%d\n", rc);
1297 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1299 "hwrm_ring_free agg failed. rc:%d\n", rc);
1302 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1310 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1313 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1314 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1316 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1318 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1319 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1320 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1321 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1323 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1325 HWRM_CHECK_RESULT();
1327 bp->grp_info[idx].fw_grp_id =
1328 rte_le_to_cpu_16(resp->ring_group_id);
1335 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1338 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1339 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1341 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1343 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1345 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1347 HWRM_CHECK_RESULT();
1350 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1354 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1357 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1358 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1360 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1363 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1365 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1367 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1369 HWRM_CHECK_RESULT();
1375 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1376 unsigned int idx __rte_unused)
1379 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1380 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1382 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1384 req.update_period_ms = rte_cpu_to_le_32(0);
1386 req.stats_dma_addr =
1387 rte_cpu_to_le_64(cpr->hw_stats_map);
1389 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1391 HWRM_CHECK_RESULT();
1393 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1400 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1401 unsigned int idx __rte_unused)
1404 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1405 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1407 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1409 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1411 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1413 HWRM_CHECK_RESULT();
1419 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1422 struct hwrm_vnic_alloc_input req = { 0 };
1423 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1425 if (!BNXT_HAS_RING_GRPS(bp))
1426 goto skip_ring_grps;
1428 /* map ring groups to this vnic */
1429 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1430 vnic->start_grp_id, vnic->end_grp_id);
1431 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1432 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1434 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1435 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1436 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1437 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1440 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1441 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1442 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1444 if (vnic->func_default)
1446 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1447 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1449 HWRM_CHECK_RESULT();
1451 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1453 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1457 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1458 struct bnxt_vnic_info *vnic,
1459 struct bnxt_plcmodes_cfg *pmode)
1462 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1463 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1465 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1467 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1469 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1471 HWRM_CHECK_RESULT();
1473 pmode->flags = rte_le_to_cpu_32(resp->flags);
1474 /* dflt_vnic bit doesn't exist in the _cfg command */
1475 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1476 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1477 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1478 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1485 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1486 struct bnxt_vnic_info *vnic,
1487 struct bnxt_plcmodes_cfg *pmode)
1490 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1491 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1493 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1495 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1496 req.flags = rte_cpu_to_le_32(pmode->flags);
1497 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1498 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1499 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1500 req.enables = rte_cpu_to_le_32(
1501 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1502 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1503 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1506 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1508 HWRM_CHECK_RESULT();
1514 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1517 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1518 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1519 uint32_t ctx_enable_flag = 0;
1520 struct bnxt_plcmodes_cfg pmodes;
1521 uint32_t enables = 0;
1523 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1524 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1528 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1532 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1534 if (BNXT_CHIP_THOR(bp)) {
1535 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1536 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1537 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1539 req.default_rx_ring_id =
1540 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1541 req.default_cmpl_ring_id =
1542 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1543 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1544 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1548 /* Only RSS support for now TBD: COS & LB */
1549 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1550 if (vnic->lb_rule != 0xffff)
1551 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1552 if (vnic->cos_rule != 0xffff)
1553 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1554 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1555 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1556 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1558 enables |= ctx_enable_flag;
1559 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1560 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1561 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1562 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1565 req.enables = rte_cpu_to_le_32(enables);
1566 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1567 req.mru = rte_cpu_to_le_16(vnic->mru);
1568 /* Configure default VNIC only once. */
1569 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1571 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1572 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1574 if (vnic->vlan_strip)
1576 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1579 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1580 if (vnic->roce_dual)
1581 req.flags |= rte_cpu_to_le_32(
1582 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1583 if (vnic->roce_only)
1584 req.flags |= rte_cpu_to_le_32(
1585 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1586 if (vnic->rss_dflt_cr)
1587 req.flags |= rte_cpu_to_le_32(
1588 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1590 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1592 HWRM_CHECK_RESULT();
1595 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1600 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1604 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1605 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1607 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1608 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1611 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1614 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1615 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1616 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1618 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1620 HWRM_CHECK_RESULT();
1622 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1623 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1624 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1625 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1626 vnic->mru = rte_le_to_cpu_16(resp->mru);
1627 vnic->func_default = rte_le_to_cpu_32(
1628 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1629 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1630 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1631 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1632 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1633 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1634 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1635 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1636 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1637 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1638 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1645 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1646 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1650 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1651 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1652 bp->hwrm_cmd_resp_addr;
1654 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1656 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1657 HWRM_CHECK_RESULT();
1659 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1660 if (!BNXT_HAS_RING_GRPS(bp))
1661 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1662 else if (ctx_idx == 0)
1663 vnic->rss_rule = ctx_id;
1670 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1671 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1674 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1675 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1676 bp->hwrm_cmd_resp_addr;
1678 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1679 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1682 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1684 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1686 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1688 HWRM_CHECK_RESULT();
1694 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1697 struct hwrm_vnic_free_input req = {.req_type = 0 };
1698 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1700 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1701 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1705 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1707 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1709 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1711 HWRM_CHECK_RESULT();
1714 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1715 /* Configure default VNIC again if necessary. */
1716 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1717 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1723 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1727 int nr_ctxs = bp->max_ring_grps;
1728 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1729 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1731 if (!(vnic->rss_table && vnic->hash_type))
1734 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1736 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1737 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1738 req.hash_mode_flags = vnic->hash_mode;
1740 req.hash_key_tbl_addr =
1741 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1743 for (i = 0; i < nr_ctxs; i++) {
1744 req.ring_grp_tbl_addr =
1745 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1746 i * HW_HASH_INDEX_SIZE);
1747 req.ring_table_pair_index = i;
1748 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1750 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1753 HWRM_CHECK_RESULT();
1763 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1764 struct bnxt_vnic_info *vnic)
1767 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1768 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1770 if (BNXT_CHIP_THOR(bp))
1771 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1773 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1775 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1776 req.hash_mode_flags = vnic->hash_mode;
1778 req.ring_grp_tbl_addr =
1779 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1780 req.hash_key_tbl_addr =
1781 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1782 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1783 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1785 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1787 HWRM_CHECK_RESULT();
1793 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1794 struct bnxt_vnic_info *vnic)
1797 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1798 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1801 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1802 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1806 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1808 req.flags = rte_cpu_to_le_32(
1809 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1811 req.enables = rte_cpu_to_le_32(
1812 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1814 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1815 size -= RTE_PKTMBUF_HEADROOM;
1817 req.jumbo_thresh = rte_cpu_to_le_16(size);
1818 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1820 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1822 HWRM_CHECK_RESULT();
1828 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1829 struct bnxt_vnic_info *vnic, bool enable)
1832 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1833 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1835 if (BNXT_CHIP_THOR(bp))
1838 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1841 req.enables = rte_cpu_to_le_32(
1842 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1843 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1844 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1845 req.flags = rte_cpu_to_le_32(
1846 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1847 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1848 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1849 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1850 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1851 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1852 req.max_agg_segs = rte_cpu_to_le_16(5);
1854 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1855 req.min_agg_len = rte_cpu_to_le_32(512);
1857 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1859 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1861 HWRM_CHECK_RESULT();
1867 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1869 struct hwrm_func_cfg_input req = {0};
1870 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1873 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1874 req.enables = rte_cpu_to_le_32(
1875 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1876 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1877 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1879 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1881 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1882 HWRM_CHECK_RESULT();
1885 bp->pf.vf_info[vf].random_mac = false;
1890 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1894 struct hwrm_func_qstats_input req = {.req_type = 0};
1895 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1897 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1899 req.fid = rte_cpu_to_le_16(fid);
1901 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1903 HWRM_CHECK_RESULT();
1906 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1913 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1914 struct rte_eth_stats *stats)
1917 struct hwrm_func_qstats_input req = {.req_type = 0};
1918 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1920 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1922 req.fid = rte_cpu_to_le_16(fid);
1924 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1926 HWRM_CHECK_RESULT();
1928 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1929 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1930 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1931 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1932 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1933 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1935 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1936 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1937 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1938 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1939 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1940 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1942 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1943 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1944 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1951 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1954 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1955 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1957 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1959 req.fid = rte_cpu_to_le_16(fid);
1961 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1963 HWRM_CHECK_RESULT();
1970 * HWRM utility functions
1973 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1978 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1979 struct bnxt_tx_queue *txq;
1980 struct bnxt_rx_queue *rxq;
1981 struct bnxt_cp_ring_info *cpr;
1983 if (i >= bp->rx_cp_nr_rings) {
1984 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1987 rxq = bp->rx_queues[i];
1991 rc = bnxt_hwrm_stat_clear(bp, cpr);
1998 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2002 struct bnxt_cp_ring_info *cpr;
2004 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2006 if (i >= bp->rx_cp_nr_rings) {
2007 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2009 cpr = bp->rx_queues[i]->cp_ring;
2010 if (BNXT_HAS_RING_GRPS(bp))
2011 bp->grp_info[i].fw_stats_ctx = -1;
2013 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2014 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2015 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2023 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2028 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2029 struct bnxt_tx_queue *txq;
2030 struct bnxt_rx_queue *rxq;
2031 struct bnxt_cp_ring_info *cpr;
2033 if (i >= bp->rx_cp_nr_rings) {
2034 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2037 rxq = bp->rx_queues[i];
2041 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2049 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2054 if (!BNXT_HAS_RING_GRPS(bp))
2057 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2059 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2062 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2070 static void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2072 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2074 bnxt_hwrm_ring_free(bp, cp_ring,
2075 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2076 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2077 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2078 sizeof(*cpr->cp_desc_ring));
2079 cpr->cp_raw_cons = 0;
2082 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2084 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2086 bnxt_hwrm_ring_free(bp, cp_ring,
2087 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2088 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2089 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2090 sizeof(*cpr->cp_desc_ring));
2091 cpr->cp_raw_cons = 0;
2094 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2096 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2097 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2098 struct bnxt_ring *ring = rxr->rx_ring_struct;
2099 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2101 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2102 bnxt_hwrm_ring_free(bp, ring,
2103 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2104 ring->fw_ring_id = INVALID_HW_RING_ID;
2105 if (BNXT_HAS_RING_GRPS(bp))
2106 bp->grp_info[queue_index].rx_fw_ring_id =
2108 memset(rxr->rx_desc_ring, 0,
2109 rxr->rx_ring_struct->ring_size *
2110 sizeof(*rxr->rx_desc_ring));
2111 memset(rxr->rx_buf_ring, 0,
2112 rxr->rx_ring_struct->ring_size *
2113 sizeof(*rxr->rx_buf_ring));
2116 ring = rxr->ag_ring_struct;
2117 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2118 bnxt_hwrm_ring_free(bp, ring,
2119 BNXT_CHIP_THOR(bp) ?
2120 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2121 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2122 ring->fw_ring_id = INVALID_HW_RING_ID;
2123 memset(rxr->ag_buf_ring, 0,
2124 rxr->ag_ring_struct->ring_size *
2125 sizeof(*rxr->ag_buf_ring));
2127 if (BNXT_HAS_RING_GRPS(bp))
2128 bp->grp_info[queue_index].ag_fw_ring_id =
2131 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2132 bnxt_free_cp_ring(bp, cpr);
2134 bnxt_free_nq_ring(bp, rxq->nq_ring);
2137 if (BNXT_HAS_RING_GRPS(bp))
2138 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2141 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2145 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2146 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2147 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2148 struct bnxt_ring *ring = txr->tx_ring_struct;
2149 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2151 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2152 bnxt_hwrm_ring_free(bp, ring,
2153 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2154 ring->fw_ring_id = INVALID_HW_RING_ID;
2155 memset(txr->tx_desc_ring, 0,
2156 txr->tx_ring_struct->ring_size *
2157 sizeof(*txr->tx_desc_ring));
2158 memset(txr->tx_buf_ring, 0,
2159 txr->tx_ring_struct->ring_size *
2160 sizeof(*txr->tx_buf_ring));
2164 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2165 bnxt_free_cp_ring(bp, cpr);
2166 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2168 bnxt_free_nq_ring(bp, txq->nq_ring);
2172 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2173 bnxt_free_hwrm_rx_ring(bp, i);
2178 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2183 if (!BNXT_HAS_RING_GRPS(bp))
2186 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2187 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2194 void bnxt_free_hwrm_resources(struct bnxt *bp)
2196 /* Release memzone */
2197 rte_free(bp->hwrm_cmd_resp_addr);
2198 rte_free(bp->hwrm_short_cmd_req_addr);
2199 bp->hwrm_cmd_resp_addr = NULL;
2200 bp->hwrm_short_cmd_req_addr = NULL;
2201 bp->hwrm_cmd_resp_dma_addr = 0;
2202 bp->hwrm_short_cmd_req_dma_addr = 0;
2205 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2207 struct rte_pci_device *pdev = bp->pdev;
2208 char type[RTE_MEMZONE_NAMESIZE];
2210 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2211 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2212 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2213 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2214 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2215 if (bp->hwrm_cmd_resp_addr == NULL)
2217 bp->hwrm_cmd_resp_dma_addr =
2218 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2219 if (bp->hwrm_cmd_resp_dma_addr == 0) {
2221 "unable to map response address to physical memory\n");
2224 rte_spinlock_init(&bp->hwrm_lock);
2229 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2231 struct bnxt_filter_info *filter;
2234 STAILQ_FOREACH(filter, &vnic->filter, next) {
2235 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2236 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2237 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2238 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2240 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2241 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2249 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2251 struct bnxt_filter_info *filter;
2252 struct rte_flow *flow;
2255 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2256 filter = flow->filter;
2257 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
2258 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2259 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2260 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2261 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2263 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2265 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2273 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2275 struct bnxt_filter_info *filter;
2278 STAILQ_FOREACH(filter, &vnic->filter, next) {
2279 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2280 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2282 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2283 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2286 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2294 void bnxt_free_tunnel_ports(struct bnxt *bp)
2296 if (bp->vxlan_port_cnt)
2297 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2298 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2300 if (bp->geneve_port_cnt)
2301 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2302 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2303 bp->geneve_port = 0;
2306 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2310 if (bp->vnic_info == NULL)
2314 * Cleanup VNICs in reverse order, to make sure the L2 filter
2315 * from vnic0 is last to be cleaned up.
2317 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2318 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2320 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2322 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2324 if (BNXT_CHIP_THOR(bp)) {
2325 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2326 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2327 vnic->fw_grp_ids[j]);
2328 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2330 vnic->num_lb_ctxts = 0;
2332 bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2333 vnic->rss_rule = INVALID_HW_RING_ID;
2336 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2338 bnxt_hwrm_vnic_free(bp, vnic);
2340 rte_free(vnic->fw_grp_ids);
2342 /* Ring resources */
2343 bnxt_free_all_hwrm_rings(bp);
2344 bnxt_free_all_hwrm_ring_grps(bp);
2345 bnxt_free_all_hwrm_stat_ctxs(bp);
2346 bnxt_free_tunnel_ports(bp);
2349 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2351 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2353 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2354 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2356 switch (conf_link_speed) {
2357 case ETH_LINK_SPEED_10M_HD:
2358 case ETH_LINK_SPEED_100M_HD:
2360 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2362 return hw_link_duplex;
2365 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2367 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2370 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2372 uint16_t eth_link_speed = 0;
2374 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2375 return ETH_LINK_SPEED_AUTONEG;
2377 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2378 case ETH_LINK_SPEED_100M:
2379 case ETH_LINK_SPEED_100M_HD:
2382 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2384 case ETH_LINK_SPEED_1G:
2386 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2388 case ETH_LINK_SPEED_2_5G:
2390 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2392 case ETH_LINK_SPEED_10G:
2394 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2396 case ETH_LINK_SPEED_20G:
2398 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2400 case ETH_LINK_SPEED_25G:
2402 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2404 case ETH_LINK_SPEED_40G:
2406 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2408 case ETH_LINK_SPEED_50G:
2410 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2412 case ETH_LINK_SPEED_100G:
2414 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2418 "Unsupported link speed %d; default to AUTO\n",
2422 return eth_link_speed;
2425 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2426 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2427 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2428 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2430 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2434 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2437 if (link_speed & ETH_LINK_SPEED_FIXED) {
2438 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2440 if (one_speed & (one_speed - 1)) {
2442 "Invalid advertised speeds (%u) for port %u\n",
2443 link_speed, port_id);
2446 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2448 "Unsupported advertised speed (%u) for port %u\n",
2449 link_speed, port_id);
2453 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2455 "Unsupported advertised speeds (%u) for port %u\n",
2456 link_speed, port_id);
2464 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2468 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2469 if (bp->link_info.support_speeds)
2470 return bp->link_info.support_speeds;
2471 link_speed = BNXT_SUPPORTED_SPEEDS;
2474 if (link_speed & ETH_LINK_SPEED_100M)
2475 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2476 if (link_speed & ETH_LINK_SPEED_100M_HD)
2477 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2478 if (link_speed & ETH_LINK_SPEED_1G)
2479 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2480 if (link_speed & ETH_LINK_SPEED_2_5G)
2481 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2482 if (link_speed & ETH_LINK_SPEED_10G)
2483 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2484 if (link_speed & ETH_LINK_SPEED_20G)
2485 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2486 if (link_speed & ETH_LINK_SPEED_25G)
2487 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2488 if (link_speed & ETH_LINK_SPEED_40G)
2489 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2490 if (link_speed & ETH_LINK_SPEED_50G)
2491 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2492 if (link_speed & ETH_LINK_SPEED_100G)
2493 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2497 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2499 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2501 switch (hw_link_speed) {
2502 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2503 eth_link_speed = ETH_SPEED_NUM_100M;
2505 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2506 eth_link_speed = ETH_SPEED_NUM_1G;
2508 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2509 eth_link_speed = ETH_SPEED_NUM_2_5G;
2511 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2512 eth_link_speed = ETH_SPEED_NUM_10G;
2514 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2515 eth_link_speed = ETH_SPEED_NUM_20G;
2517 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2518 eth_link_speed = ETH_SPEED_NUM_25G;
2520 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2521 eth_link_speed = ETH_SPEED_NUM_40G;
2523 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2524 eth_link_speed = ETH_SPEED_NUM_50G;
2526 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2527 eth_link_speed = ETH_SPEED_NUM_100G;
2529 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2531 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2535 return eth_link_speed;
2538 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2540 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2542 switch (hw_link_duplex) {
2543 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2544 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2546 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2548 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2549 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2552 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2556 return eth_link_duplex;
2559 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2562 struct bnxt_link_info *link_info = &bp->link_info;
2564 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2567 "Get link config failed with rc %d\n", rc);
2570 if (link_info->link_speed)
2572 bnxt_parse_hw_link_speed(link_info->link_speed);
2574 link->link_speed = ETH_SPEED_NUM_NONE;
2575 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2576 link->link_status = link_info->link_up;
2577 link->link_autoneg = link_info->auto_mode ==
2578 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2579 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2584 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2587 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2588 struct bnxt_link_info link_req;
2589 uint16_t speed, autoneg;
2591 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2594 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2595 bp->eth_dev->data->port_id);
2599 memset(&link_req, 0, sizeof(link_req));
2600 link_req.link_up = link_up;
2604 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2605 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2606 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2607 /* Autoneg can be done only when the FW allows */
2608 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2609 bp->link_info.force_link_speed)) {
2610 link_req.phy_flags |=
2611 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2612 link_req.auto_link_speed_mask =
2613 bnxt_parse_eth_link_speed_mask(bp,
2614 dev_conf->link_speeds);
2616 if (bp->link_info.phy_type ==
2617 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2618 bp->link_info.phy_type ==
2619 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2620 bp->link_info.media_type ==
2621 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2622 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2626 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2627 /* If user wants a particular speed try that first. */
2629 link_req.link_speed = speed;
2630 else if (bp->link_info.force_link_speed)
2631 link_req.link_speed = bp->link_info.force_link_speed;
2633 link_req.link_speed = bp->link_info.auto_link_speed;
2635 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2636 link_req.auto_pause = bp->link_info.auto_pause;
2637 link_req.force_pause = bp->link_info.force_pause;
2640 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2643 "Set link config failed with rc %d\n", rc);
2651 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2653 struct hwrm_func_qcfg_input req = {0};
2654 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2658 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2659 req.fid = rte_cpu_to_le_16(0xffff);
2661 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2663 HWRM_CHECK_RESULT();
2665 /* Hard Coded.. 0xfff VLAN ID mask */
2666 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2667 flags = rte_le_to_cpu_16(resp->flags);
2668 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2669 bp->flags |= BNXT_FLAG_MULTI_HOST;
2671 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2672 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2673 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2679 switch (resp->port_partition_type) {
2680 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2681 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2682 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2684 bp->port_partition_type = resp->port_partition_type;
2687 bp->port_partition_type = 0;
2696 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2697 struct hwrm_func_qcaps_output *qcaps)
2699 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2700 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2701 sizeof(qcaps->mac_address));
2702 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2703 qcaps->max_rx_rings = fcfg->num_rx_rings;
2704 qcaps->max_tx_rings = fcfg->num_tx_rings;
2705 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2706 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2708 qcaps->first_vf_id = 0;
2709 qcaps->max_vnics = fcfg->num_vnics;
2710 qcaps->max_decap_records = 0;
2711 qcaps->max_encap_records = 0;
2712 qcaps->max_tx_wm_flows = 0;
2713 qcaps->max_tx_em_flows = 0;
2714 qcaps->max_rx_wm_flows = 0;
2715 qcaps->max_rx_em_flows = 0;
2716 qcaps->max_flow_id = 0;
2717 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2718 qcaps->max_sp_tx_rings = 0;
2719 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2722 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2724 struct hwrm_func_cfg_input req = {0};
2725 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2729 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2730 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2731 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2732 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2733 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2734 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2735 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2736 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2737 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2739 if (BNXT_HAS_RING_GRPS(bp)) {
2740 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2741 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2742 } else if (BNXT_HAS_NQ(bp)) {
2743 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2744 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2747 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2748 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2749 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2750 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2752 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2753 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2754 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2755 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2756 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2757 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2758 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2759 req.fid = rte_cpu_to_le_16(0xffff);
2760 req.enables = rte_cpu_to_le_32(enables);
2762 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2764 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2766 HWRM_CHECK_RESULT();
2772 static void populate_vf_func_cfg_req(struct bnxt *bp,
2773 struct hwrm_func_cfg_input *req,
2776 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2777 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2778 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2779 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2780 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2781 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2782 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2783 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2784 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2785 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2787 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2788 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2790 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2791 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2793 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2795 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2796 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2798 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2799 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2800 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2801 /* TODO: For now, do not support VMDq/RFS on VFs. */
2802 req->num_vnics = rte_cpu_to_le_16(1);
2803 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2807 static void add_random_mac_if_needed(struct bnxt *bp,
2808 struct hwrm_func_cfg_input *cfg_req,
2811 struct rte_ether_addr mac;
2813 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2816 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2818 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2819 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2820 bp->pf.vf_info[vf].random_mac = true;
2822 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2823 RTE_ETHER_ADDR_LEN);
2827 static void reserve_resources_from_vf(struct bnxt *bp,
2828 struct hwrm_func_cfg_input *cfg_req,
2831 struct hwrm_func_qcaps_input req = {0};
2832 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2835 /* Get the actual allocated values now */
2836 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2837 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2838 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2841 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2842 copy_func_cfg_to_qcaps(cfg_req, resp);
2843 } else if (resp->error_code) {
2844 rc = rte_le_to_cpu_16(resp->error_code);
2845 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2846 copy_func_cfg_to_qcaps(cfg_req, resp);
2849 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2850 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2851 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2852 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2853 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2854 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2856 * TODO: While not supporting VMDq with VFs, max_vnics is always
2857 * forced to 1 in this case
2859 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2860 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2865 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2867 struct hwrm_func_qcfg_input req = {0};
2868 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2871 /* Check for zero MAC address */
2872 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2873 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2874 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2876 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2878 } else if (resp->error_code) {
2879 rc = rte_le_to_cpu_16(resp->error_code);
2880 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2883 rc = rte_le_to_cpu_16(resp->vlan);
2890 static int update_pf_resource_max(struct bnxt *bp)
2892 struct hwrm_func_qcfg_input req = {0};
2893 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2896 /* And copy the allocated numbers into the pf struct */
2897 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2898 req.fid = rte_cpu_to_le_16(0xffff);
2899 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2900 HWRM_CHECK_RESULT();
2902 /* Only TX ring value reflects actual allocation? TODO */
2903 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2904 bp->pf.evb_mode = resp->evb_mode;
2911 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2916 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2920 rc = bnxt_hwrm_func_qcaps(bp);
2924 bp->pf.func_cfg_flags &=
2925 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2926 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2927 bp->pf.func_cfg_flags |=
2928 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2929 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2930 rc = __bnxt_hwrm_func_qcaps(bp);
2934 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2936 struct hwrm_func_cfg_input req = {0};
2937 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2944 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2948 rc = bnxt_hwrm_func_qcaps(bp);
2953 bp->pf.active_vfs = num_vfs;
2956 * First, configure the PF to only use one TX ring. This ensures that
2957 * there are enough rings for all VFs.
2959 * If we don't do this, when we call func_alloc() later, we will lock
2960 * extra rings to the PF that won't be available during func_cfg() of
2963 * This has been fixed with firmware versions above 20.6.54
2965 bp->pf.func_cfg_flags &=
2966 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2967 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2968 bp->pf.func_cfg_flags |=
2969 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2970 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2975 * Now, create and register a buffer to hold forwarded VF requests
2977 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2978 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2979 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2980 if (bp->pf.vf_req_buf == NULL) {
2984 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2985 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2986 for (i = 0; i < num_vfs; i++)
2987 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2988 (i * HWRM_MAX_REQ_LEN);
2990 rc = bnxt_hwrm_func_buf_rgtr(bp);
2994 populate_vf_func_cfg_req(bp, &req, num_vfs);
2996 bp->pf.active_vfs = 0;
2997 for (i = 0; i < num_vfs; i++) {
2998 add_random_mac_if_needed(bp, &req, i);
3000 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3001 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3002 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3003 rc = bnxt_hwrm_send_message(bp,
3008 /* Clear enable flag for next pass */
3009 req.enables &= ~rte_cpu_to_le_32(
3010 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3012 if (rc || resp->error_code) {
3014 "Failed to initizlie VF %d\n", i);
3016 "Not all VFs available. (%d, %d)\n",
3017 rc, resp->error_code);
3024 reserve_resources_from_vf(bp, &req, i);
3025 bp->pf.active_vfs++;
3026 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3030 * Now configure the PF to use "the rest" of the resources
3031 * We're using STD_TX_RING_MODE here though which will limit the TX
3032 * rings. This will allow QoS to function properly. Not setting this
3033 * will cause PF rings to break bandwidth settings.
3035 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3039 rc = update_pf_resource_max(bp);
3046 bnxt_hwrm_func_buf_unrgtr(bp);
3050 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3052 struct hwrm_func_cfg_input req = {0};
3053 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3056 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3058 req.fid = rte_cpu_to_le_16(0xffff);
3059 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3060 req.evb_mode = bp->pf.evb_mode;
3062 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3063 HWRM_CHECK_RESULT();
3069 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3070 uint8_t tunnel_type)
3072 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3073 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3076 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3077 req.tunnel_type = tunnel_type;
3078 req.tunnel_dst_port_val = port;
3079 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3080 HWRM_CHECK_RESULT();
3082 switch (tunnel_type) {
3083 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3084 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3085 bp->vxlan_port = port;
3087 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3088 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3089 bp->geneve_port = port;
3100 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3101 uint8_t tunnel_type)
3103 struct hwrm_tunnel_dst_port_free_input req = {0};
3104 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3107 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3109 req.tunnel_type = tunnel_type;
3110 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3111 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3113 HWRM_CHECK_RESULT();
3119 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3122 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3123 struct hwrm_func_cfg_input req = {0};
3126 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3128 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3129 req.flags = rte_cpu_to_le_32(flags);
3130 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3132 HWRM_CHECK_RESULT();
3138 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3140 uint32_t *flag = flagp;
3142 vnic->flags = *flag;
3145 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3147 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3150 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3153 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3154 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3156 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3158 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3159 req.req_buf_page_size = rte_cpu_to_le_16(
3160 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3161 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3162 req.req_buf_page_addr0 =
3163 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3164 if (req.req_buf_page_addr0 == 0) {
3166 "unable to map buffer address to physical memory\n");
3170 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3172 HWRM_CHECK_RESULT();
3178 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3181 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3182 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3184 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3186 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3188 HWRM_CHECK_RESULT();
3194 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3196 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3197 struct hwrm_func_cfg_input req = {0};
3200 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3202 req.fid = rte_cpu_to_le_16(0xffff);
3203 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3204 req.enables = rte_cpu_to_le_32(
3205 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3206 req.async_event_cr = rte_cpu_to_le_16(
3207 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3208 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3210 HWRM_CHECK_RESULT();
3216 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3218 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3219 struct hwrm_func_vf_cfg_input req = {0};
3222 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3224 req.enables = rte_cpu_to_le_32(
3225 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3226 req.async_event_cr = rte_cpu_to_le_16(
3227 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3228 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3230 HWRM_CHECK_RESULT();
3236 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3238 struct hwrm_func_cfg_input req = {0};
3239 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3240 uint16_t dflt_vlan, fid;
3241 uint32_t func_cfg_flags;
3244 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3247 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3248 fid = bp->pf.vf_info[vf].fid;
3249 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3251 fid = rte_cpu_to_le_16(0xffff);
3252 func_cfg_flags = bp->pf.func_cfg_flags;
3253 dflt_vlan = bp->vlan;
3256 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3257 req.fid = rte_cpu_to_le_16(fid);
3258 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3259 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3261 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3263 HWRM_CHECK_RESULT();
3269 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3270 uint16_t max_bw, uint16_t enables)
3272 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3273 struct hwrm_func_cfg_input req = {0};
3276 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3278 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3279 req.enables |= rte_cpu_to_le_32(enables);
3280 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3281 req.max_bw = rte_cpu_to_le_32(max_bw);
3282 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3284 HWRM_CHECK_RESULT();
3290 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3292 struct hwrm_func_cfg_input req = {0};
3293 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3296 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3298 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3299 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3300 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3301 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3303 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3305 HWRM_CHECK_RESULT();
3311 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3316 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3318 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3323 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3324 void *encaped, size_t ec_size)
3327 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3328 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3330 if (ec_size > sizeof(req.encap_request))
3333 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3335 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3336 memcpy(req.encap_request, encaped, ec_size);
3338 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3340 HWRM_CHECK_RESULT();
3346 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3347 struct rte_ether_addr *mac)
3349 struct hwrm_func_qcfg_input req = {0};
3350 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3353 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3355 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3356 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3358 HWRM_CHECK_RESULT();
3360 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3367 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3368 void *encaped, size_t ec_size)
3371 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3372 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3374 if (ec_size > sizeof(req.encap_request))
3377 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3379 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3380 memcpy(req.encap_request, encaped, ec_size);
3382 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3384 HWRM_CHECK_RESULT();
3390 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3391 struct rte_eth_stats *stats, uint8_t rx)
3394 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3395 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3397 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3399 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3401 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3403 HWRM_CHECK_RESULT();
3406 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3407 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3408 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3409 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3410 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3411 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3412 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3413 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3415 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3416 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3417 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3418 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3419 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3420 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3429 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3431 struct hwrm_port_qstats_input req = {0};
3432 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3433 struct bnxt_pf_info *pf = &bp->pf;
3436 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3438 req.port_id = rte_cpu_to_le_16(pf->port_id);
3439 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3440 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3441 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3443 HWRM_CHECK_RESULT();
3449 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3451 struct hwrm_port_clr_stats_input req = {0};
3452 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3453 struct bnxt_pf_info *pf = &bp->pf;
3456 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3457 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3458 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3461 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3463 req.port_id = rte_cpu_to_le_16(pf->port_id);
3464 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3466 HWRM_CHECK_RESULT();
3472 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3474 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3475 struct hwrm_port_led_qcaps_input req = {0};
3481 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3482 req.port_id = bp->pf.port_id;
3483 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3485 HWRM_CHECK_RESULT();
3487 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3490 bp->num_leds = resp->num_leds;
3491 memcpy(bp->leds, &resp->led0_id,
3492 sizeof(bp->leds[0]) * bp->num_leds);
3493 for (i = 0; i < bp->num_leds; i++) {
3494 struct bnxt_led_info *led = &bp->leds[i];
3496 uint16_t caps = led->led_state_caps;
3498 if (!led->led_group_id ||
3499 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3511 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3513 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3514 struct hwrm_port_led_cfg_input req = {0};
3515 struct bnxt_led_cfg *led_cfg;
3516 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3517 uint16_t duration = 0;
3520 if (!bp->num_leds || BNXT_VF(bp))
3523 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3526 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3527 duration = rte_cpu_to_le_16(500);
3529 req.port_id = bp->pf.port_id;
3530 req.num_leds = bp->num_leds;
3531 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3532 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3533 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3534 led_cfg->led_id = bp->leds[i].led_id;
3535 led_cfg->led_state = led_state;
3536 led_cfg->led_blink_on = duration;
3537 led_cfg->led_blink_off = duration;
3538 led_cfg->led_group_id = bp->leds[i].led_group_id;
3541 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3543 HWRM_CHECK_RESULT();
3549 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3553 struct hwrm_nvm_get_dir_info_input req = {0};
3554 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3556 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3558 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3560 HWRM_CHECK_RESULT();
3564 *entries = rte_le_to_cpu_32(resp->entries);
3565 *length = rte_le_to_cpu_32(resp->entry_length);
3570 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3573 uint32_t dir_entries;
3574 uint32_t entry_length;
3577 rte_iova_t dma_handle;
3578 struct hwrm_nvm_get_dir_entries_input req = {0};
3579 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3581 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3585 *data++ = dir_entries;
3586 *data++ = entry_length;
3588 memset(data, 0xff, len);
3590 buflen = dir_entries * entry_length;
3591 buf = rte_malloc("nvm_dir", buflen, 0);
3592 rte_mem_lock_page(buf);
3595 dma_handle = rte_mem_virt2iova(buf);
3596 if (dma_handle == 0) {
3598 "unable to map response address to physical memory\n");
3601 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3602 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3603 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3606 memcpy(data, buf, len > buflen ? buflen : len);
3609 HWRM_CHECK_RESULT();
3615 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3616 uint32_t offset, uint32_t length,
3621 rte_iova_t dma_handle;
3622 struct hwrm_nvm_read_input req = {0};
3623 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3625 buf = rte_malloc("nvm_item", length, 0);
3626 rte_mem_lock_page(buf);
3630 dma_handle = rte_mem_virt2iova(buf);
3631 if (dma_handle == 0) {
3633 "unable to map response address to physical memory\n");
3636 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3637 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3638 req.dir_idx = rte_cpu_to_le_16(index);
3639 req.offset = rte_cpu_to_le_32(offset);
3640 req.len = rte_cpu_to_le_32(length);
3641 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3643 memcpy(data, buf, length);
3646 HWRM_CHECK_RESULT();
3652 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3655 struct hwrm_nvm_erase_dir_entry_input req = {0};
3656 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3658 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3659 req.dir_idx = rte_cpu_to_le_16(index);
3660 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3661 HWRM_CHECK_RESULT();
3668 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3669 uint16_t dir_ordinal, uint16_t dir_ext,
3670 uint16_t dir_attr, const uint8_t *data,
3674 struct hwrm_nvm_write_input req = {0};
3675 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3676 rte_iova_t dma_handle;
3679 buf = rte_malloc("nvm_write", data_len, 0);
3680 rte_mem_lock_page(buf);
3684 dma_handle = rte_mem_virt2iova(buf);
3685 if (dma_handle == 0) {
3687 "unable to map response address to physical memory\n");
3690 memcpy(buf, data, data_len);
3692 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3694 req.dir_type = rte_cpu_to_le_16(dir_type);
3695 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3696 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3697 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3698 req.dir_data_length = rte_cpu_to_le_32(data_len);
3699 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3701 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3704 HWRM_CHECK_RESULT();
3711 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3713 uint32_t *count = cbdata;
3715 *count = *count + 1;
3718 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3719 struct bnxt_vnic_info *vnic __rte_unused)
3724 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3728 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3729 &count, bnxt_vnic_count_hwrm_stub);
3734 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3737 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3738 struct hwrm_func_vf_vnic_ids_query_output *resp =
3739 bp->hwrm_cmd_resp_addr;
3742 /* First query all VNIC ids */
3743 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3745 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3746 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3747 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3749 if (req.vnic_id_tbl_addr == 0) {
3752 "unable to map VNIC ID table address to physical memory\n");
3755 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3758 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3760 } else if (resp->error_code) {
3761 rc = rte_le_to_cpu_16(resp->error_code);
3763 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3766 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3774 * This function queries the VNIC IDs for a specified VF. It then calls
3775 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3776 * Then it calls the hwrm_cb function to program this new vnic configuration.
3778 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3779 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3780 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3782 struct bnxt_vnic_info vnic;
3784 int i, num_vnic_ids;
3789 /* First query all VNIC ids */
3790 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3791 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3792 RTE_CACHE_LINE_SIZE);
3793 if (vnic_ids == NULL) {
3797 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3798 rte_mem_lock_page(((char *)vnic_ids) + sz);
3800 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3802 if (num_vnic_ids < 0)
3803 return num_vnic_ids;
3805 /* Retrieve VNIC, update bd_stall then update */
3807 for (i = 0; i < num_vnic_ids; i++) {
3808 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3809 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3810 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3813 if (vnic.mru <= 4) /* Indicates unallocated */
3816 vnic_cb(&vnic, cbdata);
3818 rc = hwrm_cb(bp, &vnic);
3828 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3831 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3832 struct hwrm_func_cfg_input req = {0};
3835 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3837 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3838 req.enables |= rte_cpu_to_le_32(
3839 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3840 req.vlan_antispoof_mode = on ?
3841 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3842 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3843 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3845 HWRM_CHECK_RESULT();
3851 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3853 struct bnxt_vnic_info vnic;
3856 int num_vnic_ids, i;
3860 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3861 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3862 RTE_CACHE_LINE_SIZE);
3863 if (vnic_ids == NULL) {
3868 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3869 rte_mem_lock_page(((char *)vnic_ids) + sz);
3871 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3877 * Loop through to find the default VNIC ID.
3878 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3879 * by sending the hwrm_func_qcfg command to the firmware.
3881 for (i = 0; i < num_vnic_ids; i++) {
3882 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3883 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3884 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3885 bp->pf.first_vf_id + vf);
3888 if (vnic.func_default) {
3890 return vnic.fw_vnic_id;
3893 /* Could not find a default VNIC. */
3894 PMD_DRV_LOG(ERR, "No default VNIC\n");
3900 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3902 struct bnxt_filter_info *filter)
3905 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3906 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3907 uint32_t enables = 0;
3909 if (filter->fw_em_filter_id != UINT64_MAX)
3910 bnxt_hwrm_clear_em_filter(bp, filter);
3912 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3914 req.flags = rte_cpu_to_le_32(filter->flags);
3916 enables = filter->enables |
3917 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3918 req.dst_id = rte_cpu_to_le_16(dst_id);
3920 if (filter->ip_addr_type) {
3921 req.ip_addr_type = filter->ip_addr_type;
3922 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3925 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3926 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3928 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3929 memcpy(req.src_macaddr, filter->src_macaddr,
3930 RTE_ETHER_ADDR_LEN);
3932 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3933 memcpy(req.dst_macaddr, filter->dst_macaddr,
3934 RTE_ETHER_ADDR_LEN);
3936 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3937 req.ovlan_vid = filter->l2_ovlan;
3939 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3940 req.ivlan_vid = filter->l2_ivlan;
3942 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3943 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3945 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3946 req.ip_protocol = filter->ip_protocol;
3948 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3949 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3951 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3952 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3954 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3955 req.src_port = rte_cpu_to_be_16(filter->src_port);
3957 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3958 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3960 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3961 req.mirror_vnic_id = filter->mirror_vnic_id;
3963 req.enables = rte_cpu_to_le_32(enables);
3965 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3967 HWRM_CHECK_RESULT();
3969 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3975 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3978 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3979 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3981 if (filter->fw_em_filter_id == UINT64_MAX)
3984 PMD_DRV_LOG(ERR, "Clear EM filter\n");
3985 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
3987 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3989 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3991 HWRM_CHECK_RESULT();
3994 filter->fw_em_filter_id = UINT64_MAX;
3995 filter->fw_l2_filter_id = UINT64_MAX;
4000 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4002 struct bnxt_filter_info *filter)
4005 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4006 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4007 bp->hwrm_cmd_resp_addr;
4008 uint32_t enables = 0;
4010 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4011 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4013 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4015 req.flags = rte_cpu_to_le_32(filter->flags);
4017 enables = filter->enables |
4018 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4019 req.dst_id = rte_cpu_to_le_16(dst_id);
4022 if (filter->ip_addr_type) {
4023 req.ip_addr_type = filter->ip_addr_type;
4025 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4028 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4029 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4031 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4032 memcpy(req.src_macaddr, filter->src_macaddr,
4033 RTE_ETHER_ADDR_LEN);
4035 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4036 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4037 //RTE_ETHER_ADDR_LEN);
4039 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4040 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4042 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4043 req.ip_protocol = filter->ip_protocol;
4045 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4046 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4048 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4049 req.src_ipaddr_mask[0] =
4050 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4052 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4053 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4055 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4056 req.dst_ipaddr_mask[0] =
4057 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4059 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4060 req.src_port = rte_cpu_to_le_16(filter->src_port);
4062 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4063 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4065 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4066 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4068 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4069 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4071 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4072 req.mirror_vnic_id = filter->mirror_vnic_id;
4074 req.enables = rte_cpu_to_le_32(enables);
4076 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4078 HWRM_CHECK_RESULT();
4080 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4086 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4087 struct bnxt_filter_info *filter)
4090 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4091 struct hwrm_cfa_ntuple_filter_free_output *resp =
4092 bp->hwrm_cmd_resp_addr;
4094 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4097 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4099 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4101 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4103 HWRM_CHECK_RESULT();
4106 filter->fw_ntuple_filter_id = UINT64_MAX;
4112 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4114 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4115 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4116 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4117 int nr_ctxs = bp->max_ring_grps;
4118 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4119 uint16_t *ring_tbl = vnic->rss_table;
4120 int max_rings = bp->rx_nr_rings;
4124 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4126 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4127 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4128 req.hash_mode_flags = vnic->hash_mode;
4130 req.ring_grp_tbl_addr =
4131 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
4132 req.hash_key_tbl_addr =
4133 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4135 for (i = 0, k = 0; i < nr_ctxs; i++) {
4136 struct bnxt_rx_ring_info *rxr;
4137 struct bnxt_cp_ring_info *cpr;
4139 req.ring_table_pair_index = i;
4140 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4142 for (j = 0; j < 64; j++) {
4145 /* Find next active ring. */
4146 for (cnt = 0; cnt < max_rings; cnt++) {
4147 if (rx_queue_state[k] !=
4148 RTE_ETH_QUEUE_STATE_STOPPED)
4150 if (++k == max_rings)
4154 /* Return if no rings are active. */
4155 if (cnt == max_rings)
4158 /* Add rx/cp ring pair to RSS table. */
4159 rxr = rxqs[k]->rx_ring;
4160 cpr = rxqs[k]->cp_ring;
4162 ring_id = rxr->rx_ring_struct->fw_ring_id;
4163 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4164 ring_id = cpr->cp_ring_struct->fw_ring_id;
4165 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4167 if (++k == max_rings)
4170 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4173 HWRM_CHECK_RESULT();
4183 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4185 unsigned int rss_idx, fw_idx, i;
4187 if (!(vnic->rss_table && vnic->hash_type))
4190 if (BNXT_CHIP_THOR(bp))
4191 return bnxt_vnic_rss_configure_thor(bp, vnic);
4194 * Fill the RSS hash & redirection table with
4195 * ring group ids for all VNICs
4197 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4198 rss_idx++, fw_idx++) {
4199 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4200 fw_idx %= bp->rx_cp_nr_rings;
4201 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4205 if (i == bp->rx_cp_nr_rings)
4207 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4209 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4212 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4213 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4217 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4219 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4220 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4222 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4223 req->num_cmpl_dma_aggr_during_int =
4224 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4226 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4228 /* min timer set to 1/2 of interrupt timer */
4229 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4231 /* buf timer set to 1/4 of interrupt timer */
4232 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4234 req->cmpl_aggr_dma_tmr_during_int =
4235 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4237 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4238 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4239 req->flags = rte_cpu_to_le_16(flags);
4242 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4243 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4245 struct hwrm_ring_aggint_qcaps_input req = {0};
4246 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4251 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4252 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4256 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4257 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4259 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4260 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4261 agg_req->flags = rte_cpu_to_le_16(flags);
4263 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4264 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4265 agg_req->enables = rte_cpu_to_le_32(enables);
4268 HWRM_CHECK_RESULT();
4273 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4274 struct bnxt_coal *coal, uint16_t ring_id)
4276 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4277 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4278 bp->hwrm_cmd_resp_addr;
4281 /* Set ring coalesce parameters only for 100G NICs */
4282 if (BNXT_CHIP_THOR(bp)) {
4283 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4285 } else if (bnxt_stratus_device(bp)) {
4286 bnxt_hwrm_set_coal_params(coal, &req);
4291 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4292 req.ring_id = rte_cpu_to_le_16(ring_id);
4293 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4294 HWRM_CHECK_RESULT();
4299 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4300 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4302 struct hwrm_func_backing_store_qcaps_input req = {0};
4303 struct hwrm_func_backing_store_qcaps_output *resp =
4304 bp->hwrm_cmd_resp_addr;
4307 if (!BNXT_CHIP_THOR(bp) ||
4308 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4313 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4314 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4315 HWRM_CHECK_RESULT_SILENT();
4318 struct bnxt_ctx_pg_info *ctx_pg;
4319 struct bnxt_ctx_mem_info *ctx;
4320 int total_alloc_len;
4323 total_alloc_len = sizeof(*ctx);
4324 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4325 RTE_CACHE_LINE_SIZE);
4330 memset(ctx, 0, total_alloc_len);
4332 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4333 sizeof(*ctx_pg) * BNXT_MAX_Q,
4334 RTE_CACHE_LINE_SIZE);
4339 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4340 ctx->tqm_mem[i] = ctx_pg;
4343 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4344 ctx->qp_min_qp1_entries =
4345 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4346 ctx->qp_max_l2_entries =
4347 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4348 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4349 ctx->srq_max_l2_entries =
4350 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4351 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4352 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4353 ctx->cq_max_l2_entries =
4354 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4355 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4356 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4357 ctx->vnic_max_vnic_entries =
4358 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4359 ctx->vnic_max_ring_table_entries =
4360 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4361 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4362 ctx->stat_max_entries =
4363 rte_le_to_cpu_32(resp->stat_max_entries);
4364 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4365 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4366 ctx->tqm_min_entries_per_ring =
4367 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4368 ctx->tqm_max_entries_per_ring =
4369 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4370 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4371 if (!ctx->tqm_entries_multiple)
4372 ctx->tqm_entries_multiple = 1;
4373 ctx->mrav_max_entries =
4374 rte_le_to_cpu_32(resp->mrav_max_entries);
4375 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4376 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4377 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4386 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4388 struct hwrm_func_backing_store_cfg_input req = {0};
4389 struct hwrm_func_backing_store_cfg_output *resp =
4390 bp->hwrm_cmd_resp_addr;
4391 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4392 struct bnxt_ctx_pg_info *ctx_pg;
4393 uint32_t *num_entries;
4402 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4403 req.enables = rte_cpu_to_le_32(enables);
4405 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4406 ctx_pg = &ctx->qp_mem;
4407 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4408 req.qp_num_qp1_entries =
4409 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4410 req.qp_num_l2_entries =
4411 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4412 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4413 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4414 &req.qpc_pg_size_qpc_lvl,
4418 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4419 ctx_pg = &ctx->srq_mem;
4420 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4421 req.srq_num_l2_entries =
4422 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4423 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4424 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4425 &req.srq_pg_size_srq_lvl,
4429 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4430 ctx_pg = &ctx->cq_mem;
4431 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4432 req.cq_num_l2_entries =
4433 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4434 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4435 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4436 &req.cq_pg_size_cq_lvl,
4440 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4441 ctx_pg = &ctx->vnic_mem;
4442 req.vnic_num_vnic_entries =
4443 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4444 req.vnic_num_ring_table_entries =
4445 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4446 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4447 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4448 &req.vnic_pg_size_vnic_lvl,
4449 &req.vnic_page_dir);
4452 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4453 ctx_pg = &ctx->stat_mem;
4454 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4455 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4456 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4457 &req.stat_pg_size_stat_lvl,
4458 &req.stat_page_dir);
4461 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4462 num_entries = &req.tqm_sp_num_entries;
4463 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4464 pg_dir = &req.tqm_sp_page_dir;
4465 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4466 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4467 if (!(enables & ena))
4470 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4472 ctx_pg = ctx->tqm_mem[i];
4473 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4474 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4477 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4478 HWRM_CHECK_RESULT();
4485 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4487 struct hwrm_port_qstats_ext_input req = {0};
4488 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4489 struct bnxt_pf_info *pf = &bp->pf;
4492 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4493 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4496 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4498 req.port_id = rte_cpu_to_le_16(pf->port_id);
4499 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4500 req.tx_stat_host_addr =
4501 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4503 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4505 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4506 req.rx_stat_host_addr =
4507 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4509 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4511 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4514 bp->fw_rx_port_stats_ext_size = 0;
4515 bp->fw_tx_port_stats_ext_size = 0;
4517 bp->fw_rx_port_stats_ext_size =
4518 rte_le_to_cpu_16(resp->rx_stat_size);
4519 bp->fw_tx_port_stats_ext_size =
4520 rte_le_to_cpu_16(resp->tx_stat_size);
4523 HWRM_CHECK_RESULT();
4530 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4532 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4533 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4534 bp->hwrm_cmd_resp_addr;
4537 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_KONG(bp));
4538 req.tunnel_type = type;
4539 req.dest_fid = bp->fw_fid;
4540 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4541 HWRM_CHECK_RESULT();
4549 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4551 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4552 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4553 bp->hwrm_cmd_resp_addr;
4556 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_KONG(bp));
4557 req.tunnel_type = type;
4558 req.dest_fid = bp->fw_fid;
4559 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4560 HWRM_CHECK_RESULT();
4567 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4569 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4570 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4571 bp->hwrm_cmd_resp_addr;
4574 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_KONG(bp));
4575 req.src_fid = bp->fw_fid;
4576 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4577 HWRM_CHECK_RESULT();
4580 *type = resp->tunnel_mask;
4587 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4590 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4591 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4592 bp->hwrm_cmd_resp_addr;
4595 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_KONG(bp));
4596 req.src_fid = bp->fw_fid;
4597 req.tunnel_type = tun_type;
4598 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4599 HWRM_CHECK_RESULT();
4602 *dst_fid = resp->dest_fid;
4604 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);