1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
16 #include "bnxt_filter.h"
17 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_vnic.h"
24 #include "hsi_struct_def_dpdk.h"
28 #define HWRM_SPEC_CODE_1_8_3 0x10803
29 #define HWRM_VERSION_1_9_1 0x10901
30 #define HWRM_VERSION_1_9_2 0x10903
32 struct bnxt_plcmodes_cfg {
34 uint16_t jumbo_thresh;
36 uint16_t hds_threshold;
39 static int page_getenum(size_t size)
55 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
56 return sizeof(void *) * 8 - 1;
59 static int page_roundup(size_t size)
61 return 1 << page_getenum(size);
64 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
68 if (rmem->nr_pages > 1) {
70 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
72 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
77 * HWRM Functions (sent to HWRM)
78 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
79 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
80 * command was failed by the ChiMP.
83 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
84 uint32_t msg_len, bool use_kong_mb)
87 struct input *req = msg;
88 struct output *resp = bp->hwrm_cmd_resp_addr;
92 uint16_t max_req_len = bp->max_req_len;
93 struct hwrm_short_input short_input = { 0 };
94 uint16_t bar_offset = use_kong_mb ?
95 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
96 uint16_t mb_trigger_offset = use_kong_mb ?
97 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
100 /* Do not send HWRM commands to firmware in error state */
101 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
104 /* For VER_GET command, set timeout as 50ms */
105 if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
106 timeout = HWRM_CMD_TIMEOUT;
108 timeout = bp->hwrm_cmd_timeout;
110 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
111 msg_len > bp->max_req_len) {
112 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
114 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
115 memcpy(short_cmd_req, req, msg_len);
117 short_input.req_type = rte_cpu_to_le_16(req->req_type);
118 short_input.signature = rte_cpu_to_le_16(
119 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
120 short_input.size = rte_cpu_to_le_16(msg_len);
121 short_input.req_addr =
122 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
124 data = (uint32_t *)&short_input;
125 msg_len = sizeof(short_input);
127 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
130 /* Write request msg to hwrm channel */
131 for (i = 0; i < msg_len; i += 4) {
132 bar = (uint8_t *)bp->bar0 + bar_offset + i;
133 rte_write32(*data, bar);
137 /* Zero the rest of the request space */
138 for (; i < max_req_len; i += 4) {
139 bar = (uint8_t *)bp->bar0 + bar_offset + i;
143 /* Ring channel doorbell */
144 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
147 * Make sure the channel doorbell ring command complete before
148 * reading the response to avoid getting stale or invalid
153 /* Poll for the valid bit */
154 for (i = 0; i < timeout; i++) {
155 /* Sanity check on the resp->resp_len */
157 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
158 /* Last byte of resp contains the valid key */
159 valid = (uint8_t *)resp + resp->resp_len - 1;
160 if (*valid == HWRM_RESP_VALID_KEY)
167 /* Suppress VER_GET timeout messages during reset recovery */
168 if (bp->flags & BNXT_FLAG_FW_RESET &&
169 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
172 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
180 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
181 * spinlock, and does initial processing.
183 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
184 * releases the spinlock only if it returns. If the regular int return codes
185 * are not used by the function, HWRM_CHECK_RESULT() should not be used
186 * directly, rather it should be copied and modified to suit the function.
188 * HWRM_UNLOCK() must be called after all response processing is completed.
190 #define HWRM_PREP(req, type, kong) do { \
191 rte_spinlock_lock(&bp->hwrm_lock); \
192 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
193 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
194 req.cmpl_ring = rte_cpu_to_le_16(-1); \
195 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
196 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
197 req.target_id = rte_cpu_to_le_16(0xffff); \
198 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
201 #define HWRM_CHECK_RESULT_SILENT() do {\
203 rte_spinlock_unlock(&bp->hwrm_lock); \
206 if (resp->error_code) { \
207 rc = rte_le_to_cpu_16(resp->error_code); \
208 rte_spinlock_unlock(&bp->hwrm_lock); \
213 #define HWRM_CHECK_RESULT() do {\
215 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
216 rte_spinlock_unlock(&bp->hwrm_lock); \
217 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
219 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
221 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
223 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
229 if (resp->error_code) { \
230 rc = rte_le_to_cpu_16(resp->error_code); \
231 if (resp->resp_len >= 16) { \
232 struct hwrm_err_output *tmp_hwrm_err_op = \
235 "error %d:%d:%08x:%04x\n", \
236 rc, tmp_hwrm_err_op->cmd_err, \
238 tmp_hwrm_err_op->opaque_0), \
240 tmp_hwrm_err_op->opaque_1)); \
242 PMD_DRV_LOG(ERR, "error %d\n", rc); \
244 rte_spinlock_unlock(&bp->hwrm_lock); \
245 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
247 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
249 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
251 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
259 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
261 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
264 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
265 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
267 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
268 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
271 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
279 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
280 struct bnxt_vnic_info *vnic,
282 struct bnxt_vlan_table_entry *vlan_table)
285 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
286 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
289 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
292 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
293 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
295 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
296 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
297 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
298 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
300 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
301 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
303 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
304 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
305 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
306 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
307 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
308 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
311 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
312 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
313 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
314 rte_mem_virt2iova(vlan_table));
315 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
317 req.mask = rte_cpu_to_le_32(mask);
319 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
327 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
329 struct bnxt_vlan_antispoof_table_entry *vlan_table)
332 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
333 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
334 bp->hwrm_cmd_resp_addr;
337 * Older HWRM versions did not support this command, and the set_rx_mask
338 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
339 * removed from set_rx_mask call, and this command was added.
341 * This command is also present from 1.7.8.11 and higher,
344 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
345 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
346 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
351 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
352 req.fid = rte_cpu_to_le_16(fid);
354 req.vlan_tag_mask_tbl_addr =
355 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
356 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
358 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
366 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
367 struct bnxt_filter_info *filter)
370 struct bnxt_filter_info *l2_filter = filter;
371 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
372 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
374 if (filter->fw_l2_filter_id == UINT64_MAX)
377 if (filter->matching_l2_fltr_ptr)
378 l2_filter = filter->matching_l2_fltr_ptr;
380 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
381 filter, l2_filter, l2_filter->l2_ref_cnt);
383 if (l2_filter->l2_ref_cnt > 0)
384 l2_filter->l2_ref_cnt--;
386 if (l2_filter->l2_ref_cnt > 0)
389 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
391 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
393 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
398 filter->fw_l2_filter_id = UINT64_MAX;
403 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
405 struct bnxt_filter_info *filter)
408 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
409 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
410 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
411 const struct rte_eth_vmdq_rx_conf *conf =
412 &dev_conf->rx_adv_conf.vmdq_rx_conf;
413 uint32_t enables = 0;
414 uint16_t j = dst_id - 1;
416 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
417 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
418 conf->pool_map[j].pools & (1UL << j)) {
420 "Add vlan %u to vmdq pool %u\n",
421 conf->pool_map[j].vlan_id, j);
423 filter->l2_ivlan = conf->pool_map[j].vlan_id;
425 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
426 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
429 if (filter->fw_l2_filter_id != UINT64_MAX)
430 bnxt_hwrm_clear_l2_filter(bp, filter);
432 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
434 req.flags = rte_cpu_to_le_32(filter->flags);
436 enables = filter->enables |
437 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
438 req.dst_id = rte_cpu_to_le_16(dst_id);
441 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
442 memcpy(req.l2_addr, filter->l2_addr,
445 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
446 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
449 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
450 req.l2_ovlan = filter->l2_ovlan;
452 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
453 req.l2_ivlan = filter->l2_ivlan;
455 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
456 req.l2_ovlan_mask = filter->l2_ovlan_mask;
458 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
459 req.l2_ivlan_mask = filter->l2_ivlan_mask;
460 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
461 req.src_id = rte_cpu_to_le_32(filter->src_id);
462 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
463 req.src_type = filter->src_type;
464 if (filter->pri_hint) {
465 req.pri_hint = filter->pri_hint;
466 req.l2_filter_id_hint =
467 rte_cpu_to_le_64(filter->l2_filter_id_hint);
470 req.enables = rte_cpu_to_le_32(enables);
472 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
476 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
482 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
484 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
485 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
492 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
495 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
498 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
499 if (ptp->tx_tstamp_en)
500 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
503 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
504 req.flags = rte_cpu_to_le_32(flags);
505 req.enables = rte_cpu_to_le_32
506 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
507 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
509 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
515 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
518 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
519 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
520 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
522 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
526 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
528 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
530 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
534 if (!BNXT_CHIP_THOR(bp) &&
535 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
538 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
539 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
541 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
545 if (!BNXT_CHIP_THOR(bp)) {
546 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
547 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
548 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
549 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
550 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
551 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
552 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
553 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
554 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
555 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
556 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
557 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
558 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
559 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
560 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
561 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
562 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
563 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
572 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
575 struct hwrm_func_qcaps_input req = {.req_type = 0 };
576 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
577 uint16_t new_max_vfs;
581 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
583 req.fid = rte_cpu_to_le_16(0xffff);
585 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
589 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
590 flags = rte_le_to_cpu_32(resp->flags);
592 bp->pf.port_id = resp->port_id;
593 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
594 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
595 new_max_vfs = bp->pdev->max_vfs;
596 if (new_max_vfs != bp->pf.max_vfs) {
598 rte_free(bp->pf.vf_info);
599 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
600 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
601 bp->pf.max_vfs = new_max_vfs;
602 for (i = 0; i < new_max_vfs; i++) {
603 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
604 bp->pf.vf_info[i].vlan_table =
605 rte_zmalloc("VF VLAN table",
608 if (bp->pf.vf_info[i].vlan_table == NULL)
610 "Fail to alloc VLAN table for VF %d\n",
614 bp->pf.vf_info[i].vlan_table);
615 bp->pf.vf_info[i].vlan_as_table =
616 rte_zmalloc("VF VLAN AS table",
619 if (bp->pf.vf_info[i].vlan_as_table == NULL)
621 "Alloc VLAN AS table for VF %d fail\n",
625 bp->pf.vf_info[i].vlan_as_table);
626 STAILQ_INIT(&bp->pf.vf_info[i].filter);
631 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
632 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
633 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
634 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
635 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
636 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
637 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
638 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
639 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
640 if (!BNXT_CHIP_THOR(bp))
641 bp->max_l2_ctx += bp->max_rx_em_flows;
642 /* TODO: For now, do not support VMDq/RFS on VFs. */
647 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
651 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
653 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
654 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
655 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
656 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
658 bnxt_hwrm_ptp_qcfg(bp);
662 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
663 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
665 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
666 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
667 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
669 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
672 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
673 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
675 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
682 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
686 rc = __bnxt_hwrm_func_qcaps(bp);
687 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
688 rc = bnxt_alloc_ctx_mem(bp);
692 rc = bnxt_hwrm_func_resc_qcaps(bp);
694 bp->flags |= BNXT_FLAG_NEW_RM;
700 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
701 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
704 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
705 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
707 HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
709 req.target_id = rte_cpu_to_le_16(0xffff);
711 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
715 if (rte_le_to_cpu_32(resp->flags) &
716 HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
717 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
718 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
721 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
728 int bnxt_hwrm_func_reset(struct bnxt *bp)
731 struct hwrm_func_reset_input req = {.req_type = 0 };
732 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
734 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
736 req.enables = rte_cpu_to_le_32(0);
738 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
746 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
750 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
751 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
753 if (bp->flags & BNXT_FLAG_REGISTERED)
756 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
757 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
758 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
760 /* PFs and trusted VFs should indicate the support of the
761 * Master capability on non Stingray platform
763 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
764 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
766 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
767 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
768 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
769 req.ver_maj = RTE_VER_YEAR;
770 req.ver_min = RTE_VER_MONTH;
771 req.ver_upd = RTE_VER_MINOR;
774 req.enables |= rte_cpu_to_le_32(
775 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
776 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
777 RTE_MIN(sizeof(req.vf_req_fwd),
778 sizeof(bp->pf.vf_req_fwd)));
781 * PF can sniff HWRM API issued by VF. This can be set up by
782 * linux driver and inherited by the DPDK PF driver. Clear
783 * this HWRM sniffer list in FW because DPDK PF driver does
786 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
789 req.flags = rte_cpu_to_le_32(flags);
791 req.async_event_fwd[0] |=
792 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
793 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
794 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
795 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
796 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
797 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
798 req.async_event_fwd[0] |=
799 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
800 req.async_event_fwd[1] |=
801 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
802 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
804 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
808 flags = rte_le_to_cpu_32(resp->flags);
809 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
810 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
814 bp->flags |= BNXT_FLAG_REGISTERED;
819 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
821 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
824 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
827 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
832 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
833 struct hwrm_func_vf_cfg_input req = {0};
835 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
837 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
838 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
839 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
840 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
841 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
843 if (BNXT_HAS_RING_GRPS(bp)) {
844 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
845 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
848 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
849 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
850 AGG_RING_MULTIPLIER);
851 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
852 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
854 BNXT_NUM_ASYNC_CPR(bp));
855 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
856 if (bp->vf_resv_strategy ==
857 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
858 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
859 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
860 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
861 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
862 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
863 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
867 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
868 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
869 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
870 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
871 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
872 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
874 if (test && BNXT_HAS_RING_GRPS(bp))
875 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
877 req.flags = rte_cpu_to_le_32(flags);
878 req.enables |= rte_cpu_to_le_32(enables);
880 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
883 HWRM_CHECK_RESULT_SILENT();
891 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
894 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
895 struct hwrm_func_resource_qcaps_input req = {0};
897 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
898 req.fid = rte_cpu_to_le_16(0xffff);
900 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
905 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
906 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
907 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
908 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
909 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
910 /* func_resource_qcaps does not return max_rx_em_flows.
911 * So use the value provided by func_qcaps.
913 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
914 if (!BNXT_CHIP_THOR(bp))
915 bp->max_l2_ctx += bp->max_rx_em_flows;
916 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
917 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
919 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
920 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
921 if (bp->vf_resv_strategy >
922 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
923 bp->vf_resv_strategy =
924 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
930 int bnxt_hwrm_ver_get(struct bnxt *bp)
933 struct hwrm_ver_get_input req = {.req_type = 0 };
934 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
936 uint16_t max_resp_len;
937 char type[RTE_MEMZONE_NAMESIZE];
938 uint32_t dev_caps_cfg;
940 bp->max_req_len = HWRM_MAX_REQ_LEN;
941 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
943 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
944 req.hwrm_intf_min = HWRM_VERSION_MINOR;
945 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
947 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
949 if (bp->flags & BNXT_FLAG_FW_RESET)
950 HWRM_CHECK_RESULT_SILENT();
954 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
955 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
956 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
957 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
958 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
959 (resp->hwrm_fw_min_8b << 16) |
960 (resp->hwrm_fw_bld_8b << 8) |
961 resp->hwrm_fw_rsvd_8b;
962 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
963 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
965 fw_version = resp->hwrm_intf_maj_8b << 16;
966 fw_version |= resp->hwrm_intf_min_8b << 8;
967 fw_version |= resp->hwrm_intf_upd_8b;
968 bp->hwrm_spec_code = fw_version;
970 /* def_req_timeout value is in milliseconds */
971 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
972 /* convert timeout to usec */
973 bp->hwrm_cmd_timeout *= 1000;
974 if (!bp->hwrm_cmd_timeout)
975 bp->hwrm_cmd_timeout = HWRM_CMD_TIMEOUT;
977 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
978 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
983 if (bp->max_req_len > resp->max_req_win_len) {
984 PMD_DRV_LOG(ERR, "Unsupported request length\n");
987 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
988 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
989 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
990 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
992 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
993 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
995 if (bp->max_resp_len != max_resp_len) {
996 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
997 bp->pdev->addr.domain, bp->pdev->addr.bus,
998 bp->pdev->addr.devid, bp->pdev->addr.function);
1000 rte_free(bp->hwrm_cmd_resp_addr);
1002 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1003 if (bp->hwrm_cmd_resp_addr == NULL) {
1007 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1008 bp->hwrm_cmd_resp_dma_addr =
1009 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1010 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1012 "Unable to map response buffer to physical memory.\n");
1016 bp->max_resp_len = max_resp_len;
1020 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1022 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1023 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1024 bp->flags |= BNXT_FLAG_SHORT_CMD;
1027 if (((dev_caps_cfg &
1028 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1030 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1031 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1032 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1033 bp->pdev->addr.domain, bp->pdev->addr.bus,
1034 bp->pdev->addr.devid, bp->pdev->addr.function);
1036 rte_free(bp->hwrm_short_cmd_req_addr);
1038 bp->hwrm_short_cmd_req_addr =
1039 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1040 if (bp->hwrm_short_cmd_req_addr == NULL) {
1044 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1045 bp->hwrm_short_cmd_req_dma_addr =
1046 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1047 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1048 rte_free(bp->hwrm_short_cmd_req_addr);
1050 "Unable to map buffer to physical memory.\n");
1056 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1057 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1058 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1061 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1062 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1064 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1065 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1066 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1074 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1077 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1078 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1080 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1083 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1086 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1088 HWRM_CHECK_RESULT();
1094 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1097 struct hwrm_port_phy_cfg_input req = {0};
1098 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1099 uint32_t enables = 0;
1101 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1103 if (conf->link_up) {
1104 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1105 if (bp->link_info.auto_mode && conf->link_speed) {
1106 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1107 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1110 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1111 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1112 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1114 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1115 * any auto mode, even "none".
1117 if (!conf->link_speed) {
1118 /* No speeds specified. Enable AutoNeg - all speeds */
1120 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1122 /* AutoNeg - Advertise speeds specified. */
1123 if (conf->auto_link_speed_mask &&
1124 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1126 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1127 req.auto_link_speed_mask =
1128 conf->auto_link_speed_mask;
1130 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1133 req.auto_duplex = conf->duplex;
1134 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1135 req.auto_pause = conf->auto_pause;
1136 req.force_pause = conf->force_pause;
1137 /* Set force_pause if there is no auto or if there is a force */
1138 if (req.auto_pause && !req.force_pause)
1139 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1141 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1143 req.enables = rte_cpu_to_le_32(enables);
1146 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1147 PMD_DRV_LOG(INFO, "Force Link Down\n");
1150 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1152 HWRM_CHECK_RESULT();
1158 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1159 struct bnxt_link_info *link_info)
1162 struct hwrm_port_phy_qcfg_input req = {0};
1163 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1165 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1167 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1169 HWRM_CHECK_RESULT();
1171 link_info->phy_link_status = resp->link;
1172 link_info->link_up =
1173 (link_info->phy_link_status ==
1174 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1175 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1176 link_info->duplex = resp->duplex_cfg;
1177 link_info->pause = resp->pause;
1178 link_info->auto_pause = resp->auto_pause;
1179 link_info->force_pause = resp->force_pause;
1180 link_info->auto_mode = resp->auto_mode;
1181 link_info->phy_type = resp->phy_type;
1182 link_info->media_type = resp->media_type;
1184 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1185 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1186 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1187 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1188 link_info->phy_ver[0] = resp->phy_maj;
1189 link_info->phy_ver[1] = resp->phy_min;
1190 link_info->phy_ver[2] = resp->phy_bld;
1194 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1195 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1196 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1197 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1198 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1199 link_info->auto_link_speed_mask);
1200 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1201 link_info->force_link_speed);
1206 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1209 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1210 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1211 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1215 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1217 req.flags = rte_cpu_to_le_32(dir);
1218 /* HWRM Version >= 1.9.1 */
1219 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1221 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1222 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1224 HWRM_CHECK_RESULT();
1226 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1227 GET_TX_QUEUE_INFO(0);
1228 GET_TX_QUEUE_INFO(1);
1229 GET_TX_QUEUE_INFO(2);
1230 GET_TX_QUEUE_INFO(3);
1231 GET_TX_QUEUE_INFO(4);
1232 GET_TX_QUEUE_INFO(5);
1233 GET_TX_QUEUE_INFO(6);
1234 GET_TX_QUEUE_INFO(7);
1236 GET_RX_QUEUE_INFO(0);
1237 GET_RX_QUEUE_INFO(1);
1238 GET_RX_QUEUE_INFO(2);
1239 GET_RX_QUEUE_INFO(3);
1240 GET_RX_QUEUE_INFO(4);
1241 GET_RX_QUEUE_INFO(5);
1242 GET_RX_QUEUE_INFO(6);
1243 GET_RX_QUEUE_INFO(7);
1248 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1251 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1252 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1256 /* iterate and find the COSq profile to use for Tx */
1257 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1258 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1259 if (bp->tx_cos_queue[i].id != 0xff)
1260 bp->tx_cosq_id[j++] =
1261 bp->tx_cos_queue[i].id;
1264 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1265 if (bp->tx_cos_queue[i].profile ==
1266 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1268 bp->tx_cos_queue[i].id;
1275 bp->max_tc = resp->max_configurable_queues;
1276 bp->max_lltc = resp->max_configurable_lossless_queues;
1277 if (bp->max_tc > BNXT_MAX_QUEUE)
1278 bp->max_tc = BNXT_MAX_QUEUE;
1279 bp->max_q = bp->max_tc;
1281 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1282 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1290 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1291 struct bnxt_ring *ring,
1292 uint32_t ring_type, uint32_t map_index,
1293 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1294 uint16_t tx_cosq_id)
1297 uint32_t enables = 0;
1298 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1299 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1300 struct rte_mempool *mb_pool;
1301 uint16_t rx_buf_size;
1303 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1305 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1306 req.fbo = rte_cpu_to_le_32(0);
1307 /* Association of ring index with doorbell index */
1308 req.logical_id = rte_cpu_to_le_16(map_index);
1309 req.length = rte_cpu_to_le_32(ring->ring_size);
1311 switch (ring_type) {
1312 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1313 req.ring_type = ring_type;
1314 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1315 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1316 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1317 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1319 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1321 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1322 req.ring_type = ring_type;
1323 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1324 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1325 if (BNXT_CHIP_THOR(bp)) {
1326 mb_pool = bp->rx_queues[0]->mb_pool;
1327 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1328 RTE_PKTMBUF_HEADROOM;
1329 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1330 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1332 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1334 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1336 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1338 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1339 req.ring_type = ring_type;
1340 if (BNXT_HAS_NQ(bp)) {
1341 /* Association of cp ring with nq */
1342 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1344 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1346 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1348 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1349 req.ring_type = ring_type;
1350 req.page_size = BNXT_PAGE_SHFT;
1351 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1353 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1354 req.ring_type = ring_type;
1355 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1357 mb_pool = bp->rx_queues[0]->mb_pool;
1358 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1359 RTE_PKTMBUF_HEADROOM;
1360 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1361 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1363 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1364 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1365 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1366 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1369 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1374 req.enables = rte_cpu_to_le_32(enables);
1376 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1378 if (rc || resp->error_code) {
1379 if (rc == 0 && resp->error_code)
1380 rc = rte_le_to_cpu_16(resp->error_code);
1381 switch (ring_type) {
1382 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1384 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1387 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1389 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1392 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1394 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1398 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1400 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1403 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1405 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1409 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1415 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1420 int bnxt_hwrm_ring_free(struct bnxt *bp,
1421 struct bnxt_ring *ring, uint32_t ring_type)
1424 struct hwrm_ring_free_input req = {.req_type = 0 };
1425 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1427 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1429 req.ring_type = ring_type;
1430 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1432 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1434 if (rc || resp->error_code) {
1435 if (rc == 0 && resp->error_code)
1436 rc = rte_le_to_cpu_16(resp->error_code);
1439 switch (ring_type) {
1440 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1441 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1444 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1445 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1448 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1449 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1452 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1454 "hwrm_ring_free nq failed. rc:%d\n", rc);
1456 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1458 "hwrm_ring_free agg failed. rc:%d\n", rc);
1461 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1469 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1472 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1473 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1475 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1477 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1478 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1479 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1480 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1482 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1484 HWRM_CHECK_RESULT();
1486 bp->grp_info[idx].fw_grp_id =
1487 rte_le_to_cpu_16(resp->ring_group_id);
1494 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1497 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1498 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1500 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1502 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1504 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1506 HWRM_CHECK_RESULT();
1509 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1513 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1516 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1517 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1519 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1522 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1524 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1526 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1528 HWRM_CHECK_RESULT();
1534 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1535 unsigned int idx __rte_unused)
1538 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1539 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1541 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1543 req.update_period_ms = rte_cpu_to_le_32(0);
1545 req.stats_dma_addr =
1546 rte_cpu_to_le_64(cpr->hw_stats_map);
1548 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1550 HWRM_CHECK_RESULT();
1552 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1559 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1560 unsigned int idx __rte_unused)
1563 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1564 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1566 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1568 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1570 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1572 HWRM_CHECK_RESULT();
1578 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1581 struct hwrm_vnic_alloc_input req = { 0 };
1582 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1584 if (!BNXT_HAS_RING_GRPS(bp))
1585 goto skip_ring_grps;
1587 /* map ring groups to this vnic */
1588 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1589 vnic->start_grp_id, vnic->end_grp_id);
1590 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1591 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1593 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1594 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1595 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1596 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1599 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1600 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1601 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1603 if (vnic->func_default)
1605 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1606 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1608 HWRM_CHECK_RESULT();
1610 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1612 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1616 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1617 struct bnxt_vnic_info *vnic,
1618 struct bnxt_plcmodes_cfg *pmode)
1621 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1622 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1624 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1626 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1628 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1630 HWRM_CHECK_RESULT();
1632 pmode->flags = rte_le_to_cpu_32(resp->flags);
1633 /* dflt_vnic bit doesn't exist in the _cfg command */
1634 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1635 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1636 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1637 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1644 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1645 struct bnxt_vnic_info *vnic,
1646 struct bnxt_plcmodes_cfg *pmode)
1649 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1650 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1652 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1653 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1657 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1659 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1660 req.flags = rte_cpu_to_le_32(pmode->flags);
1661 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1662 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1663 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1664 req.enables = rte_cpu_to_le_32(
1665 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1666 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1667 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1670 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1672 HWRM_CHECK_RESULT();
1678 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1681 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1682 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1683 struct bnxt_plcmodes_cfg pmodes = { 0 };
1684 uint32_t ctx_enable_flag = 0;
1685 uint32_t enables = 0;
1687 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1688 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1692 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1696 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1698 if (BNXT_CHIP_THOR(bp)) {
1699 struct bnxt_rx_queue *rxq =
1700 bp->eth_dev->data->rx_queues[vnic->start_grp_id];
1701 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1702 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1704 req.default_rx_ring_id =
1705 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1706 req.default_cmpl_ring_id =
1707 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1708 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1709 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1713 /* Only RSS support for now TBD: COS & LB */
1714 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1715 if (vnic->lb_rule != 0xffff)
1716 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1717 if (vnic->cos_rule != 0xffff)
1718 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1719 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1720 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1721 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1723 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1724 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1725 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1728 enables |= ctx_enable_flag;
1729 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1730 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1731 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1732 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1735 req.enables = rte_cpu_to_le_32(enables);
1736 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1737 req.mru = rte_cpu_to_le_16(vnic->mru);
1738 /* Configure default VNIC only once. */
1739 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1741 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1742 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1744 if (vnic->vlan_strip)
1746 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1749 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1750 if (vnic->roce_dual)
1751 req.flags |= rte_cpu_to_le_32(
1752 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1753 if (vnic->roce_only)
1754 req.flags |= rte_cpu_to_le_32(
1755 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1756 if (vnic->rss_dflt_cr)
1757 req.flags |= rte_cpu_to_le_32(
1758 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1760 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1762 HWRM_CHECK_RESULT();
1765 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1770 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1774 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1775 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1777 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1778 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1781 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1784 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1785 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1786 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1788 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1790 HWRM_CHECK_RESULT();
1792 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1793 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1794 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1795 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1796 vnic->mru = rte_le_to_cpu_16(resp->mru);
1797 vnic->func_default = rte_le_to_cpu_32(
1798 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1799 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1800 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1801 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1802 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1803 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1804 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1805 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1806 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1807 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1808 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1815 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1816 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1820 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1821 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1822 bp->hwrm_cmd_resp_addr;
1824 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1826 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1827 HWRM_CHECK_RESULT();
1829 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1830 if (!BNXT_HAS_RING_GRPS(bp))
1831 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1832 else if (ctx_idx == 0)
1833 vnic->rss_rule = ctx_id;
1841 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1842 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1845 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1846 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1847 bp->hwrm_cmd_resp_addr;
1849 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1850 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1853 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1855 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1857 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1859 HWRM_CHECK_RESULT();
1865 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1869 if (BNXT_CHIP_THOR(bp)) {
1872 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1873 rc = _bnxt_hwrm_vnic_ctx_free(bp,
1875 vnic->fw_grp_ids[j]);
1876 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1878 vnic->num_lb_ctxts = 0;
1880 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1881 vnic->rss_rule = INVALID_HW_RING_ID;
1887 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1890 struct hwrm_vnic_free_input req = {.req_type = 0 };
1891 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1893 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1894 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1898 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1900 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1902 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1904 HWRM_CHECK_RESULT();
1907 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1908 /* Configure default VNIC again if necessary. */
1909 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1910 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1916 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1920 int nr_ctxs = vnic->num_lb_ctxts;
1921 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1922 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1924 for (i = 0; i < nr_ctxs; i++) {
1925 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1927 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1928 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1929 req.hash_mode_flags = vnic->hash_mode;
1931 req.hash_key_tbl_addr =
1932 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1934 req.ring_grp_tbl_addr =
1935 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1936 i * HW_HASH_INDEX_SIZE);
1937 req.ring_table_pair_index = i;
1938 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1940 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1943 HWRM_CHECK_RESULT();
1950 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1951 struct bnxt_vnic_info *vnic)
1954 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1955 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1957 if (!vnic->rss_table)
1960 if (BNXT_CHIP_THOR(bp))
1961 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1963 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1965 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1966 req.hash_mode_flags = vnic->hash_mode;
1968 req.ring_grp_tbl_addr =
1969 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1970 req.hash_key_tbl_addr =
1971 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1972 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1973 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1975 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1977 HWRM_CHECK_RESULT();
1983 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1984 struct bnxt_vnic_info *vnic)
1987 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1988 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1991 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1992 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1996 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1998 req.flags = rte_cpu_to_le_32(
1999 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2001 req.enables = rte_cpu_to_le_32(
2002 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2004 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2005 size -= RTE_PKTMBUF_HEADROOM;
2006 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2008 req.jumbo_thresh = rte_cpu_to_le_16(size);
2009 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2011 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2013 HWRM_CHECK_RESULT();
2019 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2020 struct bnxt_vnic_info *vnic, bool enable)
2023 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2024 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2026 if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2028 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2032 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2033 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2037 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2040 req.enables = rte_cpu_to_le_32(
2041 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2042 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2043 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2044 req.flags = rte_cpu_to_le_32(
2045 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2046 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2047 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2048 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2049 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2050 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2051 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2052 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2053 req.min_agg_len = rte_cpu_to_le_32(512);
2055 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2057 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2059 HWRM_CHECK_RESULT();
2065 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2067 struct hwrm_func_cfg_input req = {0};
2068 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2071 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2072 req.enables = rte_cpu_to_le_32(
2073 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2074 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2075 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2077 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2079 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2080 HWRM_CHECK_RESULT();
2083 bp->pf.vf_info[vf].random_mac = false;
2088 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2092 struct hwrm_func_qstats_input req = {.req_type = 0};
2093 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2095 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2097 req.fid = rte_cpu_to_le_16(fid);
2099 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2101 HWRM_CHECK_RESULT();
2104 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2111 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2112 struct rte_eth_stats *stats)
2115 struct hwrm_func_qstats_input req = {.req_type = 0};
2116 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2118 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2120 req.fid = rte_cpu_to_le_16(fid);
2122 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2124 HWRM_CHECK_RESULT();
2126 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2127 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2128 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2129 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2130 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2131 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2133 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2134 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2135 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2136 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2137 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2138 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2140 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2141 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2142 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2149 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2152 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2153 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2155 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2157 req.fid = rte_cpu_to_le_16(fid);
2159 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2161 HWRM_CHECK_RESULT();
2168 * HWRM utility functions
2171 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2176 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2177 struct bnxt_tx_queue *txq;
2178 struct bnxt_rx_queue *rxq;
2179 struct bnxt_cp_ring_info *cpr;
2181 if (i >= bp->rx_cp_nr_rings) {
2182 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2185 rxq = bp->rx_queues[i];
2189 rc = bnxt_hwrm_stat_clear(bp, cpr);
2196 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2200 struct bnxt_cp_ring_info *cpr;
2202 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2204 if (i >= bp->rx_cp_nr_rings) {
2205 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2207 cpr = bp->rx_queues[i]->cp_ring;
2208 if (BNXT_HAS_RING_GRPS(bp))
2209 bp->grp_info[i].fw_stats_ctx = -1;
2211 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2212 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2213 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2221 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2226 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2227 struct bnxt_tx_queue *txq;
2228 struct bnxt_rx_queue *rxq;
2229 struct bnxt_cp_ring_info *cpr;
2231 if (i >= bp->rx_cp_nr_rings) {
2232 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2235 rxq = bp->rx_queues[i];
2239 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2247 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2252 if (!BNXT_HAS_RING_GRPS(bp))
2255 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2257 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2260 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2268 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2270 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2272 bnxt_hwrm_ring_free(bp, cp_ring,
2273 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2274 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2275 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2276 sizeof(*cpr->cp_desc_ring));
2277 cpr->cp_raw_cons = 0;
2281 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2283 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2285 bnxt_hwrm_ring_free(bp, cp_ring,
2286 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2287 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2288 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2289 sizeof(*cpr->cp_desc_ring));
2290 cpr->cp_raw_cons = 0;
2294 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2296 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2297 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2298 struct bnxt_ring *ring = rxr->rx_ring_struct;
2299 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2301 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2302 bnxt_hwrm_ring_free(bp, ring,
2303 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2304 ring->fw_ring_id = INVALID_HW_RING_ID;
2305 if (BNXT_HAS_RING_GRPS(bp))
2306 bp->grp_info[queue_index].rx_fw_ring_id =
2308 memset(rxr->rx_desc_ring, 0,
2309 rxr->rx_ring_struct->ring_size *
2310 sizeof(*rxr->rx_desc_ring));
2311 memset(rxr->rx_buf_ring, 0,
2312 rxr->rx_ring_struct->ring_size *
2313 sizeof(*rxr->rx_buf_ring));
2316 ring = rxr->ag_ring_struct;
2317 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2318 bnxt_hwrm_ring_free(bp, ring,
2319 BNXT_CHIP_THOR(bp) ?
2320 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2321 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2322 ring->fw_ring_id = INVALID_HW_RING_ID;
2323 memset(rxr->ag_buf_ring, 0,
2324 rxr->ag_ring_struct->ring_size *
2325 sizeof(*rxr->ag_buf_ring));
2327 if (BNXT_HAS_RING_GRPS(bp))
2328 bp->grp_info[queue_index].ag_fw_ring_id =
2331 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2332 bnxt_free_cp_ring(bp, cpr);
2334 if (BNXT_HAS_RING_GRPS(bp))
2335 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2338 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2342 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2343 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2344 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2345 struct bnxt_ring *ring = txr->tx_ring_struct;
2346 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2348 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2349 bnxt_hwrm_ring_free(bp, ring,
2350 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2351 ring->fw_ring_id = INVALID_HW_RING_ID;
2352 memset(txr->tx_desc_ring, 0,
2353 txr->tx_ring_struct->ring_size *
2354 sizeof(*txr->tx_desc_ring));
2355 memset(txr->tx_buf_ring, 0,
2356 txr->tx_ring_struct->ring_size *
2357 sizeof(*txr->tx_buf_ring));
2361 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2362 bnxt_free_cp_ring(bp, cpr);
2363 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2367 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2368 bnxt_free_hwrm_rx_ring(bp, i);
2373 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2378 if (!BNXT_HAS_RING_GRPS(bp))
2381 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2382 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2389 void bnxt_free_hwrm_resources(struct bnxt *bp)
2391 /* Release memzone */
2392 rte_free(bp->hwrm_cmd_resp_addr);
2393 rte_free(bp->hwrm_short_cmd_req_addr);
2394 bp->hwrm_cmd_resp_addr = NULL;
2395 bp->hwrm_short_cmd_req_addr = NULL;
2396 bp->hwrm_cmd_resp_dma_addr = 0;
2397 bp->hwrm_short_cmd_req_dma_addr = 0;
2400 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2402 struct rte_pci_device *pdev = bp->pdev;
2403 char type[RTE_MEMZONE_NAMESIZE];
2405 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2406 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2407 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2408 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2409 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2410 if (bp->hwrm_cmd_resp_addr == NULL)
2412 bp->hwrm_cmd_resp_dma_addr =
2413 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2414 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2416 "unable to map response address to physical memory\n");
2419 rte_spinlock_init(&bp->hwrm_lock);
2424 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2426 struct bnxt_filter_info *filter;
2429 STAILQ_FOREACH(filter, &vnic->filter, next) {
2430 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2431 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2432 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2433 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2435 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2436 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2437 bnxt_free_filter(bp, filter);
2445 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2447 struct bnxt_filter_info *filter;
2448 struct rte_flow *flow;
2451 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2452 flow = STAILQ_FIRST(&vnic->flow_list);
2453 filter = flow->filter;
2454 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2455 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2456 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2457 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2458 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2460 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2462 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2470 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2472 struct bnxt_filter_info *filter;
2475 STAILQ_FOREACH(filter, &vnic->filter, next) {
2476 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2477 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2479 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2480 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2483 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2494 void bnxt_free_tunnel_ports(struct bnxt *bp)
2496 if (bp->vxlan_port_cnt)
2497 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2498 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2500 if (bp->geneve_port_cnt)
2501 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2502 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2503 bp->geneve_port = 0;
2506 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2510 if (bp->vnic_info == NULL)
2514 * Cleanup VNICs in reverse order, to make sure the L2 filter
2515 * from vnic0 is last to be cleaned up.
2517 for (i = bp->max_vnics - 1; i >= 0; i--) {
2518 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2520 // If the VNIC ID is invalid we are not currently using the VNIC
2521 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2524 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2526 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2528 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2530 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2532 bnxt_hwrm_vnic_free(bp, vnic);
2534 rte_free(vnic->fw_grp_ids);
2536 /* Ring resources */
2537 bnxt_free_all_hwrm_rings(bp);
2538 bnxt_free_all_hwrm_ring_grps(bp);
2539 bnxt_free_all_hwrm_stat_ctxs(bp);
2540 bnxt_free_tunnel_ports(bp);
2543 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2545 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2547 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2548 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2550 switch (conf_link_speed) {
2551 case ETH_LINK_SPEED_10M_HD:
2552 case ETH_LINK_SPEED_100M_HD:
2554 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2556 return hw_link_duplex;
2559 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2561 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2564 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2566 uint16_t eth_link_speed = 0;
2568 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2569 return ETH_LINK_SPEED_AUTONEG;
2571 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2572 case ETH_LINK_SPEED_100M:
2573 case ETH_LINK_SPEED_100M_HD:
2576 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2578 case ETH_LINK_SPEED_1G:
2580 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2582 case ETH_LINK_SPEED_2_5G:
2584 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2586 case ETH_LINK_SPEED_10G:
2588 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2590 case ETH_LINK_SPEED_20G:
2592 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2594 case ETH_LINK_SPEED_25G:
2596 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2598 case ETH_LINK_SPEED_40G:
2600 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2602 case ETH_LINK_SPEED_50G:
2604 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2606 case ETH_LINK_SPEED_100G:
2608 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2612 "Unsupported link speed %d; default to AUTO\n",
2616 return eth_link_speed;
2619 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2620 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2621 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2622 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2624 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2628 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2631 if (link_speed & ETH_LINK_SPEED_FIXED) {
2632 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2634 if (one_speed & (one_speed - 1)) {
2636 "Invalid advertised speeds (%u) for port %u\n",
2637 link_speed, port_id);
2640 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2642 "Unsupported advertised speed (%u) for port %u\n",
2643 link_speed, port_id);
2647 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2649 "Unsupported advertised speeds (%u) for port %u\n",
2650 link_speed, port_id);
2658 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2662 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2663 if (bp->link_info.support_speeds)
2664 return bp->link_info.support_speeds;
2665 link_speed = BNXT_SUPPORTED_SPEEDS;
2668 if (link_speed & ETH_LINK_SPEED_100M)
2669 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2670 if (link_speed & ETH_LINK_SPEED_100M_HD)
2671 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2672 if (link_speed & ETH_LINK_SPEED_1G)
2673 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2674 if (link_speed & ETH_LINK_SPEED_2_5G)
2675 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2676 if (link_speed & ETH_LINK_SPEED_10G)
2677 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2678 if (link_speed & ETH_LINK_SPEED_20G)
2679 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2680 if (link_speed & ETH_LINK_SPEED_25G)
2681 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2682 if (link_speed & ETH_LINK_SPEED_40G)
2683 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2684 if (link_speed & ETH_LINK_SPEED_50G)
2685 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2686 if (link_speed & ETH_LINK_SPEED_100G)
2687 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2691 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2693 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2695 switch (hw_link_speed) {
2696 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2697 eth_link_speed = ETH_SPEED_NUM_100M;
2699 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2700 eth_link_speed = ETH_SPEED_NUM_1G;
2702 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2703 eth_link_speed = ETH_SPEED_NUM_2_5G;
2705 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2706 eth_link_speed = ETH_SPEED_NUM_10G;
2708 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2709 eth_link_speed = ETH_SPEED_NUM_20G;
2711 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2712 eth_link_speed = ETH_SPEED_NUM_25G;
2714 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2715 eth_link_speed = ETH_SPEED_NUM_40G;
2717 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2718 eth_link_speed = ETH_SPEED_NUM_50G;
2720 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2721 eth_link_speed = ETH_SPEED_NUM_100G;
2723 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2725 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2729 return eth_link_speed;
2732 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2734 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2736 switch (hw_link_duplex) {
2737 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2738 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2740 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2742 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2743 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2746 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2750 return eth_link_duplex;
2753 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2756 struct bnxt_link_info *link_info = &bp->link_info;
2758 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2761 "Get link config failed with rc %d\n", rc);
2764 if (link_info->link_speed)
2766 bnxt_parse_hw_link_speed(link_info->link_speed);
2768 link->link_speed = ETH_SPEED_NUM_NONE;
2769 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2770 link->link_status = link_info->link_up;
2771 link->link_autoneg = link_info->auto_mode ==
2772 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2773 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2778 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2781 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2782 struct bnxt_link_info link_req;
2783 uint16_t speed, autoneg;
2785 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2788 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2789 bp->eth_dev->data->port_id);
2793 memset(&link_req, 0, sizeof(link_req));
2794 link_req.link_up = link_up;
2798 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2799 if (BNXT_CHIP_THOR(bp) &&
2800 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2801 /* 40G is not supported as part of media auto detect.
2802 * The speed should be forced and autoneg disabled
2803 * to configure 40G speed.
2805 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2809 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2810 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2811 /* Autoneg can be done only when the FW allows.
2812 * When user configures fixed speed of 40G and later changes to
2813 * any other speed, auto_link_speed/force_link_speed is still set
2814 * to 40G until link comes up at new speed.
2817 !(!BNXT_CHIP_THOR(bp) &&
2818 (bp->link_info.auto_link_speed ||
2819 bp->link_info.force_link_speed))) {
2820 link_req.phy_flags |=
2821 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2822 link_req.auto_link_speed_mask =
2823 bnxt_parse_eth_link_speed_mask(bp,
2824 dev_conf->link_speeds);
2826 if (bp->link_info.phy_type ==
2827 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2828 bp->link_info.phy_type ==
2829 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2830 bp->link_info.media_type ==
2831 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2832 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2836 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2837 /* If user wants a particular speed try that first. */
2839 link_req.link_speed = speed;
2840 else if (bp->link_info.force_link_speed)
2841 link_req.link_speed = bp->link_info.force_link_speed;
2843 link_req.link_speed = bp->link_info.auto_link_speed;
2845 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2846 link_req.auto_pause = bp->link_info.auto_pause;
2847 link_req.force_pause = bp->link_info.force_pause;
2850 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2853 "Set link config failed with rc %d\n", rc);
2861 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2863 struct hwrm_func_qcfg_input req = {0};
2864 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2868 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2869 req.fid = rte_cpu_to_le_16(0xffff);
2871 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2873 HWRM_CHECK_RESULT();
2875 /* Hard Coded.. 0xfff VLAN ID mask */
2876 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2877 flags = rte_le_to_cpu_16(resp->flags);
2878 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2879 bp->flags |= BNXT_FLAG_MULTI_HOST;
2882 !BNXT_VF_IS_TRUSTED(bp) &&
2883 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2884 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2885 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2886 } else if (BNXT_VF(bp) &&
2887 BNXT_VF_IS_TRUSTED(bp) &&
2888 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2889 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2890 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2896 switch (resp->port_partition_type) {
2897 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2898 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2899 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2901 bp->port_partition_type = resp->port_partition_type;
2904 bp->port_partition_type = 0;
2913 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2914 struct hwrm_func_qcaps_output *qcaps)
2916 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2917 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2918 sizeof(qcaps->mac_address));
2919 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2920 qcaps->max_rx_rings = fcfg->num_rx_rings;
2921 qcaps->max_tx_rings = fcfg->num_tx_rings;
2922 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2923 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2925 qcaps->first_vf_id = 0;
2926 qcaps->max_vnics = fcfg->num_vnics;
2927 qcaps->max_decap_records = 0;
2928 qcaps->max_encap_records = 0;
2929 qcaps->max_tx_wm_flows = 0;
2930 qcaps->max_tx_em_flows = 0;
2931 qcaps->max_rx_wm_flows = 0;
2932 qcaps->max_rx_em_flows = 0;
2933 qcaps->max_flow_id = 0;
2934 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2935 qcaps->max_sp_tx_rings = 0;
2936 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2939 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2941 struct hwrm_func_cfg_input req = {0};
2942 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2946 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2947 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2948 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2949 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2950 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2951 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2952 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2953 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2954 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2956 if (BNXT_HAS_RING_GRPS(bp)) {
2957 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2958 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2959 } else if (BNXT_HAS_NQ(bp)) {
2960 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2961 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2964 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2965 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2966 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2967 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2969 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2970 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2971 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2972 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2973 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2974 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2975 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2976 req.fid = rte_cpu_to_le_16(0xffff);
2977 req.enables = rte_cpu_to_le_32(enables);
2979 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2981 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2983 HWRM_CHECK_RESULT();
2989 static void populate_vf_func_cfg_req(struct bnxt *bp,
2990 struct hwrm_func_cfg_input *req,
2993 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2994 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2995 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2996 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2997 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2998 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2999 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3000 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3001 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3002 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3004 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3005 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3007 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3008 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3010 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3012 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3013 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3015 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3016 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3017 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3018 /* TODO: For now, do not support VMDq/RFS on VFs. */
3019 req->num_vnics = rte_cpu_to_le_16(1);
3020 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3024 static void add_random_mac_if_needed(struct bnxt *bp,
3025 struct hwrm_func_cfg_input *cfg_req,
3028 struct rte_ether_addr mac;
3030 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3033 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3035 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3036 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3037 bp->pf.vf_info[vf].random_mac = true;
3039 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3040 RTE_ETHER_ADDR_LEN);
3044 static void reserve_resources_from_vf(struct bnxt *bp,
3045 struct hwrm_func_cfg_input *cfg_req,
3048 struct hwrm_func_qcaps_input req = {0};
3049 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3052 /* Get the actual allocated values now */
3053 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3054 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3055 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3058 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3059 copy_func_cfg_to_qcaps(cfg_req, resp);
3060 } else if (resp->error_code) {
3061 rc = rte_le_to_cpu_16(resp->error_code);
3062 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3063 copy_func_cfg_to_qcaps(cfg_req, resp);
3066 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3067 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3068 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3069 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3070 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3071 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3073 * TODO: While not supporting VMDq with VFs, max_vnics is always
3074 * forced to 1 in this case
3076 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3077 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3082 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3084 struct hwrm_func_qcfg_input req = {0};
3085 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3088 /* Check for zero MAC address */
3089 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3090 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3091 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3092 HWRM_CHECK_RESULT();
3093 rc = rte_le_to_cpu_16(resp->vlan);
3100 static int update_pf_resource_max(struct bnxt *bp)
3102 struct hwrm_func_qcfg_input req = {0};
3103 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3106 /* And copy the allocated numbers into the pf struct */
3107 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3108 req.fid = rte_cpu_to_le_16(0xffff);
3109 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3110 HWRM_CHECK_RESULT();
3112 /* Only TX ring value reflects actual allocation? TODO */
3113 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3114 bp->pf.evb_mode = resp->evb_mode;
3121 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3126 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3130 rc = bnxt_hwrm_func_qcaps(bp);
3134 bp->pf.func_cfg_flags &=
3135 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3136 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3137 bp->pf.func_cfg_flags |=
3138 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3139 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3140 rc = __bnxt_hwrm_func_qcaps(bp);
3144 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3146 struct hwrm_func_cfg_input req = {0};
3147 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3154 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3158 rc = bnxt_hwrm_func_qcaps(bp);
3163 bp->pf.active_vfs = num_vfs;
3166 * First, configure the PF to only use one TX ring. This ensures that
3167 * there are enough rings for all VFs.
3169 * If we don't do this, when we call func_alloc() later, we will lock
3170 * extra rings to the PF that won't be available during func_cfg() of
3173 * This has been fixed with firmware versions above 20.6.54
3175 bp->pf.func_cfg_flags &=
3176 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3177 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3178 bp->pf.func_cfg_flags |=
3179 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3180 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3185 * Now, create and register a buffer to hold forwarded VF requests
3187 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3188 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3189 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3190 if (bp->pf.vf_req_buf == NULL) {
3194 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3195 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3196 for (i = 0; i < num_vfs; i++)
3197 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3198 (i * HWRM_MAX_REQ_LEN);
3200 rc = bnxt_hwrm_func_buf_rgtr(bp);
3204 populate_vf_func_cfg_req(bp, &req, num_vfs);
3206 bp->pf.active_vfs = 0;
3207 for (i = 0; i < num_vfs; i++) {
3208 add_random_mac_if_needed(bp, &req, i);
3210 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3211 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3212 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3213 rc = bnxt_hwrm_send_message(bp,
3218 /* Clear enable flag for next pass */
3219 req.enables &= ~rte_cpu_to_le_32(
3220 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3222 if (rc || resp->error_code) {
3224 "Failed to initizlie VF %d\n", i);
3226 "Not all VFs available. (%d, %d)\n",
3227 rc, resp->error_code);
3234 reserve_resources_from_vf(bp, &req, i);
3235 bp->pf.active_vfs++;
3236 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3240 * Now configure the PF to use "the rest" of the resources
3241 * We're using STD_TX_RING_MODE here though which will limit the TX
3242 * rings. This will allow QoS to function properly. Not setting this
3243 * will cause PF rings to break bandwidth settings.
3245 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3249 rc = update_pf_resource_max(bp);
3256 bnxt_hwrm_func_buf_unrgtr(bp);
3260 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3262 struct hwrm_func_cfg_input req = {0};
3263 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3266 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3268 req.fid = rte_cpu_to_le_16(0xffff);
3269 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3270 req.evb_mode = bp->pf.evb_mode;
3272 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3273 HWRM_CHECK_RESULT();
3279 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3280 uint8_t tunnel_type)
3282 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3283 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3286 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3287 req.tunnel_type = tunnel_type;
3288 req.tunnel_dst_port_val = port;
3289 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3290 HWRM_CHECK_RESULT();
3292 switch (tunnel_type) {
3293 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3294 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3295 bp->vxlan_port = port;
3297 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3298 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3299 bp->geneve_port = port;
3310 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3311 uint8_t tunnel_type)
3313 struct hwrm_tunnel_dst_port_free_input req = {0};
3314 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3317 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3319 req.tunnel_type = tunnel_type;
3320 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3321 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3323 HWRM_CHECK_RESULT();
3329 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3332 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3333 struct hwrm_func_cfg_input req = {0};
3336 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3338 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3339 req.flags = rte_cpu_to_le_32(flags);
3340 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3342 HWRM_CHECK_RESULT();
3348 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3350 uint32_t *flag = flagp;
3352 vnic->flags = *flag;
3355 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3357 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3360 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3363 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3364 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3366 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3368 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3369 req.req_buf_page_size = rte_cpu_to_le_16(
3370 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3371 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3372 req.req_buf_page_addr0 =
3373 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3374 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3376 "unable to map buffer address to physical memory\n");
3380 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3382 HWRM_CHECK_RESULT();
3388 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3391 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3392 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3394 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3397 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3399 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3401 HWRM_CHECK_RESULT();
3407 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3409 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3410 struct hwrm_func_cfg_input req = {0};
3413 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3415 req.fid = rte_cpu_to_le_16(0xffff);
3416 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3417 req.enables = rte_cpu_to_le_32(
3418 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3419 req.async_event_cr = rte_cpu_to_le_16(
3420 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3421 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3423 HWRM_CHECK_RESULT();
3429 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3431 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3432 struct hwrm_func_vf_cfg_input req = {0};
3435 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3437 req.enables = rte_cpu_to_le_32(
3438 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3439 req.async_event_cr = rte_cpu_to_le_16(
3440 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3441 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3443 HWRM_CHECK_RESULT();
3449 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3451 struct hwrm_func_cfg_input req = {0};
3452 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3453 uint16_t dflt_vlan, fid;
3454 uint32_t func_cfg_flags;
3457 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3460 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3461 fid = bp->pf.vf_info[vf].fid;
3462 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3464 fid = rte_cpu_to_le_16(0xffff);
3465 func_cfg_flags = bp->pf.func_cfg_flags;
3466 dflt_vlan = bp->vlan;
3469 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3470 req.fid = rte_cpu_to_le_16(fid);
3471 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3472 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3474 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3476 HWRM_CHECK_RESULT();
3482 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3483 uint16_t max_bw, uint16_t enables)
3485 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3486 struct hwrm_func_cfg_input req = {0};
3489 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3491 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3492 req.enables |= rte_cpu_to_le_32(enables);
3493 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3494 req.max_bw = rte_cpu_to_le_32(max_bw);
3495 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3497 HWRM_CHECK_RESULT();
3503 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3505 struct hwrm_func_cfg_input req = {0};
3506 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3509 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3511 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3512 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3513 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3514 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3516 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3518 HWRM_CHECK_RESULT();
3524 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3529 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3531 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3536 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3537 void *encaped, size_t ec_size)
3540 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3541 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3543 if (ec_size > sizeof(req.encap_request))
3546 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3548 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3549 memcpy(req.encap_request, encaped, ec_size);
3551 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3553 HWRM_CHECK_RESULT();
3559 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3560 struct rte_ether_addr *mac)
3562 struct hwrm_func_qcfg_input req = {0};
3563 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3566 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3568 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3569 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3571 HWRM_CHECK_RESULT();
3573 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3580 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3581 void *encaped, size_t ec_size)
3584 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3585 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3587 if (ec_size > sizeof(req.encap_request))
3590 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3592 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3593 memcpy(req.encap_request, encaped, ec_size);
3595 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3597 HWRM_CHECK_RESULT();
3603 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3604 struct rte_eth_stats *stats, uint8_t rx)
3607 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3608 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3610 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3612 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3614 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3616 HWRM_CHECK_RESULT();
3619 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3620 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3621 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3622 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3623 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3624 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3625 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3626 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3628 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3629 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3630 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3631 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3632 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3633 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3642 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3644 struct hwrm_port_qstats_input req = {0};
3645 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3646 struct bnxt_pf_info *pf = &bp->pf;
3649 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3651 req.port_id = rte_cpu_to_le_16(pf->port_id);
3652 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3653 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3654 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3656 HWRM_CHECK_RESULT();
3662 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3664 struct hwrm_port_clr_stats_input req = {0};
3665 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3666 struct bnxt_pf_info *pf = &bp->pf;
3669 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3670 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3671 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3674 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3676 req.port_id = rte_cpu_to_le_16(pf->port_id);
3677 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3679 HWRM_CHECK_RESULT();
3685 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3687 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3688 struct hwrm_port_led_qcaps_input req = {0};
3694 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3695 req.port_id = bp->pf.port_id;
3696 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3698 HWRM_CHECK_RESULT();
3700 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3703 bp->num_leds = resp->num_leds;
3704 memcpy(bp->leds, &resp->led0_id,
3705 sizeof(bp->leds[0]) * bp->num_leds);
3706 for (i = 0; i < bp->num_leds; i++) {
3707 struct bnxt_led_info *led = &bp->leds[i];
3709 uint16_t caps = led->led_state_caps;
3711 if (!led->led_group_id ||
3712 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3724 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3726 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3727 struct hwrm_port_led_cfg_input req = {0};
3728 struct bnxt_led_cfg *led_cfg;
3729 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3730 uint16_t duration = 0;
3733 if (!bp->num_leds || BNXT_VF(bp))
3736 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3739 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3740 duration = rte_cpu_to_le_16(500);
3742 req.port_id = bp->pf.port_id;
3743 req.num_leds = bp->num_leds;
3744 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3745 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3746 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3747 led_cfg->led_id = bp->leds[i].led_id;
3748 led_cfg->led_state = led_state;
3749 led_cfg->led_blink_on = duration;
3750 led_cfg->led_blink_off = duration;
3751 led_cfg->led_group_id = bp->leds[i].led_group_id;
3754 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3756 HWRM_CHECK_RESULT();
3762 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3766 struct hwrm_nvm_get_dir_info_input req = {0};
3767 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3769 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3771 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3773 HWRM_CHECK_RESULT();
3775 *entries = rte_le_to_cpu_32(resp->entries);
3776 *length = rte_le_to_cpu_32(resp->entry_length);
3782 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3785 uint32_t dir_entries;
3786 uint32_t entry_length;
3789 rte_iova_t dma_handle;
3790 struct hwrm_nvm_get_dir_entries_input req = {0};
3791 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3793 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3797 *data++ = dir_entries;
3798 *data++ = entry_length;
3800 memset(data, 0xff, len);
3802 buflen = dir_entries * entry_length;
3803 buf = rte_malloc("nvm_dir", buflen, 0);
3804 rte_mem_lock_page(buf);
3807 dma_handle = rte_mem_virt2iova(buf);
3808 if (dma_handle == RTE_BAD_IOVA) {
3810 "unable to map response address to physical memory\n");
3813 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3814 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3815 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3818 memcpy(data, buf, len > buflen ? buflen : len);
3821 HWRM_CHECK_RESULT();
3827 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3828 uint32_t offset, uint32_t length,
3833 rte_iova_t dma_handle;
3834 struct hwrm_nvm_read_input req = {0};
3835 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3837 buf = rte_malloc("nvm_item", length, 0);
3838 rte_mem_lock_page(buf);
3842 dma_handle = rte_mem_virt2iova(buf);
3843 if (dma_handle == RTE_BAD_IOVA) {
3845 "unable to map response address to physical memory\n");
3848 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3849 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3850 req.dir_idx = rte_cpu_to_le_16(index);
3851 req.offset = rte_cpu_to_le_32(offset);
3852 req.len = rte_cpu_to_le_32(length);
3853 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3855 memcpy(data, buf, length);
3858 HWRM_CHECK_RESULT();
3864 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3867 struct hwrm_nvm_erase_dir_entry_input req = {0};
3868 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3870 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3871 req.dir_idx = rte_cpu_to_le_16(index);
3872 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3873 HWRM_CHECK_RESULT();
3880 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3881 uint16_t dir_ordinal, uint16_t dir_ext,
3882 uint16_t dir_attr, const uint8_t *data,
3886 struct hwrm_nvm_write_input req = {0};
3887 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3888 rte_iova_t dma_handle;
3891 buf = rte_malloc("nvm_write", data_len, 0);
3892 rte_mem_lock_page(buf);
3896 dma_handle = rte_mem_virt2iova(buf);
3897 if (dma_handle == RTE_BAD_IOVA) {
3899 "unable to map response address to physical memory\n");
3902 memcpy(buf, data, data_len);
3904 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3906 req.dir_type = rte_cpu_to_le_16(dir_type);
3907 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3908 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3909 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3910 req.dir_data_length = rte_cpu_to_le_32(data_len);
3911 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3913 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3916 HWRM_CHECK_RESULT();
3923 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3925 uint32_t *count = cbdata;
3927 *count = *count + 1;
3930 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3931 struct bnxt_vnic_info *vnic __rte_unused)
3936 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3940 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3941 &count, bnxt_vnic_count_hwrm_stub);
3946 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3949 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3950 struct hwrm_func_vf_vnic_ids_query_output *resp =
3951 bp->hwrm_cmd_resp_addr;
3954 /* First query all VNIC ids */
3955 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3957 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3958 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3959 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3961 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3964 "unable to map VNIC ID table address to physical memory\n");
3967 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3968 HWRM_CHECK_RESULT();
3969 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3977 * This function queries the VNIC IDs for a specified VF. It then calls
3978 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3979 * Then it calls the hwrm_cb function to program this new vnic configuration.
3981 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3982 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3983 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3985 struct bnxt_vnic_info vnic;
3987 int i, num_vnic_ids;
3992 /* First query all VNIC ids */
3993 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3994 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3995 RTE_CACHE_LINE_SIZE);
3996 if (vnic_ids == NULL)
3999 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4000 rte_mem_lock_page(((char *)vnic_ids) + sz);
4002 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4004 if (num_vnic_ids < 0)
4005 return num_vnic_ids;
4007 /* Retrieve VNIC, update bd_stall then update */
4009 for (i = 0; i < num_vnic_ids; i++) {
4010 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4011 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4012 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4015 if (vnic.mru <= 4) /* Indicates unallocated */
4018 vnic_cb(&vnic, cbdata);
4020 rc = hwrm_cb(bp, &vnic);
4030 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4033 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4034 struct hwrm_func_cfg_input req = {0};
4037 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4039 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4040 req.enables |= rte_cpu_to_le_32(
4041 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4042 req.vlan_antispoof_mode = on ?
4043 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4044 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4045 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4047 HWRM_CHECK_RESULT();
4053 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4055 struct bnxt_vnic_info vnic;
4058 int num_vnic_ids, i;
4062 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4063 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4064 RTE_CACHE_LINE_SIZE);
4065 if (vnic_ids == NULL)
4068 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4069 rte_mem_lock_page(((char *)vnic_ids) + sz);
4071 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4077 * Loop through to find the default VNIC ID.
4078 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4079 * by sending the hwrm_func_qcfg command to the firmware.
4081 for (i = 0; i < num_vnic_ids; i++) {
4082 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4083 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4084 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4085 bp->pf.first_vf_id + vf);
4088 if (vnic.func_default) {
4090 return vnic.fw_vnic_id;
4093 /* Could not find a default VNIC. */
4094 PMD_DRV_LOG(ERR, "No default VNIC\n");
4100 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4102 struct bnxt_filter_info *filter)
4105 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4106 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4107 uint32_t enables = 0;
4109 if (filter->fw_em_filter_id != UINT64_MAX)
4110 bnxt_hwrm_clear_em_filter(bp, filter);
4112 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4114 req.flags = rte_cpu_to_le_32(filter->flags);
4116 enables = filter->enables |
4117 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4118 req.dst_id = rte_cpu_to_le_16(dst_id);
4120 if (filter->ip_addr_type) {
4121 req.ip_addr_type = filter->ip_addr_type;
4122 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4125 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4126 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4128 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4129 memcpy(req.src_macaddr, filter->src_macaddr,
4130 RTE_ETHER_ADDR_LEN);
4132 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4133 memcpy(req.dst_macaddr, filter->dst_macaddr,
4134 RTE_ETHER_ADDR_LEN);
4136 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4137 req.ovlan_vid = filter->l2_ovlan;
4139 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4140 req.ivlan_vid = filter->l2_ivlan;
4142 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4143 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4145 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4146 req.ip_protocol = filter->ip_protocol;
4148 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4149 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4151 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4152 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4154 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4155 req.src_port = rte_cpu_to_be_16(filter->src_port);
4157 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4158 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4160 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4161 req.mirror_vnic_id = filter->mirror_vnic_id;
4163 req.enables = rte_cpu_to_le_32(enables);
4165 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4167 HWRM_CHECK_RESULT();
4169 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4175 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4178 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4179 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4181 if (filter->fw_em_filter_id == UINT64_MAX)
4184 PMD_DRV_LOG(ERR, "Clear EM filter\n");
4185 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4187 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4189 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4191 HWRM_CHECK_RESULT();
4194 filter->fw_em_filter_id = UINT64_MAX;
4195 filter->fw_l2_filter_id = UINT64_MAX;
4200 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4202 struct bnxt_filter_info *filter)
4205 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4206 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4207 bp->hwrm_cmd_resp_addr;
4208 uint32_t enables = 0;
4210 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4211 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4213 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4215 req.flags = rte_cpu_to_le_32(filter->flags);
4217 enables = filter->enables |
4218 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4219 req.dst_id = rte_cpu_to_le_16(dst_id);
4222 if (filter->ip_addr_type) {
4223 req.ip_addr_type = filter->ip_addr_type;
4225 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4228 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4229 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4231 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4232 memcpy(req.src_macaddr, filter->src_macaddr,
4233 RTE_ETHER_ADDR_LEN);
4235 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4236 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4237 //RTE_ETHER_ADDR_LEN);
4239 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4240 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4242 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4243 req.ip_protocol = filter->ip_protocol;
4245 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4246 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4248 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4249 req.src_ipaddr_mask[0] =
4250 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4252 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4253 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4255 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4256 req.dst_ipaddr_mask[0] =
4257 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4259 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4260 req.src_port = rte_cpu_to_le_16(filter->src_port);
4262 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4263 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4265 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4266 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4268 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4269 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4271 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4272 req.mirror_vnic_id = filter->mirror_vnic_id;
4274 req.enables = rte_cpu_to_le_32(enables);
4276 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4278 HWRM_CHECK_RESULT();
4280 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4286 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4287 struct bnxt_filter_info *filter)
4290 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4291 struct hwrm_cfa_ntuple_filter_free_output *resp =
4292 bp->hwrm_cmd_resp_addr;
4294 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4297 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4299 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4301 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4303 HWRM_CHECK_RESULT();
4306 filter->fw_ntuple_filter_id = UINT64_MAX;
4312 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4314 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4315 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4316 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4317 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4318 uint16_t *ring_tbl = vnic->rss_table;
4319 int nr_ctxs = vnic->num_lb_ctxts;
4320 int max_rings = bp->rx_nr_rings;
4324 for (i = 0, k = 0; i < nr_ctxs; i++) {
4325 struct bnxt_rx_ring_info *rxr;
4326 struct bnxt_cp_ring_info *cpr;
4328 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4330 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4331 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4332 req.hash_mode_flags = vnic->hash_mode;
4334 req.ring_grp_tbl_addr =
4335 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4336 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4337 2 * sizeof(*ring_tbl));
4338 req.hash_key_tbl_addr =
4339 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4341 req.ring_table_pair_index = i;
4342 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4344 for (j = 0; j < 64; j++) {
4347 /* Find next active ring. */
4348 for (cnt = 0; cnt < max_rings; cnt++) {
4349 if (rx_queue_state[k] !=
4350 RTE_ETH_QUEUE_STATE_STOPPED)
4352 if (++k == max_rings)
4356 /* Return if no rings are active. */
4357 if (cnt == max_rings)
4360 /* Add rx/cp ring pair to RSS table. */
4361 rxr = rxqs[k]->rx_ring;
4362 cpr = rxqs[k]->cp_ring;
4364 ring_id = rxr->rx_ring_struct->fw_ring_id;
4365 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4366 ring_id = cpr->cp_ring_struct->fw_ring_id;
4367 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4369 if (++k == max_rings)
4372 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4375 HWRM_CHECK_RESULT();
4382 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4384 unsigned int rss_idx, fw_idx, i;
4386 if (!(vnic->rss_table && vnic->hash_type))
4389 if (BNXT_CHIP_THOR(bp))
4390 return bnxt_vnic_rss_configure_thor(bp, vnic);
4392 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4395 if (vnic->rss_table && vnic->hash_type) {
4397 * Fill the RSS hash & redirection table with
4398 * ring group ids for all VNICs
4400 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4401 rss_idx++, fw_idx++) {
4402 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4403 fw_idx %= bp->rx_cp_nr_rings;
4404 if (vnic->fw_grp_ids[fw_idx] !=
4409 if (i == bp->rx_cp_nr_rings)
4411 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4413 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4419 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4420 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4424 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4426 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4427 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4429 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4430 req->num_cmpl_dma_aggr_during_int =
4431 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4433 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4435 /* min timer set to 1/2 of interrupt timer */
4436 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4438 /* buf timer set to 1/4 of interrupt timer */
4439 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4441 req->cmpl_aggr_dma_tmr_during_int =
4442 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4444 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4445 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4446 req->flags = rte_cpu_to_le_16(flags);
4449 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4450 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4452 struct hwrm_ring_aggint_qcaps_input req = {0};
4453 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4458 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4459 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4460 HWRM_CHECK_RESULT();
4462 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4463 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4465 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4466 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4467 agg_req->flags = rte_cpu_to_le_16(flags);
4469 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4470 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4471 agg_req->enables = rte_cpu_to_le_32(enables);
4477 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4478 struct bnxt_coal *coal, uint16_t ring_id)
4480 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4481 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4482 bp->hwrm_cmd_resp_addr;
4485 /* Set ring coalesce parameters only for 100G NICs */
4486 if (BNXT_CHIP_THOR(bp)) {
4487 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4489 } else if (bnxt_stratus_device(bp)) {
4490 bnxt_hwrm_set_coal_params(coal, &req);
4495 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4496 req.ring_id = rte_cpu_to_le_16(ring_id);
4497 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4498 HWRM_CHECK_RESULT();
4503 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4504 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4506 struct hwrm_func_backing_store_qcaps_input req = {0};
4507 struct hwrm_func_backing_store_qcaps_output *resp =
4508 bp->hwrm_cmd_resp_addr;
4509 struct bnxt_ctx_pg_info *ctx_pg;
4510 struct bnxt_ctx_mem_info *ctx;
4511 int total_alloc_len;
4514 if (!BNXT_CHIP_THOR(bp) ||
4515 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4520 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4521 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4522 HWRM_CHECK_RESULT_SILENT();
4524 total_alloc_len = sizeof(*ctx);
4525 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4526 RTE_CACHE_LINE_SIZE);
4532 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4533 sizeof(*ctx_pg) * BNXT_MAX_Q,
4534 RTE_CACHE_LINE_SIZE);
4539 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4540 ctx->tqm_mem[i] = ctx_pg;
4543 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4544 ctx->qp_min_qp1_entries =
4545 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4546 ctx->qp_max_l2_entries =
4547 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4548 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4549 ctx->srq_max_l2_entries =
4550 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4551 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4552 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4553 ctx->cq_max_l2_entries =
4554 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4555 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4556 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4557 ctx->vnic_max_vnic_entries =
4558 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4559 ctx->vnic_max_ring_table_entries =
4560 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4561 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4562 ctx->stat_max_entries =
4563 rte_le_to_cpu_32(resp->stat_max_entries);
4564 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4565 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4566 ctx->tqm_min_entries_per_ring =
4567 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4568 ctx->tqm_max_entries_per_ring =
4569 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4570 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4571 if (!ctx->tqm_entries_multiple)
4572 ctx->tqm_entries_multiple = 1;
4573 ctx->mrav_max_entries =
4574 rte_le_to_cpu_32(resp->mrav_max_entries);
4575 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4576 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4577 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4583 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4585 struct hwrm_func_backing_store_cfg_input req = {0};
4586 struct hwrm_func_backing_store_cfg_output *resp =
4587 bp->hwrm_cmd_resp_addr;
4588 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4589 struct bnxt_ctx_pg_info *ctx_pg;
4590 uint32_t *num_entries;
4599 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4600 req.enables = rte_cpu_to_le_32(enables);
4602 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4603 ctx_pg = &ctx->qp_mem;
4604 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4605 req.qp_num_qp1_entries =
4606 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4607 req.qp_num_l2_entries =
4608 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4609 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4610 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4611 &req.qpc_pg_size_qpc_lvl,
4615 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4616 ctx_pg = &ctx->srq_mem;
4617 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4618 req.srq_num_l2_entries =
4619 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4620 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4621 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4622 &req.srq_pg_size_srq_lvl,
4626 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4627 ctx_pg = &ctx->cq_mem;
4628 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4629 req.cq_num_l2_entries =
4630 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4631 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4632 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4633 &req.cq_pg_size_cq_lvl,
4637 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4638 ctx_pg = &ctx->vnic_mem;
4639 req.vnic_num_vnic_entries =
4640 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4641 req.vnic_num_ring_table_entries =
4642 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4643 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4644 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4645 &req.vnic_pg_size_vnic_lvl,
4646 &req.vnic_page_dir);
4649 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4650 ctx_pg = &ctx->stat_mem;
4651 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4652 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4653 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4654 &req.stat_pg_size_stat_lvl,
4655 &req.stat_page_dir);
4658 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4659 num_entries = &req.tqm_sp_num_entries;
4660 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4661 pg_dir = &req.tqm_sp_page_dir;
4662 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4663 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4664 if (!(enables & ena))
4667 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4669 ctx_pg = ctx->tqm_mem[i];
4670 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4671 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4674 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4675 HWRM_CHECK_RESULT();
4681 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4683 struct hwrm_port_qstats_ext_input req = {0};
4684 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4685 struct bnxt_pf_info *pf = &bp->pf;
4688 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4689 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4692 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4694 req.port_id = rte_cpu_to_le_16(pf->port_id);
4695 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4696 req.tx_stat_host_addr =
4697 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4699 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4701 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4702 req.rx_stat_host_addr =
4703 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4705 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4707 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4710 bp->fw_rx_port_stats_ext_size = 0;
4711 bp->fw_tx_port_stats_ext_size = 0;
4713 bp->fw_rx_port_stats_ext_size =
4714 rte_le_to_cpu_16(resp->rx_stat_size);
4715 bp->fw_tx_port_stats_ext_size =
4716 rte_le_to_cpu_16(resp->tx_stat_size);
4719 HWRM_CHECK_RESULT();
4726 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4728 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4729 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4730 bp->hwrm_cmd_resp_addr;
4733 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4734 req.tunnel_type = type;
4735 req.dest_fid = bp->fw_fid;
4736 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4737 HWRM_CHECK_RESULT();
4745 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4747 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4748 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4749 bp->hwrm_cmd_resp_addr;
4752 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4753 req.tunnel_type = type;
4754 req.dest_fid = bp->fw_fid;
4755 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4756 HWRM_CHECK_RESULT();
4763 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4765 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4766 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4767 bp->hwrm_cmd_resp_addr;
4770 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4771 req.src_fid = bp->fw_fid;
4772 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4773 HWRM_CHECK_RESULT();
4776 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4783 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4786 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4787 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4788 bp->hwrm_cmd_resp_addr;
4791 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4792 req.src_fid = bp->fw_fid;
4793 req.tunnel_type = tun_type;
4794 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4795 HWRM_CHECK_RESULT();
4798 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4800 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4807 int bnxt_hwrm_set_mac(struct bnxt *bp)
4809 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4810 struct hwrm_func_vf_cfg_input req = {0};
4816 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4819 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4820 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4822 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4824 HWRM_CHECK_RESULT();
4826 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4832 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4834 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4835 struct hwrm_func_drv_if_change_input req = {0};
4839 if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4842 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4843 * If we issue FUNC_DRV_IF_CHANGE with flags down before
4844 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4846 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4849 HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4853 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4855 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4857 HWRM_CHECK_RESULT();
4858 flags = rte_le_to_cpu_32(resp->flags);
4864 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4865 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4866 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4872 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4874 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4875 struct bnxt_error_recovery_info *info = bp->recovery_info;
4876 struct hwrm_error_recovery_qcfg_input req = {0};
4881 /* Older FW does not have error recovery support */
4882 if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4886 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4888 bp->recovery_info = info;
4892 memset(info, 0, sizeof(*info));
4895 HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4897 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4899 HWRM_CHECK_RESULT();
4901 flags = rte_le_to_cpu_32(resp->flags);
4902 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4903 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4904 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4905 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4907 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4908 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4913 /* FW returned values are in units of 100msec */
4914 info->driver_polling_freq =
4915 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4916 info->master_func_wait_period =
4917 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4918 info->normal_func_wait_period =
4919 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4920 info->master_func_wait_period_after_reset =
4921 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4922 info->max_bailout_time_after_reset =
4923 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4924 info->status_regs[BNXT_FW_STATUS_REG] =
4925 rte_le_to_cpu_32(resp->fw_health_status_reg);
4926 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4927 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4928 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4929 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4930 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4931 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4932 info->reg_array_cnt =
4933 rte_le_to_cpu_32(resp->reg_array_cnt);
4935 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4940 for (i = 0; i < info->reg_array_cnt; i++) {
4941 info->reset_reg[i] =
4942 rte_le_to_cpu_32(resp->reset_reg[i]);
4943 info->reset_reg_val[i] =
4944 rte_le_to_cpu_32(resp->reset_reg_val[i]);
4945 info->delay_after_reset[i] =
4946 resp->delay_after_reset[i];
4951 /* Map the FW status registers */
4953 rc = bnxt_map_fw_health_status_regs(bp);
4956 rte_free(bp->recovery_info);
4957 bp->recovery_info = NULL;
4962 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4964 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4965 struct hwrm_fw_reset_input req = {0};
4971 HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4973 req.embedded_proc_type =
4974 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4975 req.selfrst_status =
4976 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4977 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4979 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4982 HWRM_CHECK_RESULT();
4988 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4990 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4991 struct hwrm_port_ts_query_input req = {0};
4992 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4999 HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5002 case BNXT_PTP_FLAGS_PATH_TX:
5003 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5005 case BNXT_PTP_FLAGS_PATH_RX:
5006 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5008 case BNXT_PTP_FLAGS_CURRENT_TIME:
5009 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5013 req.flags = rte_cpu_to_le_32(flags);
5014 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5016 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5018 HWRM_CHECK_RESULT();
5021 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5023 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5030 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5032 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5033 bp->hwrm_cmd_resp_addr;
5034 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5038 if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5041 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5043 "Not a PF or trusted VF. Command not supported\n");
5047 HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5048 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5050 HWRM_CHECK_RESULT();
5051 flags = rte_le_to_cpu_32(resp->flags);
5054 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5055 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5056 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");