1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(int) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
67 if (rmem->nr_pages > 1) {
69 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
71 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
76 * HWRM Functions (sent to HWRM)
77 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
78 * HWRM command times out, or a negative error code if the HWRM
79 * command was failed by the FW.
82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
83 uint32_t msg_len, bool use_kong_mb)
86 struct input *req = msg;
87 struct output *resp = bp->hwrm_cmd_resp_addr;
91 uint16_t max_req_len = bp->max_req_len;
92 struct hwrm_short_input short_input = { 0 };
93 uint16_t bar_offset = use_kong_mb ?
94 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
95 uint16_t mb_trigger_offset = use_kong_mb ?
96 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
99 /* Do not send HWRM commands to firmware in error state */
100 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
103 timeout = bp->hwrm_cmd_timeout;
105 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
106 msg_len > bp->max_req_len) {
107 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
109 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
110 memcpy(short_cmd_req, req, msg_len);
112 short_input.req_type = rte_cpu_to_le_16(req->req_type);
113 short_input.signature = rte_cpu_to_le_16(
114 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
115 short_input.size = rte_cpu_to_le_16(msg_len);
116 short_input.req_addr =
117 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
119 data = (uint32_t *)&short_input;
120 msg_len = sizeof(short_input);
122 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
125 /* Write request msg to hwrm channel */
126 for (i = 0; i < msg_len; i += 4) {
127 bar = (uint8_t *)bp->bar0 + bar_offset + i;
128 rte_write32(*data, bar);
132 /* Zero the rest of the request space */
133 for (; i < max_req_len; i += 4) {
134 bar = (uint8_t *)bp->bar0 + bar_offset + i;
138 /* Ring channel doorbell */
139 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
142 * Make sure the channel doorbell ring command complete before
143 * reading the response to avoid getting stale or invalid
148 /* Poll for the valid bit */
149 for (i = 0; i < timeout; i++) {
150 /* Sanity check on the resp->resp_len */
152 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
153 /* Last byte of resp contains the valid key */
154 valid = (uint8_t *)resp + resp->resp_len - 1;
155 if (*valid == HWRM_RESP_VALID_KEY)
162 /* Suppress VER_GET timeout messages during reset recovery */
163 if (bp->flags & BNXT_FLAG_FW_RESET &&
164 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
168 "Error(timeout) sending msg 0x%04x, seq_id %d\n",
169 req->req_type, req->seq_id);
176 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
177 * spinlock, and does initial processing.
179 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
180 * releases the spinlock only if it returns. If the regular int return codes
181 * are not used by the function, HWRM_CHECK_RESULT() should not be used
182 * directly, rather it should be copied and modified to suit the function.
184 * HWRM_UNLOCK() must be called after all response processing is completed.
186 #define HWRM_PREP(req, type, kong) do { \
187 rte_spinlock_lock(&bp->hwrm_lock); \
188 if (bp->hwrm_cmd_resp_addr == NULL) { \
189 rte_spinlock_unlock(&bp->hwrm_lock); \
192 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
193 (req)->req_type = rte_cpu_to_le_16(type); \
194 (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
195 (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
196 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
197 (req)->target_id = rte_cpu_to_le_16(0xffff); \
198 (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
201 #define HWRM_CHECK_RESULT_SILENT() do {\
203 rte_spinlock_unlock(&bp->hwrm_lock); \
206 if (resp->error_code) { \
207 rc = rte_le_to_cpu_16(resp->error_code); \
208 rte_spinlock_unlock(&bp->hwrm_lock); \
213 #define HWRM_CHECK_RESULT() do {\
215 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
216 rte_spinlock_unlock(&bp->hwrm_lock); \
217 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
219 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
221 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
223 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
225 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
231 if (resp->error_code) { \
232 rc = rte_le_to_cpu_16(resp->error_code); \
233 if (resp->resp_len >= 16) { \
234 struct hwrm_err_output *tmp_hwrm_err_op = \
237 "error %d:%d:%08x:%04x\n", \
238 rc, tmp_hwrm_err_op->cmd_err, \
240 tmp_hwrm_err_op->opaque_0), \
242 tmp_hwrm_err_op->opaque_1)); \
244 PMD_DRV_LOG(ERR, "error %d\n", rc); \
246 rte_spinlock_unlock(&bp->hwrm_lock); \
247 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
249 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
251 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
253 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
255 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
263 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
265 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
274 bool mailbox = BNXT_USE_CHIMP_MB;
275 struct input *req = msg;
276 struct output *resp = bp->hwrm_cmd_resp_addr;
279 mailbox = BNXT_USE_KONG(bp);
281 HWRM_PREP(req, msg_type, mailbox);
283 rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
288 memcpy(resp_msg, resp, resp_len);
295 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
299 uint32_t *tf_response_code,
303 uint32_t response_len)
306 struct hwrm_cfa_tflib_input req = { .req_type = 0 };
307 struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
308 bool mailbox = BNXT_USE_CHIMP_MB;
310 if (msg_len > sizeof(req.tf_req))
314 mailbox = BNXT_USE_KONG(bp);
316 HWRM_PREP(&req, HWRM_TF, mailbox);
317 /* Build request using the user supplied request payload.
318 * TLV request size is checked at build time against HWRM
319 * request max size, thus no checking required.
321 req.tf_type = tf_type;
322 req.tf_subtype = tf_subtype;
323 memcpy(req.tf_req, msg, msg_len);
325 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
328 /* Copy the resp to user provided response buffer */
329 if (response != NULL)
330 /* Post process response data. We need to copy only
331 * the 'payload' as the HWRM data structure really is
332 * HWRM header + msg header + payload and the TFLIB
333 * only provided a payload place holder.
335 if (response_len != 0) {
341 /* Extract the internal tflib response code */
342 *tf_response_code = resp->tf_resp_code;
348 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
351 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
352 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
354 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
355 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
358 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
366 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
367 struct bnxt_vnic_info *vnic,
369 struct bnxt_vlan_table_entry *vlan_table)
372 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
373 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
376 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
379 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
380 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
382 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
383 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
384 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
385 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
387 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
388 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
390 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
391 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
392 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
393 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
394 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
395 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
398 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
399 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
400 req.vlan_tag_tbl_addr =
401 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
402 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
404 req.mask = rte_cpu_to_le_32(mask);
406 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
414 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
416 struct bnxt_vlan_antispoof_table_entry *vlan_table)
419 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
420 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
421 bp->hwrm_cmd_resp_addr;
424 * Older HWRM versions did not support this command, and the set_rx_mask
425 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
426 * removed from set_rx_mask call, and this command was added.
428 * This command is also present from 1.7.8.11 and higher,
431 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
432 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
433 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
438 HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
439 req.fid = rte_cpu_to_le_16(fid);
441 req.vlan_tag_mask_tbl_addr =
442 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
443 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
445 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
453 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
454 struct bnxt_filter_info *filter)
457 struct bnxt_filter_info *l2_filter = filter;
458 struct bnxt_vnic_info *vnic = NULL;
459 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
460 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
462 if (filter->fw_l2_filter_id == UINT64_MAX)
465 if (filter->matching_l2_fltr_ptr)
466 l2_filter = filter->matching_l2_fltr_ptr;
468 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
469 filter, l2_filter, l2_filter->l2_ref_cnt);
471 if (l2_filter->l2_ref_cnt == 0)
474 if (l2_filter->l2_ref_cnt > 0)
475 l2_filter->l2_ref_cnt--;
477 if (l2_filter->l2_ref_cnt > 0)
480 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
482 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
484 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
489 filter->fw_l2_filter_id = UINT64_MAX;
490 if (l2_filter->l2_ref_cnt == 0) {
491 vnic = l2_filter->vnic;
493 STAILQ_REMOVE(&vnic->filter, l2_filter,
494 bnxt_filter_info, next);
495 bnxt_free_filter(bp, l2_filter);
502 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
504 struct bnxt_filter_info *filter)
507 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
508 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
509 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
510 const struct rte_eth_vmdq_rx_conf *conf =
511 &dev_conf->rx_adv_conf.vmdq_rx_conf;
512 uint32_t enables = 0;
513 uint16_t j = dst_id - 1;
515 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
516 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
517 conf->pool_map[j].pools & (1UL << j)) {
519 "Add vlan %u to vmdq pool %u\n",
520 conf->pool_map[j].vlan_id, j);
522 filter->l2_ivlan = conf->pool_map[j].vlan_id;
524 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
525 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
528 if (filter->fw_l2_filter_id != UINT64_MAX)
529 bnxt_hwrm_clear_l2_filter(bp, filter);
531 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
533 /* PMD does not support XDP and RoCE */
534 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
535 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
536 req.flags = rte_cpu_to_le_32(filter->flags);
538 enables = filter->enables |
539 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
540 req.dst_id = rte_cpu_to_le_16(dst_id);
543 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
544 memcpy(req.l2_addr, filter->l2_addr,
547 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
548 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
551 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
552 req.l2_ovlan = filter->l2_ovlan;
554 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
555 req.l2_ivlan = filter->l2_ivlan;
557 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
558 req.l2_ovlan_mask = filter->l2_ovlan_mask;
560 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
561 req.l2_ivlan_mask = filter->l2_ivlan_mask;
562 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
563 req.src_id = rte_cpu_to_le_32(filter->src_id);
564 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
565 req.src_type = filter->src_type;
566 if (filter->pri_hint) {
567 req.pri_hint = filter->pri_hint;
568 req.l2_filter_id_hint =
569 rte_cpu_to_le_64(filter->l2_filter_id_hint);
572 req.enables = rte_cpu_to_le_32(enables);
574 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
578 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
579 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
582 filter->l2_ref_cnt++;
587 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
589 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
590 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
597 HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
600 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
603 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
604 if (ptp->tx_tstamp_en)
605 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
608 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
609 req.flags = rte_cpu_to_le_32(flags);
610 req.enables = rte_cpu_to_le_32
611 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
612 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
614 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
620 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
623 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
624 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
625 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
630 HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
632 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
634 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
638 if (!BNXT_CHIP_THOR(bp) &&
639 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
642 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
643 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
645 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
649 if (!BNXT_CHIP_THOR(bp)) {
650 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
651 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
652 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
653 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
654 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
655 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
656 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
657 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
658 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
659 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
660 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
661 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
662 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
663 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
664 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
665 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
666 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
667 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
676 void bnxt_hwrm_free_vf_info(struct bnxt *bp)
680 for (i = 0; i < bp->pf->max_vfs; i++) {
681 rte_free(bp->pf->vf_info[i].vlan_table);
682 bp->pf->vf_info[i].vlan_table = NULL;
683 rte_free(bp->pf->vf_info[i].vlan_as_table);
684 bp->pf->vf_info[i].vlan_as_table = NULL;
686 rte_free(bp->pf->vf_info);
687 bp->pf->vf_info = NULL;
690 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
693 struct hwrm_func_qcaps_input req = {.req_type = 0 };
694 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
695 uint16_t new_max_vfs;
699 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
701 req.fid = rte_cpu_to_le_16(0xffff);
703 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
707 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
708 flags = rte_le_to_cpu_32(resp->flags);
710 bp->pf->port_id = resp->port_id;
711 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
712 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
713 new_max_vfs = bp->pdev->max_vfs;
714 if (new_max_vfs != bp->pf->max_vfs) {
716 bnxt_hwrm_free_vf_info(bp);
717 bp->pf->vf_info = rte_zmalloc("bnxt_vf_info",
718 sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
719 if (bp->pf->vf_info == NULL) {
720 PMD_DRV_LOG(ERR, "Alloc vf info fail\n");
723 bp->pf->max_vfs = new_max_vfs;
724 for (i = 0; i < new_max_vfs; i++) {
725 bp->pf->vf_info[i].fid =
726 bp->pf->first_vf_id + i;
727 bp->pf->vf_info[i].vlan_table =
728 rte_zmalloc("VF VLAN table",
731 if (bp->pf->vf_info[i].vlan_table == NULL)
733 "Fail to alloc VLAN table for VF %d\n",
737 bp->pf->vf_info[i].vlan_table);
738 bp->pf->vf_info[i].vlan_as_table =
739 rte_zmalloc("VF VLAN AS table",
742 if (bp->pf->vf_info[i].vlan_as_table == NULL)
744 "Alloc VLAN AS table for VF %d fail\n",
748 bp->pf->vf_info[i].vlan_as_table);
749 STAILQ_INIT(&bp->pf->vf_info[i].filter);
754 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
755 if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
756 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
757 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
759 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
761 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
762 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
763 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
764 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
765 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
766 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
767 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
768 if (!BNXT_CHIP_THOR(bp))
769 bp->max_l2_ctx += bp->max_rx_em_flows;
770 /* TODO: For now, do not support VMDq/RFS on VFs. */
775 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
779 PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
780 bp->max_l2_ctx, bp->max_vnics);
781 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
783 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
784 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
785 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
786 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
788 bnxt_hwrm_ptp_qcfg(bp);
792 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
793 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
795 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
796 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
797 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
800 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
801 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
803 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
804 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
811 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
815 rc = __bnxt_hwrm_func_qcaps(bp);
816 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
817 rc = bnxt_alloc_ctx_mem(bp);
821 rc = bnxt_hwrm_func_resc_qcaps(bp);
823 bp->flags |= BNXT_FLAG_NEW_RM;
827 * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
828 * But the error can be ignored. Return success.
834 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
835 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
839 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
840 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
842 HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
844 req.target_id = rte_cpu_to_le_16(0xffff);
846 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
850 flags = rte_le_to_cpu_32(resp->flags);
852 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
853 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
854 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
857 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
858 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
860 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
867 int bnxt_hwrm_func_reset(struct bnxt *bp)
870 struct hwrm_func_reset_input req = {.req_type = 0 };
871 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
873 HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
875 req.enables = rte_cpu_to_le_32(0);
877 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
885 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
889 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
890 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
892 if (bp->flags & BNXT_FLAG_REGISTERED)
895 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
896 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
897 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
898 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
900 /* PFs and trusted VFs should indicate the support of the
901 * Master capability on non Stingray platform
903 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
904 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
906 HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
907 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
908 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
909 req.ver_maj = RTE_VER_YEAR;
910 req.ver_min = RTE_VER_MONTH;
911 req.ver_upd = RTE_VER_MINOR;
914 req.enables |= rte_cpu_to_le_32(
915 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
916 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
917 RTE_MIN(sizeof(req.vf_req_fwd),
918 sizeof(bp->pf->vf_req_fwd)));
921 * PF can sniff HWRM API issued by VF. This can be set up by
922 * linux driver and inherited by the DPDK PF driver. Clear
923 * this HWRM sniffer list in FW because DPDK PF driver does
926 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
929 req.flags = rte_cpu_to_le_32(flags);
931 req.async_event_fwd[0] |=
932 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
933 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
934 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
935 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
936 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
937 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
938 req.async_event_fwd[0] |=
939 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
940 req.async_event_fwd[1] |=
941 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
942 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
944 req.async_event_fwd[1] |=
945 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
947 if (BNXT_VF_IS_TRUSTED(bp))
948 req.async_event_fwd[1] |=
949 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
951 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
955 flags = rte_le_to_cpu_32(resp->flags);
956 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
957 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
961 bp->flags |= BNXT_FLAG_REGISTERED;
966 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
968 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
971 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
974 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
979 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
980 struct hwrm_func_vf_cfg_input req = {0};
982 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
984 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
985 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
986 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
987 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
988 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
990 if (BNXT_HAS_RING_GRPS(bp)) {
991 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
992 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
995 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
996 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
997 AGG_RING_MULTIPLIER);
998 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
999 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1001 BNXT_NUM_ASYNC_CPR(bp));
1002 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1003 if (bp->vf_resv_strategy ==
1004 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1005 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1006 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1007 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1008 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1009 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1010 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1011 } else if (bp->vf_resv_strategy ==
1012 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1013 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1014 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1018 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1019 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1020 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1021 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1022 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1023 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1025 if (test && BNXT_HAS_RING_GRPS(bp))
1026 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1028 req.flags = rte_cpu_to_le_32(flags);
1029 req.enables |= rte_cpu_to_le_32(enables);
1031 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1034 HWRM_CHECK_RESULT_SILENT();
1036 HWRM_CHECK_RESULT();
1042 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1045 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1046 struct hwrm_func_resource_qcaps_input req = {0};
1048 HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1049 req.fid = rte_cpu_to_le_16(0xffff);
1051 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1053 HWRM_CHECK_RESULT_SILENT();
1056 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1057 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1058 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1059 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1060 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1061 /* func_resource_qcaps does not return max_rx_em_flows.
1062 * So use the value provided by func_qcaps.
1064 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1065 if (!BNXT_CHIP_THOR(bp))
1066 bp->max_l2_ctx += bp->max_rx_em_flows;
1067 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1068 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1070 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1071 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1072 if (bp->vf_resv_strategy >
1073 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1074 bp->vf_resv_strategy =
1075 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1081 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1084 struct hwrm_ver_get_input req = {.req_type = 0 };
1085 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1086 uint32_t fw_version;
1087 uint16_t max_resp_len;
1088 char type[RTE_MEMZONE_NAMESIZE];
1089 uint32_t dev_caps_cfg;
1091 bp->max_req_len = HWRM_MAX_REQ_LEN;
1092 bp->hwrm_cmd_timeout = timeout;
1093 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1095 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1096 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1097 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1099 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1101 if (bp->flags & BNXT_FLAG_FW_RESET)
1102 HWRM_CHECK_RESULT_SILENT();
1104 HWRM_CHECK_RESULT();
1106 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1107 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1108 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1109 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1110 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1111 (resp->hwrm_fw_min_8b << 16) |
1112 (resp->hwrm_fw_bld_8b << 8) |
1113 resp->hwrm_fw_rsvd_8b;
1114 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1115 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1117 fw_version = resp->hwrm_intf_maj_8b << 16;
1118 fw_version |= resp->hwrm_intf_min_8b << 8;
1119 fw_version |= resp->hwrm_intf_upd_8b;
1120 bp->hwrm_spec_code = fw_version;
1122 /* def_req_timeout value is in milliseconds */
1123 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1124 /* convert timeout to usec */
1125 bp->hwrm_cmd_timeout *= 1000;
1126 if (!bp->hwrm_cmd_timeout)
1127 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1129 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1130 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1135 if (bp->max_req_len > resp->max_req_win_len) {
1136 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1139 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1140 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1141 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1142 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1144 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1145 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1147 if (bp->max_resp_len != max_resp_len) {
1148 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1149 bp->pdev->addr.domain, bp->pdev->addr.bus,
1150 bp->pdev->addr.devid, bp->pdev->addr.function);
1152 rte_free(bp->hwrm_cmd_resp_addr);
1154 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1155 if (bp->hwrm_cmd_resp_addr == NULL) {
1159 bp->hwrm_cmd_resp_dma_addr =
1160 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1161 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1163 "Unable to map response buffer to physical memory.\n");
1167 bp->max_resp_len = max_resp_len;
1171 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1173 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1174 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1175 bp->flags |= BNXT_FLAG_SHORT_CMD;
1178 if (((dev_caps_cfg &
1179 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1181 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1182 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1183 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1184 bp->pdev->addr.domain, bp->pdev->addr.bus,
1185 bp->pdev->addr.devid, bp->pdev->addr.function);
1187 rte_free(bp->hwrm_short_cmd_req_addr);
1189 bp->hwrm_short_cmd_req_addr =
1190 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1191 if (bp->hwrm_short_cmd_req_addr == NULL) {
1195 bp->hwrm_short_cmd_req_dma_addr =
1196 rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1197 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1198 rte_free(bp->hwrm_short_cmd_req_addr);
1200 "Unable to map buffer to physical memory.\n");
1206 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1207 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1208 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1211 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1212 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1214 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1215 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1216 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1220 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1221 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1222 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1231 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1234 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1235 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1237 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1240 HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1243 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1245 HWRM_CHECK_RESULT();
1251 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1254 struct hwrm_port_phy_cfg_input req = {0};
1255 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1256 uint32_t enables = 0;
1258 HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1260 if (conf->link_up) {
1261 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1262 if (bp->link_info->auto_mode && conf->link_speed) {
1263 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1264 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1267 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1269 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1270 * any auto mode, even "none".
1272 if (!conf->link_speed) {
1273 /* No speeds specified. Enable AutoNeg - all speeds */
1274 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1276 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1278 if (bp->link_info->link_signal_mode) {
1280 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1281 req.force_pam4_link_speed =
1282 rte_cpu_to_le_16(conf->link_speed);
1284 req.force_link_speed =
1285 rte_cpu_to_le_16(conf->link_speed);
1287 /* AutoNeg - Advertise speeds specified. */
1288 if (conf->auto_link_speed_mask &&
1289 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1291 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1292 req.auto_link_speed_mask =
1293 conf->auto_link_speed_mask;
1294 if (conf->auto_pam4_link_speeds) {
1296 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1297 req.auto_link_pam4_speed_mask =
1298 conf->auto_pam4_link_speeds;
1301 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1304 if (conf->auto_link_speed &&
1305 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1307 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1309 req.auto_duplex = conf->duplex;
1310 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1311 req.auto_pause = conf->auto_pause;
1312 req.force_pause = conf->force_pause;
1313 /* Set force_pause if there is no auto or if there is a force */
1314 if (req.auto_pause && !req.force_pause)
1315 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1317 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1319 req.enables = rte_cpu_to_le_32(enables);
1322 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1323 PMD_DRV_LOG(INFO, "Force Link Down\n");
1326 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1328 HWRM_CHECK_RESULT();
1334 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1335 struct bnxt_link_info *link_info)
1338 struct hwrm_port_phy_qcfg_input req = {0};
1339 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1341 HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1343 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1345 HWRM_CHECK_RESULT();
1347 link_info->phy_link_status = resp->link;
1348 link_info->link_up =
1349 (link_info->phy_link_status ==
1350 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1351 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1352 link_info->duplex = resp->duplex_cfg;
1353 link_info->pause = resp->pause;
1354 link_info->auto_pause = resp->auto_pause;
1355 link_info->force_pause = resp->force_pause;
1356 link_info->auto_mode = resp->auto_mode;
1357 link_info->phy_type = resp->phy_type;
1358 link_info->media_type = resp->media_type;
1360 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1361 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1362 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1363 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1364 link_info->phy_ver[0] = resp->phy_maj;
1365 link_info->phy_ver[1] = resp->phy_min;
1366 link_info->phy_ver[2] = resp->phy_bld;
1367 link_info->link_signal_mode =
1368 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1369 link_info->force_pam4_link_speed =
1370 rte_le_to_cpu_16(resp->force_pam4_link_speed);
1371 link_info->support_pam4_speeds =
1372 rte_le_to_cpu_16(resp->support_pam4_speeds);
1373 link_info->auto_pam4_link_speeds =
1374 rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1377 PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1378 link_info->link_speed, link_info->auto_mode,
1379 link_info->auto_link_speed, link_info->auto_link_speed_mask,
1380 link_info->support_speeds, link_info->force_link_speed);
1384 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1387 struct hwrm_port_phy_qcaps_input req = {0};
1388 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1389 struct bnxt_link_info *link_info = bp->link_info;
1391 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1394 HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1396 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1398 HWRM_CHECK_RESULT();
1400 bp->port_cnt = resp->port_cnt;
1401 if (resp->supported_speeds_auto_mode)
1402 link_info->support_auto_speeds =
1403 rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1404 if (resp->supported_pam4_speeds_auto_mode)
1405 link_info->support_pam4_auto_speeds =
1406 rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1413 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1417 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1418 if (bp->tx_cos_queue[i].profile ==
1419 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1420 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1427 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1431 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1432 if (bp->tx_cos_queue[i].profile !=
1433 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1434 bp->tx_cos_queue[i].id !=
1435 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1436 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1442 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1445 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1446 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1447 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1451 HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1453 req.flags = rte_cpu_to_le_32(dir);
1454 /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1455 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1456 !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1458 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1459 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1461 HWRM_CHECK_RESULT();
1463 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1464 GET_TX_QUEUE_INFO(0);
1465 GET_TX_QUEUE_INFO(1);
1466 GET_TX_QUEUE_INFO(2);
1467 GET_TX_QUEUE_INFO(3);
1468 GET_TX_QUEUE_INFO(4);
1469 GET_TX_QUEUE_INFO(5);
1470 GET_TX_QUEUE_INFO(6);
1471 GET_TX_QUEUE_INFO(7);
1473 GET_RX_QUEUE_INFO(0);
1474 GET_RX_QUEUE_INFO(1);
1475 GET_RX_QUEUE_INFO(2);
1476 GET_RX_QUEUE_INFO(3);
1477 GET_RX_QUEUE_INFO(4);
1478 GET_RX_QUEUE_INFO(5);
1479 GET_RX_QUEUE_INFO(6);
1480 GET_RX_QUEUE_INFO(7);
1485 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1488 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1489 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1493 /* iterate and find the COSq profile to use for Tx */
1494 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1495 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1496 if (bp->tx_cos_queue[i].id != 0xff)
1497 bp->tx_cosq_id[j++] =
1498 bp->tx_cos_queue[i].id;
1501 /* When CoS classification is disabled, for normal NIC
1502 * operations, ideally we should look to use LOSSY.
1503 * If not found, fallback to the first valid profile
1505 if (!bnxt_find_lossy_profile(bp))
1506 bnxt_find_first_valid_profile(bp);
1511 bp->max_tc = resp->max_configurable_queues;
1512 bp->max_lltc = resp->max_configurable_lossless_queues;
1513 if (bp->max_tc > BNXT_MAX_QUEUE)
1514 bp->max_tc = BNXT_MAX_QUEUE;
1515 bp->max_q = bp->max_tc;
1517 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1518 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1526 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1527 struct bnxt_ring *ring,
1528 uint32_t ring_type, uint32_t map_index,
1529 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1530 uint16_t tx_cosq_id)
1533 uint32_t enables = 0;
1534 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1535 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1536 struct rte_mempool *mb_pool;
1537 uint16_t rx_buf_size;
1539 HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1541 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1542 req.fbo = rte_cpu_to_le_32(0);
1543 /* Association of ring index with doorbell index */
1544 req.logical_id = rte_cpu_to_le_16(map_index);
1545 req.length = rte_cpu_to_le_32(ring->ring_size);
1547 switch (ring_type) {
1548 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1549 req.ring_type = ring_type;
1550 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1551 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1552 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1553 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1555 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1557 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1558 req.ring_type = ring_type;
1559 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1560 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1561 if (BNXT_CHIP_THOR(bp)) {
1562 mb_pool = bp->rx_queues[0]->mb_pool;
1563 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1564 RTE_PKTMBUF_HEADROOM;
1565 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1566 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1568 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1570 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1572 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1574 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1575 req.ring_type = ring_type;
1576 if (BNXT_HAS_NQ(bp)) {
1577 /* Association of cp ring with nq */
1578 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1580 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1582 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1584 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1585 req.ring_type = ring_type;
1586 req.page_size = BNXT_PAGE_SHFT;
1587 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1589 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1590 req.ring_type = ring_type;
1591 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1593 mb_pool = bp->rx_queues[0]->mb_pool;
1594 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1595 RTE_PKTMBUF_HEADROOM;
1596 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1597 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1599 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1600 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1601 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1602 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1605 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1610 req.enables = rte_cpu_to_le_32(enables);
1612 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1614 if (rc || resp->error_code) {
1615 if (rc == 0 && resp->error_code)
1616 rc = rte_le_to_cpu_16(resp->error_code);
1617 switch (ring_type) {
1618 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1620 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1623 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1625 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1628 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1630 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1634 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1636 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1639 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1641 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1645 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1651 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1656 int bnxt_hwrm_ring_free(struct bnxt *bp,
1657 struct bnxt_ring *ring, uint32_t ring_type)
1660 struct hwrm_ring_free_input req = {.req_type = 0 };
1661 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1663 HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1665 req.ring_type = ring_type;
1666 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1668 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1670 if (rc || resp->error_code) {
1671 if (rc == 0 && resp->error_code)
1672 rc = rte_le_to_cpu_16(resp->error_code);
1675 switch (ring_type) {
1676 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1677 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1680 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1681 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1684 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1685 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1688 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1690 "hwrm_ring_free nq failed. rc:%d\n", rc);
1692 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1694 "hwrm_ring_free agg failed. rc:%d\n", rc);
1697 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1705 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1708 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1709 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1711 HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1713 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1714 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1715 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1716 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1718 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1720 HWRM_CHECK_RESULT();
1722 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1729 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1732 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1733 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1735 HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1737 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1739 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1741 HWRM_CHECK_RESULT();
1744 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1748 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1751 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1752 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1754 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1757 HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1759 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1761 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1763 HWRM_CHECK_RESULT();
1769 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1770 unsigned int idx __rte_unused)
1773 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1774 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1776 HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1778 req.update_period_ms = rte_cpu_to_le_32(0);
1780 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1782 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1784 HWRM_CHECK_RESULT();
1786 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1793 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1794 unsigned int idx __rte_unused)
1797 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1798 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1800 HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1802 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1804 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1806 HWRM_CHECK_RESULT();
1812 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1815 struct hwrm_vnic_alloc_input req = { 0 };
1816 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1818 if (!BNXT_HAS_RING_GRPS(bp))
1819 goto skip_ring_grps;
1821 /* map ring groups to this vnic */
1822 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1823 vnic->start_grp_id, vnic->end_grp_id);
1824 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1825 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1827 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1828 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1829 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1830 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1833 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1834 HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1836 if (vnic->func_default)
1838 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1839 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1841 HWRM_CHECK_RESULT();
1843 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1845 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1849 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1850 struct bnxt_vnic_info *vnic,
1851 struct bnxt_plcmodes_cfg *pmode)
1854 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1855 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1857 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1859 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1861 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1863 HWRM_CHECK_RESULT();
1865 pmode->flags = rte_le_to_cpu_32(resp->flags);
1866 /* dflt_vnic bit doesn't exist in the _cfg command */
1867 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1868 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1869 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1870 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1877 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1878 struct bnxt_vnic_info *vnic,
1879 struct bnxt_plcmodes_cfg *pmode)
1882 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1883 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1885 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1886 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1890 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1892 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1893 req.flags = rte_cpu_to_le_32(pmode->flags);
1894 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1895 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1896 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1897 req.enables = rte_cpu_to_le_32(
1898 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1899 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1900 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1903 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1905 HWRM_CHECK_RESULT();
1911 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1914 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1915 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1916 struct bnxt_plcmodes_cfg pmodes = { 0 };
1917 uint32_t ctx_enable_flag = 0;
1918 uint32_t enables = 0;
1920 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1921 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1925 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1929 HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1931 if (BNXT_CHIP_THOR(bp)) {
1932 int dflt_rxq = vnic->start_grp_id;
1933 struct bnxt_rx_ring_info *rxr;
1934 struct bnxt_cp_ring_info *cpr;
1935 struct bnxt_rx_queue *rxq;
1939 * The first active receive ring is used as the VNIC
1940 * default receive ring. If there are no active receive
1941 * rings (all corresponding receive queues are stopped),
1942 * the first receive ring is used.
1944 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1945 rxq = bp->eth_dev->data->rx_queues[i];
1946 if (rxq->rx_started) {
1952 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1956 req.default_rx_ring_id =
1957 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1958 req.default_cmpl_ring_id =
1959 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1960 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1961 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1965 /* Only RSS support for now TBD: COS & LB */
1966 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1967 if (vnic->lb_rule != 0xffff)
1968 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1969 if (vnic->cos_rule != 0xffff)
1970 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1971 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1972 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1973 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1975 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1976 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1977 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1980 enables |= ctx_enable_flag;
1981 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1982 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1983 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1984 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1987 req.enables = rte_cpu_to_le_32(enables);
1988 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1989 req.mru = rte_cpu_to_le_16(vnic->mru);
1990 /* Configure default VNIC only once. */
1991 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1993 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1994 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1996 if (vnic->vlan_strip)
1998 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2001 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2002 if (vnic->roce_dual)
2003 req.flags |= rte_cpu_to_le_32(
2004 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
2005 if (vnic->roce_only)
2006 req.flags |= rte_cpu_to_le_32(
2007 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
2008 if (vnic->rss_dflt_cr)
2009 req.flags |= rte_cpu_to_le_32(
2010 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2012 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2014 HWRM_CHECK_RESULT();
2017 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2022 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2026 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2027 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2029 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2030 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2033 HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2036 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2037 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2038 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2040 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2042 HWRM_CHECK_RESULT();
2044 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2045 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2046 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2047 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2048 vnic->mru = rte_le_to_cpu_16(resp->mru);
2049 vnic->func_default = rte_le_to_cpu_32(
2050 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2051 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2052 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2053 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2054 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2055 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
2056 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
2057 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
2058 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
2059 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2060 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2067 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2068 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2072 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2073 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2074 bp->hwrm_cmd_resp_addr;
2076 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2078 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2079 HWRM_CHECK_RESULT();
2081 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2082 if (!BNXT_HAS_RING_GRPS(bp))
2083 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2084 else if (ctx_idx == 0)
2085 vnic->rss_rule = ctx_id;
2093 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2094 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2097 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2098 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2099 bp->hwrm_cmd_resp_addr;
2101 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2102 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2105 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2107 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2109 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2111 HWRM_CHECK_RESULT();
2117 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2121 if (BNXT_CHIP_THOR(bp)) {
2124 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2125 rc = _bnxt_hwrm_vnic_ctx_free(bp,
2127 vnic->fw_grp_ids[j]);
2128 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2130 vnic->num_lb_ctxts = 0;
2132 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2133 vnic->rss_rule = INVALID_HW_RING_ID;
2139 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2142 struct hwrm_vnic_free_input req = {.req_type = 0 };
2143 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2145 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2146 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2150 HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2152 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2154 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2156 HWRM_CHECK_RESULT();
2159 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2160 /* Configure default VNIC again if necessary. */
2161 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2162 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2168 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2172 int nr_ctxs = vnic->num_lb_ctxts;
2173 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2174 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2176 for (i = 0; i < nr_ctxs; i++) {
2177 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2179 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2180 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2181 req.hash_mode_flags = vnic->hash_mode;
2183 req.hash_key_tbl_addr =
2184 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2186 req.ring_grp_tbl_addr =
2187 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2188 i * HW_HASH_INDEX_SIZE);
2189 req.ring_table_pair_index = i;
2190 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2192 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2195 HWRM_CHECK_RESULT();
2202 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2203 struct bnxt_vnic_info *vnic)
2206 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2207 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2209 if (!vnic->rss_table)
2212 if (BNXT_CHIP_THOR(bp))
2213 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2215 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2217 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2218 req.hash_mode_flags = vnic->hash_mode;
2220 req.ring_grp_tbl_addr =
2221 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2222 req.hash_key_tbl_addr =
2223 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2224 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2225 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2227 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2229 HWRM_CHECK_RESULT();
2235 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2236 struct bnxt_vnic_info *vnic)
2239 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2240 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2243 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2244 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2248 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2250 req.flags = rte_cpu_to_le_32(
2251 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2253 req.enables = rte_cpu_to_le_32(
2254 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2256 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2257 size -= RTE_PKTMBUF_HEADROOM;
2258 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2260 req.jumbo_thresh = rte_cpu_to_le_16(size);
2261 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2263 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2265 HWRM_CHECK_RESULT();
2271 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2272 struct bnxt_vnic_info *vnic, bool enable)
2275 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2276 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2278 if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2280 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2284 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2285 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2289 HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2292 req.enables = rte_cpu_to_le_32(
2293 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2294 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2295 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2296 req.flags = rte_cpu_to_le_32(
2297 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2298 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2299 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2300 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2301 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2302 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2303 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2304 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2305 req.min_agg_len = rte_cpu_to_le_32(512);
2307 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2309 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2311 HWRM_CHECK_RESULT();
2317 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2319 struct hwrm_func_cfg_input req = {0};
2320 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2323 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2324 req.enables = rte_cpu_to_le_32(
2325 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2326 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2327 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2329 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2331 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2332 HWRM_CHECK_RESULT();
2335 bp->pf->vf_info[vf].random_mac = false;
2340 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2344 struct hwrm_func_qstats_input req = {.req_type = 0};
2345 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2347 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2349 req.fid = rte_cpu_to_le_16(fid);
2351 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2353 HWRM_CHECK_RESULT();
2356 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2363 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2364 struct rte_eth_stats *stats,
2365 struct hwrm_func_qstats_output *func_qstats)
2368 struct hwrm_func_qstats_input req = {.req_type = 0};
2369 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2371 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2373 req.fid = rte_cpu_to_le_16(fid);
2375 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2377 HWRM_CHECK_RESULT();
2379 memcpy(func_qstats, resp,
2380 sizeof(struct hwrm_func_qstats_output));
2385 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2386 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2387 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2388 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2389 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2390 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2392 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2393 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2394 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2395 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2396 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2397 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2399 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2400 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2401 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2409 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2412 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2413 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2415 HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2417 req.fid = rte_cpu_to_le_16(fid);
2419 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2421 HWRM_CHECK_RESULT();
2427 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2432 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2433 struct bnxt_tx_queue *txq;
2434 struct bnxt_rx_queue *rxq;
2435 struct bnxt_cp_ring_info *cpr;
2437 if (i >= bp->rx_cp_nr_rings) {
2438 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2441 rxq = bp->rx_queues[i];
2445 rc = bnxt_hwrm_stat_clear(bp, cpr);
2453 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2457 struct bnxt_cp_ring_info *cpr;
2459 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2461 if (i >= bp->rx_cp_nr_rings) {
2462 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2464 cpr = bp->rx_queues[i]->cp_ring;
2465 if (BNXT_HAS_RING_GRPS(bp))
2466 bp->grp_info[i].fw_stats_ctx = -1;
2468 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2469 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2470 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2478 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2483 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2484 struct bnxt_tx_queue *txq;
2485 struct bnxt_rx_queue *rxq;
2486 struct bnxt_cp_ring_info *cpr;
2488 if (i >= bp->rx_cp_nr_rings) {
2489 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2492 rxq = bp->rx_queues[i];
2496 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2505 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2510 if (!BNXT_HAS_RING_GRPS(bp))
2513 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2515 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2518 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2526 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2528 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2530 bnxt_hwrm_ring_free(bp, cp_ring,
2531 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2532 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2533 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2534 sizeof(*cpr->cp_desc_ring));
2535 cpr->cp_raw_cons = 0;
2539 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2541 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2543 bnxt_hwrm_ring_free(bp, cp_ring,
2544 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2545 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2546 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2547 sizeof(*cpr->cp_desc_ring));
2548 cpr->cp_raw_cons = 0;
2552 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2554 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2555 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2556 struct bnxt_ring *ring = rxr->rx_ring_struct;
2557 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2559 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2560 bnxt_hwrm_ring_free(bp, ring,
2561 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2562 ring->fw_ring_id = INVALID_HW_RING_ID;
2563 if (BNXT_HAS_RING_GRPS(bp))
2564 bp->grp_info[queue_index].rx_fw_ring_id =
2567 ring = rxr->ag_ring_struct;
2568 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2569 bnxt_hwrm_ring_free(bp, ring,
2570 BNXT_CHIP_THOR(bp) ?
2571 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2572 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2573 if (BNXT_HAS_RING_GRPS(bp))
2574 bp->grp_info[queue_index].ag_fw_ring_id =
2577 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2578 bnxt_free_cp_ring(bp, cpr);
2580 if (BNXT_HAS_RING_GRPS(bp))
2581 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2585 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2589 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2590 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2591 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2592 struct bnxt_ring *ring = txr->tx_ring_struct;
2593 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2595 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2596 bnxt_hwrm_ring_free(bp, ring,
2597 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2598 ring->fw_ring_id = INVALID_HW_RING_ID;
2599 memset(txr->tx_desc_ring, 0,
2600 txr->tx_ring_struct->ring_size *
2601 sizeof(*txr->tx_desc_ring));
2602 memset(txr->tx_buf_ring, 0,
2603 txr->tx_ring_struct->ring_size *
2604 sizeof(*txr->tx_buf_ring));
2608 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2609 bnxt_free_cp_ring(bp, cpr);
2610 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2614 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2615 bnxt_free_hwrm_rx_ring(bp, i);
2620 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2625 if (!BNXT_HAS_RING_GRPS(bp))
2628 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2629 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2637 * HWRM utility functions
2640 void bnxt_free_hwrm_resources(struct bnxt *bp)
2642 /* Release memzone */
2643 rte_free(bp->hwrm_cmd_resp_addr);
2644 rte_free(bp->hwrm_short_cmd_req_addr);
2645 bp->hwrm_cmd_resp_addr = NULL;
2646 bp->hwrm_short_cmd_req_addr = NULL;
2647 bp->hwrm_cmd_resp_dma_addr = 0;
2648 bp->hwrm_short_cmd_req_dma_addr = 0;
2651 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2653 struct rte_pci_device *pdev = bp->pdev;
2654 char type[RTE_MEMZONE_NAMESIZE];
2656 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2657 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2658 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2659 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2660 if (bp->hwrm_cmd_resp_addr == NULL)
2662 bp->hwrm_cmd_resp_dma_addr =
2663 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2664 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2666 "unable to map response address to physical memory\n");
2669 rte_spinlock_init(&bp->hwrm_lock);
2675 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2679 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2680 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2683 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2684 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2689 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2694 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2696 struct bnxt_filter_info *filter;
2699 STAILQ_FOREACH(filter, &vnic->filter, next) {
2700 rc = bnxt_clear_one_vnic_filter(bp, filter);
2701 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2702 bnxt_free_filter(bp, filter);
2708 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2710 struct bnxt_filter_info *filter;
2711 struct rte_flow *flow;
2714 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2715 flow = STAILQ_FIRST(&vnic->flow_list);
2716 filter = flow->filter;
2717 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2718 rc = bnxt_clear_one_vnic_filter(bp, filter);
2720 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2726 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2728 struct bnxt_filter_info *filter;
2731 STAILQ_FOREACH(filter, &vnic->filter, next) {
2732 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2733 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2735 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2736 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2739 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2748 bnxt_free_tunnel_ports(struct bnxt *bp)
2750 if (bp->vxlan_port_cnt)
2751 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2752 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2754 if (bp->geneve_port_cnt)
2755 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2756 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2757 bp->geneve_port = 0;
2760 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2764 if (bp->vnic_info == NULL)
2768 * Cleanup VNICs in reverse order, to make sure the L2 filter
2769 * from vnic0 is last to be cleaned up.
2771 for (i = bp->max_vnics - 1; i >= 0; i--) {
2772 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2774 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2777 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2779 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2781 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2783 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2785 bnxt_hwrm_vnic_free(bp, vnic);
2787 rte_free(vnic->fw_grp_ids);
2789 /* Ring resources */
2790 bnxt_free_all_hwrm_rings(bp);
2791 bnxt_free_all_hwrm_ring_grps(bp);
2792 bnxt_free_all_hwrm_stat_ctxs(bp);
2793 bnxt_free_tunnel_ports(bp);
2796 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2798 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2800 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2801 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2803 switch (conf_link_speed) {
2804 case ETH_LINK_SPEED_10M_HD:
2805 case ETH_LINK_SPEED_100M_HD:
2807 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2809 return hw_link_duplex;
2812 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2817 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2820 uint16_t eth_link_speed = 0;
2822 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2823 return ETH_LINK_SPEED_AUTONEG;
2825 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2826 case ETH_LINK_SPEED_100M:
2827 case ETH_LINK_SPEED_100M_HD:
2830 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2832 case ETH_LINK_SPEED_1G:
2834 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2836 case ETH_LINK_SPEED_2_5G:
2838 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2840 case ETH_LINK_SPEED_10G:
2842 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2844 case ETH_LINK_SPEED_20G:
2846 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2848 case ETH_LINK_SPEED_25G:
2850 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2852 case ETH_LINK_SPEED_40G:
2854 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2856 case ETH_LINK_SPEED_50G:
2857 eth_link_speed = pam4_link ?
2858 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
2859 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2861 case ETH_LINK_SPEED_100G:
2862 eth_link_speed = pam4_link ?
2863 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
2864 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2866 case ETH_LINK_SPEED_200G:
2868 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
2872 "Unsupported link speed %d; default to AUTO\n",
2876 return eth_link_speed;
2879 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2880 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2881 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2882 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2883 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2885 static int bnxt_validate_link_speed(struct bnxt *bp)
2887 uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
2888 uint16_t port_id = bp->eth_dev->data->port_id;
2889 uint32_t link_speed_capa;
2892 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2895 link_speed_capa = bnxt_get_speed_capabilities(bp);
2897 if (link_speed & ETH_LINK_SPEED_FIXED) {
2898 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2900 if (one_speed & (one_speed - 1)) {
2902 "Invalid advertised speeds (%u) for port %u\n",
2903 link_speed, port_id);
2906 if ((one_speed & link_speed_capa) != one_speed) {
2908 "Unsupported advertised speed (%u) for port %u\n",
2909 link_speed, port_id);
2913 if (!(link_speed & link_speed_capa)) {
2915 "Unsupported advertised speeds (%u) for port %u\n",
2916 link_speed, port_id);
2924 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2928 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2929 if (bp->link_info->support_speeds)
2930 return bp->link_info->support_speeds;
2931 link_speed = BNXT_SUPPORTED_SPEEDS;
2934 if (link_speed & ETH_LINK_SPEED_100M)
2935 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2936 if (link_speed & ETH_LINK_SPEED_100M_HD)
2937 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2938 if (link_speed & ETH_LINK_SPEED_1G)
2939 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2940 if (link_speed & ETH_LINK_SPEED_2_5G)
2941 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2942 if (link_speed & ETH_LINK_SPEED_10G)
2943 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2944 if (link_speed & ETH_LINK_SPEED_20G)
2945 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2946 if (link_speed & ETH_LINK_SPEED_25G)
2947 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2948 if (link_speed & ETH_LINK_SPEED_40G)
2949 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2950 if (link_speed & ETH_LINK_SPEED_50G)
2951 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2952 if (link_speed & ETH_LINK_SPEED_100G)
2953 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2954 if (link_speed & ETH_LINK_SPEED_200G)
2955 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
2959 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2961 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2963 switch (hw_link_speed) {
2964 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2965 eth_link_speed = ETH_SPEED_NUM_100M;
2967 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2968 eth_link_speed = ETH_SPEED_NUM_1G;
2970 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2971 eth_link_speed = ETH_SPEED_NUM_2_5G;
2973 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2974 eth_link_speed = ETH_SPEED_NUM_10G;
2976 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2977 eth_link_speed = ETH_SPEED_NUM_20G;
2979 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2980 eth_link_speed = ETH_SPEED_NUM_25G;
2982 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2983 eth_link_speed = ETH_SPEED_NUM_40G;
2985 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2986 eth_link_speed = ETH_SPEED_NUM_50G;
2988 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2989 eth_link_speed = ETH_SPEED_NUM_100G;
2991 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
2992 eth_link_speed = ETH_SPEED_NUM_200G;
2994 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2996 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3000 return eth_link_speed;
3003 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3005 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3007 switch (hw_link_duplex) {
3008 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3009 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3011 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3013 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3014 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3017 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3021 return eth_link_duplex;
3024 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3027 struct bnxt_link_info *link_info = bp->link_info;
3029 rc = bnxt_hwrm_port_phy_qcaps(bp);
3031 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3033 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3035 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3039 if (link_info->link_speed)
3041 bnxt_parse_hw_link_speed(link_info->link_speed);
3043 link->link_speed = ETH_SPEED_NUM_NONE;
3044 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3045 link->link_status = link_info->link_up;
3046 link->link_autoneg = link_info->auto_mode ==
3047 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3048 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3053 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3056 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3057 struct bnxt_link_info link_req;
3058 uint16_t speed, autoneg;
3060 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3063 rc = bnxt_validate_link_speed(bp);
3067 memset(&link_req, 0, sizeof(link_req));
3068 link_req.link_up = link_up;
3072 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3073 if (BNXT_CHIP_THOR(bp) &&
3074 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3075 /* 40G is not supported as part of media auto detect.
3076 * The speed should be forced and autoneg disabled
3077 * to configure 40G speed.
3079 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3083 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3084 bp->link_info->link_signal_mode);
3085 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3086 /* Autoneg can be done only when the FW allows.
3087 * When user configures fixed speed of 40G and later changes to
3088 * any other speed, auto_link_speed/force_link_speed is still set
3089 * to 40G until link comes up at new speed.
3092 !(!BNXT_CHIP_THOR(bp) &&
3093 (bp->link_info->auto_link_speed ||
3094 bp->link_info->force_link_speed))) {
3095 link_req.phy_flags |=
3096 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3097 link_req.auto_link_speed_mask =
3098 bnxt_parse_eth_link_speed_mask(bp,
3099 dev_conf->link_speeds);
3101 if (bp->link_info->phy_type ==
3102 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3103 bp->link_info->phy_type ==
3104 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3105 bp->link_info->media_type ==
3106 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3107 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3111 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3112 /* If user wants a particular speed try that first. */
3114 link_req.link_speed = speed;
3115 else if (bp->link_info->force_pam4_link_speed)
3116 link_req.link_speed =
3117 bp->link_info->force_pam4_link_speed;
3118 else if (bp->link_info->auto_pam4_link_speeds)
3119 link_req.link_speed =
3120 bp->link_info->auto_pam4_link_speeds;
3121 else if (bp->link_info->support_pam4_speeds)
3122 link_req.link_speed =
3123 bp->link_info->support_pam4_speeds;
3124 else if (bp->link_info->force_link_speed)
3125 link_req.link_speed = bp->link_info->force_link_speed;
3127 link_req.link_speed = bp->link_info->auto_link_speed;
3129 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3130 link_req.auto_pause = bp->link_info->auto_pause;
3131 link_req.force_pause = bp->link_info->force_pause;
3134 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3137 "Set link config failed with rc %d\n", rc);
3145 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3147 struct hwrm_func_qcfg_input req = {0};
3148 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3151 bp->func_svif = BNXT_SVIF_INVALID;
3154 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3155 req.fid = rte_cpu_to_le_16(0xffff);
3157 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3159 HWRM_CHECK_RESULT();
3161 /* Hard Coded.. 0xfff VLAN ID mask */
3162 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3164 svif_info = rte_le_to_cpu_16(resp->svif_info);
3165 if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3166 bp->func_svif = svif_info &
3167 HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3169 flags = rte_le_to_cpu_16(resp->flags);
3170 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3171 bp->flags |= BNXT_FLAG_MULTI_HOST;
3174 !BNXT_VF_IS_TRUSTED(bp) &&
3175 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3176 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3177 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3178 } else if (BNXT_VF(bp) &&
3179 BNXT_VF_IS_TRUSTED(bp) &&
3180 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3181 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3182 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3186 *mtu = rte_le_to_cpu_16(resp->mtu);
3188 switch (resp->port_partition_type) {
3189 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3190 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3191 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3193 bp->flags |= BNXT_FLAG_NPAR_PF;
3196 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3205 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3207 struct hwrm_func_qcfg_input req = {0};
3208 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3211 if (!BNXT_VF_IS_TRUSTED(bp))
3217 bp->parent->fid = BNXT_PF_FID_INVALID;
3219 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3221 req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3223 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3225 HWRM_CHECK_RESULT();
3227 memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3228 bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3229 bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3230 bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3232 /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3233 if (bp->parent->vnic == 0) {
3234 PMD_DRV_LOG(ERR, "Error: parent VNIC unavailable.\n");
3235 /* Use hard-coded values appropriate for current Wh+ fw. */
3236 if (bp->parent->fid == 2)
3237 bp->parent->vnic = 0x100;
3239 bp->parent->vnic = 1;
3247 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3248 uint16_t *vnic_id, uint16_t *svif)
3250 struct hwrm_func_qcfg_input req = {0};
3251 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3255 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3256 req.fid = rte_cpu_to_le_16(fid);
3258 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3260 HWRM_CHECK_RESULT();
3263 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3265 svif_info = rte_le_to_cpu_16(resp->svif_info);
3266 if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3267 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3274 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3276 struct hwrm_port_mac_qcfg_input req = {0};
3277 struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3278 uint16_t port_svif_info;
3281 bp->port_svif = BNXT_SVIF_INVALID;
3283 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3286 HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3288 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3290 HWRM_CHECK_RESULT_SILENT();
3292 port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3293 if (port_svif_info &
3294 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3295 bp->port_svif = port_svif_info &
3296 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3303 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
3304 struct hwrm_func_qcaps_output *qcaps)
3306 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
3307 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
3308 sizeof(qcaps->mac_address));
3309 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
3310 qcaps->max_rx_rings = fcfg->num_rx_rings;
3311 qcaps->max_tx_rings = fcfg->num_tx_rings;
3312 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
3313 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
3315 qcaps->first_vf_id = 0;
3316 qcaps->max_vnics = fcfg->num_vnics;
3317 qcaps->max_decap_records = 0;
3318 qcaps->max_encap_records = 0;
3319 qcaps->max_tx_wm_flows = 0;
3320 qcaps->max_tx_em_flows = 0;
3321 qcaps->max_rx_wm_flows = 0;
3322 qcaps->max_rx_em_flows = 0;
3323 qcaps->max_flow_id = 0;
3324 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
3325 qcaps->max_sp_tx_rings = 0;
3326 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3329 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3331 struct hwrm_func_cfg_input req = {0};
3332 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3336 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3337 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3338 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3339 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3340 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3341 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3342 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3343 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3344 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3346 if (BNXT_HAS_RING_GRPS(bp)) {
3347 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3348 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3349 } else if (BNXT_HAS_NQ(bp)) {
3350 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3351 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3354 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3355 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3356 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3357 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3358 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3359 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3360 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3361 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3362 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3363 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3364 req.fid = rte_cpu_to_le_16(0xffff);
3365 req.enables = rte_cpu_to_le_32(enables);
3367 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3369 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3371 HWRM_CHECK_RESULT();
3377 static void populate_vf_func_cfg_req(struct bnxt *bp,
3378 struct hwrm_func_cfg_input *req,
3381 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3382 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3383 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3384 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3385 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3386 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3387 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3388 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3389 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3390 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3392 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3393 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3395 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3396 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3398 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3399 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3401 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3402 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3403 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3404 /* TODO: For now, do not support VMDq/RFS on VFs. */
3405 req->num_vnics = rte_cpu_to_le_16(1);
3406 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3410 static void add_random_mac_if_needed(struct bnxt *bp,
3411 struct hwrm_func_cfg_input *cfg_req,
3414 struct rte_ether_addr mac;
3416 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3419 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3421 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3422 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3423 bp->pf->vf_info[vf].random_mac = true;
3425 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3426 RTE_ETHER_ADDR_LEN);
3430 static int reserve_resources_from_vf(struct bnxt *bp,
3431 struct hwrm_func_cfg_input *cfg_req,
3434 struct hwrm_func_qcaps_input req = {0};
3435 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3438 /* Get the actual allocated values now */
3439 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3440 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3441 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3444 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3445 copy_func_cfg_to_qcaps(cfg_req, resp);
3446 } else if (resp->error_code) {
3447 rc = rte_le_to_cpu_16(resp->error_code);
3448 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3449 copy_func_cfg_to_qcaps(cfg_req, resp);
3452 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3453 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3454 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3455 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3456 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3457 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3459 * TODO: While not supporting VMDq with VFs, max_vnics is always
3460 * forced to 1 in this case
3462 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3463 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3470 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3472 struct hwrm_func_qcfg_input req = {0};
3473 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3476 /* Check for zero MAC address */
3477 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3478 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3479 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3480 HWRM_CHECK_RESULT();
3481 rc = rte_le_to_cpu_16(resp->vlan);
3488 static int update_pf_resource_max(struct bnxt *bp)
3490 struct hwrm_func_qcfg_input req = {0};
3491 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3494 /* And copy the allocated numbers into the pf struct */
3495 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3496 req.fid = rte_cpu_to_le_16(0xffff);
3497 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3498 HWRM_CHECK_RESULT();
3500 /* Only TX ring value reflects actual allocation? TODO */
3501 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3502 bp->pf->evb_mode = resp->evb_mode;
3509 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3514 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3518 rc = bnxt_hwrm_func_qcaps(bp);
3522 bp->pf->func_cfg_flags &=
3523 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3524 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3525 bp->pf->func_cfg_flags |=
3526 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3527 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3528 rc = __bnxt_hwrm_func_qcaps(bp);
3532 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3534 struct hwrm_func_cfg_input req = {0};
3535 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3542 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3546 rc = bnxt_hwrm_func_qcaps(bp);
3551 bp->pf->active_vfs = num_vfs;
3554 * First, configure the PF to only use one TX ring. This ensures that
3555 * there are enough rings for all VFs.
3557 * If we don't do this, when we call func_alloc() later, we will lock
3558 * extra rings to the PF that won't be available during func_cfg() of
3561 * This has been fixed with firmware versions above 20.6.54
3563 bp->pf->func_cfg_flags &=
3564 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3565 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3566 bp->pf->func_cfg_flags |=
3567 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3568 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3573 * Now, create and register a buffer to hold forwarded VF requests
3575 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3576 bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3577 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3578 if (bp->pf->vf_req_buf == NULL) {
3582 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3583 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3584 for (i = 0; i < num_vfs; i++)
3585 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3586 (i * HWRM_MAX_REQ_LEN);
3588 rc = bnxt_hwrm_func_buf_rgtr(bp);
3592 populate_vf_func_cfg_req(bp, &req, num_vfs);
3594 bp->pf->active_vfs = 0;
3595 for (i = 0; i < num_vfs; i++) {
3596 add_random_mac_if_needed(bp, &req, i);
3598 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3599 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3600 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3601 rc = bnxt_hwrm_send_message(bp,
3606 /* Clear enable flag for next pass */
3607 req.enables &= ~rte_cpu_to_le_32(
3608 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3610 if (rc || resp->error_code) {
3612 "Failed to initizlie VF %d\n", i);
3614 "Not all VFs available. (%d, %d)\n",
3615 rc, resp->error_code);
3622 reserve_resources_from_vf(bp, &req, i);
3623 bp->pf->active_vfs++;
3624 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3628 * Now configure the PF to use "the rest" of the resources
3629 * We're using STD_TX_RING_MODE here though which will limit the TX
3630 * rings. This will allow QoS to function properly. Not setting this
3631 * will cause PF rings to break bandwidth settings.
3633 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3637 rc = update_pf_resource_max(bp);
3644 bnxt_hwrm_func_buf_unrgtr(bp);
3648 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3650 struct hwrm_func_cfg_input req = {0};
3651 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3654 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3656 req.fid = rte_cpu_to_le_16(0xffff);
3657 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3658 req.evb_mode = bp->pf->evb_mode;
3660 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3661 HWRM_CHECK_RESULT();
3667 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3668 uint8_t tunnel_type)
3670 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3671 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3674 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3675 req.tunnel_type = tunnel_type;
3676 req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3677 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3678 HWRM_CHECK_RESULT();
3680 switch (tunnel_type) {
3681 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3682 bp->vxlan_fw_dst_port_id =
3683 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3684 bp->vxlan_port = port;
3686 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3687 bp->geneve_fw_dst_port_id =
3688 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3689 bp->geneve_port = port;
3700 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3701 uint8_t tunnel_type)
3703 struct hwrm_tunnel_dst_port_free_input req = {0};
3704 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3707 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3709 req.tunnel_type = tunnel_type;
3710 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3711 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3713 HWRM_CHECK_RESULT();
3719 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3722 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3723 struct hwrm_func_cfg_input req = {0};
3726 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3728 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3729 req.flags = rte_cpu_to_le_32(flags);
3730 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3732 HWRM_CHECK_RESULT();
3738 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3740 uint32_t *flag = flagp;
3742 vnic->flags = *flag;
3745 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3747 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3750 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3753 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3754 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3756 HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3758 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3759 req.req_buf_page_size = rte_cpu_to_le_16(
3760 page_getenum(bp->pf->active_vfs * HWRM_MAX_REQ_LEN));
3761 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3762 req.req_buf_page_addr0 =
3763 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3764 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3766 "unable to map buffer address to physical memory\n");
3770 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3772 HWRM_CHECK_RESULT();
3778 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3781 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3782 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3784 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3787 HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3789 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3791 HWRM_CHECK_RESULT();
3797 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3799 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3800 struct hwrm_func_cfg_input req = {0};
3803 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3805 req.fid = rte_cpu_to_le_16(0xffff);
3806 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3807 req.enables = rte_cpu_to_le_32(
3808 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3809 req.async_event_cr = rte_cpu_to_le_16(
3810 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3811 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3813 HWRM_CHECK_RESULT();
3819 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3821 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3822 struct hwrm_func_vf_cfg_input req = {0};
3825 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3827 req.enables = rte_cpu_to_le_32(
3828 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3829 req.async_event_cr = rte_cpu_to_le_16(
3830 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3831 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3833 HWRM_CHECK_RESULT();
3839 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3841 struct hwrm_func_cfg_input req = {0};
3842 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3843 uint16_t dflt_vlan, fid;
3844 uint32_t func_cfg_flags;
3847 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3850 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
3851 fid = bp->pf->vf_info[vf].fid;
3852 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
3854 fid = rte_cpu_to_le_16(0xffff);
3855 func_cfg_flags = bp->pf->func_cfg_flags;
3856 dflt_vlan = bp->vlan;
3859 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3860 req.fid = rte_cpu_to_le_16(fid);
3861 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3862 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3864 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3866 HWRM_CHECK_RESULT();
3872 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3873 uint16_t max_bw, uint16_t enables)
3875 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3876 struct hwrm_func_cfg_input req = {0};
3879 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3881 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3882 req.enables |= rte_cpu_to_le_32(enables);
3883 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3884 req.max_bw = rte_cpu_to_le_32(max_bw);
3885 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3887 HWRM_CHECK_RESULT();
3893 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3895 struct hwrm_func_cfg_input req = {0};
3896 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3899 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3901 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3902 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3903 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3904 req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
3906 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3908 HWRM_CHECK_RESULT();
3914 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3919 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3921 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3926 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3927 void *encaped, size_t ec_size)
3930 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3931 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3933 if (ec_size > sizeof(req.encap_request))
3936 HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3938 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3939 memcpy(req.encap_request, encaped, ec_size);
3941 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3943 HWRM_CHECK_RESULT();
3949 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3950 struct rte_ether_addr *mac)
3952 struct hwrm_func_qcfg_input req = {0};
3953 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3956 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3958 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3959 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3961 HWRM_CHECK_RESULT();
3963 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3970 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3971 void *encaped, size_t ec_size)
3974 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3975 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3977 if (ec_size > sizeof(req.encap_request))
3980 HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3982 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3983 memcpy(req.encap_request, encaped, ec_size);
3985 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3987 HWRM_CHECK_RESULT();
3993 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3994 struct rte_eth_stats *stats, uint8_t rx)
3997 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3998 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4000 HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4002 req.stat_ctx_id = rte_cpu_to_le_32(cid);
4004 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4006 HWRM_CHECK_RESULT();
4009 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4010 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
4011 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
4012 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4013 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
4014 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
4015 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_discard_pkts);
4016 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_error_pkts);
4018 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4019 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
4020 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
4021 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4022 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
4023 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
4031 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4033 struct hwrm_port_qstats_input req = {0};
4034 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4035 struct bnxt_pf_info *pf = bp->pf;
4038 HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4040 req.port_id = rte_cpu_to_le_16(pf->port_id);
4041 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4042 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4043 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4045 HWRM_CHECK_RESULT();
4051 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4053 struct hwrm_port_clr_stats_input req = {0};
4054 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4055 struct bnxt_pf_info *pf = bp->pf;
4058 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4059 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4060 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4063 HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4065 req.port_id = rte_cpu_to_le_16(pf->port_id);
4066 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4068 HWRM_CHECK_RESULT();
4074 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4076 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4077 struct hwrm_port_led_qcaps_input req = {0};
4083 HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4084 req.port_id = bp->pf->port_id;
4085 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4087 HWRM_CHECK_RESULT();
4089 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4092 bp->leds->num_leds = resp->num_leds;
4093 memcpy(bp->leds, &resp->led0_id,
4094 sizeof(bp->leds[0]) * bp->leds->num_leds);
4095 for (i = 0; i < bp->leds->num_leds; i++) {
4096 struct bnxt_led_info *led = &bp->leds[i];
4098 uint16_t caps = led->led_state_caps;
4100 if (!led->led_group_id ||
4101 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4102 bp->leds->num_leds = 0;
4113 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4115 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4116 struct hwrm_port_led_cfg_input req = {0};
4117 struct bnxt_led_cfg *led_cfg;
4118 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4119 uint16_t duration = 0;
4122 if (!bp->leds->num_leds || BNXT_VF(bp))
4125 HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4128 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4129 duration = rte_cpu_to_le_16(500);
4131 req.port_id = bp->pf->port_id;
4132 req.num_leds = bp->leds->num_leds;
4133 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4134 for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4135 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4136 led_cfg->led_id = bp->leds[i].led_id;
4137 led_cfg->led_state = led_state;
4138 led_cfg->led_blink_on = duration;
4139 led_cfg->led_blink_off = duration;
4140 led_cfg->led_group_id = bp->leds[i].led_group_id;
4143 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4145 HWRM_CHECK_RESULT();
4151 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4155 struct hwrm_nvm_get_dir_info_input req = {0};
4156 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4158 HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4160 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4162 HWRM_CHECK_RESULT();
4164 *entries = rte_le_to_cpu_32(resp->entries);
4165 *length = rte_le_to_cpu_32(resp->entry_length);
4171 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4174 uint32_t dir_entries;
4175 uint32_t entry_length;
4178 rte_iova_t dma_handle;
4179 struct hwrm_nvm_get_dir_entries_input req = {0};
4180 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4182 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4186 *data++ = dir_entries;
4187 *data++ = entry_length;
4189 memset(data, 0xff, len);
4191 buflen = dir_entries * entry_length;
4192 buf = rte_malloc("nvm_dir", buflen, 0);
4195 dma_handle = rte_malloc_virt2iova(buf);
4196 if (dma_handle == RTE_BAD_IOVA) {
4198 "unable to map response address to physical memory\n");
4201 HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4202 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4203 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4206 memcpy(data, buf, len > buflen ? buflen : len);
4209 HWRM_CHECK_RESULT();
4215 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4216 uint32_t offset, uint32_t length,
4221 rte_iova_t dma_handle;
4222 struct hwrm_nvm_read_input req = {0};
4223 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4225 buf = rte_malloc("nvm_item", length, 0);
4229 dma_handle = rte_malloc_virt2iova(buf);
4230 if (dma_handle == RTE_BAD_IOVA) {
4232 "unable to map response address to physical memory\n");
4235 HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4236 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4237 req.dir_idx = rte_cpu_to_le_16(index);
4238 req.offset = rte_cpu_to_le_32(offset);
4239 req.len = rte_cpu_to_le_32(length);
4240 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4242 memcpy(data, buf, length);
4245 HWRM_CHECK_RESULT();
4251 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4254 struct hwrm_nvm_erase_dir_entry_input req = {0};
4255 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4257 HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4258 req.dir_idx = rte_cpu_to_le_16(index);
4259 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4260 HWRM_CHECK_RESULT();
4267 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4268 uint16_t dir_ordinal, uint16_t dir_ext,
4269 uint16_t dir_attr, const uint8_t *data,
4273 struct hwrm_nvm_write_input req = {0};
4274 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4275 rte_iova_t dma_handle;
4278 buf = rte_malloc("nvm_write", data_len, 0);
4282 dma_handle = rte_malloc_virt2iova(buf);
4283 if (dma_handle == RTE_BAD_IOVA) {
4285 "unable to map response address to physical memory\n");
4288 memcpy(buf, data, data_len);
4290 HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4292 req.dir_type = rte_cpu_to_le_16(dir_type);
4293 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4294 req.dir_ext = rte_cpu_to_le_16(dir_ext);
4295 req.dir_attr = rte_cpu_to_le_16(dir_attr);
4296 req.dir_data_length = rte_cpu_to_le_32(data_len);
4297 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4299 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4302 HWRM_CHECK_RESULT();
4309 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4311 uint32_t *count = cbdata;
4313 *count = *count + 1;
4316 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4317 struct bnxt_vnic_info *vnic __rte_unused)
4322 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4326 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4327 &count, bnxt_vnic_count_hwrm_stub);
4332 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4335 struct hwrm_func_vf_vnic_ids_query_input req = {0};
4336 struct hwrm_func_vf_vnic_ids_query_output *resp =
4337 bp->hwrm_cmd_resp_addr;
4340 /* First query all VNIC ids */
4341 HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4343 req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4344 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4345 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4347 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4350 "unable to map VNIC ID table address to physical memory\n");
4353 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4354 HWRM_CHECK_RESULT();
4355 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4363 * This function queries the VNIC IDs for a specified VF. It then calls
4364 * the vnic_cb to update the necessary field in vnic_info with cbdata.
4365 * Then it calls the hwrm_cb function to program this new vnic configuration.
4367 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4368 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4369 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4371 struct bnxt_vnic_info vnic;
4373 int i, num_vnic_ids;
4378 /* First query all VNIC ids */
4379 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4380 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4381 RTE_CACHE_LINE_SIZE);
4382 if (vnic_ids == NULL)
4385 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4386 rte_mem_lock_page(((char *)vnic_ids) + sz);
4388 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4390 if (num_vnic_ids < 0)
4391 return num_vnic_ids;
4393 /* Retrieve VNIC, update bd_stall then update */
4395 for (i = 0; i < num_vnic_ids; i++) {
4396 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4397 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4398 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4401 if (vnic.mru <= 4) /* Indicates unallocated */
4404 vnic_cb(&vnic, cbdata);
4406 rc = hwrm_cb(bp, &vnic);
4416 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4419 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4420 struct hwrm_func_cfg_input req = {0};
4423 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4425 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4426 req.enables |= rte_cpu_to_le_32(
4427 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4428 req.vlan_antispoof_mode = on ?
4429 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4430 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4431 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4433 HWRM_CHECK_RESULT();
4439 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4441 struct bnxt_vnic_info vnic;
4444 int num_vnic_ids, i;
4448 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4449 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4450 RTE_CACHE_LINE_SIZE);
4451 if (vnic_ids == NULL)
4454 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4455 rte_mem_lock_page(((char *)vnic_ids) + sz);
4457 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4463 * Loop through to find the default VNIC ID.
4464 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4465 * by sending the hwrm_func_qcfg command to the firmware.
4467 for (i = 0; i < num_vnic_ids; i++) {
4468 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4469 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4470 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4471 bp->pf->first_vf_id + vf);
4474 if (vnic.func_default) {
4476 return vnic.fw_vnic_id;
4479 /* Could not find a default VNIC. */
4480 PMD_DRV_LOG(ERR, "No default VNIC\n");
4486 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4488 struct bnxt_filter_info *filter)
4491 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4492 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4493 uint32_t enables = 0;
4495 if (filter->fw_em_filter_id != UINT64_MAX)
4496 bnxt_hwrm_clear_em_filter(bp, filter);
4498 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4500 req.flags = rte_cpu_to_le_32(filter->flags);
4502 enables = filter->enables |
4503 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4504 req.dst_id = rte_cpu_to_le_16(dst_id);
4506 if (filter->ip_addr_type) {
4507 req.ip_addr_type = filter->ip_addr_type;
4508 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4511 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4512 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4514 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4515 memcpy(req.src_macaddr, filter->src_macaddr,
4516 RTE_ETHER_ADDR_LEN);
4518 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4519 memcpy(req.dst_macaddr, filter->dst_macaddr,
4520 RTE_ETHER_ADDR_LEN);
4522 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4523 req.ovlan_vid = filter->l2_ovlan;
4525 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4526 req.ivlan_vid = filter->l2_ivlan;
4528 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4529 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4531 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4532 req.ip_protocol = filter->ip_protocol;
4534 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4535 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4537 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4538 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4540 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4541 req.src_port = rte_cpu_to_be_16(filter->src_port);
4543 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4544 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4546 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4547 req.mirror_vnic_id = filter->mirror_vnic_id;
4549 req.enables = rte_cpu_to_le_32(enables);
4551 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4553 HWRM_CHECK_RESULT();
4555 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4561 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4564 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4565 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4567 if (filter->fw_em_filter_id == UINT64_MAX)
4570 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4572 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4574 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4576 HWRM_CHECK_RESULT();
4579 filter->fw_em_filter_id = UINT64_MAX;
4580 filter->fw_l2_filter_id = UINT64_MAX;
4585 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4587 struct bnxt_filter_info *filter)
4590 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4591 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4592 bp->hwrm_cmd_resp_addr;
4593 uint32_t enables = 0;
4595 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4596 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4598 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4600 req.flags = rte_cpu_to_le_32(filter->flags);
4602 enables = filter->enables |
4603 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4604 req.dst_id = rte_cpu_to_le_16(dst_id);
4606 if (filter->ip_addr_type) {
4607 req.ip_addr_type = filter->ip_addr_type;
4609 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4612 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4613 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4615 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4616 memcpy(req.src_macaddr, filter->src_macaddr,
4617 RTE_ETHER_ADDR_LEN);
4619 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4620 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4622 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4623 req.ip_protocol = filter->ip_protocol;
4625 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4626 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4628 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4629 req.src_ipaddr_mask[0] =
4630 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4632 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4633 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4635 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4636 req.dst_ipaddr_mask[0] =
4637 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4639 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4640 req.src_port = rte_cpu_to_le_16(filter->src_port);
4642 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4643 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4645 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4646 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4648 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4649 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4651 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4652 req.mirror_vnic_id = filter->mirror_vnic_id;
4654 req.enables = rte_cpu_to_le_32(enables);
4656 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4658 HWRM_CHECK_RESULT();
4660 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4661 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4667 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4668 struct bnxt_filter_info *filter)
4671 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4672 struct hwrm_cfa_ntuple_filter_free_output *resp =
4673 bp->hwrm_cmd_resp_addr;
4675 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4678 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4680 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4682 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4684 HWRM_CHECK_RESULT();
4687 filter->fw_ntuple_filter_id = UINT64_MAX;
4693 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4695 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4696 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4697 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4698 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4699 uint16_t *ring_tbl = vnic->rss_table;
4700 int nr_ctxs = vnic->num_lb_ctxts;
4701 int max_rings = bp->rx_nr_rings;
4705 for (i = 0, k = 0; i < nr_ctxs; i++) {
4706 struct bnxt_rx_ring_info *rxr;
4707 struct bnxt_cp_ring_info *cpr;
4709 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4711 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4712 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4713 req.hash_mode_flags = vnic->hash_mode;
4715 req.ring_grp_tbl_addr =
4716 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4717 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4718 2 * sizeof(*ring_tbl));
4719 req.hash_key_tbl_addr =
4720 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4722 req.ring_table_pair_index = i;
4723 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4725 for (j = 0; j < 64; j++) {
4728 /* Find next active ring. */
4729 for (cnt = 0; cnt < max_rings; cnt++) {
4730 if (rx_queue_state[k] !=
4731 RTE_ETH_QUEUE_STATE_STOPPED)
4733 if (++k == max_rings)
4737 /* Return if no rings are active. */
4738 if (cnt == max_rings) {
4743 /* Add rx/cp ring pair to RSS table. */
4744 rxr = rxqs[k]->rx_ring;
4745 cpr = rxqs[k]->cp_ring;
4747 ring_id = rxr->rx_ring_struct->fw_ring_id;
4748 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4749 ring_id = cpr->cp_ring_struct->fw_ring_id;
4750 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4752 if (++k == max_rings)
4755 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4758 HWRM_CHECK_RESULT();
4765 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4767 unsigned int rss_idx, fw_idx, i;
4769 if (!(vnic->rss_table && vnic->hash_type))
4772 if (BNXT_CHIP_THOR(bp))
4773 return bnxt_vnic_rss_configure_thor(bp, vnic);
4775 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4778 if (vnic->rss_table && vnic->hash_type) {
4780 * Fill the RSS hash & redirection table with
4781 * ring group ids for all VNICs
4783 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4784 rss_idx++, fw_idx++) {
4785 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4786 fw_idx %= bp->rx_cp_nr_rings;
4787 if (vnic->fw_grp_ids[fw_idx] !=
4792 if (i == bp->rx_cp_nr_rings)
4794 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4796 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4802 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4803 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4807 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4809 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4810 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4812 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4813 req->num_cmpl_dma_aggr_during_int =
4814 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4816 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4818 /* min timer set to 1/2 of interrupt timer */
4819 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4821 /* buf timer set to 1/4 of interrupt timer */
4822 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4824 req->cmpl_aggr_dma_tmr_during_int =
4825 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4827 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4828 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4829 req->flags = rte_cpu_to_le_16(flags);
4832 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4833 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4835 struct hwrm_ring_aggint_qcaps_input req = {0};
4836 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4841 HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4842 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4843 HWRM_CHECK_RESULT();
4845 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4846 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4848 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4849 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4850 agg_req->flags = rte_cpu_to_le_16(flags);
4852 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4853 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4854 agg_req->enables = rte_cpu_to_le_32(enables);
4860 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4861 struct bnxt_coal *coal, uint16_t ring_id)
4863 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4864 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4865 bp->hwrm_cmd_resp_addr;
4868 /* Set ring coalesce parameters only for 100G NICs */
4869 if (BNXT_CHIP_THOR(bp)) {
4870 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4872 } else if (bnxt_stratus_device(bp)) {
4873 bnxt_hwrm_set_coal_params(coal, &req);
4879 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4881 req.ring_id = rte_cpu_to_le_16(ring_id);
4882 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4883 HWRM_CHECK_RESULT();
4888 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4889 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4891 struct hwrm_func_backing_store_qcaps_input req = {0};
4892 struct hwrm_func_backing_store_qcaps_output *resp =
4893 bp->hwrm_cmd_resp_addr;
4894 struct bnxt_ctx_pg_info *ctx_pg;
4895 struct bnxt_ctx_mem_info *ctx;
4896 int total_alloc_len;
4897 int rc, i, tqm_rings;
4899 if (!BNXT_CHIP_THOR(bp) ||
4900 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4905 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4906 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4907 HWRM_CHECK_RESULT_SILENT();
4909 total_alloc_len = sizeof(*ctx);
4910 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4911 RTE_CACHE_LINE_SIZE);
4917 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4918 ctx->qp_min_qp1_entries =
4919 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4920 ctx->qp_max_l2_entries =
4921 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4922 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4923 ctx->srq_max_l2_entries =
4924 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4925 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4926 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4927 ctx->cq_max_l2_entries =
4928 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4929 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4930 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4931 ctx->vnic_max_vnic_entries =
4932 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4933 ctx->vnic_max_ring_table_entries =
4934 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4935 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4936 ctx->stat_max_entries =
4937 rte_le_to_cpu_32(resp->stat_max_entries);
4938 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4939 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4940 ctx->tqm_min_entries_per_ring =
4941 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4942 ctx->tqm_max_entries_per_ring =
4943 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4944 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4945 if (!ctx->tqm_entries_multiple)
4946 ctx->tqm_entries_multiple = 1;
4947 ctx->mrav_max_entries =
4948 rte_le_to_cpu_32(resp->mrav_max_entries);
4949 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4950 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4951 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4952 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
4954 if (!ctx->tqm_fp_rings_count)
4955 ctx->tqm_fp_rings_count = bp->max_q;
4957 tqm_rings = ctx->tqm_fp_rings_count + 1;
4959 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4960 sizeof(*ctx_pg) * tqm_rings,
4961 RTE_CACHE_LINE_SIZE);
4966 for (i = 0; i < tqm_rings; i++, ctx_pg++)
4967 ctx->tqm_mem[i] = ctx_pg;
4975 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4977 struct hwrm_func_backing_store_cfg_input req = {0};
4978 struct hwrm_func_backing_store_cfg_output *resp =
4979 bp->hwrm_cmd_resp_addr;
4980 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4981 struct bnxt_ctx_pg_info *ctx_pg;
4982 uint32_t *num_entries;
4991 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4992 req.enables = rte_cpu_to_le_32(enables);
4994 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4995 ctx_pg = &ctx->qp_mem;
4996 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4997 req.qp_num_qp1_entries =
4998 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4999 req.qp_num_l2_entries =
5000 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5001 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5002 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5003 &req.qpc_pg_size_qpc_lvl,
5007 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5008 ctx_pg = &ctx->srq_mem;
5009 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5010 req.srq_num_l2_entries =
5011 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5012 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5013 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5014 &req.srq_pg_size_srq_lvl,
5018 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5019 ctx_pg = &ctx->cq_mem;
5020 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5021 req.cq_num_l2_entries =
5022 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5023 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5024 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5025 &req.cq_pg_size_cq_lvl,
5029 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5030 ctx_pg = &ctx->vnic_mem;
5031 req.vnic_num_vnic_entries =
5032 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5033 req.vnic_num_ring_table_entries =
5034 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5035 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5036 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5037 &req.vnic_pg_size_vnic_lvl,
5038 &req.vnic_page_dir);
5041 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5042 ctx_pg = &ctx->stat_mem;
5043 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5044 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5045 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5046 &req.stat_pg_size_stat_lvl,
5047 &req.stat_page_dir);
5050 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5051 num_entries = &req.tqm_sp_num_entries;
5052 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5053 pg_dir = &req.tqm_sp_page_dir;
5054 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5055 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5056 if (!(enables & ena))
5059 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5061 ctx_pg = ctx->tqm_mem[i];
5062 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5063 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5066 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5067 HWRM_CHECK_RESULT();
5073 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5075 struct hwrm_port_qstats_ext_input req = {0};
5076 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5077 struct bnxt_pf_info *pf = bp->pf;
5080 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5081 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5084 HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5086 req.port_id = rte_cpu_to_le_16(pf->port_id);
5087 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5088 req.tx_stat_host_addr =
5089 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5091 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5093 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5094 req.rx_stat_host_addr =
5095 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5097 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5099 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5102 bp->fw_rx_port_stats_ext_size = 0;
5103 bp->fw_tx_port_stats_ext_size = 0;
5105 bp->fw_rx_port_stats_ext_size =
5106 rte_le_to_cpu_16(resp->rx_stat_size);
5107 bp->fw_tx_port_stats_ext_size =
5108 rte_le_to_cpu_16(resp->tx_stat_size);
5111 HWRM_CHECK_RESULT();
5118 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5120 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5121 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5122 bp->hwrm_cmd_resp_addr;
5125 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5126 req.tunnel_type = type;
5127 req.dest_fid = bp->fw_fid;
5128 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5129 HWRM_CHECK_RESULT();
5137 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5139 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5140 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5141 bp->hwrm_cmd_resp_addr;
5144 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5145 req.tunnel_type = type;
5146 req.dest_fid = bp->fw_fid;
5147 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5148 HWRM_CHECK_RESULT();
5155 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5157 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5158 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5159 bp->hwrm_cmd_resp_addr;
5162 HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5163 req.src_fid = bp->fw_fid;
5164 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5165 HWRM_CHECK_RESULT();
5168 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5175 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5178 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5179 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5180 bp->hwrm_cmd_resp_addr;
5183 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5184 req.src_fid = bp->fw_fid;
5185 req.tunnel_type = tun_type;
5186 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5187 HWRM_CHECK_RESULT();
5190 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5192 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5199 int bnxt_hwrm_set_mac(struct bnxt *bp)
5201 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5202 struct hwrm_func_vf_cfg_input req = {0};
5208 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5211 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5212 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5214 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5216 HWRM_CHECK_RESULT();
5223 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5225 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5226 struct hwrm_func_drv_if_change_input req = {0};
5230 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5233 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5234 * If we issue FUNC_DRV_IF_CHANGE with flags down before
5235 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5237 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5240 HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5244 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5246 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5248 HWRM_CHECK_RESULT();
5249 flags = rte_le_to_cpu_32(resp->flags);
5255 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5256 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5257 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5263 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5265 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5266 struct bnxt_error_recovery_info *info = bp->recovery_info;
5267 struct hwrm_error_recovery_qcfg_input req = {0};
5272 /* Older FW does not have error recovery support */
5273 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5276 HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5278 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5280 HWRM_CHECK_RESULT();
5282 flags = rte_le_to_cpu_32(resp->flags);
5283 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5284 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5285 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5286 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5288 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5289 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5294 /* FW returned values are in units of 100msec */
5295 info->driver_polling_freq =
5296 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5297 info->master_func_wait_period =
5298 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5299 info->normal_func_wait_period =
5300 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5301 info->master_func_wait_period_after_reset =
5302 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5303 info->max_bailout_time_after_reset =
5304 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5305 info->status_regs[BNXT_FW_STATUS_REG] =
5306 rte_le_to_cpu_32(resp->fw_health_status_reg);
5307 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5308 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5309 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5310 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5311 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5312 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5313 info->reg_array_cnt =
5314 rte_le_to_cpu_32(resp->reg_array_cnt);
5316 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5321 for (i = 0; i < info->reg_array_cnt; i++) {
5322 info->reset_reg[i] =
5323 rte_le_to_cpu_32(resp->reset_reg[i]);
5324 info->reset_reg_val[i] =
5325 rte_le_to_cpu_32(resp->reset_reg_val[i]);
5326 info->delay_after_reset[i] =
5327 resp->delay_after_reset[i];
5332 /* Map the FW status registers */
5334 rc = bnxt_map_fw_health_status_regs(bp);
5337 rte_free(bp->recovery_info);
5338 bp->recovery_info = NULL;
5343 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5345 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5346 struct hwrm_fw_reset_input req = {0};
5352 HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5354 req.embedded_proc_type =
5355 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5356 req.selfrst_status =
5357 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5358 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5360 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5363 HWRM_CHECK_RESULT();
5369 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5371 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5372 struct hwrm_port_ts_query_input req = {0};
5373 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5380 HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5383 case BNXT_PTP_FLAGS_PATH_TX:
5384 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5386 case BNXT_PTP_FLAGS_PATH_RX:
5387 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5389 case BNXT_PTP_FLAGS_CURRENT_TIME:
5390 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5394 req.flags = rte_cpu_to_le_32(flags);
5395 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5397 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5399 HWRM_CHECK_RESULT();
5402 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5404 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5411 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5415 struct hwrm_cfa_counter_qcaps_input req = {0};
5416 struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5418 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5420 "Not a PF or trusted VF. Command not supported\n");
5424 HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5425 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5426 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5428 HWRM_CHECK_RESULT();
5430 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5436 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5439 struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5440 struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5442 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5444 "Not a PF or trusted VF. Command not supported\n");
5448 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5450 req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5451 req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5452 req.page_dir = rte_cpu_to_le_64(dma_addr);
5454 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5456 HWRM_CHECK_RESULT();
5458 *ctx_id = rte_le_to_cpu_16(resp->ctx_id);
5459 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5466 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5469 struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5470 struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5472 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5474 "Not a PF or trusted VF. Command not supported\n");
5478 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5480 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5482 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5484 HWRM_CHECK_RESULT();
5490 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5491 uint16_t cntr, uint16_t ctx_id,
5492 uint32_t num_entries, bool enable)
5494 struct hwrm_cfa_counter_cfg_input req = {0};
5495 struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5499 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5501 "Not a PF or trusted VF. Command not supported\n");
5505 HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5507 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5508 req.counter_type = rte_cpu_to_le_16(cntr);
5509 flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5510 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5511 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5512 if (dir == BNXT_DIR_RX)
5513 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5514 else if (dir == BNXT_DIR_TX)
5515 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5516 req.flags = rte_cpu_to_le_16(flags);
5517 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5518 req.num_entries = rte_cpu_to_le_32(num_entries);
5520 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5521 HWRM_CHECK_RESULT();
5527 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5528 enum bnxt_flow_dir dir,
5530 uint16_t num_entries)
5532 struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5533 struct hwrm_cfa_counter_qstats_input req = {0};
5534 uint16_t flow_ctx_id = 0;
5538 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5540 "Not a PF or trusted VF. Command not supported\n");
5544 if (dir == BNXT_DIR_RX) {
5545 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5546 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5547 } else if (dir == BNXT_DIR_TX) {
5548 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5549 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5552 HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5553 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5554 req.counter_type = rte_cpu_to_le_16(cntr);
5555 req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5556 req.num_entries = rte_cpu_to_le_16(num_entries);
5557 req.flags = rte_cpu_to_le_16(flags);
5558 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5560 HWRM_CHECK_RESULT();
5566 int bnxt_hwrm_cfa_vfr_alloc(struct bnxt *bp, uint16_t vf_idx)
5568 struct hwrm_cfa_vfr_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5569 struct hwrm_cfa_vfr_alloc_input req = {0};
5572 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5574 "Not a PF or trusted VF. Command not supported\n");
5578 HWRM_PREP(&req, HWRM_CFA_VFR_ALLOC, BNXT_USE_CHIMP_MB);
5579 req.vf_id = rte_cpu_to_le_16(vf_idx);
5580 snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
5581 bp->eth_dev->data->name, vf_idx);
5583 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5584 HWRM_CHECK_RESULT();
5587 PMD_DRV_LOG(DEBUG, "VFR %d allocated\n", vf_idx);
5591 int bnxt_hwrm_cfa_vfr_free(struct bnxt *bp, uint16_t vf_idx)
5593 struct hwrm_cfa_vfr_free_output *resp = bp->hwrm_cmd_resp_addr;
5594 struct hwrm_cfa_vfr_free_input req = {0};
5597 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5599 "Not a PF or trusted VF. Command not supported\n");
5603 HWRM_PREP(&req, HWRM_CFA_VFR_FREE, BNXT_USE_CHIMP_MB);
5604 req.vf_id = rte_cpu_to_le_16(vf_idx);
5605 snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
5606 bp->eth_dev->data->name, vf_idx);
5608 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5609 HWRM_CHECK_RESULT();
5611 PMD_DRV_LOG(DEBUG, "VFR %d freed\n", vf_idx);
5615 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5616 uint16_t *first_vf_id)
5619 struct hwrm_func_qcaps_input req = {.req_type = 0 };
5620 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5622 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5624 req.fid = rte_cpu_to_le_16(fid);
5626 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5628 HWRM_CHECK_RESULT();
5631 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
5638 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
5640 struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5641 struct hwrm_cfa_pair_alloc_input req = {0};
5644 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5646 "Not a PF or trusted VF. Command not supported\n");
5650 HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
5651 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5652 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5653 bp->eth_dev->data->name, rep_bp->vf_id);
5655 req.pf_b_id = rte_cpu_to_le_32(rep_bp->rep_based_pf);
5656 req.vf_b_id = rte_cpu_to_le_16(rep_bp->vf_id);
5657 req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
5658 req.host_b_id = 1; /* TBD - Confirm if this is OK */
5660 req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
5661 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
5662 req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
5663 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
5664 req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
5665 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
5666 req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
5667 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
5669 req.q_ab = rep_bp->rep_q_r2f;
5670 req.q_ba = rep_bp->rep_q_f2r;
5671 req.fc_ab = rep_bp->rep_fc_r2f;
5672 req.fc_ba = rep_bp->rep_fc_f2r;
5674 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5675 HWRM_CHECK_RESULT();
5678 PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
5679 BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
5683 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
5685 struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
5686 struct hwrm_cfa_pair_free_input req = {0};
5689 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5691 "Not a PF or trusted VF. Command not supported\n");
5695 HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
5696 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5697 bp->eth_dev->data->name, rep_bp->vf_id);
5698 req.pf_b_id = rte_cpu_to_le_32(rep_bp->rep_based_pf);
5699 req.vf_id = rte_cpu_to_le_16(rep_bp->vf_id);
5700 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5702 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5703 HWRM_CHECK_RESULT();
5705 PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",