4 * Copyright(c) Broadcom Limited.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
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22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_byteorder.h>
35 #include <rte_common.h>
36 #include <rte_cycles.h>
37 #include <rte_malloc.h>
38 #include <rte_memzone.h>
39 #include <rte_version.h>
43 #include "bnxt_filter.h"
44 #include "bnxt_hwrm.h"
47 #include "bnxt_ring.h"
50 #include "bnxt_vnic.h"
51 #include "hsi_struct_def_dpdk.h"
53 #define HWRM_CMD_TIMEOUT 2000
56 * HWRM Functions (sent to HWRM)
57 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
58 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
59 * command was failed by the ChiMP.
62 static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
66 struct input *req = msg;
67 struct output *resp = bp->hwrm_cmd_resp_addr;
72 /* Write request msg to hwrm channel */
73 for (i = 0; i < msg_len; i += 4) {
74 bar = (uint8_t *)bp->bar0 + i;
75 *(volatile uint32_t *)bar = *data;
79 /* Zero the rest of the request space */
80 for (; i < bp->max_req_len; i += 4) {
81 bar = (uint8_t *)bp->bar0 + i;
82 *(volatile uint32_t *)bar = 0;
85 /* Ring channel doorbell */
86 bar = (uint8_t *)bp->bar0 + 0x100;
87 *(volatile uint32_t *)bar = 1;
89 /* Poll for the valid bit */
90 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
91 /* Sanity check on the resp->resp_len */
93 if (resp->resp_len && resp->resp_len <=
95 /* Last byte of resp contains the valid key */
96 valid = (uint8_t *)resp + resp->resp_len - 1;
97 if (*valid == HWRM_RESP_VALID_KEY)
103 if (i >= HWRM_CMD_TIMEOUT) {
104 RTE_LOG(ERR, PMD, "Error sending msg %x\n",
114 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)
118 rte_spinlock_lock(&bp->hwrm_lock);
119 rc = bnxt_hwrm_send_message_locked(bp, msg, msg_len);
120 rte_spinlock_unlock(&bp->hwrm_lock);
124 #define HWRM_PREP(req, type, cr, resp) \
125 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
126 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
127 req.cmpl_ring = rte_cpu_to_le_16(cr); \
128 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
129 req.target_id = rte_cpu_to_le_16(0xffff); \
130 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr)
132 #define HWRM_CHECK_RESULT \
135 RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
139 if (resp->error_code) { \
140 rc = rte_le_to_cpu_16(resp->error_code); \
141 RTE_LOG(ERR, PMD, "%s error %d\n", __func__, rc); \
146 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
149 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
150 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
152 HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
153 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
156 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
163 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
166 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
167 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
170 HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
171 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
173 /* FIXME add multicast flag, when multicast adding options is supported
176 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
177 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
178 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
179 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
180 req.mask = rte_cpu_to_le_32(HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST |
181 HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST |
184 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
191 int bnxt_hwrm_clear_filter(struct bnxt *bp,
192 struct bnxt_filter_info *filter)
195 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
196 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
198 HWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);
200 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
202 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
206 filter->fw_l2_filter_id = -1;
211 int bnxt_hwrm_set_filter(struct bnxt *bp,
212 struct bnxt_vnic_info *vnic,
213 struct bnxt_filter_info *filter)
216 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
217 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
218 uint32_t enables = 0;
220 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, -1, resp);
222 req.flags = rte_cpu_to_le_32(filter->flags);
224 enables = filter->enables |
225 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
226 req.dst_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
229 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
230 memcpy(req.l2_addr, filter->l2_addr,
233 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
234 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
237 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
238 req.l2_ovlan = filter->l2_ovlan;
240 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
241 req.l2_ovlan_mask = filter->l2_ovlan_mask;
243 req.enables = rte_cpu_to_le_32(enables);
245 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
249 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
254 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, void *fwd_cmd)
257 struct hwrm_exec_fwd_resp_input req = {.req_type = 0 };
258 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
260 HWRM_PREP(req, EXEC_FWD_RESP, -1, resp);
262 memcpy(req.encap_request, fwd_cmd,
263 sizeof(req.encap_request));
265 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
272 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
275 struct hwrm_func_qcaps_input req = {.req_type = 0 };
276 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
278 HWRM_PREP(req, FUNC_QCAPS, -1, resp);
280 req.fid = rte_cpu_to_le_16(0xffff);
282 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
286 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
288 struct bnxt_pf_info *pf = &bp->pf;
290 pf->fw_fid = rte_le_to_cpu_32(resp->fid);
291 pf->port_id = resp->port_id;
292 memcpy(pf->mac_addr, resp->perm_mac_address, ETHER_ADDR_LEN);
293 pf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
294 pf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
295 pf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
296 pf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
297 pf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
298 pf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
299 pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
300 pf->max_vfs = rte_le_to_cpu_16(resp->max_vfs);
302 struct bnxt_vf_info *vf = &bp->vf;
304 vf->fw_fid = rte_le_to_cpu_32(resp->fid);
305 memcpy(vf->mac_addr, &resp->perm_mac_address, ETHER_ADDR_LEN);
306 vf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
307 vf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
308 vf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
309 vf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
310 vf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
311 vf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
317 int bnxt_hwrm_func_reset(struct bnxt *bp)
320 struct hwrm_func_reset_input req = {.req_type = 0 };
321 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
323 HWRM_PREP(req, FUNC_RESET, -1, resp);
325 req.enables = rte_cpu_to_le_32(0);
327 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
334 int bnxt_hwrm_func_driver_register(struct bnxt *bp, uint32_t flags,
335 uint32_t *vf_req_fwd)
338 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
339 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
341 if (bp->flags & BNXT_FLAG_REGISTERED)
344 HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
346 req.enables = HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER;
347 req.ver_maj = RTE_VER_YEAR;
348 req.ver_min = RTE_VER_MONTH;
349 req.ver_upd = RTE_VER_MINOR;
351 memcpy(req.vf_req_fwd, vf_req_fwd, sizeof(req.vf_req_fwd));
353 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
357 bp->flags |= BNXT_FLAG_REGISTERED;
362 int bnxt_hwrm_ver_get(struct bnxt *bp)
365 struct hwrm_ver_get_input req = {.req_type = 0 };
366 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
369 uint16_t max_resp_len;
370 char type[RTE_MEMZONE_NAMESIZE];
372 HWRM_PREP(req, VER_GET, -1, resp);
374 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
375 req.hwrm_intf_min = HWRM_VERSION_MINOR;
376 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
379 * Hold the lock since we may be adjusting the response pointers.
381 rte_spinlock_lock(&bp->hwrm_lock);
382 rc = bnxt_hwrm_send_message_locked(bp, &req, sizeof(req));
386 RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
387 resp->hwrm_intf_maj, resp->hwrm_intf_min,
389 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
391 my_version = HWRM_VERSION_MAJOR << 16;
392 my_version |= HWRM_VERSION_MINOR << 8;
393 my_version |= HWRM_VERSION_UPDATE;
395 fw_version = resp->hwrm_intf_maj << 16;
396 fw_version |= resp->hwrm_intf_min << 8;
397 fw_version |= resp->hwrm_intf_upd;
399 if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
400 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
405 if (my_version != fw_version) {
406 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
407 if (my_version < fw_version) {
409 "Firmware API version is newer than driver.\n");
411 "The driver may be missing features.\n");
414 "Firmware API version is older than driver.\n");
416 "Not all driver features may be functional.\n");
420 if (bp->max_req_len > resp->max_req_win_len) {
421 RTE_LOG(ERR, PMD, "Unsupported request length\n");
424 bp->max_req_len = resp->max_req_win_len;
425 max_resp_len = resp->max_resp_len;
426 if (bp->max_resp_len != max_resp_len) {
427 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
428 bp->pdev->addr.domain, bp->pdev->addr.bus,
429 bp->pdev->addr.devid, bp->pdev->addr.function);
431 rte_free(bp->hwrm_cmd_resp_addr);
433 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
434 if (bp->hwrm_cmd_resp_addr == NULL) {
438 bp->hwrm_cmd_resp_dma_addr =
439 rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
440 bp->max_resp_len = max_resp_len;
444 rte_spinlock_unlock(&bp->hwrm_lock);
448 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
451 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
452 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
454 if (!(bp->flags & BNXT_FLAG_REGISTERED))
457 HWRM_PREP(req, FUNC_DRV_UNRGTR, -1, resp);
460 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
464 bp->flags &= ~BNXT_FLAG_REGISTERED;
469 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
472 struct hwrm_port_phy_cfg_input req = {.req_type = 0};
473 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
475 HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
477 req.flags = conf->phy_flags;
479 req.force_link_speed = conf->link_speed;
481 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
482 * any auto mode, even "none".
484 if (req.auto_mode == HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE) {
485 req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
487 req.auto_mode = conf->auto_mode;
489 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
490 req.auto_link_speed_mask = conf->auto_link_speed_mask;
492 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
493 req.auto_link_speed = conf->auto_link_speed;
495 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
497 req.auto_duplex = conf->duplex;
498 req.enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
499 req.auto_pause = conf->auto_pause;
500 /* Set force_pause if there is no auto or if there is a force */
503 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
506 HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
507 req.force_pause = conf->force_pause;
510 HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
512 req.flags &= ~HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
513 req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN;
514 req.force_link_speed = 0;
517 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
524 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
527 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
528 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
530 HWRM_PREP(req, QUEUE_QPORTCFG, -1, resp);
532 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
536 #define GET_QUEUE_INFO(x) \
537 bp->cos_queue[x].id = resp->queue_id##x; \
538 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
552 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
553 struct bnxt_ring *ring,
554 uint32_t ring_type, uint32_t map_index,
555 uint32_t stats_ctx_id)
558 struct hwrm_ring_alloc_input req = {.req_type = 0 };
559 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
561 HWRM_PREP(req, RING_ALLOC, -1, resp);
563 req.enables = rte_cpu_to_le_32(0);
565 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
566 req.fbo = rte_cpu_to_le_32(0);
567 /* Association of ring index with doorbell index */
568 req.logical_id = rte_cpu_to_le_16(map_index);
571 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
572 req.queue_id = bp->cos_queue[0].id;
573 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
574 req.ring_type = ring_type;
576 rte_cpu_to_le_16(bp->grp_info[map_index].cp_fw_ring_id);
577 req.length = rte_cpu_to_le_32(ring->ring_size);
578 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
579 req.enables = rte_cpu_to_le_32(rte_le_to_cpu_32(req.enables) |
580 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID);
582 case HWRM_RING_ALLOC_INPUT_RING_TYPE_CMPL:
583 req.ring_type = ring_type;
585 * TODO: Some HWRM versions crash with
586 * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
588 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
589 req.length = rte_cpu_to_le_32(ring->ring_size);
592 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
597 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
599 if (rc || resp->error_code) {
600 if (rc == 0 && resp->error_code)
601 rc = rte_le_to_cpu_16(resp->error_code);
603 case HWRM_RING_FREE_INPUT_RING_TYPE_CMPL:
605 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
607 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
609 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
611 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
613 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
616 RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
621 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
625 int bnxt_hwrm_ring_free(struct bnxt *bp,
626 struct bnxt_ring *ring, uint32_t ring_type)
629 struct hwrm_ring_free_input req = {.req_type = 0 };
630 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
632 HWRM_PREP(req, RING_FREE, -1, resp);
634 req.ring_type = ring_type;
635 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
637 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
639 if (rc || resp->error_code) {
640 if (rc == 0 && resp->error_code)
641 rc = rte_le_to_cpu_16(resp->error_code);
644 case HWRM_RING_FREE_INPUT_RING_TYPE_CMPL:
645 RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
648 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
649 RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
652 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
653 RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
657 RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
664 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
667 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
668 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
670 HWRM_PREP(req, RING_GRP_ALLOC, -1, resp);
672 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
673 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
674 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
675 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
677 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
681 bp->grp_info[idx].fw_grp_id =
682 rte_le_to_cpu_16(resp->ring_group_id);
687 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
690 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
691 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
693 HWRM_PREP(req, RING_GRP_FREE, -1, resp);
695 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
697 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
701 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
705 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
708 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
709 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
711 HWRM_PREP(req, STAT_CTX_CLR_STATS, -1, resp);
713 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
716 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
717 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
719 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
726 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp,
727 struct bnxt_cp_ring_info *cpr, unsigned int idx)
730 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
731 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
733 HWRM_PREP(req, STAT_CTX_ALLOC, -1, resp);
735 req.update_period_ms = rte_cpu_to_le_32(1000);
737 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
739 rte_cpu_to_le_64(cpr->hw_stats_map);
741 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
745 cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
746 bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
751 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp,
752 struct bnxt_cp_ring_info *cpr, unsigned int idx)
755 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
756 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
758 HWRM_PREP(req, STAT_CTX_FREE, -1, resp);
760 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
761 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
763 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
767 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
768 bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
773 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
776 struct hwrm_vnic_alloc_input req = {.req_type = 0 };
777 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
779 /* map ring groups to this vnic */
780 for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++) {
781 if (bp->grp_info[i].fw_grp_id == (uint16_t)HWRM_NA_SIGNATURE) {
783 "Not enough ring groups avail:%x req:%x\n", j,
784 (vnic->end_grp_id - vnic->start_grp_id) + 1);
787 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
790 vnic->fw_rss_cos_lb_ctx = (uint16_t)HWRM_NA_SIGNATURE;
791 vnic->ctx_is_rss_cos_lb = HW_CONTEXT_NONE;
793 HWRM_PREP(req, VNIC_ALLOC, -1, resp);
795 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
799 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
803 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
806 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
807 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
809 HWRM_PREP(req, VNIC_CFG, -1, resp);
811 /* Only RSS support for now TBD: COS & LB */
813 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP |
814 HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE |
815 HWRM_VNIC_CFG_INPUT_ENABLES_MRU);
816 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
818 rte_cpu_to_le_16(bp->grp_info[vnic->start_grp_id].fw_grp_id);
819 req.rss_rule = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
820 req.cos_rule = rte_cpu_to_le_16(0xffff);
821 req.lb_rule = rte_cpu_to_le_16(0xffff);
822 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
823 ETHER_CRC_LEN + VLAN_TAG_SIZE);
824 if (vnic->func_default)
826 if (vnic->vlan_strip)
828 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
830 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
837 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
840 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
841 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
842 bp->hwrm_cmd_resp_addr;
844 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, -1, resp);
846 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
850 vnic->fw_rss_cos_lb_ctx = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
855 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
858 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
859 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
860 bp->hwrm_cmd_resp_addr;
862 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, -1, resp);
864 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
866 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
870 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
875 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
878 struct hwrm_vnic_free_input req = {.req_type = 0 };
879 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
881 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
884 HWRM_PREP(req, VNIC_FREE, -1, resp);
886 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
888 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
892 vnic->fw_vnic_id = INVALID_HW_RING_ID;
896 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
897 struct bnxt_vnic_info *vnic)
900 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
901 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
903 HWRM_PREP(req, VNIC_RSS_CFG, -1, resp);
905 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
907 req.ring_grp_tbl_addr =
908 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
909 req.hash_key_tbl_addr =
910 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
911 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
913 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
921 * HWRM utility functions
924 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
929 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
930 struct bnxt_tx_queue *txq;
931 struct bnxt_rx_queue *rxq;
932 struct bnxt_cp_ring_info *cpr;
934 if (i >= bp->rx_cp_nr_rings) {
935 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
938 rxq = bp->rx_queues[i];
942 rc = bnxt_hwrm_stat_clear(bp, cpr);
949 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
953 struct bnxt_cp_ring_info *cpr;
955 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
956 unsigned int idx = i + 1;
958 if (i >= bp->rx_cp_nr_rings)
959 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
961 cpr = bp->rx_queues[i]->cp_ring;
962 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
963 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, idx);
971 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
976 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
977 struct bnxt_tx_queue *txq;
978 struct bnxt_rx_queue *rxq;
979 struct bnxt_cp_ring_info *cpr;
980 unsigned int idx = i + 1;
982 if (i >= bp->rx_cp_nr_rings) {
983 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
986 rxq = bp->rx_queues[i];
990 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, idx);
998 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1003 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1004 unsigned int idx = i + 1;
1006 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID) {
1008 "Attempt to free invalid ring group %d\n",
1013 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1021 static void bnxt_free_cp_ring(struct bnxt *bp,
1022 struct bnxt_cp_ring_info *cpr, unsigned int idx)
1024 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1026 bnxt_hwrm_ring_free(bp, cp_ring,
1027 HWRM_RING_FREE_INPUT_RING_TYPE_CMPL);
1028 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1029 bp->grp_info[idx].cp_fw_ring_id = INVALID_HW_RING_ID;
1030 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1031 sizeof(*cpr->cp_desc_ring));
1032 cpr->cp_raw_cons = 0;
1035 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1040 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1041 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1042 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1043 struct bnxt_ring *ring = txr->tx_ring_struct;
1044 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1045 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1047 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1048 bnxt_hwrm_ring_free(bp, ring,
1049 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1050 ring->fw_ring_id = INVALID_HW_RING_ID;
1051 memset(txr->tx_desc_ring, 0,
1052 txr->tx_ring_struct->ring_size *
1053 sizeof(*txr->tx_desc_ring));
1054 memset(txr->tx_buf_ring, 0,
1055 txr->tx_ring_struct->ring_size *
1056 sizeof(*txr->tx_buf_ring));
1060 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
1061 bnxt_free_cp_ring(bp, cpr, idx);
1064 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1065 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1066 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1067 struct bnxt_ring *ring = rxr->rx_ring_struct;
1068 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1069 unsigned int idx = i + 1;
1071 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1072 bnxt_hwrm_ring_free(bp, ring,
1073 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1074 ring->fw_ring_id = INVALID_HW_RING_ID;
1075 bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1076 memset(rxr->rx_desc_ring, 0,
1077 rxr->rx_ring_struct->ring_size *
1078 sizeof(*rxr->rx_desc_ring));
1079 memset(rxr->rx_buf_ring, 0,
1080 rxr->rx_ring_struct->ring_size *
1081 sizeof(*rxr->rx_buf_ring));
1084 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
1085 bnxt_free_cp_ring(bp, cpr, idx);
1088 /* Default completion ring */
1090 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1092 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
1093 bnxt_free_cp_ring(bp, cpr, 0);
1099 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1104 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1105 unsigned int idx = i + 1;
1107 if (bp->grp_info[idx].cp_fw_ring_id == INVALID_HW_RING_ID ||
1108 bp->grp_info[idx].rx_fw_ring_id == INVALID_HW_RING_ID)
1111 rc = bnxt_hwrm_ring_grp_alloc(bp, idx);
1119 void bnxt_free_hwrm_resources(struct bnxt *bp)
1121 /* Release memzone */
1122 rte_free(bp->hwrm_cmd_resp_addr);
1123 bp->hwrm_cmd_resp_addr = NULL;
1124 bp->hwrm_cmd_resp_dma_addr = 0;
1127 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1129 struct rte_pci_device *pdev = bp->pdev;
1130 char type[RTE_MEMZONE_NAMESIZE];
1132 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1133 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1134 bp->max_req_len = HWRM_MAX_REQ_LEN;
1135 bp->max_resp_len = HWRM_MAX_RESP_LEN;
1136 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1137 if (bp->hwrm_cmd_resp_addr == NULL)
1139 bp->hwrm_cmd_resp_dma_addr =
1140 rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
1141 rte_spinlock_init(&bp->hwrm_lock);
1146 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1148 struct bnxt_filter_info *filter;
1151 STAILQ_FOREACH(filter, &vnic->filter, next) {
1152 rc = bnxt_hwrm_clear_filter(bp, filter);
1159 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1161 struct bnxt_filter_info *filter;
1164 STAILQ_FOREACH(filter, &vnic->filter, next) {
1165 rc = bnxt_hwrm_set_filter(bp, vnic, filter);
1172 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1174 struct bnxt_vnic_info *vnic;
1177 if (bp->vnic_info == NULL)
1180 vnic = &bp->vnic_info[0];
1181 bnxt_hwrm_cfa_l2_clear_rx_mask(bp, vnic);
1183 /* VNIC resources */
1184 for (i = 0; i < bp->nr_vnics; i++) {
1185 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1187 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1189 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1190 bnxt_hwrm_vnic_free(bp, vnic);
1192 /* Ring resources */
1193 bnxt_free_all_hwrm_rings(bp);
1194 bnxt_free_all_hwrm_ring_grps(bp);
1195 bnxt_free_all_hwrm_stat_ctxs(bp);
1198 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1200 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1202 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1203 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1205 switch (conf_link_speed) {
1206 case ETH_LINK_SPEED_10M_HD:
1207 case ETH_LINK_SPEED_100M_HD:
1208 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1210 return hw_link_duplex;
1213 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1215 uint16_t eth_link_speed = 0;
1217 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1218 return ETH_LINK_SPEED_AUTONEG;
1220 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1221 case ETH_LINK_SPEED_100M:
1222 case ETH_LINK_SPEED_100M_HD:
1224 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB;
1226 case ETH_LINK_SPEED_1G:
1228 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1230 case ETH_LINK_SPEED_2_5G:
1232 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1234 case ETH_LINK_SPEED_10G:
1236 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1238 case ETH_LINK_SPEED_20G:
1240 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1242 case ETH_LINK_SPEED_25G:
1244 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
1246 case ETH_LINK_SPEED_40G:
1248 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
1250 case ETH_LINK_SPEED_50G:
1252 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
1256 "Unsupported link speed %d; default to AUTO\n",
1260 return eth_link_speed;
1263 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1264 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1265 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1266 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1268 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
1272 if (link_speed == ETH_LINK_SPEED_AUTONEG)
1275 if (link_speed & ETH_LINK_SPEED_FIXED) {
1276 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1278 if (one_speed & (one_speed - 1)) {
1280 "Invalid advertised speeds (%u) for port %u\n",
1281 link_speed, port_id);
1284 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1286 "Unsupported advertised speed (%u) for port %u\n",
1287 link_speed, port_id);
1291 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1293 "Unsupported advertised speeds (%u) for port %u\n",
1294 link_speed, port_id);
1301 static uint16_t bnxt_parse_eth_link_speed_mask(uint32_t link_speed)
1305 if (link_speed == ETH_LINK_SPEED_AUTONEG)
1306 link_speed = BNXT_SUPPORTED_SPEEDS;
1308 if (link_speed & ETH_LINK_SPEED_100M)
1309 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1310 if (link_speed & ETH_LINK_SPEED_100M_HD)
1311 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1312 if (link_speed & ETH_LINK_SPEED_1G)
1313 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1314 if (link_speed & ETH_LINK_SPEED_2_5G)
1315 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1316 if (link_speed & ETH_LINK_SPEED_10G)
1317 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1318 if (link_speed & ETH_LINK_SPEED_20G)
1319 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1320 if (link_speed & ETH_LINK_SPEED_25G)
1321 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
1322 if (link_speed & ETH_LINK_SPEED_40G)
1323 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
1324 if (link_speed & ETH_LINK_SPEED_50G)
1325 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
1329 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
1332 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1333 struct bnxt_link_info link_req;
1336 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
1337 bp->eth_dev->data->port_id);
1341 memset(&link_req, 0, sizeof(link_req));
1342 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
1343 link_req.link_up = link_up;
1345 link_req.phy_flags =
1346 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
1347 link_req.auto_mode =
1348 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW;
1349 link_req.auto_link_speed_mask =
1350 bnxt_parse_eth_link_speed_mask(dev_conf->link_speeds);
1351 link_req.auto_link_speed =
1352 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB;
1354 link_req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1355 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE |
1356 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
1357 link_req.link_speed = speed;
1359 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
1360 link_req.auto_pause = bp->link_info.auto_pause;
1361 link_req.force_pause = bp->link_info.force_pause;
1363 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
1366 "Set link config failed with rc %d\n", rc);