drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SPEC_CODE_1_8_3            0x10803
  31 #define HWRM_VERSION_1_9_1              0x10901
  32 #define HWRM_VERSION_1_9_2              0x10903
  33
  34 struct bnxt_plcmodes_cfg {
  35         uint32_t        flags;
  36         uint16_t        jumbo_thresh;
  37         uint16_t        hds_offset;
  38         uint16_t        hds_threshold;
  39 };
  40
  41 static int page_getenum(size_t size)
  42 {
  43         if (size <= 1 << 4)
  44                 return 4;
  45         if (size <= 1 << 12)
  46                 return 12;
  47         if (size <= 1 << 13)
  48                 return 13;
  49         if (size <= 1 << 16)
  50                 return 16;
  51         if (size <= 1 << 21)
  52                 return 21;
  53         if (size <= 1 << 22)
  54                 return 22;
  55         if (size <= 1 << 30)
  56                 return 30;
  57         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  58         return sizeof(void *) * 8 - 1;
  59 }
  60
  61 static int page_roundup(size_t size)
  62 {
  63         return 1 << page_getenum(size);
  64 }
  65
  66 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  67                                   uint8_t *pg_attr,
  68                                   uint64_t *pg_dir)
  69 {
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 /*
  79  * HWRM Functions (sent to HWRM)
  80  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  81  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  82  * command was failed by the ChiMP.
  83  */
  84
  85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  86                                   uint32_t msg_len, bool use_kong_mb)
  87 {
  88         unsigned int i;
  89         struct input *req = msg;
  90         struct output *resp = bp->hwrm_cmd_resp_addr;
  91         uint32_t *data = msg;
  92         uint8_t *bar;
  93         uint8_t *valid;
  94         uint16_t max_req_len = bp->max_req_len;
  95         struct hwrm_short_input short_input = { 0 };
  96         uint16_t bar_offset = use_kong_mb ?
  97                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  98         uint16_t mb_trigger_offset = use_kong_mb ?
  99                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 100
 101         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 102             msg_len > bp->max_req_len) {
 103                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 104
 105                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 106                 memcpy(short_cmd_req, req, msg_len);
 107
 108                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 109                 short_input.signature = rte_cpu_to_le_16(
 110                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 111                 short_input.size = rte_cpu_to_le_16(msg_len);
 112                 short_input.req_addr =
 113                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 114
 115                 data = (uint32_t *)&short_input;
 116                 msg_len = sizeof(short_input);
 117
 118                 /* Sync memory write before updating doorbell */
 119                 rte_wmb();
 120
 121                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 122         }
 123
 124         /* Write request msg to hwrm channel */
 125         for (i = 0; i < msg_len; i += 4) {
 126                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 127                 rte_write32(*data, bar);
 128                 data++;
 129         }
 130
 131         /* Zero the rest of the request space */
 132         for (; i < max_req_len; i += 4) {
 133                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 134                 rte_write32(0, bar);
 135         }
 136
 137         /* Ring channel doorbell */
 138         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 139         rte_write32(1, bar);
 140
 141         /* Poll for the valid bit */
 142         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 143                 /* Sanity check on the resp->resp_len */
 144                 rte_rmb();
 145                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 146                         /* Last byte of resp contains the valid key */
 147                         valid = (uint8_t *)resp + resp->resp_len - 1;
 148                         if (*valid == HWRM_RESP_VALID_KEY)
 149                                 break;
 150                 }
 151                 rte_delay_us(1);
 152         }
 153
 154         if (i >= HWRM_CMD_TIMEOUT) {
 155                 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
 156                         req->req_type);
 157                 goto err_ret;
 158         }
 159         return 0;
 160
 161 err_ret:
 162         return -1;
 163 }
 164
 165 /*
 166  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 167  * spinlock, and does initial processing.
 168  *
 169  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 170  * releases the spinlock only if it returns.  If the regular int return codes
 171  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 172  * directly, rather it should be copied and modified to suit the function.
 173  *
 174  * HWRM_UNLOCK() must be called after all response processing is completed.
 175  */
 176 #define HWRM_PREP(req, type, kong) do { \
 177         rte_spinlock_lock(&bp->hwrm_lock); \
 178         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 179         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 180         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 181         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 182                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 183         req.target_id = rte_cpu_to_le_16(0xffff); \
 184         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 185 } while (0)
 186
 187 #define HWRM_CHECK_RESULT_SILENT() do {\
 188         if (rc) { \
 189                 rte_spinlock_unlock(&bp->hwrm_lock); \
 190                 return rc; \
 191         } \
 192         if (resp->error_code) { \
 193                 rc = rte_le_to_cpu_16(resp->error_code); \
 194                 rte_spinlock_unlock(&bp->hwrm_lock); \
 195                 return rc; \
 196         } \
 197 } while (0)
 198
 199 #define HWRM_CHECK_RESULT() do {\
 200         if (rc) { \
 201                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 204                         rc = -EACCES; \
 205                 else if (rc > 0) \
 206                         rc = -EINVAL; \
 207                 return rc; \
 208         } \
 209         if (resp->error_code) { \
 210                 rc = rte_le_to_cpu_16(resp->error_code); \
 211                 if (resp->resp_len >= 16) { \
 212                         struct hwrm_err_output *tmp_hwrm_err_op = \
 213                                                 (void *)resp; \
 214                         PMD_DRV_LOG(ERR, \
 215                                 "error %d:%d:%08x:%04x\n", \
 216                                 rc, tmp_hwrm_err_op->cmd_err, \
 217                                 rte_le_to_cpu_32(\
 218                                         tmp_hwrm_err_op->opaque_0), \
 219                                 rte_le_to_cpu_16(\
 220                                         tmp_hwrm_err_op->opaque_1)); \
 221                 } else { \
 222                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 223                 } \
 224                 rte_spinlock_unlock(&bp->hwrm_lock); \
 225                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 226                         rc = -EACCES; \
 227                 else if (rc > 0) \
 228                         rc = -EINVAL; \
 229                 return rc; \
 230         } \
 231 } while (0)
 232
 233 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 234
 235 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 236 {
 237         int rc = 0;
 238         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 239         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 240
 241         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 242         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 243         req.mask = 0;
 244
 245         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 246
 247         HWRM_CHECK_RESULT();
 248         HWRM_UNLOCK();
 249
 250         return rc;
 251 }
 252
 253 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 254                                  struct bnxt_vnic_info *vnic,
 255                                  uint16_t vlan_count,
 256                                  struct bnxt_vlan_table_entry *vlan_table)
 257 {
 258         int rc = 0;
 259         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 260         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 261         uint32_t mask = 0;
 262
 263         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 264                 return rc;
 265
 266         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 268
 269         /* FIXME add multicast flag, when multicast adding options is supported
 270          * by ethtool.
 271          */
 272         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 273                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 274         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 275                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 276         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 277                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 278         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 279                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 280         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 281                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 282         if (vnic->mc_addr_cnt) {
 283                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 284                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 285                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 286         }
 287         if (vlan_table) {
 288                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 289                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 290                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 291                          rte_mem_virt2iova(vlan_table));
 292                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 293         }
 294         req.mask = rte_cpu_to_le_32(mask);
 295
 296         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 297
 298         HWRM_CHECK_RESULT();
 299         HWRM_UNLOCK();
 300
 301         return rc;
 302 }
 303
 304 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 305                         uint16_t vlan_count,
 306                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 307 {
 308         int rc = 0;
 309         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 310         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 311                                                 bp->hwrm_cmd_resp_addr;
 312
 313         /*
 314          * Older HWRM versions did not support this command, and the set_rx_mask
 315          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 316          * removed from set_rx_mask call, and this command was added.
 317          *
 318          * This command is also present from 1.7.8.11 and higher,
 319          * as well as 1.7.8.0
 320          */
 321         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 322                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 323                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 324                                         (11)))
 325                                 return 0;
 326                 }
 327         }
 328         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 329         req.fid = rte_cpu_to_le_16(fid);
 330
 331         req.vlan_tag_mask_tbl_addr =
 332                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 333         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 334
 335         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 336
 337         HWRM_CHECK_RESULT();
 338         HWRM_UNLOCK();
 339
 340         return rc;
 341 }
 342
 343 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 344                            struct bnxt_filter_info *filter)
 345 {
 346         int rc = 0;
 347         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 348         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 349
 350         if (filter->fw_l2_filter_id == UINT64_MAX)
 351                 return 0;
 352
 353         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 354
 355         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         filter->fw_l2_filter_id = UINT64_MAX;
 363
 364         return 0;
 365 }
 366
 367 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 368                          uint16_t dst_id,
 369                          struct bnxt_filter_info *filter)
 370 {
 371         int rc = 0;
 372         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 373         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 374         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 375         const struct rte_eth_vmdq_rx_conf *conf =
 376                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 377         uint32_t enables = 0;
 378         uint16_t j = dst_id - 1;
 379
 380         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 381         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 382             conf->pool_map[j].pools & (1UL << j)) {
 383                 PMD_DRV_LOG(DEBUG,
 384                         "Add vlan %u to vmdq pool %u\n",
 385                         conf->pool_map[j].vlan_id, j);
 386
 387                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 388                 filter->enables |=
 389                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 390                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 391         }
 392
 393         if (filter->fw_l2_filter_id != UINT64_MAX)
 394                 bnxt_hwrm_clear_l2_filter(bp, filter);
 395
 396         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 397
 398         req.flags = rte_cpu_to_le_32(filter->flags);
 399         req.flags |=
 400         rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
 401
 402         enables = filter->enables |
 403               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 404         req.dst_id = rte_cpu_to_le_16(dst_id);
 405
 406         if (enables &
 407             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 408                 memcpy(req.l2_addr, filter->l2_addr,
 409                        RTE_ETHER_ADDR_LEN);
 410         if (enables &
 411             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 412                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 413                        RTE_ETHER_ADDR_LEN);
 414         if (enables &
 415             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 416                 req.l2_ovlan = filter->l2_ovlan;
 417         if (enables &
 418             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 419                 req.l2_ivlan = filter->l2_ivlan;
 420         if (enables &
 421             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 422                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 423         if (enables &
 424             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 425                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 426         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 427                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 428         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 429                 req.src_type = filter->src_type;
 430
 431         req.enables = rte_cpu_to_le_32(enables);
 432
 433         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 434
 435         HWRM_CHECK_RESULT();
 436
 437         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 438         HWRM_UNLOCK();
 439
 440         return rc;
 441 }
 442
 443 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 444 {
 445         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 446         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 447         uint32_t flags = 0;
 448         int rc;
 449
 450         if (!ptp)
 451                 return 0;
 452
 453         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 454
 455         if (ptp->rx_filter)
 456                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 457         else
 458                 flags |=
 459                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 460         if (ptp->tx_tstamp_en)
 461                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 462         else
 463                 flags |=
 464                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 465         req.flags = rte_cpu_to_le_32(flags);
 466         req.enables = rte_cpu_to_le_32
 467                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 468         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 469
 470         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 471         HWRM_UNLOCK();
 472
 473         return rc;
 474 }
 475
 476 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 477 {
 478         int rc = 0;
 479         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 480         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 481         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 482
 483 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 484         if (ptp)
 485                 return 0;
 486
 487         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 488
 489         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 490
 491         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 492
 493         HWRM_CHECK_RESULT();
 494
 495         if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 496                 return 0;
 497
 498         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 499         if (!ptp)
 500                 return -ENOMEM;
 501
 502         ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 503                 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 504         ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 505                 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 506         ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 507                 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 508         ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 509                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 510         ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 511                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 512         ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 513                 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 514         ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 515                 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 516         ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 517                 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 518         ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 519                 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 520
 521         ptp->bp = bp;
 522         bp->ptp_cfg = ptp;
 523
 524         return 0;
 525 }
 526
 527 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 528 {
 529         int rc = 0;
 530         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 531         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 532         uint16_t new_max_vfs;
 533         uint32_t flags;
 534         int i;
 535
 536         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 537
 538         req.fid = rte_cpu_to_le_16(0xffff);
 539
 540         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 541
 542         HWRM_CHECK_RESULT();
 543
 544         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 545         flags = rte_le_to_cpu_32(resp->flags);
 546         if (BNXT_PF(bp)) {
 547                 bp->pf.port_id = resp->port_id;
 548                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 549                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 550                 new_max_vfs = bp->pdev->max_vfs;
 551                 if (new_max_vfs != bp->pf.max_vfs) {
 552                         if (bp->pf.vf_info)
 553                                 rte_free(bp->pf.vf_info);
 554                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 555                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 556                         bp->pf.max_vfs = new_max_vfs;
 557                         for (i = 0; i < new_max_vfs; i++) {
 558                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 559                                 bp->pf.vf_info[i].vlan_table =
 560                                         rte_zmalloc("VF VLAN table",
 561                                                     getpagesize(),
 562                                                     getpagesize());
 563                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 564                                         PMD_DRV_LOG(ERR,
 565                                         "Fail to alloc VLAN table for VF %d\n",
 566                                         i);
 567                                 else
 568                                         rte_mem_lock_page(
 569                                                 bp->pf.vf_info[i].vlan_table);
 570                                 bp->pf.vf_info[i].vlan_as_table =
 571                                         rte_zmalloc("VF VLAN AS table",
 572                                                     getpagesize(),
 573                                                     getpagesize());
 574                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 575                                         PMD_DRV_LOG(ERR,
 576                                         "Alloc VLAN AS table for VF %d fail\n",
 577                                         i);
 578                                 else
 579                                         rte_mem_lock_page(
 580                                                bp->pf.vf_info[i].vlan_as_table);
 581                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 582                         }
 583                 }
 584         }
 585
 586         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 587         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 588         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 589         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 590         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 591         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 592         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 593         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 594         /* TODO: For now, do not support VMDq/RFS on VFs. */
 595         if (BNXT_PF(bp)) {
 596                 if (bp->pf.max_vfs)
 597                         bp->max_vnics = 1;
 598                 else
 599                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 600         } else {
 601                 bp->max_vnics = 1;
 602         }
 603         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 604         if (BNXT_PF(bp)) {
 605                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 606                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 607                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 608                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 609                         HWRM_UNLOCK();
 610                         bnxt_hwrm_ptp_qcfg(bp);
 611                 }
 612         }
 613
 614         HWRM_UNLOCK();
 615
 616         return rc;
 617 }
 618
 619 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 620 {
 621         int rc;
 622
 623         rc = __bnxt_hwrm_func_qcaps(bp);
 624         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 625                 rc = bnxt_alloc_ctx_mem(bp);
 626                 if (rc)
 627                         return rc;
 628
 629                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 630                 if (!rc)
 631                         bp->flags |= BNXT_FLAG_NEW_RM;
 632         }
 633
 634         return rc;
 635 }
 636
 637 int bnxt_hwrm_func_reset(struct bnxt *bp)
 638 {
 639         int rc = 0;
 640         struct hwrm_func_reset_input req = {.req_type = 0 };
 641         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 642
 643         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 644
 645         req.enables = rte_cpu_to_le_32(0);
 646
 647         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 648
 649         HWRM_CHECK_RESULT();
 650         HWRM_UNLOCK();
 651
 652         return rc;
 653 }
 654
 655 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 656 {
 657         int rc;
 658         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 659         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 660
 661         if (bp->flags & BNXT_FLAG_REGISTERED)
 662                 return 0;
 663
 664         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 665         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 666                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 667         req.ver_maj = RTE_VER_YEAR;
 668         req.ver_min = RTE_VER_MONTH;
 669         req.ver_upd = RTE_VER_MINOR;
 670
 671         if (BNXT_PF(bp)) {
 672                 req.enables |= rte_cpu_to_le_32(
 673                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 674                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 675                        RTE_MIN(sizeof(req.vf_req_fwd),
 676                                sizeof(bp->pf.vf_req_fwd)));
 677
 678                 /*
 679                  * PF can sniff HWRM API issued by VF. This can be set up by
 680                  * linux driver and inherited by the DPDK PF driver. Clear
 681                  * this HWRM sniffer list in FW because DPDK PF driver does
 682                  * not support this.
 683                  */
 684                 req.flags =
 685                 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
 686         }
 687
 688         req.async_event_fwd[0] |=
 689                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 690                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 691                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
 692         req.async_event_fwd[1] |=
 693                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 694                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 695
 696         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 697
 698         HWRM_CHECK_RESULT();
 699         HWRM_UNLOCK();
 700
 701         bp->flags |= BNXT_FLAG_REGISTERED;
 702
 703         return rc;
 704 }
 705
 706 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 707 {
 708         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 709                 return 0;
 710
 711         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 712 }
 713
 714 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 715 {
 716         int rc;
 717         uint32_t flags = 0;
 718         uint32_t enables;
 719         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 720         struct hwrm_func_vf_cfg_input req = {0};
 721
 722         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 723
 724         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 725                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 726                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 727                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 728                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 729
 730         if (BNXT_HAS_RING_GRPS(bp)) {
 731                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 732                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 733         }
 734
 735         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 736         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 737                                             AGG_RING_MULTIPLIER);
 738         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 739         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 740                                               bp->tx_nr_rings);
 741         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 742         if (bp->vf_resv_strategy ==
 743             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 744                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 745                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 746                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 747                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 748                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 749                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 750         }
 751
 752         if (test)
 753                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 754                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 755                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 756                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 757                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 758                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 759
 760         if (test && BNXT_HAS_RING_GRPS(bp))
 761                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 762
 763         req.flags = rte_cpu_to_le_32(flags);
 764         req.enables |= rte_cpu_to_le_32(enables);
 765
 766         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 767
 768         if (test)
 769                 HWRM_CHECK_RESULT_SILENT();
 770         else
 771                 HWRM_CHECK_RESULT();
 772
 773         HWRM_UNLOCK();
 774         return rc;
 775 }
 776
 777 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 778 {
 779         int rc;
 780         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 781         struct hwrm_func_resource_qcaps_input req = {0};
 782
 783         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 784         req.fid = rte_cpu_to_le_16(0xffff);
 785
 786         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 787
 788         HWRM_CHECK_RESULT();
 789
 790         if (BNXT_VF(bp)) {
 791                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 792                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 793                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 794                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 795                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 796                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 797                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 798                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 799         }
 800         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 801         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 802         if (bp->vf_resv_strategy >
 803             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 804                 bp->vf_resv_strategy =
 805                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 806
 807         HWRM_UNLOCK();
 808         return rc;
 809 }
 810
 811 int bnxt_hwrm_ver_get(struct bnxt *bp)
 812 {
 813         int rc = 0;
 814         struct hwrm_ver_get_input req = {.req_type = 0 };
 815         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 816         uint32_t fw_version;
 817         uint16_t max_resp_len;
 818         char type[RTE_MEMZONE_NAMESIZE];
 819         uint32_t dev_caps_cfg;
 820
 821         bp->max_req_len = HWRM_MAX_REQ_LEN;
 822         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 823
 824         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 825         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 826         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 827
 828         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 829
 830         HWRM_CHECK_RESULT();
 831
 832         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 833                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 834                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 835                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 836         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 837                      (resp->hwrm_fw_min_8b << 16) |
 838                      (resp->hwrm_fw_bld_8b << 8) |
 839                      resp->hwrm_fw_rsvd_8b;
 840         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 841                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 842
 843         fw_version = resp->hwrm_intf_maj_8b << 16;
 844         fw_version |= resp->hwrm_intf_min_8b << 8;
 845         fw_version |= resp->hwrm_intf_upd_8b;
 846         bp->hwrm_spec_code = fw_version;
 847
 848         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 849                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 850                 rc = -EINVAL;
 851                 goto error;
 852         }
 853
 854         if (bp->max_req_len > resp->max_req_win_len) {
 855                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 856                 rc = -EINVAL;
 857         }
 858         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 859         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 860         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 861                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 862
 863         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 864         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 865
 866         if (bp->max_resp_len != max_resp_len) {
 867                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 868                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 869                         bp->pdev->addr.devid, bp->pdev->addr.function);
 870
 871                 rte_free(bp->hwrm_cmd_resp_addr);
 872
 873                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 874                 if (bp->hwrm_cmd_resp_addr == NULL) {
 875                         rc = -ENOMEM;
 876                         goto error;
 877                 }
 878                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 879                 bp->hwrm_cmd_resp_dma_addr =
 880                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 881                 if (bp->hwrm_cmd_resp_dma_addr == 0) {
 882                         PMD_DRV_LOG(ERR,
 883                         "Unable to map response buffer to physical memory.\n");
 884                         rc = -ENOMEM;
 885                         goto error;
 886                 }
 887                 bp->max_resp_len = max_resp_len;
 888         }
 889
 890         if ((dev_caps_cfg &
 891                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 892             (dev_caps_cfg &
 893              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
 894                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 895                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 896         }
 897
 898         if (((dev_caps_cfg &
 899               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 900              (dev_caps_cfg &
 901               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
 902             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
 903                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
 904                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 905                         bp->pdev->addr.devid, bp->pdev->addr.function);
 906
 907                 rte_free(bp->hwrm_short_cmd_req_addr);
 908
 909                 bp->hwrm_short_cmd_req_addr =
 910                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
 911                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 912                         rc = -ENOMEM;
 913                         goto error;
 914                 }
 915                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 916                 bp->hwrm_short_cmd_req_dma_addr =
 917                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 918                 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
 919                         rte_free(bp->hwrm_short_cmd_req_addr);
 920                         PMD_DRV_LOG(ERR,
 921                                 "Unable to map buffer to physical memory.\n");
 922                         rc = -ENOMEM;
 923                         goto error;
 924                 }
 925         }
 926         if (dev_caps_cfg &
 927             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
 928                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
 929                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
 930         }
 931         if (dev_caps_cfg &
 932             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
 933                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
 934
 935 error:
 936         HWRM_UNLOCK();
 937         return rc;
 938 }
 939
 940 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 941 {
 942         int rc;
 943         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 944         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 945
 946         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 947                 return 0;
 948
 949         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
 950         req.flags = flags;
 951
 952         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 953
 954         HWRM_CHECK_RESULT();
 955         HWRM_UNLOCK();
 956
 957         bp->flags &= ~BNXT_FLAG_REGISTERED;
 958
 959         return rc;
 960 }
 961
 962 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 963 {
 964         int rc = 0;
 965         struct hwrm_port_phy_cfg_input req = {0};
 966         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 967         uint32_t enables = 0;
 968
 969         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
 970
 971         if (conf->link_up) {
 972                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
 973                 if (bp->link_info.auto_mode && conf->link_speed) {
 974                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
 975                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
 976                 }
 977
 978                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 979                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 980                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 981                 /*
 982                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 983                  * any auto mode, even "none".
 984                  */
 985                 if (!conf->link_speed) {
 986                         /* No speeds specified. Enable AutoNeg - all speeds */
 987                         req.auto_mode =
 988                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
 989                 }
 990                 /* AutoNeg - Advertise speeds specified. */
 991                 if (conf->auto_link_speed_mask &&
 992                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
 993                         req.auto_mode =
 994                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
 995                         req.auto_link_speed_mask =
 996                                 conf->auto_link_speed_mask;
 997                         enables |=
 998                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 999                 }
1000
1001                 req.auto_duplex = conf->duplex;
1002                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1003                 req.auto_pause = conf->auto_pause;
1004                 req.force_pause = conf->force_pause;
1005                 /* Set force_pause if there is no auto or if there is a force */
1006                 if (req.auto_pause && !req.force_pause)
1007                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1008                 else
1009                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1010
1011                 req.enables = rte_cpu_to_le_32(enables);
1012         } else {
1013                 req.flags =
1014                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1015                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1016         }
1017
1018         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1019
1020         HWRM_CHECK_RESULT();
1021         HWRM_UNLOCK();
1022
1023         return rc;
1024 }
1025
1026 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1027                                    struct bnxt_link_info *link_info)
1028 {
1029         int rc = 0;
1030         struct hwrm_port_phy_qcfg_input req = {0};
1031         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1032
1033         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1034
1035         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1036
1037         HWRM_CHECK_RESULT();
1038
1039         link_info->phy_link_status = resp->link;
1040         link_info->link_up =
1041                 (link_info->phy_link_status ==
1042                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1043         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1044         link_info->duplex = resp->duplex_cfg;
1045         link_info->pause = resp->pause;
1046         link_info->auto_pause = resp->auto_pause;
1047         link_info->force_pause = resp->force_pause;
1048         link_info->auto_mode = resp->auto_mode;
1049         link_info->phy_type = resp->phy_type;
1050         link_info->media_type = resp->media_type;
1051
1052         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1053         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1054         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1055         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1056         link_info->phy_ver[0] = resp->phy_maj;
1057         link_info->phy_ver[1] = resp->phy_min;
1058         link_info->phy_ver[2] = resp->phy_bld;
1059
1060         HWRM_UNLOCK();
1061
1062         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1063         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1064         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1065         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1066         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1067                     link_info->auto_link_speed_mask);
1068         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1069                     link_info->force_link_speed);
1070
1071         return rc;
1072 }
1073
1074 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1075 {
1076         int rc = 0;
1077         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1078         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1079         int i;
1080
1081         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1082
1083         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1084         /* HWRM Version >= 1.9.1 */
1085         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1086                 req.drv_qmap_cap =
1087                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1088         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1089
1090         HWRM_CHECK_RESULT();
1091
1092 #define GET_QUEUE_INFO(x) \
1093         bp->cos_queue[x].id = resp->queue_id##x; \
1094         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1095
1096         GET_QUEUE_INFO(0);
1097         GET_QUEUE_INFO(1);
1098         GET_QUEUE_INFO(2);
1099         GET_QUEUE_INFO(3);
1100         GET_QUEUE_INFO(4);
1101         GET_QUEUE_INFO(5);
1102         GET_QUEUE_INFO(6);
1103         GET_QUEUE_INFO(7);
1104
1105         HWRM_UNLOCK();
1106
1107         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1108                 bp->tx_cosq_id = bp->cos_queue[0].id;
1109         } else {
1110                 /* iterate and find the COSq profile to use for Tx */
1111                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1112                         if (bp->cos_queue[i].profile ==
1113                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1114                                 bp->tx_cosq_id = bp->cos_queue[i].id;
1115                                 break;
1116                         }
1117                 }
1118         }
1119
1120         bp->max_tc = resp->max_configurable_queues;
1121         bp->max_lltc = resp->max_configurable_lossless_queues;
1122         if (bp->max_tc > BNXT_MAX_QUEUE)
1123                 bp->max_tc = BNXT_MAX_QUEUE;
1124         bp->max_q = bp->max_tc;
1125
1126         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1127
1128         return rc;
1129 }
1130
1131 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1132                          struct bnxt_ring *ring,
1133                          uint32_t ring_type, uint32_t map_index,
1134                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1135 {
1136         int rc = 0;
1137         uint32_t enables = 0;
1138         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1139         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1140         struct rte_mempool *mb_pool;
1141         uint16_t rx_buf_size;
1142
1143         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1144
1145         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1146         req.fbo = rte_cpu_to_le_32(0);
1147         /* Association of ring index with doorbell index */
1148         req.logical_id = rte_cpu_to_le_16(map_index);
1149         req.length = rte_cpu_to_le_32(ring->ring_size);
1150
1151         switch (ring_type) {
1152         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1153                 req.ring_type = ring_type;
1154                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1155                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1156                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1157                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1158                         enables |=
1159                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1160                 break;
1161         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1162                 req.ring_type = ring_type;
1163                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1164                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1165                 if (BNXT_CHIP_THOR(bp)) {
1166                         mb_pool = bp->rx_queues[0]->mb_pool;
1167                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1168                                       RTE_PKTMBUF_HEADROOM;
1169                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1170                         enables |=
1171                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1172                 }
1173                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1174                         enables |=
1175                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1176                 break;
1177         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1178                 req.ring_type = ring_type;
1179                 if (BNXT_HAS_NQ(bp)) {
1180                         /* Association of cp ring with nq */
1181                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1182                         enables |=
1183                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1184                 }
1185                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1186                 break;
1187         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1188                 req.ring_type = ring_type;
1189                 req.page_size = BNXT_PAGE_SHFT;
1190                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1191                 break;
1192         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1193                 req.ring_type = ring_type;
1194                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1195
1196                 mb_pool = bp->rx_queues[0]->mb_pool;
1197                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1198                               RTE_PKTMBUF_HEADROOM;
1199                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1200
1201                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1202                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1203                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1204                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1205                 break;
1206         default:
1207                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1208                         ring_type);
1209                 HWRM_UNLOCK();
1210                 return -1;
1211         }
1212         req.enables = rte_cpu_to_le_32(enables);
1213
1214         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1215
1216         if (rc || resp->error_code) {
1217                 if (rc == 0 && resp->error_code)
1218                         rc = rte_le_to_cpu_16(resp->error_code);
1219                 switch (ring_type) {
1220                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1221                         PMD_DRV_LOG(ERR,
1222                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1223                         HWRM_UNLOCK();
1224                         return rc;
1225                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1226                         PMD_DRV_LOG(ERR,
1227                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1228                         HWRM_UNLOCK();
1229                         return rc;
1230                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1231                         PMD_DRV_LOG(ERR,
1232                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1233                                     rc);
1234                         HWRM_UNLOCK();
1235                         return rc;
1236                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1237                         PMD_DRV_LOG(ERR,
1238                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1239                         HWRM_UNLOCK();
1240                         return rc;
1241                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1242                         PMD_DRV_LOG(ERR,
1243                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1244                         HWRM_UNLOCK();
1245                         return rc;
1246                 default:
1247                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1248                         HWRM_UNLOCK();
1249                         return rc;
1250                 }
1251         }
1252
1253         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1254         HWRM_UNLOCK();
1255         return rc;
1256 }
1257
1258 int bnxt_hwrm_ring_free(struct bnxt *bp,
1259                         struct bnxt_ring *ring, uint32_t ring_type)
1260 {
1261         int rc;
1262         struct hwrm_ring_free_input req = {.req_type = 0 };
1263         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1264
1265         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1266
1267         req.ring_type = ring_type;
1268         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1269
1270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1271
1272         if (rc || resp->error_code) {
1273                 if (rc == 0 && resp->error_code)
1274                         rc = rte_le_to_cpu_16(resp->error_code);
1275                 HWRM_UNLOCK();
1276
1277                 switch (ring_type) {
1278                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1279                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1280                                 rc);
1281                         return rc;
1282                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1283                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1284                                 rc);
1285                         return rc;
1286                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1287                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1288                                 rc);
1289                         return rc;
1290                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1291                         PMD_DRV_LOG(ERR,
1292                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1293                         return rc;
1294                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1295                         PMD_DRV_LOG(ERR,
1296                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1297                         return rc;
1298                 default:
1299                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1300                         return rc;
1301                 }
1302         }
1303         HWRM_UNLOCK();
1304         return 0;
1305 }
1306
1307 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1308 {
1309         int rc = 0;
1310         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1311         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1312
1313         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1314
1315         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1316         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1317         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1318         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1319
1320         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1321
1322         HWRM_CHECK_RESULT();
1323
1324         bp->grp_info[idx].fw_grp_id =
1325             rte_le_to_cpu_16(resp->ring_group_id);
1326
1327         HWRM_UNLOCK();
1328
1329         return rc;
1330 }
1331
1332 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1333 {
1334         int rc;
1335         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1336         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1337
1338         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1339
1340         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1341
1342         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1343
1344         HWRM_CHECK_RESULT();
1345         HWRM_UNLOCK();
1346
1347         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1348         return rc;
1349 }
1350
1351 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1352 {
1353         int rc = 0;
1354         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1355         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1356
1357         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1358                 return rc;
1359
1360         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1361
1362         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1363
1364         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1365
1366         HWRM_CHECK_RESULT();
1367         HWRM_UNLOCK();
1368
1369         return rc;
1370 }
1371
1372 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1373                                 unsigned int idx __rte_unused)
1374 {
1375         int rc;
1376         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1377         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1378
1379         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1380
1381         req.update_period_ms = rte_cpu_to_le_32(0);
1382
1383         req.stats_dma_addr =
1384             rte_cpu_to_le_64(cpr->hw_stats_map);
1385
1386         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1387
1388         HWRM_CHECK_RESULT();
1389
1390         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1391
1392         HWRM_UNLOCK();
1393
1394         return rc;
1395 }
1396
1397 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1398                                 unsigned int idx __rte_unused)
1399 {
1400         int rc;
1401         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1402         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1403
1404         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1405
1406         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1407
1408         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1409
1410         HWRM_CHECK_RESULT();
1411         HWRM_UNLOCK();
1412
1413         return rc;
1414 }
1415
1416 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1417 {
1418         int rc = 0, i, j;
1419         struct hwrm_vnic_alloc_input req = { 0 };
1420         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1421
1422         if (!BNXT_HAS_RING_GRPS(bp))
1423                 goto skip_ring_grps;
1424
1425         /* map ring groups to this vnic */
1426         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1427                 vnic->start_grp_id, vnic->end_grp_id);
1428         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1429                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1430
1431         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1432         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1433         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1434         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1435
1436 skip_ring_grps:
1437         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1438                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1439         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1440
1441         if (vnic->func_default)
1442                 req.flags =
1443                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1444         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1445
1446         HWRM_CHECK_RESULT();
1447
1448         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1449         HWRM_UNLOCK();
1450         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1451         return rc;
1452 }
1453
1454 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1455                                         struct bnxt_vnic_info *vnic,
1456                                         struct bnxt_plcmodes_cfg *pmode)
1457 {
1458         int rc = 0;
1459         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1460         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1461
1462         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1463
1464         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1465
1466         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1467
1468         HWRM_CHECK_RESULT();
1469
1470         pmode->flags = rte_le_to_cpu_32(resp->flags);
1471         /* dflt_vnic bit doesn't exist in the _cfg command */
1472         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1473         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1474         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1475         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1476
1477         HWRM_UNLOCK();
1478
1479         return rc;
1480 }
1481
1482 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1483                                        struct bnxt_vnic_info *vnic,
1484                                        struct bnxt_plcmodes_cfg *pmode)
1485 {
1486         int rc = 0;
1487         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1488         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1489
1490         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1491
1492         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1493         req.flags = rte_cpu_to_le_32(pmode->flags);
1494         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1495         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1496         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1497         req.enables = rte_cpu_to_le_32(
1498             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1499             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1500             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1501         );
1502
1503         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1504
1505         HWRM_CHECK_RESULT();
1506         HWRM_UNLOCK();
1507
1508         return rc;
1509 }
1510
1511 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1512 {
1513         int rc = 0;
1514         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1515         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1516         uint32_t ctx_enable_flag = 0;
1517         struct bnxt_plcmodes_cfg pmodes;
1518         uint32_t enables = 0;
1519
1520         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1521                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1522                 return rc;
1523         }
1524
1525         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1526         if (rc)
1527                 return rc;
1528
1529         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1530
1531         if (BNXT_CHIP_THOR(bp)) {
1532                 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1533                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1534                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1535
1536                 req.default_rx_ring_id =
1537                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1538                 req.default_cmpl_ring_id =
1539                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1540                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1541                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1542                 goto config_mru;
1543         }
1544
1545         /* Only RSS support for now TBD: COS & LB */
1546         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1547         if (vnic->lb_rule != 0xffff)
1548                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1549         if (vnic->cos_rule != 0xffff)
1550                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1551         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1552                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1553                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1554         }
1555         enables |= ctx_enable_flag;
1556         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1557         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1558         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1559         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1560
1561 config_mru:
1562         req.enables = rte_cpu_to_le_32(enables);
1563         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1564         req.mru = rte_cpu_to_le_16(vnic->mru);
1565         /* Configure default VNIC only once. */
1566         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1567                 req.flags |=
1568                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1569                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1570         }
1571         if (vnic->vlan_strip)
1572                 req.flags |=
1573                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1574         if (vnic->bd_stall)
1575                 req.flags |=
1576                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1577         if (vnic->roce_dual)
1578                 req.flags |= rte_cpu_to_le_32(
1579                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1580         if (vnic->roce_only)
1581                 req.flags |= rte_cpu_to_le_32(
1582                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1583         if (vnic->rss_dflt_cr)
1584                 req.flags |= rte_cpu_to_le_32(
1585                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1586
1587         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1588
1589         HWRM_CHECK_RESULT();
1590         HWRM_UNLOCK();
1591
1592         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1593
1594         return rc;
1595 }
1596
1597 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1598                 int16_t fw_vf_id)
1599 {
1600         int rc = 0;
1601         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1602         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1603
1604         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1605                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1606                 return rc;
1607         }
1608         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1609
1610         req.enables =
1611                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1612         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1613         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1614
1615         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1616
1617         HWRM_CHECK_RESULT();
1618
1619         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1620         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1621         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1622         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1623         vnic->mru = rte_le_to_cpu_16(resp->mru);
1624         vnic->func_default = rte_le_to_cpu_32(
1625                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1626         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1627                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1628         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1629                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1630         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1631                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1632         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1633                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1634         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1635                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1636
1637         HWRM_UNLOCK();
1638
1639         return rc;
1640 }
1641
1642 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1643                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1644 {
1645         int rc = 0;
1646         uint16_t ctx_id;
1647         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1648         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1649                                                 bp->hwrm_cmd_resp_addr;
1650
1651         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1652
1653         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1654         HWRM_CHECK_RESULT();
1655
1656         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1657         if (!BNXT_HAS_RING_GRPS(bp))
1658                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1659         else if (ctx_idx == 0)
1660                 vnic->rss_rule = ctx_id;
1661
1662         HWRM_UNLOCK();
1663
1664         return rc;
1665 }
1666
1667 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1668                             struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1669 {
1670         int rc = 0;
1671         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1672         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1673                                                 bp->hwrm_cmd_resp_addr;
1674
1675         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1676                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1677                 return rc;
1678         }
1679         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1680
1681         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1682
1683         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1684
1685         HWRM_CHECK_RESULT();
1686         HWRM_UNLOCK();
1687
1688         return rc;
1689 }
1690
1691 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1692 {
1693         int rc = 0;
1694         struct hwrm_vnic_free_input req = {.req_type = 0 };
1695         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1696
1697         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1698                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1699                 return rc;
1700         }
1701
1702         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1703
1704         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1705
1706         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1707
1708         HWRM_CHECK_RESULT();
1709         HWRM_UNLOCK();
1710
1711         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1712         /* Configure default VNIC again if necessary. */
1713         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1714                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1715
1716         return rc;
1717 }
1718
1719 static int
1720 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1721 {
1722         int i;
1723         int rc = 0;
1724         int nr_ctxs = bp->max_ring_grps;
1725         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1726         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1727
1728         if (!(vnic->rss_table && vnic->hash_type))
1729                 return 0;
1730
1731         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1732
1733         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1734         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1735         req.hash_mode_flags = vnic->hash_mode;
1736
1737         req.hash_key_tbl_addr =
1738             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1739
1740         for (i = 0; i < nr_ctxs; i++) {
1741                 req.ring_grp_tbl_addr =
1742                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1743                                          i * HW_HASH_INDEX_SIZE);
1744                 req.ring_table_pair_index = i;
1745                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1746
1747                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1748                                             BNXT_USE_CHIMP_MB);
1749
1750                 HWRM_CHECK_RESULT();
1751                 if (rc)
1752                         break;
1753         }
1754
1755         HWRM_UNLOCK();
1756
1757         return rc;
1758 }
1759
1760 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1761                            struct bnxt_vnic_info *vnic)
1762 {
1763         int rc = 0;
1764         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1765         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1766
1767         if (BNXT_CHIP_THOR(bp))
1768                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1769
1770         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1771
1772         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1773         req.hash_mode_flags = vnic->hash_mode;
1774
1775         req.ring_grp_tbl_addr =
1776             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1777         req.hash_key_tbl_addr =
1778             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1779         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1780         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1781
1782         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1783
1784         HWRM_CHECK_RESULT();
1785         HWRM_UNLOCK();
1786
1787         return rc;
1788 }
1789
1790 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1791                         struct bnxt_vnic_info *vnic)
1792 {
1793         int rc = 0;
1794         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1795         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1796         uint16_t size;
1797
1798         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1799                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1800                 return rc;
1801         }
1802
1803         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1804
1805         req.flags = rte_cpu_to_le_32(
1806                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1807
1808         req.enables = rte_cpu_to_le_32(
1809                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1810
1811         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1812         size -= RTE_PKTMBUF_HEADROOM;
1813
1814         req.jumbo_thresh = rte_cpu_to_le_16(size);
1815         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1816
1817         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1818
1819         HWRM_CHECK_RESULT();
1820         HWRM_UNLOCK();
1821
1822         return rc;
1823 }
1824
1825 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1826                         struct bnxt_vnic_info *vnic, bool enable)
1827 {
1828         int rc = 0;
1829         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1830         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1831
1832         if (BNXT_CHIP_THOR(bp))
1833                 return 0;
1834
1835         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1836
1837         if (enable) {
1838                 req.enables = rte_cpu_to_le_32(
1839                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1840                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1841                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1842                 req.flags = rte_cpu_to_le_32(
1843                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1844                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1845                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1846                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1847                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1848                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1849                 req.max_agg_segs = rte_cpu_to_le_16(5);
1850                 req.max_aggs =
1851                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1852                 req.min_agg_len = rte_cpu_to_le_32(512);
1853         }
1854         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1855
1856         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1857
1858         HWRM_CHECK_RESULT();
1859         HWRM_UNLOCK();
1860
1861         return rc;
1862 }
1863
1864 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1865 {
1866         struct hwrm_func_cfg_input req = {0};
1867         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1868         int rc;
1869
1870         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1871         req.enables = rte_cpu_to_le_32(
1872                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1873         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1874         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1875
1876         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1877
1878         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1879         HWRM_CHECK_RESULT();
1880         HWRM_UNLOCK();
1881
1882         bp->pf.vf_info[vf].random_mac = false;
1883
1884         return rc;
1885 }
1886
1887 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1888                                   uint64_t *dropped)
1889 {
1890         int rc = 0;
1891         struct hwrm_func_qstats_input req = {.req_type = 0};
1892         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1893
1894         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1895
1896         req.fid = rte_cpu_to_le_16(fid);
1897
1898         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1899
1900         HWRM_CHECK_RESULT();
1901
1902         if (dropped)
1903                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1904
1905         HWRM_UNLOCK();
1906
1907         return rc;
1908 }
1909
1910 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1911                           struct rte_eth_stats *stats)
1912 {
1913         int rc = 0;
1914         struct hwrm_func_qstats_input req = {.req_type = 0};
1915         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1916
1917         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1918
1919         req.fid = rte_cpu_to_le_16(fid);
1920
1921         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1922
1923         HWRM_CHECK_RESULT();
1924
1925         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1926         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1927         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1928         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1929         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1930         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1931
1932         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1933         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1934         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1935         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1936         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1937         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1938
1939         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1940         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1941         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1942
1943         HWRM_UNLOCK();
1944
1945         return rc;
1946 }
1947
1948 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1949 {
1950         int rc = 0;
1951         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1952         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1953
1954         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1955
1956         req.fid = rte_cpu_to_le_16(fid);
1957
1958         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1959
1960         HWRM_CHECK_RESULT();
1961         HWRM_UNLOCK();
1962
1963         return rc;
1964 }
1965
1966 /*
1967  * HWRM utility functions
1968  */
1969
1970 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1971 {
1972         unsigned int i;
1973         int rc = 0;
1974
1975         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1976                 struct bnxt_tx_queue *txq;
1977                 struct bnxt_rx_queue *rxq;
1978                 struct bnxt_cp_ring_info *cpr;
1979
1980                 if (i >= bp->rx_cp_nr_rings) {
1981                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1982                         cpr = txq->cp_ring;
1983                 } else {
1984                         rxq = bp->rx_queues[i];
1985                         cpr = rxq->cp_ring;
1986                 }
1987
1988                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1989                 if (rc)
1990                         return rc;
1991         }
1992         return 0;
1993 }
1994
1995 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1996 {
1997         int rc;
1998         unsigned int i;
1999         struct bnxt_cp_ring_info *cpr;
2000
2001         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2002
2003                 if (i >= bp->rx_cp_nr_rings) {
2004                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2005                 } else {
2006                         cpr = bp->rx_queues[i]->cp_ring;
2007                         if (BNXT_HAS_RING_GRPS(bp))
2008                                 bp->grp_info[i].fw_stats_ctx = -1;
2009                 }
2010                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2011                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2012                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2013                         if (rc)
2014                                 return rc;
2015                 }
2016         }
2017         return 0;
2018 }
2019
2020 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2021 {
2022         unsigned int i;
2023         int rc = 0;
2024
2025         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2026                 struct bnxt_tx_queue *txq;
2027                 struct bnxt_rx_queue *rxq;
2028                 struct bnxt_cp_ring_info *cpr;
2029
2030                 if (i >= bp->rx_cp_nr_rings) {
2031                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2032                         cpr = txq->cp_ring;
2033                 } else {
2034                         rxq = bp->rx_queues[i];
2035                         cpr = rxq->cp_ring;
2036                 }
2037
2038                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2039
2040                 if (rc)
2041                         return rc;
2042         }
2043         return rc;
2044 }
2045
2046 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2047 {
2048         uint16_t idx;
2049         uint32_t rc = 0;
2050
2051         if (!BNXT_HAS_RING_GRPS(bp))
2052                 return 0;
2053
2054         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2055
2056                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2057                         continue;
2058
2059                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2060
2061                 if (rc)
2062                         return rc;
2063         }
2064         return rc;
2065 }
2066
2067 static void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2068 {
2069         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2070
2071         bnxt_hwrm_ring_free(bp, cp_ring,
2072                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2073         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2074         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2075                                      sizeof(*cpr->cp_desc_ring));
2076         cpr->cp_raw_cons = 0;
2077 }
2078
2079 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2080 {
2081         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2082
2083         bnxt_hwrm_ring_free(bp, cp_ring,
2084                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2085         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2086         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2087                         sizeof(*cpr->cp_desc_ring));
2088         cpr->cp_raw_cons = 0;
2089 }
2090
2091 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2092 {
2093         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2094         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2095         struct bnxt_ring *ring = rxr->rx_ring_struct;
2096         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2097
2098         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2099                 bnxt_hwrm_ring_free(bp, ring,
2100                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2101                 ring->fw_ring_id = INVALID_HW_RING_ID;
2102                 if (BNXT_HAS_RING_GRPS(bp))
2103                         bp->grp_info[queue_index].rx_fw_ring_id =
2104                                                         INVALID_HW_RING_ID;
2105                 memset(rxr->rx_desc_ring, 0,
2106                        rxr->rx_ring_struct->ring_size *
2107                        sizeof(*rxr->rx_desc_ring));
2108                 memset(rxr->rx_buf_ring, 0,
2109                        rxr->rx_ring_struct->ring_size *
2110                        sizeof(*rxr->rx_buf_ring));
2111                 rxr->rx_prod = 0;
2112         }
2113         ring = rxr->ag_ring_struct;
2114         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2115                 bnxt_hwrm_ring_free(bp, ring,
2116                                     BNXT_CHIP_THOR(bp) ?
2117                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2118                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2119                 ring->fw_ring_id = INVALID_HW_RING_ID;
2120                 memset(rxr->ag_buf_ring, 0,
2121                        rxr->ag_ring_struct->ring_size *
2122                        sizeof(*rxr->ag_buf_ring));
2123                 rxr->ag_prod = 0;
2124                 if (BNXT_HAS_RING_GRPS(bp))
2125                         bp->grp_info[queue_index].ag_fw_ring_id =
2126                                                         INVALID_HW_RING_ID;
2127         }
2128         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2129                 bnxt_free_cp_ring(bp, cpr);
2130                 if (rxq->nq_ring)
2131                         bnxt_free_nq_ring(bp, rxq->nq_ring);
2132         }
2133
2134         if (BNXT_HAS_RING_GRPS(bp))
2135                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2136 }
2137
2138 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2139 {
2140         unsigned int i;
2141
2142         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2143                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2144                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2145                 struct bnxt_ring *ring = txr->tx_ring_struct;
2146                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2147
2148                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2149                         bnxt_hwrm_ring_free(bp, ring,
2150                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2151                         ring->fw_ring_id = INVALID_HW_RING_ID;
2152                         memset(txr->tx_desc_ring, 0,
2153                                         txr->tx_ring_struct->ring_size *
2154                                         sizeof(*txr->tx_desc_ring));
2155                         memset(txr->tx_buf_ring, 0,
2156                                         txr->tx_ring_struct->ring_size *
2157                                         sizeof(*txr->tx_buf_ring));
2158                         txr->tx_prod = 0;
2159                         txr->tx_cons = 0;
2160                 }
2161                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2162                         bnxt_free_cp_ring(bp, cpr);
2163                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2164                         if (txq->nq_ring)
2165                                 bnxt_free_nq_ring(bp, txq->nq_ring);
2166                 }
2167         }
2168
2169         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2170                 bnxt_free_hwrm_rx_ring(bp, i);
2171
2172         return 0;
2173 }
2174
2175 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2176 {
2177         uint16_t i;
2178         uint32_t rc = 0;
2179
2180         if (!BNXT_HAS_RING_GRPS(bp))
2181                 return 0;
2182
2183         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2184                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2185                 if (rc)
2186                         return rc;
2187         }
2188         return rc;
2189 }
2190
2191 void bnxt_free_hwrm_resources(struct bnxt *bp)
2192 {
2193         /* Release memzone */
2194         rte_free(bp->hwrm_cmd_resp_addr);
2195         rte_free(bp->hwrm_short_cmd_req_addr);
2196         bp->hwrm_cmd_resp_addr = NULL;
2197         bp->hwrm_short_cmd_req_addr = NULL;
2198         bp->hwrm_cmd_resp_dma_addr = 0;
2199         bp->hwrm_short_cmd_req_dma_addr = 0;
2200 }
2201
2202 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2203 {
2204         struct rte_pci_device *pdev = bp->pdev;
2205         char type[RTE_MEMZONE_NAMESIZE];
2206
2207         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2208                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2209         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2210         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2211         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2212         if (bp->hwrm_cmd_resp_addr == NULL)
2213                 return -ENOMEM;
2214         bp->hwrm_cmd_resp_dma_addr =
2215                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2216         if (bp->hwrm_cmd_resp_dma_addr == 0) {
2217                 PMD_DRV_LOG(ERR,
2218                         "unable to map response address to physical memory\n");
2219                 return -ENOMEM;
2220         }
2221         rte_spinlock_init(&bp->hwrm_lock);
2222
2223         return 0;
2224 }
2225
2226 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2227 {
2228         struct bnxt_filter_info *filter;
2229         int rc = 0;
2230
2231         STAILQ_FOREACH(filter, &vnic->filter, next) {
2232                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2233                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2234                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2235                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2236                 else
2237                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2238                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2239                 //if (rc)
2240                         //break;
2241         }
2242         return rc;
2243 }
2244
2245 static int
2246 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2247 {
2248         struct bnxt_filter_info *filter;
2249         struct rte_flow *flow;
2250         int rc = 0;
2251
2252         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2253                 filter = flow->filter;
2254                 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
2255                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2256                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2257                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2258                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2259                 else
2260                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2261
2262                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2263                 rte_free(flow);
2264                 //if (rc)
2265                         //break;
2266         }
2267         return rc;
2268 }
2269
2270 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2271 {
2272         struct bnxt_filter_info *filter;
2273         int rc = 0;
2274
2275         STAILQ_FOREACH(filter, &vnic->filter, next) {
2276                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2277                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2278                                                      filter);
2279                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2280                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2281                                                          filter);
2282                 else
2283                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2284                                                      filter);
2285                 if (rc)
2286                         break;
2287         }
2288         return rc;
2289 }
2290
2291 void bnxt_free_tunnel_ports(struct bnxt *bp)
2292 {
2293         if (bp->vxlan_port_cnt)
2294                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2295                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2296         bp->vxlan_port = 0;
2297         if (bp->geneve_port_cnt)
2298                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2299                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2300         bp->geneve_port = 0;
2301 }
2302
2303 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2304 {
2305         int i, j;
2306
2307         if (bp->vnic_info == NULL)
2308                 return;
2309
2310         /*
2311          * Cleanup VNICs in reverse order, to make sure the L2 filter
2312          * from vnic0 is last to be cleaned up.
2313          */
2314         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2315                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2316
2317                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2318
2319                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2320
2321                 if (BNXT_CHIP_THOR(bp)) {
2322                         for (j = 0; j < vnic->num_lb_ctxts; j++) {
2323                                 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2324                                                         vnic->fw_grp_ids[j]);
2325                                 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2326                         }
2327                         vnic->num_lb_ctxts = 0;
2328                 } else {
2329                         bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2330                         vnic->rss_rule = INVALID_HW_RING_ID;
2331                 }
2332
2333                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2334
2335                 bnxt_hwrm_vnic_free(bp, vnic);
2336
2337                 rte_free(vnic->fw_grp_ids);
2338         }
2339         /* Ring resources */
2340         bnxt_free_all_hwrm_rings(bp);
2341         bnxt_free_all_hwrm_ring_grps(bp);
2342         bnxt_free_all_hwrm_stat_ctxs(bp);
2343         bnxt_free_tunnel_ports(bp);
2344 }
2345
2346 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2347 {
2348         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2349
2350         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2351                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2352
2353         switch (conf_link_speed) {
2354         case ETH_LINK_SPEED_10M_HD:
2355         case ETH_LINK_SPEED_100M_HD:
2356                 /* FALLTHROUGH */
2357                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2358         }
2359         return hw_link_duplex;
2360 }
2361
2362 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2363 {
2364         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2365 }
2366
2367 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2368 {
2369         uint16_t eth_link_speed = 0;
2370
2371         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2372                 return ETH_LINK_SPEED_AUTONEG;
2373
2374         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2375         case ETH_LINK_SPEED_100M:
2376         case ETH_LINK_SPEED_100M_HD:
2377                 /* FALLTHROUGH */
2378                 eth_link_speed =
2379                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2380                 break;
2381         case ETH_LINK_SPEED_1G:
2382                 eth_link_speed =
2383                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2384                 break;
2385         case ETH_LINK_SPEED_2_5G:
2386                 eth_link_speed =
2387                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2388                 break;
2389         case ETH_LINK_SPEED_10G:
2390                 eth_link_speed =
2391                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2392                 break;
2393         case ETH_LINK_SPEED_20G:
2394                 eth_link_speed =
2395                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2396                 break;
2397         case ETH_LINK_SPEED_25G:
2398                 eth_link_speed =
2399                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2400                 break;
2401         case ETH_LINK_SPEED_40G:
2402                 eth_link_speed =
2403                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2404                 break;
2405         case ETH_LINK_SPEED_50G:
2406                 eth_link_speed =
2407                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2408                 break;
2409         case ETH_LINK_SPEED_100G:
2410                 eth_link_speed =
2411                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2412                 break;
2413         default:
2414                 PMD_DRV_LOG(ERR,
2415                         "Unsupported link speed %d; default to AUTO\n",
2416                         conf_link_speed);
2417                 break;
2418         }
2419         return eth_link_speed;
2420 }
2421
2422 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2423                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2424                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2425                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2426
2427 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2428 {
2429         uint32_t one_speed;
2430
2431         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2432                 return 0;
2433
2434         if (link_speed & ETH_LINK_SPEED_FIXED) {
2435                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2436
2437                 if (one_speed & (one_speed - 1)) {
2438                         PMD_DRV_LOG(ERR,
2439                                 "Invalid advertised speeds (%u) for port %u\n",
2440                                 link_speed, port_id);
2441                         return -EINVAL;
2442                 }
2443                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2444                         PMD_DRV_LOG(ERR,
2445                                 "Unsupported advertised speed (%u) for port %u\n",
2446                                 link_speed, port_id);
2447                         return -EINVAL;
2448                 }
2449         } else {
2450                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2451                         PMD_DRV_LOG(ERR,
2452                                 "Unsupported advertised speeds (%u) for port %u\n",
2453                                 link_speed, port_id);
2454                         return -EINVAL;
2455                 }
2456         }
2457         return 0;
2458 }
2459
2460 static uint16_t
2461 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2462 {
2463         uint16_t ret = 0;
2464
2465         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2466                 if (bp->link_info.support_speeds)
2467                         return bp->link_info.support_speeds;
2468                 link_speed = BNXT_SUPPORTED_SPEEDS;
2469         }
2470
2471         if (link_speed & ETH_LINK_SPEED_100M)
2472                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2473         if (link_speed & ETH_LINK_SPEED_100M_HD)
2474                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2475         if (link_speed & ETH_LINK_SPEED_1G)
2476                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2477         if (link_speed & ETH_LINK_SPEED_2_5G)
2478                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2479         if (link_speed & ETH_LINK_SPEED_10G)
2480                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2481         if (link_speed & ETH_LINK_SPEED_20G)
2482                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2483         if (link_speed & ETH_LINK_SPEED_25G)
2484                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2485         if (link_speed & ETH_LINK_SPEED_40G)
2486                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2487         if (link_speed & ETH_LINK_SPEED_50G)
2488                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2489         if (link_speed & ETH_LINK_SPEED_100G)
2490                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2491         return ret;
2492 }
2493
2494 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2495 {
2496         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2497
2498         switch (hw_link_speed) {
2499         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2500                 eth_link_speed = ETH_SPEED_NUM_100M;
2501                 break;
2502         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2503                 eth_link_speed = ETH_SPEED_NUM_1G;
2504                 break;
2505         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2506                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2507                 break;
2508         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2509                 eth_link_speed = ETH_SPEED_NUM_10G;
2510                 break;
2511         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2512                 eth_link_speed = ETH_SPEED_NUM_20G;
2513                 break;
2514         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2515                 eth_link_speed = ETH_SPEED_NUM_25G;
2516                 break;
2517         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2518                 eth_link_speed = ETH_SPEED_NUM_40G;
2519                 break;
2520         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2521                 eth_link_speed = ETH_SPEED_NUM_50G;
2522                 break;
2523         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2524                 eth_link_speed = ETH_SPEED_NUM_100G;
2525                 break;
2526         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2527         default:
2528                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2529                         hw_link_speed);
2530                 break;
2531         }
2532         return eth_link_speed;
2533 }
2534
2535 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2536 {
2537         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2538
2539         switch (hw_link_duplex) {
2540         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2541         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2542                 /* FALLTHROUGH */
2543                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2544                 break;
2545         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2546                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2547                 break;
2548         default:
2549                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2550                         hw_link_duplex);
2551                 break;
2552         }
2553         return eth_link_duplex;
2554 }
2555
2556 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2557 {
2558         int rc = 0;
2559         struct bnxt_link_info *link_info = &bp->link_info;
2560
2561         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2562         if (rc) {
2563                 PMD_DRV_LOG(ERR,
2564                         "Get link config failed with rc %d\n", rc);
2565                 goto exit;
2566         }
2567         if (link_info->link_speed)
2568                 link->link_speed =
2569                         bnxt_parse_hw_link_speed(link_info->link_speed);
2570         else
2571                 link->link_speed = ETH_SPEED_NUM_NONE;
2572         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2573         link->link_status = link_info->link_up;
2574         link->link_autoneg = link_info->auto_mode ==
2575                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2576                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2577 exit:
2578         return rc;
2579 }
2580
2581 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2582 {
2583         int rc = 0;
2584         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2585         struct bnxt_link_info link_req;
2586         uint16_t speed, autoneg;
2587
2588         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2589                 return 0;
2590
2591         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2592                         bp->eth_dev->data->port_id);
2593         if (rc)
2594                 goto error;
2595
2596         memset(&link_req, 0, sizeof(link_req));
2597         link_req.link_up = link_up;
2598         if (!link_up)
2599                 goto port_phy_cfg;
2600
2601         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2602         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2603         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2604         /* Autoneg can be done only when the FW allows */
2605         if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2606                                 bp->link_info.force_link_speed)) {
2607                 link_req.phy_flags |=
2608                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2609                 link_req.auto_link_speed_mask =
2610                         bnxt_parse_eth_link_speed_mask(bp,
2611                                                        dev_conf->link_speeds);
2612         } else {
2613                 if (bp->link_info.phy_type ==
2614                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2615                     bp->link_info.phy_type ==
2616                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2617                     bp->link_info.media_type ==
2618                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2619                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2620                         return -EINVAL;
2621                 }
2622
2623                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2624                 /* If user wants a particular speed try that first. */
2625                 if (speed)
2626                         link_req.link_speed = speed;
2627                 else if (bp->link_info.force_link_speed)
2628                         link_req.link_speed = bp->link_info.force_link_speed;
2629                 else
2630                         link_req.link_speed = bp->link_info.auto_link_speed;
2631         }
2632         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2633         link_req.auto_pause = bp->link_info.auto_pause;
2634         link_req.force_pause = bp->link_info.force_pause;
2635
2636 port_phy_cfg:
2637         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2638         if (rc) {
2639                 PMD_DRV_LOG(ERR,
2640                         "Set link config failed with rc %d\n", rc);
2641         }
2642
2643 error:
2644         return rc;
2645 }
2646
2647 /* JIRA 22088 */
2648 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2649 {
2650         struct hwrm_func_qcfg_input req = {0};
2651         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2652         uint16_t flags;
2653         int rc = 0;
2654
2655         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2656         req.fid = rte_cpu_to_le_16(0xffff);
2657
2658         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2659
2660         HWRM_CHECK_RESULT();
2661
2662         /* Hard Coded.. 0xfff VLAN ID mask */
2663         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2664         flags = rte_le_to_cpu_16(resp->flags);
2665         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2666                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2667
2668         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2669                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2670                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2671         }
2672
2673         if (mtu)
2674                 *mtu = resp->mtu;
2675
2676         switch (resp->port_partition_type) {
2677         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2678         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2679         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2680                 /* FALLTHROUGH */
2681                 bp->port_partition_type = resp->port_partition_type;
2682                 break;
2683         default:
2684                 bp->port_partition_type = 0;
2685                 break;
2686         }
2687
2688         HWRM_UNLOCK();
2689
2690         return rc;
2691 }
2692
2693 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2694                                    struct hwrm_func_qcaps_output *qcaps)
2695 {
2696         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2697         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2698                sizeof(qcaps->mac_address));
2699         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2700         qcaps->max_rx_rings = fcfg->num_rx_rings;
2701         qcaps->max_tx_rings = fcfg->num_tx_rings;
2702         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2703         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2704         qcaps->max_vfs = 0;
2705         qcaps->first_vf_id = 0;
2706         qcaps->max_vnics = fcfg->num_vnics;
2707         qcaps->max_decap_records = 0;
2708         qcaps->max_encap_records = 0;
2709         qcaps->max_tx_wm_flows = 0;
2710         qcaps->max_tx_em_flows = 0;
2711         qcaps->max_rx_wm_flows = 0;
2712         qcaps->max_rx_em_flows = 0;
2713         qcaps->max_flow_id = 0;
2714         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2715         qcaps->max_sp_tx_rings = 0;
2716         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2717 }
2718
2719 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2720 {
2721         struct hwrm_func_cfg_input req = {0};
2722         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2723         uint32_t enables;
2724         int rc;
2725
2726         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2727                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2728                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2729                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2730                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2731                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2732                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2733                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2734                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2735
2736         if (BNXT_HAS_RING_GRPS(bp)) {
2737                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2738                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2739         } else if (BNXT_HAS_NQ(bp)) {
2740                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2741                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2742         }
2743
2744         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2745         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2746         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2747                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2748                                    BNXT_NUM_VLANS);
2749         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2750         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2751         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2752         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2753         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2754         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2755         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2756         req.fid = rte_cpu_to_le_16(0xffff);
2757         req.enables = rte_cpu_to_le_32(enables);
2758
2759         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2760
2761         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2762
2763         HWRM_CHECK_RESULT();
2764         HWRM_UNLOCK();
2765
2766         return rc;
2767 }
2768
2769 static void populate_vf_func_cfg_req(struct bnxt *bp,
2770                                      struct hwrm_func_cfg_input *req,
2771                                      int num_vfs)
2772 {
2773         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2774                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2775                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2776                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2777                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2778                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2779                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2780                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2781                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2782                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2783
2784         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2785                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2786                                     BNXT_NUM_VLANS);
2787         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2788                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2789                                     BNXT_NUM_VLANS);
2790         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2791                                                 (num_vfs + 1));
2792         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2793         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2794                                                (num_vfs + 1));
2795         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2796         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2797         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2798         /* TODO: For now, do not support VMDq/RFS on VFs. */
2799         req->num_vnics = rte_cpu_to_le_16(1);
2800         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2801                                                  (num_vfs + 1));
2802 }
2803
2804 static void add_random_mac_if_needed(struct bnxt *bp,
2805                                      struct hwrm_func_cfg_input *cfg_req,
2806                                      int vf)
2807 {
2808         struct rte_ether_addr mac;
2809
2810         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2811                 return;
2812
2813         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2814                 cfg_req->enables |=
2815                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2816                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2817                 bp->pf.vf_info[vf].random_mac = true;
2818         } else {
2819                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2820                         RTE_ETHER_ADDR_LEN);
2821         }
2822 }
2823
2824 static void reserve_resources_from_vf(struct bnxt *bp,
2825                                       struct hwrm_func_cfg_input *cfg_req,
2826                                       int vf)
2827 {
2828         struct hwrm_func_qcaps_input req = {0};
2829         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2830         int rc;
2831
2832         /* Get the actual allocated values now */
2833         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2834         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2835         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2836
2837         if (rc) {
2838                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2839                 copy_func_cfg_to_qcaps(cfg_req, resp);
2840         } else if (resp->error_code) {
2841                 rc = rte_le_to_cpu_16(resp->error_code);
2842                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2843                 copy_func_cfg_to_qcaps(cfg_req, resp);
2844         }
2845
2846         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2847         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2848         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2849         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2850         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2851         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2852         /*
2853          * TODO: While not supporting VMDq with VFs, max_vnics is always
2854          * forced to 1 in this case
2855          */
2856         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2857         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2858
2859         HWRM_UNLOCK();
2860 }
2861
2862 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2863 {
2864         struct hwrm_func_qcfg_input req = {0};
2865         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2866         int rc;
2867
2868         /* Check for zero MAC address */
2869         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2870         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2871         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2872         if (rc) {
2873                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2874                 return -1;
2875         } else if (resp->error_code) {
2876                 rc = rte_le_to_cpu_16(resp->error_code);
2877                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2878                 return -1;
2879         }
2880         rc = rte_le_to_cpu_16(resp->vlan);
2881
2882         HWRM_UNLOCK();
2883
2884         return rc;
2885 }
2886
2887 static int update_pf_resource_max(struct bnxt *bp)
2888 {
2889         struct hwrm_func_qcfg_input req = {0};
2890         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2891         int rc;
2892
2893         /* And copy the allocated numbers into the pf struct */
2894         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2895         req.fid = rte_cpu_to_le_16(0xffff);
2896         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2897         HWRM_CHECK_RESULT();
2898
2899         /* Only TX ring value reflects actual allocation? TODO */
2900         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2901         bp->pf.evb_mode = resp->evb_mode;
2902
2903         HWRM_UNLOCK();
2904
2905         return rc;
2906 }
2907
2908 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2909 {
2910         int rc;
2911
2912         if (!BNXT_PF(bp)) {
2913                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2914                 return -1;
2915         }
2916
2917         rc = bnxt_hwrm_func_qcaps(bp);
2918         if (rc)
2919                 return rc;
2920
2921         bp->pf.func_cfg_flags &=
2922                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2923                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2924         bp->pf.func_cfg_flags |=
2925                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2926         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2927         rc = __bnxt_hwrm_func_qcaps(bp);
2928         return rc;
2929 }
2930
2931 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2932 {
2933         struct hwrm_func_cfg_input req = {0};
2934         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2935         int i;
2936         size_t sz;
2937         int rc = 0;
2938         size_t req_buf_sz;
2939
2940         if (!BNXT_PF(bp)) {
2941                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2942                 return -1;
2943         }
2944
2945         rc = bnxt_hwrm_func_qcaps(bp);
2946
2947         if (rc)
2948                 return rc;
2949
2950         bp->pf.active_vfs = num_vfs;
2951
2952         /*
2953          * First, configure the PF to only use one TX ring.  This ensures that
2954          * there are enough rings for all VFs.
2955          *
2956          * If we don't do this, when we call func_alloc() later, we will lock
2957          * extra rings to the PF that won't be available during func_cfg() of
2958          * the VFs.
2959          *
2960          * This has been fixed with firmware versions above 20.6.54
2961          */
2962         bp->pf.func_cfg_flags &=
2963                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2964                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2965         bp->pf.func_cfg_flags |=
2966                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2967         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2968         if (rc)
2969                 return rc;
2970
2971         /*
2972          * Now, create and register a buffer to hold forwarded VF requests
2973          */
2974         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2975         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2976                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2977         if (bp->pf.vf_req_buf == NULL) {
2978                 rc = -ENOMEM;
2979                 goto error_free;
2980         }
2981         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2982                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2983         for (i = 0; i < num_vfs; i++)
2984                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2985                                         (i * HWRM_MAX_REQ_LEN);
2986
2987         rc = bnxt_hwrm_func_buf_rgtr(bp);
2988         if (rc)
2989                 goto error_free;
2990
2991         populate_vf_func_cfg_req(bp, &req, num_vfs);
2992
2993         bp->pf.active_vfs = 0;
2994         for (i = 0; i < num_vfs; i++) {
2995                 add_random_mac_if_needed(bp, &req, i);
2996
2997                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2998                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2999                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3000                 rc = bnxt_hwrm_send_message(bp,
3001                                             &req,
3002                                             sizeof(req),
3003                                             BNXT_USE_CHIMP_MB);
3004
3005                 /* Clear enable flag for next pass */
3006                 req.enables &= ~rte_cpu_to_le_32(
3007                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3008
3009                 if (rc || resp->error_code) {
3010                         PMD_DRV_LOG(ERR,
3011                                 "Failed to initizlie VF %d\n", i);
3012                         PMD_DRV_LOG(ERR,
3013                                 "Not all VFs available. (%d, %d)\n",
3014                                 rc, resp->error_code);
3015                         HWRM_UNLOCK();
3016                         break;
3017                 }
3018
3019                 HWRM_UNLOCK();
3020
3021                 reserve_resources_from_vf(bp, &req, i);
3022                 bp->pf.active_vfs++;
3023                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3024         }
3025
3026         /*
3027          * Now configure the PF to use "the rest" of the resources
3028          * We're using STD_TX_RING_MODE here though which will limit the TX
3029          * rings.  This will allow QoS to function properly.  Not setting this
3030          * will cause PF rings to break bandwidth settings.
3031          */
3032         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3033         if (rc)
3034                 goto error_free;
3035
3036         rc = update_pf_resource_max(bp);
3037         if (rc)
3038                 goto error_free;
3039
3040         return rc;
3041
3042 error_free:
3043         bnxt_hwrm_func_buf_unrgtr(bp);
3044         return rc;
3045 }
3046
3047 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3048 {
3049         struct hwrm_func_cfg_input req = {0};
3050         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3051         int rc;
3052
3053         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3054
3055         req.fid = rte_cpu_to_le_16(0xffff);
3056         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3057         req.evb_mode = bp->pf.evb_mode;
3058
3059         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3060         HWRM_CHECK_RESULT();
3061         HWRM_UNLOCK();
3062
3063         return rc;
3064 }
3065
3066 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3067                                 uint8_t tunnel_type)
3068 {
3069         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3070         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3071         int rc = 0;
3072
3073         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3074         req.tunnel_type = tunnel_type;
3075         req.tunnel_dst_port_val = port;
3076         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3077         HWRM_CHECK_RESULT();
3078
3079         switch (tunnel_type) {
3080         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3081                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3082                 bp->vxlan_port = port;
3083                 break;
3084         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3085                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3086                 bp->geneve_port = port;
3087                 break;
3088         default:
3089                 break;
3090         }
3091
3092         HWRM_UNLOCK();
3093
3094         return rc;
3095 }
3096
3097 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3098                                 uint8_t tunnel_type)
3099 {
3100         struct hwrm_tunnel_dst_port_free_input req = {0};
3101         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3102         int rc = 0;
3103
3104         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3105
3106         req.tunnel_type = tunnel_type;
3107         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3108         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3109
3110         HWRM_CHECK_RESULT();
3111         HWRM_UNLOCK();
3112
3113         return rc;
3114 }
3115
3116 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3117                                         uint32_t flags)
3118 {
3119         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3120         struct hwrm_func_cfg_input req = {0};
3121         int rc;
3122
3123         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3124
3125         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3126         req.flags = rte_cpu_to_le_32(flags);
3127         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3128
3129         HWRM_CHECK_RESULT();
3130         HWRM_UNLOCK();
3131
3132         return rc;
3133 }
3134
3135 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3136 {
3137         uint32_t *flag = flagp;
3138
3139         vnic->flags = *flag;
3140 }
3141
3142 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3143 {
3144         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3145 }
3146
3147 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3148 {
3149         int rc = 0;
3150         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3151         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3152
3153         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3154
3155         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3156         req.req_buf_page_size = rte_cpu_to_le_16(
3157                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3158         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3159         req.req_buf_page_addr0 =
3160                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3161         if (req.req_buf_page_addr0 == 0) {
3162                 PMD_DRV_LOG(ERR,
3163                         "unable to map buffer address to physical memory\n");
3164                 return -ENOMEM;
3165         }
3166
3167         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3168
3169         HWRM_CHECK_RESULT();
3170         HWRM_UNLOCK();
3171
3172         return rc;
3173 }
3174
3175 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3176 {
3177         int rc = 0;
3178         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3179         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3180
3181         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3182
3183         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3184
3185         HWRM_CHECK_RESULT();
3186         HWRM_UNLOCK();
3187
3188         return rc;
3189 }
3190
3191 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3192 {
3193         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3194         struct hwrm_func_cfg_input req = {0};
3195         int rc;
3196
3197         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3198
3199         req.fid = rte_cpu_to_le_16(0xffff);
3200         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3201         req.enables = rte_cpu_to_le_32(
3202                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3203         req.async_event_cr = rte_cpu_to_le_16(
3204                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3205         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3206
3207         HWRM_CHECK_RESULT();
3208         HWRM_UNLOCK();
3209
3210         return rc;
3211 }
3212
3213 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3214 {
3215         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3216         struct hwrm_func_vf_cfg_input req = {0};
3217         int rc;
3218
3219         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3220
3221         req.enables = rte_cpu_to_le_32(
3222                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3223         req.async_event_cr = rte_cpu_to_le_16(
3224                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3225         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3226
3227         HWRM_CHECK_RESULT();
3228         HWRM_UNLOCK();
3229
3230         return rc;
3231 }
3232
3233 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3234 {
3235         struct hwrm_func_cfg_input req = {0};
3236         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3237         uint16_t dflt_vlan, fid;
3238         uint32_t func_cfg_flags;
3239         int rc = 0;
3240
3241         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3242
3243         if (is_vf) {
3244                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3245                 fid = bp->pf.vf_info[vf].fid;
3246                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3247         } else {
3248                 fid = rte_cpu_to_le_16(0xffff);
3249                 func_cfg_flags = bp->pf.func_cfg_flags;
3250                 dflt_vlan = bp->vlan;
3251         }
3252
3253         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3254         req.fid = rte_cpu_to_le_16(fid);
3255         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3256         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3257
3258         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3259
3260         HWRM_CHECK_RESULT();
3261         HWRM_UNLOCK();
3262
3263         return rc;
3264 }
3265
3266 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3267                         uint16_t max_bw, uint16_t enables)
3268 {
3269         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3270         struct hwrm_func_cfg_input req = {0};
3271         int rc;
3272
3273         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3274
3275         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3276         req.enables |= rte_cpu_to_le_32(enables);
3277         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3278         req.max_bw = rte_cpu_to_le_32(max_bw);
3279         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3280
3281         HWRM_CHECK_RESULT();
3282         HWRM_UNLOCK();
3283
3284         return rc;
3285 }
3286
3287 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3288 {
3289         struct hwrm_func_cfg_input req = {0};
3290         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3291         int rc = 0;
3292
3293         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3294
3295         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3296         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3297         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3298         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3299
3300         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3301
3302         HWRM_CHECK_RESULT();
3303         HWRM_UNLOCK();
3304
3305         return rc;
3306 }
3307
3308 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3309 {
3310         int rc;
3311
3312         if (BNXT_PF(bp))
3313                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3314         else
3315                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3316
3317         return rc;
3318 }
3319
3320 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3321                               void *encaped, size_t ec_size)
3322 {
3323         int rc = 0;
3324         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3325         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3326
3327         if (ec_size > sizeof(req.encap_request))
3328                 return -1;
3329
3330         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3331
3332         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3333         memcpy(req.encap_request, encaped, ec_size);
3334
3335         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3336
3337         HWRM_CHECK_RESULT();
3338         HWRM_UNLOCK();
3339
3340         return rc;
3341 }
3342
3343 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3344                                        struct rte_ether_addr *mac)
3345 {
3346         struct hwrm_func_qcfg_input req = {0};
3347         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3348         int rc;
3349
3350         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3351
3352         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3353         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3354
3355         HWRM_CHECK_RESULT();
3356
3357         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3358
3359         HWRM_UNLOCK();
3360
3361         return rc;
3362 }
3363
3364 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3365                             void *encaped, size_t ec_size)
3366 {
3367         int rc = 0;
3368         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3369         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3370
3371         if (ec_size > sizeof(req.encap_request))
3372                 return -1;
3373
3374         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3375
3376         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3377         memcpy(req.encap_request, encaped, ec_size);
3378
3379         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3380
3381         HWRM_CHECK_RESULT();
3382         HWRM_UNLOCK();
3383
3384         return rc;
3385 }
3386
3387 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3388                          struct rte_eth_stats *stats, uint8_t rx)
3389 {
3390         int rc = 0;
3391         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3392         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3393
3394         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3395
3396         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3397
3398         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3399
3400         HWRM_CHECK_RESULT();
3401
3402         if (rx) {
3403                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3404                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3405                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3406                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3407                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3408                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3409                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3410                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3411         } else {
3412                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3413                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3414                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3415                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3416                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3417                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3418         }
3419
3420
3421         HWRM_UNLOCK();
3422
3423         return rc;
3424 }
3425
3426 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3427 {
3428         struct hwrm_port_qstats_input req = {0};
3429         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3430         struct bnxt_pf_info *pf = &bp->pf;
3431         int rc;
3432
3433         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3434
3435         req.port_id = rte_cpu_to_le_16(pf->port_id);
3436         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3437         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3438         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3439
3440         HWRM_CHECK_RESULT();
3441         HWRM_UNLOCK();
3442
3443         return rc;
3444 }
3445
3446 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3447 {
3448         struct hwrm_port_clr_stats_input req = {0};
3449         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3450         struct bnxt_pf_info *pf = &bp->pf;
3451         int rc;
3452
3453         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3454         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3455             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3456                 return 0;
3457
3458         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3459
3460         req.port_id = rte_cpu_to_le_16(pf->port_id);
3461         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3462
3463         HWRM_CHECK_RESULT();
3464         HWRM_UNLOCK();
3465
3466         return rc;
3467 }
3468
3469 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3470 {
3471         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3472         struct hwrm_port_led_qcaps_input req = {0};
3473         int rc;
3474
3475         if (BNXT_VF(bp))
3476                 return 0;
3477
3478         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3479         req.port_id = bp->pf.port_id;
3480         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3481
3482         HWRM_CHECK_RESULT();
3483
3484         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3485                 unsigned int i;
3486
3487                 bp->num_leds = resp->num_leds;
3488                 memcpy(bp->leds, &resp->led0_id,
3489                         sizeof(bp->leds[0]) * bp->num_leds);
3490                 for (i = 0; i < bp->num_leds; i++) {
3491                         struct bnxt_led_info *led = &bp->leds[i];
3492
3493                         uint16_t caps = led->led_state_caps;
3494
3495                         if (!led->led_group_id ||
3496                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3497                                 bp->num_leds = 0;
3498                                 break;
3499                         }
3500                 }
3501         }
3502
3503         HWRM_UNLOCK();
3504
3505         return rc;
3506 }
3507
3508 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3509 {
3510         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3511         struct hwrm_port_led_cfg_input req = {0};
3512         struct bnxt_led_cfg *led_cfg;
3513         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3514         uint16_t duration = 0;
3515         int rc, i;
3516
3517         if (!bp->num_leds || BNXT_VF(bp))
3518                 return -EOPNOTSUPP;
3519
3520         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3521
3522         if (led_on) {
3523                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3524                 duration = rte_cpu_to_le_16(500);
3525         }
3526         req.port_id = bp->pf.port_id;
3527         req.num_leds = bp->num_leds;
3528         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3529         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3530                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3531                 led_cfg->led_id = bp->leds[i].led_id;
3532                 led_cfg->led_state = led_state;
3533                 led_cfg->led_blink_on = duration;
3534                 led_cfg->led_blink_off = duration;
3535                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3536         }
3537
3538         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3539
3540         HWRM_CHECK_RESULT();
3541         HWRM_UNLOCK();
3542
3543         return rc;
3544 }
3545
3546 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3547                                uint32_t *length)
3548 {
3549         int rc;
3550         struct hwrm_nvm_get_dir_info_input req = {0};
3551         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3552
3553         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3554
3555         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3556
3557         HWRM_CHECK_RESULT();
3558         HWRM_UNLOCK();
3559
3560         if (!rc) {
3561                 *entries = rte_le_to_cpu_32(resp->entries);
3562                 *length = rte_le_to_cpu_32(resp->entry_length);
3563         }
3564         return rc;
3565 }
3566
3567 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3568 {
3569         int rc;
3570         uint32_t dir_entries;
3571         uint32_t entry_length;
3572         uint8_t *buf;
3573         size_t buflen;
3574         rte_iova_t dma_handle;
3575         struct hwrm_nvm_get_dir_entries_input req = {0};
3576         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3577
3578         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3579         if (rc != 0)
3580                 return rc;
3581
3582         *data++ = dir_entries;
3583         *data++ = entry_length;
3584         len -= 2;
3585         memset(data, 0xff, len);
3586
3587         buflen = dir_entries * entry_length;
3588         buf = rte_malloc("nvm_dir", buflen, 0);
3589         rte_mem_lock_page(buf);
3590         if (buf == NULL)
3591                 return -ENOMEM;
3592         dma_handle = rte_mem_virt2iova(buf);
3593         if (dma_handle == 0) {
3594                 PMD_DRV_LOG(ERR,
3595                         "unable to map response address to physical memory\n");
3596                 return -ENOMEM;
3597         }
3598         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3599         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3600         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3601
3602         if (rc == 0)
3603                 memcpy(data, buf, len > buflen ? buflen : len);
3604
3605         rte_free(buf);
3606         HWRM_CHECK_RESULT();
3607         HWRM_UNLOCK();
3608
3609         return rc;
3610 }
3611
3612 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3613                              uint32_t offset, uint32_t length,
3614                              uint8_t *data)
3615 {
3616         int rc;
3617         uint8_t *buf;
3618         rte_iova_t dma_handle;
3619         struct hwrm_nvm_read_input req = {0};
3620         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3621
3622         buf = rte_malloc("nvm_item", length, 0);
3623         rte_mem_lock_page(buf);
3624         if (!buf)
3625                 return -ENOMEM;
3626
3627         dma_handle = rte_mem_virt2iova(buf);
3628         if (dma_handle == 0) {
3629                 PMD_DRV_LOG(ERR,
3630                         "unable to map response address to physical memory\n");
3631                 return -ENOMEM;
3632         }
3633         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3634         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3635         req.dir_idx = rte_cpu_to_le_16(index);
3636         req.offset = rte_cpu_to_le_32(offset);
3637         req.len = rte_cpu_to_le_32(length);
3638         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3639         if (rc == 0)
3640                 memcpy(data, buf, length);
3641
3642         rte_free(buf);
3643         HWRM_CHECK_RESULT();
3644         HWRM_UNLOCK();
3645
3646         return rc;
3647 }
3648
3649 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3650 {
3651         int rc;
3652         struct hwrm_nvm_erase_dir_entry_input req = {0};
3653         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3654
3655         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3656         req.dir_idx = rte_cpu_to_le_16(index);
3657         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3658         HWRM_CHECK_RESULT();
3659         HWRM_UNLOCK();
3660
3661         return rc;
3662 }
3663
3664
3665 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3666                           uint16_t dir_ordinal, uint16_t dir_ext,
3667                           uint16_t dir_attr, const uint8_t *data,
3668                           size_t data_len)
3669 {
3670         int rc;
3671         struct hwrm_nvm_write_input req = {0};
3672         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3673         rte_iova_t dma_handle;
3674         uint8_t *buf;
3675
3676         buf = rte_malloc("nvm_write", data_len, 0);
3677         rte_mem_lock_page(buf);
3678         if (!buf)
3679                 return -ENOMEM;
3680
3681         dma_handle = rte_mem_virt2iova(buf);
3682         if (dma_handle == 0) {
3683                 PMD_DRV_LOG(ERR,
3684                         "unable to map response address to physical memory\n");
3685                 return -ENOMEM;
3686         }
3687         memcpy(buf, data, data_len);
3688
3689         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3690
3691         req.dir_type = rte_cpu_to_le_16(dir_type);
3692         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3693         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3694         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3695         req.dir_data_length = rte_cpu_to_le_32(data_len);
3696         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3697
3698         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3699
3700         rte_free(buf);
3701         HWRM_CHECK_RESULT();
3702         HWRM_UNLOCK();
3703
3704         return rc;
3705 }
3706
3707 static void
3708 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3709 {
3710         uint32_t *count = cbdata;
3711
3712         *count = *count + 1;
3713 }
3714
3715 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3716                                      struct bnxt_vnic_info *vnic __rte_unused)
3717 {
3718         return 0;
3719 }
3720
3721 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3722 {
3723         uint32_t count = 0;
3724
3725         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3726             &count, bnxt_vnic_count_hwrm_stub);
3727
3728         return count;
3729 }
3730
3731 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3732                                         uint16_t *vnic_ids)
3733 {
3734         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3735         struct hwrm_func_vf_vnic_ids_query_output *resp =
3736                                                 bp->hwrm_cmd_resp_addr;
3737         int rc;
3738
3739         /* First query all VNIC ids */
3740         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3741
3742         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3743         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3744         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3745
3746         if (req.vnic_id_tbl_addr == 0) {
3747                 HWRM_UNLOCK();
3748                 PMD_DRV_LOG(ERR,
3749                 "unable to map VNIC ID table address to physical memory\n");
3750                 return -ENOMEM;
3751         }
3752         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3753         if (rc) {
3754                 HWRM_UNLOCK();
3755                 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3756                 return -1;
3757         } else if (resp->error_code) {
3758                 rc = rte_le_to_cpu_16(resp->error_code);
3759                 HWRM_UNLOCK();
3760                 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3761                 return -1;
3762         }
3763         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3764
3765         HWRM_UNLOCK();
3766
3767         return rc;
3768 }
3769
3770 /*
3771  * This function queries the VNIC IDs  for a specified VF. It then calls
3772  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3773  * Then it calls the hwrm_cb function to program this new vnic configuration.
3774  */
3775 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3776         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3777         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3778 {
3779         struct bnxt_vnic_info vnic;
3780         int rc = 0;
3781         int i, num_vnic_ids;
3782         uint16_t *vnic_ids;
3783         size_t vnic_id_sz;
3784         size_t sz;
3785
3786         /* First query all VNIC ids */
3787         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3788         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3789                         RTE_CACHE_LINE_SIZE);
3790         if (vnic_ids == NULL) {
3791                 rc = -ENOMEM;
3792                 return rc;
3793         }
3794         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3795                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3796
3797         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3798
3799         if (num_vnic_ids < 0)
3800                 return num_vnic_ids;
3801
3802         /* Retrieve VNIC, update bd_stall then update */
3803
3804         for (i = 0; i < num_vnic_ids; i++) {
3805                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3806                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3807                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3808                 if (rc)
3809                         break;
3810                 if (vnic.mru <= 4)      /* Indicates unallocated */
3811                         continue;
3812
3813                 vnic_cb(&vnic, cbdata);
3814
3815                 rc = hwrm_cb(bp, &vnic);
3816                 if (rc)
3817                         break;
3818         }
3819
3820         rte_free(vnic_ids);
3821
3822         return rc;
3823 }
3824
3825 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3826                                               bool on)
3827 {
3828         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3829         struct hwrm_func_cfg_input req = {0};
3830         int rc;
3831
3832         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3833
3834         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3835         req.enables |= rte_cpu_to_le_32(
3836                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3837         req.vlan_antispoof_mode = on ?
3838                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3839                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3840         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3841
3842         HWRM_CHECK_RESULT();
3843         HWRM_UNLOCK();
3844
3845         return rc;
3846 }
3847
3848 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3849 {
3850         struct bnxt_vnic_info vnic;
3851         uint16_t *vnic_ids;
3852         size_t vnic_id_sz;
3853         int num_vnic_ids, i;
3854         size_t sz;
3855         int rc;
3856
3857         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3858         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3859                         RTE_CACHE_LINE_SIZE);
3860         if (vnic_ids == NULL) {
3861                 rc = -ENOMEM;
3862                 return rc;
3863         }
3864
3865         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3866                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3867
3868         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3869         if (rc <= 0)
3870                 goto exit;
3871         num_vnic_ids = rc;
3872
3873         /*
3874          * Loop through to find the default VNIC ID.
3875          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3876          * by sending the hwrm_func_qcfg command to the firmware.
3877          */
3878         for (i = 0; i < num_vnic_ids; i++) {
3879                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3880                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3881                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3882                                         bp->pf.first_vf_id + vf);
3883                 if (rc)
3884                         goto exit;
3885                 if (vnic.func_default) {
3886                         rte_free(vnic_ids);
3887                         return vnic.fw_vnic_id;
3888                 }
3889         }
3890         /* Could not find a default VNIC. */
3891         PMD_DRV_LOG(ERR, "No default VNIC\n");
3892 exit:
3893         rte_free(vnic_ids);
3894         return -1;
3895 }
3896
3897 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3898                          uint16_t dst_id,
3899                          struct bnxt_filter_info *filter)
3900 {
3901         int rc = 0;
3902         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3903         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3904         uint32_t enables = 0;
3905
3906         if (filter->fw_em_filter_id != UINT64_MAX)
3907                 bnxt_hwrm_clear_em_filter(bp, filter);
3908
3909         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3910
3911         req.flags = rte_cpu_to_le_32(filter->flags);
3912
3913         enables = filter->enables |
3914               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3915         req.dst_id = rte_cpu_to_le_16(dst_id);
3916
3917         if (filter->ip_addr_type) {
3918                 req.ip_addr_type = filter->ip_addr_type;
3919                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3920         }
3921         if (enables &
3922             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3923                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3924         if (enables &
3925             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3926                 memcpy(req.src_macaddr, filter->src_macaddr,
3927                        RTE_ETHER_ADDR_LEN);
3928         if (enables &
3929             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3930                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3931                        RTE_ETHER_ADDR_LEN);
3932         if (enables &
3933             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3934                 req.ovlan_vid = filter->l2_ovlan;
3935         if (enables &
3936             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3937                 req.ivlan_vid = filter->l2_ivlan;
3938         if (enables &
3939             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3940                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3941         if (enables &
3942             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3943                 req.ip_protocol = filter->ip_protocol;
3944         if (enables &
3945             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3946                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3947         if (enables &
3948             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3949                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3950         if (enables &
3951             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3952                 req.src_port = rte_cpu_to_be_16(filter->src_port);
3953         if (enables &
3954             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3955                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3956         if (enables &
3957             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3958                 req.mirror_vnic_id = filter->mirror_vnic_id;
3959
3960         req.enables = rte_cpu_to_le_32(enables);
3961
3962         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3963
3964         HWRM_CHECK_RESULT();
3965
3966         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3967         HWRM_UNLOCK();
3968
3969         return rc;
3970 }
3971
3972 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3973 {
3974         int rc = 0;
3975         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3976         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3977
3978         if (filter->fw_em_filter_id == UINT64_MAX)
3979                 return 0;
3980
3981         PMD_DRV_LOG(ERR, "Clear EM filter\n");
3982         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
3983
3984         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3985
3986         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3987
3988         HWRM_CHECK_RESULT();
3989         HWRM_UNLOCK();
3990
3991         filter->fw_em_filter_id = UINT64_MAX;
3992         filter->fw_l2_filter_id = UINT64_MAX;
3993
3994         return 0;
3995 }
3996
3997 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3998                          uint16_t dst_id,
3999                          struct bnxt_filter_info *filter)
4000 {
4001         int rc = 0;
4002         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4003         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4004                                                 bp->hwrm_cmd_resp_addr;
4005         uint32_t enables = 0;
4006
4007         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4008                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4009
4010         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4011
4012         req.flags = rte_cpu_to_le_32(filter->flags);
4013
4014         enables = filter->enables |
4015               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4016         req.dst_id = rte_cpu_to_le_16(dst_id);
4017
4018
4019         if (filter->ip_addr_type) {
4020                 req.ip_addr_type = filter->ip_addr_type;
4021                 enables |=
4022                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4023         }
4024         if (enables &
4025             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4026                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4027         if (enables &
4028             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4029                 memcpy(req.src_macaddr, filter->src_macaddr,
4030                        RTE_ETHER_ADDR_LEN);
4031         //if (enables &
4032             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4033                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4034                        //RTE_ETHER_ADDR_LEN);
4035         if (enables &
4036             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4037                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4038         if (enables &
4039             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4040                 req.ip_protocol = filter->ip_protocol;
4041         if (enables &
4042             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4043                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4044         if (enables &
4045             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4046                 req.src_ipaddr_mask[0] =
4047                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4048         if (enables &
4049             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4050                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4051         if (enables &
4052             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4053                 req.dst_ipaddr_mask[0] =
4054                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4055         if (enables &
4056             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4057                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4058         if (enables &
4059             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4060                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4061         if (enables &
4062             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4063                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4064         if (enables &
4065             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4066                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4067         if (enables &
4068             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4069                 req.mirror_vnic_id = filter->mirror_vnic_id;
4070
4071         req.enables = rte_cpu_to_le_32(enables);
4072
4073         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4074
4075         HWRM_CHECK_RESULT();
4076
4077         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4078         HWRM_UNLOCK();
4079
4080         return rc;
4081 }
4082
4083 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4084                                 struct bnxt_filter_info *filter)
4085 {
4086         int rc = 0;
4087         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4088         struct hwrm_cfa_ntuple_filter_free_output *resp =
4089                                                 bp->hwrm_cmd_resp_addr;
4090
4091         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4092                 return 0;
4093
4094         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4095
4096         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4097
4098         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4099
4100         HWRM_CHECK_RESULT();
4101         HWRM_UNLOCK();
4102
4103         filter->fw_ntuple_filter_id = UINT64_MAX;
4104
4105         return 0;
4106 }
4107
4108 static int
4109 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4110 {
4111         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4112         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4113         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4114         int nr_ctxs = bp->max_ring_grps;
4115         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4116         uint16_t *ring_tbl = vnic->rss_table;
4117         int max_rings = bp->rx_nr_rings;
4118         int i, j, k, cnt;
4119         int rc = 0;
4120
4121         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4122
4123         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4124         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4125         req.hash_mode_flags = vnic->hash_mode;
4126
4127         req.ring_grp_tbl_addr =
4128             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
4129         req.hash_key_tbl_addr =
4130             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4131
4132         for (i = 0, k = 0; i < nr_ctxs; i++) {
4133                 struct bnxt_rx_ring_info *rxr;
4134                 struct bnxt_cp_ring_info *cpr;
4135
4136                 req.ring_table_pair_index = i;
4137                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4138
4139                 for (j = 0; j < 64; j++) {
4140                         uint16_t ring_id;
4141
4142                         /* Find next active ring. */
4143                         for (cnt = 0; cnt < max_rings; cnt++) {
4144                                 if (rx_queue_state[k] !=
4145                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4146                                         break;
4147                                 if (++k == max_rings)
4148                                         k = 0;
4149                         }
4150
4151                         /* Return if no rings are active. */
4152                         if (cnt == max_rings)
4153                                 return 0;
4154
4155                         /* Add rx/cp ring pair to RSS table. */
4156                         rxr = rxqs[k]->rx_ring;
4157                         cpr = rxqs[k]->cp_ring;
4158
4159                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4160                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4161                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4162                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4163
4164                         if (++k == max_rings)
4165                                 k = 0;
4166                 }
4167                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4168                                             BNXT_USE_CHIMP_MB);
4169
4170                 HWRM_CHECK_RESULT();
4171                 if (rc)
4172                         break;
4173         }
4174
4175         HWRM_UNLOCK();
4176
4177         return rc;
4178 }
4179
4180 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4181 {
4182         unsigned int rss_idx, fw_idx, i;
4183
4184         if (!(vnic->rss_table && vnic->hash_type))
4185                 return 0;
4186
4187         if (BNXT_CHIP_THOR(bp))
4188                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4189
4190         /*
4191          * Fill the RSS hash & redirection table with
4192          * ring group ids for all VNICs
4193          */
4194         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4195                 rss_idx++, fw_idx++) {
4196                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4197                         fw_idx %= bp->rx_cp_nr_rings;
4198                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4199                                 break;
4200                         fw_idx++;
4201                 }
4202                 if (i == bp->rx_cp_nr_rings)
4203                         return 0;
4204                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4205         }
4206         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4207 }
4208
4209 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4210         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4211 {
4212         uint16_t flags;
4213
4214         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4215
4216         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4217         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4218
4219         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4220         req->num_cmpl_dma_aggr_during_int =
4221                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4222
4223         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4224
4225         /* min timer set to 1/2 of interrupt timer */
4226         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4227
4228         /* buf timer set to 1/4 of interrupt timer */
4229         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4230
4231         req->cmpl_aggr_dma_tmr_during_int =
4232                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4233
4234         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4235                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4236         req->flags = rte_cpu_to_le_16(flags);
4237 }
4238
4239 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4240                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4241 {
4242         struct hwrm_ring_aggint_qcaps_input req = {0};
4243         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4244         uint32_t enables;
4245         uint16_t flags;
4246         int rc;
4247
4248         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4249         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4250         if (rc)
4251                 goto out;
4252
4253         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4254         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4255
4256         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4257                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4258         agg_req->flags = rte_cpu_to_le_16(flags);
4259         enables =
4260          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4261          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4262         agg_req->enables = rte_cpu_to_le_32(enables);
4263
4264 out:
4265         HWRM_CHECK_RESULT();
4266         HWRM_UNLOCK();
4267         return rc;
4268 }
4269
4270 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4271                         struct bnxt_coal *coal, uint16_t ring_id)
4272 {
4273         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4274         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4275                                                 bp->hwrm_cmd_resp_addr;
4276         int rc;
4277
4278         /* Set ring coalesce parameters only for 100G NICs */
4279         if (BNXT_CHIP_THOR(bp)) {
4280                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4281                         return -1;
4282         } else if (bnxt_stratus_device(bp)) {
4283                 bnxt_hwrm_set_coal_params(coal, &req);
4284         } else {
4285                 return 0;
4286         }
4287
4288         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4289         req.ring_id = rte_cpu_to_le_16(ring_id);
4290         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4291         HWRM_CHECK_RESULT();
4292         HWRM_UNLOCK();
4293         return 0;
4294 }
4295
4296 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4297 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4298 {
4299         struct hwrm_func_backing_store_qcaps_input req = {0};
4300         struct hwrm_func_backing_store_qcaps_output *resp =
4301                 bp->hwrm_cmd_resp_addr;
4302         int rc;
4303
4304         if (!BNXT_CHIP_THOR(bp) ||
4305             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4306             BNXT_VF(bp) ||
4307             bp->ctx)
4308                 return 0;
4309
4310         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4311         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4312         HWRM_CHECK_RESULT_SILENT();
4313
4314         if (!rc) {
4315                 struct bnxt_ctx_pg_info *ctx_pg;
4316                 struct bnxt_ctx_mem_info *ctx;
4317                 int total_alloc_len;
4318                 int i;
4319
4320                 total_alloc_len = sizeof(*ctx);
4321                 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4322                                  RTE_CACHE_LINE_SIZE);
4323                 if (!ctx) {
4324                         rc = -ENOMEM;
4325                         goto ctx_err;
4326                 }
4327                 memset(ctx, 0, total_alloc_len);
4328
4329                 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4330                                     sizeof(*ctx_pg) * BNXT_MAX_Q,
4331                                     RTE_CACHE_LINE_SIZE);
4332                 if (!ctx_pg) {
4333                         rc = -ENOMEM;
4334                         goto ctx_err;
4335                 }
4336                 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4337                         ctx->tqm_mem[i] = ctx_pg;
4338
4339                 bp->ctx = ctx;
4340                 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4341                 ctx->qp_min_qp1_entries =
4342                         rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4343                 ctx->qp_max_l2_entries =
4344                         rte_le_to_cpu_16(resp->qp_max_l2_entries);
4345                 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4346                 ctx->srq_max_l2_entries =
4347                         rte_le_to_cpu_16(resp->srq_max_l2_entries);
4348                 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4349                 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4350                 ctx->cq_max_l2_entries =
4351                         rte_le_to_cpu_16(resp->cq_max_l2_entries);
4352                 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4353                 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4354                 ctx->vnic_max_vnic_entries =
4355                         rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4356                 ctx->vnic_max_ring_table_entries =
4357                         rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4358                 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4359                 ctx->stat_max_entries =
4360                         rte_le_to_cpu_32(resp->stat_max_entries);
4361                 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4362                 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4363                 ctx->tqm_min_entries_per_ring =
4364                         rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4365                 ctx->tqm_max_entries_per_ring =
4366                         rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4367                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4368                 if (!ctx->tqm_entries_multiple)
4369                         ctx->tqm_entries_multiple = 1;
4370                 ctx->mrav_max_entries =
4371                         rte_le_to_cpu_32(resp->mrav_max_entries);
4372                 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4373                 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4374                 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4375         } else {
4376                 rc = 0;
4377         }
4378 ctx_err:
4379         HWRM_UNLOCK();
4380         return rc;
4381 }
4382
4383 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4384 {
4385         struct hwrm_func_backing_store_cfg_input req = {0};
4386         struct hwrm_func_backing_store_cfg_output *resp =
4387                 bp->hwrm_cmd_resp_addr;
4388         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4389         struct bnxt_ctx_pg_info *ctx_pg;
4390         uint32_t *num_entries;
4391         uint64_t *pg_dir;
4392         uint8_t *pg_attr;
4393         uint32_t ena;
4394         int i, rc;
4395
4396         if (!ctx)
4397                 return 0;
4398
4399         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4400         req.enables = rte_cpu_to_le_32(enables);
4401
4402         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4403                 ctx_pg = &ctx->qp_mem;
4404                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4405                 req.qp_num_qp1_entries =
4406                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4407                 req.qp_num_l2_entries =
4408                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4409                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4410                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4411                                       &req.qpc_pg_size_qpc_lvl,
4412                                       &req.qpc_page_dir);
4413         }
4414
4415         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4416                 ctx_pg = &ctx->srq_mem;
4417                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4418                 req.srq_num_l2_entries =
4419                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4420                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4421                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4422                                       &req.srq_pg_size_srq_lvl,
4423                                       &req.srq_page_dir);
4424         }
4425
4426         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4427                 ctx_pg = &ctx->cq_mem;
4428                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4429                 req.cq_num_l2_entries =
4430                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4431                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4432                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4433                                       &req.cq_pg_size_cq_lvl,
4434                                       &req.cq_page_dir);
4435         }
4436
4437         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4438                 ctx_pg = &ctx->vnic_mem;
4439                 req.vnic_num_vnic_entries =
4440                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4441                 req.vnic_num_ring_table_entries =
4442                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4443                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4444                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4445                                       &req.vnic_pg_size_vnic_lvl,
4446                                       &req.vnic_page_dir);
4447         }
4448
4449         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4450                 ctx_pg = &ctx->stat_mem;
4451                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4452                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4453                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4454                                       &req.stat_pg_size_stat_lvl,
4455                                       &req.stat_page_dir);
4456         }
4457
4458         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4459         num_entries = &req.tqm_sp_num_entries;
4460         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4461         pg_dir = &req.tqm_sp_page_dir;
4462         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4463         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4464                 if (!(enables & ena))
4465                         continue;
4466
4467                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4468
4469                 ctx_pg = ctx->tqm_mem[i];
4470                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4471                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4472         }
4473
4474         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4475         HWRM_CHECK_RESULT();
4476         HWRM_UNLOCK();
4477         if (rc)
4478                 rc = -EIO;
4479         return rc;
4480 }
4481
4482 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4483 {
4484         struct hwrm_port_qstats_ext_input req = {0};
4485         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4486         struct bnxt_pf_info *pf = &bp->pf;
4487         int rc;
4488
4489         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4490               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4491                 return 0;
4492
4493         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4494
4495         req.port_id = rte_cpu_to_le_16(pf->port_id);
4496         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4497                 req.tx_stat_host_addr =
4498                         rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4499                 req.tx_stat_size =
4500                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4501         }
4502         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4503                 req.rx_stat_host_addr =
4504                         rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4505                 req.rx_stat_size =
4506                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4507         }
4508         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4509
4510         if (rc) {
4511                 bp->fw_rx_port_stats_ext_size = 0;
4512                 bp->fw_tx_port_stats_ext_size = 0;
4513         } else {
4514                 bp->fw_rx_port_stats_ext_size =
4515                         rte_le_to_cpu_16(resp->rx_stat_size);
4516                 bp->fw_tx_port_stats_ext_size =
4517                         rte_le_to_cpu_16(resp->tx_stat_size);
4518         }
4519
4520         HWRM_CHECK_RESULT();
4521         HWRM_UNLOCK();
4522
4523         return rc;
4524 }
4525
4526 int
4527 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4528 {
4529         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4530         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4531                 bp->hwrm_cmd_resp_addr;
4532         int rc = 0;
4533
4534         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_KONG(bp));
4535         req.tunnel_type = type;
4536         req.dest_fid = bp->fw_fid;
4537         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4538         HWRM_CHECK_RESULT();
4539
4540         HWRM_UNLOCK();
4541
4542         return rc;
4543 }
4544
4545 int
4546 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4547 {
4548         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4549         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4550                 bp->hwrm_cmd_resp_addr;
4551         int rc = 0;
4552
4553         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_KONG(bp));
4554         req.tunnel_type = type;
4555         req.dest_fid = bp->fw_fid;
4556         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4557         HWRM_CHECK_RESULT();
4558
4559         HWRM_UNLOCK();
4560
4561         return rc;
4562 }
4563
4564 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4565 {
4566         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4567         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4568                 bp->hwrm_cmd_resp_addr;
4569         int rc = 0;
4570
4571         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_KONG(bp));
4572         req.src_fid = bp->fw_fid;
4573         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4574         HWRM_CHECK_RESULT();
4575
4576         if (type)
4577                 *type = resp->tunnel_mask;
4578
4579         HWRM_UNLOCK();
4580
4581         return rc;
4582 }
4583
4584 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4585                                    uint16_t *dst_fid)
4586 {
4587         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4588         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4589                 bp->hwrm_cmd_resp_addr;
4590         int rc = 0;
4591
4592         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_KONG(bp));
4593         req.src_fid = bp->fw_fid;
4594         req.tunnel_type = tun_type;
4595         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4596         HWRM_CHECK_RESULT();
4597
4598         if (dst_fid)
4599                 *dst_fid = resp->dest_fid;
4600
4601         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4602
4603         HWRM_UNLOCK();
4604
4605         return rc;
4606 }