1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SPEC_CODE_1_8_3 0x10803
31 #define HWRM_VERSION_1_9_1 0x10901
32 #define HWRM_VERSION_1_9_2 0x10903
34 struct bnxt_plcmodes_cfg {
36 uint16_t jumbo_thresh;
38 uint16_t hds_threshold;
41 static int page_getenum(size_t size)
57 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
58 return sizeof(void *) * 8 - 1;
61 static int page_roundup(size_t size)
63 return 1 << page_getenum(size);
66 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
70 if (rmem->nr_pages > 1) {
72 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
74 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
79 * HWRM Functions (sent to HWRM)
80 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
81 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
82 * command was failed by the ChiMP.
85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
86 uint32_t msg_len, bool use_kong_mb)
89 struct input *req = msg;
90 struct output *resp = bp->hwrm_cmd_resp_addr;
94 uint16_t max_req_len = bp->max_req_len;
95 struct hwrm_short_input short_input = { 0 };
96 uint16_t bar_offset = use_kong_mb ?
97 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
98 uint16_t mb_trigger_offset = use_kong_mb ?
99 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
101 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
102 msg_len > bp->max_req_len) {
103 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
105 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
106 memcpy(short_cmd_req, req, msg_len);
108 short_input.req_type = rte_cpu_to_le_16(req->req_type);
109 short_input.signature = rte_cpu_to_le_16(
110 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
111 short_input.size = rte_cpu_to_le_16(msg_len);
112 short_input.req_addr =
113 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
115 data = (uint32_t *)&short_input;
116 msg_len = sizeof(short_input);
118 /* Sync memory write before updating doorbell */
121 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
124 /* Write request msg to hwrm channel */
125 for (i = 0; i < msg_len; i += 4) {
126 bar = (uint8_t *)bp->bar0 + bar_offset + i;
127 rte_write32(*data, bar);
131 /* Zero the rest of the request space */
132 for (; i < max_req_len; i += 4) {
133 bar = (uint8_t *)bp->bar0 + bar_offset + i;
137 /* Ring channel doorbell */
138 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
141 /* Poll for the valid bit */
142 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
143 /* Sanity check on the resp->resp_len */
145 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
146 /* Last byte of resp contains the valid key */
147 valid = (uint8_t *)resp + resp->resp_len - 1;
148 if (*valid == HWRM_RESP_VALID_KEY)
154 if (i >= HWRM_CMD_TIMEOUT) {
155 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
163 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
164 * spinlock, and does initial processing.
166 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
167 * releases the spinlock only if it returns. If the regular int return codes
168 * are not used by the function, HWRM_CHECK_RESULT() should not be used
169 * directly, rather it should be copied and modified to suit the function.
171 * HWRM_UNLOCK() must be called after all response processing is completed.
173 #define HWRM_PREP(req, type, kong) do { \
174 rte_spinlock_lock(&bp->hwrm_lock); \
175 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
176 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
177 req.cmpl_ring = rte_cpu_to_le_16(-1); \
178 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
179 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
180 req.target_id = rte_cpu_to_le_16(0xffff); \
181 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
184 #define HWRM_CHECK_RESULT_SILENT() do {\
186 rte_spinlock_unlock(&bp->hwrm_lock); \
189 if (resp->error_code) { \
190 rc = rte_le_to_cpu_16(resp->error_code); \
191 rte_spinlock_unlock(&bp->hwrm_lock); \
196 #define HWRM_CHECK_RESULT() do {\
198 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
199 rte_spinlock_unlock(&bp->hwrm_lock); \
200 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
206 if (resp->error_code) { \
207 rc = rte_le_to_cpu_16(resp->error_code); \
208 if (resp->resp_len >= 16) { \
209 struct hwrm_err_output *tmp_hwrm_err_op = \
212 "error %d:%d:%08x:%04x\n", \
213 rc, tmp_hwrm_err_op->cmd_err, \
215 tmp_hwrm_err_op->opaque_0), \
217 tmp_hwrm_err_op->opaque_1)); \
219 PMD_DRV_LOG(ERR, "error %d\n", rc); \
221 rte_spinlock_unlock(&bp->hwrm_lock); \
222 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
230 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
232 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
235 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
236 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
238 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
239 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
242 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
250 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
251 struct bnxt_vnic_info *vnic,
253 struct bnxt_vlan_table_entry *vlan_table)
256 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
257 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
260 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
263 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
264 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
266 /* FIXME add multicast flag, when multicast adding options is supported
269 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
270 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
271 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
272 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
273 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
274 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
275 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
276 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
277 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
278 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
279 if (vnic->mc_addr_cnt) {
280 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
281 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
282 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
285 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
286 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
287 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
288 rte_mem_virt2iova(vlan_table));
289 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
291 req.mask = rte_cpu_to_le_32(mask);
293 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
301 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
303 struct bnxt_vlan_antispoof_table_entry *vlan_table)
306 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
307 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
308 bp->hwrm_cmd_resp_addr;
311 * Older HWRM versions did not support this command, and the set_rx_mask
312 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
313 * removed from set_rx_mask call, and this command was added.
315 * This command is also present from 1.7.8.11 and higher,
318 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
319 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
320 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
325 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
326 req.fid = rte_cpu_to_le_16(fid);
328 req.vlan_tag_mask_tbl_addr =
329 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
330 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
332 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
340 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
341 struct bnxt_filter_info *filter)
344 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
345 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
347 if (filter->fw_l2_filter_id == UINT64_MAX)
350 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
352 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
354 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
359 filter->fw_l2_filter_id = UINT64_MAX;
364 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
366 struct bnxt_filter_info *filter)
369 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
370 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
371 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
372 const struct rte_eth_vmdq_rx_conf *conf =
373 &dev_conf->rx_adv_conf.vmdq_rx_conf;
374 uint32_t enables = 0;
375 uint16_t j = dst_id - 1;
377 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
378 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
379 conf->pool_map[j].pools & (1UL << j)) {
381 "Add vlan %u to vmdq pool %u\n",
382 conf->pool_map[j].vlan_id, j);
384 filter->l2_ivlan = conf->pool_map[j].vlan_id;
386 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
387 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
390 if (filter->fw_l2_filter_id != UINT64_MAX)
391 bnxt_hwrm_clear_l2_filter(bp, filter);
393 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
395 req.flags = rte_cpu_to_le_32(filter->flags);
397 rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
399 enables = filter->enables |
400 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
401 req.dst_id = rte_cpu_to_le_16(dst_id);
404 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
405 memcpy(req.l2_addr, filter->l2_addr,
408 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
409 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
412 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
413 req.l2_ovlan = filter->l2_ovlan;
415 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
416 req.l2_ivlan = filter->l2_ivlan;
418 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
419 req.l2_ovlan_mask = filter->l2_ovlan_mask;
421 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
422 req.l2_ivlan_mask = filter->l2_ivlan_mask;
423 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
424 req.src_id = rte_cpu_to_le_32(filter->src_id);
425 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
426 req.src_type = filter->src_type;
428 req.enables = rte_cpu_to_le_32(enables);
430 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
434 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
440 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
442 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
443 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
450 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
453 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
456 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
457 if (ptp->tx_tstamp_en)
458 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
461 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
462 req.flags = rte_cpu_to_le_32(flags);
463 req.enables = rte_cpu_to_le_32
464 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
465 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
467 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
473 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
476 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
477 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
478 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
480 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
484 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
486 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
488 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
492 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
495 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
499 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
500 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
501 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
502 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
503 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
504 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
505 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
506 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
507 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
508 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
509 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
510 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
511 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
512 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
513 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
514 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
515 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
516 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
524 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
527 struct hwrm_func_qcaps_input req = {.req_type = 0 };
528 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
529 uint16_t new_max_vfs;
533 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
535 req.fid = rte_cpu_to_le_16(0xffff);
537 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
541 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
542 flags = rte_le_to_cpu_32(resp->flags);
544 bp->pf.port_id = resp->port_id;
545 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
546 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
547 new_max_vfs = bp->pdev->max_vfs;
548 if (new_max_vfs != bp->pf.max_vfs) {
550 rte_free(bp->pf.vf_info);
551 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
552 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
553 bp->pf.max_vfs = new_max_vfs;
554 for (i = 0; i < new_max_vfs; i++) {
555 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
556 bp->pf.vf_info[i].vlan_table =
557 rte_zmalloc("VF VLAN table",
560 if (bp->pf.vf_info[i].vlan_table == NULL)
562 "Fail to alloc VLAN table for VF %d\n",
566 bp->pf.vf_info[i].vlan_table);
567 bp->pf.vf_info[i].vlan_as_table =
568 rte_zmalloc("VF VLAN AS table",
571 if (bp->pf.vf_info[i].vlan_as_table == NULL)
573 "Alloc VLAN AS table for VF %d fail\n",
577 bp->pf.vf_info[i].vlan_as_table);
578 STAILQ_INIT(&bp->pf.vf_info[i].filter);
583 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
584 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
585 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
586 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
587 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
588 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
589 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
590 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
592 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
593 /* TODO: For now, do not support VMDq/RFS on VFs. */
598 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
602 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
604 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
605 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
606 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
607 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
609 bnxt_hwrm_ptp_qcfg(bp);
613 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
614 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
621 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
625 rc = __bnxt_hwrm_func_qcaps(bp);
626 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
627 rc = bnxt_alloc_ctx_mem(bp);
631 rc = bnxt_hwrm_func_resc_qcaps(bp);
633 bp->flags |= BNXT_FLAG_NEW_RM;
639 int bnxt_hwrm_func_reset(struct bnxt *bp)
642 struct hwrm_func_reset_input req = {.req_type = 0 };
643 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
645 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
647 req.enables = rte_cpu_to_le_32(0);
649 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
657 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
660 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
661 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
663 if (bp->flags & BNXT_FLAG_REGISTERED)
666 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
667 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
668 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
669 req.ver_maj = RTE_VER_YEAR;
670 req.ver_min = RTE_VER_MONTH;
671 req.ver_upd = RTE_VER_MINOR;
674 req.enables |= rte_cpu_to_le_32(
675 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
676 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
677 RTE_MIN(sizeof(req.vf_req_fwd),
678 sizeof(bp->pf.vf_req_fwd)));
681 * PF can sniff HWRM API issued by VF. This can be set up by
682 * linux driver and inherited by the DPDK PF driver. Clear
683 * this HWRM sniffer list in FW because DPDK PF driver does
687 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
690 req.async_event_fwd[0] |=
691 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
692 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
693 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
694 req.async_event_fwd[1] |=
695 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
696 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
698 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
703 bp->flags |= BNXT_FLAG_REGISTERED;
708 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
710 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
713 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
716 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
721 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
722 struct hwrm_func_vf_cfg_input req = {0};
724 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
726 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
727 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
728 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
729 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
730 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
732 if (BNXT_HAS_RING_GRPS(bp)) {
733 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
734 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
737 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
738 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
739 AGG_RING_MULTIPLIER);
740 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
742 BNXT_NUM_ASYNC_CPR(bp));
743 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
745 BNXT_NUM_ASYNC_CPR(bp));
746 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
747 if (bp->vf_resv_strategy ==
748 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
749 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
750 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
751 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
752 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
753 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
754 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
758 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
759 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
760 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
761 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
762 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
763 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
765 if (test && BNXT_HAS_RING_GRPS(bp))
766 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
768 req.flags = rte_cpu_to_le_32(flags);
769 req.enables |= rte_cpu_to_le_32(enables);
771 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
774 HWRM_CHECK_RESULT_SILENT();
782 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
785 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
786 struct hwrm_func_resource_qcaps_input req = {0};
788 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
789 req.fid = rte_cpu_to_le_16(0xffff);
791 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
796 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
797 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
798 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
799 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
800 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
801 /* func_resource_qcaps does not return max_rx_em_flows.
802 * So use the value provided by func_qcaps.
805 rte_le_to_cpu_16(resp->max_l2_ctxs) +
807 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
808 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
810 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
811 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
812 if (bp->vf_resv_strategy >
813 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
814 bp->vf_resv_strategy =
815 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
821 int bnxt_hwrm_ver_get(struct bnxt *bp)
824 struct hwrm_ver_get_input req = {.req_type = 0 };
825 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
827 uint16_t max_resp_len;
828 char type[RTE_MEMZONE_NAMESIZE];
829 uint32_t dev_caps_cfg;
831 bp->max_req_len = HWRM_MAX_REQ_LEN;
832 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
834 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
835 req.hwrm_intf_min = HWRM_VERSION_MINOR;
836 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
838 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
842 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
843 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
844 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
845 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
846 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
847 (resp->hwrm_fw_min_8b << 16) |
848 (resp->hwrm_fw_bld_8b << 8) |
849 resp->hwrm_fw_rsvd_8b;
850 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
851 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
853 fw_version = resp->hwrm_intf_maj_8b << 16;
854 fw_version |= resp->hwrm_intf_min_8b << 8;
855 fw_version |= resp->hwrm_intf_upd_8b;
856 bp->hwrm_spec_code = fw_version;
858 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
859 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
864 if (bp->max_req_len > resp->max_req_win_len) {
865 PMD_DRV_LOG(ERR, "Unsupported request length\n");
868 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
869 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
870 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
871 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
873 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
874 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
876 if (bp->max_resp_len != max_resp_len) {
877 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
878 bp->pdev->addr.domain, bp->pdev->addr.bus,
879 bp->pdev->addr.devid, bp->pdev->addr.function);
881 rte_free(bp->hwrm_cmd_resp_addr);
883 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
884 if (bp->hwrm_cmd_resp_addr == NULL) {
888 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
889 bp->hwrm_cmd_resp_dma_addr =
890 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
891 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
893 "Unable to map response buffer to physical memory.\n");
897 bp->max_resp_len = max_resp_len;
901 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
903 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
904 PMD_DRV_LOG(DEBUG, "Short command supported\n");
905 bp->flags |= BNXT_FLAG_SHORT_CMD;
909 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
911 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
912 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
913 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
914 bp->pdev->addr.domain, bp->pdev->addr.bus,
915 bp->pdev->addr.devid, bp->pdev->addr.function);
917 rte_free(bp->hwrm_short_cmd_req_addr);
919 bp->hwrm_short_cmd_req_addr =
920 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
921 if (bp->hwrm_short_cmd_req_addr == NULL) {
925 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
926 bp->hwrm_short_cmd_req_dma_addr =
927 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
928 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
929 rte_free(bp->hwrm_short_cmd_req_addr);
931 "Unable to map buffer to physical memory.\n");
937 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
938 bp->flags |= BNXT_FLAG_KONG_MB_EN;
939 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
942 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
943 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
950 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
953 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
954 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
956 if (!(bp->flags & BNXT_FLAG_REGISTERED))
959 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
962 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
970 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
973 struct hwrm_port_phy_cfg_input req = {0};
974 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
975 uint32_t enables = 0;
977 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
980 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
981 if (bp->link_info.auto_mode && conf->link_speed) {
982 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
983 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
986 req.flags = rte_cpu_to_le_32(conf->phy_flags);
987 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
988 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
990 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
991 * any auto mode, even "none".
993 if (!conf->link_speed) {
994 /* No speeds specified. Enable AutoNeg - all speeds */
996 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
998 /* AutoNeg - Advertise speeds specified. */
999 if (conf->auto_link_speed_mask &&
1000 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1002 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1003 req.auto_link_speed_mask =
1004 conf->auto_link_speed_mask;
1006 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1009 req.auto_duplex = conf->duplex;
1010 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1011 req.auto_pause = conf->auto_pause;
1012 req.force_pause = conf->force_pause;
1013 /* Set force_pause if there is no auto or if there is a force */
1014 if (req.auto_pause && !req.force_pause)
1015 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1017 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1019 req.enables = rte_cpu_to_le_32(enables);
1022 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1023 PMD_DRV_LOG(INFO, "Force Link Down\n");
1026 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1028 HWRM_CHECK_RESULT();
1034 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1035 struct bnxt_link_info *link_info)
1038 struct hwrm_port_phy_qcfg_input req = {0};
1039 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1041 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1043 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1045 HWRM_CHECK_RESULT();
1047 link_info->phy_link_status = resp->link;
1048 link_info->link_up =
1049 (link_info->phy_link_status ==
1050 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1051 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1052 link_info->duplex = resp->duplex_cfg;
1053 link_info->pause = resp->pause;
1054 link_info->auto_pause = resp->auto_pause;
1055 link_info->force_pause = resp->force_pause;
1056 link_info->auto_mode = resp->auto_mode;
1057 link_info->phy_type = resp->phy_type;
1058 link_info->media_type = resp->media_type;
1060 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1061 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1062 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1063 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1064 link_info->phy_ver[0] = resp->phy_maj;
1065 link_info->phy_ver[1] = resp->phy_min;
1066 link_info->phy_ver[2] = resp->phy_bld;
1070 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1071 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1072 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1073 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1074 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1075 link_info->auto_link_speed_mask);
1076 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1077 link_info->force_link_speed);
1082 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1085 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1086 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1089 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1091 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1092 /* HWRM Version >= 1.9.1 */
1093 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1095 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1096 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1098 HWRM_CHECK_RESULT();
1100 #define GET_QUEUE_INFO(x) \
1101 bp->cos_queue[x].id = resp->queue_id##x; \
1102 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1115 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1116 bp->tx_cosq_id = bp->cos_queue[0].id;
1118 /* iterate and find the COSq profile to use for Tx */
1119 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1120 if (bp->cos_queue[i].profile ==
1121 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1122 bp->tx_cosq_id = bp->cos_queue[i].id;
1128 bp->max_tc = resp->max_configurable_queues;
1129 bp->max_lltc = resp->max_configurable_lossless_queues;
1130 if (bp->max_tc > BNXT_MAX_QUEUE)
1131 bp->max_tc = BNXT_MAX_QUEUE;
1132 bp->max_q = bp->max_tc;
1134 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1139 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1140 struct bnxt_ring *ring,
1141 uint32_t ring_type, uint32_t map_index,
1142 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1145 uint32_t enables = 0;
1146 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1147 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1148 struct rte_mempool *mb_pool;
1149 uint16_t rx_buf_size;
1151 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1153 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1154 req.fbo = rte_cpu_to_le_32(0);
1155 /* Association of ring index with doorbell index */
1156 req.logical_id = rte_cpu_to_le_16(map_index);
1157 req.length = rte_cpu_to_le_32(ring->ring_size);
1159 switch (ring_type) {
1160 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1161 req.ring_type = ring_type;
1162 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1163 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1164 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1165 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1167 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1169 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1170 req.ring_type = ring_type;
1171 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1172 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1173 if (BNXT_CHIP_THOR(bp)) {
1174 mb_pool = bp->rx_queues[0]->mb_pool;
1175 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1176 RTE_PKTMBUF_HEADROOM;
1177 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1179 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1181 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1183 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1185 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1186 req.ring_type = ring_type;
1187 if (BNXT_HAS_NQ(bp)) {
1188 /* Association of cp ring with nq */
1189 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1191 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1193 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1195 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1196 req.ring_type = ring_type;
1197 req.page_size = BNXT_PAGE_SHFT;
1198 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1200 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1201 req.ring_type = ring_type;
1202 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1204 mb_pool = bp->rx_queues[0]->mb_pool;
1205 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1206 RTE_PKTMBUF_HEADROOM;
1207 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1209 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1210 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1211 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1212 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1215 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1220 req.enables = rte_cpu_to_le_32(enables);
1222 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1224 if (rc || resp->error_code) {
1225 if (rc == 0 && resp->error_code)
1226 rc = rte_le_to_cpu_16(resp->error_code);
1227 switch (ring_type) {
1228 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1230 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1233 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1235 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1238 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1240 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1244 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1246 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1249 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1251 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1255 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1261 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1266 int bnxt_hwrm_ring_free(struct bnxt *bp,
1267 struct bnxt_ring *ring, uint32_t ring_type)
1270 struct hwrm_ring_free_input req = {.req_type = 0 };
1271 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1273 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1275 req.ring_type = ring_type;
1276 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1278 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1280 if (rc || resp->error_code) {
1281 if (rc == 0 && resp->error_code)
1282 rc = rte_le_to_cpu_16(resp->error_code);
1285 switch (ring_type) {
1286 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1287 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1290 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1291 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1294 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1295 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1298 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1300 "hwrm_ring_free nq failed. rc:%d\n", rc);
1302 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1304 "hwrm_ring_free agg failed. rc:%d\n", rc);
1307 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1315 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1318 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1319 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1321 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1323 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1324 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1325 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1326 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1328 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1330 HWRM_CHECK_RESULT();
1332 bp->grp_info[idx].fw_grp_id =
1333 rte_le_to_cpu_16(resp->ring_group_id);
1340 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1343 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1344 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1346 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1348 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1350 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1352 HWRM_CHECK_RESULT();
1355 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1359 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1362 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1363 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1365 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1368 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1370 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1372 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1374 HWRM_CHECK_RESULT();
1380 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1381 unsigned int idx __rte_unused)
1384 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1385 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1387 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1389 req.update_period_ms = rte_cpu_to_le_32(0);
1391 req.stats_dma_addr =
1392 rte_cpu_to_le_64(cpr->hw_stats_map);
1394 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1396 HWRM_CHECK_RESULT();
1398 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1405 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1406 unsigned int idx __rte_unused)
1409 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1410 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1412 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1414 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1416 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1418 HWRM_CHECK_RESULT();
1424 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1427 struct hwrm_vnic_alloc_input req = { 0 };
1428 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1430 if (!BNXT_HAS_RING_GRPS(bp))
1431 goto skip_ring_grps;
1433 /* map ring groups to this vnic */
1434 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1435 vnic->start_grp_id, vnic->end_grp_id);
1436 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1437 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1439 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1440 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1441 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1442 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1445 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1446 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1447 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1449 if (vnic->func_default)
1451 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1452 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1454 HWRM_CHECK_RESULT();
1456 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1458 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1462 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1463 struct bnxt_vnic_info *vnic,
1464 struct bnxt_plcmodes_cfg *pmode)
1467 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1468 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1470 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1472 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1474 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1476 HWRM_CHECK_RESULT();
1478 pmode->flags = rte_le_to_cpu_32(resp->flags);
1479 /* dflt_vnic bit doesn't exist in the _cfg command */
1480 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1481 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1482 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1483 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1490 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1491 struct bnxt_vnic_info *vnic,
1492 struct bnxt_plcmodes_cfg *pmode)
1495 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1496 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1498 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1499 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1503 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1505 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1506 req.flags = rte_cpu_to_le_32(pmode->flags);
1507 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1508 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1509 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1510 req.enables = rte_cpu_to_le_32(
1511 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1512 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1513 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1516 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1518 HWRM_CHECK_RESULT();
1524 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1527 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1528 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1529 struct bnxt_plcmodes_cfg pmodes = { 0 };
1530 uint32_t ctx_enable_flag = 0;
1531 uint32_t enables = 0;
1533 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1534 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1538 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1542 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1544 if (BNXT_CHIP_THOR(bp)) {
1545 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1546 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1547 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1549 req.default_rx_ring_id =
1550 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1551 req.default_cmpl_ring_id =
1552 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1553 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1554 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1558 /* Only RSS support for now TBD: COS & LB */
1559 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1560 if (vnic->lb_rule != 0xffff)
1561 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1562 if (vnic->cos_rule != 0xffff)
1563 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1564 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1565 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1566 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1568 enables |= ctx_enable_flag;
1569 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1570 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1571 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1572 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1575 req.enables = rte_cpu_to_le_32(enables);
1576 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1577 req.mru = rte_cpu_to_le_16(vnic->mru);
1578 /* Configure default VNIC only once. */
1579 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1581 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1582 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1584 if (vnic->vlan_strip)
1586 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1589 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1590 if (vnic->roce_dual)
1591 req.flags |= rte_cpu_to_le_32(
1592 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1593 if (vnic->roce_only)
1594 req.flags |= rte_cpu_to_le_32(
1595 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1596 if (vnic->rss_dflt_cr)
1597 req.flags |= rte_cpu_to_le_32(
1598 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1600 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1602 HWRM_CHECK_RESULT();
1605 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1610 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1614 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1615 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1617 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1618 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1621 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1624 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1625 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1626 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1628 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1630 HWRM_CHECK_RESULT();
1632 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1633 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1634 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1635 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1636 vnic->mru = rte_le_to_cpu_16(resp->mru);
1637 vnic->func_default = rte_le_to_cpu_32(
1638 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1639 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1640 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1641 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1642 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1643 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1644 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1645 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1646 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1647 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1648 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1655 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1656 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1660 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1661 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1662 bp->hwrm_cmd_resp_addr;
1664 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1666 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1667 HWRM_CHECK_RESULT();
1669 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1670 if (!BNXT_HAS_RING_GRPS(bp))
1671 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1672 else if (ctx_idx == 0)
1673 vnic->rss_rule = ctx_id;
1680 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1681 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1684 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1685 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1686 bp->hwrm_cmd_resp_addr;
1688 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1689 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1692 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1694 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1696 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1698 HWRM_CHECK_RESULT();
1704 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1707 struct hwrm_vnic_free_input req = {.req_type = 0 };
1708 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1710 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1711 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1715 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1717 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1719 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1721 HWRM_CHECK_RESULT();
1724 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1725 /* Configure default VNIC again if necessary. */
1726 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1727 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1733 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1737 int nr_ctxs = vnic->num_lb_ctxts;
1738 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1739 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1741 for (i = 0; i < nr_ctxs; i++) {
1742 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1744 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1745 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1746 req.hash_mode_flags = vnic->hash_mode;
1748 req.hash_key_tbl_addr =
1749 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1751 req.ring_grp_tbl_addr =
1752 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1753 i * HW_HASH_INDEX_SIZE);
1754 req.ring_table_pair_index = i;
1755 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1757 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1760 HWRM_CHECK_RESULT();
1767 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1768 struct bnxt_vnic_info *vnic)
1771 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1772 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1774 if (!vnic->rss_table)
1777 if (BNXT_CHIP_THOR(bp))
1778 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1780 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1782 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1783 req.hash_mode_flags = vnic->hash_mode;
1785 req.ring_grp_tbl_addr =
1786 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1787 req.hash_key_tbl_addr =
1788 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1789 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1790 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1792 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1794 HWRM_CHECK_RESULT();
1800 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1801 struct bnxt_vnic_info *vnic)
1804 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1805 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1808 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1809 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1813 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1815 req.flags = rte_cpu_to_le_32(
1816 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1818 req.enables = rte_cpu_to_le_32(
1819 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1821 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1822 size -= RTE_PKTMBUF_HEADROOM;
1824 req.jumbo_thresh = rte_cpu_to_le_16(size);
1825 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1827 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1829 HWRM_CHECK_RESULT();
1835 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1836 struct bnxt_vnic_info *vnic, bool enable)
1839 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1840 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1842 if (BNXT_CHIP_THOR(bp))
1845 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1848 req.enables = rte_cpu_to_le_32(
1849 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1850 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1851 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1852 req.flags = rte_cpu_to_le_32(
1853 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1854 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1855 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1856 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1857 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1858 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1859 req.max_agg_segs = rte_cpu_to_le_16(5);
1861 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1862 req.min_agg_len = rte_cpu_to_le_32(512);
1864 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1866 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1868 HWRM_CHECK_RESULT();
1874 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1876 struct hwrm_func_cfg_input req = {0};
1877 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1880 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1881 req.enables = rte_cpu_to_le_32(
1882 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1883 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1884 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1886 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1888 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1889 HWRM_CHECK_RESULT();
1892 bp->pf.vf_info[vf].random_mac = false;
1897 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1901 struct hwrm_func_qstats_input req = {.req_type = 0};
1902 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1904 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1906 req.fid = rte_cpu_to_le_16(fid);
1908 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1910 HWRM_CHECK_RESULT();
1913 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1920 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1921 struct rte_eth_stats *stats)
1924 struct hwrm_func_qstats_input req = {.req_type = 0};
1925 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1927 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1929 req.fid = rte_cpu_to_le_16(fid);
1931 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1933 HWRM_CHECK_RESULT();
1935 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1936 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1937 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1938 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1939 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1940 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1942 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1943 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1944 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1945 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1946 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1947 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1949 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1950 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1951 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1958 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1961 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1962 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1964 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1966 req.fid = rte_cpu_to_le_16(fid);
1968 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1970 HWRM_CHECK_RESULT();
1977 * HWRM utility functions
1980 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1985 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1986 struct bnxt_tx_queue *txq;
1987 struct bnxt_rx_queue *rxq;
1988 struct bnxt_cp_ring_info *cpr;
1990 if (i >= bp->rx_cp_nr_rings) {
1991 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1994 rxq = bp->rx_queues[i];
1998 rc = bnxt_hwrm_stat_clear(bp, cpr);
2005 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2009 struct bnxt_cp_ring_info *cpr;
2011 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2013 if (i >= bp->rx_cp_nr_rings) {
2014 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2016 cpr = bp->rx_queues[i]->cp_ring;
2017 if (BNXT_HAS_RING_GRPS(bp))
2018 bp->grp_info[i].fw_stats_ctx = -1;
2020 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2021 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2022 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2030 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2035 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2036 struct bnxt_tx_queue *txq;
2037 struct bnxt_rx_queue *rxq;
2038 struct bnxt_cp_ring_info *cpr;
2040 if (i >= bp->rx_cp_nr_rings) {
2041 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2044 rxq = bp->rx_queues[i];
2048 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2056 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2061 if (!BNXT_HAS_RING_GRPS(bp))
2064 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2066 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2069 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2077 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2079 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2081 bnxt_hwrm_ring_free(bp, cp_ring,
2082 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2083 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2084 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2085 sizeof(*cpr->cp_desc_ring));
2086 cpr->cp_raw_cons = 0;
2090 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2092 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2094 bnxt_hwrm_ring_free(bp, cp_ring,
2095 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2096 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2097 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2098 sizeof(*cpr->cp_desc_ring));
2099 cpr->cp_raw_cons = 0;
2103 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2105 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2106 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2107 struct bnxt_ring *ring = rxr->rx_ring_struct;
2108 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2110 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2111 bnxt_hwrm_ring_free(bp, ring,
2112 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2113 ring->fw_ring_id = INVALID_HW_RING_ID;
2114 if (BNXT_HAS_RING_GRPS(bp))
2115 bp->grp_info[queue_index].rx_fw_ring_id =
2117 memset(rxr->rx_desc_ring, 0,
2118 rxr->rx_ring_struct->ring_size *
2119 sizeof(*rxr->rx_desc_ring));
2120 memset(rxr->rx_buf_ring, 0,
2121 rxr->rx_ring_struct->ring_size *
2122 sizeof(*rxr->rx_buf_ring));
2125 ring = rxr->ag_ring_struct;
2126 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2127 bnxt_hwrm_ring_free(bp, ring,
2128 BNXT_CHIP_THOR(bp) ?
2129 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2130 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2131 ring->fw_ring_id = INVALID_HW_RING_ID;
2132 memset(rxr->ag_buf_ring, 0,
2133 rxr->ag_ring_struct->ring_size *
2134 sizeof(*rxr->ag_buf_ring));
2136 if (BNXT_HAS_RING_GRPS(bp))
2137 bp->grp_info[queue_index].ag_fw_ring_id =
2140 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2141 bnxt_free_cp_ring(bp, cpr);
2143 bnxt_free_nq_ring(bp, rxq->nq_ring);
2146 if (BNXT_HAS_RING_GRPS(bp))
2147 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2150 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2154 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2155 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2156 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2157 struct bnxt_ring *ring = txr->tx_ring_struct;
2158 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2160 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2161 bnxt_hwrm_ring_free(bp, ring,
2162 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2163 ring->fw_ring_id = INVALID_HW_RING_ID;
2164 memset(txr->tx_desc_ring, 0,
2165 txr->tx_ring_struct->ring_size *
2166 sizeof(*txr->tx_desc_ring));
2167 memset(txr->tx_buf_ring, 0,
2168 txr->tx_ring_struct->ring_size *
2169 sizeof(*txr->tx_buf_ring));
2173 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2174 bnxt_free_cp_ring(bp, cpr);
2175 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2177 bnxt_free_nq_ring(bp, txq->nq_ring);
2181 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2182 bnxt_free_hwrm_rx_ring(bp, i);
2187 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2192 if (!BNXT_HAS_RING_GRPS(bp))
2195 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2196 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2203 void bnxt_free_hwrm_resources(struct bnxt *bp)
2205 /* Release memzone */
2206 rte_free(bp->hwrm_cmd_resp_addr);
2207 rte_free(bp->hwrm_short_cmd_req_addr);
2208 bp->hwrm_cmd_resp_addr = NULL;
2209 bp->hwrm_short_cmd_req_addr = NULL;
2210 bp->hwrm_cmd_resp_dma_addr = 0;
2211 bp->hwrm_short_cmd_req_dma_addr = 0;
2214 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2216 struct rte_pci_device *pdev = bp->pdev;
2217 char type[RTE_MEMZONE_NAMESIZE];
2219 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2220 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2221 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2222 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2223 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2224 if (bp->hwrm_cmd_resp_addr == NULL)
2226 bp->hwrm_cmd_resp_dma_addr =
2227 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2228 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2230 "unable to map response address to physical memory\n");
2233 rte_spinlock_init(&bp->hwrm_lock);
2238 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2240 struct bnxt_filter_info *filter;
2243 STAILQ_FOREACH(filter, &vnic->filter, next) {
2244 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2245 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2246 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2247 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2249 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2250 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2258 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2260 struct bnxt_filter_info *filter;
2261 struct rte_flow *flow;
2264 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2265 filter = flow->filter;
2266 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2267 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2268 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2269 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2270 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2272 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2274 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2282 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2284 struct bnxt_filter_info *filter;
2287 STAILQ_FOREACH(filter, &vnic->filter, next) {
2288 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2289 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2291 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2292 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2295 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2303 void bnxt_free_tunnel_ports(struct bnxt *bp)
2305 if (bp->vxlan_port_cnt)
2306 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2307 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2309 if (bp->geneve_port_cnt)
2310 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2311 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2312 bp->geneve_port = 0;
2315 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2319 if (bp->vnic_info == NULL)
2323 * Cleanup VNICs in reverse order, to make sure the L2 filter
2324 * from vnic0 is last to be cleaned up.
2326 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2327 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2329 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2330 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2334 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2336 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2338 if (BNXT_CHIP_THOR(bp)) {
2339 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2340 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2341 vnic->fw_grp_ids[j]);
2342 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2344 vnic->num_lb_ctxts = 0;
2346 bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2347 vnic->rss_rule = INVALID_HW_RING_ID;
2350 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2352 bnxt_hwrm_vnic_free(bp, vnic);
2354 rte_free(vnic->fw_grp_ids);
2356 /* Ring resources */
2357 bnxt_free_all_hwrm_rings(bp);
2358 bnxt_free_all_hwrm_ring_grps(bp);
2359 bnxt_free_all_hwrm_stat_ctxs(bp);
2360 bnxt_free_tunnel_ports(bp);
2363 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2365 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2367 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2368 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2370 switch (conf_link_speed) {
2371 case ETH_LINK_SPEED_10M_HD:
2372 case ETH_LINK_SPEED_100M_HD:
2374 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2376 return hw_link_duplex;
2379 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2381 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2384 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2386 uint16_t eth_link_speed = 0;
2388 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2389 return ETH_LINK_SPEED_AUTONEG;
2391 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2392 case ETH_LINK_SPEED_100M:
2393 case ETH_LINK_SPEED_100M_HD:
2396 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2398 case ETH_LINK_SPEED_1G:
2400 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2402 case ETH_LINK_SPEED_2_5G:
2404 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2406 case ETH_LINK_SPEED_10G:
2408 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2410 case ETH_LINK_SPEED_20G:
2412 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2414 case ETH_LINK_SPEED_25G:
2416 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2418 case ETH_LINK_SPEED_40G:
2420 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2422 case ETH_LINK_SPEED_50G:
2424 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2426 case ETH_LINK_SPEED_100G:
2428 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2432 "Unsupported link speed %d; default to AUTO\n",
2436 return eth_link_speed;
2439 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2440 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2441 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2442 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2444 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2448 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2451 if (link_speed & ETH_LINK_SPEED_FIXED) {
2452 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2454 if (one_speed & (one_speed - 1)) {
2456 "Invalid advertised speeds (%u) for port %u\n",
2457 link_speed, port_id);
2460 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2462 "Unsupported advertised speed (%u) for port %u\n",
2463 link_speed, port_id);
2467 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2469 "Unsupported advertised speeds (%u) for port %u\n",
2470 link_speed, port_id);
2478 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2482 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2483 if (bp->link_info.support_speeds)
2484 return bp->link_info.support_speeds;
2485 link_speed = BNXT_SUPPORTED_SPEEDS;
2488 if (link_speed & ETH_LINK_SPEED_100M)
2489 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2490 if (link_speed & ETH_LINK_SPEED_100M_HD)
2491 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2492 if (link_speed & ETH_LINK_SPEED_1G)
2493 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2494 if (link_speed & ETH_LINK_SPEED_2_5G)
2495 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2496 if (link_speed & ETH_LINK_SPEED_10G)
2497 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2498 if (link_speed & ETH_LINK_SPEED_20G)
2499 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2500 if (link_speed & ETH_LINK_SPEED_25G)
2501 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2502 if (link_speed & ETH_LINK_SPEED_40G)
2503 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2504 if (link_speed & ETH_LINK_SPEED_50G)
2505 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2506 if (link_speed & ETH_LINK_SPEED_100G)
2507 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2511 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2513 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2515 switch (hw_link_speed) {
2516 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2517 eth_link_speed = ETH_SPEED_NUM_100M;
2519 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2520 eth_link_speed = ETH_SPEED_NUM_1G;
2522 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2523 eth_link_speed = ETH_SPEED_NUM_2_5G;
2525 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2526 eth_link_speed = ETH_SPEED_NUM_10G;
2528 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2529 eth_link_speed = ETH_SPEED_NUM_20G;
2531 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2532 eth_link_speed = ETH_SPEED_NUM_25G;
2534 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2535 eth_link_speed = ETH_SPEED_NUM_40G;
2537 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2538 eth_link_speed = ETH_SPEED_NUM_50G;
2540 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2541 eth_link_speed = ETH_SPEED_NUM_100G;
2543 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2545 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2549 return eth_link_speed;
2552 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2554 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2556 switch (hw_link_duplex) {
2557 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2558 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2560 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2562 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2563 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2566 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2570 return eth_link_duplex;
2573 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2576 struct bnxt_link_info *link_info = &bp->link_info;
2578 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2581 "Get link config failed with rc %d\n", rc);
2584 if (link_info->link_speed)
2586 bnxt_parse_hw_link_speed(link_info->link_speed);
2588 link->link_speed = ETH_SPEED_NUM_NONE;
2589 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2590 link->link_status = link_info->link_up;
2591 link->link_autoneg = link_info->auto_mode ==
2592 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2593 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2598 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2601 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2602 struct bnxt_link_info link_req;
2603 uint16_t speed, autoneg;
2605 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2608 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2609 bp->eth_dev->data->port_id);
2613 memset(&link_req, 0, sizeof(link_req));
2614 link_req.link_up = link_up;
2618 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2619 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2620 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2621 /* Autoneg can be done only when the FW allows */
2622 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2623 bp->link_info.force_link_speed)) {
2624 link_req.phy_flags |=
2625 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2626 link_req.auto_link_speed_mask =
2627 bnxt_parse_eth_link_speed_mask(bp,
2628 dev_conf->link_speeds);
2630 if (bp->link_info.phy_type ==
2631 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2632 bp->link_info.phy_type ==
2633 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2634 bp->link_info.media_type ==
2635 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2636 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2640 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2641 /* If user wants a particular speed try that first. */
2643 link_req.link_speed = speed;
2644 else if (bp->link_info.force_link_speed)
2645 link_req.link_speed = bp->link_info.force_link_speed;
2647 link_req.link_speed = bp->link_info.auto_link_speed;
2649 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2650 link_req.auto_pause = bp->link_info.auto_pause;
2651 link_req.force_pause = bp->link_info.force_pause;
2654 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2657 "Set link config failed with rc %d\n", rc);
2665 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2667 struct hwrm_func_qcfg_input req = {0};
2668 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2672 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2673 req.fid = rte_cpu_to_le_16(0xffff);
2675 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2677 HWRM_CHECK_RESULT();
2679 /* Hard Coded.. 0xfff VLAN ID mask */
2680 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2681 flags = rte_le_to_cpu_16(resp->flags);
2682 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2683 bp->flags |= BNXT_FLAG_MULTI_HOST;
2685 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2686 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2687 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2693 switch (resp->port_partition_type) {
2694 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2695 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2696 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2698 bp->port_partition_type = resp->port_partition_type;
2701 bp->port_partition_type = 0;
2710 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2711 struct hwrm_func_qcaps_output *qcaps)
2713 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2714 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2715 sizeof(qcaps->mac_address));
2716 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2717 qcaps->max_rx_rings = fcfg->num_rx_rings;
2718 qcaps->max_tx_rings = fcfg->num_tx_rings;
2719 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2720 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2722 qcaps->first_vf_id = 0;
2723 qcaps->max_vnics = fcfg->num_vnics;
2724 qcaps->max_decap_records = 0;
2725 qcaps->max_encap_records = 0;
2726 qcaps->max_tx_wm_flows = 0;
2727 qcaps->max_tx_em_flows = 0;
2728 qcaps->max_rx_wm_flows = 0;
2729 qcaps->max_rx_em_flows = 0;
2730 qcaps->max_flow_id = 0;
2731 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2732 qcaps->max_sp_tx_rings = 0;
2733 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2736 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2738 struct hwrm_func_cfg_input req = {0};
2739 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2743 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2744 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2745 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2746 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2747 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2748 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2749 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2750 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2751 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2753 if (BNXT_HAS_RING_GRPS(bp)) {
2754 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2755 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2756 } else if (BNXT_HAS_NQ(bp)) {
2757 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2758 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2761 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2762 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2763 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2764 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2766 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2767 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2768 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2769 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2770 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2771 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2772 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2773 req.fid = rte_cpu_to_le_16(0xffff);
2774 req.enables = rte_cpu_to_le_32(enables);
2776 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2778 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2780 HWRM_CHECK_RESULT();
2786 static void populate_vf_func_cfg_req(struct bnxt *bp,
2787 struct hwrm_func_cfg_input *req,
2790 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2791 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2792 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2793 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2794 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2795 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2796 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2797 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2798 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2799 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2801 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2802 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2804 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2805 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2807 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2809 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2810 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2812 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2813 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2814 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2815 /* TODO: For now, do not support VMDq/RFS on VFs. */
2816 req->num_vnics = rte_cpu_to_le_16(1);
2817 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2821 static void add_random_mac_if_needed(struct bnxt *bp,
2822 struct hwrm_func_cfg_input *cfg_req,
2825 struct rte_ether_addr mac;
2827 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2830 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2832 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2833 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2834 bp->pf.vf_info[vf].random_mac = true;
2836 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2837 RTE_ETHER_ADDR_LEN);
2841 static void reserve_resources_from_vf(struct bnxt *bp,
2842 struct hwrm_func_cfg_input *cfg_req,
2845 struct hwrm_func_qcaps_input req = {0};
2846 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2849 /* Get the actual allocated values now */
2850 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2851 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2852 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2855 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2856 copy_func_cfg_to_qcaps(cfg_req, resp);
2857 } else if (resp->error_code) {
2858 rc = rte_le_to_cpu_16(resp->error_code);
2859 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2860 copy_func_cfg_to_qcaps(cfg_req, resp);
2863 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2864 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2865 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2866 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2867 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2868 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2870 * TODO: While not supporting VMDq with VFs, max_vnics is always
2871 * forced to 1 in this case
2873 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2874 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2879 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2881 struct hwrm_func_qcfg_input req = {0};
2882 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2885 /* Check for zero MAC address */
2886 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2887 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2888 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2889 HWRM_CHECK_RESULT();
2890 rc = rte_le_to_cpu_16(resp->vlan);
2897 static int update_pf_resource_max(struct bnxt *bp)
2899 struct hwrm_func_qcfg_input req = {0};
2900 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2903 /* And copy the allocated numbers into the pf struct */
2904 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2905 req.fid = rte_cpu_to_le_16(0xffff);
2906 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2907 HWRM_CHECK_RESULT();
2909 /* Only TX ring value reflects actual allocation? TODO */
2910 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2911 bp->pf.evb_mode = resp->evb_mode;
2918 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2923 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2927 rc = bnxt_hwrm_func_qcaps(bp);
2931 bp->pf.func_cfg_flags &=
2932 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2933 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2934 bp->pf.func_cfg_flags |=
2935 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2936 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2937 rc = __bnxt_hwrm_func_qcaps(bp);
2941 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2943 struct hwrm_func_cfg_input req = {0};
2944 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2951 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2955 rc = bnxt_hwrm_func_qcaps(bp);
2960 bp->pf.active_vfs = num_vfs;
2963 * First, configure the PF to only use one TX ring. This ensures that
2964 * there are enough rings for all VFs.
2966 * If we don't do this, when we call func_alloc() later, we will lock
2967 * extra rings to the PF that won't be available during func_cfg() of
2970 * This has been fixed with firmware versions above 20.6.54
2972 bp->pf.func_cfg_flags &=
2973 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2974 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2975 bp->pf.func_cfg_flags |=
2976 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2977 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2982 * Now, create and register a buffer to hold forwarded VF requests
2984 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2985 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2986 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2987 if (bp->pf.vf_req_buf == NULL) {
2991 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2992 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2993 for (i = 0; i < num_vfs; i++)
2994 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2995 (i * HWRM_MAX_REQ_LEN);
2997 rc = bnxt_hwrm_func_buf_rgtr(bp);
3001 populate_vf_func_cfg_req(bp, &req, num_vfs);
3003 bp->pf.active_vfs = 0;
3004 for (i = 0; i < num_vfs; i++) {
3005 add_random_mac_if_needed(bp, &req, i);
3007 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3008 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3009 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3010 rc = bnxt_hwrm_send_message(bp,
3015 /* Clear enable flag for next pass */
3016 req.enables &= ~rte_cpu_to_le_32(
3017 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3019 if (rc || resp->error_code) {
3021 "Failed to initizlie VF %d\n", i);
3023 "Not all VFs available. (%d, %d)\n",
3024 rc, resp->error_code);
3031 reserve_resources_from_vf(bp, &req, i);
3032 bp->pf.active_vfs++;
3033 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3037 * Now configure the PF to use "the rest" of the resources
3038 * We're using STD_TX_RING_MODE here though which will limit the TX
3039 * rings. This will allow QoS to function properly. Not setting this
3040 * will cause PF rings to break bandwidth settings.
3042 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3046 rc = update_pf_resource_max(bp);
3053 bnxt_hwrm_func_buf_unrgtr(bp);
3057 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3059 struct hwrm_func_cfg_input req = {0};
3060 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3063 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3065 req.fid = rte_cpu_to_le_16(0xffff);
3066 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3067 req.evb_mode = bp->pf.evb_mode;
3069 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3070 HWRM_CHECK_RESULT();
3076 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3077 uint8_t tunnel_type)
3079 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3080 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3083 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3084 req.tunnel_type = tunnel_type;
3085 req.tunnel_dst_port_val = port;
3086 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3087 HWRM_CHECK_RESULT();
3089 switch (tunnel_type) {
3090 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3091 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3092 bp->vxlan_port = port;
3094 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3095 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3096 bp->geneve_port = port;
3107 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3108 uint8_t tunnel_type)
3110 struct hwrm_tunnel_dst_port_free_input req = {0};
3111 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3114 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3116 req.tunnel_type = tunnel_type;
3117 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3118 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3120 HWRM_CHECK_RESULT();
3126 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3129 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3130 struct hwrm_func_cfg_input req = {0};
3133 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3135 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3136 req.flags = rte_cpu_to_le_32(flags);
3137 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3139 HWRM_CHECK_RESULT();
3145 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3147 uint32_t *flag = flagp;
3149 vnic->flags = *flag;
3152 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3154 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3157 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3160 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3161 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3163 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3165 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3166 req.req_buf_page_size = rte_cpu_to_le_16(
3167 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3168 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3169 req.req_buf_page_addr0 =
3170 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3171 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3173 "unable to map buffer address to physical memory\n");
3177 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3179 HWRM_CHECK_RESULT();
3185 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3188 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3189 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3191 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3194 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3196 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3198 HWRM_CHECK_RESULT();
3204 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3206 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3207 struct hwrm_func_cfg_input req = {0};
3210 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3212 req.fid = rte_cpu_to_le_16(0xffff);
3213 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3214 req.enables = rte_cpu_to_le_32(
3215 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3216 req.async_event_cr = rte_cpu_to_le_16(
3217 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3218 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3220 HWRM_CHECK_RESULT();
3226 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3228 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3229 struct hwrm_func_vf_cfg_input req = {0};
3232 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3234 req.enables = rte_cpu_to_le_32(
3235 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3236 req.async_event_cr = rte_cpu_to_le_16(
3237 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3238 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3240 HWRM_CHECK_RESULT();
3246 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3248 struct hwrm_func_cfg_input req = {0};
3249 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3250 uint16_t dflt_vlan, fid;
3251 uint32_t func_cfg_flags;
3254 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3257 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3258 fid = bp->pf.vf_info[vf].fid;
3259 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3261 fid = rte_cpu_to_le_16(0xffff);
3262 func_cfg_flags = bp->pf.func_cfg_flags;
3263 dflt_vlan = bp->vlan;
3266 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3267 req.fid = rte_cpu_to_le_16(fid);
3268 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3269 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3271 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3273 HWRM_CHECK_RESULT();
3279 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3280 uint16_t max_bw, uint16_t enables)
3282 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3283 struct hwrm_func_cfg_input req = {0};
3286 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3288 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3289 req.enables |= rte_cpu_to_le_32(enables);
3290 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3291 req.max_bw = rte_cpu_to_le_32(max_bw);
3292 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3294 HWRM_CHECK_RESULT();
3300 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3302 struct hwrm_func_cfg_input req = {0};
3303 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3306 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3308 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3309 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3310 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3311 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3313 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3315 HWRM_CHECK_RESULT();
3321 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3326 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3328 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3333 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3334 void *encaped, size_t ec_size)
3337 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3338 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3340 if (ec_size > sizeof(req.encap_request))
3343 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3345 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3346 memcpy(req.encap_request, encaped, ec_size);
3348 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3350 HWRM_CHECK_RESULT();
3356 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3357 struct rte_ether_addr *mac)
3359 struct hwrm_func_qcfg_input req = {0};
3360 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3363 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3365 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3366 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3368 HWRM_CHECK_RESULT();
3370 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3377 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3378 void *encaped, size_t ec_size)
3381 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3382 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3384 if (ec_size > sizeof(req.encap_request))
3387 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3389 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3390 memcpy(req.encap_request, encaped, ec_size);
3392 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3394 HWRM_CHECK_RESULT();
3400 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3401 struct rte_eth_stats *stats, uint8_t rx)
3404 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3405 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3407 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3409 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3411 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3413 HWRM_CHECK_RESULT();
3416 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3417 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3418 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3419 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3420 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3421 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3422 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3423 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3425 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3426 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3427 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3428 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3429 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3430 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3439 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3441 struct hwrm_port_qstats_input req = {0};
3442 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3443 struct bnxt_pf_info *pf = &bp->pf;
3446 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3448 req.port_id = rte_cpu_to_le_16(pf->port_id);
3449 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3450 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3451 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3453 HWRM_CHECK_RESULT();
3459 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3461 struct hwrm_port_clr_stats_input req = {0};
3462 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3463 struct bnxt_pf_info *pf = &bp->pf;
3466 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3467 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3468 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3471 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3473 req.port_id = rte_cpu_to_le_16(pf->port_id);
3474 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3476 HWRM_CHECK_RESULT();
3482 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3484 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3485 struct hwrm_port_led_qcaps_input req = {0};
3491 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3492 req.port_id = bp->pf.port_id;
3493 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3495 HWRM_CHECK_RESULT();
3497 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3500 bp->num_leds = resp->num_leds;
3501 memcpy(bp->leds, &resp->led0_id,
3502 sizeof(bp->leds[0]) * bp->num_leds);
3503 for (i = 0; i < bp->num_leds; i++) {
3504 struct bnxt_led_info *led = &bp->leds[i];
3506 uint16_t caps = led->led_state_caps;
3508 if (!led->led_group_id ||
3509 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3521 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3523 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3524 struct hwrm_port_led_cfg_input req = {0};
3525 struct bnxt_led_cfg *led_cfg;
3526 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3527 uint16_t duration = 0;
3530 if (!bp->num_leds || BNXT_VF(bp))
3533 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3536 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3537 duration = rte_cpu_to_le_16(500);
3539 req.port_id = bp->pf.port_id;
3540 req.num_leds = bp->num_leds;
3541 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3542 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3543 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3544 led_cfg->led_id = bp->leds[i].led_id;
3545 led_cfg->led_state = led_state;
3546 led_cfg->led_blink_on = duration;
3547 led_cfg->led_blink_off = duration;
3548 led_cfg->led_group_id = bp->leds[i].led_group_id;
3551 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3553 HWRM_CHECK_RESULT();
3559 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3563 struct hwrm_nvm_get_dir_info_input req = {0};
3564 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3566 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3568 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3570 HWRM_CHECK_RESULT();
3572 *entries = rte_le_to_cpu_32(resp->entries);
3573 *length = rte_le_to_cpu_32(resp->entry_length);
3579 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3582 uint32_t dir_entries;
3583 uint32_t entry_length;
3586 rte_iova_t dma_handle;
3587 struct hwrm_nvm_get_dir_entries_input req = {0};
3588 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3590 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3594 *data++ = dir_entries;
3595 *data++ = entry_length;
3597 memset(data, 0xff, len);
3599 buflen = dir_entries * entry_length;
3600 buf = rte_malloc("nvm_dir", buflen, 0);
3601 rte_mem_lock_page(buf);
3604 dma_handle = rte_mem_virt2iova(buf);
3605 if (dma_handle == RTE_BAD_IOVA) {
3607 "unable to map response address to physical memory\n");
3610 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3611 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3612 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3615 memcpy(data, buf, len > buflen ? buflen : len);
3618 HWRM_CHECK_RESULT();
3624 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3625 uint32_t offset, uint32_t length,
3630 rte_iova_t dma_handle;
3631 struct hwrm_nvm_read_input req = {0};
3632 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3634 buf = rte_malloc("nvm_item", length, 0);
3635 rte_mem_lock_page(buf);
3639 dma_handle = rte_mem_virt2iova(buf);
3640 if (dma_handle == RTE_BAD_IOVA) {
3642 "unable to map response address to physical memory\n");
3645 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3646 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3647 req.dir_idx = rte_cpu_to_le_16(index);
3648 req.offset = rte_cpu_to_le_32(offset);
3649 req.len = rte_cpu_to_le_32(length);
3650 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3652 memcpy(data, buf, length);
3655 HWRM_CHECK_RESULT();
3661 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3664 struct hwrm_nvm_erase_dir_entry_input req = {0};
3665 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3667 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3668 req.dir_idx = rte_cpu_to_le_16(index);
3669 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3670 HWRM_CHECK_RESULT();
3677 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3678 uint16_t dir_ordinal, uint16_t dir_ext,
3679 uint16_t dir_attr, const uint8_t *data,
3683 struct hwrm_nvm_write_input req = {0};
3684 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3685 rte_iova_t dma_handle;
3688 buf = rte_malloc("nvm_write", data_len, 0);
3689 rte_mem_lock_page(buf);
3693 dma_handle = rte_mem_virt2iova(buf);
3694 if (dma_handle == RTE_BAD_IOVA) {
3696 "unable to map response address to physical memory\n");
3699 memcpy(buf, data, data_len);
3701 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3703 req.dir_type = rte_cpu_to_le_16(dir_type);
3704 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3705 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3706 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3707 req.dir_data_length = rte_cpu_to_le_32(data_len);
3708 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3710 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3713 HWRM_CHECK_RESULT();
3720 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3722 uint32_t *count = cbdata;
3724 *count = *count + 1;
3727 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3728 struct bnxt_vnic_info *vnic __rte_unused)
3733 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3737 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3738 &count, bnxt_vnic_count_hwrm_stub);
3743 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3746 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3747 struct hwrm_func_vf_vnic_ids_query_output *resp =
3748 bp->hwrm_cmd_resp_addr;
3751 /* First query all VNIC ids */
3752 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3754 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3755 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3756 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3758 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3761 "unable to map VNIC ID table address to physical memory\n");
3764 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3765 HWRM_CHECK_RESULT();
3766 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3774 * This function queries the VNIC IDs for a specified VF. It then calls
3775 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3776 * Then it calls the hwrm_cb function to program this new vnic configuration.
3778 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3779 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3780 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3782 struct bnxt_vnic_info vnic;
3784 int i, num_vnic_ids;
3789 /* First query all VNIC ids */
3790 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3791 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3792 RTE_CACHE_LINE_SIZE);
3793 if (vnic_ids == NULL)
3796 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3797 rte_mem_lock_page(((char *)vnic_ids) + sz);
3799 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3801 if (num_vnic_ids < 0)
3802 return num_vnic_ids;
3804 /* Retrieve VNIC, update bd_stall then update */
3806 for (i = 0; i < num_vnic_ids; i++) {
3807 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3808 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3809 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3812 if (vnic.mru <= 4) /* Indicates unallocated */
3815 vnic_cb(&vnic, cbdata);
3817 rc = hwrm_cb(bp, &vnic);
3827 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3830 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3831 struct hwrm_func_cfg_input req = {0};
3834 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3836 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3837 req.enables |= rte_cpu_to_le_32(
3838 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3839 req.vlan_antispoof_mode = on ?
3840 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3841 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3842 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3844 HWRM_CHECK_RESULT();
3850 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3852 struct bnxt_vnic_info vnic;
3855 int num_vnic_ids, i;
3859 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3860 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3861 RTE_CACHE_LINE_SIZE);
3862 if (vnic_ids == NULL)
3865 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3866 rte_mem_lock_page(((char *)vnic_ids) + sz);
3868 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3874 * Loop through to find the default VNIC ID.
3875 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3876 * by sending the hwrm_func_qcfg command to the firmware.
3878 for (i = 0; i < num_vnic_ids; i++) {
3879 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3880 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3881 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3882 bp->pf.first_vf_id + vf);
3885 if (vnic.func_default) {
3887 return vnic.fw_vnic_id;
3890 /* Could not find a default VNIC. */
3891 PMD_DRV_LOG(ERR, "No default VNIC\n");
3897 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3899 struct bnxt_filter_info *filter)
3902 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3903 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3904 uint32_t enables = 0;
3906 if (filter->fw_em_filter_id != UINT64_MAX)
3907 bnxt_hwrm_clear_em_filter(bp, filter);
3909 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3911 req.flags = rte_cpu_to_le_32(filter->flags);
3913 enables = filter->enables |
3914 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3915 req.dst_id = rte_cpu_to_le_16(dst_id);
3917 if (filter->ip_addr_type) {
3918 req.ip_addr_type = filter->ip_addr_type;
3919 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3922 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3923 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3925 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3926 memcpy(req.src_macaddr, filter->src_macaddr,
3927 RTE_ETHER_ADDR_LEN);
3929 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3930 memcpy(req.dst_macaddr, filter->dst_macaddr,
3931 RTE_ETHER_ADDR_LEN);
3933 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3934 req.ovlan_vid = filter->l2_ovlan;
3936 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3937 req.ivlan_vid = filter->l2_ivlan;
3939 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3940 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3942 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3943 req.ip_protocol = filter->ip_protocol;
3945 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3946 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3948 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3949 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3951 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3952 req.src_port = rte_cpu_to_be_16(filter->src_port);
3954 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3955 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3957 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3958 req.mirror_vnic_id = filter->mirror_vnic_id;
3960 req.enables = rte_cpu_to_le_32(enables);
3962 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3964 HWRM_CHECK_RESULT();
3966 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3972 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3975 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3976 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3978 if (filter->fw_em_filter_id == UINT64_MAX)
3981 PMD_DRV_LOG(ERR, "Clear EM filter\n");
3982 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
3984 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3986 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3988 HWRM_CHECK_RESULT();
3991 filter->fw_em_filter_id = UINT64_MAX;
3992 filter->fw_l2_filter_id = UINT64_MAX;
3997 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3999 struct bnxt_filter_info *filter)
4002 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4003 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4004 bp->hwrm_cmd_resp_addr;
4005 uint32_t enables = 0;
4007 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4008 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4010 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4012 req.flags = rte_cpu_to_le_32(filter->flags);
4014 enables = filter->enables |
4015 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4016 req.dst_id = rte_cpu_to_le_16(dst_id);
4019 if (filter->ip_addr_type) {
4020 req.ip_addr_type = filter->ip_addr_type;
4022 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4025 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4026 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4028 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4029 memcpy(req.src_macaddr, filter->src_macaddr,
4030 RTE_ETHER_ADDR_LEN);
4032 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4033 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4034 //RTE_ETHER_ADDR_LEN);
4036 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4037 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4039 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4040 req.ip_protocol = filter->ip_protocol;
4042 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4043 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4045 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4046 req.src_ipaddr_mask[0] =
4047 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4049 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4050 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4052 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4053 req.dst_ipaddr_mask[0] =
4054 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4056 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4057 req.src_port = rte_cpu_to_le_16(filter->src_port);
4059 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4060 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4062 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4063 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4065 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4066 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4068 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4069 req.mirror_vnic_id = filter->mirror_vnic_id;
4071 req.enables = rte_cpu_to_le_32(enables);
4073 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4075 HWRM_CHECK_RESULT();
4077 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4083 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4084 struct bnxt_filter_info *filter)
4087 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4088 struct hwrm_cfa_ntuple_filter_free_output *resp =
4089 bp->hwrm_cmd_resp_addr;
4091 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4094 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4096 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4098 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4100 HWRM_CHECK_RESULT();
4103 filter->fw_ntuple_filter_id = UINT64_MAX;
4109 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4111 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4112 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4113 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4114 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4115 uint16_t *ring_tbl = vnic->rss_table;
4116 int nr_ctxs = vnic->num_lb_ctxts;
4117 int max_rings = bp->rx_nr_rings;
4121 for (i = 0, k = 0; i < nr_ctxs; i++) {
4122 struct bnxt_rx_ring_info *rxr;
4123 struct bnxt_cp_ring_info *cpr;
4125 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4127 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4128 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4129 req.hash_mode_flags = vnic->hash_mode;
4131 req.ring_grp_tbl_addr =
4132 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4133 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4134 2 * sizeof(*ring_tbl));
4135 req.hash_key_tbl_addr =
4136 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4138 req.ring_table_pair_index = i;
4139 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4141 for (j = 0; j < 64; j++) {
4144 /* Find next active ring. */
4145 for (cnt = 0; cnt < max_rings; cnt++) {
4146 if (rx_queue_state[k] !=
4147 RTE_ETH_QUEUE_STATE_STOPPED)
4149 if (++k == max_rings)
4153 /* Return if no rings are active. */
4154 if (cnt == max_rings)
4157 /* Add rx/cp ring pair to RSS table. */
4158 rxr = rxqs[k]->rx_ring;
4159 cpr = rxqs[k]->cp_ring;
4161 ring_id = rxr->rx_ring_struct->fw_ring_id;
4162 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4163 ring_id = cpr->cp_ring_struct->fw_ring_id;
4164 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4166 if (++k == max_rings)
4169 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4172 HWRM_CHECK_RESULT();
4179 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4181 unsigned int rss_idx, fw_idx, i;
4183 if (!(vnic->rss_table && vnic->hash_type))
4186 if (BNXT_CHIP_THOR(bp))
4187 return bnxt_vnic_rss_configure_thor(bp, vnic);
4190 * Fill the RSS hash & redirection table with
4191 * ring group ids for all VNICs
4193 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4194 rss_idx++, fw_idx++) {
4195 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4196 fw_idx %= bp->rx_cp_nr_rings;
4197 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4201 if (i == bp->rx_cp_nr_rings)
4203 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4205 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4208 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4209 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4213 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4215 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4216 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4218 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4219 req->num_cmpl_dma_aggr_during_int =
4220 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4222 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4224 /* min timer set to 1/2 of interrupt timer */
4225 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4227 /* buf timer set to 1/4 of interrupt timer */
4228 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4230 req->cmpl_aggr_dma_tmr_during_int =
4231 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4233 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4234 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4235 req->flags = rte_cpu_to_le_16(flags);
4238 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4239 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4241 struct hwrm_ring_aggint_qcaps_input req = {0};
4242 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4247 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4248 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4249 HWRM_CHECK_RESULT();
4251 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4252 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4254 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4255 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4256 agg_req->flags = rte_cpu_to_le_16(flags);
4258 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4259 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4260 agg_req->enables = rte_cpu_to_le_32(enables);
4266 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4267 struct bnxt_coal *coal, uint16_t ring_id)
4269 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4270 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4271 bp->hwrm_cmd_resp_addr;
4274 /* Set ring coalesce parameters only for 100G NICs */
4275 if (BNXT_CHIP_THOR(bp)) {
4276 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4278 } else if (bnxt_stratus_device(bp)) {
4279 bnxt_hwrm_set_coal_params(coal, &req);
4284 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4285 req.ring_id = rte_cpu_to_le_16(ring_id);
4286 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4287 HWRM_CHECK_RESULT();
4292 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4293 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4295 struct hwrm_func_backing_store_qcaps_input req = {0};
4296 struct hwrm_func_backing_store_qcaps_output *resp =
4297 bp->hwrm_cmd_resp_addr;
4300 if (!BNXT_CHIP_THOR(bp) ||
4301 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4306 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4307 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4308 HWRM_CHECK_RESULT_SILENT();
4311 struct bnxt_ctx_pg_info *ctx_pg;
4312 struct bnxt_ctx_mem_info *ctx;
4313 int total_alloc_len;
4316 total_alloc_len = sizeof(*ctx);
4317 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4318 RTE_CACHE_LINE_SIZE);
4323 memset(ctx, 0, total_alloc_len);
4325 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4326 sizeof(*ctx_pg) * BNXT_MAX_Q,
4327 RTE_CACHE_LINE_SIZE);
4332 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4333 ctx->tqm_mem[i] = ctx_pg;
4336 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4337 ctx->qp_min_qp1_entries =
4338 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4339 ctx->qp_max_l2_entries =
4340 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4341 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4342 ctx->srq_max_l2_entries =
4343 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4344 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4345 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4346 ctx->cq_max_l2_entries =
4347 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4348 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4349 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4350 ctx->vnic_max_vnic_entries =
4351 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4352 ctx->vnic_max_ring_table_entries =
4353 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4354 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4355 ctx->stat_max_entries =
4356 rte_le_to_cpu_32(resp->stat_max_entries);
4357 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4358 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4359 ctx->tqm_min_entries_per_ring =
4360 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4361 ctx->tqm_max_entries_per_ring =
4362 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4363 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4364 if (!ctx->tqm_entries_multiple)
4365 ctx->tqm_entries_multiple = 1;
4366 ctx->mrav_max_entries =
4367 rte_le_to_cpu_32(resp->mrav_max_entries);
4368 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4369 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4370 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4379 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4381 struct hwrm_func_backing_store_cfg_input req = {0};
4382 struct hwrm_func_backing_store_cfg_output *resp =
4383 bp->hwrm_cmd_resp_addr;
4384 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4385 struct bnxt_ctx_pg_info *ctx_pg;
4386 uint32_t *num_entries;
4395 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4396 req.enables = rte_cpu_to_le_32(enables);
4398 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4399 ctx_pg = &ctx->qp_mem;
4400 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4401 req.qp_num_qp1_entries =
4402 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4403 req.qp_num_l2_entries =
4404 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4405 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4406 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4407 &req.qpc_pg_size_qpc_lvl,
4411 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4412 ctx_pg = &ctx->srq_mem;
4413 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4414 req.srq_num_l2_entries =
4415 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4416 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4417 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4418 &req.srq_pg_size_srq_lvl,
4422 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4423 ctx_pg = &ctx->cq_mem;
4424 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4425 req.cq_num_l2_entries =
4426 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4427 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4428 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4429 &req.cq_pg_size_cq_lvl,
4433 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4434 ctx_pg = &ctx->vnic_mem;
4435 req.vnic_num_vnic_entries =
4436 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4437 req.vnic_num_ring_table_entries =
4438 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4439 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4440 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4441 &req.vnic_pg_size_vnic_lvl,
4442 &req.vnic_page_dir);
4445 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4446 ctx_pg = &ctx->stat_mem;
4447 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4448 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4449 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4450 &req.stat_pg_size_stat_lvl,
4451 &req.stat_page_dir);
4454 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4455 num_entries = &req.tqm_sp_num_entries;
4456 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4457 pg_dir = &req.tqm_sp_page_dir;
4458 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4459 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4460 if (!(enables & ena))
4463 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4465 ctx_pg = ctx->tqm_mem[i];
4466 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4467 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4470 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4471 HWRM_CHECK_RESULT();
4477 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4479 struct hwrm_port_qstats_ext_input req = {0};
4480 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4481 struct bnxt_pf_info *pf = &bp->pf;
4484 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4485 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4488 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4490 req.port_id = rte_cpu_to_le_16(pf->port_id);
4491 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4492 req.tx_stat_host_addr =
4493 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4495 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4497 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4498 req.rx_stat_host_addr =
4499 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4501 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4503 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4506 bp->fw_rx_port_stats_ext_size = 0;
4507 bp->fw_tx_port_stats_ext_size = 0;
4509 bp->fw_rx_port_stats_ext_size =
4510 rte_le_to_cpu_16(resp->rx_stat_size);
4511 bp->fw_tx_port_stats_ext_size =
4512 rte_le_to_cpu_16(resp->tx_stat_size);
4515 HWRM_CHECK_RESULT();
4522 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4524 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4525 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4526 bp->hwrm_cmd_resp_addr;
4529 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4530 req.tunnel_type = type;
4531 req.dest_fid = bp->fw_fid;
4532 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4533 HWRM_CHECK_RESULT();
4541 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4543 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4544 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4545 bp->hwrm_cmd_resp_addr;
4548 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4549 req.tunnel_type = type;
4550 req.dest_fid = bp->fw_fid;
4551 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4552 HWRM_CHECK_RESULT();
4559 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4561 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4562 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4563 bp->hwrm_cmd_resp_addr;
4566 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4567 req.src_fid = bp->fw_fid;
4568 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4569 HWRM_CHECK_RESULT();
4572 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4579 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4582 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4583 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4584 bp->hwrm_cmd_resp_addr;
4587 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4588 req.src_fid = bp->fw_fid;
4589 req.tunnel_type = tun_type;
4590 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4591 HWRM_CHECK_RESULT();
4594 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4596 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4603 int bnxt_hwrm_set_mac(struct bnxt *bp)
4605 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4606 struct hwrm_func_vf_cfg_input req = {0};
4612 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4615 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4616 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4618 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4620 HWRM_CHECK_RESULT();
4622 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);