1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2021 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
30 #define HWRM_VERSION_1_10_2_13 0x10a020d
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(int) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
67 if (rmem->nr_pages == 0)
70 if (rmem->nr_pages > 1) {
72 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
74 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
78 static struct bnxt_cp_ring_info*
79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
81 struct bnxt_cp_ring_info *cp_ring = NULL;
85 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
86 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
88 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
89 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
91 if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
92 rte_cpu_to_le_16(rid)) {
97 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
98 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
99 struct bnxt_tx_queue *txq = bp->tx_queues[i];
101 if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
102 rte_cpu_to_le_16(rid)) {
113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
114 * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
115 * before timeout, we force the done bit for the cleanup to proceed.
116 * Also if cpr is null, do nothing.. The HWRM command is not for a
117 * Tx/Rx/AGG ring cleanup.
120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
121 bool tx, bool rx, bool timeout)
127 done = bnxt_flush_tx_cmp(cpr);
130 done = bnxt_flush_rx_cmp(cpr);
133 PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
136 /* We are about to timeout and still haven't seen the
137 * HWRM done for the Ring free. Force the cleanup.
139 if (!done && timeout) {
141 PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
145 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
146 * Otherwise the cpr would have been valid. So do nothing.
155 * HWRM Functions (sent to HWRM)
156 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
157 * HWRM command times out, or a negative error code if the HWRM
158 * command was failed by the FW.
161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
162 uint32_t msg_len, bool use_kong_mb)
165 struct input *req = msg;
166 struct output *resp = bp->hwrm_cmd_resp_addr;
167 uint32_t *data = msg;
170 uint16_t max_req_len = bp->max_req_len;
171 struct hwrm_short_input short_input = { 0 };
172 uint16_t bar_offset = use_kong_mb ?
173 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
174 uint16_t mb_trigger_offset = use_kong_mb ?
175 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
176 struct bnxt_cp_ring_info *cpr = NULL;
181 /* Do not send HWRM commands to firmware in error state */
182 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
185 timeout = bp->hwrm_cmd_timeout;
187 /* Update the message length for backing store config for new FW. */
188 if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
189 rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
190 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
192 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
193 msg_len > bp->max_req_len) {
194 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
196 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
197 memcpy(short_cmd_req, req, msg_len);
199 short_input.req_type = rte_cpu_to_le_16(req->req_type);
200 short_input.signature = rte_cpu_to_le_16(
201 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
202 short_input.size = rte_cpu_to_le_16(msg_len);
203 short_input.req_addr =
204 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
206 data = (uint32_t *)&short_input;
207 msg_len = sizeof(short_input);
209 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
212 /* Write request msg to hwrm channel */
213 for (i = 0; i < msg_len; i += 4) {
214 bar = (uint8_t *)bp->bar0 + bar_offset + i;
215 rte_write32(*data, bar);
219 /* Zero the rest of the request space */
220 for (; i < max_req_len; i += 4) {
221 bar = (uint8_t *)bp->bar0 + bar_offset + i;
225 /* Ring channel doorbell */
226 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
229 * Make sure the channel doorbell ring command complete before
230 * reading the response to avoid getting stale or invalid
235 /* Check ring flush is done.
236 * This is valid only for Tx and Rx rings (including AGG rings).
237 * The Tx and Rx rings should be freed once the HW confirms all
238 * the internal buffers and BDs associated with the rings are
239 * consumed and the corresponding DMA is handled.
241 if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
242 /* Check if the TxCQ matches. If that fails check if RxCQ
243 * matches. And if neither match, is_rx = false, is_tx = false.
245 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
246 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
248 /* Not a TxCQ. Check if the RxCQ matches. */
250 bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
251 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
259 /* Poll for the valid bit */
260 for (i = 0; i < timeout; i++) {
263 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
265 /* Sanity check on the resp->resp_len */
267 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
268 /* Last byte of resp contains the valid key */
269 valid = (uint8_t *)resp + resp->resp_len - 1;
270 if (*valid == HWRM_RESP_VALID_KEY && done)
277 /* Suppress VER_GET timeout messages during reset recovery */
278 if (bp->flags & BNXT_FLAG_FW_RESET &&
279 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
283 "Error(timeout) sending msg 0x%04x, seq_id %d\n",
284 req->req_type, req->seq_id);
291 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
292 * spinlock, and does initial processing.
294 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
295 * releases the spinlock only if it returns. If the regular int return codes
296 * are not used by the function, HWRM_CHECK_RESULT() should not be used
297 * directly, rather it should be copied and modified to suit the function.
299 * HWRM_UNLOCK() must be called after all response processing is completed.
301 #define HWRM_PREP(req, type, kong) do { \
302 rte_spinlock_lock(&bp->hwrm_lock); \
303 if (bp->hwrm_cmd_resp_addr == NULL) { \
304 rte_spinlock_unlock(&bp->hwrm_lock); \
307 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
308 (req)->req_type = rte_cpu_to_le_16(type); \
309 (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
310 (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
311 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
312 (req)->target_id = rte_cpu_to_le_16(0xffff); \
313 (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
316 #define HWRM_CHECK_RESULT_SILENT() do {\
318 rte_spinlock_unlock(&bp->hwrm_lock); \
321 if (resp->error_code) { \
322 rc = rte_le_to_cpu_16(resp->error_code); \
323 rte_spinlock_unlock(&bp->hwrm_lock); \
328 #define HWRM_CHECK_RESULT() do {\
330 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
331 rte_spinlock_unlock(&bp->hwrm_lock); \
332 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
334 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
336 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
338 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
340 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
346 if (resp->error_code) { \
347 rc = rte_le_to_cpu_16(resp->error_code); \
348 if (resp->resp_len >= 16) { \
349 struct hwrm_err_output *tmp_hwrm_err_op = \
352 "error %d:%d:%08x:%04x\n", \
353 rc, tmp_hwrm_err_op->cmd_err, \
355 tmp_hwrm_err_op->opaque_0), \
357 tmp_hwrm_err_op->opaque_1)); \
359 PMD_DRV_LOG(ERR, "error %d\n", rc); \
361 rte_spinlock_unlock(&bp->hwrm_lock); \
362 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
364 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
366 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
368 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
370 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
378 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
389 bool mailbox = BNXT_USE_CHIMP_MB;
390 struct input *req = msg;
391 struct output *resp = bp->hwrm_cmd_resp_addr;
394 mailbox = BNXT_USE_KONG(bp);
396 HWRM_PREP(req, msg_type, mailbox);
398 rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
403 memcpy(resp_msg, resp, resp_len);
410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
414 uint32_t *tf_response_code,
418 uint32_t response_len)
421 struct hwrm_cfa_tflib_input req = { .req_type = 0 };
422 struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
423 bool mailbox = BNXT_USE_CHIMP_MB;
425 if (msg_len > sizeof(req.tf_req))
429 mailbox = BNXT_USE_KONG(bp);
431 HWRM_PREP(&req, HWRM_TF, mailbox);
432 /* Build request using the user supplied request payload.
433 * TLV request size is checked at build time against HWRM
434 * request max size, thus no checking required.
436 req.tf_type = tf_type;
437 req.tf_subtype = tf_subtype;
438 memcpy(req.tf_req, msg, msg_len);
440 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
443 /* Copy the resp to user provided response buffer */
444 if (response != NULL)
445 /* Post process response data. We need to copy only
446 * the 'payload' as the HWRM data structure really is
447 * HWRM header + msg header + payload and the TFLIB
448 * only provided a payload place holder.
450 if (response_len != 0) {
456 /* Extract the internal tflib response code */
457 *tf_response_code = resp->tf_resp_code;
463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
466 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
467 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
469 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
470 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
473 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
482 struct bnxt_vnic_info *vnic,
484 struct bnxt_vlan_table_entry *vlan_table)
487 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
488 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
491 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
494 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
495 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
497 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
498 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
499 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
500 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
502 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
503 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
505 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
506 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
507 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
508 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
509 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
510 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
513 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
514 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
515 req.vlan_tag_tbl_addr =
516 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
517 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
519 req.mask = rte_cpu_to_le_32(mask);
521 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
531 struct bnxt_vlan_antispoof_table_entry *vlan_table)
534 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
535 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
536 bp->hwrm_cmd_resp_addr;
539 * Older HWRM versions did not support this command, and the set_rx_mask
540 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
541 * removed from set_rx_mask call, and this command was added.
543 * This command is also present from 1.7.8.11 and higher,
546 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
547 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
548 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
553 HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
554 req.fid = rte_cpu_to_le_16(fid);
556 req.vlan_tag_mask_tbl_addr =
557 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
558 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
560 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
569 struct bnxt_filter_info *filter)
572 struct bnxt_filter_info *l2_filter = filter;
573 struct bnxt_vnic_info *vnic = NULL;
574 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
575 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
577 if (filter->fw_l2_filter_id == UINT64_MAX)
580 if (filter->matching_l2_fltr_ptr)
581 l2_filter = filter->matching_l2_fltr_ptr;
583 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
584 filter, l2_filter, l2_filter->l2_ref_cnt);
586 if (l2_filter->l2_ref_cnt == 0)
589 if (l2_filter->l2_ref_cnt > 0)
590 l2_filter->l2_ref_cnt--;
592 if (l2_filter->l2_ref_cnt > 0)
595 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
597 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
599 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
604 filter->fw_l2_filter_id = UINT64_MAX;
605 if (l2_filter->l2_ref_cnt == 0) {
606 vnic = l2_filter->vnic;
608 STAILQ_REMOVE(&vnic->filter, l2_filter,
609 bnxt_filter_info, next);
610 bnxt_free_filter(bp, l2_filter);
617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
619 struct bnxt_filter_info *filter)
622 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
623 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
624 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
625 const struct rte_eth_vmdq_rx_conf *conf =
626 &dev_conf->rx_adv_conf.vmdq_rx_conf;
627 uint32_t enables = 0;
628 uint16_t j = dst_id - 1;
630 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
631 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
632 conf->pool_map[j].pools & (1UL << j)) {
634 "Add vlan %u to vmdq pool %u\n",
635 conf->pool_map[j].vlan_id, j);
637 filter->l2_ivlan = conf->pool_map[j].vlan_id;
639 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
640 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
643 if (filter->fw_l2_filter_id != UINT64_MAX)
644 bnxt_hwrm_clear_l2_filter(bp, filter);
646 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
648 /* PMD does not support XDP and RoCE */
649 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
650 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
651 req.flags = rte_cpu_to_le_32(filter->flags);
653 enables = filter->enables |
654 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
655 req.dst_id = rte_cpu_to_le_16(dst_id);
658 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
659 memcpy(req.l2_addr, filter->l2_addr,
662 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
663 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
666 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
667 req.l2_ovlan = filter->l2_ovlan;
669 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
670 req.l2_ivlan = filter->l2_ivlan;
672 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
673 req.l2_ovlan_mask = filter->l2_ovlan_mask;
675 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
676 req.l2_ivlan_mask = filter->l2_ivlan_mask;
677 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
678 req.src_id = rte_cpu_to_le_32(filter->src_id);
679 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
680 req.src_type = filter->src_type;
681 if (filter->pri_hint) {
682 req.pri_hint = filter->pri_hint;
683 req.l2_filter_id_hint =
684 rte_cpu_to_le_64(filter->l2_filter_id_hint);
687 req.enables = rte_cpu_to_le_32(enables);
689 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
693 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
694 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
697 filter->l2_ref_cnt++;
702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
704 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
705 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
712 HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
715 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
718 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
719 if (ptp->tx_tstamp_en)
720 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
723 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
724 req.flags = rte_cpu_to_le_32(flags);
725 req.enables = rte_cpu_to_le_32
726 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
727 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
729 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
738 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
739 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
740 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
745 HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
747 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
749 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
753 if (!BNXT_CHIP_P5(bp) &&
754 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
757 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
758 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
760 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
764 if (!BNXT_CHIP_P5(bp)) {
765 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
766 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
767 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
768 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
769 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
770 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
771 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
772 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
773 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
774 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
775 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
776 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
777 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
778 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
779 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
780 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
781 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
782 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
791 void bnxt_free_vf_info(struct bnxt *bp)
798 if (bp->pf->vf_info == NULL)
801 for (i = 0; i < bp->pf->max_vfs; i++) {
802 rte_free(bp->pf->vf_info[i].vlan_table);
803 bp->pf->vf_info[i].vlan_table = NULL;
804 rte_free(bp->pf->vf_info[i].vlan_as_table);
805 bp->pf->vf_info[i].vlan_as_table = NULL;
807 rte_free(bp->pf->vf_info);
808 bp->pf->vf_info = NULL;
811 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
813 struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
817 bnxt_free_vf_info(bp);
819 vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
820 if (vf_info == NULL) {
821 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
825 bp->pf->max_vfs = max_vfs;
826 for (i = 0; i < max_vfs; i++) {
827 vf_info[i].fid = bp->pf->first_vf_id + i;
828 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
829 getpagesize(), getpagesize());
830 if (vf_info[i].vlan_table == NULL) {
831 PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
834 rte_mem_lock_page(vf_info[i].vlan_table);
836 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
837 getpagesize(), getpagesize());
838 if (vf_info[i].vlan_as_table == NULL) {
839 PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
842 rte_mem_lock_page(vf_info[i].vlan_as_table);
844 STAILQ_INIT(&vf_info[i].filter);
847 bp->pf->vf_info = vf_info;
851 bnxt_free_vf_info(bp);
855 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
858 struct hwrm_func_qcaps_input req = {.req_type = 0 };
859 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
860 uint16_t new_max_vfs;
863 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
865 req.fid = rte_cpu_to_le_16(0xffff);
867 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
871 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
872 flags = rte_le_to_cpu_32(resp->flags);
874 bp->pf->port_id = resp->port_id;
875 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
876 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
877 new_max_vfs = bp->pdev->max_vfs;
878 if (new_max_vfs != bp->pf->max_vfs) {
879 rc = bnxt_alloc_vf_info(bp, new_max_vfs);
885 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
886 if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
887 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
888 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
890 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
892 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
893 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
894 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
895 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
896 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
897 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
898 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
899 if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
900 bp->max_l2_ctx += bp->max_rx_em_flows;
901 /* TODO: For now, do not support VMDq/RFS on VFs. */
906 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
910 PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
911 bp->max_l2_ctx, bp->max_vnics);
912 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
914 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
915 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
916 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
917 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
919 bnxt_hwrm_ptp_qcfg(bp);
923 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
924 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
926 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
927 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
928 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
931 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
932 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
934 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
935 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
937 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
938 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
946 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
950 rc = __bnxt_hwrm_func_qcaps(bp);
954 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
955 rc = bnxt_alloc_ctx_mem(bp);
960 * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
961 * But the error can be ignored. Return success.
963 rc = bnxt_hwrm_func_resc_qcaps(bp);
965 bp->flags |= BNXT_FLAG_NEW_RM;
971 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
972 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
976 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
977 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
979 HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
981 req.target_id = rte_cpu_to_le_16(0xffff);
983 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
987 flags = rte_le_to_cpu_32(resp->flags);
989 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
990 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
991 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
994 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
995 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
997 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
998 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
1000 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
1007 int bnxt_hwrm_func_reset(struct bnxt *bp)
1010 struct hwrm_func_reset_input req = {.req_type = 0 };
1011 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1013 HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1015 req.enables = rte_cpu_to_le_32(0);
1017 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1019 HWRM_CHECK_RESULT();
1025 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1029 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1030 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1032 if (bp->flags & BNXT_FLAG_REGISTERED)
1035 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1036 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1037 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1038 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1040 /* PFs and trusted VFs should indicate the support of the
1041 * Master capability on non Stingray platform
1043 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1044 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1046 HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1047 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1048 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1049 req.ver_maj = RTE_VER_YEAR;
1050 req.ver_min = RTE_VER_MONTH;
1051 req.ver_upd = RTE_VER_MINOR;
1054 req.enables |= rte_cpu_to_le_32(
1055 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1056 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1057 RTE_MIN(sizeof(req.vf_req_fwd),
1058 sizeof(bp->pf->vf_req_fwd)));
1061 req.flags = rte_cpu_to_le_32(flags);
1063 req.async_event_fwd[0] |=
1064 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1065 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1066 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1067 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1068 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1069 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1070 req.async_event_fwd[0] |=
1071 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1072 req.async_event_fwd[1] |=
1073 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1074 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1076 req.async_event_fwd[1] |=
1077 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1079 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1080 req.async_event_fwd[1] |=
1081 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1083 req.async_event_fwd[2] |=
1084 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST);
1086 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1088 HWRM_CHECK_RESULT();
1090 flags = rte_le_to_cpu_32(resp->flags);
1091 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1092 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1096 bp->flags |= BNXT_FLAG_REGISTERED;
1101 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1103 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1106 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1109 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1114 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1115 struct hwrm_func_vf_cfg_input req = {0};
1117 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1119 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
1120 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
1121 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
1122 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1123 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1125 if (BNXT_HAS_RING_GRPS(bp)) {
1126 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1127 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1130 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1131 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1132 AGG_RING_MULTIPLIER);
1133 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1134 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1136 BNXT_NUM_ASYNC_CPR(bp));
1137 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1138 if (bp->vf_resv_strategy ==
1139 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1140 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1141 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1142 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1143 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1144 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1145 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1146 } else if (bp->vf_resv_strategy ==
1147 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1148 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1149 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1153 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1154 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1155 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1156 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1157 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1158 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1160 if (test && BNXT_HAS_RING_GRPS(bp))
1161 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1163 req.flags = rte_cpu_to_le_32(flags);
1164 req.enables |= rte_cpu_to_le_32(enables);
1166 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1169 HWRM_CHECK_RESULT_SILENT();
1171 HWRM_CHECK_RESULT();
1177 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1180 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1181 struct hwrm_func_resource_qcaps_input req = {0};
1183 HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1184 req.fid = rte_cpu_to_le_16(0xffff);
1186 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1188 HWRM_CHECK_RESULT_SILENT();
1190 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1191 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1192 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1193 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1194 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1195 /* func_resource_qcaps does not return max_rx_em_flows.
1196 * So use the value provided by func_qcaps.
1198 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1199 if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1200 bp->max_l2_ctx += bp->max_rx_em_flows;
1201 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1202 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1203 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1204 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1205 if (bp->vf_resv_strategy >
1206 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1207 bp->vf_resv_strategy =
1208 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1214 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1217 struct hwrm_ver_get_input req = {.req_type = 0 };
1218 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1219 uint32_t fw_version;
1220 uint16_t max_resp_len;
1221 char type[RTE_MEMZONE_NAMESIZE];
1222 uint32_t dev_caps_cfg;
1224 bp->max_req_len = HWRM_MAX_REQ_LEN;
1225 bp->hwrm_cmd_timeout = timeout;
1226 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1228 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1229 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1230 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1232 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1234 if (bp->flags & BNXT_FLAG_FW_RESET)
1235 HWRM_CHECK_RESULT_SILENT();
1237 HWRM_CHECK_RESULT();
1239 if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
1244 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1245 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1246 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1247 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1248 resp->hwrm_fw_rsvd_8b);
1249 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1250 (resp->hwrm_fw_min_8b << 16) |
1251 (resp->hwrm_fw_bld_8b << 8) |
1252 resp->hwrm_fw_rsvd_8b;
1253 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1254 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1256 fw_version = resp->hwrm_intf_maj_8b << 16;
1257 fw_version |= resp->hwrm_intf_min_8b << 8;
1258 fw_version |= resp->hwrm_intf_upd_8b;
1259 bp->hwrm_spec_code = fw_version;
1261 /* def_req_timeout value is in milliseconds */
1262 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1263 /* convert timeout to usec */
1264 bp->hwrm_cmd_timeout *= 1000;
1265 if (!bp->hwrm_cmd_timeout)
1266 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1268 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1269 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1274 if (bp->max_req_len > resp->max_req_win_len) {
1275 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1280 bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1282 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1283 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1284 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1285 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1287 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1288 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1290 RTE_VERIFY(max_resp_len <= bp->max_resp_len);
1291 bp->max_resp_len = max_resp_len;
1294 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1296 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1297 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1298 bp->flags |= BNXT_FLAG_SHORT_CMD;
1301 if (((dev_caps_cfg &
1302 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1304 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1305 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1306 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1307 bp->pdev->addr.domain, bp->pdev->addr.bus,
1308 bp->pdev->addr.devid, bp->pdev->addr.function);
1310 rte_free(bp->hwrm_short_cmd_req_addr);
1312 bp->hwrm_short_cmd_req_addr =
1313 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1314 if (bp->hwrm_short_cmd_req_addr == NULL) {
1318 bp->hwrm_short_cmd_req_dma_addr =
1319 rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1320 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1321 rte_free(bp->hwrm_short_cmd_req_addr);
1323 "Unable to map buffer to physical memory.\n");
1329 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1330 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1331 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1334 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1335 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1337 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1338 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1339 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1343 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1344 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1345 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1353 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1356 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1357 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1359 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1362 HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1365 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1367 HWRM_CHECK_RESULT();
1370 PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1371 bp->eth_dev->data->port_id);
1376 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1379 struct hwrm_port_phy_cfg_input req = {0};
1380 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1381 uint32_t enables = 0;
1383 HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1385 if (conf->link_up) {
1386 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1387 if (bp->link_info->auto_mode && conf->link_speed) {
1388 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1389 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1392 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1394 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1395 * any auto mode, even "none".
1397 if (!conf->link_speed) {
1398 /* No speeds specified. Enable AutoNeg - all speeds */
1399 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1401 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1403 if (bp->link_info->link_signal_mode) {
1405 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1406 req.force_pam4_link_speed =
1407 rte_cpu_to_le_16(conf->link_speed);
1409 req.force_link_speed =
1410 rte_cpu_to_le_16(conf->link_speed);
1413 /* AutoNeg - Advertise speeds specified. */
1414 if (conf->auto_link_speed_mask &&
1415 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1417 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1418 req.auto_link_speed_mask =
1419 conf->auto_link_speed_mask;
1420 if (conf->auto_pam4_link_speeds) {
1422 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1423 req.auto_link_pam4_speed_mask =
1424 conf->auto_pam4_link_speeds;
1427 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1430 if (conf->auto_link_speed &&
1431 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1433 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1435 req.auto_duplex = conf->duplex;
1436 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1437 req.auto_pause = conf->auto_pause;
1438 req.force_pause = conf->force_pause;
1439 /* Set force_pause if there is no auto or if there is a force */
1440 if (req.auto_pause && !req.force_pause)
1441 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1443 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1445 req.enables = rte_cpu_to_le_32(enables);
1448 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1449 PMD_DRV_LOG(INFO, "Force Link Down\n");
1452 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1454 HWRM_CHECK_RESULT();
1460 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1461 struct bnxt_link_info *link_info)
1464 struct hwrm_port_phy_qcfg_input req = {0};
1465 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1467 HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1469 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1471 HWRM_CHECK_RESULT();
1473 link_info->phy_link_status = resp->link;
1474 link_info->link_up =
1475 (link_info->phy_link_status ==
1476 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1477 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1478 link_info->duplex = resp->duplex_cfg;
1479 link_info->pause = resp->pause;
1480 link_info->auto_pause = resp->auto_pause;
1481 link_info->force_pause = resp->force_pause;
1482 link_info->auto_mode = resp->auto_mode;
1483 link_info->phy_type = resp->phy_type;
1484 link_info->media_type = resp->media_type;
1486 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1487 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1488 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1489 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1490 link_info->phy_ver[0] = resp->phy_maj;
1491 link_info->phy_ver[1] = resp->phy_min;
1492 link_info->phy_ver[2] = resp->phy_bld;
1493 link_info->link_signal_mode =
1494 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1495 link_info->force_pam4_link_speed =
1496 rte_le_to_cpu_16(resp->force_pam4_link_speed);
1497 link_info->support_pam4_speeds =
1498 rte_le_to_cpu_16(resp->support_pam4_speeds);
1499 link_info->auto_pam4_link_speeds =
1500 rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1503 PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1504 link_info->link_speed, link_info->auto_mode,
1505 link_info->auto_link_speed, link_info->auto_link_speed_mask,
1506 link_info->support_speeds, link_info->force_link_speed);
1507 PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1508 link_info->link_signal_mode,
1509 link_info->auto_pam4_link_speeds,
1510 link_info->support_pam4_speeds,
1511 link_info->force_pam4_link_speed);
1515 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1518 struct hwrm_port_phy_qcaps_input req = {0};
1519 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1520 struct bnxt_link_info *link_info = bp->link_info;
1522 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1525 HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1527 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1529 HWRM_CHECK_RESULT_SILENT();
1531 bp->port_cnt = resp->port_cnt;
1532 if (resp->supported_speeds_auto_mode)
1533 link_info->support_auto_speeds =
1534 rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1535 if (resp->supported_pam4_speeds_auto_mode)
1536 link_info->support_pam4_auto_speeds =
1537 rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1544 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1548 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1549 if (bp->tx_cos_queue[i].profile ==
1550 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1551 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1558 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1562 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1563 if (bp->tx_cos_queue[i].profile !=
1564 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1565 bp->tx_cos_queue[i].id !=
1566 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1567 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1573 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1576 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1577 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1578 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1582 HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1584 req.flags = rte_cpu_to_le_32(dir);
1585 /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1586 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1587 !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1589 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1590 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1592 HWRM_CHECK_RESULT();
1594 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1595 GET_TX_QUEUE_INFO(0);
1596 GET_TX_QUEUE_INFO(1);
1597 GET_TX_QUEUE_INFO(2);
1598 GET_TX_QUEUE_INFO(3);
1599 GET_TX_QUEUE_INFO(4);
1600 GET_TX_QUEUE_INFO(5);
1601 GET_TX_QUEUE_INFO(6);
1602 GET_TX_QUEUE_INFO(7);
1604 GET_RX_QUEUE_INFO(0);
1605 GET_RX_QUEUE_INFO(1);
1606 GET_RX_QUEUE_INFO(2);
1607 GET_RX_QUEUE_INFO(3);
1608 GET_RX_QUEUE_INFO(4);
1609 GET_RX_QUEUE_INFO(5);
1610 GET_RX_QUEUE_INFO(6);
1611 GET_RX_QUEUE_INFO(7);
1616 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1619 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1620 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1624 /* iterate and find the COSq profile to use for Tx */
1625 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1626 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1627 if (bp->tx_cos_queue[i].id != 0xff)
1628 bp->tx_cosq_id[j++] =
1629 bp->tx_cos_queue[i].id;
1632 /* When CoS classification is disabled, for normal NIC
1633 * operations, ideally we should look to use LOSSY.
1634 * If not found, fallback to the first valid profile
1636 if (!bnxt_find_lossy_profile(bp))
1637 bnxt_find_first_valid_profile(bp);
1642 bp->max_tc = resp->max_configurable_queues;
1643 bp->max_lltc = resp->max_configurable_lossless_queues;
1644 if (bp->max_tc > BNXT_MAX_QUEUE)
1645 bp->max_tc = BNXT_MAX_QUEUE;
1646 bp->max_q = bp->max_tc;
1648 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1649 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1657 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1658 struct bnxt_ring *ring,
1659 uint32_t ring_type, uint32_t map_index,
1660 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1661 uint16_t tx_cosq_id)
1664 uint32_t enables = 0;
1665 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1666 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1667 struct rte_mempool *mb_pool;
1668 uint16_t rx_buf_size;
1670 HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1672 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1673 req.fbo = rte_cpu_to_le_32(0);
1674 /* Association of ring index with doorbell index */
1675 req.logical_id = rte_cpu_to_le_16(map_index);
1676 req.length = rte_cpu_to_le_32(ring->ring_size);
1678 switch (ring_type) {
1679 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1680 req.ring_type = ring_type;
1681 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1682 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1683 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1684 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1686 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1688 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1689 req.ring_type = ring_type;
1690 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1691 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1692 if (BNXT_CHIP_P5(bp)) {
1693 mb_pool = bp->rx_queues[0]->mb_pool;
1694 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1695 RTE_PKTMBUF_HEADROOM;
1696 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1697 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1699 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1701 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1703 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1705 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1706 req.ring_type = ring_type;
1707 if (BNXT_HAS_NQ(bp)) {
1708 /* Association of cp ring with nq */
1709 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1711 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1713 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1715 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1716 req.ring_type = ring_type;
1717 req.page_size = BNXT_PAGE_SHFT;
1718 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1720 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1721 req.ring_type = ring_type;
1722 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1724 mb_pool = bp->rx_queues[0]->mb_pool;
1725 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1726 RTE_PKTMBUF_HEADROOM;
1727 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1728 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1730 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1731 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1732 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1733 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1736 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1741 req.enables = rte_cpu_to_le_32(enables);
1743 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1745 if (rc || resp->error_code) {
1746 if (rc == 0 && resp->error_code)
1747 rc = rte_le_to_cpu_16(resp->error_code);
1748 switch (ring_type) {
1749 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1751 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1754 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1756 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1759 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1761 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1765 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1767 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1770 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1772 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1776 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1782 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1787 int bnxt_hwrm_ring_free(struct bnxt *bp,
1788 struct bnxt_ring *ring, uint32_t ring_type,
1789 uint16_t cp_ring_id)
1792 struct hwrm_ring_free_input req = {.req_type = 0 };
1793 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1795 HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1797 req.ring_type = ring_type;
1798 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1799 req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1801 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1803 if (rc || resp->error_code) {
1804 if (rc == 0 && resp->error_code)
1805 rc = rte_le_to_cpu_16(resp->error_code);
1808 switch (ring_type) {
1809 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1810 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1813 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1814 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1817 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1818 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1821 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1823 "hwrm_ring_free nq failed. rc:%d\n", rc);
1825 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1827 "hwrm_ring_free agg failed. rc:%d\n", rc);
1830 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1838 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1841 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1842 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1844 HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1846 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1847 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1848 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1849 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1851 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1853 HWRM_CHECK_RESULT();
1855 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1862 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1865 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1866 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1868 HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1870 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1872 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1874 HWRM_CHECK_RESULT();
1877 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1881 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1884 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1885 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1887 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1890 HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1892 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1894 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1896 HWRM_CHECK_RESULT();
1902 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1905 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1906 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1908 HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1910 req.update_period_ms = rte_cpu_to_le_32(0);
1912 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1914 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1916 HWRM_CHECK_RESULT();
1918 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1925 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1928 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1929 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1931 HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1933 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1935 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1937 HWRM_CHECK_RESULT();
1943 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1946 struct hwrm_vnic_alloc_input req = { 0 };
1947 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1949 if (!BNXT_HAS_RING_GRPS(bp))
1950 goto skip_ring_grps;
1952 /* map ring groups to this vnic */
1953 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1954 vnic->start_grp_id, vnic->end_grp_id);
1955 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1956 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1958 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1959 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1960 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1961 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1964 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1965 HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1967 if (vnic->func_default)
1969 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1970 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1972 HWRM_CHECK_RESULT();
1974 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1976 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1980 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1981 struct bnxt_vnic_info *vnic,
1982 struct bnxt_plcmodes_cfg *pmode)
1985 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1986 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1988 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1990 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1992 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1994 HWRM_CHECK_RESULT();
1996 pmode->flags = rte_le_to_cpu_32(resp->flags);
1997 /* dflt_vnic bit doesn't exist in the _cfg command */
1998 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1999 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
2000 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2001 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2008 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2009 struct bnxt_vnic_info *vnic,
2010 struct bnxt_plcmodes_cfg *pmode)
2013 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2014 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2016 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2017 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2021 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2023 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2024 req.flags = rte_cpu_to_le_32(pmode->flags);
2025 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2026 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2027 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2028 req.enables = rte_cpu_to_le_32(
2029 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2030 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2031 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2034 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2036 HWRM_CHECK_RESULT();
2042 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2045 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2046 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2047 struct bnxt_plcmodes_cfg pmodes = { 0 };
2048 uint32_t ctx_enable_flag = 0;
2049 uint32_t enables = 0;
2051 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2052 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2056 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2060 HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2062 if (BNXT_CHIP_P5(bp)) {
2063 int dflt_rxq = vnic->start_grp_id;
2064 struct bnxt_rx_ring_info *rxr;
2065 struct bnxt_cp_ring_info *cpr;
2066 struct bnxt_rx_queue *rxq;
2070 * The first active receive ring is used as the VNIC
2071 * default receive ring. If there are no active receive
2072 * rings (all corresponding receive queues are stopped),
2073 * the first receive ring is used.
2075 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2076 rxq = bp->eth_dev->data->rx_queues[i];
2077 if (rxq->rx_started) {
2083 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2087 req.default_rx_ring_id =
2088 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2089 req.default_cmpl_ring_id =
2090 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2091 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2092 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2093 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2094 enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2095 req.rx_csum_v2_mode =
2096 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2101 /* Only RSS support for now TBD: COS & LB */
2102 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2103 if (vnic->lb_rule != 0xffff)
2104 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2105 if (vnic->cos_rule != 0xffff)
2106 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2107 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2108 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2109 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2111 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2112 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2113 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2116 enables |= ctx_enable_flag;
2117 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2118 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2119 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2120 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2123 req.enables = rte_cpu_to_le_32(enables);
2124 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2125 req.mru = rte_cpu_to_le_16(vnic->mru);
2126 /* Configure default VNIC only once. */
2127 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2129 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2130 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2132 if (vnic->vlan_strip)
2134 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2137 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2138 if (vnic->rss_dflt_cr)
2139 req.flags |= rte_cpu_to_le_32(
2140 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2142 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2144 HWRM_CHECK_RESULT();
2147 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2152 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2156 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2157 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2159 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2160 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2163 HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2166 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2167 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2168 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2170 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2172 HWRM_CHECK_RESULT();
2174 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2175 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2176 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2177 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2178 vnic->mru = rte_le_to_cpu_16(resp->mru);
2179 vnic->func_default = rte_le_to_cpu_32(
2180 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2181 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2182 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2183 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2184 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2185 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2186 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2193 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2194 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2198 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2199 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2200 bp->hwrm_cmd_resp_addr;
2202 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2204 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2205 HWRM_CHECK_RESULT();
2207 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2208 if (!BNXT_HAS_RING_GRPS(bp))
2209 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2210 else if (ctx_idx == 0)
2211 vnic->rss_rule = ctx_id;
2219 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2220 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2223 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2224 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2225 bp->hwrm_cmd_resp_addr;
2227 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2228 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2231 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2233 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2235 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2237 HWRM_CHECK_RESULT();
2243 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2247 if (BNXT_CHIP_P5(bp)) {
2250 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2251 rc = _bnxt_hwrm_vnic_ctx_free(bp,
2253 vnic->fw_grp_ids[j]);
2254 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2256 vnic->num_lb_ctxts = 0;
2258 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2259 vnic->rss_rule = INVALID_HW_RING_ID;
2265 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2268 struct hwrm_vnic_free_input req = {.req_type = 0 };
2269 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2271 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2272 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2276 HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2278 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2280 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2282 HWRM_CHECK_RESULT();
2285 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2286 /* Configure default VNIC again if necessary. */
2287 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2288 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2294 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2298 int nr_ctxs = vnic->num_lb_ctxts;
2299 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2300 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2302 for (i = 0; i < nr_ctxs; i++) {
2303 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2305 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2306 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2307 req.hash_mode_flags = vnic->hash_mode;
2309 req.hash_key_tbl_addr =
2310 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2312 req.ring_grp_tbl_addr =
2313 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2314 i * HW_HASH_INDEX_SIZE);
2315 req.ring_table_pair_index = i;
2316 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2318 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2321 HWRM_CHECK_RESULT();
2328 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2329 struct bnxt_vnic_info *vnic)
2332 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2333 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2335 if (!vnic->rss_table)
2338 if (BNXT_CHIP_P5(bp))
2339 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2341 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2343 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2344 req.hash_mode_flags = vnic->hash_mode;
2346 req.ring_grp_tbl_addr =
2347 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2348 req.hash_key_tbl_addr =
2349 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2350 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2351 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2353 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2355 HWRM_CHECK_RESULT();
2361 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2362 struct bnxt_vnic_info *vnic)
2365 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2366 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2369 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2370 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2374 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2376 req.flags = rte_cpu_to_le_32(
2377 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2379 req.enables = rte_cpu_to_le_32(
2380 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2382 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2383 size -= RTE_PKTMBUF_HEADROOM;
2384 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2386 req.jumbo_thresh = rte_cpu_to_le_16(size);
2387 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2389 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2391 HWRM_CHECK_RESULT();
2397 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2398 struct bnxt_vnic_info *vnic, bool enable)
2401 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2402 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2404 if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2406 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2410 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2411 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2415 HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2418 req.enables = rte_cpu_to_le_32(
2419 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2420 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2421 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2422 req.flags = rte_cpu_to_le_32(
2423 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2424 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2425 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2426 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2427 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2428 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2429 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2430 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2431 req.min_agg_len = rte_cpu_to_le_32(512);
2433 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2435 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2437 HWRM_CHECK_RESULT();
2443 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2445 struct hwrm_func_cfg_input req = {0};
2446 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2449 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2450 req.enables = rte_cpu_to_le_32(
2451 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2452 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2453 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2455 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2457 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2458 HWRM_CHECK_RESULT();
2461 bp->pf->vf_info[vf].random_mac = false;
2466 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2470 struct hwrm_func_qstats_input req = {.req_type = 0};
2471 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2473 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2475 req.fid = rte_cpu_to_le_16(fid);
2477 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2479 HWRM_CHECK_RESULT();
2482 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2489 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2490 struct rte_eth_stats *stats,
2491 struct hwrm_func_qstats_output *func_qstats)
2494 struct hwrm_func_qstats_input req = {.req_type = 0};
2495 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2497 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2499 req.fid = rte_cpu_to_le_16(fid);
2501 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2503 HWRM_CHECK_RESULT();
2505 memcpy(func_qstats, resp,
2506 sizeof(struct hwrm_func_qstats_output));
2511 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2512 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2513 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2514 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2515 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2516 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2518 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2519 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2520 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2521 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2522 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2523 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2525 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2526 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2527 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2535 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2538 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2539 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2541 HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2543 req.fid = rte_cpu_to_le_16(fid);
2545 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2547 HWRM_CHECK_RESULT();
2553 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2558 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2559 struct bnxt_tx_queue *txq;
2560 struct bnxt_rx_queue *rxq;
2561 struct bnxt_cp_ring_info *cpr;
2563 if (i >= bp->rx_cp_nr_rings) {
2564 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2567 rxq = bp->rx_queues[i];
2571 rc = bnxt_hwrm_stat_clear(bp, cpr);
2579 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2583 struct bnxt_cp_ring_info *cpr;
2585 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2587 if (i >= bp->rx_cp_nr_rings) {
2588 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2590 cpr = bp->rx_queues[i]->cp_ring;
2591 if (BNXT_HAS_RING_GRPS(bp))
2592 bp->grp_info[i].fw_stats_ctx = -1;
2594 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2595 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2596 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2604 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2609 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2610 struct bnxt_tx_queue *txq;
2611 struct bnxt_rx_queue *rxq;
2612 struct bnxt_cp_ring_info *cpr;
2614 if (i >= bp->rx_cp_nr_rings) {
2615 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2618 rxq = bp->rx_queues[i];
2622 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr);
2631 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2636 if (!BNXT_HAS_RING_GRPS(bp))
2639 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2641 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2644 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2652 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2654 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2656 bnxt_hwrm_ring_free(bp, cp_ring,
2657 HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2658 INVALID_HW_RING_ID);
2659 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2660 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2661 sizeof(*cpr->cp_desc_ring));
2662 cpr->cp_raw_cons = 0;
2666 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2668 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2670 bnxt_hwrm_ring_free(bp, cp_ring,
2671 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2672 INVALID_HW_RING_ID);
2673 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2674 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2675 sizeof(*cpr->cp_desc_ring));
2676 cpr->cp_raw_cons = 0;
2680 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2682 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2683 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2684 struct bnxt_ring *ring = rxr->rx_ring_struct;
2685 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2687 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2688 bnxt_hwrm_ring_free(bp, ring,
2689 HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2690 cpr->cp_ring_struct->fw_ring_id);
2691 ring->fw_ring_id = INVALID_HW_RING_ID;
2692 if (BNXT_HAS_RING_GRPS(bp))
2693 bp->grp_info[queue_index].rx_fw_ring_id =
2696 ring = rxr->ag_ring_struct;
2697 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2698 bnxt_hwrm_ring_free(bp, ring,
2700 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2701 HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2702 cpr->cp_ring_struct->fw_ring_id);
2703 if (BNXT_HAS_RING_GRPS(bp))
2704 bp->grp_info[queue_index].ag_fw_ring_id =
2707 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2708 bnxt_free_cp_ring(bp, cpr);
2710 if (BNXT_HAS_RING_GRPS(bp))
2711 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2714 int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int queue_index)
2717 struct hwrm_ring_reset_input req = {.req_type = 0 };
2718 struct hwrm_ring_reset_output *resp = bp->hwrm_cmd_resp_addr;
2720 HWRM_PREP(&req, HWRM_RING_RESET, BNXT_USE_CHIMP_MB);
2722 req.ring_type = HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP;
2723 req.ring_id = rte_cpu_to_le_16(bp->grp_info[queue_index].fw_grp_id);
2724 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2726 HWRM_CHECK_RESULT();
2734 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2738 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2739 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2740 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2741 struct bnxt_ring *ring = txr->tx_ring_struct;
2742 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2744 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2745 bnxt_hwrm_ring_free(bp, ring,
2746 HWRM_RING_FREE_INPUT_RING_TYPE_TX,
2747 cpr->cp_ring_struct->fw_ring_id);
2748 ring->fw_ring_id = INVALID_HW_RING_ID;
2749 memset(txr->tx_desc_ring, 0,
2750 txr->tx_ring_struct->ring_size *
2751 sizeof(*txr->tx_desc_ring));
2752 memset(txr->tx_buf_ring, 0,
2753 txr->tx_ring_struct->ring_size *
2754 sizeof(*txr->tx_buf_ring));
2755 txr->tx_raw_prod = 0;
2756 txr->tx_raw_cons = 0;
2758 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2759 bnxt_free_cp_ring(bp, cpr);
2760 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2764 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2765 bnxt_free_hwrm_rx_ring(bp, i);
2770 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2775 if (!BNXT_HAS_RING_GRPS(bp))
2778 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2779 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2787 * HWRM utility functions
2790 void bnxt_free_hwrm_resources(struct bnxt *bp)
2792 /* Release memzone */
2793 rte_free(bp->hwrm_cmd_resp_addr);
2794 rte_free(bp->hwrm_short_cmd_req_addr);
2795 bp->hwrm_cmd_resp_addr = NULL;
2796 bp->hwrm_short_cmd_req_addr = NULL;
2797 bp->hwrm_cmd_resp_dma_addr = 0;
2798 bp->hwrm_short_cmd_req_dma_addr = 0;
2801 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2803 struct rte_pci_device *pdev = bp->pdev;
2804 char type[RTE_MEMZONE_NAMESIZE];
2806 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2807 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2808 bp->max_resp_len = BNXT_PAGE_SIZE;
2809 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2810 if (bp->hwrm_cmd_resp_addr == NULL)
2812 bp->hwrm_cmd_resp_dma_addr =
2813 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2814 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2816 "unable to map response address to physical memory\n");
2819 rte_spinlock_init(&bp->hwrm_lock);
2825 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2829 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2830 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2833 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2834 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2839 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2844 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2846 struct bnxt_filter_info *filter;
2849 STAILQ_FOREACH(filter, &vnic->filter, next) {
2850 rc = bnxt_clear_one_vnic_filter(bp, filter);
2851 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2852 bnxt_free_filter(bp, filter);
2858 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2860 struct bnxt_filter_info *filter;
2861 struct rte_flow *flow;
2864 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2865 flow = STAILQ_FIRST(&vnic->flow_list);
2866 filter = flow->filter;
2867 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2868 rc = bnxt_clear_one_vnic_filter(bp, filter);
2870 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2876 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2878 struct bnxt_filter_info *filter;
2881 STAILQ_FOREACH(filter, &vnic->filter, next) {
2882 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2883 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2885 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2886 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2889 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2898 bnxt_free_tunnel_ports(struct bnxt *bp)
2900 if (bp->vxlan_port_cnt)
2901 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2902 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2904 if (bp->geneve_port_cnt)
2905 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2906 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2909 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2913 if (bp->vnic_info == NULL)
2917 * Cleanup VNICs in reverse order, to make sure the L2 filter
2918 * from vnic0 is last to be cleaned up.
2920 for (i = bp->max_vnics - 1; i >= 0; i--) {
2921 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2923 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2926 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2928 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2930 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2932 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2934 bnxt_hwrm_vnic_free(bp, vnic);
2936 rte_free(vnic->fw_grp_ids);
2938 /* Ring resources */
2939 bnxt_free_all_hwrm_rings(bp);
2940 bnxt_free_all_hwrm_ring_grps(bp);
2941 bnxt_free_all_hwrm_stat_ctxs(bp);
2942 bnxt_free_tunnel_ports(bp);
2945 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2947 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2949 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2950 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2952 switch (conf_link_speed) {
2953 case ETH_LINK_SPEED_10M_HD:
2954 case ETH_LINK_SPEED_100M_HD:
2956 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2958 return hw_link_duplex;
2961 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2966 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2969 uint16_t eth_link_speed = 0;
2971 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2972 return ETH_LINK_SPEED_AUTONEG;
2974 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2975 case ETH_LINK_SPEED_100M:
2976 case ETH_LINK_SPEED_100M_HD:
2979 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2981 case ETH_LINK_SPEED_1G:
2983 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2985 case ETH_LINK_SPEED_2_5G:
2987 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2989 case ETH_LINK_SPEED_10G:
2991 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2993 case ETH_LINK_SPEED_20G:
2995 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2997 case ETH_LINK_SPEED_25G:
2999 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
3001 case ETH_LINK_SPEED_40G:
3003 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
3005 case ETH_LINK_SPEED_50G:
3006 eth_link_speed = pam4_link ?
3007 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
3008 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
3010 case ETH_LINK_SPEED_100G:
3011 eth_link_speed = pam4_link ?
3012 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
3013 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
3015 case ETH_LINK_SPEED_200G:
3017 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3021 "Unsupported link speed %d; default to AUTO\n",
3025 return eth_link_speed;
3028 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
3029 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
3030 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
3031 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
3032 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
3034 static int bnxt_validate_link_speed(struct bnxt *bp)
3036 uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3037 uint16_t port_id = bp->eth_dev->data->port_id;
3038 uint32_t link_speed_capa;
3041 if (link_speed == ETH_LINK_SPEED_AUTONEG)
3044 link_speed_capa = bnxt_get_speed_capabilities(bp);
3046 if (link_speed & ETH_LINK_SPEED_FIXED) {
3047 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
3049 if (one_speed & (one_speed - 1)) {
3051 "Invalid advertised speeds (%u) for port %u\n",
3052 link_speed, port_id);
3055 if ((one_speed & link_speed_capa) != one_speed) {
3057 "Unsupported advertised speed (%u) for port %u\n",
3058 link_speed, port_id);
3062 if (!(link_speed & link_speed_capa)) {
3064 "Unsupported advertised speeds (%u) for port %u\n",
3065 link_speed, port_id);
3073 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3077 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
3078 if (bp->link_info->support_speeds)
3079 return bp->link_info->support_speeds;
3080 link_speed = BNXT_SUPPORTED_SPEEDS;
3083 if (link_speed & ETH_LINK_SPEED_100M)
3084 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3085 if (link_speed & ETH_LINK_SPEED_100M_HD)
3086 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3087 if (link_speed & ETH_LINK_SPEED_1G)
3088 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3089 if (link_speed & ETH_LINK_SPEED_2_5G)
3090 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3091 if (link_speed & ETH_LINK_SPEED_10G)
3092 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3093 if (link_speed & ETH_LINK_SPEED_20G)
3094 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3095 if (link_speed & ETH_LINK_SPEED_25G)
3096 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3097 if (link_speed & ETH_LINK_SPEED_40G)
3098 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3099 if (link_speed & ETH_LINK_SPEED_50G)
3100 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3101 if (link_speed & ETH_LINK_SPEED_100G)
3102 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3103 if (link_speed & ETH_LINK_SPEED_200G)
3104 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3108 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3110 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
3112 switch (hw_link_speed) {
3113 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3114 eth_link_speed = ETH_SPEED_NUM_100M;
3116 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3117 eth_link_speed = ETH_SPEED_NUM_1G;
3119 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3120 eth_link_speed = ETH_SPEED_NUM_2_5G;
3122 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3123 eth_link_speed = ETH_SPEED_NUM_10G;
3125 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3126 eth_link_speed = ETH_SPEED_NUM_20G;
3128 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3129 eth_link_speed = ETH_SPEED_NUM_25G;
3131 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3132 eth_link_speed = ETH_SPEED_NUM_40G;
3134 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3135 eth_link_speed = ETH_SPEED_NUM_50G;
3137 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3138 eth_link_speed = ETH_SPEED_NUM_100G;
3140 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3141 eth_link_speed = ETH_SPEED_NUM_200G;
3143 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3145 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3149 return eth_link_speed;
3152 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3154 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3156 switch (hw_link_duplex) {
3157 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3158 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3160 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3162 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3163 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3166 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3170 return eth_link_duplex;
3173 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3176 struct bnxt_link_info *link_info = bp->link_info;
3178 rc = bnxt_hwrm_port_phy_qcaps(bp);
3180 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3182 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3184 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3188 if (link_info->link_speed)
3190 bnxt_parse_hw_link_speed(link_info->link_speed);
3192 link->link_speed = ETH_SPEED_NUM_NONE;
3193 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3194 link->link_status = link_info->link_up;
3195 link->link_autoneg = link_info->auto_mode ==
3196 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3197 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3202 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3205 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3206 struct bnxt_link_info link_req;
3207 uint16_t speed, autoneg;
3209 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3212 rc = bnxt_validate_link_speed(bp);
3216 memset(&link_req, 0, sizeof(link_req));
3217 link_req.link_up = link_up;
3221 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3222 if (BNXT_CHIP_P5(bp) &&
3223 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3224 /* 40G is not supported as part of media auto detect.
3225 * The speed should be forced and autoneg disabled
3226 * to configure 40G speed.
3228 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3232 /* No auto speeds and no auto_pam4_link. Disable autoneg */
3233 if (bp->link_info->auto_link_speed == 0 &&
3234 bp->link_info->link_signal_mode &&
3235 bp->link_info->auto_pam4_link_speeds == 0)
3238 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3239 bp->link_info->link_signal_mode);
3240 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3241 /* Autoneg can be done only when the FW allows.
3242 * When user configures fixed speed of 40G and later changes to
3243 * any other speed, auto_link_speed/force_link_speed is still set
3244 * to 40G until link comes up at new speed.
3247 !(!BNXT_CHIP_P5(bp) &&
3248 (bp->link_info->auto_link_speed ||
3249 bp->link_info->force_link_speed))) {
3250 link_req.phy_flags |=
3251 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3252 link_req.auto_link_speed_mask =
3253 bnxt_parse_eth_link_speed_mask(bp,
3254 dev_conf->link_speeds);
3256 if (bp->link_info->phy_type ==
3257 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3258 bp->link_info->phy_type ==
3259 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3260 bp->link_info->media_type ==
3261 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3262 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3266 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3267 /* If user wants a particular speed try that first. */
3269 link_req.link_speed = speed;
3270 else if (bp->link_info->force_pam4_link_speed)
3271 link_req.link_speed =
3272 bp->link_info->force_pam4_link_speed;
3273 else if (bp->link_info->auto_pam4_link_speeds)
3274 link_req.link_speed =
3275 bp->link_info->auto_pam4_link_speeds;
3276 else if (bp->link_info->support_pam4_speeds)
3277 link_req.link_speed =
3278 bp->link_info->support_pam4_speeds;
3279 else if (bp->link_info->force_link_speed)
3280 link_req.link_speed = bp->link_info->force_link_speed;
3282 link_req.link_speed = bp->link_info->auto_link_speed;
3283 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3284 * zero. Use the auto_link_speed.
3286 if (bp->link_info->auto_link_speed != 0 &&
3287 bp->link_info->auto_pam4_link_speeds == 0)
3288 link_req.link_speed = bp->link_info->auto_link_speed;
3290 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3291 link_req.auto_pause = bp->link_info->auto_pause;
3292 link_req.force_pause = bp->link_info->force_pause;
3295 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3298 "Set link config failed with rc %d\n", rc);
3306 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3308 struct hwrm_func_qcfg_input req = {0};
3309 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3312 bp->func_svif = BNXT_SVIF_INVALID;
3315 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3316 req.fid = rte_cpu_to_le_16(0xffff);
3318 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3320 HWRM_CHECK_RESULT();
3322 /* Hard Coded.. 0xfff VLAN ID mask */
3323 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3325 svif_info = rte_le_to_cpu_16(resp->svif_info);
3326 if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3327 bp->func_svif = svif_info &
3328 HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3330 flags = rte_le_to_cpu_16(resp->flags);
3331 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3332 bp->flags |= BNXT_FLAG_MULTI_HOST;
3335 !BNXT_VF_IS_TRUSTED(bp) &&
3336 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3337 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3338 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3339 } else if (BNXT_VF(bp) &&
3340 BNXT_VF_IS_TRUSTED(bp) &&
3341 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3342 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3343 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3347 *mtu = rte_le_to_cpu_16(resp->mtu);
3349 switch (resp->port_partition_type) {
3350 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3351 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3352 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3354 bp->flags |= BNXT_FLAG_NPAR_PF;
3357 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3361 bp->legacy_db_size =
3362 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3369 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3371 struct hwrm_func_qcfg_input req = {0};
3372 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3375 if (!BNXT_VF_IS_TRUSTED(bp))
3381 bp->parent->fid = BNXT_PF_FID_INVALID;
3383 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3385 req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3387 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3389 HWRM_CHECK_RESULT_SILENT();
3391 memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3392 bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3393 bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3394 bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3396 /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3397 if (bp->parent->vnic == 0) {
3398 PMD_DRV_LOG(DEBUG, "parent VNIC unavailable.\n");
3399 /* Use hard-coded values appropriate for current Wh+ fw. */
3400 if (bp->parent->fid == 2)
3401 bp->parent->vnic = 0x100;
3403 bp->parent->vnic = 1;
3411 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3412 uint16_t *vnic_id, uint16_t *svif)
3414 struct hwrm_func_qcfg_input req = {0};
3415 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3419 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3420 req.fid = rte_cpu_to_le_16(fid);
3422 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3424 HWRM_CHECK_RESULT();
3427 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3429 svif_info = rte_le_to_cpu_16(resp->svif_info);
3430 if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3431 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3438 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3440 struct hwrm_port_mac_qcfg_input req = {0};
3441 struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3442 uint16_t port_svif_info;
3445 bp->port_svif = BNXT_SVIF_INVALID;
3447 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3450 HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3452 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3454 HWRM_CHECK_RESULT_SILENT();
3456 port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3457 if (port_svif_info &
3458 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3459 bp->port_svif = port_svif_info &
3460 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3467 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3468 struct bnxt_pf_resource_info *pf_resc)
3470 struct hwrm_func_cfg_input req = {0};
3471 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3475 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3476 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3477 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3478 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3479 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3480 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3481 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3482 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3483 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3485 if (BNXT_HAS_RING_GRPS(bp)) {
3486 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3487 req.num_hw_ring_grps =
3488 rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3489 } else if (BNXT_HAS_NQ(bp)) {
3490 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3491 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3494 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3495 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3496 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3497 req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3498 req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3499 req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3500 req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3501 req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3502 req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3503 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3504 req.fid = rte_cpu_to_le_16(0xffff);
3505 req.enables = rte_cpu_to_le_32(enables);
3507 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3509 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3511 HWRM_CHECK_RESULT();
3517 /* min values are the guaranteed resources and max values are subject
3518 * to availability. The strategy for now is to keep both min & max
3522 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3523 struct hwrm_func_vf_resource_cfg_input *req,
3526 req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3528 req->min_rsscos_ctx = req->max_rsscos_ctx;
3529 req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3530 req->min_stat_ctx = req->max_stat_ctx;
3531 req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3533 req->min_cmpl_rings = req->max_cmpl_rings;
3534 req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3535 req->min_tx_rings = req->max_tx_rings;
3536 req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3537 req->min_rx_rings = req->max_rx_rings;
3538 req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3539 req->min_l2_ctxs = req->max_l2_ctxs;
3540 /* TODO: For now, do not support VMDq/RFS on VFs. */
3541 req->max_vnics = rte_cpu_to_le_16(1);
3542 req->min_vnics = req->max_vnics;
3543 req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3545 req->min_hw_ring_grps = req->max_hw_ring_grps;
3547 rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3551 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3552 struct hwrm_func_cfg_input *req,
3555 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3556 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3557 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3558 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3559 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3560 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3561 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3562 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3563 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3564 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3566 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3567 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3569 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3570 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3572 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3573 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3575 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3576 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3577 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3578 /* TODO: For now, do not support VMDq/RFS on VFs. */
3579 req->num_vnics = rte_cpu_to_le_16(1);
3580 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3584 /* Update the port wide resource values based on how many resources
3585 * got allocated to the VF.
3587 static int bnxt_update_max_resources(struct bnxt *bp,
3590 struct hwrm_func_qcfg_input req = {0};
3591 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3594 /* Get the actual allocated values now */
3595 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3596 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3597 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3598 HWRM_CHECK_RESULT();
3600 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3601 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3602 bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3603 bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3604 bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3605 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3606 bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3613 /* Update the PF resource values based on how many resources
3614 * got allocated to it.
3616 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3618 struct hwrm_func_qcfg_input req = {0};
3619 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3622 /* Get the actual allocated values now */
3623 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3624 req.fid = rte_cpu_to_le_16(0xffff);
3625 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3626 HWRM_CHECK_RESULT();
3628 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3629 bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3630 bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3631 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3632 bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3633 bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3634 bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3635 bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3642 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3644 struct hwrm_func_qcfg_input req = {0};
3645 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3648 /* Check for zero MAC address */
3649 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3650 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3651 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3652 HWRM_CHECK_RESULT();
3653 rc = rte_le_to_cpu_16(resp->vlan);
3660 static int bnxt_query_pf_resources(struct bnxt *bp,
3661 struct bnxt_pf_resource_info *pf_resc)
3663 struct hwrm_func_qcfg_input req = {0};
3664 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3667 /* And copy the allocated numbers into the pf struct */
3668 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3669 req.fid = rte_cpu_to_le_16(0xffff);
3670 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3671 HWRM_CHECK_RESULT();
3673 pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3674 pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3675 pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3676 pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3677 pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3678 pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3679 pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3680 bp->pf->evb_mode = resp->evb_mode;
3688 bnxt_calculate_pf_resources(struct bnxt *bp,
3689 struct bnxt_pf_resource_info *pf_resc,
3693 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3694 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3695 pf_resc->num_cp_rings = bp->max_cp_rings;
3696 pf_resc->num_tx_rings = bp->max_tx_rings;
3697 pf_resc->num_rx_rings = bp->max_rx_rings;
3698 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3699 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3704 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3705 bp->max_rsscos_ctx % (num_vfs + 1);
3706 pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3707 bp->max_stat_ctx % (num_vfs + 1);
3708 pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3709 bp->max_cp_rings % (num_vfs + 1);
3710 pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3711 bp->max_tx_rings % (num_vfs + 1);
3712 pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3713 bp->max_rx_rings % (num_vfs + 1);
3714 pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3715 bp->max_l2_ctx % (num_vfs + 1);
3716 pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3717 bp->max_ring_grps % (num_vfs + 1);
3720 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3722 struct bnxt_pf_resource_info pf_resc = { 0 };
3726 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3730 rc = bnxt_hwrm_func_qcaps(bp);
3734 bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3736 bp->pf->func_cfg_flags &=
3737 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3738 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3739 bp->pf->func_cfg_flags |=
3740 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3742 rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3746 rc = bnxt_update_max_resources_pf_only(bp);
3752 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3754 size_t req_buf_sz, sz;
3757 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3758 bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3759 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3760 if (bp->pf->vf_req_buf == NULL) {
3764 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3765 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3767 for (i = 0; i < num_vfs; i++)
3768 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3769 (i * HWRM_MAX_REQ_LEN);
3771 rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3773 rte_free(bp->pf->vf_req_buf);
3779 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3781 struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3782 struct hwrm_func_vf_resource_cfg_input req = {0};
3785 bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3786 bp->pf->active_vfs = 0;
3787 for (i = 0; i < num_vfs; i++) {
3788 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3789 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3790 rc = bnxt_hwrm_send_message(bp,
3794 if (rc || resp->error_code) {
3796 "Failed to initialize VF %d\n", i);
3798 "Not all VFs available. (%d, %d)\n",
3799 rc, resp->error_code);
3802 /* If the first VF configuration itself fails,
3803 * unregister the vf_fwd_request buffer.
3806 bnxt_hwrm_func_buf_unrgtr(bp);
3811 /* Update the max resource values based on the resource values
3812 * allocated to the VF.
3814 bnxt_update_max_resources(bp, i);
3815 bp->pf->active_vfs++;
3816 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3823 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3825 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3826 struct hwrm_func_cfg_input req = {0};
3829 bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3831 bp->pf->active_vfs = 0;
3832 for (i = 0; i < num_vfs; i++) {
3833 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3834 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3835 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3836 rc = bnxt_hwrm_send_message(bp,
3841 /* Clear enable flag for next pass */
3842 req.enables &= ~rte_cpu_to_le_32(
3843 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3845 if (rc || resp->error_code) {
3847 "Failed to initialize VF %d\n", i);
3849 "Not all VFs available. (%d, %d)\n",
3850 rc, resp->error_code);
3853 /* If the first VF configuration itself fails,
3854 * unregister the vf_fwd_request buffer.
3857 bnxt_hwrm_func_buf_unrgtr(bp);
3863 /* Update the max resource values based on the resource values
3864 * allocated to the VF.
3866 bnxt_update_max_resources(bp, i);
3867 bp->pf->active_vfs++;
3868 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3875 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3877 if (bp->flags & BNXT_FLAG_NEW_RM)
3878 bnxt_process_vf_resc_config_new(bp, num_vfs);
3880 bnxt_process_vf_resc_config_old(bp, num_vfs);
3884 bnxt_update_pf_resources(struct bnxt *bp,
3885 struct bnxt_pf_resource_info *pf_resc)
3887 bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3888 bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3889 bp->max_cp_rings = pf_resc->num_cp_rings;
3890 bp->max_tx_rings = pf_resc->num_tx_rings;
3891 bp->max_rx_rings = pf_resc->num_rx_rings;
3892 bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3896 bnxt_configure_pf_resources(struct bnxt *bp,
3897 struct bnxt_pf_resource_info *pf_resc)
3900 * We're using STD_TX_RING_MODE here which will limit the TX
3901 * rings. This will allow QoS to function properly. Not setting this
3902 * will cause PF rings to break bandwidth settings.
3904 bp->pf->func_cfg_flags &=
3905 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3906 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3907 bp->pf->func_cfg_flags |=
3908 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3909 return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3912 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3914 struct bnxt_pf_resource_info pf_resc = { 0 };
3918 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3922 rc = bnxt_hwrm_func_qcaps(bp);
3926 bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3928 rc = bnxt_configure_pf_resources(bp, &pf_resc);
3932 rc = bnxt_query_pf_resources(bp, &pf_resc);
3937 * Now, create and register a buffer to hold forwarded VF requests
3939 rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3943 bnxt_configure_vf_resources(bp, num_vfs);
3945 bnxt_update_pf_resources(bp, &pf_resc);
3950 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3952 struct hwrm_func_cfg_input req = {0};
3953 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3956 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3958 req.fid = rte_cpu_to_le_16(0xffff);
3959 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3960 req.evb_mode = bp->pf->evb_mode;
3962 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3963 HWRM_CHECK_RESULT();
3969 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3970 uint8_t tunnel_type)
3972 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3973 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3976 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3977 req.tunnel_type = tunnel_type;
3978 req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3979 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3980 HWRM_CHECK_RESULT();
3982 switch (tunnel_type) {
3983 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3984 bp->vxlan_fw_dst_port_id =
3985 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3986 bp->vxlan_port = port;
3988 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3989 bp->geneve_fw_dst_port_id =
3990 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3991 bp->geneve_port = port;
4002 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
4003 uint8_t tunnel_type)
4005 struct hwrm_tunnel_dst_port_free_input req = {0};
4006 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
4009 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
4011 req.tunnel_type = tunnel_type;
4012 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
4013 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4015 HWRM_CHECK_RESULT();
4019 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4021 bp->vxlan_port_cnt = 0;
4025 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4026 bp->geneve_port = 0;
4027 bp->geneve_port_cnt = 0;
4033 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4036 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4037 struct hwrm_func_cfg_input req = {0};
4040 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4042 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4043 req.flags = rte_cpu_to_le_32(flags);
4044 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4046 HWRM_CHECK_RESULT();
4052 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4054 uint32_t *flag = flagp;
4056 vnic->flags = *flag;
4059 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4061 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4064 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4066 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4067 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4070 HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4072 req.req_buf_num_pages = rte_cpu_to_le_16(1);
4073 req.req_buf_page_size =
4074 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4075 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4076 req.req_buf_page_addr0 =
4077 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4078 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4080 "unable to map buffer address to physical memory\n");
4085 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4087 HWRM_CHECK_RESULT();
4093 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4096 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4097 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4099 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4102 HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4104 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4106 HWRM_CHECK_RESULT();
4112 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4114 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4115 struct hwrm_func_cfg_input req = {0};
4118 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4120 req.fid = rte_cpu_to_le_16(0xffff);
4121 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4122 req.enables = rte_cpu_to_le_32(
4123 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4124 req.async_event_cr = rte_cpu_to_le_16(
4125 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4126 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4128 HWRM_CHECK_RESULT();
4134 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4136 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4137 struct hwrm_func_vf_cfg_input req = {0};
4140 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4142 req.enables = rte_cpu_to_le_32(
4143 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4144 req.async_event_cr = rte_cpu_to_le_16(
4145 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4146 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4148 HWRM_CHECK_RESULT();
4154 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4156 struct hwrm_func_cfg_input req = {0};
4157 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4158 uint16_t dflt_vlan, fid;
4159 uint32_t func_cfg_flags;
4162 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4165 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4166 fid = bp->pf->vf_info[vf].fid;
4167 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4169 fid = rte_cpu_to_le_16(0xffff);
4170 func_cfg_flags = bp->pf->func_cfg_flags;
4171 dflt_vlan = bp->vlan;
4174 req.flags = rte_cpu_to_le_32(func_cfg_flags);
4175 req.fid = rte_cpu_to_le_16(fid);
4176 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4177 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4179 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4181 HWRM_CHECK_RESULT();
4187 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4188 uint16_t max_bw, uint16_t enables)
4190 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4191 struct hwrm_func_cfg_input req = {0};
4194 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4196 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4197 req.enables |= rte_cpu_to_le_32(enables);
4198 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4199 req.max_bw = rte_cpu_to_le_32(max_bw);
4200 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4202 HWRM_CHECK_RESULT();
4208 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4210 struct hwrm_func_cfg_input req = {0};
4211 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4214 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4216 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4217 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4218 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4219 req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4221 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4223 HWRM_CHECK_RESULT();
4229 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4234 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4236 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4241 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4242 void *encaped, size_t ec_size)
4245 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4246 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4248 if (ec_size > sizeof(req.encap_request))
4251 HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4253 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4254 memcpy(req.encap_request, encaped, ec_size);
4256 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4258 HWRM_CHECK_RESULT();
4264 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4265 struct rte_ether_addr *mac)
4267 struct hwrm_func_qcfg_input req = {0};
4268 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4271 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4273 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4274 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4276 HWRM_CHECK_RESULT();
4278 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4285 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4286 void *encaped, size_t ec_size)
4289 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4290 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4292 if (ec_size > sizeof(req.encap_request))
4295 HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4297 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4298 memcpy(req.encap_request, encaped, ec_size);
4300 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4302 HWRM_CHECK_RESULT();
4308 static void bnxt_update_prev_stat(uint64_t *cntr, uint64_t *prev_cntr)
4310 /* One of the HW stat values that make up this counter was zero as
4311 * returned by HW in this iteration, so use the previous
4312 * iteration's counter value
4314 if (*prev_cntr && *cntr == 0)
4320 int bnxt_hwrm_ring_stats(struct bnxt *bp, uint32_t cid, int idx,
4321 struct bnxt_ring_stats *ring_stats, bool rx)
4324 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4325 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4327 HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4329 req.stat_ctx_id = rte_cpu_to_le_32(cid);
4331 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4333 HWRM_CHECK_RESULT();
4336 struct bnxt_ring_stats *prev_stats = &bp->prev_rx_ring_stats[idx];
4338 ring_stats->rx_ucast_pkts = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4339 bnxt_update_prev_stat(&ring_stats->rx_ucast_pkts,
4340 &prev_stats->rx_ucast_pkts);
4342 ring_stats->rx_mcast_pkts = rte_le_to_cpu_64(resp->rx_mcast_pkts);
4343 bnxt_update_prev_stat(&ring_stats->rx_mcast_pkts,
4344 &prev_stats->rx_mcast_pkts);
4346 ring_stats->rx_bcast_pkts = rte_le_to_cpu_64(resp->rx_bcast_pkts);
4347 bnxt_update_prev_stat(&ring_stats->rx_bcast_pkts,
4348 &prev_stats->rx_bcast_pkts);
4350 ring_stats->rx_ucast_bytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4351 bnxt_update_prev_stat(&ring_stats->rx_ucast_bytes,
4352 &prev_stats->rx_ucast_bytes);
4354 ring_stats->rx_mcast_bytes = rte_le_to_cpu_64(resp->rx_mcast_bytes);
4355 bnxt_update_prev_stat(&ring_stats->rx_mcast_bytes,
4356 &prev_stats->rx_mcast_bytes);
4358 ring_stats->rx_bcast_bytes = rte_le_to_cpu_64(resp->rx_bcast_bytes);
4359 bnxt_update_prev_stat(&ring_stats->rx_bcast_bytes,
4360 &prev_stats->rx_bcast_bytes);
4362 ring_stats->rx_discard_pkts = rte_le_to_cpu_64(resp->rx_discard_pkts);
4363 bnxt_update_prev_stat(&ring_stats->rx_discard_pkts,
4364 &prev_stats->rx_discard_pkts);
4366 ring_stats->rx_error_pkts = rte_le_to_cpu_64(resp->rx_error_pkts);
4367 bnxt_update_prev_stat(&ring_stats->rx_error_pkts,
4368 &prev_stats->rx_error_pkts);
4370 ring_stats->rx_agg_pkts = rte_le_to_cpu_64(resp->rx_agg_pkts);
4371 bnxt_update_prev_stat(&ring_stats->rx_agg_pkts,
4372 &prev_stats->rx_agg_pkts);
4374 ring_stats->rx_agg_bytes = rte_le_to_cpu_64(resp->rx_agg_bytes);
4375 bnxt_update_prev_stat(&ring_stats->rx_agg_bytes,
4376 &prev_stats->rx_agg_bytes);
4378 ring_stats->rx_agg_events = rte_le_to_cpu_64(resp->rx_agg_events);
4379 bnxt_update_prev_stat(&ring_stats->rx_agg_events,
4380 &prev_stats->rx_agg_events);
4382 ring_stats->rx_agg_aborts = rte_le_to_cpu_64(resp->rx_agg_aborts);
4383 bnxt_update_prev_stat(&ring_stats->rx_agg_aborts,
4384 &prev_stats->rx_agg_aborts);
4386 struct bnxt_ring_stats *prev_stats = &bp->prev_tx_ring_stats[idx];
4388 ring_stats->tx_ucast_pkts = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4389 bnxt_update_prev_stat(&ring_stats->tx_ucast_pkts,
4390 &prev_stats->tx_ucast_pkts);
4392 ring_stats->tx_mcast_pkts = rte_le_to_cpu_64(resp->tx_mcast_pkts);
4393 bnxt_update_prev_stat(&ring_stats->tx_mcast_pkts,
4394 &prev_stats->tx_mcast_pkts);
4396 ring_stats->tx_bcast_pkts = rte_le_to_cpu_64(resp->tx_bcast_pkts);
4397 bnxt_update_prev_stat(&ring_stats->tx_bcast_pkts,
4398 &prev_stats->tx_bcast_pkts);
4400 ring_stats->tx_ucast_bytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4401 bnxt_update_prev_stat(&ring_stats->tx_ucast_bytes,
4402 &prev_stats->tx_ucast_bytes);
4404 ring_stats->tx_mcast_bytes = rte_le_to_cpu_64(resp->tx_mcast_bytes);
4405 bnxt_update_prev_stat(&ring_stats->tx_mcast_bytes,
4406 &prev_stats->tx_mcast_bytes);
4408 ring_stats->tx_bcast_bytes = rte_le_to_cpu_64(resp->tx_bcast_bytes);
4409 bnxt_update_prev_stat(&ring_stats->tx_bcast_bytes,
4410 &prev_stats->tx_bcast_bytes);
4412 ring_stats->tx_discard_pkts = rte_le_to_cpu_64(resp->tx_discard_pkts);
4413 bnxt_update_prev_stat(&ring_stats->tx_discard_pkts,
4414 &prev_stats->tx_discard_pkts);
4422 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4424 struct hwrm_port_qstats_input req = {0};
4425 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4426 struct bnxt_pf_info *pf = bp->pf;
4429 HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4431 req.port_id = rte_cpu_to_le_16(pf->port_id);
4432 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4433 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4434 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4436 HWRM_CHECK_RESULT();
4442 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4444 struct hwrm_port_clr_stats_input req = {0};
4445 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4446 struct bnxt_pf_info *pf = bp->pf;
4449 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4450 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4451 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4454 HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4456 req.port_id = rte_cpu_to_le_16(pf->port_id);
4457 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4459 HWRM_CHECK_RESULT();
4465 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4467 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4468 struct hwrm_port_led_qcaps_input req = {0};
4474 HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4475 req.port_id = bp->pf->port_id;
4476 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4478 HWRM_CHECK_RESULT_SILENT();
4480 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4483 bp->leds->num_leds = resp->num_leds;
4484 memcpy(bp->leds, &resp->led0_id,
4485 sizeof(bp->leds[0]) * bp->leds->num_leds);
4486 for (i = 0; i < bp->leds->num_leds; i++) {
4487 struct bnxt_led_info *led = &bp->leds[i];
4489 uint16_t caps = led->led_state_caps;
4491 if (!led->led_group_id ||
4492 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4493 bp->leds->num_leds = 0;
4504 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4506 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4507 struct hwrm_port_led_cfg_input req = {0};
4508 struct bnxt_led_cfg *led_cfg;
4509 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4510 uint16_t duration = 0;
4513 if (!bp->leds->num_leds || BNXT_VF(bp))
4516 HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4519 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4520 duration = rte_cpu_to_le_16(500);
4522 req.port_id = bp->pf->port_id;
4523 req.num_leds = bp->leds->num_leds;
4524 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4525 for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4526 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4527 led_cfg->led_id = bp->leds[i].led_id;
4528 led_cfg->led_state = led_state;
4529 led_cfg->led_blink_on = duration;
4530 led_cfg->led_blink_off = duration;
4531 led_cfg->led_group_id = bp->leds[i].led_group_id;
4534 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4536 HWRM_CHECK_RESULT();
4542 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4546 struct hwrm_nvm_get_dir_info_input req = {0};
4547 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4549 HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4551 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4553 HWRM_CHECK_RESULT();
4555 *entries = rte_le_to_cpu_32(resp->entries);
4556 *length = rte_le_to_cpu_32(resp->entry_length);
4562 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4565 uint32_t dir_entries;
4566 uint32_t entry_length;
4569 rte_iova_t dma_handle;
4570 struct hwrm_nvm_get_dir_entries_input req = {0};
4571 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4573 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4577 *data++ = dir_entries;
4578 *data++ = entry_length;
4580 memset(data, 0xff, len);
4582 buflen = dir_entries * entry_length;
4583 buf = rte_malloc("nvm_dir", buflen, 0);
4586 dma_handle = rte_malloc_virt2iova(buf);
4587 if (dma_handle == RTE_BAD_IOVA) {
4590 "unable to map response address to physical memory\n");
4593 HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4594 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4595 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4598 memcpy(data, buf, len > buflen ? buflen : len);
4601 HWRM_CHECK_RESULT();
4607 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4608 uint32_t offset, uint32_t length,
4613 rte_iova_t dma_handle;
4614 struct hwrm_nvm_read_input req = {0};
4615 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4617 buf = rte_malloc("nvm_item", length, 0);
4621 dma_handle = rte_malloc_virt2iova(buf);
4622 if (dma_handle == RTE_BAD_IOVA) {
4625 "unable to map response address to physical memory\n");
4628 HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4629 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4630 req.dir_idx = rte_cpu_to_le_16(index);
4631 req.offset = rte_cpu_to_le_32(offset);
4632 req.len = rte_cpu_to_le_32(length);
4633 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4635 memcpy(data, buf, length);
4638 HWRM_CHECK_RESULT();
4644 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4647 struct hwrm_nvm_erase_dir_entry_input req = {0};
4648 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4650 HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4651 req.dir_idx = rte_cpu_to_le_16(index);
4652 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4653 HWRM_CHECK_RESULT();
4660 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4661 uint16_t dir_ordinal, uint16_t dir_ext,
4662 uint16_t dir_attr, const uint8_t *data,
4666 struct hwrm_nvm_write_input req = {0};
4667 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4668 rte_iova_t dma_handle;
4671 buf = rte_malloc("nvm_write", data_len, 0);
4675 dma_handle = rte_malloc_virt2iova(buf);
4676 if (dma_handle == RTE_BAD_IOVA) {
4679 "unable to map response address to physical memory\n");
4682 memcpy(buf, data, data_len);
4684 HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4686 req.dir_type = rte_cpu_to_le_16(dir_type);
4687 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4688 req.dir_ext = rte_cpu_to_le_16(dir_ext);
4689 req.dir_attr = rte_cpu_to_le_16(dir_attr);
4690 req.dir_data_length = rte_cpu_to_le_32(data_len);
4691 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4693 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4696 HWRM_CHECK_RESULT();
4703 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4705 uint32_t *count = cbdata;
4707 *count = *count + 1;
4710 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4711 struct bnxt_vnic_info *vnic __rte_unused)
4716 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4720 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4721 &count, bnxt_vnic_count_hwrm_stub);
4726 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4729 struct hwrm_func_vf_vnic_ids_query_input req = {0};
4730 struct hwrm_func_vf_vnic_ids_query_output *resp =
4731 bp->hwrm_cmd_resp_addr;
4734 /* First query all VNIC ids */
4735 HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4737 req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4738 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4739 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4741 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4744 "unable to map VNIC ID table address to physical memory\n");
4747 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4748 HWRM_CHECK_RESULT();
4749 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4757 * This function queries the VNIC IDs for a specified VF. It then calls
4758 * the vnic_cb to update the necessary field in vnic_info with cbdata.
4759 * Then it calls the hwrm_cb function to program this new vnic configuration.
4761 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4762 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4763 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4765 struct bnxt_vnic_info vnic;
4767 int i, num_vnic_ids;
4772 /* First query all VNIC ids */
4773 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4774 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4775 RTE_CACHE_LINE_SIZE);
4776 if (vnic_ids == NULL)
4779 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4780 rte_mem_lock_page(((char *)vnic_ids) + sz);
4782 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4784 if (num_vnic_ids < 0)
4785 return num_vnic_ids;
4787 /* Retrieve VNIC, update bd_stall then update */
4789 for (i = 0; i < num_vnic_ids; i++) {
4790 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4791 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4792 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4795 if (vnic.mru <= 4) /* Indicates unallocated */
4798 vnic_cb(&vnic, cbdata);
4800 rc = hwrm_cb(bp, &vnic);
4810 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4813 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4814 struct hwrm_func_cfg_input req = {0};
4817 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4819 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4820 req.enables |= rte_cpu_to_le_32(
4821 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4822 req.vlan_antispoof_mode = on ?
4823 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4824 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4825 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4827 HWRM_CHECK_RESULT();
4833 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4835 struct bnxt_vnic_info vnic;
4838 int num_vnic_ids, i;
4842 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4843 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4844 RTE_CACHE_LINE_SIZE);
4845 if (vnic_ids == NULL)
4848 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4849 rte_mem_lock_page(((char *)vnic_ids) + sz);
4851 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4857 * Loop through to find the default VNIC ID.
4858 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4859 * by sending the hwrm_func_qcfg command to the firmware.
4861 for (i = 0; i < num_vnic_ids; i++) {
4862 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4863 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4864 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4865 bp->pf->first_vf_id + vf);
4868 if (vnic.func_default) {
4870 return vnic.fw_vnic_id;
4873 /* Could not find a default VNIC. */
4874 PMD_DRV_LOG(ERR, "No default VNIC\n");
4880 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4882 struct bnxt_filter_info *filter)
4885 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4886 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4887 uint32_t enables = 0;
4889 if (filter->fw_em_filter_id != UINT64_MAX)
4890 bnxt_hwrm_clear_em_filter(bp, filter);
4892 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4894 req.flags = rte_cpu_to_le_32(filter->flags);
4896 enables = filter->enables |
4897 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4898 req.dst_id = rte_cpu_to_le_16(dst_id);
4900 if (filter->ip_addr_type) {
4901 req.ip_addr_type = filter->ip_addr_type;
4902 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4905 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4906 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4908 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4909 memcpy(req.src_macaddr, filter->src_macaddr,
4910 RTE_ETHER_ADDR_LEN);
4912 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4913 memcpy(req.dst_macaddr, filter->dst_macaddr,
4914 RTE_ETHER_ADDR_LEN);
4916 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4917 req.ovlan_vid = filter->l2_ovlan;
4919 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4920 req.ivlan_vid = filter->l2_ivlan;
4922 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4923 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4925 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4926 req.ip_protocol = filter->ip_protocol;
4928 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4929 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4931 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4932 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4934 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4935 req.src_port = rte_cpu_to_be_16(filter->src_port);
4937 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4938 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4940 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4941 req.mirror_vnic_id = filter->mirror_vnic_id;
4943 req.enables = rte_cpu_to_le_32(enables);
4945 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4947 HWRM_CHECK_RESULT();
4949 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4955 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4958 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4959 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4961 if (filter->fw_em_filter_id == UINT64_MAX)
4964 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4966 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4968 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4970 HWRM_CHECK_RESULT();
4973 filter->fw_em_filter_id = UINT64_MAX;
4974 filter->fw_l2_filter_id = UINT64_MAX;
4979 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4981 struct bnxt_filter_info *filter)
4984 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4985 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4986 bp->hwrm_cmd_resp_addr;
4987 uint32_t enables = 0;
4989 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4990 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4992 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4994 req.flags = rte_cpu_to_le_32(filter->flags);
4996 enables = filter->enables |
4997 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4998 req.dst_id = rte_cpu_to_le_16(dst_id);
5000 if (filter->ip_addr_type) {
5001 req.ip_addr_type = filter->ip_addr_type;
5003 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
5006 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
5007 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
5009 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
5010 memcpy(req.src_macaddr, filter->src_macaddr,
5011 RTE_ETHER_ADDR_LEN);
5013 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
5014 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
5016 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
5017 req.ip_protocol = filter->ip_protocol;
5019 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
5020 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
5022 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
5023 req.src_ipaddr_mask[0] =
5024 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
5026 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
5027 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
5029 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
5030 req.dst_ipaddr_mask[0] =
5031 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
5033 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
5034 req.src_port = rte_cpu_to_le_16(filter->src_port);
5036 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
5037 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
5039 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
5040 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
5042 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
5043 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
5045 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
5046 req.mirror_vnic_id = filter->mirror_vnic_id;
5048 req.enables = rte_cpu_to_le_32(enables);
5050 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5052 HWRM_CHECK_RESULT();
5054 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
5055 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
5061 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
5062 struct bnxt_filter_info *filter)
5065 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
5066 struct hwrm_cfa_ntuple_filter_free_output *resp =
5067 bp->hwrm_cmd_resp_addr;
5069 if (filter->fw_ntuple_filter_id == UINT64_MAX)
5072 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
5074 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
5076 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5078 HWRM_CHECK_RESULT();
5081 filter->fw_ntuple_filter_id = UINT64_MAX;
5087 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5089 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5090 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
5091 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
5092 struct bnxt_rx_queue **rxqs = bp->rx_queues;
5093 uint16_t *ring_tbl = vnic->rss_table;
5094 int nr_ctxs = vnic->num_lb_ctxts;
5095 int max_rings = bp->rx_nr_rings;
5099 for (i = 0, k = 0; i < nr_ctxs; i++) {
5100 struct bnxt_rx_ring_info *rxr;
5101 struct bnxt_cp_ring_info *cpr;
5103 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5105 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5106 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5107 req.hash_mode_flags = vnic->hash_mode;
5109 req.ring_grp_tbl_addr =
5110 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5111 i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5112 2 * sizeof(*ring_tbl));
5113 req.hash_key_tbl_addr =
5114 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5116 req.ring_table_pair_index = i;
5117 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5119 for (j = 0; j < 64; j++) {
5122 /* Find next active ring. */
5123 for (cnt = 0; cnt < max_rings; cnt++) {
5124 if (rx_queue_state[k] !=
5125 RTE_ETH_QUEUE_STATE_STOPPED)
5127 if (++k == max_rings)
5131 /* Return if no rings are active. */
5132 if (cnt == max_rings) {
5137 /* Add rx/cp ring pair to RSS table. */
5138 rxr = rxqs[k]->rx_ring;
5139 cpr = rxqs[k]->cp_ring;
5141 ring_id = rxr->rx_ring_struct->fw_ring_id;
5142 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5143 ring_id = cpr->cp_ring_struct->fw_ring_id;
5144 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5146 if (++k == max_rings)
5149 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5152 HWRM_CHECK_RESULT();
5159 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5161 unsigned int rss_idx, fw_idx, i;
5163 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5166 if (!(vnic->rss_table && vnic->hash_type))
5169 if (BNXT_CHIP_P5(bp))
5170 return bnxt_vnic_rss_configure_p5(bp, vnic);
5173 * Fill the RSS hash & redirection table with
5174 * ring group ids for all VNICs
5176 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5177 rss_idx++, fw_idx++) {
5178 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5179 fw_idx %= bp->rx_cp_nr_rings;
5180 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5185 if (i == bp->rx_cp_nr_rings)
5188 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5191 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5194 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5195 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5199 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5201 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5202 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5204 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5205 req->num_cmpl_dma_aggr_during_int =
5206 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5208 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5210 /* min timer set to 1/2 of interrupt timer */
5211 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5213 /* buf timer set to 1/4 of interrupt timer */
5214 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5216 req->cmpl_aggr_dma_tmr_during_int =
5217 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5219 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5220 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5221 req->flags = rte_cpu_to_le_16(flags);
5224 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5225 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5227 struct hwrm_ring_aggint_qcaps_input req = {0};
5228 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5233 HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5234 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5235 HWRM_CHECK_RESULT();
5237 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5238 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5240 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5241 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5242 agg_req->flags = rte_cpu_to_le_16(flags);
5244 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5245 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5246 agg_req->enables = rte_cpu_to_le_32(enables);
5252 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5253 struct bnxt_coal *coal, uint16_t ring_id)
5255 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5256 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5257 bp->hwrm_cmd_resp_addr;
5260 /* Set ring coalesce parameters only for 100G NICs */
5261 if (BNXT_CHIP_P5(bp)) {
5262 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5264 } else if (bnxt_stratus_device(bp)) {
5265 bnxt_hwrm_set_coal_params(coal, &req);
5271 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5273 req.ring_id = rte_cpu_to_le_16(ring_id);
5274 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5275 HWRM_CHECK_RESULT();
5280 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5281 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5283 struct hwrm_func_backing_store_qcaps_input req = {0};
5284 struct hwrm_func_backing_store_qcaps_output *resp =
5285 bp->hwrm_cmd_resp_addr;
5286 struct bnxt_ctx_pg_info *ctx_pg;
5287 struct bnxt_ctx_mem_info *ctx;
5288 int total_alloc_len;
5289 int rc, i, tqm_rings;
5291 if (!BNXT_CHIP_P5(bp) ||
5292 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5297 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5298 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5299 HWRM_CHECK_RESULT_SILENT();
5301 total_alloc_len = sizeof(*ctx);
5302 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5303 RTE_CACHE_LINE_SIZE);
5309 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5310 ctx->qp_min_qp1_entries =
5311 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5312 ctx->qp_max_l2_entries =
5313 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5314 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5315 ctx->srq_max_l2_entries =
5316 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5317 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5318 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5319 ctx->cq_max_l2_entries =
5320 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5321 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5322 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5323 ctx->vnic_max_vnic_entries =
5324 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5325 ctx->vnic_max_ring_table_entries =
5326 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5327 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5328 ctx->stat_max_entries =
5329 rte_le_to_cpu_32(resp->stat_max_entries);
5330 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5331 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5332 ctx->tqm_min_entries_per_ring =
5333 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5334 ctx->tqm_max_entries_per_ring =
5335 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5336 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5337 if (!ctx->tqm_entries_multiple)
5338 ctx->tqm_entries_multiple = 1;
5339 ctx->mrav_max_entries =
5340 rte_le_to_cpu_32(resp->mrav_max_entries);
5341 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5342 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5343 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5344 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5346 ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5347 RTE_MIN(ctx->tqm_fp_rings_count,
5348 BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5351 /* Check if the ext ring count needs to be counted.
5352 * Ext ring count is available only with new FW so we should not
5353 * look at the field on older FW.
5355 if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5356 bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5357 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5358 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5359 ctx->tqm_fp_rings_count);
5362 tqm_rings = ctx->tqm_fp_rings_count + 1;
5364 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5365 sizeof(*ctx_pg) * tqm_rings,
5366 RTE_CACHE_LINE_SIZE);
5371 for (i = 0; i < tqm_rings; i++, ctx_pg++)
5372 ctx->tqm_mem[i] = ctx_pg;
5380 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5382 struct hwrm_func_backing_store_cfg_input req = {0};
5383 struct hwrm_func_backing_store_cfg_output *resp =
5384 bp->hwrm_cmd_resp_addr;
5385 struct bnxt_ctx_mem_info *ctx = bp->ctx;
5386 struct bnxt_ctx_pg_info *ctx_pg;
5387 uint32_t *num_entries;
5396 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5397 req.enables = rte_cpu_to_le_32(enables);
5399 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5400 ctx_pg = &ctx->qp_mem;
5401 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5402 req.qp_num_qp1_entries =
5403 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5404 req.qp_num_l2_entries =
5405 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5406 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5407 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5408 &req.qpc_pg_size_qpc_lvl,
5412 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5413 ctx_pg = &ctx->srq_mem;
5414 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5415 req.srq_num_l2_entries =
5416 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5417 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5418 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5419 &req.srq_pg_size_srq_lvl,
5423 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5424 ctx_pg = &ctx->cq_mem;
5425 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5426 req.cq_num_l2_entries =
5427 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5428 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5429 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5430 &req.cq_pg_size_cq_lvl,
5434 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5435 ctx_pg = &ctx->vnic_mem;
5436 req.vnic_num_vnic_entries =
5437 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5438 req.vnic_num_ring_table_entries =
5439 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5440 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5441 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5442 &req.vnic_pg_size_vnic_lvl,
5443 &req.vnic_page_dir);
5446 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5447 ctx_pg = &ctx->stat_mem;
5448 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5449 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5450 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5451 &req.stat_pg_size_stat_lvl,
5452 &req.stat_page_dir);
5455 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5456 num_entries = &req.tqm_sp_num_entries;
5457 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5458 pg_dir = &req.tqm_sp_page_dir;
5459 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5460 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5461 if (!(enables & ena))
5464 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5466 ctx_pg = ctx->tqm_mem[i];
5467 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5468 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5471 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5472 /* DPDK does not need to configure MRAV and TIM type.
5473 * So we are skipping over MRAV and TIM. Skip to configure
5474 * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5476 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5477 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5478 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5479 &req.tqm_ring8_pg_size_tqm_ring_lvl,
5480 &req.tqm_ring8_page_dir);
5483 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5484 HWRM_CHECK_RESULT();
5490 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5492 struct hwrm_port_qstats_ext_input req = {0};
5493 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5494 struct bnxt_pf_info *pf = bp->pf;
5497 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5498 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5501 HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5503 req.port_id = rte_cpu_to_le_16(pf->port_id);
5504 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5505 req.tx_stat_host_addr =
5506 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5508 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5510 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5511 req.rx_stat_host_addr =
5512 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5514 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5516 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5519 bp->fw_rx_port_stats_ext_size = 0;
5520 bp->fw_tx_port_stats_ext_size = 0;
5522 bp->fw_rx_port_stats_ext_size =
5523 rte_le_to_cpu_16(resp->rx_stat_size);
5524 bp->fw_tx_port_stats_ext_size =
5525 rte_le_to_cpu_16(resp->tx_stat_size);
5528 HWRM_CHECK_RESULT();
5535 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5537 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5538 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5539 bp->hwrm_cmd_resp_addr;
5542 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5543 req.tunnel_type = type;
5544 req.dest_fid = bp->fw_fid;
5545 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5546 HWRM_CHECK_RESULT();
5554 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5556 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5557 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5558 bp->hwrm_cmd_resp_addr;
5561 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5562 req.tunnel_type = type;
5563 req.dest_fid = bp->fw_fid;
5564 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5565 HWRM_CHECK_RESULT();
5572 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5574 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5575 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5576 bp->hwrm_cmd_resp_addr;
5579 HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5580 req.src_fid = bp->fw_fid;
5581 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5582 HWRM_CHECK_RESULT();
5585 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5592 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5595 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5596 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5597 bp->hwrm_cmd_resp_addr;
5600 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5601 req.src_fid = bp->fw_fid;
5602 req.tunnel_type = tun_type;
5603 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5604 HWRM_CHECK_RESULT();
5607 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5609 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5616 int bnxt_hwrm_set_mac(struct bnxt *bp)
5618 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5619 struct hwrm_func_vf_cfg_input req = {0};
5625 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5628 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5629 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5631 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5633 HWRM_CHECK_RESULT();
5640 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5642 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5643 struct hwrm_func_drv_if_change_input req = {0};
5647 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5650 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5651 * If we issue FUNC_DRV_IF_CHANGE with flags down before
5652 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5654 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5657 HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5661 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5663 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5665 HWRM_CHECK_RESULT();
5666 flags = rte_le_to_cpu_32(resp->flags);
5672 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5673 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5674 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5680 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5682 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5683 struct bnxt_error_recovery_info *info = bp->recovery_info;
5684 struct hwrm_error_recovery_qcfg_input req = {0};
5689 /* Older FW does not have error recovery support */
5690 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5693 HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5695 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5697 HWRM_CHECK_RESULT();
5699 flags = rte_le_to_cpu_32(resp->flags);
5700 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5701 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5702 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5703 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5705 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5706 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5711 /* FW returned values are in units of 100msec */
5712 info->driver_polling_freq =
5713 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5714 info->master_func_wait_period =
5715 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5716 info->normal_func_wait_period =
5717 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5718 info->master_func_wait_period_after_reset =
5719 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5720 info->max_bailout_time_after_reset =
5721 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5722 info->status_regs[BNXT_FW_STATUS_REG] =
5723 rte_le_to_cpu_32(resp->fw_health_status_reg);
5724 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5725 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5726 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5727 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5728 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5729 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5730 info->reg_array_cnt =
5731 rte_le_to_cpu_32(resp->reg_array_cnt);
5733 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5738 for (i = 0; i < info->reg_array_cnt; i++) {
5739 info->reset_reg[i] =
5740 rte_le_to_cpu_32(resp->reset_reg[i]);
5741 info->reset_reg_val[i] =
5742 rte_le_to_cpu_32(resp->reset_reg_val[i]);
5743 info->delay_after_reset[i] =
5744 resp->delay_after_reset[i];
5749 /* Map the FW status registers */
5751 rc = bnxt_map_fw_health_status_regs(bp);
5754 rte_free(bp->recovery_info);
5755 bp->recovery_info = NULL;
5760 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5762 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5763 struct hwrm_fw_reset_input req = {0};
5769 HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5771 req.embedded_proc_type =
5772 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5773 req.selfrst_status =
5774 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5775 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5777 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5780 HWRM_CHECK_RESULT();
5786 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5788 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5789 struct hwrm_port_ts_query_input req = {0};
5790 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5797 HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5800 case BNXT_PTP_FLAGS_PATH_TX:
5801 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5803 case BNXT_PTP_FLAGS_PATH_RX:
5804 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5806 case BNXT_PTP_FLAGS_CURRENT_TIME:
5807 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5811 req.flags = rte_cpu_to_le_32(flags);
5812 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5814 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5816 HWRM_CHECK_RESULT();
5819 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5821 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5828 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5832 struct hwrm_cfa_counter_qcaps_input req = {0};
5833 struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5835 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5837 "Not a PF or trusted VF. Command not supported\n");
5841 HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5842 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5843 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5845 HWRM_CHECK_RESULT();
5847 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5853 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5856 struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5857 struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5859 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5861 "Not a PF or trusted VF. Command not supported\n");
5865 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5867 req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5868 req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5869 req.page_dir = rte_cpu_to_le_64(dma_addr);
5871 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5873 HWRM_CHECK_RESULT();
5875 *ctx_id = rte_le_to_cpu_16(resp->ctx_id);
5876 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5883 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5886 struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5887 struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5889 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5891 "Not a PF or trusted VF. Command not supported\n");
5895 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5897 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5899 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5901 HWRM_CHECK_RESULT();
5907 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5908 uint16_t cntr, uint16_t ctx_id,
5909 uint32_t num_entries, bool enable)
5911 struct hwrm_cfa_counter_cfg_input req = {0};
5912 struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5916 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5918 "Not a PF or trusted VF. Command not supported\n");
5922 HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5924 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5925 req.counter_type = rte_cpu_to_le_16(cntr);
5926 flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5927 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5928 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5929 if (dir == BNXT_DIR_RX)
5930 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5931 else if (dir == BNXT_DIR_TX)
5932 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5933 req.flags = rte_cpu_to_le_16(flags);
5934 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5935 req.num_entries = rte_cpu_to_le_32(num_entries);
5937 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5938 HWRM_CHECK_RESULT();
5944 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5945 enum bnxt_flow_dir dir,
5947 uint16_t num_entries)
5949 struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5950 struct hwrm_cfa_counter_qstats_input req = {0};
5951 uint16_t flow_ctx_id = 0;
5955 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5957 "Not a PF or trusted VF. Command not supported\n");
5961 if (dir == BNXT_DIR_RX) {
5962 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5963 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5964 } else if (dir == BNXT_DIR_TX) {
5965 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5966 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5969 HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5970 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5971 req.counter_type = rte_cpu_to_le_16(cntr);
5972 req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5973 req.num_entries = rte_cpu_to_le_16(num_entries);
5974 req.flags = rte_cpu_to_le_16(flags);
5975 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5977 HWRM_CHECK_RESULT();
5983 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5984 uint16_t *first_vf_id)
5987 struct hwrm_func_qcaps_input req = {.req_type = 0 };
5988 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5990 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5992 req.fid = rte_cpu_to_le_16(fid);
5994 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5996 HWRM_CHECK_RESULT();
5999 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
6006 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
6008 struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6009 struct hwrm_cfa_pair_alloc_input req = {0};
6012 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6014 "Not a PF or trusted VF. Command not supported\n");
6018 HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
6019 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6020 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6021 bp->eth_dev->data->name, rep_bp->vf_id);
6023 req.pf_b_id = rep_bp->parent_pf_idx;
6024 req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6025 rte_cpu_to_le_16(rep_bp->vf_id);
6026 req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
6027 req.host_b_id = 1; /* TBD - Confirm if this is OK */
6029 req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
6030 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
6031 req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
6032 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
6033 req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
6034 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
6035 req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
6036 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
6038 req.q_ab = rep_bp->rep_q_r2f;
6039 req.q_ba = rep_bp->rep_q_f2r;
6040 req.fc_ab = rep_bp->rep_fc_r2f;
6041 req.fc_ba = rep_bp->rep_fc_f2r;
6043 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6044 HWRM_CHECK_RESULT();
6047 PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
6048 BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
6052 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
6054 struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
6055 struct hwrm_cfa_pair_free_input req = {0};
6058 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6060 "Not a PF or trusted VF. Command not supported\n");
6064 HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
6065 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6066 bp->eth_dev->data->name, rep_bp->vf_id);
6067 req.pf_b_id = rep_bp->parent_pf_idx;
6068 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6069 req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6070 rte_cpu_to_le_16(rep_bp->vf_id);
6071 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6072 HWRM_CHECK_RESULT();
6074 PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
6079 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
6081 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
6082 bp->hwrm_cmd_resp_addr;
6083 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
6087 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
6090 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6092 "Not a PF or trusted VF. Command not supported\n");
6096 HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
6097 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6099 HWRM_CHECK_RESULT();
6100 flags = rte_le_to_cpu_32(resp->flags);
6103 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
6104 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
6106 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
6111 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6112 uint32_t echo_req_data2)
6114 struct hwrm_func_echo_response_input req = {0};
6115 struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6118 HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6119 req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6120 req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6122 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6124 HWRM_CHECK_RESULT();
6130 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6132 struct hwrm_ver_get_input req = {.req_type = 0 };
6133 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6136 bp->max_req_len = HWRM_MAX_REQ_LEN;
6137 bp->max_resp_len = BNXT_PAGE_SIZE;
6138 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6140 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6141 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6142 req.hwrm_intf_min = HWRM_VERSION_MINOR;
6143 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6145 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6147 HWRM_CHECK_RESULT_SILENT();
6149 if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)