drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         /* For VER_GET command, set timeout as 50ms */
 104         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 105                 timeout = HWRM_CMD_TIMEOUT;
 106         else
 107                 timeout = bp->hwrm_cmd_timeout;
 108
 109         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 110             msg_len > bp->max_req_len) {
 111                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 112
 113                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 114                 memcpy(short_cmd_req, req, msg_len);
 115
 116                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 117                 short_input.signature = rte_cpu_to_le_16(
 118                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 119                 short_input.size = rte_cpu_to_le_16(msg_len);
 120                 short_input.req_addr =
 121                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 122
 123                 data = (uint32_t *)&short_input;
 124                 msg_len = sizeof(short_input);
 125
 126                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 127         }
 128
 129         /* Write request msg to hwrm channel */
 130         for (i = 0; i < msg_len; i += 4) {
 131                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 132                 rte_write32(*data, bar);
 133                 data++;
 134         }
 135
 136         /* Zero the rest of the request space */
 137         for (; i < max_req_len; i += 4) {
 138                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 139                 rte_write32(0, bar);
 140         }
 141
 142         /* Ring channel doorbell */
 143         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 144         rte_write32(1, bar);
 145         /*
 146          * Make sure the channel doorbell ring command complete before
 147          * reading the response to avoid getting stale or invalid
 148          * responses.
 149          */
 150         rte_io_mb();
 151
 152         /* Poll for the valid bit */
 153         for (i = 0; i < timeout; i++) {
 154                 /* Sanity check on the resp->resp_len */
 155                 rte_cio_rmb();
 156                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 157                         /* Last byte of resp contains the valid key */
 158                         valid = (uint8_t *)resp + resp->resp_len - 1;
 159                         if (*valid == HWRM_RESP_VALID_KEY)
 160                                 break;
 161                 }
 162                 rte_delay_us(1);
 163         }
 164
 165         if (i >= timeout) {
 166                 /* Suppress VER_GET timeout messages during reset recovery */
 167                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 168                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 169                         return -ETIMEDOUT;
 170
 171                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 172                             req->req_type);
 173                 return -ETIMEDOUT;
 174         }
 175         return 0;
 176 }
 177
 178 /*
 179  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 180  * spinlock, and does initial processing.
 181  *
 182  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 183  * releases the spinlock only if it returns. If the regular int return codes
 184  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 185  * directly, rather it should be copied and modified to suit the function.
 186  *
 187  * HWRM_UNLOCK() must be called after all response processing is completed.
 188  */
 189 #define HWRM_PREP(req, type, kong) do { \
 190         rte_spinlock_lock(&bp->hwrm_lock); \
 191         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 192         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 193         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 194         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 195                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 196         req.target_id = rte_cpu_to_le_16(0xffff); \
 197         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 198 } while (0)
 199
 200 #define HWRM_CHECK_RESULT_SILENT() do {\
 201         if (rc) { \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 return rc; \
 204         } \
 205         if (resp->error_code) { \
 206                 rc = rte_le_to_cpu_16(resp->error_code); \
 207                 rte_spinlock_unlock(&bp->hwrm_lock); \
 208                 return rc; \
 209         } \
 210 } while (0)
 211
 212 #define HWRM_CHECK_RESULT() do {\
 213         if (rc) { \
 214                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 215                 rte_spinlock_unlock(&bp->hwrm_lock); \
 216                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 217                         rc = -EACCES; \
 218                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 219                         rc = -ENOSPC; \
 220                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 221                         rc = -EINVAL; \
 222                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 223                         rc = -ENOTSUP; \
 224                 else if (rc > 0) \
 225                         rc = -EIO; \
 226                 return rc; \
 227         } \
 228         if (resp->error_code) { \
 229                 rc = rte_le_to_cpu_16(resp->error_code); \
 230                 if (resp->resp_len >= 16) { \
 231                         struct hwrm_err_output *tmp_hwrm_err_op = \
 232                                                 (void *)resp; \
 233                         PMD_DRV_LOG(ERR, \
 234                                 "error %d:%d:%08x:%04x\n", \
 235                                 rc, tmp_hwrm_err_op->cmd_err, \
 236                                 rte_le_to_cpu_32(\
 237                                         tmp_hwrm_err_op->opaque_0), \
 238                                 rte_le_to_cpu_16(\
 239                                         tmp_hwrm_err_op->opaque_1)); \
 240                 } else { \
 241                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 242                 } \
 243                 rte_spinlock_unlock(&bp->hwrm_lock); \
 244                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 245                         rc = -EACCES; \
 246                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 247                         rc = -ENOSPC; \
 248                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 249                         rc = -EINVAL; \
 250                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 251                         rc = -ENOTSUP; \
 252                 else if (rc > 0) \
 253                         rc = -EIO; \
 254                 return rc; \
 255         } \
 256 } while (0)
 257
 258 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 259
 260 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 261 {
 262         int rc = 0;
 263         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 264         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 265
 266         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 268         req.mask = 0;
 269
 270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 271
 272         HWRM_CHECK_RESULT();
 273         HWRM_UNLOCK();
 274
 275         return rc;
 276 }
 277
 278 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 279                                  struct bnxt_vnic_info *vnic,
 280                                  uint16_t vlan_count,
 281                                  struct bnxt_vlan_table_entry *vlan_table)
 282 {
 283         int rc = 0;
 284         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 285         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 286         uint32_t mask = 0;
 287
 288         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 289                 return rc;
 290
 291         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 292         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 293
 294         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 295                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 296         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 297                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 298
 299         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 300                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 301
 302         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 303                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 304         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 305                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 306                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 307                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 308         }
 309         if (vlan_table) {
 310                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 311                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 312                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 313                          rte_mem_virt2iova(vlan_table));
 314                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 315         }
 316         req.mask = rte_cpu_to_le_32(mask);
 317
 318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 319
 320         HWRM_CHECK_RESULT();
 321         HWRM_UNLOCK();
 322
 323         return rc;
 324 }
 325
 326 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 327                         uint16_t vlan_count,
 328                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 329 {
 330         int rc = 0;
 331         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 332         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 333                                                 bp->hwrm_cmd_resp_addr;
 334
 335         /*
 336          * Older HWRM versions did not support this command, and the set_rx_mask
 337          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 338          * removed from set_rx_mask call, and this command was added.
 339          *
 340          * This command is also present from 1.7.8.11 and higher,
 341          * as well as 1.7.8.0
 342          */
 343         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 344                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 345                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 346                                         (11)))
 347                                 return 0;
 348                 }
 349         }
 350         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 351         req.fid = rte_cpu_to_le_16(fid);
 352
 353         req.vlan_tag_mask_tbl_addr =
 354                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 355         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         return rc;
 363 }
 364
 365 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 366                            struct bnxt_filter_info *filter)
 367 {
 368         int rc = 0;
 369         struct bnxt_filter_info *l2_filter = filter;
 370         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 371         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 372
 373         if (filter->fw_l2_filter_id == UINT64_MAX)
 374                 return 0;
 375
 376         if (filter->matching_l2_fltr_ptr)
 377                 l2_filter = filter->matching_l2_fltr_ptr;
 378
 379         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 380                     filter, l2_filter, l2_filter->l2_ref_cnt);
 381
 382         if (l2_filter->l2_ref_cnt > 0)
 383                 l2_filter->l2_ref_cnt--;
 384
 385         if (l2_filter->l2_ref_cnt > 0)
 386                 return 0;
 387
 388         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 389
 390         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 391
 392         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 393
 394         HWRM_CHECK_RESULT();
 395         HWRM_UNLOCK();
 396
 397         filter->fw_l2_filter_id = UINT64_MAX;
 398
 399         return 0;
 400 }
 401
 402 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 403                          uint16_t dst_id,
 404                          struct bnxt_filter_info *filter)
 405 {
 406         int rc = 0;
 407         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 408         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 409         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 410         const struct rte_eth_vmdq_rx_conf *conf =
 411                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 412         uint32_t enables = 0;
 413         uint16_t j = dst_id - 1;
 414
 415         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 416         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 417             conf->pool_map[j].pools & (1UL << j)) {
 418                 PMD_DRV_LOG(DEBUG,
 419                         "Add vlan %u to vmdq pool %u\n",
 420                         conf->pool_map[j].vlan_id, j);
 421
 422                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 423                 filter->enables |=
 424                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 425                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 426         }
 427
 428         if (filter->fw_l2_filter_id != UINT64_MAX)
 429                 bnxt_hwrm_clear_l2_filter(bp, filter);
 430
 431         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 432
 433         req.flags = rte_cpu_to_le_32(filter->flags);
 434
 435         enables = filter->enables |
 436               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 437         req.dst_id = rte_cpu_to_le_16(dst_id);
 438
 439         if (enables &
 440             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 441                 memcpy(req.l2_addr, filter->l2_addr,
 442                        RTE_ETHER_ADDR_LEN);
 443         if (enables &
 444             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 445                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 446                        RTE_ETHER_ADDR_LEN);
 447         if (enables &
 448             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 449                 req.l2_ovlan = filter->l2_ovlan;
 450         if (enables &
 451             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 452                 req.l2_ivlan = filter->l2_ivlan;
 453         if (enables &
 454             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 455                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 456         if (enables &
 457             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 458                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 459         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 460                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 461         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 462                 req.src_type = filter->src_type;
 463         if (filter->pri_hint) {
 464                 req.pri_hint = filter->pri_hint;
 465                 req.l2_filter_id_hint =
 466                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 467         }
 468
 469         req.enables = rte_cpu_to_le_32(enables);
 470
 471         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 472
 473         HWRM_CHECK_RESULT();
 474
 475         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 482 {
 483         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 484         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 485         uint32_t flags = 0;
 486         int rc;
 487
 488         if (!ptp)
 489                 return 0;
 490
 491         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 492
 493         if (ptp->rx_filter)
 494                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 495         else
 496                 flags |=
 497                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 498         if (ptp->tx_tstamp_en)
 499                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 500         else
 501                 flags |=
 502                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 503         req.flags = rte_cpu_to_le_32(flags);
 504         req.enables = rte_cpu_to_le_32
 505                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 506         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 507
 508         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 509         HWRM_UNLOCK();
 510
 511         return rc;
 512 }
 513
 514 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 515 {
 516         int rc = 0;
 517         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 518         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 519         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 520
 521         if (ptp)
 522                 return 0;
 523
 524         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 525
 526         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 527
 528         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 529
 530         HWRM_CHECK_RESULT();
 531
 532         if (!BNXT_CHIP_THOR(bp) &&
 533             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 534                 return 0;
 535
 536         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 537                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 538
 539         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 540         if (!ptp)
 541                 return -ENOMEM;
 542
 543         if (!BNXT_CHIP_THOR(bp)) {
 544                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 545                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 546                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 547                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 548                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 549                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 550                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 551                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 552                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 553                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 554                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 555                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 556                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 557                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 558                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 559                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 560                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 561                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 562         }
 563
 564         ptp->bp = bp;
 565         bp->ptp_cfg = ptp;
 566
 567         return 0;
 568 }
 569
 570 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 571 {
 572         int rc = 0;
 573         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 574         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 575         uint16_t new_max_vfs;
 576         uint32_t flags;
 577         int i;
 578
 579         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 580
 581         req.fid = rte_cpu_to_le_16(0xffff);
 582
 583         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 584
 585         HWRM_CHECK_RESULT();
 586
 587         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 588         flags = rte_le_to_cpu_32(resp->flags);
 589         if (BNXT_PF(bp)) {
 590                 bp->pf.port_id = resp->port_id;
 591                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 592                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 593                 new_max_vfs = bp->pdev->max_vfs;
 594                 if (new_max_vfs != bp->pf.max_vfs) {
 595                         if (bp->pf.vf_info)
 596                                 rte_free(bp->pf.vf_info);
 597                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 598                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 599                         bp->pf.max_vfs = new_max_vfs;
 600                         for (i = 0; i < new_max_vfs; i++) {
 601                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 602                                 bp->pf.vf_info[i].vlan_table =
 603                                         rte_zmalloc("VF VLAN table",
 604                                                     getpagesize(),
 605                                                     getpagesize());
 606                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 607                                         PMD_DRV_LOG(ERR,
 608                                         "Fail to alloc VLAN table for VF %d\n",
 609                                         i);
 610                                 else
 611                                         rte_mem_lock_page(
 612                                                 bp->pf.vf_info[i].vlan_table);
 613                                 bp->pf.vf_info[i].vlan_as_table =
 614                                         rte_zmalloc("VF VLAN AS table",
 615                                                     getpagesize(),
 616                                                     getpagesize());
 617                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 618                                         PMD_DRV_LOG(ERR,
 619                                         "Alloc VLAN AS table for VF %d fail\n",
 620                                         i);
 621                                 else
 622                                         rte_mem_lock_page(
 623                                                bp->pf.vf_info[i].vlan_as_table);
 624                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 625                         }
 626                 }
 627         }
 628
 629         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 630         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 631         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 632         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 633         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 634         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 635         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 636         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 637         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 638         if (!BNXT_CHIP_THOR(bp))
 639                 bp->max_l2_ctx += bp->max_rx_em_flows;
 640         /* TODO: For now, do not support VMDq/RFS on VFs. */
 641         if (BNXT_PF(bp)) {
 642                 if (bp->pf.max_vfs)
 643                         bp->max_vnics = 1;
 644                 else
 645                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 646         } else {
 647                 bp->max_vnics = 1;
 648         }
 649         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 650         if (BNXT_PF(bp)) {
 651                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 652                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 653                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 654                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 655                         HWRM_UNLOCK();
 656                         bnxt_hwrm_ptp_qcfg(bp);
 657                 }
 658         }
 659
 660         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 661                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 662
 663         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 664                 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 665                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 666         } else {
 667                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 668         }
 669
 670         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 671                 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 672         else
 673                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 674
 675         HWRM_UNLOCK();
 676
 677         return rc;
 678 }
 679
 680 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 681 {
 682         int rc;
 683
 684         rc = __bnxt_hwrm_func_qcaps(bp);
 685         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 686                 rc = bnxt_alloc_ctx_mem(bp);
 687                 if (rc)
 688                         return rc;
 689
 690                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 691                 if (!rc)
 692                         bp->flags |= BNXT_FLAG_NEW_RM;
 693         }
 694
 695         return rc;
 696 }
 697
 698 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 699 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 700 {
 701         int rc = 0;
 702         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 703         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 704
 705         HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 706
 707         req.target_id = rte_cpu_to_le_16(0xffff);
 708
 709         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 710
 711         HWRM_CHECK_RESULT();
 712
 713         if (rte_le_to_cpu_32(resp->flags) &
 714             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 715                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 716                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 717         }
 718
 719         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 720
 721         HWRM_UNLOCK();
 722
 723         return rc;
 724 }
 725
 726 int bnxt_hwrm_func_reset(struct bnxt *bp)
 727 {
 728         int rc = 0;
 729         struct hwrm_func_reset_input req = {.req_type = 0 };
 730         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 731
 732         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 733
 734         req.enables = rte_cpu_to_le_32(0);
 735
 736         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 737
 738         HWRM_CHECK_RESULT();
 739         HWRM_UNLOCK();
 740
 741         return rc;
 742 }
 743
 744 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 745 {
 746         int rc;
 747         uint32_t flags = 0;
 748         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 749         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 750
 751         if (bp->flags & BNXT_FLAG_REGISTERED)
 752                 return 0;
 753
 754         flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 755         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 756                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 757
 758         /* PFs and trusted VFs should indicate the support of the
 759          * Master capability on non Stingray platform
 760          */
 761         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 762                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 763
 764         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 765         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 766                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 767         req.ver_maj = RTE_VER_YEAR;
 768         req.ver_min = RTE_VER_MONTH;
 769         req.ver_upd = RTE_VER_MINOR;
 770
 771         if (BNXT_PF(bp)) {
 772                 req.enables |= rte_cpu_to_le_32(
 773                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 774                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 775                        RTE_MIN(sizeof(req.vf_req_fwd),
 776                                sizeof(bp->pf.vf_req_fwd)));
 777
 778                 /*
 779                  * PF can sniff HWRM API issued by VF. This can be set up by
 780                  * linux driver and inherited by the DPDK PF driver. Clear
 781                  * this HWRM sniffer list in FW because DPDK PF driver does
 782                  * not support this.
 783                  */
 784                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 785         }
 786
 787         req.flags = rte_cpu_to_le_32(flags);
 788
 789         req.async_event_fwd[0] |=
 790                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 791                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 792                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 793                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 794                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 795         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 796                 req.async_event_fwd[0] |=
 797                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 798         req.async_event_fwd[1] |=
 799                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 800                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 801
 802         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 803
 804         HWRM_CHECK_RESULT();
 805
 806         flags = rte_le_to_cpu_32(resp->flags);
 807         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 808                 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
 809
 810         HWRM_UNLOCK();
 811
 812         bp->flags |= BNXT_FLAG_REGISTERED;
 813
 814         return rc;
 815 }
 816
 817 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 818 {
 819         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 820                 return 0;
 821
 822         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 823 }
 824
 825 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 826 {
 827         int rc;
 828         uint32_t flags = 0;
 829         uint32_t enables;
 830         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 831         struct hwrm_func_vf_cfg_input req = {0};
 832
 833         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 834
 835         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 836                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 837                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 838                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 839                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 840
 841         if (BNXT_HAS_RING_GRPS(bp)) {
 842                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 843                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 844         }
 845
 846         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 847         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 848                                             AGG_RING_MULTIPLIER);
 849         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 850         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 851                                               bp->tx_nr_rings +
 852                                               BNXT_NUM_ASYNC_CPR(bp));
 853         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 854         if (bp->vf_resv_strategy ==
 855             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 856                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 857                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 858                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 859                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 860                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 861                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 862         } else if (bp->vf_resv_strategy ==
 863                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 864                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 865                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 866         }
 867
 868         if (test)
 869                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 870                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 871                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 872                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 873                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 874                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 875
 876         if (test && BNXT_HAS_RING_GRPS(bp))
 877                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 878
 879         req.flags = rte_cpu_to_le_32(flags);
 880         req.enables |= rte_cpu_to_le_32(enables);
 881
 882         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 883
 884         if (test)
 885                 HWRM_CHECK_RESULT_SILENT();
 886         else
 887                 HWRM_CHECK_RESULT();
 888
 889         HWRM_UNLOCK();
 890         return rc;
 891 }
 892
 893 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 894 {
 895         int rc;
 896         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 897         struct hwrm_func_resource_qcaps_input req = {0};
 898
 899         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 900         req.fid = rte_cpu_to_le_16(0xffff);
 901
 902         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 903
 904         HWRM_CHECK_RESULT();
 905
 906         if (BNXT_VF(bp)) {
 907                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 908                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 909                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 910                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 911                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 912                 /* func_resource_qcaps does not return max_rx_em_flows.
 913                  * So use the value provided by func_qcaps.
 914                  */
 915                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 916                 if (!BNXT_CHIP_THOR(bp))
 917                         bp->max_l2_ctx += bp->max_rx_em_flows;
 918                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 919                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 920         }
 921         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 922         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 923         if (bp->vf_resv_strategy >
 924             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 925                 bp->vf_resv_strategy =
 926                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 927
 928         HWRM_UNLOCK();
 929         return rc;
 930 }
 931
 932 int bnxt_hwrm_ver_get(struct bnxt *bp)
 933 {
 934         int rc = 0;
 935         struct hwrm_ver_get_input req = {.req_type = 0 };
 936         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 937         uint32_t fw_version;
 938         uint16_t max_resp_len;
 939         char type[RTE_MEMZONE_NAMESIZE];
 940         uint32_t dev_caps_cfg;
 941
 942         bp->max_req_len = HWRM_MAX_REQ_LEN;
 943         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 944
 945         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 946         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 947         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 948
 949         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 950
 951         if (bp->flags & BNXT_FLAG_FW_RESET)
 952                 HWRM_CHECK_RESULT_SILENT();
 953         else
 954                 HWRM_CHECK_RESULT();
 955
 956         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 957                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 958                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 959                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 960         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 961                      (resp->hwrm_fw_min_8b << 16) |
 962                      (resp->hwrm_fw_bld_8b << 8) |
 963                      resp->hwrm_fw_rsvd_8b;
 964         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 965                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 966
 967         fw_version = resp->hwrm_intf_maj_8b << 16;
 968         fw_version |= resp->hwrm_intf_min_8b << 8;
 969         fw_version |= resp->hwrm_intf_upd_8b;
 970         bp->hwrm_spec_code = fw_version;
 971
 972         /* def_req_timeout value is in milliseconds */
 973         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
 974         /* convert timeout to usec */
 975         bp->hwrm_cmd_timeout *= 1000;
 976         if (!bp->hwrm_cmd_timeout)
 977                 bp->hwrm_cmd_timeout = HWRM_CMD_TIMEOUT;
 978
 979         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 980                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 981                 rc = -EINVAL;
 982                 goto error;
 983         }
 984
 985         if (bp->max_req_len > resp->max_req_win_len) {
 986                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 987                 rc = -EINVAL;
 988         }
 989         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 990         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 991         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 992                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 993
 994         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 995         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 996
 997         if (bp->max_resp_len != max_resp_len) {
 998                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 999                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1000                         bp->pdev->addr.devid, bp->pdev->addr.function);
1001
1002                 rte_free(bp->hwrm_cmd_resp_addr);
1003
1004                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1005                 if (bp->hwrm_cmd_resp_addr == NULL) {
1006                         rc = -ENOMEM;
1007                         goto error;
1008                 }
1009                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1010                 bp->hwrm_cmd_resp_dma_addr =
1011                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1012                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1013                         PMD_DRV_LOG(ERR,
1014                         "Unable to map response buffer to physical memory.\n");
1015                         rc = -ENOMEM;
1016                         goto error;
1017                 }
1018                 bp->max_resp_len = max_resp_len;
1019         }
1020
1021         if ((dev_caps_cfg &
1022                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1023             (dev_caps_cfg &
1024              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1025                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1026                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1027         }
1028
1029         if (((dev_caps_cfg &
1030               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1031              (dev_caps_cfg &
1032               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1033             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1034                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1035                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1036                         bp->pdev->addr.devid, bp->pdev->addr.function);
1037
1038                 rte_free(bp->hwrm_short_cmd_req_addr);
1039
1040                 bp->hwrm_short_cmd_req_addr =
1041                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1042                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1043                         rc = -ENOMEM;
1044                         goto error;
1045                 }
1046                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1047                 bp->hwrm_short_cmd_req_dma_addr =
1048                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1049                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1050                         rte_free(bp->hwrm_short_cmd_req_addr);
1051                         PMD_DRV_LOG(ERR,
1052                                 "Unable to map buffer to physical memory.\n");
1053                         rc = -ENOMEM;
1054                         goto error;
1055                 }
1056         }
1057         if (dev_caps_cfg &
1058             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1059                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1060                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1061         }
1062         if (dev_caps_cfg &
1063             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1064                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1065         if (dev_caps_cfg &
1066             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1067                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1068                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1069         }
1070
1071 error:
1072         HWRM_UNLOCK();
1073         return rc;
1074 }
1075
1076 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1077 {
1078         int rc;
1079         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1080         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1081
1082         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1083                 return 0;
1084
1085         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1086         req.flags = flags;
1087
1088         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1089
1090         HWRM_CHECK_RESULT();
1091         HWRM_UNLOCK();
1092
1093         return rc;
1094 }
1095
1096 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1097 {
1098         int rc = 0;
1099         struct hwrm_port_phy_cfg_input req = {0};
1100         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1101         uint32_t enables = 0;
1102
1103         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1104
1105         if (conf->link_up) {
1106                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1107                 if (bp->link_info.auto_mode && conf->link_speed) {
1108                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1109                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1110                 }
1111
1112                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1113                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1114                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1115                 /*
1116                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1117                  * any auto mode, even "none".
1118                  */
1119                 if (!conf->link_speed) {
1120                         /* No speeds specified. Enable AutoNeg - all speeds */
1121                         req.auto_mode =
1122                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1123                 }
1124                 /* AutoNeg - Advertise speeds specified. */
1125                 if (conf->auto_link_speed_mask &&
1126                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1127                         req.auto_mode =
1128                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1129                         req.auto_link_speed_mask =
1130                                 conf->auto_link_speed_mask;
1131                         enables |=
1132                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1133                 }
1134
1135                 req.auto_duplex = conf->duplex;
1136                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1137                 req.auto_pause = conf->auto_pause;
1138                 req.force_pause = conf->force_pause;
1139                 /* Set force_pause if there is no auto or if there is a force */
1140                 if (req.auto_pause && !req.force_pause)
1141                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1142                 else
1143                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1144
1145                 req.enables = rte_cpu_to_le_32(enables);
1146         } else {
1147                 req.flags =
1148                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1149                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1150         }
1151
1152         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1153
1154         HWRM_CHECK_RESULT();
1155         HWRM_UNLOCK();
1156
1157         return rc;
1158 }
1159
1160 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1161                                    struct bnxt_link_info *link_info)
1162 {
1163         int rc = 0;
1164         struct hwrm_port_phy_qcfg_input req = {0};
1165         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1166
1167         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1168
1169         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1170
1171         HWRM_CHECK_RESULT();
1172
1173         link_info->phy_link_status = resp->link;
1174         link_info->link_up =
1175                 (link_info->phy_link_status ==
1176                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1177         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1178         link_info->duplex = resp->duplex_cfg;
1179         link_info->pause = resp->pause;
1180         link_info->auto_pause = resp->auto_pause;
1181         link_info->force_pause = resp->force_pause;
1182         link_info->auto_mode = resp->auto_mode;
1183         link_info->phy_type = resp->phy_type;
1184         link_info->media_type = resp->media_type;
1185
1186         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1187         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1188         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1189         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1190         link_info->phy_ver[0] = resp->phy_maj;
1191         link_info->phy_ver[1] = resp->phy_min;
1192         link_info->phy_ver[2] = resp->phy_bld;
1193
1194         HWRM_UNLOCK();
1195
1196         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1197         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1198         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1199         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1200         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1201                     link_info->auto_link_speed_mask);
1202         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1203                     link_info->force_link_speed);
1204
1205         return rc;
1206 }
1207
1208 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1209 {
1210         int rc = 0;
1211         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1212         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1213         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1214         int i;
1215
1216 get_rx_info:
1217         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1218
1219         req.flags = rte_cpu_to_le_32(dir);
1220         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1221         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1222             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1223                 req.drv_qmap_cap =
1224                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1225         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1226
1227         HWRM_CHECK_RESULT();
1228
1229         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1230                 GET_TX_QUEUE_INFO(0);
1231                 GET_TX_QUEUE_INFO(1);
1232                 GET_TX_QUEUE_INFO(2);
1233                 GET_TX_QUEUE_INFO(3);
1234                 GET_TX_QUEUE_INFO(4);
1235                 GET_TX_QUEUE_INFO(5);
1236                 GET_TX_QUEUE_INFO(6);
1237                 GET_TX_QUEUE_INFO(7);
1238         } else  {
1239                 GET_RX_QUEUE_INFO(0);
1240                 GET_RX_QUEUE_INFO(1);
1241                 GET_RX_QUEUE_INFO(2);
1242                 GET_RX_QUEUE_INFO(3);
1243                 GET_RX_QUEUE_INFO(4);
1244                 GET_RX_QUEUE_INFO(5);
1245                 GET_RX_QUEUE_INFO(6);
1246                 GET_RX_QUEUE_INFO(7);
1247         }
1248
1249         HWRM_UNLOCK();
1250
1251         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1252                 goto done;
1253
1254         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1255                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1256         } else {
1257                 int j;
1258
1259                 /* iterate and find the COSq profile to use for Tx */
1260                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1261                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1262                                 if (bp->tx_cos_queue[i].id != 0xff)
1263                                         bp->tx_cosq_id[j++] =
1264                                                 bp->tx_cos_queue[i].id;
1265                         }
1266                 } else {
1267                         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1268                                 if (bp->tx_cos_queue[i].profile ==
1269                                         HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1270                                         bp->tx_cosq_id[0] =
1271                                                 bp->tx_cos_queue[i].id;
1272                                         break;
1273                                 }
1274                         }
1275                 }
1276         }
1277
1278         bp->max_tc = resp->max_configurable_queues;
1279         bp->max_lltc = resp->max_configurable_lossless_queues;
1280         if (bp->max_tc > BNXT_MAX_QUEUE)
1281                 bp->max_tc = BNXT_MAX_QUEUE;
1282         bp->max_q = bp->max_tc;
1283
1284         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1285                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1286                 goto get_rx_info;
1287         }
1288
1289 done:
1290         return rc;
1291 }
1292
1293 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1294                          struct bnxt_ring *ring,
1295                          uint32_t ring_type, uint32_t map_index,
1296                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1297                          uint16_t tx_cosq_id)
1298 {
1299         int rc = 0;
1300         uint32_t enables = 0;
1301         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1302         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1303         struct rte_mempool *mb_pool;
1304         uint16_t rx_buf_size;
1305
1306         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1307
1308         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1309         req.fbo = rte_cpu_to_le_32(0);
1310         /* Association of ring index with doorbell index */
1311         req.logical_id = rte_cpu_to_le_16(map_index);
1312         req.length = rte_cpu_to_le_32(ring->ring_size);
1313
1314         switch (ring_type) {
1315         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1316                 req.ring_type = ring_type;
1317                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1318                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1319                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1320                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1321                         enables |=
1322                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1323                 break;
1324         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1325                 req.ring_type = ring_type;
1326                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1327                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1328                 if (BNXT_CHIP_THOR(bp)) {
1329                         mb_pool = bp->rx_queues[0]->mb_pool;
1330                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1331                                       RTE_PKTMBUF_HEADROOM;
1332                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1333                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1334                         enables |=
1335                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1336                 }
1337                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1338                         enables |=
1339                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1340                 break;
1341         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1342                 req.ring_type = ring_type;
1343                 if (BNXT_HAS_NQ(bp)) {
1344                         /* Association of cp ring with nq */
1345                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1346                         enables |=
1347                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1348                 }
1349                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1350                 break;
1351         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1352                 req.ring_type = ring_type;
1353                 req.page_size = BNXT_PAGE_SHFT;
1354                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1355                 break;
1356         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1357                 req.ring_type = ring_type;
1358                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1359
1360                 mb_pool = bp->rx_queues[0]->mb_pool;
1361                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1362                               RTE_PKTMBUF_HEADROOM;
1363                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1364                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1365
1366                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1367                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1368                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1369                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1370                 break;
1371         default:
1372                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1373                         ring_type);
1374                 HWRM_UNLOCK();
1375                 return -EINVAL;
1376         }
1377         req.enables = rte_cpu_to_le_32(enables);
1378
1379         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1380
1381         if (rc || resp->error_code) {
1382                 if (rc == 0 && resp->error_code)
1383                         rc = rte_le_to_cpu_16(resp->error_code);
1384                 switch (ring_type) {
1385                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1386                         PMD_DRV_LOG(ERR,
1387                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1388                         HWRM_UNLOCK();
1389                         return rc;
1390                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1391                         PMD_DRV_LOG(ERR,
1392                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1393                         HWRM_UNLOCK();
1394                         return rc;
1395                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1396                         PMD_DRV_LOG(ERR,
1397                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1398                                     rc);
1399                         HWRM_UNLOCK();
1400                         return rc;
1401                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1402                         PMD_DRV_LOG(ERR,
1403                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1404                         HWRM_UNLOCK();
1405                         return rc;
1406                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1407                         PMD_DRV_LOG(ERR,
1408                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1409                         HWRM_UNLOCK();
1410                         return rc;
1411                 default:
1412                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1413                         HWRM_UNLOCK();
1414                         return rc;
1415                 }
1416         }
1417
1418         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1419         HWRM_UNLOCK();
1420         return rc;
1421 }
1422
1423 int bnxt_hwrm_ring_free(struct bnxt *bp,
1424                         struct bnxt_ring *ring, uint32_t ring_type)
1425 {
1426         int rc;
1427         struct hwrm_ring_free_input req = {.req_type = 0 };
1428         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1429
1430         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1431
1432         req.ring_type = ring_type;
1433         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1434
1435         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1436
1437         if (rc || resp->error_code) {
1438                 if (rc == 0 && resp->error_code)
1439                         rc = rte_le_to_cpu_16(resp->error_code);
1440                 HWRM_UNLOCK();
1441
1442                 switch (ring_type) {
1443                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1444                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1445                                 rc);
1446                         return rc;
1447                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1448                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1449                                 rc);
1450                         return rc;
1451                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1452                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1453                                 rc);
1454                         return rc;
1455                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1456                         PMD_DRV_LOG(ERR,
1457                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1458                         return rc;
1459                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1460                         PMD_DRV_LOG(ERR,
1461                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1462                         return rc;
1463                 default:
1464                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1465                         return rc;
1466                 }
1467         }
1468         HWRM_UNLOCK();
1469         return 0;
1470 }
1471
1472 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1473 {
1474         int rc = 0;
1475         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1476         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1477
1478         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1479
1480         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1481         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1482         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1483         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1484
1485         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1486
1487         HWRM_CHECK_RESULT();
1488
1489         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1490
1491         HWRM_UNLOCK();
1492
1493         return rc;
1494 }
1495
1496 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1497 {
1498         int rc;
1499         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1500         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1501
1502         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1503
1504         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1505
1506         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1507
1508         HWRM_CHECK_RESULT();
1509         HWRM_UNLOCK();
1510
1511         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1512         return rc;
1513 }
1514
1515 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1516 {
1517         int rc = 0;
1518         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1519         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1520
1521         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1522                 return rc;
1523
1524         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1525
1526         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1527
1528         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1529
1530         HWRM_CHECK_RESULT();
1531         HWRM_UNLOCK();
1532
1533         return rc;
1534 }
1535
1536 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1537                                 unsigned int idx __rte_unused)
1538 {
1539         int rc;
1540         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1541         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1542
1543         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1544
1545         req.update_period_ms = rte_cpu_to_le_32(0);
1546
1547         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1548
1549         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1550
1551         HWRM_CHECK_RESULT();
1552
1553         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1554
1555         HWRM_UNLOCK();
1556
1557         return rc;
1558 }
1559
1560 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1561                                 unsigned int idx __rte_unused)
1562 {
1563         int rc;
1564         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1565         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1566
1567         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1568
1569         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1570
1571         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1572
1573         HWRM_CHECK_RESULT();
1574         HWRM_UNLOCK();
1575
1576         return rc;
1577 }
1578
1579 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1580 {
1581         int rc = 0, i, j;
1582         struct hwrm_vnic_alloc_input req = { 0 };
1583         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1584
1585         if (!BNXT_HAS_RING_GRPS(bp))
1586                 goto skip_ring_grps;
1587
1588         /* map ring groups to this vnic */
1589         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1590                 vnic->start_grp_id, vnic->end_grp_id);
1591         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1592                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1593
1594         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1595         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1596         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1597         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1598
1599 skip_ring_grps:
1600         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1601         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1602
1603         if (vnic->func_default)
1604                 req.flags =
1605                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1606         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1607
1608         HWRM_CHECK_RESULT();
1609
1610         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1611         HWRM_UNLOCK();
1612         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1613         return rc;
1614 }
1615
1616 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1617                                         struct bnxt_vnic_info *vnic,
1618                                         struct bnxt_plcmodes_cfg *pmode)
1619 {
1620         int rc = 0;
1621         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1622         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1623
1624         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1625
1626         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1627
1628         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1629
1630         HWRM_CHECK_RESULT();
1631
1632         pmode->flags = rte_le_to_cpu_32(resp->flags);
1633         /* dflt_vnic bit doesn't exist in the _cfg command */
1634         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1635         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1636         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1637         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1638
1639         HWRM_UNLOCK();
1640
1641         return rc;
1642 }
1643
1644 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1645                                        struct bnxt_vnic_info *vnic,
1646                                        struct bnxt_plcmodes_cfg *pmode)
1647 {
1648         int rc = 0;
1649         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1650         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1651
1652         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1653                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1654                 return rc;
1655         }
1656
1657         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1658
1659         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1660         req.flags = rte_cpu_to_le_32(pmode->flags);
1661         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1662         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1663         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1664         req.enables = rte_cpu_to_le_32(
1665             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1666             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1667             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1668         );
1669
1670         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1671
1672         HWRM_CHECK_RESULT();
1673         HWRM_UNLOCK();
1674
1675         return rc;
1676 }
1677
1678 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1679 {
1680         int rc = 0;
1681         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1682         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1683         struct bnxt_plcmodes_cfg pmodes = { 0 };
1684         uint32_t ctx_enable_flag = 0;
1685         uint32_t enables = 0;
1686
1687         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1688                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1689                 return rc;
1690         }
1691
1692         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1693         if (rc)
1694                 return rc;
1695
1696         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1697
1698         if (BNXT_CHIP_THOR(bp)) {
1699                 struct bnxt_rx_queue *rxq =
1700                         bp->eth_dev->data->rx_queues[vnic->start_grp_id];
1701                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1702                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1703
1704                 req.default_rx_ring_id =
1705                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1706                 req.default_cmpl_ring_id =
1707                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1708                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1709                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1710                 goto config_mru;
1711         }
1712
1713         /* Only RSS support for now TBD: COS & LB */
1714         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1715         if (vnic->lb_rule != 0xffff)
1716                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1717         if (vnic->cos_rule != 0xffff)
1718                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1719         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1720                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1721                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1722         }
1723         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1724                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1725                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1726         }
1727
1728         enables |= ctx_enable_flag;
1729         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1730         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1731         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1732         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1733
1734 config_mru:
1735         req.enables = rte_cpu_to_le_32(enables);
1736         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1737         req.mru = rte_cpu_to_le_16(vnic->mru);
1738         /* Configure default VNIC only once. */
1739         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1740                 req.flags |=
1741                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1742                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1743         }
1744         if (vnic->vlan_strip)
1745                 req.flags |=
1746                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1747         if (vnic->bd_stall)
1748                 req.flags |=
1749                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1750         if (vnic->roce_dual)
1751                 req.flags |= rte_cpu_to_le_32(
1752                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1753         if (vnic->roce_only)
1754                 req.flags |= rte_cpu_to_le_32(
1755                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1756         if (vnic->rss_dflt_cr)
1757                 req.flags |= rte_cpu_to_le_32(
1758                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1759
1760         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1761
1762         HWRM_CHECK_RESULT();
1763         HWRM_UNLOCK();
1764
1765         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1766
1767         return rc;
1768 }
1769
1770 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1771                 int16_t fw_vf_id)
1772 {
1773         int rc = 0;
1774         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1775         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1776
1777         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1778                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1779                 return rc;
1780         }
1781         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1782
1783         req.enables =
1784                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1785         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1786         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1787
1788         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1789
1790         HWRM_CHECK_RESULT();
1791
1792         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1793         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1794         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1795         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1796         vnic->mru = rte_le_to_cpu_16(resp->mru);
1797         vnic->func_default = rte_le_to_cpu_32(
1798                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1799         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1800                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1801         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1802                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1803         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1804                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1805         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1806                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1807         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1808                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1809
1810         HWRM_UNLOCK();
1811
1812         return rc;
1813 }
1814
1815 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1816                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1817 {
1818         int rc = 0;
1819         uint16_t ctx_id;
1820         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1821         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1822                                                 bp->hwrm_cmd_resp_addr;
1823
1824         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1825
1826         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1827         HWRM_CHECK_RESULT();
1828
1829         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1830         if (!BNXT_HAS_RING_GRPS(bp))
1831                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1832         else if (ctx_idx == 0)
1833                 vnic->rss_rule = ctx_id;
1834
1835         HWRM_UNLOCK();
1836
1837         return rc;
1838 }
1839
1840 static
1841 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1842                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1843 {
1844         int rc = 0;
1845         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1846         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1847                                                 bp->hwrm_cmd_resp_addr;
1848
1849         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1850                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1851                 return rc;
1852         }
1853         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1854
1855         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1856
1857         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1858
1859         HWRM_CHECK_RESULT();
1860         HWRM_UNLOCK();
1861
1862         return rc;
1863 }
1864
1865 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1866 {
1867         int rc = 0;
1868
1869         if (BNXT_CHIP_THOR(bp)) {
1870                 int j;
1871
1872                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1873                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
1874                                                       vnic,
1875                                                       vnic->fw_grp_ids[j]);
1876                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1877                 }
1878                 vnic->num_lb_ctxts = 0;
1879         } else {
1880                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1881                 vnic->rss_rule = INVALID_HW_RING_ID;
1882         }
1883
1884         return rc;
1885 }
1886
1887 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1888 {
1889         int rc = 0;
1890         struct hwrm_vnic_free_input req = {.req_type = 0 };
1891         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1892
1893         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1894                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1895                 return rc;
1896         }
1897
1898         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1899
1900         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1901
1902         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1903
1904         HWRM_CHECK_RESULT();
1905         HWRM_UNLOCK();
1906
1907         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1908         /* Configure default VNIC again if necessary. */
1909         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1910                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1911
1912         return rc;
1913 }
1914
1915 static int
1916 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1917 {
1918         int i;
1919         int rc = 0;
1920         int nr_ctxs = vnic->num_lb_ctxts;
1921         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1922         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1923
1924         for (i = 0; i < nr_ctxs; i++) {
1925                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1926
1927                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1928                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1929                 req.hash_mode_flags = vnic->hash_mode;
1930
1931                 req.hash_key_tbl_addr =
1932                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1933
1934                 req.ring_grp_tbl_addr =
1935                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1936                                          i * HW_HASH_INDEX_SIZE);
1937                 req.ring_table_pair_index = i;
1938                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1939
1940                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1941                                             BNXT_USE_CHIMP_MB);
1942
1943                 HWRM_CHECK_RESULT();
1944                 HWRM_UNLOCK();
1945         }
1946
1947         return rc;
1948 }
1949
1950 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1951                            struct bnxt_vnic_info *vnic)
1952 {
1953         int rc = 0;
1954         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1955         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1956
1957         if (!vnic->rss_table)
1958                 return 0;
1959
1960         if (BNXT_CHIP_THOR(bp))
1961                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1962
1963         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1964
1965         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1966         req.hash_mode_flags = vnic->hash_mode;
1967
1968         req.ring_grp_tbl_addr =
1969             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1970         req.hash_key_tbl_addr =
1971             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1972         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1973         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1974
1975         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1976
1977         HWRM_CHECK_RESULT();
1978         HWRM_UNLOCK();
1979
1980         return rc;
1981 }
1982
1983 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1984                         struct bnxt_vnic_info *vnic)
1985 {
1986         int rc = 0;
1987         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1988         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1989         uint16_t size;
1990
1991         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1992                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1993                 return rc;
1994         }
1995
1996         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1997
1998         req.flags = rte_cpu_to_le_32(
1999                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2000
2001         req.enables = rte_cpu_to_le_32(
2002                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2003
2004         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2005         size -= RTE_PKTMBUF_HEADROOM;
2006         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2007
2008         req.jumbo_thresh = rte_cpu_to_le_16(size);
2009         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2010
2011         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2012
2013         HWRM_CHECK_RESULT();
2014         HWRM_UNLOCK();
2015
2016         return rc;
2017 }
2018
2019 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2020                         struct bnxt_vnic_info *vnic, bool enable)
2021 {
2022         int rc = 0;
2023         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2024         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2025
2026         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2027                 if (enable)
2028                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2029                 return -ENOTSUP;
2030         }
2031
2032         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2033                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2034                 return 0;
2035         }
2036
2037         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2038
2039         if (enable) {
2040                 req.enables = rte_cpu_to_le_32(
2041                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2042                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2043                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2044                 req.flags = rte_cpu_to_le_32(
2045                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2046                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2047                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2048                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2049                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2050                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2051                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2052                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2053                 req.min_agg_len = rte_cpu_to_le_32(512);
2054         }
2055         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2056
2057         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2058
2059         HWRM_CHECK_RESULT();
2060         HWRM_UNLOCK();
2061
2062         return rc;
2063 }
2064
2065 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2066 {
2067         struct hwrm_func_cfg_input req = {0};
2068         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2069         int rc;
2070
2071         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2072         req.enables = rte_cpu_to_le_32(
2073                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2074         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2075         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2076
2077         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2078
2079         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2080         HWRM_CHECK_RESULT();
2081         HWRM_UNLOCK();
2082
2083         bp->pf.vf_info[vf].random_mac = false;
2084
2085         return rc;
2086 }
2087
2088 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2089                                   uint64_t *dropped)
2090 {
2091         int rc = 0;
2092         struct hwrm_func_qstats_input req = {.req_type = 0};
2093         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2094
2095         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2096
2097         req.fid = rte_cpu_to_le_16(fid);
2098
2099         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2100
2101         HWRM_CHECK_RESULT();
2102
2103         if (dropped)
2104                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2105
2106         HWRM_UNLOCK();
2107
2108         return rc;
2109 }
2110
2111 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2112                           struct rte_eth_stats *stats)
2113 {
2114         int rc = 0;
2115         struct hwrm_func_qstats_input req = {.req_type = 0};
2116         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2117
2118         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2119
2120         req.fid = rte_cpu_to_le_16(fid);
2121
2122         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2123
2124         HWRM_CHECK_RESULT();
2125
2126         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2127         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2128         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2129         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2130         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2131         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2132
2133         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2134         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2135         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2136         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2137         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2138         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2139
2140         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2141         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2142         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2143
2144         HWRM_UNLOCK();
2145
2146         return rc;
2147 }
2148
2149 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2150 {
2151         int rc = 0;
2152         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2153         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2154
2155         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2156
2157         req.fid = rte_cpu_to_le_16(fid);
2158
2159         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2160
2161         HWRM_CHECK_RESULT();
2162         HWRM_UNLOCK();
2163
2164         return rc;
2165 }
2166
2167 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2168 {
2169         unsigned int i;
2170         int rc = 0;
2171
2172         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2173                 struct bnxt_tx_queue *txq;
2174                 struct bnxt_rx_queue *rxq;
2175                 struct bnxt_cp_ring_info *cpr;
2176
2177                 if (i >= bp->rx_cp_nr_rings) {
2178                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2179                         cpr = txq->cp_ring;
2180                 } else {
2181                         rxq = bp->rx_queues[i];
2182                         cpr = rxq->cp_ring;
2183                 }
2184
2185                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2186                 if (rc)
2187                         return rc;
2188         }
2189         return 0;
2190 }
2191
2192 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2193 {
2194         int rc;
2195         unsigned int i;
2196         struct bnxt_cp_ring_info *cpr;
2197
2198         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2199
2200                 if (i >= bp->rx_cp_nr_rings) {
2201                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2202                 } else {
2203                         cpr = bp->rx_queues[i]->cp_ring;
2204                         if (BNXT_HAS_RING_GRPS(bp))
2205                                 bp->grp_info[i].fw_stats_ctx = -1;
2206                 }
2207                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2208                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2209                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2210                         if (rc)
2211                                 return rc;
2212                 }
2213         }
2214         return 0;
2215 }
2216
2217 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2218 {
2219         unsigned int i;
2220         int rc = 0;
2221
2222         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2223                 struct bnxt_tx_queue *txq;
2224                 struct bnxt_rx_queue *rxq;
2225                 struct bnxt_cp_ring_info *cpr;
2226
2227                 if (i >= bp->rx_cp_nr_rings) {
2228                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2229                         cpr = txq->cp_ring;
2230                 } else {
2231                         rxq = bp->rx_queues[i];
2232                         cpr = rxq->cp_ring;
2233                 }
2234
2235                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2236
2237                 if (rc)
2238                         return rc;
2239         }
2240         return rc;
2241 }
2242
2243 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2244 {
2245         uint16_t idx;
2246         uint32_t rc = 0;
2247
2248         if (!BNXT_HAS_RING_GRPS(bp))
2249                 return 0;
2250
2251         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2252
2253                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2254                         continue;
2255
2256                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2257
2258                 if (rc)
2259                         return rc;
2260         }
2261         return rc;
2262 }
2263
2264 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2265 {
2266         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2267
2268         bnxt_hwrm_ring_free(bp, cp_ring,
2269                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2270         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2271         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2272                                      sizeof(*cpr->cp_desc_ring));
2273         cpr->cp_raw_cons = 0;
2274         cpr->valid = 0;
2275 }
2276
2277 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2278 {
2279         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2280
2281         bnxt_hwrm_ring_free(bp, cp_ring,
2282                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2283         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2284         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2285                         sizeof(*cpr->cp_desc_ring));
2286         cpr->cp_raw_cons = 0;
2287         cpr->valid = 0;
2288 }
2289
2290 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2291 {
2292         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2293         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2294         struct bnxt_ring *ring = rxr->rx_ring_struct;
2295         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2296
2297         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2298                 bnxt_hwrm_ring_free(bp, ring,
2299                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2300                 ring->fw_ring_id = INVALID_HW_RING_ID;
2301                 if (BNXT_HAS_RING_GRPS(bp))
2302                         bp->grp_info[queue_index].rx_fw_ring_id =
2303                                                         INVALID_HW_RING_ID;
2304                 memset(rxr->rx_desc_ring, 0,
2305                        rxr->rx_ring_struct->ring_size *
2306                        sizeof(*rxr->rx_desc_ring));
2307                 memset(rxr->rx_buf_ring, 0,
2308                        rxr->rx_ring_struct->ring_size *
2309                        sizeof(*rxr->rx_buf_ring));
2310                 rxr->rx_prod = 0;
2311         }
2312         ring = rxr->ag_ring_struct;
2313         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2314                 bnxt_hwrm_ring_free(bp, ring,
2315                                     BNXT_CHIP_THOR(bp) ?
2316                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2317                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2318                 ring->fw_ring_id = INVALID_HW_RING_ID;
2319                 memset(rxr->ag_buf_ring, 0,
2320                        rxr->ag_ring_struct->ring_size *
2321                        sizeof(*rxr->ag_buf_ring));
2322                 rxr->ag_prod = 0;
2323                 if (BNXT_HAS_RING_GRPS(bp))
2324                         bp->grp_info[queue_index].ag_fw_ring_id =
2325                                                         INVALID_HW_RING_ID;
2326         }
2327         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2328                 bnxt_free_cp_ring(bp, cpr);
2329
2330         if (BNXT_HAS_RING_GRPS(bp))
2331                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2332 }
2333
2334 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2335 {
2336         unsigned int i;
2337
2338         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2339                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2340                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2341                 struct bnxt_ring *ring = txr->tx_ring_struct;
2342                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2343
2344                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2345                         bnxt_hwrm_ring_free(bp, ring,
2346                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2347                         ring->fw_ring_id = INVALID_HW_RING_ID;
2348                         memset(txr->tx_desc_ring, 0,
2349                                         txr->tx_ring_struct->ring_size *
2350                                         sizeof(*txr->tx_desc_ring));
2351                         memset(txr->tx_buf_ring, 0,
2352                                         txr->tx_ring_struct->ring_size *
2353                                         sizeof(*txr->tx_buf_ring));
2354                         txr->tx_prod = 0;
2355                         txr->tx_cons = 0;
2356                 }
2357                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2358                         bnxt_free_cp_ring(bp, cpr);
2359                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2360                 }
2361         }
2362
2363         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2364                 bnxt_free_hwrm_rx_ring(bp, i);
2365
2366         return 0;
2367 }
2368
2369 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2370 {
2371         uint16_t i;
2372         uint32_t rc = 0;
2373
2374         if (!BNXT_HAS_RING_GRPS(bp))
2375                 return 0;
2376
2377         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2378                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2379                 if (rc)
2380                         return rc;
2381         }
2382         return rc;
2383 }
2384
2385 /*
2386  * HWRM utility functions
2387  */
2388
2389 void bnxt_free_hwrm_resources(struct bnxt *bp)
2390 {
2391         /* Release memzone */
2392         rte_free(bp->hwrm_cmd_resp_addr);
2393         rte_free(bp->hwrm_short_cmd_req_addr);
2394         bp->hwrm_cmd_resp_addr = NULL;
2395         bp->hwrm_short_cmd_req_addr = NULL;
2396         bp->hwrm_cmd_resp_dma_addr = 0;
2397         bp->hwrm_short_cmd_req_dma_addr = 0;
2398 }
2399
2400 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2401 {
2402         struct rte_pci_device *pdev = bp->pdev;
2403         char type[RTE_MEMZONE_NAMESIZE];
2404
2405         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2406                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2407         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2408         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2409         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2410         if (bp->hwrm_cmd_resp_addr == NULL)
2411                 return -ENOMEM;
2412         bp->hwrm_cmd_resp_dma_addr =
2413                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2414         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2415                 PMD_DRV_LOG(ERR,
2416                         "unable to map response address to physical memory\n");
2417                 return -ENOMEM;
2418         }
2419         rte_spinlock_init(&bp->hwrm_lock);
2420
2421         return 0;
2422 }
2423
2424 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2425 {
2426         struct bnxt_filter_info *filter;
2427         int rc = 0;
2428
2429         STAILQ_FOREACH(filter, &vnic->filter, next) {
2430                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2431                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2432                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2433                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2434                 else
2435                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2436                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2437                 bnxt_free_filter(bp, filter);
2438         }
2439         return rc;
2440 }
2441
2442 static int
2443 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2444 {
2445         struct bnxt_filter_info *filter;
2446         struct rte_flow *flow;
2447         int rc = 0;
2448
2449         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2450                 flow = STAILQ_FIRST(&vnic->flow_list);
2451                 filter = flow->filter;
2452                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2453                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2454                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2455                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2456                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2457                 else
2458                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2459
2460                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2461                 rte_free(flow);
2462         }
2463         return rc;
2464 }
2465
2466 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2467 {
2468         struct bnxt_filter_info *filter;
2469         int rc = 0;
2470
2471         STAILQ_FOREACH(filter, &vnic->filter, next) {
2472                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2473                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2474                                                      filter);
2475                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2476                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2477                                                          filter);
2478                 else
2479                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2480                                                      filter);
2481                 if (rc)
2482                         break;
2483         }
2484         return rc;
2485 }
2486
2487 void bnxt_free_tunnel_ports(struct bnxt *bp)
2488 {
2489         if (bp->vxlan_port_cnt)
2490                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2491                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2492         bp->vxlan_port = 0;
2493         if (bp->geneve_port_cnt)
2494                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2495                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2496         bp->geneve_port = 0;
2497 }
2498
2499 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2500 {
2501         int i;
2502
2503         if (bp->vnic_info == NULL)
2504                 return;
2505
2506         /*
2507          * Cleanup VNICs in reverse order, to make sure the L2 filter
2508          * from vnic0 is last to be cleaned up.
2509          */
2510         for (i = bp->max_vnics - 1; i >= 0; i--) {
2511                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2512
2513                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2514                         continue;
2515
2516                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2517
2518                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2519
2520                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2521
2522                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2523
2524                 bnxt_hwrm_vnic_free(bp, vnic);
2525
2526                 rte_free(vnic->fw_grp_ids);
2527         }
2528         /* Ring resources */
2529         bnxt_free_all_hwrm_rings(bp);
2530         bnxt_free_all_hwrm_ring_grps(bp);
2531         bnxt_free_all_hwrm_stat_ctxs(bp);
2532         bnxt_free_tunnel_ports(bp);
2533 }
2534
2535 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2536 {
2537         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2538
2539         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2540                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2541
2542         switch (conf_link_speed) {
2543         case ETH_LINK_SPEED_10M_HD:
2544         case ETH_LINK_SPEED_100M_HD:
2545                 /* FALLTHROUGH */
2546                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2547         }
2548         return hw_link_duplex;
2549 }
2550
2551 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2552 {
2553         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2554 }
2555
2556 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2557 {
2558         uint16_t eth_link_speed = 0;
2559
2560         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2561                 return ETH_LINK_SPEED_AUTONEG;
2562
2563         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2564         case ETH_LINK_SPEED_100M:
2565         case ETH_LINK_SPEED_100M_HD:
2566                 /* FALLTHROUGH */
2567                 eth_link_speed =
2568                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2569                 break;
2570         case ETH_LINK_SPEED_1G:
2571                 eth_link_speed =
2572                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2573                 break;
2574         case ETH_LINK_SPEED_2_5G:
2575                 eth_link_speed =
2576                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2577                 break;
2578         case ETH_LINK_SPEED_10G:
2579                 eth_link_speed =
2580                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2581                 break;
2582         case ETH_LINK_SPEED_20G:
2583                 eth_link_speed =
2584                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2585                 break;
2586         case ETH_LINK_SPEED_25G:
2587                 eth_link_speed =
2588                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2589                 break;
2590         case ETH_LINK_SPEED_40G:
2591                 eth_link_speed =
2592                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2593                 break;
2594         case ETH_LINK_SPEED_50G:
2595                 eth_link_speed =
2596                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2597                 break;
2598         case ETH_LINK_SPEED_100G:
2599                 eth_link_speed =
2600                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2601                 break;
2602         default:
2603                 PMD_DRV_LOG(ERR,
2604                         "Unsupported link speed %d; default to AUTO\n",
2605                         conf_link_speed);
2606                 break;
2607         }
2608         return eth_link_speed;
2609 }
2610
2611 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2612                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2613                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2614                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2615
2616 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2617 {
2618         uint32_t one_speed;
2619
2620         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2621                 return 0;
2622
2623         if (link_speed & ETH_LINK_SPEED_FIXED) {
2624                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2625
2626                 if (one_speed & (one_speed - 1)) {
2627                         PMD_DRV_LOG(ERR,
2628                                 "Invalid advertised speeds (%u) for port %u\n",
2629                                 link_speed, port_id);
2630                         return -EINVAL;
2631                 }
2632                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2633                         PMD_DRV_LOG(ERR,
2634                                 "Unsupported advertised speed (%u) for port %u\n",
2635                                 link_speed, port_id);
2636                         return -EINVAL;
2637                 }
2638         } else {
2639                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2640                         PMD_DRV_LOG(ERR,
2641                                 "Unsupported advertised speeds (%u) for port %u\n",
2642                                 link_speed, port_id);
2643                         return -EINVAL;
2644                 }
2645         }
2646         return 0;
2647 }
2648
2649 static uint16_t
2650 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2651 {
2652         uint16_t ret = 0;
2653
2654         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2655                 if (bp->link_info.support_speeds)
2656                         return bp->link_info.support_speeds;
2657                 link_speed = BNXT_SUPPORTED_SPEEDS;
2658         }
2659
2660         if (link_speed & ETH_LINK_SPEED_100M)
2661                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2662         if (link_speed & ETH_LINK_SPEED_100M_HD)
2663                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2664         if (link_speed & ETH_LINK_SPEED_1G)
2665                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2666         if (link_speed & ETH_LINK_SPEED_2_5G)
2667                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2668         if (link_speed & ETH_LINK_SPEED_10G)
2669                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2670         if (link_speed & ETH_LINK_SPEED_20G)
2671                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2672         if (link_speed & ETH_LINK_SPEED_25G)
2673                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2674         if (link_speed & ETH_LINK_SPEED_40G)
2675                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2676         if (link_speed & ETH_LINK_SPEED_50G)
2677                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2678         if (link_speed & ETH_LINK_SPEED_100G)
2679                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2680         return ret;
2681 }
2682
2683 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2684 {
2685         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2686
2687         switch (hw_link_speed) {
2688         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2689                 eth_link_speed = ETH_SPEED_NUM_100M;
2690                 break;
2691         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2692                 eth_link_speed = ETH_SPEED_NUM_1G;
2693                 break;
2694         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2695                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2696                 break;
2697         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2698                 eth_link_speed = ETH_SPEED_NUM_10G;
2699                 break;
2700         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2701                 eth_link_speed = ETH_SPEED_NUM_20G;
2702                 break;
2703         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2704                 eth_link_speed = ETH_SPEED_NUM_25G;
2705                 break;
2706         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2707                 eth_link_speed = ETH_SPEED_NUM_40G;
2708                 break;
2709         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2710                 eth_link_speed = ETH_SPEED_NUM_50G;
2711                 break;
2712         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2713                 eth_link_speed = ETH_SPEED_NUM_100G;
2714                 break;
2715         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2716         default:
2717                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2718                         hw_link_speed);
2719                 break;
2720         }
2721         return eth_link_speed;
2722 }
2723
2724 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2725 {
2726         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2727
2728         switch (hw_link_duplex) {
2729         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2730         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2731                 /* FALLTHROUGH */
2732                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2733                 break;
2734         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2735                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2736                 break;
2737         default:
2738                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2739                         hw_link_duplex);
2740                 break;
2741         }
2742         return eth_link_duplex;
2743 }
2744
2745 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2746 {
2747         int rc = 0;
2748         struct bnxt_link_info *link_info = &bp->link_info;
2749
2750         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2751         if (rc) {
2752                 PMD_DRV_LOG(ERR,
2753                         "Get link config failed with rc %d\n", rc);
2754                 goto exit;
2755         }
2756         if (link_info->link_speed)
2757                 link->link_speed =
2758                         bnxt_parse_hw_link_speed(link_info->link_speed);
2759         else
2760                 link->link_speed = ETH_SPEED_NUM_NONE;
2761         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2762         link->link_status = link_info->link_up;
2763         link->link_autoneg = link_info->auto_mode ==
2764                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2765                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2766 exit:
2767         return rc;
2768 }
2769
2770 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2771 {
2772         int rc = 0;
2773         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2774         struct bnxt_link_info link_req;
2775         uint16_t speed, autoneg;
2776
2777         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2778                 return 0;
2779
2780         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2781                         bp->eth_dev->data->port_id);
2782         if (rc)
2783                 goto error;
2784
2785         memset(&link_req, 0, sizeof(link_req));
2786         link_req.link_up = link_up;
2787         if (!link_up)
2788                 goto port_phy_cfg;
2789
2790         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2791         if (BNXT_CHIP_THOR(bp) &&
2792             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2793                 /* 40G is not supported as part of media auto detect.
2794                  * The speed should be forced and autoneg disabled
2795                  * to configure 40G speed.
2796                  */
2797                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2798                 autoneg = 0;
2799         }
2800
2801         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2802         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2803         /* Autoneg can be done only when the FW allows.
2804          * When user configures fixed speed of 40G and later changes to
2805          * any other speed, auto_link_speed/force_link_speed is still set
2806          * to 40G until link comes up at new speed.
2807          */
2808         if (autoneg == 1 &&
2809             !(!BNXT_CHIP_THOR(bp) &&
2810               (bp->link_info.auto_link_speed ||
2811                bp->link_info.force_link_speed))) {
2812                 link_req.phy_flags |=
2813                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2814                 link_req.auto_link_speed_mask =
2815                         bnxt_parse_eth_link_speed_mask(bp,
2816                                                        dev_conf->link_speeds);
2817         } else {
2818                 if (bp->link_info.phy_type ==
2819                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2820                     bp->link_info.phy_type ==
2821                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2822                     bp->link_info.media_type ==
2823                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2824                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2825                         return -EINVAL;
2826                 }
2827
2828                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2829                 /* If user wants a particular speed try that first. */
2830                 if (speed)
2831                         link_req.link_speed = speed;
2832                 else if (bp->link_info.force_link_speed)
2833                         link_req.link_speed = bp->link_info.force_link_speed;
2834                 else
2835                         link_req.link_speed = bp->link_info.auto_link_speed;
2836         }
2837         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2838         link_req.auto_pause = bp->link_info.auto_pause;
2839         link_req.force_pause = bp->link_info.force_pause;
2840
2841 port_phy_cfg:
2842         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2843         if (rc) {
2844                 PMD_DRV_LOG(ERR,
2845                         "Set link config failed with rc %d\n", rc);
2846         }
2847
2848 error:
2849         return rc;
2850 }
2851
2852 /* JIRA 22088 */
2853 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2854 {
2855         struct hwrm_func_qcfg_input req = {0};
2856         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2857         uint16_t flags;
2858         int rc = 0;
2859
2860         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2861         req.fid = rte_cpu_to_le_16(0xffff);
2862
2863         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2864
2865         HWRM_CHECK_RESULT();
2866
2867         /* Hard Coded.. 0xfff VLAN ID mask */
2868         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2869         flags = rte_le_to_cpu_16(resp->flags);
2870         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2871                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2872
2873         if (BNXT_VF(bp) &&
2874             !BNXT_VF_IS_TRUSTED(bp) &&
2875             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2876                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2877                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2878         } else if (BNXT_VF(bp) &&
2879                    BNXT_VF_IS_TRUSTED(bp) &&
2880                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2881                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2882                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2883         }
2884
2885         if (mtu)
2886                 *mtu = rte_le_to_cpu_16(resp->mtu);
2887
2888         switch (resp->port_partition_type) {
2889         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2890         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2891         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2892                 /* FALLTHROUGH */
2893                 bp->port_partition_type = resp->port_partition_type;
2894                 break;
2895         default:
2896                 bp->port_partition_type = 0;
2897                 break;
2898         }
2899
2900         HWRM_UNLOCK();
2901
2902         return rc;
2903 }
2904
2905 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2906                                    struct hwrm_func_qcaps_output *qcaps)
2907 {
2908         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2909         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2910                sizeof(qcaps->mac_address));
2911         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2912         qcaps->max_rx_rings = fcfg->num_rx_rings;
2913         qcaps->max_tx_rings = fcfg->num_tx_rings;
2914         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2915         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2916         qcaps->max_vfs = 0;
2917         qcaps->first_vf_id = 0;
2918         qcaps->max_vnics = fcfg->num_vnics;
2919         qcaps->max_decap_records = 0;
2920         qcaps->max_encap_records = 0;
2921         qcaps->max_tx_wm_flows = 0;
2922         qcaps->max_tx_em_flows = 0;
2923         qcaps->max_rx_wm_flows = 0;
2924         qcaps->max_rx_em_flows = 0;
2925         qcaps->max_flow_id = 0;
2926         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2927         qcaps->max_sp_tx_rings = 0;
2928         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2929 }
2930
2931 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2932 {
2933         struct hwrm_func_cfg_input req = {0};
2934         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2935         uint32_t enables;
2936         int rc;
2937
2938         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2939                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2940                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2941                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2942                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2943                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2944                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2945                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2946                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2947
2948         if (BNXT_HAS_RING_GRPS(bp)) {
2949                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2950                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2951         } else if (BNXT_HAS_NQ(bp)) {
2952                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2953                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2954         }
2955
2956         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2957         req.mtu = rte_cpu_to_le_16(RTE_MIN(bp->eth_dev->data->mtu,
2958                                            BNXT_MAX_MTU)); //FW adds hdr sizes
2959         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
2960         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2961         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2962         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2963         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2964         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2965         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2966         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2967         req.fid = rte_cpu_to_le_16(0xffff);
2968         req.enables = rte_cpu_to_le_32(enables);
2969
2970         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2971
2972         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2973
2974         HWRM_CHECK_RESULT();
2975         HWRM_UNLOCK();
2976
2977         return rc;
2978 }
2979
2980 static void populate_vf_func_cfg_req(struct bnxt *bp,
2981                                      struct hwrm_func_cfg_input *req,
2982                                      int num_vfs)
2983 {
2984         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2985                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2986                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2987                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2988                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2989                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2990                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2991                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2992                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2993                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2994
2995         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2996                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2997                                     BNXT_NUM_VLANS);
2998         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
2999         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3000                                                 (num_vfs + 1));
3001         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3002         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3003                                                (num_vfs + 1));
3004         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3005         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3006         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3007         /* TODO: For now, do not support VMDq/RFS on VFs. */
3008         req->num_vnics = rte_cpu_to_le_16(1);
3009         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3010                                                  (num_vfs + 1));
3011 }
3012
3013 static void add_random_mac_if_needed(struct bnxt *bp,
3014                                      struct hwrm_func_cfg_input *cfg_req,
3015                                      int vf)
3016 {
3017         struct rte_ether_addr mac;
3018
3019         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3020                 return;
3021
3022         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3023                 cfg_req->enables |=
3024                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3025                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3026                 bp->pf.vf_info[vf].random_mac = true;
3027         } else {
3028                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3029                         RTE_ETHER_ADDR_LEN);
3030         }
3031 }
3032
3033 static void reserve_resources_from_vf(struct bnxt *bp,
3034                                       struct hwrm_func_cfg_input *cfg_req,
3035                                       int vf)
3036 {
3037         struct hwrm_func_qcaps_input req = {0};
3038         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3039         int rc;
3040
3041         /* Get the actual allocated values now */
3042         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3043         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3044         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3045
3046         if (rc) {
3047                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3048                 copy_func_cfg_to_qcaps(cfg_req, resp);
3049         } else if (resp->error_code) {
3050                 rc = rte_le_to_cpu_16(resp->error_code);
3051                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3052                 copy_func_cfg_to_qcaps(cfg_req, resp);
3053         }
3054
3055         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3056         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3057         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3058         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3059         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3060         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3061         /*
3062          * TODO: While not supporting VMDq with VFs, max_vnics is always
3063          * forced to 1 in this case
3064          */
3065         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3066         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3067
3068         HWRM_UNLOCK();
3069 }
3070
3071 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3072 {
3073         struct hwrm_func_qcfg_input req = {0};
3074         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3075         int rc;
3076
3077         /* Check for zero MAC address */
3078         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3079         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3080         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3081         HWRM_CHECK_RESULT();
3082         rc = rte_le_to_cpu_16(resp->vlan);
3083
3084         HWRM_UNLOCK();
3085
3086         return rc;
3087 }
3088
3089 static int update_pf_resource_max(struct bnxt *bp)
3090 {
3091         struct hwrm_func_qcfg_input req = {0};
3092         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3093         int rc;
3094
3095         /* And copy the allocated numbers into the pf struct */
3096         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3097         req.fid = rte_cpu_to_le_16(0xffff);
3098         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3099         HWRM_CHECK_RESULT();
3100
3101         /* Only TX ring value reflects actual allocation? TODO */
3102         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3103         bp->pf.evb_mode = resp->evb_mode;
3104
3105         HWRM_UNLOCK();
3106
3107         return rc;
3108 }
3109
3110 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3111 {
3112         int rc;
3113
3114         if (!BNXT_PF(bp)) {
3115                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3116                 return -EINVAL;
3117         }
3118
3119         rc = bnxt_hwrm_func_qcaps(bp);
3120         if (rc)
3121                 return rc;
3122
3123         bp->pf.func_cfg_flags &=
3124                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3125                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3126         bp->pf.func_cfg_flags |=
3127                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3128         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3129         rc = __bnxt_hwrm_func_qcaps(bp);
3130         return rc;
3131 }
3132
3133 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3134 {
3135         struct hwrm_func_cfg_input req = {0};
3136         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3137         int i;
3138         size_t sz;
3139         int rc = 0;
3140         size_t req_buf_sz;
3141
3142         if (!BNXT_PF(bp)) {
3143                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3144                 return -EINVAL;
3145         }
3146
3147         rc = bnxt_hwrm_func_qcaps(bp);
3148
3149         if (rc)
3150                 return rc;
3151
3152         bp->pf.active_vfs = num_vfs;
3153
3154         /*
3155          * First, configure the PF to only use one TX ring.  This ensures that
3156          * there are enough rings for all VFs.
3157          *
3158          * If we don't do this, when we call func_alloc() later, we will lock
3159          * extra rings to the PF that won't be available during func_cfg() of
3160          * the VFs.
3161          *
3162          * This has been fixed with firmware versions above 20.6.54
3163          */
3164         bp->pf.func_cfg_flags &=
3165                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3166                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3167         bp->pf.func_cfg_flags |=
3168                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3169         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3170         if (rc)
3171                 return rc;
3172
3173         /*
3174          * Now, create and register a buffer to hold forwarded VF requests
3175          */
3176         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3177         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3178                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3179         if (bp->pf.vf_req_buf == NULL) {
3180                 rc = -ENOMEM;
3181                 goto error_free;
3182         }
3183         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3184                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3185         for (i = 0; i < num_vfs; i++)
3186                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3187                                         (i * HWRM_MAX_REQ_LEN);
3188
3189         rc = bnxt_hwrm_func_buf_rgtr(bp);
3190         if (rc)
3191                 goto error_free;
3192
3193         populate_vf_func_cfg_req(bp, &req, num_vfs);
3194
3195         bp->pf.active_vfs = 0;
3196         for (i = 0; i < num_vfs; i++) {
3197                 add_random_mac_if_needed(bp, &req, i);
3198
3199                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3200                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3201                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3202                 rc = bnxt_hwrm_send_message(bp,
3203                                             &req,
3204                                             sizeof(req),
3205                                             BNXT_USE_CHIMP_MB);
3206
3207                 /* Clear enable flag for next pass */
3208                 req.enables &= ~rte_cpu_to_le_32(
3209                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3210
3211                 if (rc || resp->error_code) {
3212                         PMD_DRV_LOG(ERR,
3213                                 "Failed to initizlie VF %d\n", i);
3214                         PMD_DRV_LOG(ERR,
3215                                 "Not all VFs available. (%d, %d)\n",
3216                                 rc, resp->error_code);
3217                         HWRM_UNLOCK();
3218                         break;
3219                 }
3220
3221                 HWRM_UNLOCK();
3222
3223                 reserve_resources_from_vf(bp, &req, i);
3224                 bp->pf.active_vfs++;
3225                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3226         }
3227
3228         /*
3229          * Now configure the PF to use "the rest" of the resources
3230          * We're using STD_TX_RING_MODE here though which will limit the TX
3231          * rings.  This will allow QoS to function properly.  Not setting this
3232          * will cause PF rings to break bandwidth settings.
3233          */
3234         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3235         if (rc)
3236                 goto error_free;
3237
3238         rc = update_pf_resource_max(bp);
3239         if (rc)
3240                 goto error_free;
3241
3242         return rc;
3243
3244 error_free:
3245         bnxt_hwrm_func_buf_unrgtr(bp);
3246         return rc;
3247 }
3248
3249 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3250 {
3251         struct hwrm_func_cfg_input req = {0};
3252         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3253         int rc;
3254
3255         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3256
3257         req.fid = rte_cpu_to_le_16(0xffff);
3258         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3259         req.evb_mode = bp->pf.evb_mode;
3260
3261         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3262         HWRM_CHECK_RESULT();
3263         HWRM_UNLOCK();
3264
3265         return rc;
3266 }
3267
3268 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3269                                 uint8_t tunnel_type)
3270 {
3271         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3272         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3273         int rc = 0;
3274
3275         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3276         req.tunnel_type = tunnel_type;
3277         req.tunnel_dst_port_val = port;
3278         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3279         HWRM_CHECK_RESULT();
3280
3281         switch (tunnel_type) {
3282         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3283                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3284                 bp->vxlan_port = port;
3285                 break;
3286         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3287                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3288                 bp->geneve_port = port;
3289                 break;
3290         default:
3291                 break;
3292         }
3293
3294         HWRM_UNLOCK();
3295
3296         return rc;
3297 }
3298
3299 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3300                                 uint8_t tunnel_type)
3301 {
3302         struct hwrm_tunnel_dst_port_free_input req = {0};
3303         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3304         int rc = 0;
3305
3306         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3307
3308         req.tunnel_type = tunnel_type;
3309         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3310         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3311
3312         HWRM_CHECK_RESULT();
3313         HWRM_UNLOCK();
3314
3315         return rc;
3316 }
3317
3318 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3319                                         uint32_t flags)
3320 {
3321         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3322         struct hwrm_func_cfg_input req = {0};
3323         int rc;
3324
3325         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3326
3327         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3328         req.flags = rte_cpu_to_le_32(flags);
3329         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3330
3331         HWRM_CHECK_RESULT();
3332         HWRM_UNLOCK();
3333
3334         return rc;
3335 }
3336
3337 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3338 {
3339         uint32_t *flag = flagp;
3340
3341         vnic->flags = *flag;
3342 }
3343
3344 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3345 {
3346         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3347 }
3348
3349 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3350 {
3351         int rc = 0;
3352         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3353         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3354
3355         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3356
3357         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3358         req.req_buf_page_size = rte_cpu_to_le_16(
3359                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3360         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3361         req.req_buf_page_addr0 =
3362                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3363         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3364                 PMD_DRV_LOG(ERR,
3365                         "unable to map buffer address to physical memory\n");
3366                 return -ENOMEM;
3367         }
3368
3369         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3370
3371         HWRM_CHECK_RESULT();
3372         HWRM_UNLOCK();
3373
3374         return rc;
3375 }
3376
3377 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3378 {
3379         int rc = 0;
3380         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3381         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3382
3383         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3384                 return 0;
3385
3386         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3387
3388         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3389
3390         HWRM_CHECK_RESULT();
3391         HWRM_UNLOCK();
3392
3393         return rc;
3394 }
3395
3396 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3397 {
3398         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3399         struct hwrm_func_cfg_input req = {0};
3400         int rc;
3401
3402         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3403
3404         req.fid = rte_cpu_to_le_16(0xffff);
3405         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3406         req.enables = rte_cpu_to_le_32(
3407                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3408         req.async_event_cr = rte_cpu_to_le_16(
3409                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3410         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3411
3412         HWRM_CHECK_RESULT();
3413         HWRM_UNLOCK();
3414
3415         return rc;
3416 }
3417
3418 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3419 {
3420         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3421         struct hwrm_func_vf_cfg_input req = {0};
3422         int rc;
3423
3424         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3425
3426         req.enables = rte_cpu_to_le_32(
3427                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3428         req.async_event_cr = rte_cpu_to_le_16(
3429                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3430         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3431
3432         HWRM_CHECK_RESULT();
3433         HWRM_UNLOCK();
3434
3435         return rc;
3436 }
3437
3438 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3439 {
3440         struct hwrm_func_cfg_input req = {0};
3441         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3442         uint16_t dflt_vlan, fid;
3443         uint32_t func_cfg_flags;
3444         int rc = 0;
3445
3446         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3447
3448         if (is_vf) {
3449                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3450                 fid = bp->pf.vf_info[vf].fid;
3451                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3452         } else {
3453                 fid = rte_cpu_to_le_16(0xffff);
3454                 func_cfg_flags = bp->pf.func_cfg_flags;
3455                 dflt_vlan = bp->vlan;
3456         }
3457
3458         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3459         req.fid = rte_cpu_to_le_16(fid);
3460         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3461         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3462
3463         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3464
3465         HWRM_CHECK_RESULT();
3466         HWRM_UNLOCK();
3467
3468         return rc;
3469 }
3470
3471 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3472                         uint16_t max_bw, uint16_t enables)
3473 {
3474         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3475         struct hwrm_func_cfg_input req = {0};
3476         int rc;
3477
3478         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3479
3480         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3481         req.enables |= rte_cpu_to_le_32(enables);
3482         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3483         req.max_bw = rte_cpu_to_le_32(max_bw);
3484         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3485
3486         HWRM_CHECK_RESULT();
3487         HWRM_UNLOCK();
3488
3489         return rc;
3490 }
3491
3492 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3493 {
3494         struct hwrm_func_cfg_input req = {0};
3495         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3496         int rc = 0;
3497
3498         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3499
3500         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3501         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3502         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3503         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3504
3505         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3506
3507         HWRM_CHECK_RESULT();
3508         HWRM_UNLOCK();
3509
3510         return rc;
3511 }
3512
3513 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3514 {
3515         int rc;
3516
3517         if (BNXT_PF(bp))
3518                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3519         else
3520                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3521
3522         return rc;
3523 }
3524
3525 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3526                               void *encaped, size_t ec_size)
3527 {
3528         int rc = 0;
3529         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3530         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3531
3532         if (ec_size > sizeof(req.encap_request))
3533                 return -1;
3534
3535         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3536
3537         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3538         memcpy(req.encap_request, encaped, ec_size);
3539
3540         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3541
3542         HWRM_CHECK_RESULT();
3543         HWRM_UNLOCK();
3544
3545         return rc;
3546 }
3547
3548 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3549                                        struct rte_ether_addr *mac)
3550 {
3551         struct hwrm_func_qcfg_input req = {0};
3552         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3553         int rc;
3554
3555         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3556
3557         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3558         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3559
3560         HWRM_CHECK_RESULT();
3561
3562         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3563
3564         HWRM_UNLOCK();
3565
3566         return rc;
3567 }
3568
3569 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3570                             void *encaped, size_t ec_size)
3571 {
3572         int rc = 0;
3573         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3574         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3575
3576         if (ec_size > sizeof(req.encap_request))
3577                 return -1;
3578
3579         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3580
3581         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3582         memcpy(req.encap_request, encaped, ec_size);
3583
3584         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3585
3586         HWRM_CHECK_RESULT();
3587         HWRM_UNLOCK();
3588
3589         return rc;
3590 }
3591
3592 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3593                          struct rte_eth_stats *stats, uint8_t rx)
3594 {
3595         int rc = 0;
3596         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3597         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3598
3599         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3600
3601         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3602
3603         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3604
3605         HWRM_CHECK_RESULT();
3606
3607         if (rx) {
3608                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3609                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3610                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3611                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3612                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3613                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3614                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3615                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3616         } else {
3617                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3618                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3619                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3620                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3621                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3622                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3623         }
3624
3625         HWRM_UNLOCK();
3626
3627         return rc;
3628 }
3629
3630 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3631 {
3632         struct hwrm_port_qstats_input req = {0};
3633         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3634         struct bnxt_pf_info *pf = &bp->pf;
3635         int rc;
3636
3637         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3638
3639         req.port_id = rte_cpu_to_le_16(pf->port_id);
3640         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3641         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3642         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3643
3644         HWRM_CHECK_RESULT();
3645         HWRM_UNLOCK();
3646
3647         return rc;
3648 }
3649
3650 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3651 {
3652         struct hwrm_port_clr_stats_input req = {0};
3653         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3654         struct bnxt_pf_info *pf = &bp->pf;
3655         int rc;
3656
3657         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3658         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3659             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3660                 return 0;
3661
3662         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3663
3664         req.port_id = rte_cpu_to_le_16(pf->port_id);
3665         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3666
3667         HWRM_CHECK_RESULT();
3668         HWRM_UNLOCK();
3669
3670         return rc;
3671 }
3672
3673 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3674 {
3675         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3676         struct hwrm_port_led_qcaps_input req = {0};
3677         int rc;
3678
3679         if (BNXT_VF(bp))
3680                 return 0;
3681
3682         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3683         req.port_id = bp->pf.port_id;
3684         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3685
3686         HWRM_CHECK_RESULT();
3687
3688         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3689                 unsigned int i;
3690
3691                 bp->num_leds = resp->num_leds;
3692                 memcpy(bp->leds, &resp->led0_id,
3693                         sizeof(bp->leds[0]) * bp->num_leds);
3694                 for (i = 0; i < bp->num_leds; i++) {
3695                         struct bnxt_led_info *led = &bp->leds[i];
3696
3697                         uint16_t caps = led->led_state_caps;
3698
3699                         if (!led->led_group_id ||
3700                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3701                                 bp->num_leds = 0;
3702                                 break;
3703                         }
3704                 }
3705         }
3706
3707         HWRM_UNLOCK();
3708
3709         return rc;
3710 }
3711
3712 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3713 {
3714         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3715         struct hwrm_port_led_cfg_input req = {0};
3716         struct bnxt_led_cfg *led_cfg;
3717         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3718         uint16_t duration = 0;
3719         int rc, i;
3720
3721         if (!bp->num_leds || BNXT_VF(bp))
3722                 return -EOPNOTSUPP;
3723
3724         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3725
3726         if (led_on) {
3727                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3728                 duration = rte_cpu_to_le_16(500);
3729         }
3730         req.port_id = bp->pf.port_id;
3731         req.num_leds = bp->num_leds;
3732         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3733         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3734                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3735                 led_cfg->led_id = bp->leds[i].led_id;
3736                 led_cfg->led_state = led_state;
3737                 led_cfg->led_blink_on = duration;
3738                 led_cfg->led_blink_off = duration;
3739                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3740         }
3741
3742         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3743
3744         HWRM_CHECK_RESULT();
3745         HWRM_UNLOCK();
3746
3747         return rc;
3748 }
3749
3750 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3751                                uint32_t *length)
3752 {
3753         int rc;
3754         struct hwrm_nvm_get_dir_info_input req = {0};
3755         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3756
3757         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3758
3759         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3760
3761         HWRM_CHECK_RESULT();
3762
3763         *entries = rte_le_to_cpu_32(resp->entries);
3764         *length = rte_le_to_cpu_32(resp->entry_length);
3765
3766         HWRM_UNLOCK();
3767         return rc;
3768 }
3769
3770 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3771 {
3772         int rc;
3773         uint32_t dir_entries;
3774         uint32_t entry_length;
3775         uint8_t *buf;
3776         size_t buflen;
3777         rte_iova_t dma_handle;
3778         struct hwrm_nvm_get_dir_entries_input req = {0};
3779         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3780
3781         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3782         if (rc != 0)
3783                 return rc;
3784
3785         *data++ = dir_entries;
3786         *data++ = entry_length;
3787         len -= 2;
3788         memset(data, 0xff, len);
3789
3790         buflen = dir_entries * entry_length;
3791         buf = rte_malloc("nvm_dir", buflen, 0);
3792         rte_mem_lock_page(buf);
3793         if (buf == NULL)
3794                 return -ENOMEM;
3795         dma_handle = rte_mem_virt2iova(buf);
3796         if (dma_handle == RTE_BAD_IOVA) {
3797                 PMD_DRV_LOG(ERR,
3798                         "unable to map response address to physical memory\n");
3799                 return -ENOMEM;
3800         }
3801         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3802         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3803         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3804
3805         if (rc == 0)
3806                 memcpy(data, buf, len > buflen ? buflen : len);
3807
3808         rte_free(buf);
3809         HWRM_CHECK_RESULT();
3810         HWRM_UNLOCK();
3811
3812         return rc;
3813 }
3814
3815 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3816                              uint32_t offset, uint32_t length,
3817                              uint8_t *data)
3818 {
3819         int rc;
3820         uint8_t *buf;
3821         rte_iova_t dma_handle;
3822         struct hwrm_nvm_read_input req = {0};
3823         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3824
3825         buf = rte_malloc("nvm_item", length, 0);
3826         rte_mem_lock_page(buf);
3827         if (!buf)
3828                 return -ENOMEM;
3829
3830         dma_handle = rte_mem_virt2iova(buf);
3831         if (dma_handle == RTE_BAD_IOVA) {
3832                 PMD_DRV_LOG(ERR,
3833                         "unable to map response address to physical memory\n");
3834                 return -ENOMEM;
3835         }
3836         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3837         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3838         req.dir_idx = rte_cpu_to_le_16(index);
3839         req.offset = rte_cpu_to_le_32(offset);
3840         req.len = rte_cpu_to_le_32(length);
3841         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3842         if (rc == 0)
3843                 memcpy(data, buf, length);
3844
3845         rte_free(buf);
3846         HWRM_CHECK_RESULT();
3847         HWRM_UNLOCK();
3848
3849         return rc;
3850 }
3851
3852 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3853 {
3854         int rc;
3855         struct hwrm_nvm_erase_dir_entry_input req = {0};
3856         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3857
3858         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3859         req.dir_idx = rte_cpu_to_le_16(index);
3860         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3861         HWRM_CHECK_RESULT();
3862         HWRM_UNLOCK();
3863
3864         return rc;
3865 }
3866
3867
3868 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3869                           uint16_t dir_ordinal, uint16_t dir_ext,
3870                           uint16_t dir_attr, const uint8_t *data,
3871                           size_t data_len)
3872 {
3873         int rc;
3874         struct hwrm_nvm_write_input req = {0};
3875         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3876         rte_iova_t dma_handle;
3877         uint8_t *buf;
3878
3879         buf = rte_malloc("nvm_write", data_len, 0);
3880         rte_mem_lock_page(buf);
3881         if (!buf)
3882                 return -ENOMEM;
3883
3884         dma_handle = rte_mem_virt2iova(buf);
3885         if (dma_handle == RTE_BAD_IOVA) {
3886                 PMD_DRV_LOG(ERR,
3887                         "unable to map response address to physical memory\n");
3888                 return -ENOMEM;
3889         }
3890         memcpy(buf, data, data_len);
3891
3892         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3893
3894         req.dir_type = rte_cpu_to_le_16(dir_type);
3895         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3896         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3897         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3898         req.dir_data_length = rte_cpu_to_le_32(data_len);
3899         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3900
3901         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3902
3903         rte_free(buf);
3904         HWRM_CHECK_RESULT();
3905         HWRM_UNLOCK();
3906
3907         return rc;
3908 }
3909
3910 static void
3911 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3912 {
3913         uint32_t *count = cbdata;
3914
3915         *count = *count + 1;
3916 }
3917
3918 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3919                                      struct bnxt_vnic_info *vnic __rte_unused)
3920 {
3921         return 0;
3922 }
3923
3924 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3925 {
3926         uint32_t count = 0;
3927
3928         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3929             &count, bnxt_vnic_count_hwrm_stub);
3930
3931         return count;
3932 }
3933
3934 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3935                                         uint16_t *vnic_ids)
3936 {
3937         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3938         struct hwrm_func_vf_vnic_ids_query_output *resp =
3939                                                 bp->hwrm_cmd_resp_addr;
3940         int rc;
3941
3942         /* First query all VNIC ids */
3943         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3944
3945         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3946         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3947         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3948
3949         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3950                 HWRM_UNLOCK();
3951                 PMD_DRV_LOG(ERR,
3952                 "unable to map VNIC ID table address to physical memory\n");
3953                 return -ENOMEM;
3954         }
3955         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3956         HWRM_CHECK_RESULT();
3957         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3958
3959         HWRM_UNLOCK();
3960
3961         return rc;
3962 }
3963
3964 /*
3965  * This function queries the VNIC IDs  for a specified VF. It then calls
3966  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3967  * Then it calls the hwrm_cb function to program this new vnic configuration.
3968  */
3969 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3970         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3971         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3972 {
3973         struct bnxt_vnic_info vnic;
3974         int rc = 0;
3975         int i, num_vnic_ids;
3976         uint16_t *vnic_ids;
3977         size_t vnic_id_sz;
3978         size_t sz;
3979
3980         /* First query all VNIC ids */
3981         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3982         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3983                         RTE_CACHE_LINE_SIZE);
3984         if (vnic_ids == NULL)
3985                 return -ENOMEM;
3986
3987         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3988                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3989
3990         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3991
3992         if (num_vnic_ids < 0)
3993                 return num_vnic_ids;
3994
3995         /* Retrieve VNIC, update bd_stall then update */
3996
3997         for (i = 0; i < num_vnic_ids; i++) {
3998                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3999                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4000                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4001                 if (rc)
4002                         break;
4003                 if (vnic.mru <= 4)      /* Indicates unallocated */
4004                         continue;
4005
4006                 vnic_cb(&vnic, cbdata);
4007
4008                 rc = hwrm_cb(bp, &vnic);
4009                 if (rc)
4010                         break;
4011         }
4012
4013         rte_free(vnic_ids);
4014
4015         return rc;
4016 }
4017
4018 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4019                                               bool on)
4020 {
4021         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4022         struct hwrm_func_cfg_input req = {0};
4023         int rc;
4024
4025         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4026
4027         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4028         req.enables |= rte_cpu_to_le_32(
4029                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4030         req.vlan_antispoof_mode = on ?
4031                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4032                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4033         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4034
4035         HWRM_CHECK_RESULT();
4036         HWRM_UNLOCK();
4037
4038         return rc;
4039 }
4040
4041 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4042 {
4043         struct bnxt_vnic_info vnic;
4044         uint16_t *vnic_ids;
4045         size_t vnic_id_sz;
4046         int num_vnic_ids, i;
4047         size_t sz;
4048         int rc;
4049
4050         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4051         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4052                         RTE_CACHE_LINE_SIZE);
4053         if (vnic_ids == NULL)
4054                 return -ENOMEM;
4055
4056         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4057                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4058
4059         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4060         if (rc <= 0)
4061                 goto exit;
4062         num_vnic_ids = rc;
4063
4064         /*
4065          * Loop through to find the default VNIC ID.
4066          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4067          * by sending the hwrm_func_qcfg command to the firmware.
4068          */
4069         for (i = 0; i < num_vnic_ids; i++) {
4070                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4071                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4072                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4073                                         bp->pf.first_vf_id + vf);
4074                 if (rc)
4075                         goto exit;
4076                 if (vnic.func_default) {
4077                         rte_free(vnic_ids);
4078                         return vnic.fw_vnic_id;
4079                 }
4080         }
4081         /* Could not find a default VNIC. */
4082         PMD_DRV_LOG(ERR, "No default VNIC\n");
4083 exit:
4084         rte_free(vnic_ids);
4085         return rc;
4086 }
4087
4088 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4089                          uint16_t dst_id,
4090                          struct bnxt_filter_info *filter)
4091 {
4092         int rc = 0;
4093         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4094         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4095         uint32_t enables = 0;
4096
4097         if (filter->fw_em_filter_id != UINT64_MAX)
4098                 bnxt_hwrm_clear_em_filter(bp, filter);
4099
4100         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4101
4102         req.flags = rte_cpu_to_le_32(filter->flags);
4103
4104         enables = filter->enables |
4105               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4106         req.dst_id = rte_cpu_to_le_16(dst_id);
4107
4108         if (filter->ip_addr_type) {
4109                 req.ip_addr_type = filter->ip_addr_type;
4110                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4111         }
4112         if (enables &
4113             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4114                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4115         if (enables &
4116             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4117                 memcpy(req.src_macaddr, filter->src_macaddr,
4118                        RTE_ETHER_ADDR_LEN);
4119         if (enables &
4120             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4121                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4122                        RTE_ETHER_ADDR_LEN);
4123         if (enables &
4124             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4125                 req.ovlan_vid = filter->l2_ovlan;
4126         if (enables &
4127             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4128                 req.ivlan_vid = filter->l2_ivlan;
4129         if (enables &
4130             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4131                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4132         if (enables &
4133             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4134                 req.ip_protocol = filter->ip_protocol;
4135         if (enables &
4136             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4137                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4138         if (enables &
4139             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4140                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4141         if (enables &
4142             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4143                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4144         if (enables &
4145             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4146                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4147         if (enables &
4148             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4149                 req.mirror_vnic_id = filter->mirror_vnic_id;
4150
4151         req.enables = rte_cpu_to_le_32(enables);
4152
4153         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4154
4155         HWRM_CHECK_RESULT();
4156
4157         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4158         HWRM_UNLOCK();
4159
4160         return rc;
4161 }
4162
4163 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4164 {
4165         int rc = 0;
4166         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4167         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4168
4169         if (filter->fw_em_filter_id == UINT64_MAX)
4170                 return 0;
4171
4172         PMD_DRV_LOG(ERR, "Clear EM filter\n");
4173         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4174
4175         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4176
4177         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4178
4179         HWRM_CHECK_RESULT();
4180         HWRM_UNLOCK();
4181
4182         filter->fw_em_filter_id = UINT64_MAX;
4183         filter->fw_l2_filter_id = UINT64_MAX;
4184
4185         return 0;
4186 }
4187
4188 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4189                          uint16_t dst_id,
4190                          struct bnxt_filter_info *filter)
4191 {
4192         int rc = 0;
4193         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4194         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4195                                                 bp->hwrm_cmd_resp_addr;
4196         uint32_t enables = 0;
4197
4198         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4199                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4200
4201         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4202
4203         req.flags = rte_cpu_to_le_32(filter->flags);
4204
4205         enables = filter->enables |
4206               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4207         req.dst_id = rte_cpu_to_le_16(dst_id);
4208
4209         if (filter->ip_addr_type) {
4210                 req.ip_addr_type = filter->ip_addr_type;
4211                 enables |=
4212                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4213         }
4214         if (enables &
4215             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4216                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4217         if (enables &
4218             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4219                 memcpy(req.src_macaddr, filter->src_macaddr,
4220                        RTE_ETHER_ADDR_LEN);
4221         if (enables &
4222             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4223                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4224         if (enables &
4225             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4226                 req.ip_protocol = filter->ip_protocol;
4227         if (enables &
4228             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4229                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4230         if (enables &
4231             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4232                 req.src_ipaddr_mask[0] =
4233                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4234         if (enables &
4235             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4236                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4237         if (enables &
4238             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4239                 req.dst_ipaddr_mask[0] =
4240                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4241         if (enables &
4242             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4243                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4244         if (enables &
4245             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4246                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4247         if (enables &
4248             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4249                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4250         if (enables &
4251             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4252                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4253         if (enables &
4254             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4255                 req.mirror_vnic_id = filter->mirror_vnic_id;
4256
4257         req.enables = rte_cpu_to_le_32(enables);
4258
4259         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4260
4261         HWRM_CHECK_RESULT();
4262
4263         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4264         HWRM_UNLOCK();
4265
4266         return rc;
4267 }
4268
4269 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4270                                 struct bnxt_filter_info *filter)
4271 {
4272         int rc = 0;
4273         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4274         struct hwrm_cfa_ntuple_filter_free_output *resp =
4275                                                 bp->hwrm_cmd_resp_addr;
4276
4277         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4278                 return 0;
4279
4280         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4281
4282         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4283
4284         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4285
4286         HWRM_CHECK_RESULT();
4287         HWRM_UNLOCK();
4288
4289         filter->fw_ntuple_filter_id = UINT64_MAX;
4290
4291         return 0;
4292 }
4293
4294 static int
4295 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4296 {
4297         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4298         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4299         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4300         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4301         uint16_t *ring_tbl = vnic->rss_table;
4302         int nr_ctxs = vnic->num_lb_ctxts;
4303         int max_rings = bp->rx_nr_rings;
4304         int i, j, k, cnt;
4305         int rc = 0;
4306
4307         for (i = 0, k = 0; i < nr_ctxs; i++) {
4308                 struct bnxt_rx_ring_info *rxr;
4309                 struct bnxt_cp_ring_info *cpr;
4310
4311                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4312
4313                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4314                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4315                 req.hash_mode_flags = vnic->hash_mode;
4316
4317                 req.ring_grp_tbl_addr =
4318                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4319                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4320                                      2 * sizeof(*ring_tbl));
4321                 req.hash_key_tbl_addr =
4322                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4323
4324                 req.ring_table_pair_index = i;
4325                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4326
4327                 for (j = 0; j < 64; j++) {
4328                         uint16_t ring_id;
4329
4330                         /* Find next active ring. */
4331                         for (cnt = 0; cnt < max_rings; cnt++) {
4332                                 if (rx_queue_state[k] !=
4333                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4334                                         break;
4335                                 if (++k == max_rings)
4336                                         k = 0;
4337                         }
4338
4339                         /* Return if no rings are active. */
4340                         if (cnt == max_rings)
4341                                 return 0;
4342
4343                         /* Add rx/cp ring pair to RSS table. */
4344                         rxr = rxqs[k]->rx_ring;
4345                         cpr = rxqs[k]->cp_ring;
4346
4347                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4348                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4349                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4350                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4351
4352                         if (++k == max_rings)
4353                                 k = 0;
4354                 }
4355                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4356                                             BNXT_USE_CHIMP_MB);
4357
4358                 HWRM_CHECK_RESULT();
4359                 HWRM_UNLOCK();
4360         }
4361
4362         return rc;
4363 }
4364
4365 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4366 {
4367         unsigned int rss_idx, fw_idx, i;
4368
4369         if (!(vnic->rss_table && vnic->hash_type))
4370                 return 0;
4371
4372         if (BNXT_CHIP_THOR(bp))
4373                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4374
4375         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4376                 return 0;
4377
4378         if (vnic->rss_table && vnic->hash_type) {
4379                 /*
4380                  * Fill the RSS hash & redirection table with
4381                  * ring group ids for all VNICs
4382                  */
4383                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4384                         rss_idx++, fw_idx++) {
4385                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4386                                 fw_idx %= bp->rx_cp_nr_rings;
4387                                 if (vnic->fw_grp_ids[fw_idx] !=
4388                                     INVALID_HW_RING_ID)
4389                                         break;
4390                                 fw_idx++;
4391                         }
4392                         if (i == bp->rx_cp_nr_rings)
4393                                 return 0;
4394                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4395                 }
4396                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4397         }
4398
4399         return 0;
4400 }
4401
4402 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4403         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4404 {
4405         uint16_t flags;
4406
4407         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4408
4409         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4410         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4411
4412         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4413         req->num_cmpl_dma_aggr_during_int =
4414                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4415
4416         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4417
4418         /* min timer set to 1/2 of interrupt timer */
4419         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4420
4421         /* buf timer set to 1/4 of interrupt timer */
4422         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4423
4424         req->cmpl_aggr_dma_tmr_during_int =
4425                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4426
4427         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4428                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4429         req->flags = rte_cpu_to_le_16(flags);
4430 }
4431
4432 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4433                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4434 {
4435         struct hwrm_ring_aggint_qcaps_input req = {0};
4436         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4437         uint32_t enables;
4438         uint16_t flags;
4439         int rc;
4440
4441         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4442         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4443         HWRM_CHECK_RESULT();
4444
4445         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4446         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4447
4448         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4449                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4450         agg_req->flags = rte_cpu_to_le_16(flags);
4451         enables =
4452          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4453          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4454         agg_req->enables = rte_cpu_to_le_32(enables);
4455
4456         HWRM_UNLOCK();
4457         return rc;
4458 }
4459
4460 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4461                         struct bnxt_coal *coal, uint16_t ring_id)
4462 {
4463         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4464         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4465                                                 bp->hwrm_cmd_resp_addr;
4466         int rc;
4467
4468         /* Set ring coalesce parameters only for 100G NICs */
4469         if (BNXT_CHIP_THOR(bp)) {
4470                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4471                         return -1;
4472         } else if (bnxt_stratus_device(bp)) {
4473                 bnxt_hwrm_set_coal_params(coal, &req);
4474         } else {
4475                 return 0;
4476         }
4477
4478         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4479         req.ring_id = rte_cpu_to_le_16(ring_id);
4480         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4481         HWRM_CHECK_RESULT();
4482         HWRM_UNLOCK();
4483         return 0;
4484 }
4485
4486 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4487 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4488 {
4489         struct hwrm_func_backing_store_qcaps_input req = {0};
4490         struct hwrm_func_backing_store_qcaps_output *resp =
4491                 bp->hwrm_cmd_resp_addr;
4492         struct bnxt_ctx_pg_info *ctx_pg;
4493         struct bnxt_ctx_mem_info *ctx;
4494         int total_alloc_len;
4495         int rc, i;
4496
4497         if (!BNXT_CHIP_THOR(bp) ||
4498             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4499             BNXT_VF(bp) ||
4500             bp->ctx)
4501                 return 0;
4502
4503         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4504         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4505         HWRM_CHECK_RESULT_SILENT();
4506
4507         total_alloc_len = sizeof(*ctx);
4508         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4509                           RTE_CACHE_LINE_SIZE);
4510         if (!ctx) {
4511                 rc = -ENOMEM;
4512                 goto ctx_err;
4513         }
4514
4515         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4516                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4517                             RTE_CACHE_LINE_SIZE);
4518         if (!ctx_pg) {
4519                 rc = -ENOMEM;
4520                 goto ctx_err;
4521         }
4522         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4523                 ctx->tqm_mem[i] = ctx_pg;
4524
4525         bp->ctx = ctx;
4526         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4527         ctx->qp_min_qp1_entries =
4528                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4529         ctx->qp_max_l2_entries =
4530                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4531         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4532         ctx->srq_max_l2_entries =
4533                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4534         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4535         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4536         ctx->cq_max_l2_entries =
4537                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4538         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4539         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4540         ctx->vnic_max_vnic_entries =
4541                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4542         ctx->vnic_max_ring_table_entries =
4543                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4544         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4545         ctx->stat_max_entries =
4546                 rte_le_to_cpu_32(resp->stat_max_entries);
4547         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4548         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4549         ctx->tqm_min_entries_per_ring =
4550                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4551         ctx->tqm_max_entries_per_ring =
4552                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4553         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4554         if (!ctx->tqm_entries_multiple)
4555                 ctx->tqm_entries_multiple = 1;
4556         ctx->mrav_max_entries =
4557                 rte_le_to_cpu_32(resp->mrav_max_entries);
4558         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4559         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4560         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4561 ctx_err:
4562         HWRM_UNLOCK();
4563         return rc;
4564 }
4565
4566 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4567 {
4568         struct hwrm_func_backing_store_cfg_input req = {0};
4569         struct hwrm_func_backing_store_cfg_output *resp =
4570                 bp->hwrm_cmd_resp_addr;
4571         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4572         struct bnxt_ctx_pg_info *ctx_pg;
4573         uint32_t *num_entries;
4574         uint64_t *pg_dir;
4575         uint8_t *pg_attr;
4576         uint32_t ena;
4577         int i, rc;
4578
4579         if (!ctx)
4580                 return 0;
4581
4582         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4583         req.enables = rte_cpu_to_le_32(enables);
4584
4585         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4586                 ctx_pg = &ctx->qp_mem;
4587                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4588                 req.qp_num_qp1_entries =
4589                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4590                 req.qp_num_l2_entries =
4591                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4592                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4593                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4594                                       &req.qpc_pg_size_qpc_lvl,
4595                                       &req.qpc_page_dir);
4596         }
4597
4598         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4599                 ctx_pg = &ctx->srq_mem;
4600                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4601                 req.srq_num_l2_entries =
4602                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4603                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4604                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4605                                       &req.srq_pg_size_srq_lvl,
4606                                       &req.srq_page_dir);
4607         }
4608
4609         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4610                 ctx_pg = &ctx->cq_mem;
4611                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4612                 req.cq_num_l2_entries =
4613                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4614                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4615                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4616                                       &req.cq_pg_size_cq_lvl,
4617                                       &req.cq_page_dir);
4618         }
4619
4620         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4621                 ctx_pg = &ctx->vnic_mem;
4622                 req.vnic_num_vnic_entries =
4623                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4624                 req.vnic_num_ring_table_entries =
4625                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4626                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4627                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4628                                       &req.vnic_pg_size_vnic_lvl,
4629                                       &req.vnic_page_dir);
4630         }
4631
4632         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4633                 ctx_pg = &ctx->stat_mem;
4634                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4635                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4636                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4637                                       &req.stat_pg_size_stat_lvl,
4638                                       &req.stat_page_dir);
4639         }
4640
4641         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4642         num_entries = &req.tqm_sp_num_entries;
4643         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4644         pg_dir = &req.tqm_sp_page_dir;
4645         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4646         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4647                 if (!(enables & ena))
4648                         continue;
4649
4650                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4651
4652                 ctx_pg = ctx->tqm_mem[i];
4653                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4654                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4655         }
4656
4657         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4658         HWRM_CHECK_RESULT();
4659         HWRM_UNLOCK();
4660
4661         return rc;
4662 }
4663
4664 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4665 {
4666         struct hwrm_port_qstats_ext_input req = {0};
4667         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4668         struct bnxt_pf_info *pf = &bp->pf;
4669         int rc;
4670
4671         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4672               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4673                 return 0;
4674
4675         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4676
4677         req.port_id = rte_cpu_to_le_16(pf->port_id);
4678         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4679                 req.tx_stat_host_addr =
4680                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4681                 req.tx_stat_size =
4682                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4683         }
4684         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4685                 req.rx_stat_host_addr =
4686                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4687                 req.rx_stat_size =
4688                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4689         }
4690         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4691
4692         if (rc) {
4693                 bp->fw_rx_port_stats_ext_size = 0;
4694                 bp->fw_tx_port_stats_ext_size = 0;
4695         } else {
4696                 bp->fw_rx_port_stats_ext_size =
4697                         rte_le_to_cpu_16(resp->rx_stat_size);
4698                 bp->fw_tx_port_stats_ext_size =
4699                         rte_le_to_cpu_16(resp->tx_stat_size);
4700         }
4701
4702         HWRM_CHECK_RESULT();
4703         HWRM_UNLOCK();
4704
4705         return rc;
4706 }
4707
4708 int
4709 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4710 {
4711         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4712         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4713                 bp->hwrm_cmd_resp_addr;
4714         int rc = 0;
4715
4716         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4717         req.tunnel_type = type;
4718         req.dest_fid = bp->fw_fid;
4719         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4720         HWRM_CHECK_RESULT();
4721
4722         HWRM_UNLOCK();
4723
4724         return rc;
4725 }
4726
4727 int
4728 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4729 {
4730         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4731         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4732                 bp->hwrm_cmd_resp_addr;
4733         int rc = 0;
4734
4735         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4736         req.tunnel_type = type;
4737         req.dest_fid = bp->fw_fid;
4738         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4739         HWRM_CHECK_RESULT();
4740
4741         HWRM_UNLOCK();
4742
4743         return rc;
4744 }
4745
4746 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4747 {
4748         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4749         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4750                 bp->hwrm_cmd_resp_addr;
4751         int rc = 0;
4752
4753         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4754         req.src_fid = bp->fw_fid;
4755         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4756         HWRM_CHECK_RESULT();
4757
4758         if (type)
4759                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4760
4761         HWRM_UNLOCK();
4762
4763         return rc;
4764 }
4765
4766 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4767                                    uint16_t *dst_fid)
4768 {
4769         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4770         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4771                 bp->hwrm_cmd_resp_addr;
4772         int rc = 0;
4773
4774         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4775         req.src_fid = bp->fw_fid;
4776         req.tunnel_type = tun_type;
4777         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4778         HWRM_CHECK_RESULT();
4779
4780         if (dst_fid)
4781                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4782
4783         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4784
4785         HWRM_UNLOCK();
4786
4787         return rc;
4788 }
4789
4790 int bnxt_hwrm_set_mac(struct bnxt *bp)
4791 {
4792         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4793         struct hwrm_func_vf_cfg_input req = {0};
4794         int rc = 0;
4795
4796         if (!BNXT_VF(bp))
4797                 return 0;
4798
4799         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4800
4801         req.enables =
4802                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4803         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4804
4805         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4806
4807         HWRM_CHECK_RESULT();
4808
4809         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4810         HWRM_UNLOCK();
4811
4812         return rc;
4813 }
4814
4815 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4816 {
4817         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4818         struct hwrm_func_drv_if_change_input req = {0};
4819         uint32_t flags;
4820         int rc;
4821
4822         if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4823                 return 0;
4824
4825         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4826          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4827          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4828          */
4829         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4830                 return 0;
4831
4832         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4833
4834         if (up)
4835                 req.flags =
4836                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4837
4838         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4839
4840         HWRM_CHECK_RESULT();
4841         flags = rte_le_to_cpu_32(resp->flags);
4842         HWRM_UNLOCK();
4843
4844         if (!up)
4845                 return 0;
4846
4847         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4848                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4849                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4850         }
4851
4852         return 0;
4853 }
4854
4855 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4856 {
4857         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4858         struct bnxt_error_recovery_info *info = bp->recovery_info;
4859         struct hwrm_error_recovery_qcfg_input req = {0};
4860         uint32_t flags = 0;
4861         unsigned int i;
4862         int rc;
4863
4864         /* Older FW does not have error recovery support */
4865         if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4866                 return 0;
4867
4868         if (!info) {
4869                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4870                                    sizeof(*info), 0);
4871                 bp->recovery_info = info;
4872                 if (info == NULL)
4873                         return -ENOMEM;
4874         } else {
4875                 memset(info, 0, sizeof(*info));
4876         }
4877
4878         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4879
4880         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4881
4882         HWRM_CHECK_RESULT();
4883
4884         flags = rte_le_to_cpu_32(resp->flags);
4885         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4886                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4887         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4888                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4889
4890         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4891             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4892                 rc = -EINVAL;
4893                 goto err;
4894         }
4895
4896         /* FW returned values are in units of 100msec */
4897         info->driver_polling_freq =
4898                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4899         info->master_func_wait_period =
4900                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4901         info->normal_func_wait_period =
4902                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4903         info->master_func_wait_period_after_reset =
4904                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4905         info->max_bailout_time_after_reset =
4906                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4907         info->status_regs[BNXT_FW_STATUS_REG] =
4908                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4909         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4910                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4911         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4912                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4913         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4914                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4915         info->reg_array_cnt =
4916                 rte_le_to_cpu_32(resp->reg_array_cnt);
4917
4918         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4919                 rc = -EINVAL;
4920                 goto err;
4921         }
4922
4923         for (i = 0; i < info->reg_array_cnt; i++) {
4924                 info->reset_reg[i] =
4925                         rte_le_to_cpu_32(resp->reset_reg[i]);
4926                 info->reset_reg_val[i] =
4927                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4928                 info->delay_after_reset[i] =
4929                         resp->delay_after_reset[i];
4930         }
4931 err:
4932         HWRM_UNLOCK();
4933
4934         /* Map the FW status registers */
4935         if (!rc)
4936                 rc = bnxt_map_fw_health_status_regs(bp);
4937
4938         if (rc) {
4939                 rte_free(bp->recovery_info);
4940                 bp->recovery_info = NULL;
4941         }
4942         return rc;
4943 }
4944
4945 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4946 {
4947         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4948         struct hwrm_fw_reset_input req = {0};
4949         int rc;
4950
4951         if (!BNXT_PF(bp))
4952                 return -EOPNOTSUPP;
4953
4954         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4955
4956         req.embedded_proc_type =
4957                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4958         req.selfrst_status =
4959                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4960         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4961
4962         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4963                                     BNXT_USE_KONG(bp));
4964
4965         HWRM_CHECK_RESULT();
4966         HWRM_UNLOCK();
4967
4968         return rc;
4969 }
4970
4971 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4972 {
4973         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4974         struct hwrm_port_ts_query_input req = {0};
4975         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4976         uint32_t flags = 0;
4977         int rc;
4978
4979         if (!ptp)
4980                 return 0;
4981
4982         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4983
4984         switch (path) {
4985         case BNXT_PTP_FLAGS_PATH_TX:
4986                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4987                 break;
4988         case BNXT_PTP_FLAGS_PATH_RX:
4989                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4990                 break;
4991         case BNXT_PTP_FLAGS_CURRENT_TIME:
4992                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
4993                 break;
4994         }
4995
4996         req.flags = rte_cpu_to_le_32(flags);
4997         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
4998
4999         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5000
5001         HWRM_CHECK_RESULT();
5002
5003         if (timestamp) {
5004                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5005                 *timestamp |=
5006                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5007         }
5008         HWRM_UNLOCK();
5009
5010         return rc;
5011 }
5012
5013 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5014 {
5015         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5016                                         bp->hwrm_cmd_resp_addr;
5017         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5018         uint32_t flags = 0;
5019         int rc = 0;
5020
5021         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5022                 return rc;
5023
5024         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5025                 PMD_DRV_LOG(DEBUG,
5026                             "Not a PF or trusted VF. Command not supported\n");
5027                 return 0;
5028         }
5029
5030         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5031         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5032
5033         HWRM_CHECK_RESULT();
5034         flags = rte_le_to_cpu_32(resp->flags);
5035         HWRM_UNLOCK();
5036
5037         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5038                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5039                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5040         }
5041
5042         return rc;
5043 }