4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <rte_byteorder.h>
37 #include <rte_common.h>
38 #include <rte_cycles.h>
39 #include <rte_malloc.h>
40 #include <rte_memzone.h>
41 #include <rte_version.h>
45 #include "bnxt_filter.h"
46 #include "bnxt_hwrm.h"
49 #include "bnxt_ring.h"
52 #include "bnxt_vnic.h"
53 #include "hsi_struct_def_dpdk.h"
57 #define HWRM_CMD_TIMEOUT 10000
59 struct bnxt_plcmodes_cfg {
61 uint16_t jumbo_thresh;
63 uint16_t hds_threshold;
66 static int page_getenum(size_t size)
82 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
83 return sizeof(void *) * 8 - 1;
86 static int page_roundup(size_t size)
88 return 1 << page_getenum(size);
92 * HWRM Functions (sent to HWRM)
93 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
94 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
95 * command was failed by the ChiMP.
98 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
102 struct input *req = msg;
103 struct output *resp = bp->hwrm_cmd_resp_addr;
104 uint32_t *data = msg;
107 uint16_t max_req_len = bp->max_req_len;
108 struct hwrm_short_input short_input = { 0 };
110 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
111 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
113 memset(short_cmd_req, 0, bp->max_req_len);
114 memcpy(short_cmd_req, req, msg_len);
116 short_input.req_type = rte_cpu_to_le_16(req->req_type);
117 short_input.signature = rte_cpu_to_le_16(
118 HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
119 short_input.size = rte_cpu_to_le_16(msg_len);
120 short_input.req_addr =
121 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
123 data = (uint32_t *)&short_input;
124 msg_len = sizeof(short_input);
126 /* Sync memory write before updating doorbell */
129 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
132 /* Write request msg to hwrm channel */
133 for (i = 0; i < msg_len; i += 4) {
134 bar = (uint8_t *)bp->bar0 + i;
135 rte_write32(*data, bar);
139 /* Zero the rest of the request space */
140 for (; i < max_req_len; i += 4) {
141 bar = (uint8_t *)bp->bar0 + i;
145 /* Ring channel doorbell */
146 bar = (uint8_t *)bp->bar0 + 0x100;
149 /* Poll for the valid bit */
150 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
151 /* Sanity check on the resp->resp_len */
153 if (resp->resp_len && resp->resp_len <=
155 /* Last byte of resp contains the valid key */
156 valid = (uint8_t *)resp + resp->resp_len - 1;
157 if (*valid == HWRM_RESP_VALID_KEY)
163 if (i >= HWRM_CMD_TIMEOUT) {
164 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
175 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
176 * spinlock, and does initial processing.
178 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
179 * releases the spinlock only if it returns. If the regular int return codes
180 * are not used by the function, HWRM_CHECK_RESULT() should not be used
181 * directly, rather it should be copied and modified to suit the function.
183 * HWRM_UNLOCK() must be called after all response processing is completed.
185 #define HWRM_PREP(req, type) do { \
186 rte_spinlock_lock(&bp->hwrm_lock); \
187 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
188 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
189 req.cmpl_ring = rte_cpu_to_le_16(-1); \
190 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
191 req.target_id = rte_cpu_to_le_16(0xffff); \
192 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
195 #define HWRM_CHECK_RESULT() do {\
197 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
198 rte_spinlock_unlock(&bp->hwrm_lock); \
201 if (resp->error_code) { \
202 rc = rte_le_to_cpu_16(resp->error_code); \
203 if (resp->resp_len >= 16) { \
204 struct hwrm_err_output *tmp_hwrm_err_op = \
207 "error %d:%d:%08x:%04x\n", \
208 rc, tmp_hwrm_err_op->cmd_err, \
210 tmp_hwrm_err_op->opaque_0), \
212 tmp_hwrm_err_op->opaque_1)); \
214 PMD_DRV_LOG(ERR, "error %d\n", rc); \
216 rte_spinlock_unlock(&bp->hwrm_lock); \
221 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
223 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
226 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
227 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
229 HWRM_PREP(req, CFA_L2_SET_RX_MASK);
230 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
233 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
241 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
242 struct bnxt_vnic_info *vnic,
244 struct bnxt_vlan_table_entry *vlan_table)
247 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
248 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
251 HWRM_PREP(req, CFA_L2_SET_RX_MASK);
252 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
254 /* FIXME add multicast flag, when multicast adding options is supported
257 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
258 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
259 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
260 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
261 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
262 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
263 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
264 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
265 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
266 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
267 if (vnic->mc_addr_cnt) {
268 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
269 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
270 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
273 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
274 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
275 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
276 rte_mem_virt2iova(vlan_table));
277 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
279 req.mask = rte_cpu_to_le_32(mask);
281 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
289 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
291 struct bnxt_vlan_antispoof_table_entry *vlan_table)
294 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
295 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
296 bp->hwrm_cmd_resp_addr;
299 * Older HWRM versions did not support this command, and the set_rx_mask
300 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
301 * removed from set_rx_mask call, and this command was added.
303 * This command is also present from 1.7.8.11 and higher,
306 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
307 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
308 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
313 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG);
314 req.fid = rte_cpu_to_le_16(fid);
316 req.vlan_tag_mask_tbl_addr =
317 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
318 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
320 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
328 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
329 struct bnxt_filter_info *filter)
332 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
333 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
335 if (filter->fw_l2_filter_id == UINT64_MAX)
338 HWRM_PREP(req, CFA_L2_FILTER_FREE);
340 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
342 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
347 filter->fw_l2_filter_id = -1;
352 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
354 struct bnxt_filter_info *filter)
357 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
358 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
359 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
360 const struct rte_eth_vmdq_rx_conf *conf =
361 &dev_conf->rx_adv_conf.vmdq_rx_conf;
362 uint32_t enables = 0;
363 uint16_t j = dst_id - 1;
365 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
366 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
367 conf->pool_map[j].pools & (1UL << j)) {
369 "Add vlan %u to vmdq pool %u\n",
370 conf->pool_map[j].vlan_id, j);
372 filter->l2_ivlan = conf->pool_map[j].vlan_id;
374 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
375 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
378 if (filter->fw_l2_filter_id != UINT64_MAX)
379 bnxt_hwrm_clear_l2_filter(bp, filter);
381 HWRM_PREP(req, CFA_L2_FILTER_ALLOC);
383 req.flags = rte_cpu_to_le_32(filter->flags);
385 enables = filter->enables |
386 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
387 req.dst_id = rte_cpu_to_le_16(dst_id);
390 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
391 memcpy(req.l2_addr, filter->l2_addr,
394 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
395 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
398 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
399 req.l2_ovlan = filter->l2_ovlan;
401 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
402 req.l2_ovlan = filter->l2_ivlan;
404 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
405 req.l2_ovlan_mask = filter->l2_ovlan_mask;
407 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
408 req.l2_ovlan_mask = filter->l2_ivlan_mask;
409 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
410 req.src_id = rte_cpu_to_le_32(filter->src_id);
411 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
412 req.src_type = filter->src_type;
414 req.enables = rte_cpu_to_le_32(enables);
416 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
420 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
426 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
428 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
429 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
436 HWRM_PREP(req, PORT_MAC_CFG);
439 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
441 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
442 if (ptp->tx_tstamp_en)
443 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
445 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
446 req.flags = rte_cpu_to_le_32(flags);
448 rte_cpu_to_le_32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
449 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
451 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
457 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
460 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
461 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
462 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
464 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
468 HWRM_PREP(req, PORT_MAC_PTP_QCFG);
470 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
472 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
476 if (!(resp->flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS))
479 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
483 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
484 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
485 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
486 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
487 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
488 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
489 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
490 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
491 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
492 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
493 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
494 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
495 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
496 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
497 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
498 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
499 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
500 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
508 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
511 struct hwrm_func_qcaps_input req = {.req_type = 0 };
512 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
513 uint16_t new_max_vfs;
517 HWRM_PREP(req, FUNC_QCAPS);
519 req.fid = rte_cpu_to_le_16(0xffff);
521 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
525 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
526 flags = rte_le_to_cpu_32(resp->flags);
528 bp->pf.port_id = resp->port_id;
529 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
530 new_max_vfs = bp->pdev->max_vfs;
531 if (new_max_vfs != bp->pf.max_vfs) {
533 rte_free(bp->pf.vf_info);
534 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
535 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
536 bp->pf.max_vfs = new_max_vfs;
537 for (i = 0; i < new_max_vfs; i++) {
538 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
539 bp->pf.vf_info[i].vlan_table =
540 rte_zmalloc("VF VLAN table",
543 if (bp->pf.vf_info[i].vlan_table == NULL)
545 "Fail to alloc VLAN table for VF %d\n",
549 bp->pf.vf_info[i].vlan_table);
550 bp->pf.vf_info[i].vlan_as_table =
551 rte_zmalloc("VF VLAN AS table",
554 if (bp->pf.vf_info[i].vlan_as_table == NULL)
556 "Alloc VLAN AS table for VF %d fail\n",
560 bp->pf.vf_info[i].vlan_as_table);
561 STAILQ_INIT(&bp->pf.vf_info[i].filter);
566 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
567 memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
568 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
569 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
570 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
571 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
572 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
573 /* TODO: For now, do not support VMDq/RFS on VFs. */
578 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
582 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
584 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
585 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
586 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
587 PMD_DRV_LOG(INFO, "PTP SUPPORTED\n");
589 bnxt_hwrm_ptp_qcfg(bp);
598 int bnxt_hwrm_func_reset(struct bnxt *bp)
601 struct hwrm_func_reset_input req = {.req_type = 0 };
602 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
604 HWRM_PREP(req, FUNC_RESET);
606 req.enables = rte_cpu_to_le_32(0);
608 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
616 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
619 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
620 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
622 if (bp->flags & BNXT_FLAG_REGISTERED)
625 HWRM_PREP(req, FUNC_DRV_RGTR);
626 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
627 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
628 req.ver_maj = RTE_VER_YEAR;
629 req.ver_min = RTE_VER_MONTH;
630 req.ver_upd = RTE_VER_MINOR;
633 req.enables |= rte_cpu_to_le_32(
634 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
635 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
636 RTE_MIN(sizeof(req.vf_req_fwd),
637 sizeof(bp->pf.vf_req_fwd)));
640 req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1); /* TODO: Use MACRO */
641 //memset(req.async_event_fwd, 0xff, sizeof(req.async_event_fwd));
643 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
648 bp->flags |= BNXT_FLAG_REGISTERED;
653 int bnxt_hwrm_ver_get(struct bnxt *bp)
656 struct hwrm_ver_get_input req = {.req_type = 0 };
657 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
660 uint16_t max_resp_len;
661 char type[RTE_MEMZONE_NAMESIZE];
662 uint32_t dev_caps_cfg;
664 bp->max_req_len = HWRM_MAX_REQ_LEN;
665 HWRM_PREP(req, VER_GET);
667 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
668 req.hwrm_intf_min = HWRM_VERSION_MINOR;
669 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
671 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
675 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
676 resp->hwrm_intf_maj, resp->hwrm_intf_min,
678 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
679 bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
680 (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
681 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
682 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
684 my_version = HWRM_VERSION_MAJOR << 16;
685 my_version |= HWRM_VERSION_MINOR << 8;
686 my_version |= HWRM_VERSION_UPDATE;
688 fw_version = resp->hwrm_intf_maj << 16;
689 fw_version |= resp->hwrm_intf_min << 8;
690 fw_version |= resp->hwrm_intf_upd;
692 if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
693 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
698 if (my_version != fw_version) {
699 PMD_DRV_LOG(INFO, "BNXT Driver/HWRM API mismatch.\n");
700 if (my_version < fw_version) {
702 "Firmware API version is newer than driver.\n");
704 "The driver may be missing features.\n");
707 "Firmware API version is older than driver.\n");
709 "Not all driver features may be functional.\n");
713 if (bp->max_req_len > resp->max_req_win_len) {
714 PMD_DRV_LOG(ERR, "Unsupported request length\n");
717 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
718 max_resp_len = resp->max_resp_len;
719 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
721 if (bp->max_resp_len != max_resp_len) {
722 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
723 bp->pdev->addr.domain, bp->pdev->addr.bus,
724 bp->pdev->addr.devid, bp->pdev->addr.function);
726 rte_free(bp->hwrm_cmd_resp_addr);
728 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
729 if (bp->hwrm_cmd_resp_addr == NULL) {
733 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
734 bp->hwrm_cmd_resp_dma_addr =
735 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
736 if (bp->hwrm_cmd_resp_dma_addr == 0) {
738 "Unable to map response buffer to physical memory.\n");
742 bp->max_resp_len = max_resp_len;
746 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
748 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
749 PMD_DRV_LOG(DEBUG, "Short command supported\n");
751 rte_free(bp->hwrm_short_cmd_req_addr);
753 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
755 if (bp->hwrm_short_cmd_req_addr == NULL) {
759 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
760 bp->hwrm_short_cmd_req_dma_addr =
761 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
762 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
763 rte_free(bp->hwrm_short_cmd_req_addr);
765 "Unable to map buffer to physical memory.\n");
770 bp->flags |= BNXT_FLAG_SHORT_CMD;
778 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
781 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
782 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
784 if (!(bp->flags & BNXT_FLAG_REGISTERED))
787 HWRM_PREP(req, FUNC_DRV_UNRGTR);
790 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
795 bp->flags &= ~BNXT_FLAG_REGISTERED;
800 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
803 struct hwrm_port_phy_cfg_input req = {0};
804 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
805 uint32_t enables = 0;
807 HWRM_PREP(req, PORT_PHY_CFG);
810 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
811 if (bp->link_info.auto_mode && conf->link_speed) {
812 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
813 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
816 req.flags = rte_cpu_to_le_32(conf->phy_flags);
817 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
818 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
820 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
821 * any auto mode, even "none".
823 if (!conf->link_speed) {
824 /* No speeds specified. Enable AutoNeg - all speeds */
826 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
828 /* AutoNeg - Advertise speeds specified. */
829 if (conf->auto_link_speed_mask) {
831 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
832 req.auto_link_speed_mask =
833 conf->auto_link_speed_mask;
835 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
838 req.auto_duplex = conf->duplex;
839 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
840 req.auto_pause = conf->auto_pause;
841 req.force_pause = conf->force_pause;
842 /* Set force_pause if there is no auto or if there is a force */
843 if (req.auto_pause && !req.force_pause)
844 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
846 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
848 req.enables = rte_cpu_to_le_32(enables);
851 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
852 PMD_DRV_LOG(INFO, "Force Link Down\n");
855 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
863 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
864 struct bnxt_link_info *link_info)
867 struct hwrm_port_phy_qcfg_input req = {0};
868 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
870 HWRM_PREP(req, PORT_PHY_QCFG);
872 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
876 link_info->phy_link_status = resp->link;
878 (link_info->phy_link_status ==
879 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
880 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
881 link_info->duplex = resp->duplex_cfg;
882 link_info->pause = resp->pause;
883 link_info->auto_pause = resp->auto_pause;
884 link_info->force_pause = resp->force_pause;
885 link_info->auto_mode = resp->auto_mode;
886 link_info->phy_type = resp->phy_type;
887 link_info->media_type = resp->media_type;
889 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
890 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
891 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
892 link_info->phy_ver[0] = resp->phy_maj;
893 link_info->phy_ver[1] = resp->phy_min;
894 link_info->phy_ver[2] = resp->phy_bld;
901 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
904 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
905 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
907 HWRM_PREP(req, QUEUE_QPORTCFG);
909 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
913 #define GET_QUEUE_INFO(x) \
914 bp->cos_queue[x].id = resp->queue_id##x; \
915 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
931 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
932 struct bnxt_ring *ring,
933 uint32_t ring_type, uint32_t map_index,
934 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
937 uint32_t enables = 0;
938 struct hwrm_ring_alloc_input req = {.req_type = 0 };
939 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
941 HWRM_PREP(req, RING_ALLOC);
943 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
944 req.fbo = rte_cpu_to_le_32(0);
945 /* Association of ring index with doorbell index */
946 req.logical_id = rte_cpu_to_le_16(map_index);
947 req.length = rte_cpu_to_le_32(ring->ring_size);
950 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
951 req.queue_id = bp->cos_queue[0].id;
953 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
954 req.ring_type = ring_type;
955 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
956 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
957 if (stats_ctx_id != INVALID_STATS_CTX_ID)
959 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
961 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
962 req.ring_type = ring_type;
964 * TODO: Some HWRM versions crash with
965 * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
967 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
970 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
975 req.enables = rte_cpu_to_le_32(enables);
977 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
979 if (rc || resp->error_code) {
980 if (rc == 0 && resp->error_code)
981 rc = rte_le_to_cpu_16(resp->error_code);
983 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
985 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
988 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
990 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
993 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
995 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
999 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1005 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1010 int bnxt_hwrm_ring_free(struct bnxt *bp,
1011 struct bnxt_ring *ring, uint32_t ring_type)
1014 struct hwrm_ring_free_input req = {.req_type = 0 };
1015 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1017 HWRM_PREP(req, RING_FREE);
1019 req.ring_type = ring_type;
1020 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1022 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1024 if (rc || resp->error_code) {
1025 if (rc == 0 && resp->error_code)
1026 rc = rte_le_to_cpu_16(resp->error_code);
1029 switch (ring_type) {
1030 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1031 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1034 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1035 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1038 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1039 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1043 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1051 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1054 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1055 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1057 HWRM_PREP(req, RING_GRP_ALLOC);
1059 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1060 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1061 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1062 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1064 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1066 HWRM_CHECK_RESULT();
1068 bp->grp_info[idx].fw_grp_id =
1069 rte_le_to_cpu_16(resp->ring_group_id);
1076 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1079 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1080 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1082 HWRM_PREP(req, RING_GRP_FREE);
1084 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1086 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1088 HWRM_CHECK_RESULT();
1091 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1095 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1098 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1099 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1101 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1104 HWRM_PREP(req, STAT_CTX_CLR_STATS);
1106 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1108 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1110 HWRM_CHECK_RESULT();
1116 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1117 unsigned int idx __rte_unused)
1120 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1121 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1123 HWRM_PREP(req, STAT_CTX_ALLOC);
1125 req.update_period_ms = rte_cpu_to_le_32(0);
1127 req.stats_dma_addr =
1128 rte_cpu_to_le_64(cpr->hw_stats_map);
1130 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1132 HWRM_CHECK_RESULT();
1134 cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
1141 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1142 unsigned int idx __rte_unused)
1145 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1146 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1148 HWRM_PREP(req, STAT_CTX_FREE);
1150 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1152 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1154 HWRM_CHECK_RESULT();
1160 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1163 struct hwrm_vnic_alloc_input req = { 0 };
1164 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1166 /* map ring groups to this vnic */
1167 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1168 vnic->start_grp_id, vnic->end_grp_id);
1169 for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
1170 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1171 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1172 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1173 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1174 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1175 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1176 ETHER_CRC_LEN + VLAN_TAG_SIZE;
1177 HWRM_PREP(req, VNIC_ALLOC);
1179 if (vnic->func_default)
1180 req.flags = HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT;
1181 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1183 HWRM_CHECK_RESULT();
1185 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1187 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1191 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1192 struct bnxt_vnic_info *vnic,
1193 struct bnxt_plcmodes_cfg *pmode)
1196 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1197 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1199 HWRM_PREP(req, VNIC_PLCMODES_QCFG);
1201 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1203 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1205 HWRM_CHECK_RESULT();
1207 pmode->flags = rte_le_to_cpu_32(resp->flags);
1208 /* dflt_vnic bit doesn't exist in the _cfg command */
1209 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1210 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1211 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1212 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1219 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1220 struct bnxt_vnic_info *vnic,
1221 struct bnxt_plcmodes_cfg *pmode)
1224 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1225 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1227 HWRM_PREP(req, VNIC_PLCMODES_CFG);
1229 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1230 req.flags = rte_cpu_to_le_32(pmode->flags);
1231 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1232 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1233 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1234 req.enables = rte_cpu_to_le_32(
1235 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1236 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1237 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1240 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1242 HWRM_CHECK_RESULT();
1248 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1251 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1252 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1253 uint32_t ctx_enable_flag = 0;
1254 struct bnxt_plcmodes_cfg pmodes;
1256 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1257 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1261 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1265 HWRM_PREP(req, VNIC_CFG);
1267 /* Only RSS support for now TBD: COS & LB */
1269 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP);
1270 if (vnic->lb_rule != 0xffff)
1271 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1272 if (vnic->cos_rule != 0xffff)
1273 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1274 if (vnic->rss_rule != 0xffff) {
1275 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1276 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1278 req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1279 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1280 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1281 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1282 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1283 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1284 req.mru = rte_cpu_to_le_16(vnic->mru);
1285 if (vnic->func_default)
1287 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1288 if (vnic->vlan_strip)
1290 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1293 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1294 if (vnic->roce_dual)
1295 req.flags |= rte_cpu_to_le_32(
1296 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1297 if (vnic->roce_only)
1298 req.flags |= rte_cpu_to_le_32(
1299 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1300 if (vnic->rss_dflt_cr)
1301 req.flags |= rte_cpu_to_le_32(
1302 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1304 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1306 HWRM_CHECK_RESULT();
1309 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1314 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1318 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1319 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1321 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1322 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1325 HWRM_PREP(req, VNIC_QCFG);
1328 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1329 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1330 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1332 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1334 HWRM_CHECK_RESULT();
1336 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1337 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1338 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1339 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1340 vnic->mru = rte_le_to_cpu_16(resp->mru);
1341 vnic->func_default = rte_le_to_cpu_32(
1342 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1343 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1344 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1345 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1346 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1347 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1348 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1349 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1350 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1351 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1352 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1359 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1362 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1363 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1364 bp->hwrm_cmd_resp_addr;
1366 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC);
1368 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1370 HWRM_CHECK_RESULT();
1372 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1374 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1379 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1382 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1383 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1384 bp->hwrm_cmd_resp_addr;
1386 if (vnic->rss_rule == 0xffff) {
1387 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1390 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE);
1392 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1394 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1396 HWRM_CHECK_RESULT();
1399 vnic->rss_rule = INVALID_HW_RING_ID;
1404 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1407 struct hwrm_vnic_free_input req = {.req_type = 0 };
1408 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1410 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1411 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1415 HWRM_PREP(req, VNIC_FREE);
1417 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1419 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1421 HWRM_CHECK_RESULT();
1424 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1428 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1429 struct bnxt_vnic_info *vnic)
1432 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1433 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1435 HWRM_PREP(req, VNIC_RSS_CFG);
1437 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1439 req.ring_grp_tbl_addr =
1440 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1441 req.hash_key_tbl_addr =
1442 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1443 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1445 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1447 HWRM_CHECK_RESULT();
1453 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1454 struct bnxt_vnic_info *vnic)
1457 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1458 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1461 HWRM_PREP(req, VNIC_PLCMODES_CFG);
1463 req.flags = rte_cpu_to_le_32(
1464 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1466 req.enables = rte_cpu_to_le_32(
1467 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1469 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1470 size -= RTE_PKTMBUF_HEADROOM;
1472 req.jumbo_thresh = rte_cpu_to_le_16(size);
1473 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1475 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1477 HWRM_CHECK_RESULT();
1483 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1484 struct bnxt_vnic_info *vnic, bool enable)
1487 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1488 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1490 HWRM_PREP(req, VNIC_TPA_CFG);
1493 req.enables = rte_cpu_to_le_32(
1494 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1495 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1496 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1497 req.flags = rte_cpu_to_le_32(
1498 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1499 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1500 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1501 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1502 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1503 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1504 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1505 req.max_agg_segs = rte_cpu_to_le_16(5);
1507 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1508 req.min_agg_len = rte_cpu_to_le_32(512);
1511 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1513 HWRM_CHECK_RESULT();
1519 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1521 struct hwrm_func_cfg_input req = {0};
1522 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1525 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1526 req.enables = rte_cpu_to_le_32(
1527 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1528 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1529 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1531 HWRM_PREP(req, FUNC_CFG);
1533 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1534 HWRM_CHECK_RESULT();
1537 bp->pf.vf_info[vf].random_mac = false;
1542 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1546 struct hwrm_func_qstats_input req = {.req_type = 0};
1547 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1549 HWRM_PREP(req, FUNC_QSTATS);
1551 req.fid = rte_cpu_to_le_16(fid);
1553 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1555 HWRM_CHECK_RESULT();
1558 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1565 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1566 struct rte_eth_stats *stats)
1569 struct hwrm_func_qstats_input req = {.req_type = 0};
1570 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1572 HWRM_PREP(req, FUNC_QSTATS);
1574 req.fid = rte_cpu_to_le_16(fid);
1576 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1578 HWRM_CHECK_RESULT();
1580 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1581 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1582 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1583 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1584 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1585 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1587 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1588 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1589 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1590 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1591 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1592 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1594 stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1595 stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1597 stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1604 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1607 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1608 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1610 HWRM_PREP(req, FUNC_CLR_STATS);
1612 req.fid = rte_cpu_to_le_16(fid);
1614 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1616 HWRM_CHECK_RESULT();
1623 * HWRM utility functions
1626 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1631 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1632 struct bnxt_tx_queue *txq;
1633 struct bnxt_rx_queue *rxq;
1634 struct bnxt_cp_ring_info *cpr;
1636 if (i >= bp->rx_cp_nr_rings) {
1637 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1640 rxq = bp->rx_queues[i];
1644 rc = bnxt_hwrm_stat_clear(bp, cpr);
1651 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1655 struct bnxt_cp_ring_info *cpr;
1657 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1659 if (i >= bp->rx_cp_nr_rings) {
1660 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1662 cpr = bp->rx_queues[i]->cp_ring;
1663 bp->grp_info[i].fw_stats_ctx = -1;
1665 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1666 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1667 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1675 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1680 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1681 struct bnxt_tx_queue *txq;
1682 struct bnxt_rx_queue *rxq;
1683 struct bnxt_cp_ring_info *cpr;
1685 if (i >= bp->rx_cp_nr_rings) {
1686 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1689 rxq = bp->rx_queues[i];
1693 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1701 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1706 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1708 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1711 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1719 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1720 unsigned int idx __rte_unused)
1722 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1724 bnxt_hwrm_ring_free(bp, cp_ring,
1725 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1726 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1727 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1728 sizeof(*cpr->cp_desc_ring));
1729 cpr->cp_raw_cons = 0;
1732 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1737 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1738 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1739 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1740 struct bnxt_ring *ring = txr->tx_ring_struct;
1741 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1742 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1744 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1745 bnxt_hwrm_ring_free(bp, ring,
1746 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1747 ring->fw_ring_id = INVALID_HW_RING_ID;
1748 memset(txr->tx_desc_ring, 0,
1749 txr->tx_ring_struct->ring_size *
1750 sizeof(*txr->tx_desc_ring));
1751 memset(txr->tx_buf_ring, 0,
1752 txr->tx_ring_struct->ring_size *
1753 sizeof(*txr->tx_buf_ring));
1757 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1758 bnxt_free_cp_ring(bp, cpr, idx);
1759 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1763 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1764 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1765 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1766 struct bnxt_ring *ring = rxr->rx_ring_struct;
1767 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1768 unsigned int idx = i + 1;
1770 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1771 bnxt_hwrm_ring_free(bp, ring,
1772 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1773 ring->fw_ring_id = INVALID_HW_RING_ID;
1774 bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1775 memset(rxr->rx_desc_ring, 0,
1776 rxr->rx_ring_struct->ring_size *
1777 sizeof(*rxr->rx_desc_ring));
1778 memset(rxr->rx_buf_ring, 0,
1779 rxr->rx_ring_struct->ring_size *
1780 sizeof(*rxr->rx_buf_ring));
1783 ring = rxr->ag_ring_struct;
1784 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1785 bnxt_hwrm_ring_free(bp, ring,
1786 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1787 ring->fw_ring_id = INVALID_HW_RING_ID;
1788 memset(rxr->ag_buf_ring, 0,
1789 rxr->ag_ring_struct->ring_size *
1790 sizeof(*rxr->ag_buf_ring));
1792 bp->grp_info[i].ag_fw_ring_id = INVALID_HW_RING_ID;
1794 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1795 bnxt_free_cp_ring(bp, cpr, idx);
1796 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1797 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1801 /* Default completion ring */
1803 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1805 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1806 bnxt_free_cp_ring(bp, cpr, 0);
1807 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1814 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1819 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1820 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1827 void bnxt_free_hwrm_resources(struct bnxt *bp)
1829 /* Release memzone */
1830 rte_free(bp->hwrm_cmd_resp_addr);
1831 rte_free(bp->hwrm_short_cmd_req_addr);
1832 bp->hwrm_cmd_resp_addr = NULL;
1833 bp->hwrm_short_cmd_req_addr = NULL;
1834 bp->hwrm_cmd_resp_dma_addr = 0;
1835 bp->hwrm_short_cmd_req_dma_addr = 0;
1838 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1840 struct rte_pci_device *pdev = bp->pdev;
1841 char type[RTE_MEMZONE_NAMESIZE];
1843 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1844 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1845 bp->max_resp_len = HWRM_MAX_RESP_LEN;
1846 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1847 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1848 if (bp->hwrm_cmd_resp_addr == NULL)
1850 bp->hwrm_cmd_resp_dma_addr =
1851 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1852 if (bp->hwrm_cmd_resp_dma_addr == 0) {
1854 "unable to map response address to physical memory\n");
1857 rte_spinlock_init(&bp->hwrm_lock);
1862 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1864 struct bnxt_filter_info *filter;
1867 STAILQ_FOREACH(filter, &vnic->filter, next) {
1868 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1869 rc = bnxt_hwrm_clear_em_filter(bp, filter);
1870 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1871 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1873 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1881 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1883 struct bnxt_filter_info *filter;
1884 struct rte_flow *flow;
1887 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
1888 filter = flow->filter;
1889 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
1890 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1891 rc = bnxt_hwrm_clear_em_filter(bp, filter);
1892 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1893 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1895 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1897 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
1905 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1907 struct bnxt_filter_info *filter;
1910 STAILQ_FOREACH(filter, &vnic->filter, next) {
1911 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1912 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
1914 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1915 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
1918 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
1926 void bnxt_free_tunnel_ports(struct bnxt *bp)
1928 if (bp->vxlan_port_cnt)
1929 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1930 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1932 if (bp->geneve_port_cnt)
1933 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1934 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1935 bp->geneve_port = 0;
1938 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1942 if (bp->vnic_info == NULL)
1946 * Cleanup VNICs in reverse order, to make sure the L2 filter
1947 * from vnic0 is last to be cleaned up.
1949 for (i = bp->nr_vnics - 1; i >= 0; i--) {
1950 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1952 bnxt_clear_hwrm_vnic_flows(bp, vnic);
1954 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1956 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1958 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1960 bnxt_hwrm_vnic_free(bp, vnic);
1962 /* Ring resources */
1963 bnxt_free_all_hwrm_rings(bp);
1964 bnxt_free_all_hwrm_ring_grps(bp);
1965 bnxt_free_all_hwrm_stat_ctxs(bp);
1966 bnxt_free_tunnel_ports(bp);
1969 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1971 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1973 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1974 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1976 switch (conf_link_speed) {
1977 case ETH_LINK_SPEED_10M_HD:
1978 case ETH_LINK_SPEED_100M_HD:
1979 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1981 return hw_link_duplex;
1984 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
1986 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
1989 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1991 uint16_t eth_link_speed = 0;
1993 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1994 return ETH_LINK_SPEED_AUTONEG;
1996 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1997 case ETH_LINK_SPEED_100M:
1998 case ETH_LINK_SPEED_100M_HD:
2000 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2002 case ETH_LINK_SPEED_1G:
2004 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2006 case ETH_LINK_SPEED_2_5G:
2008 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2010 case ETH_LINK_SPEED_10G:
2012 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2014 case ETH_LINK_SPEED_20G:
2016 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2018 case ETH_LINK_SPEED_25G:
2020 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2022 case ETH_LINK_SPEED_40G:
2024 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2026 case ETH_LINK_SPEED_50G:
2028 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2032 "Unsupported link speed %d; default to AUTO\n",
2036 return eth_link_speed;
2039 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2040 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2041 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2042 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
2044 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2048 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2051 if (link_speed & ETH_LINK_SPEED_FIXED) {
2052 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2054 if (one_speed & (one_speed - 1)) {
2056 "Invalid advertised speeds (%u) for port %u\n",
2057 link_speed, port_id);
2060 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2062 "Unsupported advertised speed (%u) for port %u\n",
2063 link_speed, port_id);
2067 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2069 "Unsupported advertised speeds (%u) for port %u\n",
2070 link_speed, port_id);
2078 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2082 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2083 if (bp->link_info.support_speeds)
2084 return bp->link_info.support_speeds;
2085 link_speed = BNXT_SUPPORTED_SPEEDS;
2088 if (link_speed & ETH_LINK_SPEED_100M)
2089 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2090 if (link_speed & ETH_LINK_SPEED_100M_HD)
2091 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2092 if (link_speed & ETH_LINK_SPEED_1G)
2093 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2094 if (link_speed & ETH_LINK_SPEED_2_5G)
2095 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2096 if (link_speed & ETH_LINK_SPEED_10G)
2097 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2098 if (link_speed & ETH_LINK_SPEED_20G)
2099 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2100 if (link_speed & ETH_LINK_SPEED_25G)
2101 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2102 if (link_speed & ETH_LINK_SPEED_40G)
2103 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2104 if (link_speed & ETH_LINK_SPEED_50G)
2105 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2109 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2111 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2113 switch (hw_link_speed) {
2114 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2115 eth_link_speed = ETH_SPEED_NUM_100M;
2117 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2118 eth_link_speed = ETH_SPEED_NUM_1G;
2120 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2121 eth_link_speed = ETH_SPEED_NUM_2_5G;
2123 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2124 eth_link_speed = ETH_SPEED_NUM_10G;
2126 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2127 eth_link_speed = ETH_SPEED_NUM_20G;
2129 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2130 eth_link_speed = ETH_SPEED_NUM_25G;
2132 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2133 eth_link_speed = ETH_SPEED_NUM_40G;
2135 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2136 eth_link_speed = ETH_SPEED_NUM_50G;
2138 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2140 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2144 return eth_link_speed;
2147 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2149 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2151 switch (hw_link_duplex) {
2152 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2153 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2154 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2156 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2157 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2160 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2164 return eth_link_duplex;
2167 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2170 struct bnxt_link_info *link_info = &bp->link_info;
2172 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2175 "Get link config failed with rc %d\n", rc);
2178 if (link_info->link_speed)
2180 bnxt_parse_hw_link_speed(link_info->link_speed);
2182 link->link_speed = ETH_SPEED_NUM_NONE;
2183 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2184 link->link_status = link_info->link_up;
2185 link->link_autoneg = link_info->auto_mode ==
2186 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2187 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2192 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2195 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2196 struct bnxt_link_info link_req;
2197 uint16_t speed, autoneg;
2199 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2202 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2203 bp->eth_dev->data->port_id);
2207 memset(&link_req, 0, sizeof(link_req));
2208 link_req.link_up = link_up;
2212 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2213 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2214 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2216 link_req.phy_flags |=
2217 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2218 link_req.auto_link_speed_mask =
2219 bnxt_parse_eth_link_speed_mask(bp,
2220 dev_conf->link_speeds);
2222 if (bp->link_info.phy_type ==
2223 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2224 bp->link_info.phy_type ==
2225 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2226 bp->link_info.media_type ==
2227 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2228 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2232 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2233 link_req.link_speed = speed;
2235 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2236 link_req.auto_pause = bp->link_info.auto_pause;
2237 link_req.force_pause = bp->link_info.force_pause;
2240 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2243 "Set link config failed with rc %d\n", rc);
2251 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2253 struct hwrm_func_qcfg_input req = {0};
2254 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2258 HWRM_PREP(req, FUNC_QCFG);
2259 req.fid = rte_cpu_to_le_16(0xffff);
2261 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2263 HWRM_CHECK_RESULT();
2265 /* Hard Coded.. 0xfff VLAN ID mask */
2266 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2267 flags = rte_le_to_cpu_16(resp->flags);
2268 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2269 bp->flags |= BNXT_FLAG_MULTI_HOST;
2271 switch (resp->port_partition_type) {
2272 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2273 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2274 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2275 bp->port_partition_type = resp->port_partition_type;
2278 bp->port_partition_type = 0;
2287 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2288 struct hwrm_func_qcaps_output *qcaps)
2290 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2291 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2292 sizeof(qcaps->mac_address));
2293 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2294 qcaps->max_rx_rings = fcfg->num_rx_rings;
2295 qcaps->max_tx_rings = fcfg->num_tx_rings;
2296 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2297 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2299 qcaps->first_vf_id = 0;
2300 qcaps->max_vnics = fcfg->num_vnics;
2301 qcaps->max_decap_records = 0;
2302 qcaps->max_encap_records = 0;
2303 qcaps->max_tx_wm_flows = 0;
2304 qcaps->max_tx_em_flows = 0;
2305 qcaps->max_rx_wm_flows = 0;
2306 qcaps->max_rx_em_flows = 0;
2307 qcaps->max_flow_id = 0;
2308 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2309 qcaps->max_sp_tx_rings = 0;
2310 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2313 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2315 struct hwrm_func_cfg_input req = {0};
2316 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2319 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2320 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2321 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2322 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2323 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2324 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2325 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2326 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2327 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2328 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2329 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2330 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2331 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2332 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2333 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2334 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2335 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2336 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2337 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2338 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2339 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2340 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2341 req.fid = rte_cpu_to_le_16(0xffff);
2343 HWRM_PREP(req, FUNC_CFG);
2345 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2347 HWRM_CHECK_RESULT();
2353 static void populate_vf_func_cfg_req(struct bnxt *bp,
2354 struct hwrm_func_cfg_input *req,
2357 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2358 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2359 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2360 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2361 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2362 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2363 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2364 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2365 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2366 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2368 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2369 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2370 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2371 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2372 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2374 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2375 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2377 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2378 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2379 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2380 /* TODO: For now, do not support VMDq/RFS on VFs. */
2381 req->num_vnics = rte_cpu_to_le_16(1);
2382 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2386 static void add_random_mac_if_needed(struct bnxt *bp,
2387 struct hwrm_func_cfg_input *cfg_req,
2390 struct ether_addr mac;
2392 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2395 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2397 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2398 eth_random_addr(cfg_req->dflt_mac_addr);
2399 bp->pf.vf_info[vf].random_mac = true;
2401 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2405 static void reserve_resources_from_vf(struct bnxt *bp,
2406 struct hwrm_func_cfg_input *cfg_req,
2409 struct hwrm_func_qcaps_input req = {0};
2410 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2413 /* Get the actual allocated values now */
2414 HWRM_PREP(req, FUNC_QCAPS);
2415 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2416 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2419 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2420 copy_func_cfg_to_qcaps(cfg_req, resp);
2421 } else if (resp->error_code) {
2422 rc = rte_le_to_cpu_16(resp->error_code);
2423 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2424 copy_func_cfg_to_qcaps(cfg_req, resp);
2427 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2428 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2429 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2430 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2431 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2432 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2434 * TODO: While not supporting VMDq with VFs, max_vnics is always
2435 * forced to 1 in this case
2437 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2438 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2443 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2445 struct hwrm_func_qcfg_input req = {0};
2446 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2449 /* Check for zero MAC address */
2450 HWRM_PREP(req, FUNC_QCFG);
2451 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2452 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2454 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2456 } else if (resp->error_code) {
2457 rc = rte_le_to_cpu_16(resp->error_code);
2458 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2461 rc = rte_le_to_cpu_16(resp->vlan);
2468 static int update_pf_resource_max(struct bnxt *bp)
2470 struct hwrm_func_qcfg_input req = {0};
2471 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2474 /* And copy the allocated numbers into the pf struct */
2475 HWRM_PREP(req, FUNC_QCFG);
2476 req.fid = rte_cpu_to_le_16(0xffff);
2477 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2478 HWRM_CHECK_RESULT();
2480 /* Only TX ring value reflects actual allocation? TODO */
2481 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2482 bp->pf.evb_mode = resp->evb_mode;
2489 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2494 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2498 rc = bnxt_hwrm_func_qcaps(bp);
2502 bp->pf.func_cfg_flags &=
2503 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2504 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2505 bp->pf.func_cfg_flags |=
2506 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2507 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2511 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2513 struct hwrm_func_cfg_input req = {0};
2514 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2521 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2525 rc = bnxt_hwrm_func_qcaps(bp);
2530 bp->pf.active_vfs = num_vfs;
2533 * First, configure the PF to only use one TX ring. This ensures that
2534 * there are enough rings for all VFs.
2536 * If we don't do this, when we call func_alloc() later, we will lock
2537 * extra rings to the PF that won't be available during func_cfg() of
2540 * This has been fixed with firmware versions above 20.6.54
2542 bp->pf.func_cfg_flags &=
2543 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2544 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2545 bp->pf.func_cfg_flags |=
2546 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2547 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2552 * Now, create and register a buffer to hold forwarded VF requests
2554 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2555 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2556 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2557 if (bp->pf.vf_req_buf == NULL) {
2561 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2562 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2563 for (i = 0; i < num_vfs; i++)
2564 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2565 (i * HWRM_MAX_REQ_LEN);
2567 rc = bnxt_hwrm_func_buf_rgtr(bp);
2571 populate_vf_func_cfg_req(bp, &req, num_vfs);
2573 bp->pf.active_vfs = 0;
2574 for (i = 0; i < num_vfs; i++) {
2575 add_random_mac_if_needed(bp, &req, i);
2577 HWRM_PREP(req, FUNC_CFG);
2578 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2579 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2580 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2582 /* Clear enable flag for next pass */
2583 req.enables &= ~rte_cpu_to_le_32(
2584 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2586 if (rc || resp->error_code) {
2588 "Failed to initizlie VF %d\n", i);
2590 "Not all VFs available. (%d, %d)\n",
2591 rc, resp->error_code);
2598 reserve_resources_from_vf(bp, &req, i);
2599 bp->pf.active_vfs++;
2600 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2604 * Now configure the PF to use "the rest" of the resources
2605 * We're using STD_TX_RING_MODE here though which will limit the TX
2606 * rings. This will allow QoS to function properly. Not setting this
2607 * will cause PF rings to break bandwidth settings.
2609 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2613 rc = update_pf_resource_max(bp);
2620 bnxt_hwrm_func_buf_unrgtr(bp);
2624 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2626 struct hwrm_func_cfg_input req = {0};
2627 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2630 HWRM_PREP(req, FUNC_CFG);
2632 req.fid = rte_cpu_to_le_16(0xffff);
2633 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2634 req.evb_mode = bp->pf.evb_mode;
2636 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2637 HWRM_CHECK_RESULT();
2643 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2644 uint8_t tunnel_type)
2646 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2647 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2650 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC);
2651 req.tunnel_type = tunnel_type;
2652 req.tunnel_dst_port_val = port;
2653 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2654 HWRM_CHECK_RESULT();
2656 switch (tunnel_type) {
2657 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2658 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2659 bp->vxlan_port = port;
2661 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2662 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2663 bp->geneve_port = port;
2674 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2675 uint8_t tunnel_type)
2677 struct hwrm_tunnel_dst_port_free_input req = {0};
2678 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2681 HWRM_PREP(req, TUNNEL_DST_PORT_FREE);
2683 req.tunnel_type = tunnel_type;
2684 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2685 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2687 HWRM_CHECK_RESULT();
2693 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2696 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2697 struct hwrm_func_cfg_input req = {0};
2700 HWRM_PREP(req, FUNC_CFG);
2702 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2703 req.flags = rte_cpu_to_le_32(flags);
2704 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2706 HWRM_CHECK_RESULT();
2712 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2714 uint32_t *flag = flagp;
2716 vnic->flags = *flag;
2719 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2721 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2724 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2727 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2728 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2730 HWRM_PREP(req, FUNC_BUF_RGTR);
2732 req.req_buf_num_pages = rte_cpu_to_le_16(1);
2733 req.req_buf_page_size = rte_cpu_to_le_16(
2734 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2735 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2736 req.req_buf_page_addr[0] =
2737 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
2738 if (req.req_buf_page_addr[0] == 0) {
2740 "unable to map buffer address to physical memory\n");
2744 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2746 HWRM_CHECK_RESULT();
2752 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2755 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2756 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2758 HWRM_PREP(req, FUNC_BUF_UNRGTR);
2760 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2762 HWRM_CHECK_RESULT();
2768 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2770 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2771 struct hwrm_func_cfg_input req = {0};
2774 HWRM_PREP(req, FUNC_CFG);
2776 req.fid = rte_cpu_to_le_16(0xffff);
2777 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2778 req.enables = rte_cpu_to_le_32(
2779 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2780 req.async_event_cr = rte_cpu_to_le_16(
2781 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2782 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2784 HWRM_CHECK_RESULT();
2790 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2792 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2793 struct hwrm_func_vf_cfg_input req = {0};
2796 HWRM_PREP(req, FUNC_VF_CFG);
2798 req.enables = rte_cpu_to_le_32(
2799 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2800 req.async_event_cr = rte_cpu_to_le_16(
2801 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2802 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2804 HWRM_CHECK_RESULT();
2810 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2812 struct hwrm_func_cfg_input req = {0};
2813 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2814 uint16_t dflt_vlan, fid;
2815 uint32_t func_cfg_flags;
2818 HWRM_PREP(req, FUNC_CFG);
2821 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2822 fid = bp->pf.vf_info[vf].fid;
2823 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2825 fid = rte_cpu_to_le_16(0xffff);
2826 func_cfg_flags = bp->pf.func_cfg_flags;
2827 dflt_vlan = bp->vlan;
2830 req.flags = rte_cpu_to_le_32(func_cfg_flags);
2831 req.fid = rte_cpu_to_le_16(fid);
2832 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2833 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2835 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2837 HWRM_CHECK_RESULT();
2843 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2844 uint16_t max_bw, uint16_t enables)
2846 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2847 struct hwrm_func_cfg_input req = {0};
2850 HWRM_PREP(req, FUNC_CFG);
2852 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2853 req.enables |= rte_cpu_to_le_32(enables);
2854 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2855 req.max_bw = rte_cpu_to_le_32(max_bw);
2856 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2858 HWRM_CHECK_RESULT();
2864 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2866 struct hwrm_func_cfg_input req = {0};
2867 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2870 HWRM_PREP(req, FUNC_CFG);
2872 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2873 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2874 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2875 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2877 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2879 HWRM_CHECK_RESULT();
2885 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2886 void *encaped, size_t ec_size)
2889 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2890 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2892 if (ec_size > sizeof(req.encap_request))
2895 HWRM_PREP(req, REJECT_FWD_RESP);
2897 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2898 memcpy(req.encap_request, encaped, ec_size);
2900 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2902 HWRM_CHECK_RESULT();
2908 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2909 struct ether_addr *mac)
2911 struct hwrm_func_qcfg_input req = {0};
2912 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2915 HWRM_PREP(req, FUNC_QCFG);
2917 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2918 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2920 HWRM_CHECK_RESULT();
2922 memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2929 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2930 void *encaped, size_t ec_size)
2933 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2934 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2936 if (ec_size > sizeof(req.encap_request))
2939 HWRM_PREP(req, EXEC_FWD_RESP);
2941 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2942 memcpy(req.encap_request, encaped, ec_size);
2944 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2946 HWRM_CHECK_RESULT();
2952 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2953 struct rte_eth_stats *stats, uint8_t rx)
2956 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2957 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2959 HWRM_PREP(req, STAT_CTX_QUERY);
2961 req.stat_ctx_id = rte_cpu_to_le_32(cid);
2963 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2965 HWRM_CHECK_RESULT();
2968 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2969 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2970 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2971 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2972 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2973 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2974 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2975 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2977 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2978 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2979 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2980 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2981 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2982 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2983 stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
2992 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2994 struct hwrm_port_qstats_input req = {0};
2995 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2996 struct bnxt_pf_info *pf = &bp->pf;
2999 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
3002 HWRM_PREP(req, PORT_QSTATS);
3004 req.port_id = rte_cpu_to_le_16(pf->port_id);
3005 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3006 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3007 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3009 HWRM_CHECK_RESULT();
3015 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3017 struct hwrm_port_clr_stats_input req = {0};
3018 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3019 struct bnxt_pf_info *pf = &bp->pf;
3022 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
3025 HWRM_PREP(req, PORT_CLR_STATS);
3027 req.port_id = rte_cpu_to_le_16(pf->port_id);
3028 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3030 HWRM_CHECK_RESULT();
3036 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3038 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3039 struct hwrm_port_led_qcaps_input req = {0};
3045 HWRM_PREP(req, PORT_LED_QCAPS);
3046 req.port_id = bp->pf.port_id;
3047 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3049 HWRM_CHECK_RESULT();
3051 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3054 bp->num_leds = resp->num_leds;
3055 memcpy(bp->leds, &resp->led0_id,
3056 sizeof(bp->leds[0]) * bp->num_leds);
3057 for (i = 0; i < bp->num_leds; i++) {
3058 struct bnxt_led_info *led = &bp->leds[i];
3060 uint16_t caps = led->led_state_caps;
3062 if (!led->led_group_id ||
3063 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3075 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3077 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3078 struct hwrm_port_led_cfg_input req = {0};
3079 struct bnxt_led_cfg *led_cfg;
3080 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3081 uint16_t duration = 0;
3084 if (!bp->num_leds || BNXT_VF(bp))
3087 HWRM_PREP(req, PORT_LED_CFG);
3090 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3091 duration = rte_cpu_to_le_16(500);
3093 req.port_id = bp->pf.port_id;
3094 req.num_leds = bp->num_leds;
3095 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3096 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3097 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3098 led_cfg->led_id = bp->leds[i].led_id;
3099 led_cfg->led_state = led_state;
3100 led_cfg->led_blink_on = duration;
3101 led_cfg->led_blink_off = duration;
3102 led_cfg->led_group_id = bp->leds[i].led_group_id;
3105 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3107 HWRM_CHECK_RESULT();
3113 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3117 struct hwrm_nvm_get_dir_info_input req = {0};
3118 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3120 HWRM_PREP(req, NVM_GET_DIR_INFO);
3122 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3124 HWRM_CHECK_RESULT();
3128 *entries = rte_le_to_cpu_32(resp->entries);
3129 *length = rte_le_to_cpu_32(resp->entry_length);
3134 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3137 uint32_t dir_entries;
3138 uint32_t entry_length;
3141 rte_iova_t dma_handle;
3142 struct hwrm_nvm_get_dir_entries_input req = {0};
3143 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3145 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3149 *data++ = dir_entries;
3150 *data++ = entry_length;
3152 memset(data, 0xff, len);
3154 buflen = dir_entries * entry_length;
3155 buf = rte_malloc("nvm_dir", buflen, 0);
3156 rte_mem_lock_page(buf);
3159 dma_handle = rte_mem_virt2iova(buf);
3160 if (dma_handle == 0) {
3162 "unable to map response address to physical memory\n");
3165 HWRM_PREP(req, NVM_GET_DIR_ENTRIES);
3166 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3167 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3169 HWRM_CHECK_RESULT();
3173 memcpy(data, buf, len > buflen ? buflen : len);
3180 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3181 uint32_t offset, uint32_t length,
3186 rte_iova_t dma_handle;
3187 struct hwrm_nvm_read_input req = {0};
3188 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3190 buf = rte_malloc("nvm_item", length, 0);
3191 rte_mem_lock_page(buf);
3195 dma_handle = rte_mem_virt2iova(buf);
3196 if (dma_handle == 0) {
3198 "unable to map response address to physical memory\n");
3201 HWRM_PREP(req, NVM_READ);
3202 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3203 req.dir_idx = rte_cpu_to_le_16(index);
3204 req.offset = rte_cpu_to_le_32(offset);
3205 req.len = rte_cpu_to_le_32(length);
3206 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3207 HWRM_CHECK_RESULT();
3210 memcpy(data, buf, length);
3216 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3219 struct hwrm_nvm_erase_dir_entry_input req = {0};
3220 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3222 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY);
3223 req.dir_idx = rte_cpu_to_le_16(index);
3224 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3225 HWRM_CHECK_RESULT();
3232 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3233 uint16_t dir_ordinal, uint16_t dir_ext,
3234 uint16_t dir_attr, const uint8_t *data,
3238 struct hwrm_nvm_write_input req = {0};
3239 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3240 rte_iova_t dma_handle;
3243 HWRM_PREP(req, NVM_WRITE);
3245 req.dir_type = rte_cpu_to_le_16(dir_type);
3246 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3247 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3248 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3249 req.dir_data_length = rte_cpu_to_le_32(data_len);
3251 buf = rte_malloc("nvm_write", data_len, 0);
3252 rte_mem_lock_page(buf);
3256 dma_handle = rte_mem_virt2iova(buf);
3257 if (dma_handle == 0) {
3259 "unable to map response address to physical memory\n");
3262 memcpy(buf, data, data_len);
3263 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3265 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3267 HWRM_CHECK_RESULT();
3275 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3277 uint32_t *count = cbdata;
3279 *count = *count + 1;
3282 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3283 struct bnxt_vnic_info *vnic __rte_unused)
3288 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3292 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3293 &count, bnxt_vnic_count_hwrm_stub);
3298 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3301 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3302 struct hwrm_func_vf_vnic_ids_query_output *resp =
3303 bp->hwrm_cmd_resp_addr;
3306 /* First query all VNIC ids */
3307 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY);
3309 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3310 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3311 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3313 if (req.vnic_id_tbl_addr == 0) {
3316 "unable to map VNIC ID table address to physical memory\n");
3319 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3322 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3324 } else if (resp->error_code) {
3325 rc = rte_le_to_cpu_16(resp->error_code);
3327 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3330 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3338 * This function queries the VNIC IDs for a specified VF. It then calls
3339 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3340 * Then it calls the hwrm_cb function to program this new vnic configuration.
3342 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3343 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3344 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3346 struct bnxt_vnic_info vnic;
3348 int i, num_vnic_ids;
3353 /* First query all VNIC ids */
3354 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3355 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3356 RTE_CACHE_LINE_SIZE);
3357 if (vnic_ids == NULL) {
3361 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3362 rte_mem_lock_page(((char *)vnic_ids) + sz);
3364 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3366 if (num_vnic_ids < 0)
3367 return num_vnic_ids;
3369 /* Retrieve VNIC, update bd_stall then update */
3371 for (i = 0; i < num_vnic_ids; i++) {
3372 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3373 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3374 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3377 if (vnic.mru <= 4) /* Indicates unallocated */
3380 vnic_cb(&vnic, cbdata);
3382 rc = hwrm_cb(bp, &vnic);
3392 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3395 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3396 struct hwrm_func_cfg_input req = {0};
3399 HWRM_PREP(req, FUNC_CFG);
3401 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3402 req.enables |= rte_cpu_to_le_32(
3403 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3404 req.vlan_antispoof_mode = on ?
3405 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3406 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3407 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3409 HWRM_CHECK_RESULT();
3415 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3417 struct bnxt_vnic_info vnic;
3420 int num_vnic_ids, i;
3424 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3425 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3426 RTE_CACHE_LINE_SIZE);
3427 if (vnic_ids == NULL) {
3432 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3433 rte_mem_lock_page(((char *)vnic_ids) + sz);
3435 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3441 * Loop through to find the default VNIC ID.
3442 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3443 * by sending the hwrm_func_qcfg command to the firmware.
3445 for (i = 0; i < num_vnic_ids; i++) {
3446 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3447 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3448 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3449 bp->pf.first_vf_id + vf);
3452 if (vnic.func_default) {
3454 return vnic.fw_vnic_id;
3457 /* Could not find a default VNIC. */
3458 PMD_DRV_LOG(ERR, "No default VNIC\n");
3464 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3466 struct bnxt_filter_info *filter)
3469 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3470 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3471 uint32_t enables = 0;
3473 if (filter->fw_em_filter_id != UINT64_MAX)
3474 bnxt_hwrm_clear_em_filter(bp, filter);
3476 HWRM_PREP(req, CFA_EM_FLOW_ALLOC);
3478 req.flags = rte_cpu_to_le_32(filter->flags);
3480 enables = filter->enables |
3481 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3482 req.dst_id = rte_cpu_to_le_16(dst_id);
3484 if (filter->ip_addr_type) {
3485 req.ip_addr_type = filter->ip_addr_type;
3486 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3489 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3490 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3492 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3493 memcpy(req.src_macaddr, filter->src_macaddr,
3496 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3497 memcpy(req.dst_macaddr, filter->dst_macaddr,
3500 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3501 req.ovlan_vid = filter->l2_ovlan;
3503 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3504 req.ivlan_vid = filter->l2_ivlan;
3506 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3507 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3509 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3510 req.ip_protocol = filter->ip_protocol;
3512 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3513 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3515 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3516 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3518 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3519 req.src_port = rte_cpu_to_be_16(filter->src_port);
3521 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3522 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3524 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3525 req.mirror_vnic_id = filter->mirror_vnic_id;
3527 req.enables = rte_cpu_to_le_32(enables);
3529 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3531 HWRM_CHECK_RESULT();
3533 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3539 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3542 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3543 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3545 if (filter->fw_em_filter_id == UINT64_MAX)
3548 PMD_DRV_LOG(ERR, "Clear EM filter\n");
3549 HWRM_PREP(req, CFA_EM_FLOW_FREE);
3551 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3553 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3555 HWRM_CHECK_RESULT();
3558 filter->fw_em_filter_id = -1;
3559 filter->fw_l2_filter_id = -1;
3564 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3566 struct bnxt_filter_info *filter)
3569 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3570 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3571 bp->hwrm_cmd_resp_addr;
3572 uint32_t enables = 0;
3574 if (filter->fw_ntuple_filter_id != UINT64_MAX)
3575 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3577 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC);
3579 req.flags = rte_cpu_to_le_32(filter->flags);
3581 enables = filter->enables |
3582 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3583 req.dst_id = rte_cpu_to_le_16(dst_id);
3586 if (filter->ip_addr_type) {
3587 req.ip_addr_type = filter->ip_addr_type;
3589 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3592 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3593 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3595 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3596 memcpy(req.src_macaddr, filter->src_macaddr,
3599 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3600 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3603 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3604 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3606 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3607 req.ip_protocol = filter->ip_protocol;
3609 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3610 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3612 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3613 req.src_ipaddr_mask[0] =
3614 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3616 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3617 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3619 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3620 req.dst_ipaddr_mask[0] =
3621 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3623 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3624 req.src_port = rte_cpu_to_le_16(filter->src_port);
3626 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3627 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3629 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3630 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3632 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3633 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3635 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3636 req.mirror_vnic_id = filter->mirror_vnic_id;
3638 req.enables = rte_cpu_to_le_32(enables);
3640 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3642 HWRM_CHECK_RESULT();
3644 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
3650 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
3651 struct bnxt_filter_info *filter)
3654 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
3655 struct hwrm_cfa_ntuple_filter_free_output *resp =
3656 bp->hwrm_cmd_resp_addr;
3658 if (filter->fw_ntuple_filter_id == UINT64_MAX)
3661 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE);
3663 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
3665 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3667 HWRM_CHECK_RESULT();
3670 filter->fw_ntuple_filter_id = -1;