drivers/net/bnxt/bnxt_hwrm.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <rte_byteorder.h>
  35 #include <rte_common.h>
  36 #include <rte_cycles.h>
  37 #include <rte_malloc.h>
  38 #include <rte_memzone.h>
  39 #include <rte_version.h>
  40
  41 #include "bnxt.h"
  42 #include "bnxt_cpr.h"
  43 #include "bnxt_filter.h"
  44 #include "bnxt_hwrm.h"
  45 #include "bnxt_rxq.h"
  46 #include "bnxt_rxr.h"
  47 #include "bnxt_ring.h"
  48 #include "bnxt_txq.h"
  49 #include "bnxt_txr.h"
  50 #include "bnxt_vnic.h"
  51 #include "hsi_struct_def_dpdk.h"
  52
  53 #define HWRM_CMD_TIMEOUT                2000
  54
  55 /*
  56  * HWRM Functions (sent to HWRM)
  57  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  58  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  59  * command was failed by the ChiMP.
  60  */
  61
  62 static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
  63                                         uint32_t msg_len)
  64 {
  65         unsigned int i;
  66         struct input *req = msg;
  67         struct output *resp = bp->hwrm_cmd_resp_addr;
  68         uint32_t *data = msg;
  69         uint8_t *bar;
  70         uint8_t *valid;
  71
  72         /* Write request msg to hwrm channel */
  73         for (i = 0; i < msg_len; i += 4) {
  74                 bar = (uint8_t *)bp->bar0 + i;
  75                 *(volatile uint32_t *)bar = *data;
  76                 data++;
  77         }
  78
  79         /* Zero the rest of the request space */
  80         for (; i < bp->max_req_len; i += 4) {
  81                 bar = (uint8_t *)bp->bar0 + i;
  82                 *(volatile uint32_t *)bar = 0;
  83         }
  84
  85         /* Ring channel doorbell */
  86         bar = (uint8_t *)bp->bar0 + 0x100;
  87         *(volatile uint32_t *)bar = 1;
  88
  89         /* Poll for the valid bit */
  90         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
  91                 /* Sanity check on the resp->resp_len */
  92                 rte_rmb();
  93                 if (resp->resp_len && resp->resp_len <=
  94                                 bp->max_resp_len) {
  95                         /* Last byte of resp contains the valid key */
  96                         valid = (uint8_t *)resp + resp->resp_len - 1;
  97                         if (*valid == HWRM_RESP_VALID_KEY)
  98                                 break;
  99                 }
 100                 rte_delay_us(600);
 101         }
 102
 103         if (i >= HWRM_CMD_TIMEOUT) {
 104                 RTE_LOG(ERR, PMD, "Error sending msg %x\n",
 105                         req->req_type);
 106                 goto err_ret;
 107         }
 108         return 0;
 109
 110 err_ret:
 111         return -1;
 112 }
 113
 114 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)
 115 {
 116         int rc;
 117
 118         rte_spinlock_lock(&bp->hwrm_lock);
 119         rc = bnxt_hwrm_send_message_locked(bp, msg, msg_len);
 120         rte_spinlock_unlock(&bp->hwrm_lock);
 121         return rc;
 122 }
 123
 124 #define HWRM_PREP(req, type, cr, resp) \
 125         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 126         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 127         req.cmpl_ring = rte_cpu_to_le_16(cr); \
 128         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 129         req.target_id = rte_cpu_to_le_16(0xffff); \
 130         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr)
 131
 132 #define HWRM_CHECK_RESULT \
 133         { \
 134                 if (rc) { \
 135                         RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
 136                                 __func__, rc); \
 137                         return rc; \
 138                 } \
 139                 if (resp->error_code) { \
 140                         rc = rte_le_to_cpu_16(resp->error_code); \
 141                         RTE_LOG(ERR, PMD, "%s error %d\n", __func__, rc); \
 142                         return rc; \
 143                 } \
 144         }
 145
 146 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 147 {
 148         int rc = 0;
 149         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 150         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 151
 152         HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
 153         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 154         req.mask = 0;
 155
 156         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 157
 158         HWRM_CHECK_RESULT;
 159
 160         return rc;
 161 }
 162
 163 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 164 {
 165         int rc = 0;
 166         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 167         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 168         uint32_t mask = 0;
 169
 170         HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
 171         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 172
 173         /* FIXME add multicast flag, when multicast adding options is supported
 174          * by ethtool.
 175          */
 176         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 177                 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 178         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 179                 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 180         req.mask = rte_cpu_to_le_32(HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST |
 181                                     HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST |
 182                                     mask);
 183
 184         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 185
 186         HWRM_CHECK_RESULT;
 187
 188         return rc;
 189 }
 190
 191 int bnxt_hwrm_clear_filter(struct bnxt *bp,
 192                            struct bnxt_filter_info *filter)
 193 {
 194         int rc = 0;
 195         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 196         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 197
 198         HWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);
 199
 200         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 201
 202         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 203
 204         HWRM_CHECK_RESULT;
 205
 206         filter->fw_l2_filter_id = -1;
 207
 208         return 0;
 209 }
 210
 211 int bnxt_hwrm_set_filter(struct bnxt *bp,
 212                          struct bnxt_vnic_info *vnic,
 213                          struct bnxt_filter_info *filter)
 214 {
 215         int rc = 0;
 216         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 217         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 218         uint32_t enables = 0;
 219
 220         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, -1, resp);
 221
 222         req.flags = rte_cpu_to_le_32(filter->flags);
 223
 224         enables = filter->enables |
 225               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 226         req.dst_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 227
 228         if (enables &
 229             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 230                 memcpy(req.l2_addr, filter->l2_addr,
 231                        ETHER_ADDR_LEN);
 232         if (enables &
 233             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 234                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 235                        ETHER_ADDR_LEN);
 236         if (enables &
 237             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 238                 req.l2_ovlan = filter->l2_ovlan;
 239         if (enables &
 240             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 241                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 242
 243         req.enables = rte_cpu_to_le_32(enables);
 244
 245         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 246
 247         HWRM_CHECK_RESULT;
 248
 249         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 250
 251         return rc;
 252 }
 253
 254 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, void *fwd_cmd)
 255 {
 256         int rc;
 257         struct hwrm_exec_fwd_resp_input req = {.req_type = 0 };
 258         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
 259
 260         HWRM_PREP(req, EXEC_FWD_RESP, -1, resp);
 261
 262         memcpy(req.encap_request, fwd_cmd,
 263                sizeof(req.encap_request));
 264
 265         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 266
 267         HWRM_CHECK_RESULT;
 268
 269         return rc;
 270 }
 271
 272 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 273 {
 274         int rc = 0;
 275         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 276         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 277
 278         HWRM_PREP(req, FUNC_QCAPS, -1, resp);
 279
 280         req.fid = rte_cpu_to_le_16(0xffff);
 281
 282         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 283
 284         HWRM_CHECK_RESULT;
 285
 286         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 287         if (BNXT_PF(bp)) {
 288                 struct bnxt_pf_info *pf = &bp->pf;
 289
 290                 pf->fw_fid = rte_le_to_cpu_32(resp->fid);
 291                 pf->port_id = resp->port_id;
 292                 memcpy(pf->mac_addr, resp->perm_mac_address, ETHER_ADDR_LEN);
 293                 pf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 294                 pf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 295                 pf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 296                 pf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 297                 pf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 298                 pf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 299                 pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 300                 pf->max_vfs = rte_le_to_cpu_16(resp->max_vfs);
 301         } else {
 302                 struct bnxt_vf_info *vf = &bp->vf;
 303
 304                 vf->fw_fid = rte_le_to_cpu_32(resp->fid);
 305                 memcpy(vf->mac_addr, &resp->perm_mac_address, ETHER_ADDR_LEN);
 306                 vf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 307                 vf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 308                 vf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 309                 vf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 310                 vf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 311                 vf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 312         }
 313
 314         return rc;
 315 }
 316
 317 int bnxt_hwrm_func_reset(struct bnxt *bp)
 318 {
 319         int rc = 0;
 320         struct hwrm_func_reset_input req = {.req_type = 0 };
 321         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 322
 323         HWRM_PREP(req, FUNC_RESET, -1, resp);
 324
 325         req.enables = rte_cpu_to_le_32(0);
 326
 327         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 328
 329         HWRM_CHECK_RESULT;
 330
 331         return rc;
 332 }
 333
 334 int bnxt_hwrm_func_driver_register(struct bnxt *bp, uint32_t flags,
 335                                    uint32_t *vf_req_fwd)
 336 {
 337         int rc;
 338         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 339         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 340
 341         if (bp->flags & BNXT_FLAG_REGISTERED)
 342                 return 0;
 343
 344         HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
 345         req.flags = flags;
 346         req.enables = HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER;
 347         req.ver_maj = RTE_VER_YEAR;
 348         req.ver_min = RTE_VER_MONTH;
 349         req.ver_upd = RTE_VER_MINOR;
 350
 351         memcpy(req.vf_req_fwd, vf_req_fwd, sizeof(req.vf_req_fwd));
 352
 353         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 354
 355         HWRM_CHECK_RESULT;
 356
 357         bp->flags |= BNXT_FLAG_REGISTERED;
 358
 359         return rc;
 360 }
 361
 362 int bnxt_hwrm_ver_get(struct bnxt *bp)
 363 {
 364         int rc = 0;
 365         struct hwrm_ver_get_input req = {.req_type = 0 };
 366         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 367         uint32_t my_version;
 368         uint32_t fw_version;
 369         uint16_t max_resp_len;
 370         char type[RTE_MEMZONE_NAMESIZE];
 371
 372         HWRM_PREP(req, VER_GET, -1, resp);
 373
 374         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 375         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 376         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 377
 378         /*
 379          * Hold the lock since we may be adjusting the response pointers.
 380          */
 381         rte_spinlock_lock(&bp->hwrm_lock);
 382         rc = bnxt_hwrm_send_message_locked(bp, &req, sizeof(req));
 383
 384         HWRM_CHECK_RESULT;
 385
 386         RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
 387                 resp->hwrm_intf_maj, resp->hwrm_intf_min,
 388                 resp->hwrm_intf_upd,
 389                 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
 390
 391         my_version = HWRM_VERSION_MAJOR << 16;
 392         my_version |= HWRM_VERSION_MINOR << 8;
 393         my_version |= HWRM_VERSION_UPDATE;
 394
 395         fw_version = resp->hwrm_intf_maj << 16;
 396         fw_version |= resp->hwrm_intf_min << 8;
 397         fw_version |= resp->hwrm_intf_upd;
 398
 399         if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
 400                 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
 401                 rc = -EINVAL;
 402                 goto error;
 403         }
 404
 405         if (my_version != fw_version) {
 406                 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
 407                 if (my_version < fw_version) {
 408                         RTE_LOG(INFO, PMD,
 409                                 "Firmware API version is newer than driver.\n");
 410                         RTE_LOG(INFO, PMD,
 411                                 "The driver may be missing features.\n");
 412                 } else {
 413                         RTE_LOG(INFO, PMD,
 414                                 "Firmware API version is older than driver.\n");
 415                         RTE_LOG(INFO, PMD,
 416                                 "Not all driver features may be functional.\n");
 417                 }
 418         }
 419
 420         if (bp->max_req_len > resp->max_req_win_len) {
 421                 RTE_LOG(ERR, PMD, "Unsupported request length\n");
 422                 rc = -EINVAL;
 423         }
 424         bp->max_req_len = resp->max_req_win_len;
 425         max_resp_len = resp->max_resp_len;
 426         if (bp->max_resp_len != max_resp_len) {
 427                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 428                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 429                         bp->pdev->addr.devid, bp->pdev->addr.function);
 430
 431                 rte_free(bp->hwrm_cmd_resp_addr);
 432
 433                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 434                 if (bp->hwrm_cmd_resp_addr == NULL) {
 435                         rc = -ENOMEM;
 436                         goto error;
 437                 }
 438                 bp->hwrm_cmd_resp_dma_addr =
 439                         rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
 440                 bp->max_resp_len = max_resp_len;
 441         }
 442
 443 error:
 444         rte_spinlock_unlock(&bp->hwrm_lock);
 445         return rc;
 446 }
 447
 448 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 449 {
 450         int rc;
 451         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 452         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 453
 454         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 455                 return 0;
 456
 457         HWRM_PREP(req, FUNC_DRV_UNRGTR, -1, resp);
 458         req.flags = flags;
 459
 460         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 461
 462         HWRM_CHECK_RESULT;
 463
 464         bp->flags &= ~BNXT_FLAG_REGISTERED;
 465
 466         return rc;
 467 }
 468
 469 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 470 {
 471         int rc = 0;
 472         struct hwrm_port_phy_cfg_input req = {.req_type = 0};
 473         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 474
 475         HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
 476
 477         req.flags = conf->phy_flags;
 478         if (conf->link_up) {
 479                 req.force_link_speed = conf->link_speed;
 480                 /*
 481                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 482                  * any auto mode, even "none".
 483                  */
 484                 if (req.auto_mode == HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE) {
 485                         req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
 486                 } else {
 487                         req.auto_mode = conf->auto_mode;
 488                         req.enables |=
 489                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 490                         req.auto_link_speed_mask = conf->auto_link_speed_mask;
 491                         req.enables |=
 492                            HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 493                         req.auto_link_speed = conf->auto_link_speed;
 494                         req.enables |=
 495                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
 496                 }
 497                 req.auto_duplex = conf->duplex;
 498                 req.enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
 499                 req.auto_pause = conf->auto_pause;
 500                 /* Set force_pause if there is no auto or if there is a force */
 501                 if (req.auto_pause)
 502                         req.enables |=
 503                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
 504                 else
 505                         req.enables |=
 506                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 507                 req.force_pause = conf->force_pause;
 508                 if (req.force_pause)
 509                         req.enables |=
 510                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 511         } else {
 512                 req.flags &= ~HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
 513                 req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN;
 514                 req.force_link_speed = 0;
 515         }
 516
 517         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 518
 519         HWRM_CHECK_RESULT;
 520
 521         return rc;
 522 }
 523
 524 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
 525 {
 526         int rc = 0;
 527         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
 528         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
 529
 530         HWRM_PREP(req, QUEUE_QPORTCFG, -1, resp);
 531
 532         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 533
 534         HWRM_CHECK_RESULT;
 535
 536 #define GET_QUEUE_INFO(x) \
 537         bp->cos_queue[x].id = resp->queue_id##x; \
 538         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
 539
 540         GET_QUEUE_INFO(0);
 541         GET_QUEUE_INFO(1);
 542         GET_QUEUE_INFO(2);
 543         GET_QUEUE_INFO(3);
 544         GET_QUEUE_INFO(4);
 545         GET_QUEUE_INFO(5);
 546         GET_QUEUE_INFO(6);
 547         GET_QUEUE_INFO(7);
 548
 549         return rc;
 550 }
 551
 552 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
 553                          struct bnxt_ring *ring,
 554                          uint32_t ring_type, uint32_t map_index,
 555                          uint32_t stats_ctx_id)
 556 {
 557         int rc = 0;
 558         struct hwrm_ring_alloc_input req = {.req_type = 0 };
 559         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 560
 561         HWRM_PREP(req, RING_ALLOC, -1, resp);
 562
 563         req.enables = rte_cpu_to_le_32(0);
 564
 565         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
 566         req.fbo = rte_cpu_to_le_32(0);
 567         /* Association of ring index with doorbell index */
 568         req.logical_id = rte_cpu_to_le_16(map_index);
 569
 570         switch (ring_type) {
 571         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
 572                 req.queue_id = bp->cos_queue[0].id;
 573         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
 574                 req.ring_type = ring_type;
 575                 req.cmpl_ring_id =
 576                     rte_cpu_to_le_16(bp->grp_info[map_index].cp_fw_ring_id);
 577                 req.length = rte_cpu_to_le_32(ring->ring_size);
 578                 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
 579                 req.enables = rte_cpu_to_le_32(rte_le_to_cpu_32(req.enables) |
 580                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID);
 581                 break;
 582         case HWRM_RING_ALLOC_INPUT_RING_TYPE_CMPL:
 583                 req.ring_type = ring_type;
 584                 /*
 585                  * TODO: Some HWRM versions crash with
 586                  * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
 587                  */
 588                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
 589                 req.length = rte_cpu_to_le_32(ring->ring_size);
 590                 break;
 591         default:
 592                 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
 593                         ring_type);
 594                 return -1;
 595         }
 596
 597         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 598
 599         if (rc || resp->error_code) {
 600                 if (rc == 0 && resp->error_code)
 601                         rc = rte_le_to_cpu_16(resp->error_code);
 602                 switch (ring_type) {
 603                 case HWRM_RING_FREE_INPUT_RING_TYPE_CMPL:
 604                         RTE_LOG(ERR, PMD,
 605                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
 606                         return rc;
 607                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 608                         RTE_LOG(ERR, PMD,
 609                                 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
 610                         return rc;
 611                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 612                         RTE_LOG(ERR, PMD,
 613                                 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
 614                         return rc;
 615                 default:
 616                         RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
 617                         return rc;
 618                 }
 619         }
 620
 621         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
 622         return rc;
 623 }
 624
 625 int bnxt_hwrm_ring_free(struct bnxt *bp,
 626                         struct bnxt_ring *ring, uint32_t ring_type)
 627 {
 628         int rc;
 629         struct hwrm_ring_free_input req = {.req_type = 0 };
 630         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
 631
 632         HWRM_PREP(req, RING_FREE, -1, resp);
 633
 634         req.ring_type = ring_type;
 635         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
 636
 637         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 638
 639         if (rc || resp->error_code) {
 640                 if (rc == 0 && resp->error_code)
 641                         rc = rte_le_to_cpu_16(resp->error_code);
 642
 643                 switch (ring_type) {
 644                 case HWRM_RING_FREE_INPUT_RING_TYPE_CMPL:
 645                         RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
 646                                 rc);
 647                         return rc;
 648                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 649                         RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
 650                                 rc);
 651                         return rc;
 652                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 653                         RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
 654                                 rc);
 655                         return rc;
 656                 default:
 657                         RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
 658                         return rc;
 659                 }
 660         }
 661         return 0;
 662 }
 663
 664 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
 665 {
 666         int rc = 0;
 667         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
 668         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 669
 670         HWRM_PREP(req, RING_GRP_ALLOC, -1, resp);
 671
 672         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
 673         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
 674         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
 675         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
 676
 677         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 678
 679         HWRM_CHECK_RESULT;
 680
 681         bp->grp_info[idx].fw_grp_id =
 682             rte_le_to_cpu_16(resp->ring_group_id);
 683
 684         return rc;
 685 }
 686
 687 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
 688 {
 689         int rc;
 690         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
 691         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
 692
 693         HWRM_PREP(req, RING_GRP_FREE, -1, resp);
 694
 695         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
 696
 697         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 698
 699         HWRM_CHECK_RESULT;
 700
 701         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
 702         return rc;
 703 }
 704
 705 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
 706 {
 707         int rc = 0;
 708         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
 709         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
 710
 711         HWRM_PREP(req, STAT_CTX_CLR_STATS, -1, resp);
 712
 713         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
 714                 return rc;
 715
 716         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
 717         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
 718
 719         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 720
 721         HWRM_CHECK_RESULT;
 722
 723         return rc;
 724 }
 725
 726 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp,
 727                              struct bnxt_cp_ring_info *cpr, unsigned int idx)
 728 {
 729         int rc;
 730         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
 731         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 732
 733         HWRM_PREP(req, STAT_CTX_ALLOC, -1, resp);
 734
 735         req.update_period_ms = rte_cpu_to_le_32(1000);
 736
 737         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
 738         req.stats_dma_addr =
 739             rte_cpu_to_le_64(cpr->hw_stats_map);
 740
 741         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 742
 743         HWRM_CHECK_RESULT;
 744
 745         cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
 746         bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
 747
 748         return rc;
 749 }
 750
 751 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp,
 752                             struct bnxt_cp_ring_info *cpr, unsigned int idx)
 753 {
 754         int rc;
 755         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
 756         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
 757
 758         HWRM_PREP(req, STAT_CTX_FREE, -1, resp);
 759
 760         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
 761         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
 762
 763         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 764
 765         HWRM_CHECK_RESULT;
 766
 767         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
 768         bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
 769
 770         return rc;
 771 }
 772
 773 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 774 {
 775         int rc = 0, i, j;
 776         struct hwrm_vnic_alloc_input req = {.req_type = 0 };
 777         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 778
 779         /* map ring groups to this vnic */
 780         for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++) {
 781                 if (bp->grp_info[i].fw_grp_id == (uint16_t)HWRM_NA_SIGNATURE) {
 782                         RTE_LOG(ERR, PMD,
 783                                 "Not enough ring groups avail:%x req:%x\n", j,
 784                                 (vnic->end_grp_id - vnic->start_grp_id) + 1);
 785                         break;
 786                 }
 787                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
 788         }
 789
 790         vnic->fw_rss_cos_lb_ctx = (uint16_t)HWRM_NA_SIGNATURE;
 791         vnic->ctx_is_rss_cos_lb = HW_CONTEXT_NONE;
 792
 793         HWRM_PREP(req, VNIC_ALLOC, -1, resp);
 794
 795         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 796
 797         HWRM_CHECK_RESULT;
 798
 799         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
 800         return rc;
 801 }
 802
 803 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 804 {
 805         int rc = 0;
 806         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
 807         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 808
 809         HWRM_PREP(req, VNIC_CFG, -1, resp);
 810
 811         /* Only RSS support for now TBD: COS & LB */
 812         req.enables =
 813             rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP |
 814                              HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE |
 815                              HWRM_VNIC_CFG_INPUT_ENABLES_MRU);
 816         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 817         req.dflt_ring_grp =
 818                 rte_cpu_to_le_16(bp->grp_info[vnic->start_grp_id].fw_grp_id);
 819         req.rss_rule = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
 820         req.cos_rule = rte_cpu_to_le_16(0xffff);
 821         req.lb_rule = rte_cpu_to_le_16(0xffff);
 822         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
 823                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
 824         if (vnic->func_default)
 825                 req.flags = 1;
 826         if (vnic->vlan_strip)
 827                 req.flags |=
 828                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
 829
 830         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 831
 832         HWRM_CHECK_RESULT;
 833
 834         return rc;
 835 }
 836
 837 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 838 {
 839         int rc = 0;
 840         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
 841         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
 842                                                 bp->hwrm_cmd_resp_addr;
 843
 844         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, -1, resp);
 845
 846         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 847
 848         HWRM_CHECK_RESULT;
 849
 850         vnic->fw_rss_cos_lb_ctx = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
 851
 852         return rc;
 853 }
 854
 855 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 856 {
 857         int rc = 0;
 858         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
 859         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
 860                                                 bp->hwrm_cmd_resp_addr;
 861
 862         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, -1, resp);
 863
 864         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
 865
 866         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 867
 868         HWRM_CHECK_RESULT;
 869
 870         vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
 871
 872         return rc;
 873 }
 874
 875 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 876 {
 877         int rc = 0;
 878         struct hwrm_vnic_free_input req = {.req_type = 0 };
 879         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
 880
 881         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 882                 return rc;
 883
 884         HWRM_PREP(req, VNIC_FREE, -1, resp);
 885
 886         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 887
 888         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 889
 890         HWRM_CHECK_RESULT;
 891
 892         vnic->fw_vnic_id = INVALID_HW_RING_ID;
 893         return rc;
 894 }
 895
 896 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
 897                            struct bnxt_vnic_info *vnic)
 898 {
 899         int rc = 0;
 900         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
 901         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 902
 903         HWRM_PREP(req, VNIC_RSS_CFG, -1, resp);
 904
 905         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
 906
 907         req.ring_grp_tbl_addr =
 908             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
 909         req.hash_key_tbl_addr =
 910             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
 911         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
 912
 913         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 914
 915         HWRM_CHECK_RESULT;
 916
 917         return rc;
 918 }
 919
 920 /*
 921  * HWRM utility functions
 922  */
 923
 924 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
 925 {
 926         unsigned int i;
 927         int rc = 0;
 928
 929         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
 930                 struct bnxt_tx_queue *txq;
 931                 struct bnxt_rx_queue *rxq;
 932                 struct bnxt_cp_ring_info *cpr;
 933
 934                 if (i >= bp->rx_cp_nr_rings) {
 935                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
 936                         cpr = txq->cp_ring;
 937                 } else {
 938                         rxq = bp->rx_queues[i];
 939                         cpr = rxq->cp_ring;
 940                 }
 941
 942                 rc = bnxt_hwrm_stat_clear(bp, cpr);
 943                 if (rc)
 944                         return rc;
 945         }
 946         return 0;
 947 }
 948
 949 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
 950 {
 951         int rc;
 952         unsigned int i;
 953         struct bnxt_cp_ring_info *cpr;
 954
 955         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
 956                 unsigned int idx = i + 1;
 957
 958                 if (i >= bp->rx_cp_nr_rings)
 959                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
 960                 else
 961                         cpr = bp->rx_queues[i]->cp_ring;
 962                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
 963                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, idx);
 964                         if (rc)
 965                                 return rc;
 966                 }
 967         }
 968         return 0;
 969 }
 970
 971 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
 972 {
 973         unsigned int i;
 974         int rc = 0;
 975
 976         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
 977                 struct bnxt_tx_queue *txq;
 978                 struct bnxt_rx_queue *rxq;
 979                 struct bnxt_cp_ring_info *cpr;
 980                 unsigned int idx = i + 1;
 981
 982                 if (i >= bp->rx_cp_nr_rings) {
 983                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
 984                         cpr = txq->cp_ring;
 985                 } else {
 986                         rxq = bp->rx_queues[i];
 987                         cpr = rxq->cp_ring;
 988                 }
 989
 990                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, idx);
 991
 992                 if (rc)
 993                         return rc;
 994         }
 995         return rc;
 996 }
 997
 998 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
 999 {
1000         uint16_t i;
1001         uint32_t rc = 0;
1002
1003         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1004                 unsigned int idx = i + 1;
1005
1006                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID) {
1007                         RTE_LOG(ERR, PMD,
1008                                 "Attempt to free invalid ring group %d\n",
1009                                 idx);
1010                         continue;
1011                 }
1012
1013                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1014
1015                 if (rc)
1016                         return rc;
1017         }
1018         return rc;
1019 }
1020
1021 static void bnxt_free_cp_ring(struct bnxt *bp,
1022                               struct bnxt_cp_ring_info *cpr, unsigned int idx)
1023 {
1024         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1025
1026         bnxt_hwrm_ring_free(bp, cp_ring,
1027                         HWRM_RING_FREE_INPUT_RING_TYPE_CMPL);
1028         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1029         bp->grp_info[idx].cp_fw_ring_id = INVALID_HW_RING_ID;
1030         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1031                         sizeof(*cpr->cp_desc_ring));
1032         cpr->cp_raw_cons = 0;
1033 }
1034
1035 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1036 {
1037         unsigned int i;
1038         int rc = 0;
1039
1040         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1041                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1042                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1043                 struct bnxt_ring *ring = txr->tx_ring_struct;
1044                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1045                 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1046
1047                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1048                         bnxt_hwrm_ring_free(bp, ring,
1049                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1050                         ring->fw_ring_id = INVALID_HW_RING_ID;
1051                         memset(txr->tx_desc_ring, 0,
1052                                         txr->tx_ring_struct->ring_size *
1053                                         sizeof(*txr->tx_desc_ring));
1054                         memset(txr->tx_buf_ring, 0,
1055                                         txr->tx_ring_struct->ring_size *
1056                                         sizeof(*txr->tx_buf_ring));
1057                         txr->tx_prod = 0;
1058                         txr->tx_cons = 0;
1059                 }
1060                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
1061                         bnxt_free_cp_ring(bp, cpr, idx);
1062         }
1063
1064         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1065                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1066                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1067                 struct bnxt_ring *ring = rxr->rx_ring_struct;
1068                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1069                 unsigned int idx = i + 1;
1070
1071                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1072                         bnxt_hwrm_ring_free(bp, ring,
1073                                         HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1074                         ring->fw_ring_id = INVALID_HW_RING_ID;
1075                         bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1076                         memset(rxr->rx_desc_ring, 0,
1077                                         rxr->rx_ring_struct->ring_size *
1078                                         sizeof(*rxr->rx_desc_ring));
1079                         memset(rxr->rx_buf_ring, 0,
1080                                         rxr->rx_ring_struct->ring_size *
1081                                         sizeof(*rxr->rx_buf_ring));
1082                         rxr->rx_prod = 0;
1083                 }
1084                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
1085                         bnxt_free_cp_ring(bp, cpr, idx);
1086         }
1087
1088         /* Default completion ring */
1089         {
1090                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1091
1092                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
1093                         bnxt_free_cp_ring(bp, cpr, 0);
1094         }
1095
1096         return rc;
1097 }
1098
1099 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1100 {
1101         uint16_t i;
1102         uint32_t rc = 0;
1103
1104         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1105                 unsigned int idx = i + 1;
1106
1107                 if (bp->grp_info[idx].cp_fw_ring_id == INVALID_HW_RING_ID ||
1108                     bp->grp_info[idx].rx_fw_ring_id == INVALID_HW_RING_ID)
1109                         continue;
1110
1111                 rc = bnxt_hwrm_ring_grp_alloc(bp, idx);
1112
1113                 if (rc)
1114                         return rc;
1115         }
1116         return rc;
1117 }
1118
1119 void bnxt_free_hwrm_resources(struct bnxt *bp)
1120 {
1121         /* Release memzone */
1122         rte_free(bp->hwrm_cmd_resp_addr);
1123         bp->hwrm_cmd_resp_addr = NULL;
1124         bp->hwrm_cmd_resp_dma_addr = 0;
1125 }
1126
1127 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1128 {
1129         struct rte_pci_device *pdev = bp->pdev;
1130         char type[RTE_MEMZONE_NAMESIZE];
1131
1132         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1133                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1134         bp->max_req_len = HWRM_MAX_REQ_LEN;
1135         bp->max_resp_len = HWRM_MAX_RESP_LEN;
1136         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1137         if (bp->hwrm_cmd_resp_addr == NULL)
1138                 return -ENOMEM;
1139         bp->hwrm_cmd_resp_dma_addr =
1140                 rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
1141         rte_spinlock_init(&bp->hwrm_lock);
1142
1143         return 0;
1144 }
1145
1146 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1147 {
1148         struct bnxt_filter_info *filter;
1149         int rc = 0;
1150
1151         STAILQ_FOREACH(filter, &vnic->filter, next) {
1152                 rc = bnxt_hwrm_clear_filter(bp, filter);
1153                 if (rc)
1154                         break;
1155         }
1156         return rc;
1157 }
1158
1159 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1160 {
1161         struct bnxt_filter_info *filter;
1162         int rc = 0;
1163
1164         STAILQ_FOREACH(filter, &vnic->filter, next) {
1165                 rc = bnxt_hwrm_set_filter(bp, vnic, filter);
1166                 if (rc)
1167                         break;
1168         }
1169         return rc;
1170 }
1171
1172 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1173 {
1174         struct bnxt_vnic_info *vnic;
1175         unsigned int i;
1176
1177         if (bp->vnic_info == NULL)
1178                 return;
1179
1180         vnic = &bp->vnic_info[0];
1181         bnxt_hwrm_cfa_l2_clear_rx_mask(bp, vnic);
1182
1183         /* VNIC resources */
1184         for (i = 0; i < bp->nr_vnics; i++) {
1185                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1186
1187                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1188
1189                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1190                 bnxt_hwrm_vnic_free(bp, vnic);
1191         }
1192         /* Ring resources */
1193         bnxt_free_all_hwrm_rings(bp);
1194         bnxt_free_all_hwrm_ring_grps(bp);
1195         bnxt_free_all_hwrm_stat_ctxs(bp);
1196 }
1197
1198 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1199 {
1200         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1201
1202         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1203                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1204
1205         switch (conf_link_speed) {
1206         case ETH_LINK_SPEED_10M_HD:
1207         case ETH_LINK_SPEED_100M_HD:
1208                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1209         }
1210         return hw_link_duplex;
1211 }
1212
1213 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1214 {
1215         uint16_t eth_link_speed = 0;
1216
1217         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1218                 return ETH_LINK_SPEED_AUTONEG;
1219
1220         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1221         case ETH_LINK_SPEED_100M:
1222         case ETH_LINK_SPEED_100M_HD:
1223                 eth_link_speed =
1224                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB;
1225                 break;
1226         case ETH_LINK_SPEED_1G:
1227                 eth_link_speed =
1228                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1229                 break;
1230         case ETH_LINK_SPEED_2_5G:
1231                 eth_link_speed =
1232                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1233                 break;
1234         case ETH_LINK_SPEED_10G:
1235                 eth_link_speed =
1236                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1237                 break;
1238         case ETH_LINK_SPEED_20G:
1239                 eth_link_speed =
1240                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1241                 break;
1242         case ETH_LINK_SPEED_25G:
1243                 eth_link_speed =
1244                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
1245                 break;
1246         case ETH_LINK_SPEED_40G:
1247                 eth_link_speed =
1248                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
1249                 break;
1250         case ETH_LINK_SPEED_50G:
1251                 eth_link_speed =
1252                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
1253                 break;
1254         default:
1255                 RTE_LOG(ERR, PMD,
1256                         "Unsupported link speed %d; default to AUTO\n",
1257                         conf_link_speed);
1258                 break;
1259         }
1260         return eth_link_speed;
1261 }
1262
1263 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1264                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1265                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1266                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1267
1268 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
1269 {
1270         uint32_t one_speed;
1271
1272         if (link_speed == ETH_LINK_SPEED_AUTONEG)
1273                 return 0;
1274
1275         if (link_speed & ETH_LINK_SPEED_FIXED) {
1276                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1277
1278                 if (one_speed & (one_speed - 1)) {
1279                         RTE_LOG(ERR, PMD,
1280                                 "Invalid advertised speeds (%u) for port %u\n",
1281                                 link_speed, port_id);
1282                         return -EINVAL;
1283                 }
1284                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1285                         RTE_LOG(ERR, PMD,
1286                                 "Unsupported advertised speed (%u) for port %u\n",
1287                                 link_speed, port_id);
1288                         return -EINVAL;
1289                 }
1290         } else {
1291                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1292                         RTE_LOG(ERR, PMD,
1293                                 "Unsupported advertised speeds (%u) for port %u\n",
1294                                 link_speed, port_id);
1295                         return -EINVAL;
1296                 }
1297         }
1298         return 0;
1299 }
1300
1301 static uint16_t bnxt_parse_eth_link_speed_mask(uint32_t link_speed)
1302 {
1303         uint16_t ret = 0;
1304
1305         if (link_speed == ETH_LINK_SPEED_AUTONEG)
1306                 link_speed = BNXT_SUPPORTED_SPEEDS;
1307
1308         if (link_speed & ETH_LINK_SPEED_100M)
1309                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1310         if (link_speed & ETH_LINK_SPEED_100M_HD)
1311                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1312         if (link_speed & ETH_LINK_SPEED_1G)
1313                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1314         if (link_speed & ETH_LINK_SPEED_2_5G)
1315                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1316         if (link_speed & ETH_LINK_SPEED_10G)
1317                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1318         if (link_speed & ETH_LINK_SPEED_20G)
1319                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1320         if (link_speed & ETH_LINK_SPEED_25G)
1321                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
1322         if (link_speed & ETH_LINK_SPEED_40G)
1323                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
1324         if (link_speed & ETH_LINK_SPEED_50G)
1325                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
1326         return ret;
1327 }
1328
1329 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
1330 {
1331         int rc = 0;
1332         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1333         struct bnxt_link_info link_req;
1334         uint16_t speed;
1335
1336         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
1337                         bp->eth_dev->data->port_id);
1338         if (rc)
1339                 goto error;
1340
1341         memset(&link_req, 0, sizeof(link_req));
1342         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
1343         link_req.link_up = link_up;
1344         if (speed == 0) {
1345                 link_req.phy_flags =
1346                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
1347                 link_req.auto_mode =
1348                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW;
1349                 link_req.auto_link_speed_mask =
1350                         bnxt_parse_eth_link_speed_mask(dev_conf->link_speeds);
1351                 link_req.auto_link_speed =
1352                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB;
1353         } else {
1354                 link_req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1355                 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE |
1356                         HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
1357                 link_req.link_speed = speed;
1358         }
1359         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
1360         link_req.auto_pause = bp->link_info.auto_pause;
1361         link_req.force_pause = bp->link_info.force_pause;
1362
1363         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
1364         if (rc) {
1365                 RTE_LOG(ERR, PMD,
1366                         "Set link config failed with rc %d\n", rc);
1367         }
1368
1369 error:
1370         return rc;
1371 }