drivers/net/bnxt/bnxt_hwrm.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <unistd.h>
  35
  36 #include <unistd.h>
  37
  38 #include <rte_byteorder.h>
  39 #include <rte_common.h>
  40 #include <rte_cycles.h>
  41 #include <rte_malloc.h>
  42 #include <rte_memzone.h>
  43 #include <rte_version.h>
  44
  45 #include "bnxt.h"
  46 #include "bnxt_cpr.h"
  47 #include "bnxt_filter.h"
  48 #include "bnxt_hwrm.h"
  49 #include "bnxt_rxq.h"
  50 #include "bnxt_rxr.h"
  51 #include "bnxt_ring.h"
  52 #include "bnxt_txq.h"
  53 #include "bnxt_txr.h"
  54 #include "bnxt_vnic.h"
  55 #include "hsi_struct_def_dpdk.h"
  56
  57 #include <rte_io.h>
  58
  59 #define HWRM_CMD_TIMEOUT                2000
  60
  61 struct bnxt_plcmodes_cfg {
  62         uint32_t        flags;
  63         uint16_t        jumbo_thresh;
  64         uint16_t        hds_offset;
  65         uint16_t        hds_threshold;
  66 };
  67
  68 static int page_getenum(size_t size)
  69 {
  70         if (size <= 1 << 4)
  71                 return 4;
  72         if (size <= 1 << 12)
  73                 return 12;
  74         if (size <= 1 << 13)
  75                 return 13;
  76         if (size <= 1 << 16)
  77                 return 16;
  78         if (size <= 1 << 21)
  79                 return 21;
  80         if (size <= 1 << 22)
  81                 return 22;
  82         if (size <= 1 << 30)
  83                 return 30;
  84         RTE_LOG(ERR, PMD, "Page size %zu out of range\n", size);
  85         return sizeof(void *) * 8 - 1;
  86 }
  87
  88 static int page_roundup(size_t size)
  89 {
  90         return 1 << page_getenum(size);
  91 }
  92
  93 /*
  94  * HWRM Functions (sent to HWRM)
  95  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  96  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  97  * command was failed by the ChiMP.
  98  */
  99
 100 static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
 101                                         uint32_t msg_len)
 102 {
 103         unsigned int i;
 104         struct input *req = msg;
 105         struct output *resp = bp->hwrm_cmd_resp_addr;
 106         uint32_t *data = msg;
 107         uint8_t *bar;
 108         uint8_t *valid;
 109         uint16_t max_req_len = bp->max_req_len;
 110         struct hwrm_short_input short_input = { 0 };
 111
 112         if (bp->flags & BNXT_FLAG_SHORT_CMD) {
 113                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 114
 115                 memset(short_cmd_req, 0, bp->max_req_len);
 116                 memcpy(short_cmd_req, req, msg_len);
 117
 118                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 119                 short_input.signature = rte_cpu_to_le_16(
 120                                         HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
 121                 short_input.size = rte_cpu_to_le_16(msg_len);
 122                 short_input.req_addr =
 123                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 124
 125                 data = (uint32_t *)&short_input;
 126                 msg_len = sizeof(short_input);
 127
 128                 /* Sync memory write before updating doorbell */
 129                 rte_wmb();
 130
 131                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 132         }
 133
 134         /* Write request msg to hwrm channel */
 135         for (i = 0; i < msg_len; i += 4) {
 136                 bar = (uint8_t *)bp->bar0 + i;
 137                 rte_write32(*data, bar);
 138                 data++;
 139         }
 140
 141         /* Zero the rest of the request space */
 142         for (; i < max_req_len; i += 4) {
 143                 bar = (uint8_t *)bp->bar0 + i;
 144                 rte_write32(0, bar);
 145         }
 146
 147         /* Ring channel doorbell */
 148         bar = (uint8_t *)bp->bar0 + 0x100;
 149         rte_write32(1, bar);
 150
 151         /* Poll for the valid bit */
 152         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 153                 /* Sanity check on the resp->resp_len */
 154                 rte_rmb();
 155                 if (resp->resp_len && resp->resp_len <=
 156                                 bp->max_resp_len) {
 157                         /* Last byte of resp contains the valid key */
 158                         valid = (uint8_t *)resp + resp->resp_len - 1;
 159                         if (*valid == HWRM_RESP_VALID_KEY)
 160                                 break;
 161                 }
 162                 rte_delay_us(600);
 163         }
 164
 165         if (i >= HWRM_CMD_TIMEOUT) {
 166                 RTE_LOG(ERR, PMD, "Error sending msg 0x%04x\n",
 167                         req->req_type);
 168                 goto err_ret;
 169         }
 170         return 0;
 171
 172 err_ret:
 173         return -1;
 174 }
 175
 176 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)
 177 {
 178         int rc;
 179
 180         rte_spinlock_lock(&bp->hwrm_lock);
 181         rc = bnxt_hwrm_send_message_locked(bp, msg, msg_len);
 182         rte_spinlock_unlock(&bp->hwrm_lock);
 183         return rc;
 184 }
 185
 186 #define HWRM_PREP(req, type, cr, resp) \
 187         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 188         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 189         req.cmpl_ring = rte_cpu_to_le_16(cr); \
 190         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 191         req.target_id = rte_cpu_to_le_16(0xffff); \
 192         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr)
 193
 194 #define HWRM_CHECK_RESULT \
 195         { \
 196                 if (rc) { \
 197                         RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
 198                                 __func__, rc); \
 199                         return rc; \
 200                 } \
 201                 if (resp->error_code) { \
 202                         rc = rte_le_to_cpu_16(resp->error_code); \
 203                         if (resp->resp_len >= 16) { \
 204                                 struct hwrm_err_output *tmp_hwrm_err_op = \
 205                                                         (void *)resp; \
 206                                 RTE_LOG(ERR, PMD, \
 207                                         "%s error %d:%d:%08x:%04x\n", \
 208                                         __func__, \
 209                                         rc, tmp_hwrm_err_op->cmd_err, \
 210                                         rte_le_to_cpu_32(\
 211                                                 tmp_hwrm_err_op->opaque_0), \
 212                                         rte_le_to_cpu_16(\
 213                                                 tmp_hwrm_err_op->opaque_1)); \
 214                         } \
 215                         else { \
 216                                 RTE_LOG(ERR, PMD, \
 217                                         "%s error %d\n", __func__, rc); \
 218                         } \
 219                         return rc; \
 220                 } \
 221         }
 222
 223 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 224 {
 225         int rc = 0;
 226         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 227         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 228
 229         HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
 230         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 231         req.mask = 0;
 232
 233         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 234
 235         HWRM_CHECK_RESULT;
 236
 237         return rc;
 238 }
 239
 240 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 241                                  struct bnxt_vnic_info *vnic,
 242                                  uint16_t vlan_count,
 243                                  struct bnxt_vlan_table_entry *vlan_table)
 244 {
 245         int rc = 0;
 246         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 247         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 248         uint32_t mask = 0;
 249
 250         HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
 251         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 252
 253         /* FIXME add multicast flag, when multicast adding options is supported
 254          * by ethtool.
 255          */
 256         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 257                 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 258         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 259                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 260         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 261                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 262         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 263                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 264         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 265                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 266         if (vnic->mc_addr_cnt) {
 267                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 268                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 269                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 270         }
 271         if (vlan_count && vlan_table) {
 272                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 273                 req.vlan_tag_tbl_addr = rte_cpu_to_le_16(
 274                          rte_mem_virt2phy(vlan_table));
 275                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 276         }
 277         req.mask = rte_cpu_to_le_32(HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST |
 278                                     mask);
 279
 280         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 281
 282         HWRM_CHECK_RESULT;
 283
 284         return rc;
 285 }
 286
 287 int bnxt_hwrm_clear_filter(struct bnxt *bp,
 288                            struct bnxt_filter_info *filter)
 289 {
 290         int rc = 0;
 291         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 292         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 293
 294         HWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);
 295
 296         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 297
 298         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 299
 300         HWRM_CHECK_RESULT;
 301
 302         filter->fw_l2_filter_id = -1;
 303
 304         return 0;
 305 }
 306
 307 int bnxt_hwrm_set_filter(struct bnxt *bp,
 308                          uint16_t dst_id,
 309                          struct bnxt_filter_info *filter)
 310 {
 311         int rc = 0;
 312         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 313         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 314         uint32_t enables = 0;
 315
 316         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, -1, resp);
 317
 318         req.flags = rte_cpu_to_le_32(filter->flags);
 319
 320         enables = filter->enables |
 321               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 322         req.dst_id = rte_cpu_to_le_16(dst_id);
 323
 324         if (enables &
 325             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 326                 memcpy(req.l2_addr, filter->l2_addr,
 327                        ETHER_ADDR_LEN);
 328         if (enables &
 329             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 330                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 331                        ETHER_ADDR_LEN);
 332         if (enables &
 333             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 334                 req.l2_ovlan = filter->l2_ovlan;
 335         if (enables &
 336             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 337                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 338         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 339                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 340         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 341                 req.src_type = filter->src_type;
 342
 343         req.enables = rte_cpu_to_le_32(enables);
 344
 345         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 346
 347         HWRM_CHECK_RESULT;
 348
 349         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 350
 351         return rc;
 352 }
 353
 354 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 355 {
 356         int rc = 0;
 357         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 358         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 359         uint16_t new_max_vfs;
 360         int i;
 361
 362         HWRM_PREP(req, FUNC_QCAPS, -1, resp);
 363
 364         req.fid = rte_cpu_to_le_16(0xffff);
 365
 366         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 367
 368         HWRM_CHECK_RESULT;
 369
 370         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 371         if (BNXT_PF(bp)) {
 372                 bp->pf.port_id = resp->port_id;
 373                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 374                 new_max_vfs = bp->pdev->max_vfs;
 375                 if (new_max_vfs != bp->pf.max_vfs) {
 376                         if (bp->pf.vf_info)
 377                                 rte_free(bp->pf.vf_info);
 378                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 379                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 380                         bp->pf.max_vfs = new_max_vfs;
 381                         for (i = 0; i < new_max_vfs; i++) {
 382                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 383                                 bp->pf.vf_info[i].vlan_table =
 384                                         rte_zmalloc("VF VLAN table",
 385                                                     getpagesize(),
 386                                                     getpagesize());
 387                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 388                                         RTE_LOG(ERR, PMD,
 389                                         "Fail to alloc VLAN table for VF %d\n",
 390                                         i);
 391                                 else
 392                                         rte_mem_lock_page(
 393                                                 bp->pf.vf_info[i].vlan_table);
 394                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 395                         }
 396                 }
 397         }
 398
 399         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 400         memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
 401         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 402         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 403         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 404         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 405         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 406         /* TODO: For now, do not support VMDq/RFS on VFs. */
 407         if (BNXT_PF(bp)) {
 408                 if (bp->pf.max_vfs)
 409                         bp->max_vnics = 1;
 410                 else
 411                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 412         } else {
 413                 bp->max_vnics = 1;
 414         }
 415         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 416         if (BNXT_PF(bp))
 417                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 418
 419         return rc;
 420 }
 421
 422 int bnxt_hwrm_func_reset(struct bnxt *bp)
 423 {
 424         int rc = 0;
 425         struct hwrm_func_reset_input req = {.req_type = 0 };
 426         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 427
 428         HWRM_PREP(req, FUNC_RESET, -1, resp);
 429
 430         req.enables = rte_cpu_to_le_32(0);
 431
 432         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 433
 434         HWRM_CHECK_RESULT;
 435
 436         return rc;
 437 }
 438
 439 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 440 {
 441         int rc;
 442         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 443         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 444
 445         if (bp->flags & BNXT_FLAG_REGISTERED)
 446                 return 0;
 447
 448         HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
 449         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 450                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 451         req.ver_maj = RTE_VER_YEAR;
 452         req.ver_min = RTE_VER_MONTH;
 453         req.ver_upd = RTE_VER_MINOR;
 454
 455         if (BNXT_PF(bp)) {
 456                 req.enables |= rte_cpu_to_le_32(
 457                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
 458                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 459                        RTE_MIN(sizeof(req.vf_req_fwd),
 460                                sizeof(bp->pf.vf_req_fwd)));
 461         }
 462
 463         req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1);   /* TODO: Use MACRO */
 464         memset(req.async_event_fwd, 0xff, sizeof(req.async_event_fwd));
 465
 466         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 467
 468         HWRM_CHECK_RESULT;
 469
 470         bp->flags |= BNXT_FLAG_REGISTERED;
 471
 472         return rc;
 473 }
 474
 475 int bnxt_hwrm_ver_get(struct bnxt *bp)
 476 {
 477         int rc = 0;
 478         struct hwrm_ver_get_input req = {.req_type = 0 };
 479         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 480         uint32_t my_version;
 481         uint32_t fw_version;
 482         uint16_t max_resp_len;
 483         char type[RTE_MEMZONE_NAMESIZE];
 484         uint32_t dev_caps_cfg;
 485
 486         bp->max_req_len = HWRM_MAX_REQ_LEN;
 487         HWRM_PREP(req, VER_GET, -1, resp);
 488
 489         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 490         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 491         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 492
 493         /*
 494          * Hold the lock since we may be adjusting the response pointers.
 495          */
 496         rte_spinlock_lock(&bp->hwrm_lock);
 497         rc = bnxt_hwrm_send_message_locked(bp, &req, sizeof(req));
 498
 499         HWRM_CHECK_RESULT;
 500
 501         RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
 502                 resp->hwrm_intf_maj, resp->hwrm_intf_min,
 503                 resp->hwrm_intf_upd,
 504                 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
 505         bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
 506                         (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
 507         RTE_LOG(INFO, PMD, "Driver HWRM version: %d.%d.%d\n",
 508                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 509
 510         my_version = HWRM_VERSION_MAJOR << 16;
 511         my_version |= HWRM_VERSION_MINOR << 8;
 512         my_version |= HWRM_VERSION_UPDATE;
 513
 514         fw_version = resp->hwrm_intf_maj << 16;
 515         fw_version |= resp->hwrm_intf_min << 8;
 516         fw_version |= resp->hwrm_intf_upd;
 517
 518         if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
 519                 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
 520                 rc = -EINVAL;
 521                 goto error;
 522         }
 523
 524         if (my_version != fw_version) {
 525                 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
 526                 if (my_version < fw_version) {
 527                         RTE_LOG(INFO, PMD,
 528                                 "Firmware API version is newer than driver.\n");
 529                         RTE_LOG(INFO, PMD,
 530                                 "The driver may be missing features.\n");
 531                 } else {
 532                         RTE_LOG(INFO, PMD,
 533                                 "Firmware API version is older than driver.\n");
 534                         RTE_LOG(INFO, PMD,
 535                                 "Not all driver features may be functional.\n");
 536                 }
 537         }
 538
 539         if (bp->max_req_len > resp->max_req_win_len) {
 540                 RTE_LOG(ERR, PMD, "Unsupported request length\n");
 541                 rc = -EINVAL;
 542         }
 543         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 544         max_resp_len = resp->max_resp_len;
 545         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 546
 547         if (bp->max_resp_len != max_resp_len) {
 548                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 549                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 550                         bp->pdev->addr.devid, bp->pdev->addr.function);
 551
 552                 rte_free(bp->hwrm_cmd_resp_addr);
 553
 554                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 555                 if (bp->hwrm_cmd_resp_addr == NULL) {
 556                         rc = -ENOMEM;
 557                         goto error;
 558                 }
 559                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 560                 bp->hwrm_cmd_resp_dma_addr =
 561                         rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
 562                 if (bp->hwrm_cmd_resp_dma_addr == 0) {
 563                         RTE_LOG(ERR, PMD,
 564                         "Unable to map response buffer to physical memory.\n");
 565                         rc = -ENOMEM;
 566                         goto error;
 567                 }
 568                 bp->max_resp_len = max_resp_len;
 569         }
 570
 571         if ((dev_caps_cfg &
 572                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 573             (dev_caps_cfg &
 574              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
 575                 RTE_LOG(DEBUG, PMD, "Short command supported\n");
 576
 577                 rte_free(bp->hwrm_short_cmd_req_addr);
 578
 579                 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
 580                                                         bp->max_req_len, 0);
 581                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 582                         rc = -ENOMEM;
 583                         goto error;
 584                 }
 585                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 586                 bp->hwrm_short_cmd_req_dma_addr =
 587                         rte_mem_virt2phy(bp->hwrm_short_cmd_req_addr);
 588                 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
 589                         rte_free(bp->hwrm_short_cmd_req_addr);
 590                         RTE_LOG(ERR, PMD,
 591                                 "Unable to map buffer to physical memory.\n");
 592                         rc = -ENOMEM;
 593                         goto error;
 594                 }
 595
 596                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 597         }
 598
 599 error:
 600         rte_spinlock_unlock(&bp->hwrm_lock);
 601         return rc;
 602 }
 603
 604 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 605 {
 606         int rc;
 607         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 608         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 609
 610         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 611                 return 0;
 612
 613         HWRM_PREP(req, FUNC_DRV_UNRGTR, -1, resp);
 614         req.flags = flags;
 615
 616         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 617
 618         HWRM_CHECK_RESULT;
 619
 620         bp->flags &= ~BNXT_FLAG_REGISTERED;
 621
 622         return rc;
 623 }
 624
 625 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 626 {
 627         int rc = 0;
 628         struct hwrm_port_phy_cfg_input req = {0};
 629         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 630         uint32_t enables = 0;
 631         uint32_t link_speed_mask =
 632                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 633
 634         HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
 635
 636         if (conf->link_up) {
 637                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 638                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 639                 /*
 640                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 641                  * any auto mode, even "none".
 642                  */
 643                 if (!conf->link_speed) {
 644                         req.auto_mode = conf->auto_mode;
 645                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 646                         if (conf->auto_mode ==
 647                             HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK) {
 648                                 req.auto_link_speed_mask =
 649                                         conf->auto_link_speed_mask;
 650                                 enables |= link_speed_mask;
 651                         }
 652                         if (bp->link_info.auto_link_speed) {
 653                                 req.auto_link_speed =
 654                                         bp->link_info.auto_link_speed;
 655                                 enables |=
 656                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
 657                         }
 658                 }
 659                 req.auto_duplex = conf->duplex;
 660                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
 661                 req.auto_pause = conf->auto_pause;
 662                 req.force_pause = conf->force_pause;
 663                 /* Set force_pause if there is no auto or if there is a force */
 664                 if (req.auto_pause && !req.force_pause)
 665                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
 666                 else
 667                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 668
 669                 req.enables = rte_cpu_to_le_32(enables);
 670         } else {
 671                 req.flags =
 672                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
 673                 RTE_LOG(INFO, PMD, "Force Link Down\n");
 674         }
 675
 676         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 677
 678         HWRM_CHECK_RESULT;
 679
 680         return rc;
 681 }
 682
 683 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
 684                                    struct bnxt_link_info *link_info)
 685 {
 686         int rc = 0;
 687         struct hwrm_port_phy_qcfg_input req = {0};
 688         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 689
 690         HWRM_PREP(req, PORT_PHY_QCFG, -1, resp);
 691
 692         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 693
 694         HWRM_CHECK_RESULT;
 695
 696         link_info->phy_link_status = resp->link;
 697         link_info->link_up =
 698                 (link_info->phy_link_status ==
 699                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
 700         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
 701         link_info->duplex = resp->duplex;
 702         link_info->pause = resp->pause;
 703         link_info->auto_pause = resp->auto_pause;
 704         link_info->force_pause = resp->force_pause;
 705         link_info->auto_mode = resp->auto_mode;
 706
 707         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
 708         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
 709         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
 710         link_info->phy_ver[0] = resp->phy_maj;
 711         link_info->phy_ver[1] = resp->phy_min;
 712         link_info->phy_ver[2] = resp->phy_bld;
 713
 714         return rc;
 715 }
 716
 717 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
 718 {
 719         int rc = 0;
 720         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
 721         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
 722
 723         HWRM_PREP(req, QUEUE_QPORTCFG, -1, resp);
 724
 725         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 726
 727         HWRM_CHECK_RESULT;
 728
 729 #define GET_QUEUE_INFO(x) \
 730         bp->cos_queue[x].id = resp->queue_id##x; \
 731         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
 732
 733         GET_QUEUE_INFO(0);
 734         GET_QUEUE_INFO(1);
 735         GET_QUEUE_INFO(2);
 736         GET_QUEUE_INFO(3);
 737         GET_QUEUE_INFO(4);
 738         GET_QUEUE_INFO(5);
 739         GET_QUEUE_INFO(6);
 740         GET_QUEUE_INFO(7);
 741
 742         return rc;
 743 }
 744
 745 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
 746                          struct bnxt_ring *ring,
 747                          uint32_t ring_type, uint32_t map_index,
 748                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
 749 {
 750         int rc = 0;
 751         uint32_t enables = 0;
 752         struct hwrm_ring_alloc_input req = {.req_type = 0 };
 753         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 754
 755         HWRM_PREP(req, RING_ALLOC, -1, resp);
 756
 757         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
 758         req.fbo = rte_cpu_to_le_32(0);
 759         /* Association of ring index with doorbell index */
 760         req.logical_id = rte_cpu_to_le_16(map_index);
 761         req.length = rte_cpu_to_le_32(ring->ring_size);
 762
 763         switch (ring_type) {
 764         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
 765                 req.queue_id = bp->cos_queue[0].id;
 766                 /* FALLTHROUGH */
 767         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
 768                 req.ring_type = ring_type;
 769                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
 770                 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
 771                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
 772                         enables |=
 773                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
 774                 break;
 775         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
 776                 req.ring_type = ring_type;
 777                 /*
 778                  * TODO: Some HWRM versions crash with
 779                  * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
 780                  */
 781                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
 782                 break;
 783         default:
 784                 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
 785                         ring_type);
 786                 return -1;
 787         }
 788         req.enables = rte_cpu_to_le_32(enables);
 789
 790         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 791
 792         if (rc || resp->error_code) {
 793                 if (rc == 0 && resp->error_code)
 794                         rc = rte_le_to_cpu_16(resp->error_code);
 795                 switch (ring_type) {
 796                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 797                         RTE_LOG(ERR, PMD,
 798                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
 799                         return rc;
 800                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 801                         RTE_LOG(ERR, PMD,
 802                                 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
 803                         return rc;
 804                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 805                         RTE_LOG(ERR, PMD,
 806                                 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
 807                         return rc;
 808                 default:
 809                         RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
 810                         return rc;
 811                 }
 812         }
 813
 814         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
 815         return rc;
 816 }
 817
 818 int bnxt_hwrm_ring_free(struct bnxt *bp,
 819                         struct bnxt_ring *ring, uint32_t ring_type)
 820 {
 821         int rc;
 822         struct hwrm_ring_free_input req = {.req_type = 0 };
 823         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
 824
 825         HWRM_PREP(req, RING_FREE, -1, resp);
 826
 827         req.ring_type = ring_type;
 828         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
 829
 830         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 831
 832         if (rc || resp->error_code) {
 833                 if (rc == 0 && resp->error_code)
 834                         rc = rte_le_to_cpu_16(resp->error_code);
 835
 836                 switch (ring_type) {
 837                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 838                         RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
 839                                 rc);
 840                         return rc;
 841                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 842                         RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
 843                                 rc);
 844                         return rc;
 845                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 846                         RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
 847                                 rc);
 848                         return rc;
 849                 default:
 850                         RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
 851                         return rc;
 852                 }
 853         }
 854         return 0;
 855 }
 856
 857 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
 858 {
 859         int rc = 0;
 860         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
 861         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 862
 863         HWRM_PREP(req, RING_GRP_ALLOC, -1, resp);
 864
 865         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
 866         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
 867         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
 868         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
 869
 870         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 871
 872         HWRM_CHECK_RESULT;
 873
 874         bp->grp_info[idx].fw_grp_id =
 875             rte_le_to_cpu_16(resp->ring_group_id);
 876
 877         return rc;
 878 }
 879
 880 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
 881 {
 882         int rc;
 883         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
 884         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
 885
 886         HWRM_PREP(req, RING_GRP_FREE, -1, resp);
 887
 888         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
 889
 890         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 891
 892         HWRM_CHECK_RESULT;
 893
 894         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
 895         return rc;
 896 }
 897
 898 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
 899 {
 900         int rc = 0;
 901         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
 902         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
 903
 904         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
 905                 return rc;
 906
 907         HWRM_PREP(req, STAT_CTX_CLR_STATS, -1, resp);
 908
 909         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
 910
 911         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 912
 913         HWRM_CHECK_RESULT;
 914
 915         return rc;
 916 }
 917
 918 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 919                                 unsigned int idx __rte_unused)
 920 {
 921         int rc;
 922         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
 923         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 924
 925         HWRM_PREP(req, STAT_CTX_ALLOC, -1, resp);
 926
 927         req.update_period_ms = rte_cpu_to_le_32(0);
 928
 929         req.stats_dma_addr =
 930             rte_cpu_to_le_64(cpr->hw_stats_map);
 931
 932         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 933
 934         HWRM_CHECK_RESULT;
 935
 936         cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
 937
 938         return rc;
 939 }
 940
 941 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 942                                 unsigned int idx __rte_unused)
 943 {
 944         int rc;
 945         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
 946         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
 947
 948         HWRM_PREP(req, STAT_CTX_FREE, -1, resp);
 949
 950         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
 951
 952         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 953
 954         HWRM_CHECK_RESULT;
 955
 956         return rc;
 957 }
 958
 959 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 960 {
 961         int rc = 0, i, j;
 962         struct hwrm_vnic_alloc_input req = { 0 };
 963         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 964
 965         /* map ring groups to this vnic */
 966         RTE_LOG(DEBUG, PMD, "Alloc VNIC. Start %x, End %x\n",
 967                 vnic->start_grp_id, vnic->end_grp_id);
 968         for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
 969                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
 970         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
 971         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
 972         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
 973         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
 974         vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
 975                                 ETHER_CRC_LEN + VLAN_TAG_SIZE;
 976         HWRM_PREP(req, VNIC_ALLOC, -1, resp);
 977
 978         if (vnic->func_default)
 979                 req.flags = HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT;
 980         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 981
 982         HWRM_CHECK_RESULT;
 983
 984         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
 985         return rc;
 986 }
 987
 988 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
 989                                         struct bnxt_vnic_info *vnic,
 990                                         struct bnxt_plcmodes_cfg *pmode)
 991 {
 992         int rc = 0;
 993         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
 994         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 995
 996         HWRM_PREP(req, VNIC_PLCMODES_QCFG, -1, resp);
 997
 998         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
 999
1000         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1001
1002         HWRM_CHECK_RESULT;
1003
1004         pmode->flags = rte_le_to_cpu_32(resp->flags);
1005         /* dflt_vnic bit doesn't exist in the _cfg command */
1006         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1007         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1008         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1009         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1010
1011         return rc;
1012 }
1013
1014 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1015                                        struct bnxt_vnic_info *vnic,
1016                                        struct bnxt_plcmodes_cfg *pmode)
1017 {
1018         int rc = 0;
1019         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1020         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1021
1022         HWRM_PREP(req, VNIC_PLCMODES_CFG, -1, resp);
1023
1024         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1025         req.flags = rte_cpu_to_le_32(pmode->flags);
1026         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1027         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1028         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1029         req.enables = rte_cpu_to_le_32(
1030             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1031             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1032             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1033         );
1034
1035         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1036
1037         HWRM_CHECK_RESULT;
1038
1039         return rc;
1040 }
1041
1042 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1043 {
1044         int rc = 0;
1045         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1046         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1047         uint32_t ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1048         struct bnxt_plcmodes_cfg pmodes;
1049
1050         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1051         if (rc)
1052                 return rc;
1053
1054         HWRM_PREP(req, VNIC_CFG, -1, resp);
1055
1056         /* Only RSS support for now TBD: COS & LB */
1057         req.enables =
1058             rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP |
1059                              HWRM_VNIC_CFG_INPUT_ENABLES_MRU);
1060         if (vnic->lb_rule != 0xffff)
1061                 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1062         if (vnic->cos_rule != 0xffff)
1063                 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1064         if (vnic->rss_rule != 0xffff)
1065                 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1066         req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1067         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1068         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1069         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1070         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1071         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1072         req.mru = rte_cpu_to_le_16(vnic->mru);
1073         if (vnic->func_default)
1074                 req.flags |=
1075                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1076         if (vnic->vlan_strip)
1077                 req.flags |=
1078                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1079         if (vnic->bd_stall)
1080                 req.flags |=
1081                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1082         if (vnic->roce_dual)
1083                 req.flags |= rte_cpu_to_le_32(
1084                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1085         if (vnic->roce_only)
1086                 req.flags |= rte_cpu_to_le_32(
1087                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1088         if (vnic->rss_dflt_cr)
1089                 req.flags |= rte_cpu_to_le_32(
1090                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1091
1092         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1093
1094         HWRM_CHECK_RESULT;
1095
1096         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1097
1098         return rc;
1099 }
1100
1101 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1102                 int16_t fw_vf_id)
1103 {
1104         int rc = 0;
1105         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1106         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1107
1108         HWRM_PREP(req, VNIC_QCFG, -1, resp);
1109
1110         req.enables =
1111                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1112         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1113         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1114
1115         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1116
1117         HWRM_CHECK_RESULT;
1118
1119         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1120         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1121         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1122         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1123         vnic->mru = rte_le_to_cpu_16(resp->mru);
1124         vnic->func_default = rte_le_to_cpu_32(
1125                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1126         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1127                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1128         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1129                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1130         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1131                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1132         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1133                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1134         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1135                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1136
1137         return rc;
1138 }
1139
1140 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1141 {
1142         int rc = 0;
1143         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1144         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1145                                                 bp->hwrm_cmd_resp_addr;
1146
1147         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, -1, resp);
1148
1149         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1150
1151         HWRM_CHECK_RESULT;
1152
1153         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1154
1155         return rc;
1156 }
1157
1158 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1159 {
1160         int rc = 0;
1161         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1162         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1163                                                 bp->hwrm_cmd_resp_addr;
1164
1165         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, -1, resp);
1166
1167         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1168
1169         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1170
1171         HWRM_CHECK_RESULT;
1172
1173         vnic->rss_rule = INVALID_HW_RING_ID;
1174
1175         return rc;
1176 }
1177
1178 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1179 {
1180         int rc = 0;
1181         struct hwrm_vnic_free_input req = {.req_type = 0 };
1182         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1183
1184         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
1185                 return rc;
1186
1187         HWRM_PREP(req, VNIC_FREE, -1, resp);
1188
1189         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1190
1191         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1192
1193         HWRM_CHECK_RESULT;
1194
1195         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1196         return rc;
1197 }
1198
1199 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1200                            struct bnxt_vnic_info *vnic)
1201 {
1202         int rc = 0;
1203         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1204         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1205
1206         HWRM_PREP(req, VNIC_RSS_CFG, -1, resp);
1207
1208         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1209
1210         req.ring_grp_tbl_addr =
1211             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1212         req.hash_key_tbl_addr =
1213             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1214         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1215
1216         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1217
1218         HWRM_CHECK_RESULT;
1219
1220         return rc;
1221 }
1222
1223 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1224                         struct bnxt_vnic_info *vnic)
1225 {
1226         int rc = 0;
1227         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1228         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1229         uint16_t size;
1230
1231         HWRM_PREP(req, VNIC_PLCMODES_CFG, -1, resp);
1232
1233         req.flags = rte_cpu_to_le_32(
1234                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1235
1236         req.enables = rte_cpu_to_le_32(
1237                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1238
1239         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1240         size -= RTE_PKTMBUF_HEADROOM;
1241
1242         req.jumbo_thresh = rte_cpu_to_le_16(size);
1243         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1244
1245         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1246
1247         HWRM_CHECK_RESULT;
1248
1249         return rc;
1250 }
1251
1252 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1253                         struct bnxt_vnic_info *vnic, bool enable)
1254 {
1255         int rc = 0;
1256         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1257         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1258
1259         HWRM_PREP(req, VNIC_TPA_CFG, -1, resp);
1260
1261         if (enable) {
1262                 req.enables = rte_cpu_to_le_32(
1263                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1264                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1265                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1266                 req.flags = rte_cpu_to_le_32(
1267                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1268                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1269                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1270                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1271                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1272                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1273                 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1274                 req.max_agg_segs = rte_cpu_to_le_16(5);
1275                 req.max_aggs =
1276                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1277                 req.min_agg_len = rte_cpu_to_le_32(512);
1278         }
1279
1280         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1281
1282         HWRM_CHECK_RESULT;
1283
1284         return rc;
1285 }
1286
1287 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1288 {
1289         struct hwrm_func_cfg_input req = {0};
1290         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1291         int rc;
1292
1293         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1294         req.enables = rte_cpu_to_le_32(
1295                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1296         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1297         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1298
1299         HWRM_PREP(req, FUNC_CFG, -1, resp);
1300
1301         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1302         HWRM_CHECK_RESULT;
1303
1304         bp->pf.vf_info[vf].random_mac = false;
1305
1306         return rc;
1307 }
1308
1309 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1310                                   uint64_t *dropped)
1311 {
1312         int rc = 0;
1313         struct hwrm_func_qstats_input req = {.req_type = 0};
1314         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1315
1316         HWRM_PREP(req, FUNC_QSTATS, -1, resp);
1317
1318         req.fid = rte_cpu_to_le_16(fid);
1319
1320         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1321
1322         HWRM_CHECK_RESULT;
1323
1324         if (dropped)
1325                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1326
1327         return rc;
1328 }
1329
1330 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1331                           struct rte_eth_stats *stats)
1332 {
1333         int rc = 0;
1334         struct hwrm_func_qstats_input req = {.req_type = 0};
1335         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1336
1337         HWRM_PREP(req, FUNC_QSTATS, -1, resp);
1338
1339         req.fid = rte_cpu_to_le_16(fid);
1340
1341         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1342
1343         HWRM_CHECK_RESULT;
1344
1345         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1346         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1347         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1348         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1349         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1350         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1351
1352         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1353         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1354         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1355         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1356         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1357         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1358
1359         stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1360         stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1361
1362         stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1363
1364         return rc;
1365 }
1366
1367 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1368 {
1369         int rc = 0;
1370         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1371         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1372
1373         HWRM_PREP(req, FUNC_CLR_STATS, -1, resp);
1374
1375         req.fid = rte_cpu_to_le_16(fid);
1376
1377         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1378
1379         HWRM_CHECK_RESULT;
1380
1381         return rc;
1382 }
1383
1384 /*
1385  * HWRM utility functions
1386  */
1387
1388 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1389 {
1390         unsigned int i;
1391         int rc = 0;
1392
1393         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1394                 struct bnxt_tx_queue *txq;
1395                 struct bnxt_rx_queue *rxq;
1396                 struct bnxt_cp_ring_info *cpr;
1397
1398                 if (i >= bp->rx_cp_nr_rings) {
1399                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1400                         cpr = txq->cp_ring;
1401                 } else {
1402                         rxq = bp->rx_queues[i];
1403                         cpr = rxq->cp_ring;
1404                 }
1405
1406                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1407                 if (rc)
1408                         return rc;
1409         }
1410         return 0;
1411 }
1412
1413 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1414 {
1415         int rc;
1416         unsigned int i;
1417         struct bnxt_cp_ring_info *cpr;
1418
1419         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1420
1421                 if (i >= bp->rx_cp_nr_rings)
1422                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1423                 else
1424                         cpr = bp->rx_queues[i]->cp_ring;
1425                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1426                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1427                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1428                         /*
1429                          * TODO. Need a better way to reset grp_info.stats_ctx
1430                          * for Rx rings only. stats_ctx is not saved for Tx
1431                          * in grp_info.
1432                          */
1433                         bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
1434                         if (rc)
1435                                 return rc;
1436                 }
1437         }
1438         return 0;
1439 }
1440
1441 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1442 {
1443         unsigned int i;
1444         int rc = 0;
1445
1446         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1447                 struct bnxt_tx_queue *txq;
1448                 struct bnxt_rx_queue *rxq;
1449                 struct bnxt_cp_ring_info *cpr;
1450
1451                 if (i >= bp->rx_cp_nr_rings) {
1452                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1453                         cpr = txq->cp_ring;
1454                 } else {
1455                         rxq = bp->rx_queues[i];
1456                         cpr = rxq->cp_ring;
1457                 }
1458
1459                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1460
1461                 if (rc)
1462                         return rc;
1463         }
1464         return rc;
1465 }
1466
1467 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1468 {
1469         uint16_t idx;
1470         uint32_t rc = 0;
1471
1472         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1473
1474                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID) {
1475                         RTE_LOG(ERR, PMD,
1476                                 "Attempt to free invalid ring group %d\n",
1477                                 idx);
1478                         continue;
1479                 }
1480
1481                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1482
1483                 if (rc)
1484                         return rc;
1485         }
1486         return rc;
1487 }
1488
1489 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1490                                 unsigned int idx __rte_unused)
1491 {
1492         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1493
1494         bnxt_hwrm_ring_free(bp, cp_ring,
1495                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1496         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1497         bp->grp_info[idx].cp_fw_ring_id = INVALID_HW_RING_ID;
1498         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1499                         sizeof(*cpr->cp_desc_ring));
1500         cpr->cp_raw_cons = 0;
1501 }
1502
1503 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1504 {
1505         unsigned int i;
1506         int rc = 0;
1507
1508         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1509                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1510                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1511                 struct bnxt_ring *ring = txr->tx_ring_struct;
1512                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1513                 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1514
1515                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1516                         bnxt_hwrm_ring_free(bp, ring,
1517                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1518                         ring->fw_ring_id = INVALID_HW_RING_ID;
1519                         memset(txr->tx_desc_ring, 0,
1520                                         txr->tx_ring_struct->ring_size *
1521                                         sizeof(*txr->tx_desc_ring));
1522                         memset(txr->tx_buf_ring, 0,
1523                                         txr->tx_ring_struct->ring_size *
1524                                         sizeof(*txr->tx_buf_ring));
1525                         txr->tx_prod = 0;
1526                         txr->tx_cons = 0;
1527                 }
1528                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1529                         bnxt_free_cp_ring(bp, cpr, idx);
1530                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1531                 }
1532         }
1533
1534         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1535                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1536                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1537                 struct bnxt_ring *ring = rxr->rx_ring_struct;
1538                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1539                 unsigned int idx = i + 1;
1540
1541                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1542                         bnxt_hwrm_ring_free(bp, ring,
1543                                         HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1544                         ring->fw_ring_id = INVALID_HW_RING_ID;
1545                         bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1546                         memset(rxr->rx_desc_ring, 0,
1547                                         rxr->rx_ring_struct->ring_size *
1548                                         sizeof(*rxr->rx_desc_ring));
1549                         memset(rxr->rx_buf_ring, 0,
1550                                         rxr->rx_ring_struct->ring_size *
1551                                         sizeof(*rxr->rx_buf_ring));
1552                         rxr->rx_prod = 0;
1553                         memset(rxr->ag_buf_ring, 0,
1554                                         rxr->ag_ring_struct->ring_size *
1555                                         sizeof(*rxr->ag_buf_ring));
1556                         rxr->ag_prod = 0;
1557                 }
1558                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1559                         bnxt_free_cp_ring(bp, cpr, idx);
1560                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1561                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1562                 }
1563         }
1564
1565         /* Default completion ring */
1566         {
1567                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1568
1569                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1570                         bnxt_free_cp_ring(bp, cpr, 0);
1571                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1572                 }
1573         }
1574
1575         return rc;
1576 }
1577
1578 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1579 {
1580         uint16_t i;
1581         uint32_t rc = 0;
1582
1583         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1584                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1585                 if (rc)
1586                         return rc;
1587         }
1588         return rc;
1589 }
1590
1591 void bnxt_free_hwrm_resources(struct bnxt *bp)
1592 {
1593         /* Release memzone */
1594         rte_free(bp->hwrm_cmd_resp_addr);
1595         rte_free(bp->hwrm_short_cmd_req_addr);
1596         bp->hwrm_cmd_resp_addr = NULL;
1597         bp->hwrm_short_cmd_req_addr = NULL;
1598         bp->hwrm_cmd_resp_dma_addr = 0;
1599         bp->hwrm_short_cmd_req_dma_addr = 0;
1600 }
1601
1602 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1603 {
1604         struct rte_pci_device *pdev = bp->pdev;
1605         char type[RTE_MEMZONE_NAMESIZE];
1606
1607         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1608                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1609         bp->max_resp_len = HWRM_MAX_RESP_LEN;
1610         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1611         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1612         if (bp->hwrm_cmd_resp_addr == NULL)
1613                 return -ENOMEM;
1614         bp->hwrm_cmd_resp_dma_addr =
1615                 rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
1616         if (bp->hwrm_cmd_resp_dma_addr == 0) {
1617                 RTE_LOG(ERR, PMD,
1618                         "unable to map response address to physical memory\n");
1619                 return -ENOMEM;
1620         }
1621         rte_spinlock_init(&bp->hwrm_lock);
1622
1623         return 0;
1624 }
1625
1626 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1627 {
1628         struct bnxt_filter_info *filter;
1629         int rc = 0;
1630
1631         STAILQ_FOREACH(filter, &vnic->filter, next) {
1632                 rc = bnxt_hwrm_clear_filter(bp, filter);
1633                 if (rc)
1634                         break;
1635         }
1636         return rc;
1637 }
1638
1639 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1640 {
1641         struct bnxt_filter_info *filter;
1642         int rc = 0;
1643
1644         STAILQ_FOREACH(filter, &vnic->filter, next) {
1645                 rc = bnxt_hwrm_set_filter(bp, vnic->fw_vnic_id, filter);
1646                 if (rc)
1647                         break;
1648         }
1649         return rc;
1650 }
1651
1652 void bnxt_free_tunnel_ports(struct bnxt *bp)
1653 {
1654         if (bp->vxlan_port_cnt)
1655                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1656                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1657         bp->vxlan_port = 0;
1658         if (bp->geneve_port_cnt)
1659                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1660                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1661         bp->geneve_port = 0;
1662 }
1663
1664 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1665 {
1666         struct bnxt_vnic_info *vnic;
1667         unsigned int i;
1668
1669         if (bp->vnic_info == NULL)
1670                 return;
1671
1672         vnic = &bp->vnic_info[0];
1673         if (BNXT_PF(bp))
1674                 bnxt_hwrm_cfa_l2_clear_rx_mask(bp, vnic);
1675
1676         /* VNIC resources */
1677         for (i = 0; i < bp->nr_vnics; i++) {
1678                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1679
1680                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1681
1682                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1683
1684                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1685
1686                 bnxt_hwrm_vnic_free(bp, vnic);
1687         }
1688         /* Ring resources */
1689         bnxt_free_all_hwrm_rings(bp);
1690         bnxt_free_all_hwrm_ring_grps(bp);
1691         bnxt_free_all_hwrm_stat_ctxs(bp);
1692         bnxt_free_tunnel_ports(bp);
1693 }
1694
1695 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1696 {
1697         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1698
1699         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1700                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1701
1702         switch (conf_link_speed) {
1703         case ETH_LINK_SPEED_10M_HD:
1704         case ETH_LINK_SPEED_100M_HD:
1705                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1706         }
1707         return hw_link_duplex;
1708 }
1709
1710 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1711 {
1712         uint16_t eth_link_speed = 0;
1713
1714         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1715                 return ETH_LINK_SPEED_AUTONEG;
1716
1717         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1718         case ETH_LINK_SPEED_100M:
1719         case ETH_LINK_SPEED_100M_HD:
1720                 eth_link_speed =
1721                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1722                 break;
1723         case ETH_LINK_SPEED_1G:
1724                 eth_link_speed =
1725                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1726                 break;
1727         case ETH_LINK_SPEED_2_5G:
1728                 eth_link_speed =
1729                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1730                 break;
1731         case ETH_LINK_SPEED_10G:
1732                 eth_link_speed =
1733                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
1734                 break;
1735         case ETH_LINK_SPEED_20G:
1736                 eth_link_speed =
1737                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
1738                 break;
1739         case ETH_LINK_SPEED_25G:
1740                 eth_link_speed =
1741                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
1742                 break;
1743         case ETH_LINK_SPEED_40G:
1744                 eth_link_speed =
1745                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
1746                 break;
1747         case ETH_LINK_SPEED_50G:
1748                 eth_link_speed =
1749                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
1750                 break;
1751         default:
1752                 RTE_LOG(ERR, PMD,
1753                         "Unsupported link speed %d; default to AUTO\n",
1754                         conf_link_speed);
1755                 break;
1756         }
1757         return eth_link_speed;
1758 }
1759
1760 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1761                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1762                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1763                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1764
1765 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
1766 {
1767         uint32_t one_speed;
1768
1769         if (link_speed == ETH_LINK_SPEED_AUTONEG)
1770                 return 0;
1771
1772         if (link_speed & ETH_LINK_SPEED_FIXED) {
1773                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1774
1775                 if (one_speed & (one_speed - 1)) {
1776                         RTE_LOG(ERR, PMD,
1777                                 "Invalid advertised speeds (%u) for port %u\n",
1778                                 link_speed, port_id);
1779                         return -EINVAL;
1780                 }
1781                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1782                         RTE_LOG(ERR, PMD,
1783                                 "Unsupported advertised speed (%u) for port %u\n",
1784                                 link_speed, port_id);
1785                         return -EINVAL;
1786                 }
1787         } else {
1788                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1789                         RTE_LOG(ERR, PMD,
1790                                 "Unsupported advertised speeds (%u) for port %u\n",
1791                                 link_speed, port_id);
1792                         return -EINVAL;
1793                 }
1794         }
1795         return 0;
1796 }
1797
1798 static uint16_t
1799 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
1800 {
1801         uint16_t ret = 0;
1802
1803         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
1804                 if (bp->link_info.support_speeds)
1805                         return bp->link_info.support_speeds;
1806                 link_speed = BNXT_SUPPORTED_SPEEDS;
1807         }
1808
1809         if (link_speed & ETH_LINK_SPEED_100M)
1810                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1811         if (link_speed & ETH_LINK_SPEED_100M_HD)
1812                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1813         if (link_speed & ETH_LINK_SPEED_1G)
1814                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1815         if (link_speed & ETH_LINK_SPEED_2_5G)
1816                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1817         if (link_speed & ETH_LINK_SPEED_10G)
1818                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1819         if (link_speed & ETH_LINK_SPEED_20G)
1820                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1821         if (link_speed & ETH_LINK_SPEED_25G)
1822                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
1823         if (link_speed & ETH_LINK_SPEED_40G)
1824                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
1825         if (link_speed & ETH_LINK_SPEED_50G)
1826                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
1827         return ret;
1828 }
1829
1830 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
1831 {
1832         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
1833
1834         switch (hw_link_speed) {
1835         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
1836                 eth_link_speed = ETH_SPEED_NUM_100M;
1837                 break;
1838         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
1839                 eth_link_speed = ETH_SPEED_NUM_1G;
1840                 break;
1841         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
1842                 eth_link_speed = ETH_SPEED_NUM_2_5G;
1843                 break;
1844         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
1845                 eth_link_speed = ETH_SPEED_NUM_10G;
1846                 break;
1847         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
1848                 eth_link_speed = ETH_SPEED_NUM_20G;
1849                 break;
1850         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
1851                 eth_link_speed = ETH_SPEED_NUM_25G;
1852                 break;
1853         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
1854                 eth_link_speed = ETH_SPEED_NUM_40G;
1855                 break;
1856         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
1857                 eth_link_speed = ETH_SPEED_NUM_50G;
1858                 break;
1859         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
1860         default:
1861                 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
1862                         hw_link_speed);
1863                 break;
1864         }
1865         return eth_link_speed;
1866 }
1867
1868 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
1869 {
1870         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1871
1872         switch (hw_link_duplex) {
1873         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
1874         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
1875                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1876                 break;
1877         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
1878                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
1879                 break;
1880         default:
1881                 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
1882                         hw_link_duplex);
1883                 break;
1884         }
1885         return eth_link_duplex;
1886 }
1887
1888 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
1889 {
1890         int rc = 0;
1891         struct bnxt_link_info *link_info = &bp->link_info;
1892
1893         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
1894         if (rc) {
1895                 RTE_LOG(ERR, PMD,
1896                         "Get link config failed with rc %d\n", rc);
1897                 goto exit;
1898         }
1899         if (link_info->link_speed)
1900                 link->link_speed =
1901                         bnxt_parse_hw_link_speed(link_info->link_speed);
1902         else
1903                 link->link_speed = ETH_SPEED_NUM_NONE;
1904         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
1905         link->link_status = link_info->link_up;
1906         link->link_autoneg = link_info->auto_mode ==
1907                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
1908                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
1909 exit:
1910         return rc;
1911 }
1912
1913 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
1914 {
1915         int rc = 0;
1916         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1917         struct bnxt_link_info link_req;
1918         uint16_t speed;
1919
1920         if (BNXT_NPAR_PF(bp) || BNXT_VF(bp))
1921                 return 0;
1922
1923         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
1924                         bp->eth_dev->data->port_id);
1925         if (rc)
1926                 goto error;
1927
1928         memset(&link_req, 0, sizeof(link_req));
1929         link_req.link_up = link_up;
1930         if (!link_up)
1931                 goto port_phy_cfg;
1932
1933         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
1934         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
1935         if (speed == 0) {
1936                 link_req.phy_flags |=
1937                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
1938                 link_req.auto_mode =
1939                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1940                 link_req.auto_link_speed_mask =
1941                         bnxt_parse_eth_link_speed_mask(bp,
1942                                                        dev_conf->link_speeds);
1943         } else {
1944                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
1945                 link_req.link_speed = speed;
1946                 RTE_LOG(INFO, PMD, "Set Link Speed %x\n", speed);
1947         }
1948         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
1949         link_req.auto_pause = bp->link_info.auto_pause;
1950         link_req.force_pause = bp->link_info.force_pause;
1951
1952 port_phy_cfg:
1953         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
1954         if (rc) {
1955                 RTE_LOG(ERR, PMD,
1956                         "Set link config failed with rc %d\n", rc);
1957         }
1958
1959         rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1960 error:
1961         return rc;
1962 }
1963
1964 /* JIRA 22088 */
1965 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
1966 {
1967         struct hwrm_func_qcfg_input req = {0};
1968         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1969         int rc = 0;
1970
1971         HWRM_PREP(req, FUNC_QCFG, -1, resp);
1972         req.fid = rte_cpu_to_le_16(0xffff);
1973
1974         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1975
1976         HWRM_CHECK_RESULT;
1977
1978         /* Hard Coded.. 0xfff VLAN ID mask */
1979         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
1980
1981         switch (resp->port_partition_type) {
1982         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
1983         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
1984         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
1985                 bp->port_partition_type = resp->port_partition_type;
1986                 break;
1987         default:
1988                 bp->port_partition_type = 0;
1989                 break;
1990         }
1991
1992         return rc;
1993 }
1994
1995 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
1996                                    struct hwrm_func_qcaps_output *qcaps)
1997 {
1998         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
1999         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2000                sizeof(qcaps->mac_address));
2001         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2002         qcaps->max_rx_rings = fcfg->num_rx_rings;
2003         qcaps->max_tx_rings = fcfg->num_tx_rings;
2004         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2005         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2006         qcaps->max_vfs = 0;
2007         qcaps->first_vf_id = 0;
2008         qcaps->max_vnics = fcfg->num_vnics;
2009         qcaps->max_decap_records = 0;
2010         qcaps->max_encap_records = 0;
2011         qcaps->max_tx_wm_flows = 0;
2012         qcaps->max_tx_em_flows = 0;
2013         qcaps->max_rx_wm_flows = 0;
2014         qcaps->max_rx_em_flows = 0;
2015         qcaps->max_flow_id = 0;
2016         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2017         qcaps->max_sp_tx_rings = 0;
2018         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2019 }
2020
2021 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2022 {
2023         struct hwrm_func_cfg_input req = {0};
2024         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2025         int rc;
2026
2027         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2028                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2029                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2030                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2031                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2032                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2033                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2034                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2035                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2036                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2037         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2038         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2039         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2040                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
2041         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2042         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2043         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2044         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2045         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2046         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2047         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2048         req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2049         req.fid = rte_cpu_to_le_16(0xffff);
2050
2051         HWRM_PREP(req, FUNC_CFG, -1, resp);
2052
2053         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2054         HWRM_CHECK_RESULT;
2055
2056         return rc;
2057 }
2058
2059 static void populate_vf_func_cfg_req(struct bnxt *bp,
2060                                      struct hwrm_func_cfg_input *req,
2061                                      int num_vfs)
2062 {
2063         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2064                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2065                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2066                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2067                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2068                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2069                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2070                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2071                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2072                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2073
2074         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2075                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2076         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2077                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2078         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2079                                                 (num_vfs + 1));
2080         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2081         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2082                                                (num_vfs + 1));
2083         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2084         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2085         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2086         /* TODO: For now, do not support VMDq/RFS on VFs. */
2087         req->num_vnics = rte_cpu_to_le_16(1);
2088         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2089                                                  (num_vfs + 1));
2090 }
2091
2092 static void add_random_mac_if_needed(struct bnxt *bp,
2093                                      struct hwrm_func_cfg_input *cfg_req,
2094                                      int vf)
2095 {
2096         struct ether_addr mac;
2097
2098         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2099                 return;
2100
2101         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2102                 cfg_req->enables |=
2103                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2104                 eth_random_addr(cfg_req->dflt_mac_addr);
2105                 bp->pf.vf_info[vf].random_mac = true;
2106         } else {
2107                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2108         }
2109 }
2110
2111 static void reserve_resources_from_vf(struct bnxt *bp,
2112                                       struct hwrm_func_cfg_input *cfg_req,
2113                                       int vf)
2114 {
2115         struct hwrm_func_qcaps_input req = {0};
2116         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2117         int rc;
2118
2119         /* Get the actual allocated values now */
2120         HWRM_PREP(req, FUNC_QCAPS, -1, resp);
2121         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2122         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2123
2124         if (rc) {
2125                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps failed rc:%d\n", rc);
2126                 copy_func_cfg_to_qcaps(cfg_req, resp);
2127         } else if (resp->error_code) {
2128                 rc = rte_le_to_cpu_16(resp->error_code);
2129                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps error %d\n", rc);
2130                 copy_func_cfg_to_qcaps(cfg_req, resp);
2131         }
2132
2133         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2134         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2135         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2136         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2137         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2138         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2139         /*
2140          * TODO: While not supporting VMDq with VFs, max_vnics is always
2141          * forced to 1 in this case
2142          */
2143         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2144         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2145 }
2146
2147 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2148 {
2149         struct hwrm_func_qcfg_input req = {0};
2150         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2151         int rc;
2152
2153         /* Check for zero MAC address */
2154         HWRM_PREP(req, FUNC_QCFG, -1, resp);
2155         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2156         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2157         if (rc) {
2158                 RTE_LOG(ERR, PMD, "hwrm_func_qcfg failed rc:%d\n", rc);
2159                 return -1;
2160         } else if (resp->error_code) {
2161                 rc = rte_le_to_cpu_16(resp->error_code);
2162                 RTE_LOG(ERR, PMD, "hwrm_func_qcfg error %d\n", rc);
2163                 return -1;
2164         }
2165         return rte_le_to_cpu_16(resp->vlan);
2166 }
2167
2168 static int update_pf_resource_max(struct bnxt *bp)
2169 {
2170         struct hwrm_func_qcfg_input req = {0};
2171         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2172         int rc;
2173
2174         /* And copy the allocated numbers into the pf struct */
2175         HWRM_PREP(req, FUNC_QCFG, -1, resp);
2176         req.fid = rte_cpu_to_le_16(0xffff);
2177         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2178         HWRM_CHECK_RESULT;
2179
2180         /* Only TX ring value reflects actual allocation? TODO */
2181         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2182         bp->pf.evb_mode = resp->evb_mode;
2183
2184         return rc;
2185 }
2186
2187 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2188 {
2189         int rc;
2190
2191         if (!BNXT_PF(bp)) {
2192                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2193                 return -1;
2194         }
2195
2196         rc = bnxt_hwrm_func_qcaps(bp);
2197         if (rc)
2198                 return rc;
2199
2200         bp->pf.func_cfg_flags &=
2201                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2202                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2203         bp->pf.func_cfg_flags |=
2204                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2205         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2206         return rc;
2207 }
2208
2209 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2210 {
2211         struct hwrm_func_cfg_input req = {0};
2212         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2213         int i;
2214         size_t sz;
2215         int rc = 0;
2216         size_t req_buf_sz;
2217
2218         if (!BNXT_PF(bp)) {
2219                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2220                 return -1;
2221         }
2222
2223         rc = bnxt_hwrm_func_qcaps(bp);
2224
2225         if (rc)
2226                 return rc;
2227
2228         bp->pf.active_vfs = num_vfs;
2229
2230         /*
2231          * First, configure the PF to only use one TX ring.  This ensures that
2232          * there are enough rings for all VFs.
2233          *
2234          * If we don't do this, when we call func_alloc() later, we will lock
2235          * extra rings to the PF that won't be available during func_cfg() of
2236          * the VFs.
2237          *
2238          * This has been fixed with firmware versions above 20.6.54
2239          */
2240         bp->pf.func_cfg_flags &=
2241                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2242                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2243         bp->pf.func_cfg_flags |=
2244                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2245         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2246         if (rc)
2247                 return rc;
2248
2249         /*
2250          * Now, create and register a buffer to hold forwarded VF requests
2251          */
2252         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2253         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2254                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2255         if (bp->pf.vf_req_buf == NULL) {
2256                 rc = -ENOMEM;
2257                 goto error_free;
2258         }
2259         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2260                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2261         for (i = 0; i < num_vfs; i++)
2262                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2263                                         (i * HWRM_MAX_REQ_LEN);
2264
2265         rc = bnxt_hwrm_func_buf_rgtr(bp);
2266         if (rc)
2267                 goto error_free;
2268
2269         populate_vf_func_cfg_req(bp, &req, num_vfs);
2270
2271         bp->pf.active_vfs = 0;
2272         for (i = 0; i < num_vfs; i++) {
2273                 add_random_mac_if_needed(bp, &req, i);
2274
2275                 HWRM_PREP(req, FUNC_CFG, -1, resp);
2276                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2277                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2278                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2279
2280                 /* Clear enable flag for next pass */
2281                 req.enables &= ~rte_cpu_to_le_32(
2282                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2283
2284                 if (rc || resp->error_code) {
2285                         RTE_LOG(ERR, PMD,
2286                                 "Failed to initizlie VF %d\n", i);
2287                         RTE_LOG(ERR, PMD,
2288                                 "Not all VFs available. (%d, %d)\n",
2289                                 rc, resp->error_code);
2290                         break;
2291                 }
2292
2293                 reserve_resources_from_vf(bp, &req, i);
2294                 bp->pf.active_vfs++;
2295         }
2296
2297         /*
2298          * Now configure the PF to use "the rest" of the resources
2299          * We're using STD_TX_RING_MODE here though which will limit the TX
2300          * rings.  This will allow QoS to function properly.  Not setting this
2301          * will cause PF rings to break bandwidth settings.
2302          */
2303         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2304         if (rc)
2305                 goto error_free;
2306
2307         rc = update_pf_resource_max(bp);
2308         if (rc)
2309                 goto error_free;
2310
2311         return rc;
2312
2313 error_free:
2314         bnxt_hwrm_func_buf_unrgtr(bp);
2315         return rc;
2316 }
2317
2318 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2319 {
2320         struct hwrm_func_cfg_input req = {0};
2321         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2322         int rc;
2323
2324         HWRM_PREP(req, FUNC_CFG, -1, resp);
2325
2326         req.fid = rte_cpu_to_le_16(0xffff);
2327         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2328         req.evb_mode = bp->pf.evb_mode;
2329
2330         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2331         HWRM_CHECK_RESULT;
2332
2333         return rc;
2334 }
2335
2336 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2337                                 uint8_t tunnel_type)
2338 {
2339         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2340         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2341         int rc = 0;
2342
2343         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, -1, resp);
2344         req.tunnel_type = tunnel_type;
2345         req.tunnel_dst_port_val = port;
2346         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2347         HWRM_CHECK_RESULT;
2348
2349         switch (tunnel_type) {
2350         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2351                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2352                 bp->vxlan_port = port;
2353                 break;
2354         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2355                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2356                 bp->geneve_port = port;
2357                 break;
2358         default:
2359                 break;
2360         }
2361         return rc;
2362 }
2363
2364 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2365                                 uint8_t tunnel_type)
2366 {
2367         struct hwrm_tunnel_dst_port_free_input req = {0};
2368         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2369         int rc = 0;
2370
2371         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, -1, resp);
2372         req.tunnel_type = tunnel_type;
2373         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2374         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2375         HWRM_CHECK_RESULT;
2376
2377         return rc;
2378 }
2379
2380 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2381                                         uint32_t flags)
2382 {
2383         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2384         struct hwrm_func_cfg_input req = {0};
2385         int rc;
2386
2387         HWRM_PREP(req, FUNC_CFG, -1, resp);
2388         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2389         req.flags = rte_cpu_to_le_32(flags);
2390         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2391         HWRM_CHECK_RESULT;
2392
2393         return rc;
2394 }
2395
2396 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2397 {
2398         uint32_t *flag = flagp;
2399
2400         vnic->flags = *flag;
2401 }
2402
2403 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2404 {
2405         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2406 }
2407
2408 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2409 {
2410         int rc = 0;
2411         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2412         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2413
2414         HWRM_PREP(req, FUNC_BUF_RGTR, -1, resp);
2415
2416         req.req_buf_num_pages = rte_cpu_to_le_16(1);
2417         req.req_buf_page_size = rte_cpu_to_le_16(
2418                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2419         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2420         req.req_buf_page_addr[0] =
2421                 rte_cpu_to_le_64(rte_mem_virt2phy(bp->pf.vf_req_buf));
2422         if (req.req_buf_page_addr[0] == 0) {
2423                 RTE_LOG(ERR, PMD,
2424                         "unable to map buffer address to physical memory\n");
2425                 return -ENOMEM;
2426         }
2427
2428         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2429
2430         HWRM_CHECK_RESULT;
2431
2432         return rc;
2433 }
2434
2435 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2436 {
2437         int rc = 0;
2438         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2439         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2440
2441         HWRM_PREP(req, FUNC_BUF_UNRGTR, -1, resp);
2442
2443         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2444
2445         HWRM_CHECK_RESULT;
2446
2447         return rc;
2448 }
2449
2450 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2451 {
2452         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2453         struct hwrm_func_cfg_input req = {0};
2454         int rc;
2455
2456         HWRM_PREP(req, FUNC_CFG, -1, resp);
2457         req.fid = rte_cpu_to_le_16(0xffff);
2458         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2459         req.enables = rte_cpu_to_le_32(
2460                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2461         req.async_event_cr = rte_cpu_to_le_16(
2462                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2463         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2464         HWRM_CHECK_RESULT;
2465
2466         return rc;
2467 }
2468
2469 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2470 {
2471         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2472         struct hwrm_func_vf_cfg_input req = {0};
2473         int rc;
2474
2475         HWRM_PREP(req, FUNC_VF_CFG, -1, resp);
2476         req.enables = rte_cpu_to_le_32(
2477                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2478         req.async_event_cr = rte_cpu_to_le_16(
2479                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2480         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2481         HWRM_CHECK_RESULT;
2482
2483         return rc;
2484 }
2485
2486 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2487 {
2488         struct hwrm_func_cfg_input req = {0};
2489         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2490         uint16_t dflt_vlan, fid;
2491         uint32_t func_cfg_flags;
2492         int rc = 0;
2493
2494         HWRM_PREP(req, FUNC_CFG, -1, resp);
2495
2496         if (is_vf) {
2497                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2498                 fid = bp->pf.vf_info[vf].fid;
2499                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2500         } else {
2501                 fid = rte_cpu_to_le_16(0xffff);
2502                 func_cfg_flags = bp->pf.func_cfg_flags;
2503                 dflt_vlan = bp->vlan;
2504         }
2505
2506         req.flags = rte_cpu_to_le_32(func_cfg_flags);
2507         req.fid = rte_cpu_to_le_16(fid);
2508         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2509         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2510
2511         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2512         HWRM_CHECK_RESULT;
2513
2514         return rc;
2515 }
2516
2517 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2518                         uint16_t max_bw, uint16_t enables)
2519 {
2520         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2521         struct hwrm_func_cfg_input req = {0};
2522         int rc;
2523
2524         HWRM_PREP(req, FUNC_CFG, -1, resp);
2525         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2526         req.enables |= rte_cpu_to_le_32(enables);
2527         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2528         req.max_bw = rte_cpu_to_le_32(max_bw);
2529         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2530         HWRM_CHECK_RESULT;
2531
2532         return rc;
2533 }
2534
2535 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2536 {
2537         struct hwrm_func_cfg_input req = {0};
2538         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2539         int rc = 0;
2540
2541         HWRM_PREP(req, FUNC_CFG, -1, resp);
2542         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2543         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2544         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2545         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2546
2547         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2548         HWRM_CHECK_RESULT;
2549
2550         return rc;
2551 }
2552
2553 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2554                               void *encaped, size_t ec_size)
2555 {
2556         int rc = 0;
2557         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2558         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2559
2560         if (ec_size > sizeof(req.encap_request))
2561                 return -1;
2562
2563         HWRM_PREP(req, REJECT_FWD_RESP, -1, resp);
2564
2565         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2566         memcpy(req.encap_request, encaped, ec_size);
2567
2568         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2569
2570         HWRM_CHECK_RESULT;
2571
2572         return rc;
2573 }
2574
2575 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2576                                        struct ether_addr *mac)
2577 {
2578         struct hwrm_func_qcfg_input req = {0};
2579         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2580         int rc;
2581
2582         HWRM_PREP(req, FUNC_QCFG, -1, resp);
2583         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2584         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2585
2586         HWRM_CHECK_RESULT;
2587
2588         memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2589         return rc;
2590 }
2591
2592 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2593                             void *encaped, size_t ec_size)
2594 {
2595         int rc = 0;
2596         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2597         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2598
2599         if (ec_size > sizeof(req.encap_request))
2600                 return -1;
2601
2602         HWRM_PREP(req, EXEC_FWD_RESP, -1, resp);
2603
2604         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2605         memcpy(req.encap_request, encaped, ec_size);
2606
2607         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2608
2609         HWRM_CHECK_RESULT;
2610
2611         return rc;
2612 }
2613
2614 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2615                          struct rte_eth_stats *stats)
2616 {
2617         int rc = 0;
2618         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2619         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2620
2621         HWRM_PREP(req, STAT_CTX_QUERY, -1, resp);
2622
2623         req.stat_ctx_id = rte_cpu_to_le_32(cid);
2624
2625         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2626
2627         HWRM_CHECK_RESULT;
2628
2629         stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2630         stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2631         stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2632         stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2633         stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2634         stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2635
2636         stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2637         stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2638         stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2639         stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2640         stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2641         stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2642
2643         stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2644         stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
2645         stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2646
2647         return rc;
2648 }
2649
2650 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2651 {
2652         struct hwrm_port_qstats_input req = {0};
2653         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2654         struct bnxt_pf_info *pf = &bp->pf;
2655         int rc;
2656
2657         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2658                 return 0;
2659
2660         HWRM_PREP(req, PORT_QSTATS, -1, resp);
2661         req.port_id = rte_cpu_to_le_16(pf->port_id);
2662         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
2663         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
2664         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2665         HWRM_CHECK_RESULT;
2666         return rc;
2667 }
2668
2669 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
2670 {
2671         struct hwrm_port_clr_stats_input req = {0};
2672         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2673         struct bnxt_pf_info *pf = &bp->pf;
2674         int rc;
2675
2676         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2677                 return 0;
2678
2679         HWRM_PREP(req, PORT_CLR_STATS, -1, resp);
2680         req.port_id = rte_cpu_to_le_16(pf->port_id);
2681         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2682         HWRM_CHECK_RESULT;
2683         return rc;
2684 }
2685
2686 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
2687 {
2688         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2689         struct hwrm_port_led_qcaps_input req = {0};
2690         int rc;
2691
2692         if (BNXT_VF(bp))
2693                 return 0;
2694
2695         HWRM_PREP(req, PORT_LED_QCAPS, -1, resp);
2696         req.port_id = bp->pf.port_id;
2697         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2698         HWRM_CHECK_RESULT;
2699
2700         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
2701                 unsigned int i;
2702
2703                 bp->num_leds = resp->num_leds;
2704                 memcpy(bp->leds, &resp->led0_id,
2705                         sizeof(bp->leds[0]) * bp->num_leds);
2706                 for (i = 0; i < bp->num_leds; i++) {
2707                         struct bnxt_led_info *led = &bp->leds[i];
2708
2709                         uint16_t caps = led->led_state_caps;
2710
2711                         if (!led->led_group_id ||
2712                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
2713                                 bp->num_leds = 0;
2714                                 break;
2715                         }
2716                 }
2717         }
2718         return rc;
2719 }
2720
2721 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
2722 {
2723         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2724         struct hwrm_port_led_cfg_input req = {0};
2725         struct bnxt_led_cfg *led_cfg;
2726         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
2727         uint16_t duration = 0;
2728         int rc, i;
2729
2730         if (!bp->num_leds || BNXT_VF(bp))
2731                 return -EOPNOTSUPP;
2732
2733         HWRM_PREP(req, PORT_LED_CFG, -1, resp);
2734         if (led_on) {
2735                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
2736                 duration = rte_cpu_to_le_16(500);
2737         }
2738         req.port_id = bp->pf.port_id;
2739         req.num_leds = bp->num_leds;
2740         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
2741         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
2742                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
2743                 led_cfg->led_id = bp->leds[i].led_id;
2744                 led_cfg->led_state = led_state;
2745                 led_cfg->led_blink_on = duration;
2746                 led_cfg->led_blink_off = duration;
2747                 led_cfg->led_group_id = bp->leds[i].led_group_id;
2748         }
2749
2750         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2751         HWRM_CHECK_RESULT;
2752
2753         return rc;
2754 }
2755
2756 static void
2757 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
2758 {
2759         uint32_t *count = cbdata;
2760
2761         *count = *count + 1;
2762 }
2763
2764 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
2765                                      struct bnxt_vnic_info *vnic __rte_unused)
2766 {
2767         return 0;
2768 }
2769
2770 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
2771 {
2772         uint32_t count = 0;
2773
2774         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
2775             &count, bnxt_vnic_count_hwrm_stub);
2776
2777         return count;
2778 }
2779
2780 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
2781                                         uint16_t *vnic_ids)
2782 {
2783         struct hwrm_func_vf_vnic_ids_query_input req = {0};
2784         struct hwrm_func_vf_vnic_ids_query_output *resp =
2785                                                 bp->hwrm_cmd_resp_addr;
2786         int rc;
2787
2788         /* First query all VNIC ids */
2789         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, -1, resp_vf_vnic_ids);
2790
2791         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
2792         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
2793         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2phy(vnic_ids));
2794
2795         if (req.vnic_id_tbl_addr == 0) {
2796                 RTE_LOG(ERR, PMD,
2797                 "unable to map VNIC ID table address to physical memory\n");
2798                 return -ENOMEM;
2799         }
2800         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2801         if (rc) {
2802                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
2803                 return -1;
2804         } else if (resp->error_code) {
2805                 rc = rte_le_to_cpu_16(resp->error_code);
2806                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query error %d\n", rc);
2807                 return -1;
2808         }
2809
2810         return rte_le_to_cpu_32(resp->vnic_id_cnt);
2811 }
2812
2813 /*
2814  * This function queries the VNIC IDs  for a specified VF. It then calls
2815  * the vnic_cb to update the necessary field in vnic_info with cbdata.
2816  * Then it calls the hwrm_cb function to program this new vnic configuration.
2817  */
2818 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
2819         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
2820         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
2821 {
2822         struct bnxt_vnic_info vnic;
2823         int rc = 0;
2824         int i, num_vnic_ids;
2825         uint16_t *vnic_ids;
2826         size_t vnic_id_sz;
2827         size_t sz;
2828
2829         /* First query all VNIC ids */
2830         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
2831         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
2832                         RTE_CACHE_LINE_SIZE);
2833         if (vnic_ids == NULL) {
2834                 rc = -ENOMEM;
2835                 return rc;
2836         }
2837         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
2838                 rte_mem_lock_page(((char *)vnic_ids) + sz);
2839
2840         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
2841
2842         if (num_vnic_ids < 0)
2843                 return num_vnic_ids;
2844
2845         /* Retrieve VNIC, update bd_stall then update */
2846
2847         for (i = 0; i < num_vnic_ids; i++) {
2848                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
2849                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
2850                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
2851                 if (rc)
2852                         break;
2853                 if (vnic.mru <= 4)      /* Indicates unallocated */
2854                         continue;
2855
2856                 vnic_cb(&vnic, cbdata);
2857
2858                 rc = hwrm_cb(bp, &vnic);
2859                 if (rc)
2860                         break;
2861         }
2862
2863         rte_free(vnic_ids);
2864
2865         return rc;
2866 }
2867
2868 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
2869                                               bool on)
2870 {
2871         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2872         struct hwrm_func_cfg_input req = {0};
2873         int rc;
2874
2875         HWRM_PREP(req, FUNC_CFG, -1, resp);
2876         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2877         req.enables |= rte_cpu_to_le_32(
2878                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
2879         req.vlan_antispoof_mode = on ?
2880                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
2881                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
2882         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2883         HWRM_CHECK_RESULT;
2884
2885         return rc;
2886 }
2887
2888 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
2889 {
2890         struct bnxt_vnic_info vnic;
2891         uint16_t *vnic_ids;
2892         size_t vnic_id_sz;
2893         int num_vnic_ids, i;
2894         size_t sz;
2895         int rc;
2896
2897         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
2898         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
2899                         RTE_CACHE_LINE_SIZE);
2900         if (vnic_ids == NULL) {
2901                 rc = -ENOMEM;
2902                 return rc;
2903         }
2904
2905         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
2906                 rte_mem_lock_page(((char *)vnic_ids) + sz);
2907
2908         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
2909         if (rc <= 0)
2910                 goto exit;
2911         num_vnic_ids = rc;
2912
2913         /*
2914          * Loop through to find the default VNIC ID.
2915          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
2916          * by sending the hwrm_func_qcfg command to the firmware.
2917          */
2918         for (i = 0; i < num_vnic_ids; i++) {
2919                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
2920                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
2921                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
2922                                         bp->pf.first_vf_id + vf);
2923                 if (rc)
2924                         goto exit;
2925                 if (vnic.func_default) {
2926                         rte_free(vnic_ids);
2927                         return vnic.fw_vnic_id;
2928                 }
2929         }
2930         /* Could not find a default VNIC. */
2931         RTE_LOG(ERR, PMD, "No default VNIC\n");
2932 exit:
2933         rte_free(vnic_ids);
2934         return -1;
2935 }