drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SHORT_CMD_TIMEOUT          50000
  31 #define HWRM_SPEC_CODE_1_8_3            0x10803
  32 #define HWRM_VERSION_1_9_1              0x10901
  33 #define HWRM_VERSION_1_9_2              0x10903
  34
  35 struct bnxt_plcmodes_cfg {
  36         uint32_t        flags;
  37         uint16_t        jumbo_thresh;
  38         uint16_t        hds_offset;
  39         uint16_t        hds_threshold;
  40 };
  41
  42 static int page_getenum(size_t size)
  43 {
  44         if (size <= 1 << 4)
  45                 return 4;
  46         if (size <= 1 << 12)
  47                 return 12;
  48         if (size <= 1 << 13)
  49                 return 13;
  50         if (size <= 1 << 16)
  51                 return 16;
  52         if (size <= 1 << 21)
  53                 return 21;
  54         if (size <= 1 << 22)
  55                 return 22;
  56         if (size <= 1 << 30)
  57                 return 30;
  58         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  59         return sizeof(void *) * 8 - 1;
  60 }
  61
  62 static int page_roundup(size_t size)
  63 {
  64         return 1 << page_getenum(size);
  65 }
  66
  67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  68                                   uint8_t *pg_attr,
  69                                   uint64_t *pg_dir)
  70 {
  71         if (rmem->nr_pages > 1) {
  72                 *pg_attr = 1;
  73                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  74         } else {
  75                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  76         }
  77 }
  78
  79 /*
  80  * HWRM Functions (sent to HWRM)
  81  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  82  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  83  * command was failed by the ChiMP.
  84  */
  85
  86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  87                                   uint32_t msg_len, bool use_kong_mb)
  88 {
  89         unsigned int i;
  90         struct input *req = msg;
  91         struct output *resp = bp->hwrm_cmd_resp_addr;
  92         uint32_t *data = msg;
  93         uint8_t *bar;
  94         uint8_t *valid;
  95         uint16_t max_req_len = bp->max_req_len;
  96         struct hwrm_short_input short_input = { 0 };
  97         uint16_t bar_offset = use_kong_mb ?
  98                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  99         uint16_t mb_trigger_offset = use_kong_mb ?
 100                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 101         uint32_t timeout;
 102
 103         /* Do not send HWRM commands to firmware in error state */
 104         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 105                 return 0;
 106
 107         /* For VER_GET command, set timeout as 50ms */
 108         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 109                 timeout = HWRM_SHORT_CMD_TIMEOUT;
 110         else
 111                 timeout = HWRM_CMD_TIMEOUT;
 112
 113         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 114             msg_len > bp->max_req_len) {
 115                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 116
 117                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 118                 memcpy(short_cmd_req, req, msg_len);
 119
 120                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 121                 short_input.signature = rte_cpu_to_le_16(
 122                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 123                 short_input.size = rte_cpu_to_le_16(msg_len);
 124                 short_input.req_addr =
 125                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 126
 127                 data = (uint32_t *)&short_input;
 128                 msg_len = sizeof(short_input);
 129
 130                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 131         }
 132
 133         /* Write request msg to hwrm channel */
 134         for (i = 0; i < msg_len; i += 4) {
 135                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 136                 rte_write32(*data, bar);
 137                 data++;
 138         }
 139
 140         /* Zero the rest of the request space */
 141         for (; i < max_req_len; i += 4) {
 142                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 143                 rte_write32(0, bar);
 144         }
 145
 146         /* Ring channel doorbell */
 147         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 148         rte_write32(1, bar);
 149         /*
 150          * Make sure the channel doorbell ring command complete before
 151          * reading the response to avoid getting stale or invalid
 152          * responses.
 153          */
 154         rte_io_mb();
 155
 156         /* Poll for the valid bit */
 157         for (i = 0; i < timeout; i++) {
 158                 /* Sanity check on the resp->resp_len */
 159                 rte_cio_rmb();
 160                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 161                         /* Last byte of resp contains the valid key */
 162                         valid = (uint8_t *)resp + resp->resp_len - 1;
 163                         if (*valid == HWRM_RESP_VALID_KEY)
 164                                 break;
 165                 }
 166                 rte_delay_us(1);
 167         }
 168
 169         if (i >= timeout) {
 170                 /* Suppress VER_GET timeout messages during reset recovery */
 171                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 172                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 173                         return -ETIMEDOUT;
 174
 175                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 176                             req->req_type);
 177                 return -ETIMEDOUT;
 178         }
 179         return 0;
 180 }
 181
 182 /*
 183  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 184  * spinlock, and does initial processing.
 185  *
 186  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 187  * releases the spinlock only if it returns.  If the regular int return codes
 188  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 189  * directly, rather it should be copied and modified to suit the function.
 190  *
 191  * HWRM_UNLOCK() must be called after all response processing is completed.
 192  */
 193 #define HWRM_PREP(req, type, kong) do { \
 194         rte_spinlock_lock(&bp->hwrm_lock); \
 195         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 196         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 197         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 198         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 199                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 200         req.target_id = rte_cpu_to_le_16(0xffff); \
 201         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 202 } while (0)
 203
 204 #define HWRM_CHECK_RESULT_SILENT() do {\
 205         if (rc) { \
 206                 rte_spinlock_unlock(&bp->hwrm_lock); \
 207                 return rc; \
 208         } \
 209         if (resp->error_code) { \
 210                 rc = rte_le_to_cpu_16(resp->error_code); \
 211                 rte_spinlock_unlock(&bp->hwrm_lock); \
 212                 return rc; \
 213         } \
 214 } while (0)
 215
 216 #define HWRM_CHECK_RESULT() do {\
 217         if (rc) { \
 218                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 219                 rte_spinlock_unlock(&bp->hwrm_lock); \
 220                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 221                         rc = -EACCES; \
 222                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 223                         rc = -ENOSPC; \
 224                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 225                         rc = -EINVAL; \
 226                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 227                         rc = -ENOTSUP; \
 228                 else if (rc > 0) \
 229                         rc = -EIO; \
 230                 return rc; \
 231         } \
 232         if (resp->error_code) { \
 233                 rc = rte_le_to_cpu_16(resp->error_code); \
 234                 if (resp->resp_len >= 16) { \
 235                         struct hwrm_err_output *tmp_hwrm_err_op = \
 236                                                 (void *)resp; \
 237                         PMD_DRV_LOG(ERR, \
 238                                 "error %d:%d:%08x:%04x\n", \
 239                                 rc, tmp_hwrm_err_op->cmd_err, \
 240                                 rte_le_to_cpu_32(\
 241                                         tmp_hwrm_err_op->opaque_0), \
 242                                 rte_le_to_cpu_16(\
 243                                         tmp_hwrm_err_op->opaque_1)); \
 244                 } else { \
 245                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 246                 } \
 247                 rte_spinlock_unlock(&bp->hwrm_lock); \
 248                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 249                         rc = -EACCES; \
 250                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 251                         rc = -ENOSPC; \
 252                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 253                         rc = -EINVAL; \
 254                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 255                         rc = -ENOTSUP; \
 256                 else if (rc > 0) \
 257                         rc = -EIO; \
 258                 return rc; \
 259         } \
 260 } while (0)
 261
 262 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 263
 264 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 265 {
 266         int rc = 0;
 267         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 268         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 269
 270         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 271         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 272         req.mask = 0;
 273
 274         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 275
 276         HWRM_CHECK_RESULT();
 277         HWRM_UNLOCK();
 278
 279         return rc;
 280 }
 281
 282 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 283                                  struct bnxt_vnic_info *vnic,
 284                                  uint16_t vlan_count,
 285                                  struct bnxt_vlan_table_entry *vlan_table)
 286 {
 287         int rc = 0;
 288         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 289         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 290         uint32_t mask = 0;
 291
 292         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 293                 return rc;
 294
 295         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 296         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 297
 298         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 299                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 300         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 301                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 302
 303         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 304                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 305
 306         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 307                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 308         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 309                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 310                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 311                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 312         }
 313         if (vlan_table) {
 314                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 315                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 316                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 317                          rte_mem_virt2iova(vlan_table));
 318                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 319         }
 320         req.mask = rte_cpu_to_le_32(mask);
 321
 322         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 323
 324         HWRM_CHECK_RESULT();
 325         HWRM_UNLOCK();
 326
 327         return rc;
 328 }
 329
 330 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 331                         uint16_t vlan_count,
 332                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 333 {
 334         int rc = 0;
 335         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 336         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 337                                                 bp->hwrm_cmd_resp_addr;
 338
 339         /*
 340          * Older HWRM versions did not support this command, and the set_rx_mask
 341          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 342          * removed from set_rx_mask call, and this command was added.
 343          *
 344          * This command is also present from 1.7.8.11 and higher,
 345          * as well as 1.7.8.0
 346          */
 347         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 348                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 349                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 350                                         (11)))
 351                                 return 0;
 352                 }
 353         }
 354         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 355         req.fid = rte_cpu_to_le_16(fid);
 356
 357         req.vlan_tag_mask_tbl_addr =
 358                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 359         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 360
 361         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 362
 363         HWRM_CHECK_RESULT();
 364         HWRM_UNLOCK();
 365
 366         return rc;
 367 }
 368
 369 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 370                            struct bnxt_filter_info *filter)
 371 {
 372         int rc = 0;
 373         struct bnxt_filter_info *l2_filter = filter;
 374         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 375         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 376
 377         if (filter->fw_l2_filter_id == UINT64_MAX)
 378                 return 0;
 379
 380         if (filter->matching_l2_fltr_ptr)
 381                 l2_filter = filter->matching_l2_fltr_ptr;
 382
 383         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 384                     filter, l2_filter, l2_filter->l2_ref_cnt);
 385
 386         if (l2_filter->l2_ref_cnt > 0)
 387                 l2_filter->l2_ref_cnt--;
 388
 389         if (l2_filter->l2_ref_cnt > 0)
 390                 return 0;
 391
 392         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 393
 394         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 395
 396         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 397
 398         HWRM_CHECK_RESULT();
 399         HWRM_UNLOCK();
 400
 401         filter->fw_l2_filter_id = UINT64_MAX;
 402
 403         return 0;
 404 }
 405
 406 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 407                          uint16_t dst_id,
 408                          struct bnxt_filter_info *filter)
 409 {
 410         int rc = 0;
 411         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 412         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 413         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 414         const struct rte_eth_vmdq_rx_conf *conf =
 415                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 416         uint32_t enables = 0;
 417         uint16_t j = dst_id - 1;
 418
 419         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 420         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 421             conf->pool_map[j].pools & (1UL << j)) {
 422                 PMD_DRV_LOG(DEBUG,
 423                         "Add vlan %u to vmdq pool %u\n",
 424                         conf->pool_map[j].vlan_id, j);
 425
 426                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 427                 filter->enables |=
 428                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 429                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 430         }
 431
 432         if (filter->fw_l2_filter_id != UINT64_MAX)
 433                 bnxt_hwrm_clear_l2_filter(bp, filter);
 434
 435         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 436
 437         req.flags = rte_cpu_to_le_32(filter->flags);
 438
 439         enables = filter->enables |
 440               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 441         req.dst_id = rte_cpu_to_le_16(dst_id);
 442
 443         if (enables &
 444             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 445                 memcpy(req.l2_addr, filter->l2_addr,
 446                        RTE_ETHER_ADDR_LEN);
 447         if (enables &
 448             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 449                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 450                        RTE_ETHER_ADDR_LEN);
 451         if (enables &
 452             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 453                 req.l2_ovlan = filter->l2_ovlan;
 454         if (enables &
 455             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 456                 req.l2_ivlan = filter->l2_ivlan;
 457         if (enables &
 458             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 459                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 460         if (enables &
 461             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 462                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 463         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 464                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 465         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 466                 req.src_type = filter->src_type;
 467         if (filter->pri_hint) {
 468                 req.pri_hint = filter->pri_hint;
 469                 req.l2_filter_id_hint =
 470                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 471         }
 472
 473         req.enables = rte_cpu_to_le_32(enables);
 474
 475         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 476
 477         HWRM_CHECK_RESULT();
 478
 479         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 480         HWRM_UNLOCK();
 481
 482         return rc;
 483 }
 484
 485 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 486 {
 487         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 488         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 489         uint32_t flags = 0;
 490         int rc;
 491
 492         if (!ptp)
 493                 return 0;
 494
 495         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 496
 497         if (ptp->rx_filter)
 498                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 499         else
 500                 flags |=
 501                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 502         if (ptp->tx_tstamp_en)
 503                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 504         else
 505                 flags |=
 506                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 507         req.flags = rte_cpu_to_le_32(flags);
 508         req.enables = rte_cpu_to_le_32
 509                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 510         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 511
 512         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 513         HWRM_UNLOCK();
 514
 515         return rc;
 516 }
 517
 518 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 519 {
 520         int rc = 0;
 521         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 522         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 523         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 524
 525 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 526         if (ptp)
 527                 return 0;
 528
 529         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 530
 531         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 532
 533         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 534
 535         HWRM_CHECK_RESULT();
 536
 537         if (!BNXT_CHIP_THOR(bp) &&
 538             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 539                 return 0;
 540
 541         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 542                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 543
 544         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 545         if (!ptp)
 546                 return -ENOMEM;
 547
 548         if (!BNXT_CHIP_THOR(bp)) {
 549                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 550                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 551                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 552                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 553                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 554                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 555                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 556                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 557                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 558                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 559                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 560                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 561                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 562                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 563                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 564                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 565                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 566                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 567         }
 568
 569         ptp->bp = bp;
 570         bp->ptp_cfg = ptp;
 571
 572         return 0;
 573 }
 574
 575 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 576 {
 577         int rc = 0;
 578         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 579         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 580         uint16_t new_max_vfs;
 581         uint32_t flags;
 582         int i;
 583
 584         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 585
 586         req.fid = rte_cpu_to_le_16(0xffff);
 587
 588         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 589
 590         HWRM_CHECK_RESULT();
 591
 592         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 593         flags = rte_le_to_cpu_32(resp->flags);
 594         if (BNXT_PF(bp)) {
 595                 bp->pf.port_id = resp->port_id;
 596                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 597                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 598                 new_max_vfs = bp->pdev->max_vfs;
 599                 if (new_max_vfs != bp->pf.max_vfs) {
 600                         if (bp->pf.vf_info)
 601                                 rte_free(bp->pf.vf_info);
 602                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 603                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 604                         bp->pf.max_vfs = new_max_vfs;
 605                         for (i = 0; i < new_max_vfs; i++) {
 606                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 607                                 bp->pf.vf_info[i].vlan_table =
 608                                         rte_zmalloc("VF VLAN table",
 609                                                     getpagesize(),
 610                                                     getpagesize());
 611                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 612                                         PMD_DRV_LOG(ERR,
 613                                         "Fail to alloc VLAN table for VF %d\n",
 614                                         i);
 615                                 else
 616                                         rte_mem_lock_page(
 617                                                 bp->pf.vf_info[i].vlan_table);
 618                                 bp->pf.vf_info[i].vlan_as_table =
 619                                         rte_zmalloc("VF VLAN AS table",
 620                                                     getpagesize(),
 621                                                     getpagesize());
 622                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 623                                         PMD_DRV_LOG(ERR,
 624                                         "Alloc VLAN AS table for VF %d fail\n",
 625                                         i);
 626                                 else
 627                                         rte_mem_lock_page(
 628                                                bp->pf.vf_info[i].vlan_as_table);
 629                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 630                         }
 631                 }
 632         }
 633
 634         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 635         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 636         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 637         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 638         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 639         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 640         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 641         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 642         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 643         if (!BNXT_CHIP_THOR(bp))
 644                 bp->max_l2_ctx += bp->max_rx_em_flows;
 645         /* TODO: For now, do not support VMDq/RFS on VFs. */
 646         if (BNXT_PF(bp)) {
 647                 if (bp->pf.max_vfs)
 648                         bp->max_vnics = 1;
 649                 else
 650                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 651         } else {
 652                 bp->max_vnics = 1;
 653         }
 654         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 655         if (BNXT_PF(bp)) {
 656                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 657                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 658                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 659                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 660                         HWRM_UNLOCK();
 661                         bnxt_hwrm_ptp_qcfg(bp);
 662                 }
 663         }
 664
 665         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 666                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 667
 668         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 669                 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 670                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 671         } else {
 672                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 673         }
 674
 675         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 676                 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 677         else
 678                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 679
 680         HWRM_UNLOCK();
 681
 682         return rc;
 683 }
 684
 685 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 686 {
 687         int rc;
 688
 689         rc = __bnxt_hwrm_func_qcaps(bp);
 690         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 691                 rc = bnxt_alloc_ctx_mem(bp);
 692                 if (rc)
 693                         return rc;
 694
 695                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 696                 if (!rc)
 697                         bp->flags |= BNXT_FLAG_NEW_RM;
 698         }
 699
 700         return rc;
 701 }
 702
 703 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 704 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 705 {
 706         int rc = 0;
 707         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 708         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 709
 710         HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 711
 712         req.target_id = rte_cpu_to_le_16(0xffff);
 713
 714         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 715
 716         HWRM_CHECK_RESULT();
 717
 718         if (rte_le_to_cpu_32(resp->flags) &
 719             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 720                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 721                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 722         }
 723
 724         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 725
 726         HWRM_UNLOCK();
 727
 728         return rc;
 729 }
 730
 731 int bnxt_hwrm_func_reset(struct bnxt *bp)
 732 {
 733         int rc = 0;
 734         struct hwrm_func_reset_input req = {.req_type = 0 };
 735         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 736
 737         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 738
 739         req.enables = rte_cpu_to_le_32(0);
 740
 741         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 742
 743         HWRM_CHECK_RESULT();
 744         HWRM_UNLOCK();
 745
 746         return rc;
 747 }
 748
 749 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 750 {
 751         int rc;
 752         uint32_t flags = 0;
 753         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 754         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 755
 756         if (bp->flags & BNXT_FLAG_REGISTERED)
 757                 return 0;
 758
 759         flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 760         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 761                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 762
 763         /* PFs and trusted VFs should indicate the support of the
 764          * Master capability on non Stingray platform
 765          */
 766         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 767                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 768
 769         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 770         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 771                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 772         req.ver_maj = RTE_VER_YEAR;
 773         req.ver_min = RTE_VER_MONTH;
 774         req.ver_upd = RTE_VER_MINOR;
 775
 776         if (BNXT_PF(bp)) {
 777                 req.enables |= rte_cpu_to_le_32(
 778                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 779                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 780                        RTE_MIN(sizeof(req.vf_req_fwd),
 781                                sizeof(bp->pf.vf_req_fwd)));
 782
 783                 /*
 784                  * PF can sniff HWRM API issued by VF. This can be set up by
 785                  * linux driver and inherited by the DPDK PF driver. Clear
 786                  * this HWRM sniffer list in FW because DPDK PF driver does
 787                  * not support this.
 788                  */
 789                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 790         }
 791
 792         req.flags = rte_cpu_to_le_32(flags);
 793
 794         req.async_event_fwd[0] |=
 795                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 796                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 797                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 798                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 799                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 800         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 801                 req.async_event_fwd[0] |=
 802                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 803         req.async_event_fwd[1] |=
 804                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 805                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 806
 807         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 808
 809         HWRM_CHECK_RESULT();
 810
 811         flags = rte_le_to_cpu_32(resp->flags);
 812         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 813                 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
 814
 815         HWRM_UNLOCK();
 816
 817         bp->flags |= BNXT_FLAG_REGISTERED;
 818
 819         return rc;
 820 }
 821
 822 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 823 {
 824         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 825                 return 0;
 826
 827         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 828 }
 829
 830 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 831 {
 832         int rc;
 833         uint32_t flags = 0;
 834         uint32_t enables;
 835         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 836         struct hwrm_func_vf_cfg_input req = {0};
 837
 838         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 839
 840         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 841                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 842                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 843                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 844                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 845
 846         if (BNXT_HAS_RING_GRPS(bp)) {
 847                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 848                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 849         }
 850
 851         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 852         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 853                                             AGG_RING_MULTIPLIER);
 854         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
 855                                              bp->tx_nr_rings +
 856                                              BNXT_NUM_ASYNC_CPR(bp));
 857         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 858                                               bp->tx_nr_rings +
 859                                               BNXT_NUM_ASYNC_CPR(bp));
 860         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 861         if (bp->vf_resv_strategy ==
 862             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 863                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 864                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 865                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 866                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 867                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 868                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 869         }
 870
 871         if (test)
 872                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 873                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 874                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 875                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 876                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 877                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 878
 879         if (test && BNXT_HAS_RING_GRPS(bp))
 880                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 881
 882         req.flags = rte_cpu_to_le_32(flags);
 883         req.enables |= rte_cpu_to_le_32(enables);
 884
 885         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 886
 887         if (test)
 888                 HWRM_CHECK_RESULT_SILENT();
 889         else
 890                 HWRM_CHECK_RESULT();
 891
 892         HWRM_UNLOCK();
 893         return rc;
 894 }
 895
 896 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 897 {
 898         int rc;
 899         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 900         struct hwrm_func_resource_qcaps_input req = {0};
 901
 902         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 903         req.fid = rte_cpu_to_le_16(0xffff);
 904
 905         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 906
 907         HWRM_CHECK_RESULT();
 908
 909         if (BNXT_VF(bp)) {
 910                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 911                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 912                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 913                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 914                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 915                 /* func_resource_qcaps does not return max_rx_em_flows.
 916                  * So use the value provided by func_qcaps.
 917                  */
 918                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 919                 if (!BNXT_CHIP_THOR(bp))
 920                         bp->max_l2_ctx += bp->max_rx_em_flows;
 921                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 922                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 923         }
 924         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 925         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 926         if (bp->vf_resv_strategy >
 927             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 928                 bp->vf_resv_strategy =
 929                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 930
 931         HWRM_UNLOCK();
 932         return rc;
 933 }
 934
 935 int bnxt_hwrm_ver_get(struct bnxt *bp)
 936 {
 937         int rc = 0;
 938         struct hwrm_ver_get_input req = {.req_type = 0 };
 939         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 940         uint32_t fw_version;
 941         uint16_t max_resp_len;
 942         char type[RTE_MEMZONE_NAMESIZE];
 943         uint32_t dev_caps_cfg;
 944
 945         bp->max_req_len = HWRM_MAX_REQ_LEN;
 946         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 947
 948         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 949         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 950         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 951
 952         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 953
 954         if (bp->flags & BNXT_FLAG_FW_RESET)
 955                 HWRM_CHECK_RESULT_SILENT();
 956         else
 957                 HWRM_CHECK_RESULT();
 958
 959         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 960                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 961                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 962                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 963         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 964                      (resp->hwrm_fw_min_8b << 16) |
 965                      (resp->hwrm_fw_bld_8b << 8) |
 966                      resp->hwrm_fw_rsvd_8b;
 967         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 968                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 969
 970         fw_version = resp->hwrm_intf_maj_8b << 16;
 971         fw_version |= resp->hwrm_intf_min_8b << 8;
 972         fw_version |= resp->hwrm_intf_upd_8b;
 973         bp->hwrm_spec_code = fw_version;
 974
 975         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 976                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 977                 rc = -EINVAL;
 978                 goto error;
 979         }
 980
 981         if (bp->max_req_len > resp->max_req_win_len) {
 982                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 983                 rc = -EINVAL;
 984         }
 985         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 986         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 987         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 988                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 989
 990         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 991         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 992
 993         if (bp->max_resp_len != max_resp_len) {
 994                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 995                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 996                         bp->pdev->addr.devid, bp->pdev->addr.function);
 997
 998                 rte_free(bp->hwrm_cmd_resp_addr);
 999
1000                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1001                 if (bp->hwrm_cmd_resp_addr == NULL) {
1002                         rc = -ENOMEM;
1003                         goto error;
1004                 }
1005                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1006                 bp->hwrm_cmd_resp_dma_addr =
1007                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1008                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1009                         PMD_DRV_LOG(ERR,
1010                         "Unable to map response buffer to physical memory.\n");
1011                         rc = -ENOMEM;
1012                         goto error;
1013                 }
1014                 bp->max_resp_len = max_resp_len;
1015         }
1016
1017         if ((dev_caps_cfg &
1018                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1019             (dev_caps_cfg &
1020              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1021                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1022                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1023         }
1024
1025         if (((dev_caps_cfg &
1026               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1027              (dev_caps_cfg &
1028               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1029             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1030                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1031                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1032                         bp->pdev->addr.devid, bp->pdev->addr.function);
1033
1034                 rte_free(bp->hwrm_short_cmd_req_addr);
1035
1036                 bp->hwrm_short_cmd_req_addr =
1037                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1038                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1039                         rc = -ENOMEM;
1040                         goto error;
1041                 }
1042                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1043                 bp->hwrm_short_cmd_req_dma_addr =
1044                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1045                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1046                         rte_free(bp->hwrm_short_cmd_req_addr);
1047                         PMD_DRV_LOG(ERR,
1048                                 "Unable to map buffer to physical memory.\n");
1049                         rc = -ENOMEM;
1050                         goto error;
1051                 }
1052         }
1053         if (dev_caps_cfg &
1054             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1055                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1056                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1057         }
1058         if (dev_caps_cfg &
1059             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1060                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1061         if (dev_caps_cfg &
1062             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1063                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1064                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1065         }
1066
1067 error:
1068         HWRM_UNLOCK();
1069         return rc;
1070 }
1071
1072 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1073 {
1074         int rc;
1075         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1076         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1077
1078         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1079                 return 0;
1080
1081         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1082         req.flags = flags;
1083
1084         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1085
1086         HWRM_CHECK_RESULT();
1087         HWRM_UNLOCK();
1088
1089         return rc;
1090 }
1091
1092 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1093 {
1094         int rc = 0;
1095         struct hwrm_port_phy_cfg_input req = {0};
1096         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1097         uint32_t enables = 0;
1098
1099         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1100
1101         if (conf->link_up) {
1102                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1103                 if (bp->link_info.auto_mode && conf->link_speed) {
1104                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1105                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1106                 }
1107
1108                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1109                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1110                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1111                 /*
1112                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1113                  * any auto mode, even "none".
1114                  */
1115                 if (!conf->link_speed) {
1116                         /* No speeds specified. Enable AutoNeg - all speeds */
1117                         req.auto_mode =
1118                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1119                 }
1120                 /* AutoNeg - Advertise speeds specified. */
1121                 if (conf->auto_link_speed_mask &&
1122                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1123                         req.auto_mode =
1124                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1125                         req.auto_link_speed_mask =
1126                                 conf->auto_link_speed_mask;
1127                         enables |=
1128                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1129                 }
1130
1131                 req.auto_duplex = conf->duplex;
1132                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1133                 req.auto_pause = conf->auto_pause;
1134                 req.force_pause = conf->force_pause;
1135                 /* Set force_pause if there is no auto or if there is a force */
1136                 if (req.auto_pause && !req.force_pause)
1137                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1138                 else
1139                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1140
1141                 req.enables = rte_cpu_to_le_32(enables);
1142         } else {
1143                 req.flags =
1144                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1145                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1146         }
1147
1148         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1149
1150         HWRM_CHECK_RESULT();
1151         HWRM_UNLOCK();
1152
1153         return rc;
1154 }
1155
1156 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1157                                    struct bnxt_link_info *link_info)
1158 {
1159         int rc = 0;
1160         struct hwrm_port_phy_qcfg_input req = {0};
1161         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1162
1163         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1164
1165         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1166
1167         HWRM_CHECK_RESULT();
1168
1169         link_info->phy_link_status = resp->link;
1170         link_info->link_up =
1171                 (link_info->phy_link_status ==
1172                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1173         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1174         link_info->duplex = resp->duplex_cfg;
1175         link_info->pause = resp->pause;
1176         link_info->auto_pause = resp->auto_pause;
1177         link_info->force_pause = resp->force_pause;
1178         link_info->auto_mode = resp->auto_mode;
1179         link_info->phy_type = resp->phy_type;
1180         link_info->media_type = resp->media_type;
1181
1182         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1183         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1184         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1185         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1186         link_info->phy_ver[0] = resp->phy_maj;
1187         link_info->phy_ver[1] = resp->phy_min;
1188         link_info->phy_ver[2] = resp->phy_bld;
1189
1190         HWRM_UNLOCK();
1191
1192         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1193         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1194         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1195         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1196         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1197                     link_info->auto_link_speed_mask);
1198         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1199                     link_info->force_link_speed);
1200
1201         return rc;
1202 }
1203
1204 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1205 {
1206         int rc = 0;
1207         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1208         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1209         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1210         int i;
1211
1212 get_rx_info:
1213         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1214
1215         req.flags = rte_cpu_to_le_32(dir);
1216         /* HWRM Version >= 1.9.1 */
1217         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1218                 req.drv_qmap_cap =
1219                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1220         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1221
1222         HWRM_CHECK_RESULT();
1223
1224         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1225                 GET_TX_QUEUE_INFO(0);
1226                 GET_TX_QUEUE_INFO(1);
1227                 GET_TX_QUEUE_INFO(2);
1228                 GET_TX_QUEUE_INFO(3);
1229                 GET_TX_QUEUE_INFO(4);
1230                 GET_TX_QUEUE_INFO(5);
1231                 GET_TX_QUEUE_INFO(6);
1232                 GET_TX_QUEUE_INFO(7);
1233         } else  {
1234                 GET_RX_QUEUE_INFO(0);
1235                 GET_RX_QUEUE_INFO(1);
1236                 GET_RX_QUEUE_INFO(2);
1237                 GET_RX_QUEUE_INFO(3);
1238                 GET_RX_QUEUE_INFO(4);
1239                 GET_RX_QUEUE_INFO(5);
1240                 GET_RX_QUEUE_INFO(6);
1241                 GET_RX_QUEUE_INFO(7);
1242         }
1243
1244         HWRM_UNLOCK();
1245
1246         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1247                 goto done;
1248
1249         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1250                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1251         } else {
1252                 int j;
1253
1254                 /* iterate and find the COSq profile to use for Tx */
1255                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1256                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1257                                 if (bp->tx_cos_queue[i].id != 0xff)
1258                                         bp->tx_cosq_id[j++] =
1259                                                 bp->tx_cos_queue[i].id;
1260                         }
1261                 } else {
1262                         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1263                                 if (bp->tx_cos_queue[i].profile ==
1264                                         HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1265                                         bp->tx_cosq_id[0] =
1266                                                 bp->tx_cos_queue[i].id;
1267                                         break;
1268                                 }
1269                         }
1270                 }
1271         }
1272
1273         bp->max_tc = resp->max_configurable_queues;
1274         bp->max_lltc = resp->max_configurable_lossless_queues;
1275         if (bp->max_tc > BNXT_MAX_QUEUE)
1276                 bp->max_tc = BNXT_MAX_QUEUE;
1277         bp->max_q = bp->max_tc;
1278
1279         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1280                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1281                 goto get_rx_info;
1282         }
1283
1284 done:
1285         return rc;
1286 }
1287
1288 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1289                          struct bnxt_ring *ring,
1290                          uint32_t ring_type, uint32_t map_index,
1291                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1292                          uint16_t tx_cosq_id)
1293 {
1294         int rc = 0;
1295         uint32_t enables = 0;
1296         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1297         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1298         struct rte_mempool *mb_pool;
1299         uint16_t rx_buf_size;
1300
1301         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1302
1303         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1304         req.fbo = rte_cpu_to_le_32(0);
1305         /* Association of ring index with doorbell index */
1306         req.logical_id = rte_cpu_to_le_16(map_index);
1307         req.length = rte_cpu_to_le_32(ring->ring_size);
1308
1309         switch (ring_type) {
1310         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1311                 req.ring_type = ring_type;
1312                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1313                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1314                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1315                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1316                         enables |=
1317                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1318                 break;
1319         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1320                 req.ring_type = ring_type;
1321                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1322                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1323                 if (BNXT_CHIP_THOR(bp)) {
1324                         mb_pool = bp->rx_queues[0]->mb_pool;
1325                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1326                                       RTE_PKTMBUF_HEADROOM;
1327                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1328                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1329                         enables |=
1330                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1331                 }
1332                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1333                         enables |=
1334                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1335                 break;
1336         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1337                 req.ring_type = ring_type;
1338                 if (BNXT_HAS_NQ(bp)) {
1339                         /* Association of cp ring with nq */
1340                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1341                         enables |=
1342                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1343                 }
1344                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1345                 break;
1346         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1347                 req.ring_type = ring_type;
1348                 req.page_size = BNXT_PAGE_SHFT;
1349                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1350                 break;
1351         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1352                 req.ring_type = ring_type;
1353                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1354
1355                 mb_pool = bp->rx_queues[0]->mb_pool;
1356                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1357                               RTE_PKTMBUF_HEADROOM;
1358                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1359                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1360
1361                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1362                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1363                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1364                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1365                 break;
1366         default:
1367                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1368                         ring_type);
1369                 HWRM_UNLOCK();
1370                 return -EINVAL;
1371         }
1372         req.enables = rte_cpu_to_le_32(enables);
1373
1374         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1375
1376         if (rc || resp->error_code) {
1377                 if (rc == 0 && resp->error_code)
1378                         rc = rte_le_to_cpu_16(resp->error_code);
1379                 switch (ring_type) {
1380                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1381                         PMD_DRV_LOG(ERR,
1382                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1383                         HWRM_UNLOCK();
1384                         return rc;
1385                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1386                         PMD_DRV_LOG(ERR,
1387                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1388                         HWRM_UNLOCK();
1389                         return rc;
1390                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1391                         PMD_DRV_LOG(ERR,
1392                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1393                                     rc);
1394                         HWRM_UNLOCK();
1395                         return rc;
1396                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1397                         PMD_DRV_LOG(ERR,
1398                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1399                         HWRM_UNLOCK();
1400                         return rc;
1401                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1402                         PMD_DRV_LOG(ERR,
1403                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1404                         HWRM_UNLOCK();
1405                         return rc;
1406                 default:
1407                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1408                         HWRM_UNLOCK();
1409                         return rc;
1410                 }
1411         }
1412
1413         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1414         HWRM_UNLOCK();
1415         return rc;
1416 }
1417
1418 int bnxt_hwrm_ring_free(struct bnxt *bp,
1419                         struct bnxt_ring *ring, uint32_t ring_type)
1420 {
1421         int rc;
1422         struct hwrm_ring_free_input req = {.req_type = 0 };
1423         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1424
1425         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1426
1427         req.ring_type = ring_type;
1428         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1429
1430         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1431
1432         if (rc || resp->error_code) {
1433                 if (rc == 0 && resp->error_code)
1434                         rc = rte_le_to_cpu_16(resp->error_code);
1435                 HWRM_UNLOCK();
1436
1437                 switch (ring_type) {
1438                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1439                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1440                                 rc);
1441                         return rc;
1442                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1443                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1444                                 rc);
1445                         return rc;
1446                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1447                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1448                                 rc);
1449                         return rc;
1450                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1451                         PMD_DRV_LOG(ERR,
1452                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1453                         return rc;
1454                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1455                         PMD_DRV_LOG(ERR,
1456                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1457                         return rc;
1458                 default:
1459                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1460                         return rc;
1461                 }
1462         }
1463         HWRM_UNLOCK();
1464         return 0;
1465 }
1466
1467 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1468 {
1469         int rc = 0;
1470         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1471         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1472
1473         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1474
1475         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1476         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1477         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1478         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1479
1480         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1481
1482         HWRM_CHECK_RESULT();
1483
1484         bp->grp_info[idx].fw_grp_id =
1485             rte_le_to_cpu_16(resp->ring_group_id);
1486
1487         HWRM_UNLOCK();
1488
1489         return rc;
1490 }
1491
1492 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1493 {
1494         int rc;
1495         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1496         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1497
1498         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1499
1500         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1501
1502         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1503
1504         HWRM_CHECK_RESULT();
1505         HWRM_UNLOCK();
1506
1507         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1508         return rc;
1509 }
1510
1511 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1512 {
1513         int rc = 0;
1514         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1515         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1516
1517         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1518                 return rc;
1519
1520         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1521
1522         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1523
1524         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1525
1526         HWRM_CHECK_RESULT();
1527         HWRM_UNLOCK();
1528
1529         return rc;
1530 }
1531
1532 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1533                                 unsigned int idx __rte_unused)
1534 {
1535         int rc;
1536         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1537         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1538
1539         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1540
1541         req.update_period_ms = rte_cpu_to_le_32(0);
1542
1543         req.stats_dma_addr =
1544             rte_cpu_to_le_64(cpr->hw_stats_map);
1545
1546         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1547
1548         HWRM_CHECK_RESULT();
1549
1550         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1551
1552         HWRM_UNLOCK();
1553
1554         return rc;
1555 }
1556
1557 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1558                                 unsigned int idx __rte_unused)
1559 {
1560         int rc;
1561         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1562         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1563
1564         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1565
1566         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1567
1568         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1569
1570         HWRM_CHECK_RESULT();
1571         HWRM_UNLOCK();
1572
1573         return rc;
1574 }
1575
1576 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1577 {
1578         int rc = 0, i, j;
1579         struct hwrm_vnic_alloc_input req = { 0 };
1580         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1581
1582         if (!BNXT_HAS_RING_GRPS(bp))
1583                 goto skip_ring_grps;
1584
1585         /* map ring groups to this vnic */
1586         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1587                 vnic->start_grp_id, vnic->end_grp_id);
1588         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1589                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1590
1591         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1592         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1593         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1594         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1595
1596 skip_ring_grps:
1597         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1598                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1599         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1600
1601         if (vnic->func_default)
1602                 req.flags =
1603                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1604         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1605
1606         HWRM_CHECK_RESULT();
1607
1608         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1609         HWRM_UNLOCK();
1610         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1611         return rc;
1612 }
1613
1614 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1615                                         struct bnxt_vnic_info *vnic,
1616                                         struct bnxt_plcmodes_cfg *pmode)
1617 {
1618         int rc = 0;
1619         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1620         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1621
1622         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1623
1624         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1625
1626         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1627
1628         HWRM_CHECK_RESULT();
1629
1630         pmode->flags = rte_le_to_cpu_32(resp->flags);
1631         /* dflt_vnic bit doesn't exist in the _cfg command */
1632         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1633         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1634         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1635         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1636
1637         HWRM_UNLOCK();
1638
1639         return rc;
1640 }
1641
1642 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1643                                        struct bnxt_vnic_info *vnic,
1644                                        struct bnxt_plcmodes_cfg *pmode)
1645 {
1646         int rc = 0;
1647         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1648         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1649
1650         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1651                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1652                 return rc;
1653         }
1654
1655         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1656
1657         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1658         req.flags = rte_cpu_to_le_32(pmode->flags);
1659         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1660         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1661         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1662         req.enables = rte_cpu_to_le_32(
1663             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1664             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1665             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1666         );
1667
1668         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1669
1670         HWRM_CHECK_RESULT();
1671         HWRM_UNLOCK();
1672
1673         return rc;
1674 }
1675
1676 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1677 {
1678         int rc = 0;
1679         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1680         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1681         struct bnxt_plcmodes_cfg pmodes = { 0 };
1682         uint32_t ctx_enable_flag = 0;
1683         uint32_t enables = 0;
1684
1685         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1686                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1687                 return rc;
1688         }
1689
1690         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1691         if (rc)
1692                 return rc;
1693
1694         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1695
1696         if (BNXT_CHIP_THOR(bp)) {
1697                 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1698                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1699                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1700
1701                 req.default_rx_ring_id =
1702                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1703                 req.default_cmpl_ring_id =
1704                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1705                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1706                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1707                 goto config_mru;
1708         }
1709
1710         /* Only RSS support for now TBD: COS & LB */
1711         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1712         if (vnic->lb_rule != 0xffff)
1713                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1714         if (vnic->cos_rule != 0xffff)
1715                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1716         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1717                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1718                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1719         }
1720         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1721                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1722                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1723         }
1724
1725         enables |= ctx_enable_flag;
1726         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1727         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1728         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1729         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1730
1731 config_mru:
1732         req.enables = rte_cpu_to_le_32(enables);
1733         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1734         req.mru = rte_cpu_to_le_16(vnic->mru);
1735         /* Configure default VNIC only once. */
1736         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1737                 req.flags |=
1738                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1739                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1740         }
1741         if (vnic->vlan_strip)
1742                 req.flags |=
1743                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1744         if (vnic->bd_stall)
1745                 req.flags |=
1746                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1747         if (vnic->roce_dual)
1748                 req.flags |= rte_cpu_to_le_32(
1749                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1750         if (vnic->roce_only)
1751                 req.flags |= rte_cpu_to_le_32(
1752                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1753         if (vnic->rss_dflt_cr)
1754                 req.flags |= rte_cpu_to_le_32(
1755                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1756
1757         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1758
1759         HWRM_CHECK_RESULT();
1760         HWRM_UNLOCK();
1761
1762         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1763
1764         return rc;
1765 }
1766
1767 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1768                 int16_t fw_vf_id)
1769 {
1770         int rc = 0;
1771         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1772         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1773
1774         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1775                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1776                 return rc;
1777         }
1778         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1779
1780         req.enables =
1781                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1782         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1783         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1784
1785         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1786
1787         HWRM_CHECK_RESULT();
1788
1789         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1790         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1791         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1792         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1793         vnic->mru = rte_le_to_cpu_16(resp->mru);
1794         vnic->func_default = rte_le_to_cpu_32(
1795                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1796         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1797                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1798         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1799                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1800         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1801                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1802         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1803                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1804         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1805                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1806
1807         HWRM_UNLOCK();
1808
1809         return rc;
1810 }
1811
1812 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1813                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1814 {
1815         int rc = 0;
1816         uint16_t ctx_id;
1817         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1818         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1819                                                 bp->hwrm_cmd_resp_addr;
1820
1821         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1822
1823         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1824         HWRM_CHECK_RESULT();
1825
1826         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1827         if (!BNXT_HAS_RING_GRPS(bp))
1828                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1829         else if (ctx_idx == 0)
1830                 vnic->rss_rule = ctx_id;
1831
1832         HWRM_UNLOCK();
1833
1834         return rc;
1835 }
1836
1837 static
1838 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1839                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1840 {
1841         int rc = 0;
1842         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1843         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1844                                                 bp->hwrm_cmd_resp_addr;
1845
1846         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1847                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1848                 return rc;
1849         }
1850         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1851
1852         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1853
1854         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1855
1856         HWRM_CHECK_RESULT();
1857         HWRM_UNLOCK();
1858
1859         return rc;
1860 }
1861
1862 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1863 {
1864         int rc = 0;
1865
1866         if (BNXT_CHIP_THOR(bp)) {
1867                 int j;
1868
1869                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1870                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
1871                                                       vnic,
1872                                                       vnic->fw_grp_ids[j]);
1873                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1874                 }
1875                 vnic->num_lb_ctxts = 0;
1876         } else {
1877                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1878                 vnic->rss_rule = INVALID_HW_RING_ID;
1879         }
1880
1881         return rc;
1882 }
1883
1884 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1885 {
1886         int rc = 0;
1887         struct hwrm_vnic_free_input req = {.req_type = 0 };
1888         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1889
1890         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1891                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1892                 return rc;
1893         }
1894
1895         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1896
1897         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1898
1899         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1900
1901         HWRM_CHECK_RESULT();
1902         HWRM_UNLOCK();
1903
1904         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1905         /* Configure default VNIC again if necessary. */
1906         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1907                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1908
1909         return rc;
1910 }
1911
1912 static int
1913 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1914 {
1915         int i;
1916         int rc = 0;
1917         int nr_ctxs = vnic->num_lb_ctxts;
1918         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1919         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1920
1921         for (i = 0; i < nr_ctxs; i++) {
1922                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1923
1924                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1925                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1926                 req.hash_mode_flags = vnic->hash_mode;
1927
1928                 req.hash_key_tbl_addr =
1929                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1930
1931                 req.ring_grp_tbl_addr =
1932                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1933                                          i * HW_HASH_INDEX_SIZE);
1934                 req.ring_table_pair_index = i;
1935                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1936
1937                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1938                                             BNXT_USE_CHIMP_MB);
1939
1940                 HWRM_CHECK_RESULT();
1941                 HWRM_UNLOCK();
1942         }
1943
1944         return rc;
1945 }
1946
1947 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1948                            struct bnxt_vnic_info *vnic)
1949 {
1950         int rc = 0;
1951         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1952         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1953
1954         if (!vnic->rss_table)
1955                 return 0;
1956
1957         if (BNXT_CHIP_THOR(bp))
1958                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1959
1960         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1961
1962         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1963         req.hash_mode_flags = vnic->hash_mode;
1964
1965         req.ring_grp_tbl_addr =
1966             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1967         req.hash_key_tbl_addr =
1968             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1969         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1970         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1971
1972         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1973
1974         HWRM_CHECK_RESULT();
1975         HWRM_UNLOCK();
1976
1977         return rc;
1978 }
1979
1980 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1981                         struct bnxt_vnic_info *vnic)
1982 {
1983         int rc = 0;
1984         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1985         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1986         uint16_t size;
1987
1988         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1989                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1990                 return rc;
1991         }
1992
1993         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1994
1995         req.flags = rte_cpu_to_le_32(
1996                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1997
1998         req.enables = rte_cpu_to_le_32(
1999                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2000
2001         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2002         size -= RTE_PKTMBUF_HEADROOM;
2003         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2004
2005         req.jumbo_thresh = rte_cpu_to_le_16(size);
2006         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2007
2008         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2009
2010         HWRM_CHECK_RESULT();
2011         HWRM_UNLOCK();
2012
2013         return rc;
2014 }
2015
2016 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2017                         struct bnxt_vnic_info *vnic, bool enable)
2018 {
2019         int rc = 0;
2020         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2021         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2022
2023         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2024                 if (enable)
2025                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2026                 return -ENOTSUP;
2027         }
2028
2029         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2030                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2031                 return 0;
2032         }
2033
2034         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2035
2036         if (enable) {
2037                 req.enables = rte_cpu_to_le_32(
2038                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2039                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2040                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2041                 req.flags = rte_cpu_to_le_32(
2042                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2043                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2044                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2045                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2046                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2047                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2048                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2049                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2050                 req.min_agg_len = rte_cpu_to_le_32(512);
2051         }
2052         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2053
2054         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2055
2056         HWRM_CHECK_RESULT();
2057         HWRM_UNLOCK();
2058
2059         return rc;
2060 }
2061
2062 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2063 {
2064         struct hwrm_func_cfg_input req = {0};
2065         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2066         int rc;
2067
2068         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2069         req.enables = rte_cpu_to_le_32(
2070                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2071         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2072         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2073
2074         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2075
2076         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2077         HWRM_CHECK_RESULT();
2078         HWRM_UNLOCK();
2079
2080         bp->pf.vf_info[vf].random_mac = false;
2081
2082         return rc;
2083 }
2084
2085 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2086                                   uint64_t *dropped)
2087 {
2088         int rc = 0;
2089         struct hwrm_func_qstats_input req = {.req_type = 0};
2090         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2091
2092         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2093
2094         req.fid = rte_cpu_to_le_16(fid);
2095
2096         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2097
2098         HWRM_CHECK_RESULT();
2099
2100         if (dropped)
2101                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2102
2103         HWRM_UNLOCK();
2104
2105         return rc;
2106 }
2107
2108 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2109                           struct rte_eth_stats *stats)
2110 {
2111         int rc = 0;
2112         struct hwrm_func_qstats_input req = {.req_type = 0};
2113         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2114
2115         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2116
2117         req.fid = rte_cpu_to_le_16(fid);
2118
2119         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2120
2121         HWRM_CHECK_RESULT();
2122
2123         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2124         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2125         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2126         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2127         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2128         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2129
2130         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2131         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2132         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2133         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2134         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2135         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2136
2137         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2138         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2139         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2140
2141         HWRM_UNLOCK();
2142
2143         return rc;
2144 }
2145
2146 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2147 {
2148         int rc = 0;
2149         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2150         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2151
2152         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2153
2154         req.fid = rte_cpu_to_le_16(fid);
2155
2156         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2157
2158         HWRM_CHECK_RESULT();
2159         HWRM_UNLOCK();
2160
2161         return rc;
2162 }
2163
2164 /*
2165  * HWRM utility functions
2166  */
2167
2168 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2169 {
2170         unsigned int i;
2171         int rc = 0;
2172
2173         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2174                 struct bnxt_tx_queue *txq;
2175                 struct bnxt_rx_queue *rxq;
2176                 struct bnxt_cp_ring_info *cpr;
2177
2178                 if (i >= bp->rx_cp_nr_rings) {
2179                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2180                         cpr = txq->cp_ring;
2181                 } else {
2182                         rxq = bp->rx_queues[i];
2183                         cpr = rxq->cp_ring;
2184                 }
2185
2186                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2187                 if (rc)
2188                         return rc;
2189         }
2190         return 0;
2191 }
2192
2193 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2194 {
2195         int rc;
2196         unsigned int i;
2197         struct bnxt_cp_ring_info *cpr;
2198
2199         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2200
2201                 if (i >= bp->rx_cp_nr_rings) {
2202                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2203                 } else {
2204                         cpr = bp->rx_queues[i]->cp_ring;
2205                         if (BNXT_HAS_RING_GRPS(bp))
2206                                 bp->grp_info[i].fw_stats_ctx = -1;
2207                 }
2208                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2209                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2210                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2211                         if (rc)
2212                                 return rc;
2213                 }
2214         }
2215         return 0;
2216 }
2217
2218 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2219 {
2220         unsigned int i;
2221         int rc = 0;
2222
2223         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2224                 struct bnxt_tx_queue *txq;
2225                 struct bnxt_rx_queue *rxq;
2226                 struct bnxt_cp_ring_info *cpr;
2227
2228                 if (i >= bp->rx_cp_nr_rings) {
2229                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2230                         cpr = txq->cp_ring;
2231                 } else {
2232                         rxq = bp->rx_queues[i];
2233                         cpr = rxq->cp_ring;
2234                 }
2235
2236                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2237
2238                 if (rc)
2239                         return rc;
2240         }
2241         return rc;
2242 }
2243
2244 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2245 {
2246         uint16_t idx;
2247         uint32_t rc = 0;
2248
2249         if (!BNXT_HAS_RING_GRPS(bp))
2250                 return 0;
2251
2252         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2253
2254                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2255                         continue;
2256
2257                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2258
2259                 if (rc)
2260                         return rc;
2261         }
2262         return rc;
2263 }
2264
2265 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2266 {
2267         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2268
2269         bnxt_hwrm_ring_free(bp, cp_ring,
2270                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2271         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2272         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2273                                      sizeof(*cpr->cp_desc_ring));
2274         cpr->cp_raw_cons = 0;
2275         cpr->valid = 0;
2276 }
2277
2278 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2279 {
2280         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2281
2282         bnxt_hwrm_ring_free(bp, cp_ring,
2283                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2284         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2285         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2286                         sizeof(*cpr->cp_desc_ring));
2287         cpr->cp_raw_cons = 0;
2288         cpr->valid = 0;
2289 }
2290
2291 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2292 {
2293         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2294         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2295         struct bnxt_ring *ring = rxr->rx_ring_struct;
2296         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2297
2298         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2299                 bnxt_hwrm_ring_free(bp, ring,
2300                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2301                 ring->fw_ring_id = INVALID_HW_RING_ID;
2302                 if (BNXT_HAS_RING_GRPS(bp))
2303                         bp->grp_info[queue_index].rx_fw_ring_id =
2304                                                         INVALID_HW_RING_ID;
2305                 memset(rxr->rx_desc_ring, 0,
2306                        rxr->rx_ring_struct->ring_size *
2307                        sizeof(*rxr->rx_desc_ring));
2308                 memset(rxr->rx_buf_ring, 0,
2309                        rxr->rx_ring_struct->ring_size *
2310                        sizeof(*rxr->rx_buf_ring));
2311                 rxr->rx_prod = 0;
2312         }
2313         ring = rxr->ag_ring_struct;
2314         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2315                 bnxt_hwrm_ring_free(bp, ring,
2316                                     BNXT_CHIP_THOR(bp) ?
2317                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2318                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2319                 ring->fw_ring_id = INVALID_HW_RING_ID;
2320                 memset(rxr->ag_buf_ring, 0,
2321                        rxr->ag_ring_struct->ring_size *
2322                        sizeof(*rxr->ag_buf_ring));
2323                 rxr->ag_prod = 0;
2324                 if (BNXT_HAS_RING_GRPS(bp))
2325                         bp->grp_info[queue_index].ag_fw_ring_id =
2326                                                         INVALID_HW_RING_ID;
2327         }
2328         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2329                 bnxt_free_cp_ring(bp, cpr);
2330
2331         if (BNXT_HAS_RING_GRPS(bp))
2332                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2333 }
2334
2335 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2336 {
2337         unsigned int i;
2338
2339         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2340                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2341                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2342                 struct bnxt_ring *ring = txr->tx_ring_struct;
2343                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2344
2345                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2346                         bnxt_hwrm_ring_free(bp, ring,
2347                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2348                         ring->fw_ring_id = INVALID_HW_RING_ID;
2349                         memset(txr->tx_desc_ring, 0,
2350                                         txr->tx_ring_struct->ring_size *
2351                                         sizeof(*txr->tx_desc_ring));
2352                         memset(txr->tx_buf_ring, 0,
2353                                         txr->tx_ring_struct->ring_size *
2354                                         sizeof(*txr->tx_buf_ring));
2355                         txr->tx_prod = 0;
2356                         txr->tx_cons = 0;
2357                 }
2358                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2359                         bnxt_free_cp_ring(bp, cpr);
2360                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2361                 }
2362         }
2363
2364         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2365                 bnxt_free_hwrm_rx_ring(bp, i);
2366
2367         return 0;
2368 }
2369
2370 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2371 {
2372         uint16_t i;
2373         uint32_t rc = 0;
2374
2375         if (!BNXT_HAS_RING_GRPS(bp))
2376                 return 0;
2377
2378         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2379                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2380                 if (rc)
2381                         return rc;
2382         }
2383         return rc;
2384 }
2385
2386 void bnxt_free_hwrm_resources(struct bnxt *bp)
2387 {
2388         /* Release memzone */
2389         rte_free(bp->hwrm_cmd_resp_addr);
2390         rte_free(bp->hwrm_short_cmd_req_addr);
2391         bp->hwrm_cmd_resp_addr = NULL;
2392         bp->hwrm_short_cmd_req_addr = NULL;
2393         bp->hwrm_cmd_resp_dma_addr = 0;
2394         bp->hwrm_short_cmd_req_dma_addr = 0;
2395 }
2396
2397 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2398 {
2399         struct rte_pci_device *pdev = bp->pdev;
2400         char type[RTE_MEMZONE_NAMESIZE];
2401
2402         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2403                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2404         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2405         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2406         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2407         if (bp->hwrm_cmd_resp_addr == NULL)
2408                 return -ENOMEM;
2409         bp->hwrm_cmd_resp_dma_addr =
2410                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2411         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2412                 PMD_DRV_LOG(ERR,
2413                         "unable to map response address to physical memory\n");
2414                 return -ENOMEM;
2415         }
2416         rte_spinlock_init(&bp->hwrm_lock);
2417
2418         return 0;
2419 }
2420
2421 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2422 {
2423         struct bnxt_filter_info *filter;
2424         int rc = 0;
2425
2426         STAILQ_FOREACH(filter, &vnic->filter, next) {
2427                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2428                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2429                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2430                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2431                 else
2432                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2433                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2434                 bnxt_free_filter(bp, filter);
2435                 //if (rc)
2436                         //break;
2437         }
2438         return rc;
2439 }
2440
2441 static int
2442 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2443 {
2444         struct bnxt_filter_info *filter;
2445         struct rte_flow *flow;
2446         int rc = 0;
2447
2448         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2449                 flow = STAILQ_FIRST(&vnic->flow_list);
2450                 filter = flow->filter;
2451                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2452                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2453                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2454                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2455                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2456                 else
2457                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2458
2459                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2460                 rte_free(flow);
2461                 //if (rc)
2462                         //break;
2463         }
2464         return rc;
2465 }
2466
2467 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2468 {
2469         struct bnxt_filter_info *filter;
2470         int rc = 0;
2471
2472         STAILQ_FOREACH(filter, &vnic->filter, next) {
2473                 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2474                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2475                                                      filter);
2476                 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2477                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2478                                                          filter);
2479                 } else {
2480                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2481                                                      filter);
2482                         if (!rc)
2483                                 filter->dflt = 1;
2484                 }
2485                 if (rc)
2486                         break;
2487         }
2488         return rc;
2489 }
2490
2491 void bnxt_free_tunnel_ports(struct bnxt *bp)
2492 {
2493         if (bp->vxlan_port_cnt)
2494                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2495                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2496         bp->vxlan_port = 0;
2497         if (bp->geneve_port_cnt)
2498                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2499                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2500         bp->geneve_port = 0;
2501 }
2502
2503 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2504 {
2505         int i;
2506
2507         if (bp->vnic_info == NULL)
2508                 return;
2509
2510         /*
2511          * Cleanup VNICs in reverse order, to make sure the L2 filter
2512          * from vnic0 is last to be cleaned up.
2513          */
2514         for (i = bp->max_vnics - 1; i >= 0; i--) {
2515                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2516
2517                 // If the VNIC ID is invalid we are not currently using the VNIC
2518                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2519                         continue;
2520
2521                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2522
2523                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2524
2525                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2526
2527                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2528
2529                 bnxt_hwrm_vnic_free(bp, vnic);
2530
2531                 rte_free(vnic->fw_grp_ids);
2532         }
2533         /* Ring resources */
2534         bnxt_free_all_hwrm_rings(bp);
2535         bnxt_free_all_hwrm_ring_grps(bp);
2536         bnxt_free_all_hwrm_stat_ctxs(bp);
2537         bnxt_free_tunnel_ports(bp);
2538 }
2539
2540 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2541 {
2542         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2543
2544         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2545                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2546
2547         switch (conf_link_speed) {
2548         case ETH_LINK_SPEED_10M_HD:
2549         case ETH_LINK_SPEED_100M_HD:
2550                 /* FALLTHROUGH */
2551                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2552         }
2553         return hw_link_duplex;
2554 }
2555
2556 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2557 {
2558         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2559 }
2560
2561 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2562 {
2563         uint16_t eth_link_speed = 0;
2564
2565         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2566                 return ETH_LINK_SPEED_AUTONEG;
2567
2568         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2569         case ETH_LINK_SPEED_100M:
2570         case ETH_LINK_SPEED_100M_HD:
2571                 /* FALLTHROUGH */
2572                 eth_link_speed =
2573                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2574                 break;
2575         case ETH_LINK_SPEED_1G:
2576                 eth_link_speed =
2577                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2578                 break;
2579         case ETH_LINK_SPEED_2_5G:
2580                 eth_link_speed =
2581                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2582                 break;
2583         case ETH_LINK_SPEED_10G:
2584                 eth_link_speed =
2585                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2586                 break;
2587         case ETH_LINK_SPEED_20G:
2588                 eth_link_speed =
2589                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2590                 break;
2591         case ETH_LINK_SPEED_25G:
2592                 eth_link_speed =
2593                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2594                 break;
2595         case ETH_LINK_SPEED_40G:
2596                 eth_link_speed =
2597                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2598                 break;
2599         case ETH_LINK_SPEED_50G:
2600                 eth_link_speed =
2601                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2602                 break;
2603         case ETH_LINK_SPEED_100G:
2604                 eth_link_speed =
2605                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2606                 break;
2607         default:
2608                 PMD_DRV_LOG(ERR,
2609                         "Unsupported link speed %d; default to AUTO\n",
2610                         conf_link_speed);
2611                 break;
2612         }
2613         return eth_link_speed;
2614 }
2615
2616 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2617                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2618                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2619                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2620
2621 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2622 {
2623         uint32_t one_speed;
2624
2625         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2626                 return 0;
2627
2628         if (link_speed & ETH_LINK_SPEED_FIXED) {
2629                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2630
2631                 if (one_speed & (one_speed - 1)) {
2632                         PMD_DRV_LOG(ERR,
2633                                 "Invalid advertised speeds (%u) for port %u\n",
2634                                 link_speed, port_id);
2635                         return -EINVAL;
2636                 }
2637                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2638                         PMD_DRV_LOG(ERR,
2639                                 "Unsupported advertised speed (%u) for port %u\n",
2640                                 link_speed, port_id);
2641                         return -EINVAL;
2642                 }
2643         } else {
2644                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2645                         PMD_DRV_LOG(ERR,
2646                                 "Unsupported advertised speeds (%u) for port %u\n",
2647                                 link_speed, port_id);
2648                         return -EINVAL;
2649                 }
2650         }
2651         return 0;
2652 }
2653
2654 static uint16_t
2655 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2656 {
2657         uint16_t ret = 0;
2658
2659         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2660                 if (bp->link_info.support_speeds)
2661                         return bp->link_info.support_speeds;
2662                 link_speed = BNXT_SUPPORTED_SPEEDS;
2663         }
2664
2665         if (link_speed & ETH_LINK_SPEED_100M)
2666                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2667         if (link_speed & ETH_LINK_SPEED_100M_HD)
2668                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2669         if (link_speed & ETH_LINK_SPEED_1G)
2670                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2671         if (link_speed & ETH_LINK_SPEED_2_5G)
2672                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2673         if (link_speed & ETH_LINK_SPEED_10G)
2674                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2675         if (link_speed & ETH_LINK_SPEED_20G)
2676                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2677         if (link_speed & ETH_LINK_SPEED_25G)
2678                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2679         if (link_speed & ETH_LINK_SPEED_40G)
2680                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2681         if (link_speed & ETH_LINK_SPEED_50G)
2682                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2683         if (link_speed & ETH_LINK_SPEED_100G)
2684                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2685         return ret;
2686 }
2687
2688 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2689 {
2690         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2691
2692         switch (hw_link_speed) {
2693         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2694                 eth_link_speed = ETH_SPEED_NUM_100M;
2695                 break;
2696         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2697                 eth_link_speed = ETH_SPEED_NUM_1G;
2698                 break;
2699         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2700                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2701                 break;
2702         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2703                 eth_link_speed = ETH_SPEED_NUM_10G;
2704                 break;
2705         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2706                 eth_link_speed = ETH_SPEED_NUM_20G;
2707                 break;
2708         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2709                 eth_link_speed = ETH_SPEED_NUM_25G;
2710                 break;
2711         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2712                 eth_link_speed = ETH_SPEED_NUM_40G;
2713                 break;
2714         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2715                 eth_link_speed = ETH_SPEED_NUM_50G;
2716                 break;
2717         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2718                 eth_link_speed = ETH_SPEED_NUM_100G;
2719                 break;
2720         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2721         default:
2722                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2723                         hw_link_speed);
2724                 break;
2725         }
2726         return eth_link_speed;
2727 }
2728
2729 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2730 {
2731         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2732
2733         switch (hw_link_duplex) {
2734         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2735         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2736                 /* FALLTHROUGH */
2737                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2738                 break;
2739         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2740                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2741                 break;
2742         default:
2743                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2744                         hw_link_duplex);
2745                 break;
2746         }
2747         return eth_link_duplex;
2748 }
2749
2750 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2751 {
2752         int rc = 0;
2753         struct bnxt_link_info *link_info = &bp->link_info;
2754
2755         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2756         if (rc) {
2757                 PMD_DRV_LOG(ERR,
2758                         "Get link config failed with rc %d\n", rc);
2759                 goto exit;
2760         }
2761         if (link_info->link_speed)
2762                 link->link_speed =
2763                         bnxt_parse_hw_link_speed(link_info->link_speed);
2764         else
2765                 link->link_speed = ETH_SPEED_NUM_NONE;
2766         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2767         link->link_status = link_info->link_up;
2768         link->link_autoneg = link_info->auto_mode ==
2769                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2770                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2771 exit:
2772         return rc;
2773 }
2774
2775 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2776 {
2777         int rc = 0;
2778         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2779         struct bnxt_link_info link_req;
2780         uint16_t speed, autoneg;
2781
2782         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2783                 return 0;
2784
2785         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2786                         bp->eth_dev->data->port_id);
2787         if (rc)
2788                 goto error;
2789
2790         memset(&link_req, 0, sizeof(link_req));
2791         link_req.link_up = link_up;
2792         if (!link_up)
2793                 goto port_phy_cfg;
2794
2795         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2796         if (BNXT_CHIP_THOR(bp) &&
2797             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2798                 /* 40G is not supported as part of media auto detect.
2799                  * The speed should be forced and autoneg disabled
2800                  * to configure 40G speed.
2801                  */
2802                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2803                 autoneg = 0;
2804         }
2805
2806         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2807         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2808         /* Autoneg can be done only when the FW allows.
2809          * When user configures fixed speed of 40G and later changes to
2810          * any other speed, auto_link_speed/force_link_speed is still set
2811          * to 40G until link comes up at new speed.
2812          */
2813         if (autoneg == 1 &&
2814             !(!BNXT_CHIP_THOR(bp) &&
2815               (bp->link_info.auto_link_speed ||
2816                bp->link_info.force_link_speed))) {
2817                 link_req.phy_flags |=
2818                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2819                 link_req.auto_link_speed_mask =
2820                         bnxt_parse_eth_link_speed_mask(bp,
2821                                                        dev_conf->link_speeds);
2822         } else {
2823                 if (bp->link_info.phy_type ==
2824                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2825                     bp->link_info.phy_type ==
2826                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2827                     bp->link_info.media_type ==
2828                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2829                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2830                         return -EINVAL;
2831                 }
2832
2833                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2834                 /* If user wants a particular speed try that first. */
2835                 if (speed)
2836                         link_req.link_speed = speed;
2837                 else if (bp->link_info.force_link_speed)
2838                         link_req.link_speed = bp->link_info.force_link_speed;
2839                 else
2840                         link_req.link_speed = bp->link_info.auto_link_speed;
2841         }
2842         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2843         link_req.auto_pause = bp->link_info.auto_pause;
2844         link_req.force_pause = bp->link_info.force_pause;
2845
2846 port_phy_cfg:
2847         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2848         if (rc) {
2849                 PMD_DRV_LOG(ERR,
2850                         "Set link config failed with rc %d\n", rc);
2851         }
2852
2853 error:
2854         return rc;
2855 }
2856
2857 /* JIRA 22088 */
2858 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2859 {
2860         struct hwrm_func_qcfg_input req = {0};
2861         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2862         uint16_t flags;
2863         int rc = 0;
2864
2865         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2866         req.fid = rte_cpu_to_le_16(0xffff);
2867
2868         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2869
2870         HWRM_CHECK_RESULT();
2871
2872         /* Hard Coded.. 0xfff VLAN ID mask */
2873         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2874         flags = rte_le_to_cpu_16(resp->flags);
2875         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2876                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2877
2878         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2879                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2880                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2881         } else if (BNXT_VF(bp) &&
2882                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2883                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2884                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2885         }
2886
2887         if (mtu)
2888                 *mtu = resp->mtu;
2889
2890         switch (resp->port_partition_type) {
2891         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2892         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2893         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2894                 /* FALLTHROUGH */
2895                 bp->port_partition_type = resp->port_partition_type;
2896                 break;
2897         default:
2898                 bp->port_partition_type = 0;
2899                 break;
2900         }
2901
2902         HWRM_UNLOCK();
2903
2904         return rc;
2905 }
2906
2907 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2908                                    struct hwrm_func_qcaps_output *qcaps)
2909 {
2910         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2911         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2912                sizeof(qcaps->mac_address));
2913         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2914         qcaps->max_rx_rings = fcfg->num_rx_rings;
2915         qcaps->max_tx_rings = fcfg->num_tx_rings;
2916         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2917         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2918         qcaps->max_vfs = 0;
2919         qcaps->first_vf_id = 0;
2920         qcaps->max_vnics = fcfg->num_vnics;
2921         qcaps->max_decap_records = 0;
2922         qcaps->max_encap_records = 0;
2923         qcaps->max_tx_wm_flows = 0;
2924         qcaps->max_tx_em_flows = 0;
2925         qcaps->max_rx_wm_flows = 0;
2926         qcaps->max_rx_em_flows = 0;
2927         qcaps->max_flow_id = 0;
2928         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2929         qcaps->max_sp_tx_rings = 0;
2930         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2931 }
2932
2933 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2934 {
2935         struct hwrm_func_cfg_input req = {0};
2936         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2937         uint32_t enables;
2938         int rc;
2939
2940         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2941                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2942                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2943                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2944                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2945                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2946                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2947                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2948                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2949
2950         if (BNXT_HAS_RING_GRPS(bp)) {
2951                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2952                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2953         } else if (BNXT_HAS_NQ(bp)) {
2954                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2955                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2956         }
2957
2958         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2959         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2960         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2961                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2962                                    BNXT_NUM_VLANS);
2963         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2964         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2965         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2966         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2967         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2968         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2969         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2970         req.fid = rte_cpu_to_le_16(0xffff);
2971         req.enables = rte_cpu_to_le_32(enables);
2972
2973         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2974
2975         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2976
2977         HWRM_CHECK_RESULT();
2978         HWRM_UNLOCK();
2979
2980         return rc;
2981 }
2982
2983 static void populate_vf_func_cfg_req(struct bnxt *bp,
2984                                      struct hwrm_func_cfg_input *req,
2985                                      int num_vfs)
2986 {
2987         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2988                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2989                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2990                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2991                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2992                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2993                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2994                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2995                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2996                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2997
2998         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2999                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3000                                     BNXT_NUM_VLANS);
3001         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3002                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3003                                     BNXT_NUM_VLANS);
3004         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3005                                                 (num_vfs + 1));
3006         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3007         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3008                                                (num_vfs + 1));
3009         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3010         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3011         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3012         /* TODO: For now, do not support VMDq/RFS on VFs. */
3013         req->num_vnics = rte_cpu_to_le_16(1);
3014         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3015                                                  (num_vfs + 1));
3016 }
3017
3018 static void add_random_mac_if_needed(struct bnxt *bp,
3019                                      struct hwrm_func_cfg_input *cfg_req,
3020                                      int vf)
3021 {
3022         struct rte_ether_addr mac;
3023
3024         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3025                 return;
3026
3027         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3028                 cfg_req->enables |=
3029                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3030                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3031                 bp->pf.vf_info[vf].random_mac = true;
3032         } else {
3033                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3034                         RTE_ETHER_ADDR_LEN);
3035         }
3036 }
3037
3038 static void reserve_resources_from_vf(struct bnxt *bp,
3039                                       struct hwrm_func_cfg_input *cfg_req,
3040                                       int vf)
3041 {
3042         struct hwrm_func_qcaps_input req = {0};
3043         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3044         int rc;
3045
3046         /* Get the actual allocated values now */
3047         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3048         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3049         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3050
3051         if (rc) {
3052                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3053                 copy_func_cfg_to_qcaps(cfg_req, resp);
3054         } else if (resp->error_code) {
3055                 rc = rte_le_to_cpu_16(resp->error_code);
3056                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3057                 copy_func_cfg_to_qcaps(cfg_req, resp);
3058         }
3059
3060         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3061         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3062         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3063         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3064         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3065         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3066         /*
3067          * TODO: While not supporting VMDq with VFs, max_vnics is always
3068          * forced to 1 in this case
3069          */
3070         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3071         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3072
3073         HWRM_UNLOCK();
3074 }
3075
3076 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3077 {
3078         struct hwrm_func_qcfg_input req = {0};
3079         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3080         int rc;
3081
3082         /* Check for zero MAC address */
3083         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3084         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3085         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3086         HWRM_CHECK_RESULT();
3087         rc = rte_le_to_cpu_16(resp->vlan);
3088
3089         HWRM_UNLOCK();
3090
3091         return rc;
3092 }
3093
3094 static int update_pf_resource_max(struct bnxt *bp)
3095 {
3096         struct hwrm_func_qcfg_input req = {0};
3097         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3098         int rc;
3099
3100         /* And copy the allocated numbers into the pf struct */
3101         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3102         req.fid = rte_cpu_to_le_16(0xffff);
3103         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3104         HWRM_CHECK_RESULT();
3105
3106         /* Only TX ring value reflects actual allocation? TODO */
3107         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3108         bp->pf.evb_mode = resp->evb_mode;
3109
3110         HWRM_UNLOCK();
3111
3112         return rc;
3113 }
3114
3115 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3116 {
3117         int rc;
3118
3119         if (!BNXT_PF(bp)) {
3120                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3121                 return -EINVAL;
3122         }
3123
3124         rc = bnxt_hwrm_func_qcaps(bp);
3125         if (rc)
3126                 return rc;
3127
3128         bp->pf.func_cfg_flags &=
3129                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3130                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3131         bp->pf.func_cfg_flags |=
3132                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3133         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3134         rc = __bnxt_hwrm_func_qcaps(bp);
3135         return rc;
3136 }
3137
3138 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3139 {
3140         struct hwrm_func_cfg_input req = {0};
3141         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3142         int i;
3143         size_t sz;
3144         int rc = 0;
3145         size_t req_buf_sz;
3146
3147         if (!BNXT_PF(bp)) {
3148                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3149                 return -EINVAL;
3150         }
3151
3152         rc = bnxt_hwrm_func_qcaps(bp);
3153
3154         if (rc)
3155                 return rc;
3156
3157         bp->pf.active_vfs = num_vfs;
3158
3159         /*
3160          * First, configure the PF to only use one TX ring.  This ensures that
3161          * there are enough rings for all VFs.
3162          *
3163          * If we don't do this, when we call func_alloc() later, we will lock
3164          * extra rings to the PF that won't be available during func_cfg() of
3165          * the VFs.
3166          *
3167          * This has been fixed with firmware versions above 20.6.54
3168          */
3169         bp->pf.func_cfg_flags &=
3170                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3171                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3172         bp->pf.func_cfg_flags |=
3173                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3174         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3175         if (rc)
3176                 return rc;
3177
3178         /*
3179          * Now, create and register a buffer to hold forwarded VF requests
3180          */
3181         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3182         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3183                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3184         if (bp->pf.vf_req_buf == NULL) {
3185                 rc = -ENOMEM;
3186                 goto error_free;
3187         }
3188         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3189                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3190         for (i = 0; i < num_vfs; i++)
3191                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3192                                         (i * HWRM_MAX_REQ_LEN);
3193
3194         rc = bnxt_hwrm_func_buf_rgtr(bp);
3195         if (rc)
3196                 goto error_free;
3197
3198         populate_vf_func_cfg_req(bp, &req, num_vfs);
3199
3200         bp->pf.active_vfs = 0;
3201         for (i = 0; i < num_vfs; i++) {
3202                 add_random_mac_if_needed(bp, &req, i);
3203
3204                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3205                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3206                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3207                 rc = bnxt_hwrm_send_message(bp,
3208                                             &req,
3209                                             sizeof(req),
3210                                             BNXT_USE_CHIMP_MB);
3211
3212                 /* Clear enable flag for next pass */
3213                 req.enables &= ~rte_cpu_to_le_32(
3214                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3215
3216                 if (rc || resp->error_code) {
3217                         PMD_DRV_LOG(ERR,
3218                                 "Failed to initizlie VF %d\n", i);
3219                         PMD_DRV_LOG(ERR,
3220                                 "Not all VFs available. (%d, %d)\n",
3221                                 rc, resp->error_code);
3222                         HWRM_UNLOCK();
3223                         break;
3224                 }
3225
3226                 HWRM_UNLOCK();
3227
3228                 reserve_resources_from_vf(bp, &req, i);
3229                 bp->pf.active_vfs++;
3230                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3231         }
3232
3233         /*
3234          * Now configure the PF to use "the rest" of the resources
3235          * We're using STD_TX_RING_MODE here though which will limit the TX
3236          * rings.  This will allow QoS to function properly.  Not setting this
3237          * will cause PF rings to break bandwidth settings.
3238          */
3239         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3240         if (rc)
3241                 goto error_free;
3242
3243         rc = update_pf_resource_max(bp);
3244         if (rc)
3245                 goto error_free;
3246
3247         return rc;
3248
3249 error_free:
3250         bnxt_hwrm_func_buf_unrgtr(bp);
3251         return rc;
3252 }
3253
3254 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3255 {
3256         struct hwrm_func_cfg_input req = {0};
3257         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3258         int rc;
3259
3260         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3261
3262         req.fid = rte_cpu_to_le_16(0xffff);
3263         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3264         req.evb_mode = bp->pf.evb_mode;
3265
3266         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3267         HWRM_CHECK_RESULT();
3268         HWRM_UNLOCK();
3269
3270         return rc;
3271 }
3272
3273 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3274                                 uint8_t tunnel_type)
3275 {
3276         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3277         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3278         int rc = 0;
3279
3280         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3281         req.tunnel_type = tunnel_type;
3282         req.tunnel_dst_port_val = port;
3283         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3284         HWRM_CHECK_RESULT();
3285
3286         switch (tunnel_type) {
3287         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3288                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3289                 bp->vxlan_port = port;
3290                 break;
3291         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3292                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3293                 bp->geneve_port = port;
3294                 break;
3295         default:
3296                 break;
3297         }
3298
3299         HWRM_UNLOCK();
3300
3301         return rc;
3302 }
3303
3304 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3305                                 uint8_t tunnel_type)
3306 {
3307         struct hwrm_tunnel_dst_port_free_input req = {0};
3308         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3309         int rc = 0;
3310
3311         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3312
3313         req.tunnel_type = tunnel_type;
3314         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3315         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3316
3317         HWRM_CHECK_RESULT();
3318         HWRM_UNLOCK();
3319
3320         return rc;
3321 }
3322
3323 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3324                                         uint32_t flags)
3325 {
3326         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3327         struct hwrm_func_cfg_input req = {0};
3328         int rc;
3329
3330         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3331
3332         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3333         req.flags = rte_cpu_to_le_32(flags);
3334         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3335
3336         HWRM_CHECK_RESULT();
3337         HWRM_UNLOCK();
3338
3339         return rc;
3340 }
3341
3342 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3343 {
3344         uint32_t *flag = flagp;
3345
3346         vnic->flags = *flag;
3347 }
3348
3349 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3350 {
3351         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3352 }
3353
3354 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3355 {
3356         int rc = 0;
3357         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3358         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3359
3360         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3361
3362         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3363         req.req_buf_page_size = rte_cpu_to_le_16(
3364                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3365         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3366         req.req_buf_page_addr0 =
3367                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3368         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3369                 PMD_DRV_LOG(ERR,
3370                         "unable to map buffer address to physical memory\n");
3371                 return -ENOMEM;
3372         }
3373
3374         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3375
3376         HWRM_CHECK_RESULT();
3377         HWRM_UNLOCK();
3378
3379         return rc;
3380 }
3381
3382 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3383 {
3384         int rc = 0;
3385         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3386         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3387
3388         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3389                 return 0;
3390
3391         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3392
3393         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3394
3395         HWRM_CHECK_RESULT();
3396         HWRM_UNLOCK();
3397
3398         return rc;
3399 }
3400
3401 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3402 {
3403         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3404         struct hwrm_func_cfg_input req = {0};
3405         int rc;
3406
3407         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3408
3409         req.fid = rte_cpu_to_le_16(0xffff);
3410         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3411         req.enables = rte_cpu_to_le_32(
3412                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3413         req.async_event_cr = rte_cpu_to_le_16(
3414                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3415         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3416
3417         HWRM_CHECK_RESULT();
3418         HWRM_UNLOCK();
3419
3420         return rc;
3421 }
3422
3423 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3424 {
3425         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3426         struct hwrm_func_vf_cfg_input req = {0};
3427         int rc;
3428
3429         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3430
3431         req.enables = rte_cpu_to_le_32(
3432                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3433         req.async_event_cr = rte_cpu_to_le_16(
3434                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3435         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3436
3437         HWRM_CHECK_RESULT();
3438         HWRM_UNLOCK();
3439
3440         return rc;
3441 }
3442
3443 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3444 {
3445         struct hwrm_func_cfg_input req = {0};
3446         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3447         uint16_t dflt_vlan, fid;
3448         uint32_t func_cfg_flags;
3449         int rc = 0;
3450
3451         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3452
3453         if (is_vf) {
3454                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3455                 fid = bp->pf.vf_info[vf].fid;
3456                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3457         } else {
3458                 fid = rte_cpu_to_le_16(0xffff);
3459                 func_cfg_flags = bp->pf.func_cfg_flags;
3460                 dflt_vlan = bp->vlan;
3461         }
3462
3463         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3464         req.fid = rte_cpu_to_le_16(fid);
3465         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3466         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3467
3468         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3469
3470         HWRM_CHECK_RESULT();
3471         HWRM_UNLOCK();
3472
3473         return rc;
3474 }
3475
3476 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3477                         uint16_t max_bw, uint16_t enables)
3478 {
3479         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3480         struct hwrm_func_cfg_input req = {0};
3481         int rc;
3482
3483         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3484
3485         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3486         req.enables |= rte_cpu_to_le_32(enables);
3487         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3488         req.max_bw = rte_cpu_to_le_32(max_bw);
3489         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3490
3491         HWRM_CHECK_RESULT();
3492         HWRM_UNLOCK();
3493
3494         return rc;
3495 }
3496
3497 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3498 {
3499         struct hwrm_func_cfg_input req = {0};
3500         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3501         int rc = 0;
3502
3503         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3504
3505         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3506         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3507         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3508         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3509
3510         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3511
3512         HWRM_CHECK_RESULT();
3513         HWRM_UNLOCK();
3514
3515         return rc;
3516 }
3517
3518 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3519 {
3520         int rc;
3521
3522         if (BNXT_PF(bp))
3523                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3524         else
3525                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3526
3527         return rc;
3528 }
3529
3530 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3531                               void *encaped, size_t ec_size)
3532 {
3533         int rc = 0;
3534         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3535         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3536
3537         if (ec_size > sizeof(req.encap_request))
3538                 return -1;
3539
3540         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3541
3542         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3543         memcpy(req.encap_request, encaped, ec_size);
3544
3545         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3546
3547         HWRM_CHECK_RESULT();
3548         HWRM_UNLOCK();
3549
3550         return rc;
3551 }
3552
3553 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3554                                        struct rte_ether_addr *mac)
3555 {
3556         struct hwrm_func_qcfg_input req = {0};
3557         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3558         int rc;
3559
3560         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3561
3562         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3563         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3564
3565         HWRM_CHECK_RESULT();
3566
3567         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3568
3569         HWRM_UNLOCK();
3570
3571         return rc;
3572 }
3573
3574 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3575                             void *encaped, size_t ec_size)
3576 {
3577         int rc = 0;
3578         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3579         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3580
3581         if (ec_size > sizeof(req.encap_request))
3582                 return -1;
3583
3584         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3585
3586         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3587         memcpy(req.encap_request, encaped, ec_size);
3588
3589         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3590
3591         HWRM_CHECK_RESULT();
3592         HWRM_UNLOCK();
3593
3594         return rc;
3595 }
3596
3597 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3598                          struct rte_eth_stats *stats, uint8_t rx)
3599 {
3600         int rc = 0;
3601         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3602         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3603
3604         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3605
3606         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3607
3608         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3609
3610         HWRM_CHECK_RESULT();
3611
3612         if (rx) {
3613                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3614                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3615                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3616                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3617                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3618                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3619                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3620                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3621         } else {
3622                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3623                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3624                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3625                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3626                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3627                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3628         }
3629
3630
3631         HWRM_UNLOCK();
3632
3633         return rc;
3634 }
3635
3636 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3637 {
3638         struct hwrm_port_qstats_input req = {0};
3639         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3640         struct bnxt_pf_info *pf = &bp->pf;
3641         int rc;
3642
3643         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3644
3645         req.port_id = rte_cpu_to_le_16(pf->port_id);
3646         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3647         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3648         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3649
3650         HWRM_CHECK_RESULT();
3651         HWRM_UNLOCK();
3652
3653         return rc;
3654 }
3655
3656 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3657 {
3658         struct hwrm_port_clr_stats_input req = {0};
3659         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3660         struct bnxt_pf_info *pf = &bp->pf;
3661         int rc;
3662
3663         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3664         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3665             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3666                 return 0;
3667
3668         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3669
3670         req.port_id = rte_cpu_to_le_16(pf->port_id);
3671         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3672
3673         HWRM_CHECK_RESULT();
3674         HWRM_UNLOCK();
3675
3676         return rc;
3677 }
3678
3679 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3680 {
3681         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3682         struct hwrm_port_led_qcaps_input req = {0};
3683         int rc;
3684
3685         if (BNXT_VF(bp))
3686                 return 0;
3687
3688         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3689         req.port_id = bp->pf.port_id;
3690         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3691
3692         HWRM_CHECK_RESULT();
3693
3694         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3695                 unsigned int i;
3696
3697                 bp->num_leds = resp->num_leds;
3698                 memcpy(bp->leds, &resp->led0_id,
3699                         sizeof(bp->leds[0]) * bp->num_leds);
3700                 for (i = 0; i < bp->num_leds; i++) {
3701                         struct bnxt_led_info *led = &bp->leds[i];
3702
3703                         uint16_t caps = led->led_state_caps;
3704
3705                         if (!led->led_group_id ||
3706                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3707                                 bp->num_leds = 0;
3708                                 break;
3709                         }
3710                 }
3711         }
3712
3713         HWRM_UNLOCK();
3714
3715         return rc;
3716 }
3717
3718 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3719 {
3720         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3721         struct hwrm_port_led_cfg_input req = {0};
3722         struct bnxt_led_cfg *led_cfg;
3723         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3724         uint16_t duration = 0;
3725         int rc, i;
3726
3727         if (!bp->num_leds || BNXT_VF(bp))
3728                 return -EOPNOTSUPP;
3729
3730         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3731
3732         if (led_on) {
3733                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3734                 duration = rte_cpu_to_le_16(500);
3735         }
3736         req.port_id = bp->pf.port_id;
3737         req.num_leds = bp->num_leds;
3738         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3739         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3740                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3741                 led_cfg->led_id = bp->leds[i].led_id;
3742                 led_cfg->led_state = led_state;
3743                 led_cfg->led_blink_on = duration;
3744                 led_cfg->led_blink_off = duration;
3745                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3746         }
3747
3748         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3749
3750         HWRM_CHECK_RESULT();
3751         HWRM_UNLOCK();
3752
3753         return rc;
3754 }
3755
3756 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3757                                uint32_t *length)
3758 {
3759         int rc;
3760         struct hwrm_nvm_get_dir_info_input req = {0};
3761         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3762
3763         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3764
3765         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3766
3767         HWRM_CHECK_RESULT();
3768
3769         *entries = rte_le_to_cpu_32(resp->entries);
3770         *length = rte_le_to_cpu_32(resp->entry_length);
3771
3772         HWRM_UNLOCK();
3773         return rc;
3774 }
3775
3776 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3777 {
3778         int rc;
3779         uint32_t dir_entries;
3780         uint32_t entry_length;
3781         uint8_t *buf;
3782         size_t buflen;
3783         rte_iova_t dma_handle;
3784         struct hwrm_nvm_get_dir_entries_input req = {0};
3785         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3786
3787         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3788         if (rc != 0)
3789                 return rc;
3790
3791         *data++ = dir_entries;
3792         *data++ = entry_length;
3793         len -= 2;
3794         memset(data, 0xff, len);
3795
3796         buflen = dir_entries * entry_length;
3797         buf = rte_malloc("nvm_dir", buflen, 0);
3798         rte_mem_lock_page(buf);
3799         if (buf == NULL)
3800                 return -ENOMEM;
3801         dma_handle = rte_mem_virt2iova(buf);
3802         if (dma_handle == RTE_BAD_IOVA) {
3803                 PMD_DRV_LOG(ERR,
3804                         "unable to map response address to physical memory\n");
3805                 return -ENOMEM;
3806         }
3807         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3808         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3809         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3810
3811         if (rc == 0)
3812                 memcpy(data, buf, len > buflen ? buflen : len);
3813
3814         rte_free(buf);
3815         HWRM_CHECK_RESULT();
3816         HWRM_UNLOCK();
3817
3818         return rc;
3819 }
3820
3821 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3822                              uint32_t offset, uint32_t length,
3823                              uint8_t *data)
3824 {
3825         int rc;
3826         uint8_t *buf;
3827         rte_iova_t dma_handle;
3828         struct hwrm_nvm_read_input req = {0};
3829         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3830
3831         buf = rte_malloc("nvm_item", length, 0);
3832         rte_mem_lock_page(buf);
3833         if (!buf)
3834                 return -ENOMEM;
3835
3836         dma_handle = rte_mem_virt2iova(buf);
3837         if (dma_handle == RTE_BAD_IOVA) {
3838                 PMD_DRV_LOG(ERR,
3839                         "unable to map response address to physical memory\n");
3840                 return -ENOMEM;
3841         }
3842         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3843         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3844         req.dir_idx = rte_cpu_to_le_16(index);
3845         req.offset = rte_cpu_to_le_32(offset);
3846         req.len = rte_cpu_to_le_32(length);
3847         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3848         if (rc == 0)
3849                 memcpy(data, buf, length);
3850
3851         rte_free(buf);
3852         HWRM_CHECK_RESULT();
3853         HWRM_UNLOCK();
3854
3855         return rc;
3856 }
3857
3858 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3859 {
3860         int rc;
3861         struct hwrm_nvm_erase_dir_entry_input req = {0};
3862         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3863
3864         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3865         req.dir_idx = rte_cpu_to_le_16(index);
3866         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3867         HWRM_CHECK_RESULT();
3868         HWRM_UNLOCK();
3869
3870         return rc;
3871 }
3872
3873
3874 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3875                           uint16_t dir_ordinal, uint16_t dir_ext,
3876                           uint16_t dir_attr, const uint8_t *data,
3877                           size_t data_len)
3878 {
3879         int rc;
3880         struct hwrm_nvm_write_input req = {0};
3881         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3882         rte_iova_t dma_handle;
3883         uint8_t *buf;
3884
3885         buf = rte_malloc("nvm_write", data_len, 0);
3886         rte_mem_lock_page(buf);
3887         if (!buf)
3888                 return -ENOMEM;
3889
3890         dma_handle = rte_mem_virt2iova(buf);
3891         if (dma_handle == RTE_BAD_IOVA) {
3892                 PMD_DRV_LOG(ERR,
3893                         "unable to map response address to physical memory\n");
3894                 return -ENOMEM;
3895         }
3896         memcpy(buf, data, data_len);
3897
3898         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3899
3900         req.dir_type = rte_cpu_to_le_16(dir_type);
3901         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3902         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3903         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3904         req.dir_data_length = rte_cpu_to_le_32(data_len);
3905         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3906
3907         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3908
3909         rte_free(buf);
3910         HWRM_CHECK_RESULT();
3911         HWRM_UNLOCK();
3912
3913         return rc;
3914 }
3915
3916 static void
3917 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3918 {
3919         uint32_t *count = cbdata;
3920
3921         *count = *count + 1;
3922 }
3923
3924 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3925                                      struct bnxt_vnic_info *vnic __rte_unused)
3926 {
3927         return 0;
3928 }
3929
3930 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3931 {
3932         uint32_t count = 0;
3933
3934         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3935             &count, bnxt_vnic_count_hwrm_stub);
3936
3937         return count;
3938 }
3939
3940 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3941                                         uint16_t *vnic_ids)
3942 {
3943         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3944         struct hwrm_func_vf_vnic_ids_query_output *resp =
3945                                                 bp->hwrm_cmd_resp_addr;
3946         int rc;
3947
3948         /* First query all VNIC ids */
3949         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3950
3951         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3952         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3953         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3954
3955         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3956                 HWRM_UNLOCK();
3957                 PMD_DRV_LOG(ERR,
3958                 "unable to map VNIC ID table address to physical memory\n");
3959                 return -ENOMEM;
3960         }
3961         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3962         HWRM_CHECK_RESULT();
3963         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3964
3965         HWRM_UNLOCK();
3966
3967         return rc;
3968 }
3969
3970 /*
3971  * This function queries the VNIC IDs  for a specified VF. It then calls
3972  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3973  * Then it calls the hwrm_cb function to program this new vnic configuration.
3974  */
3975 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3976         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3977         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3978 {
3979         struct bnxt_vnic_info vnic;
3980         int rc = 0;
3981         int i, num_vnic_ids;
3982         uint16_t *vnic_ids;
3983         size_t vnic_id_sz;
3984         size_t sz;
3985
3986         /* First query all VNIC ids */
3987         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3988         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3989                         RTE_CACHE_LINE_SIZE);
3990         if (vnic_ids == NULL)
3991                 return -ENOMEM;
3992
3993         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3994                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3995
3996         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3997
3998         if (num_vnic_ids < 0)
3999                 return num_vnic_ids;
4000
4001         /* Retrieve VNIC, update bd_stall then update */
4002
4003         for (i = 0; i < num_vnic_ids; i++) {
4004                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4005                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4006                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4007                 if (rc)
4008                         break;
4009                 if (vnic.mru <= 4)      /* Indicates unallocated */
4010                         continue;
4011
4012                 vnic_cb(&vnic, cbdata);
4013
4014                 rc = hwrm_cb(bp, &vnic);
4015                 if (rc)
4016                         break;
4017         }
4018
4019         rte_free(vnic_ids);
4020
4021         return rc;
4022 }
4023
4024 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4025                                               bool on)
4026 {
4027         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4028         struct hwrm_func_cfg_input req = {0};
4029         int rc;
4030
4031         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4032
4033         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4034         req.enables |= rte_cpu_to_le_32(
4035                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4036         req.vlan_antispoof_mode = on ?
4037                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4038                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4039         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4040
4041         HWRM_CHECK_RESULT();
4042         HWRM_UNLOCK();
4043
4044         return rc;
4045 }
4046
4047 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4048 {
4049         struct bnxt_vnic_info vnic;
4050         uint16_t *vnic_ids;
4051         size_t vnic_id_sz;
4052         int num_vnic_ids, i;
4053         size_t sz;
4054         int rc;
4055
4056         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4057         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4058                         RTE_CACHE_LINE_SIZE);
4059         if (vnic_ids == NULL)
4060                 return -ENOMEM;
4061
4062         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4063                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4064
4065         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4066         if (rc <= 0)
4067                 goto exit;
4068         num_vnic_ids = rc;
4069
4070         /*
4071          * Loop through to find the default VNIC ID.
4072          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4073          * by sending the hwrm_func_qcfg command to the firmware.
4074          */
4075         for (i = 0; i < num_vnic_ids; i++) {
4076                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4077                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4078                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4079                                         bp->pf.first_vf_id + vf);
4080                 if (rc)
4081                         goto exit;
4082                 if (vnic.func_default) {
4083                         rte_free(vnic_ids);
4084                         return vnic.fw_vnic_id;
4085                 }
4086         }
4087         /* Could not find a default VNIC. */
4088         PMD_DRV_LOG(ERR, "No default VNIC\n");
4089 exit:
4090         rte_free(vnic_ids);
4091         return rc;
4092 }
4093
4094 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4095                          uint16_t dst_id,
4096                          struct bnxt_filter_info *filter)
4097 {
4098         int rc = 0;
4099         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4100         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4101         uint32_t enables = 0;
4102
4103         if (filter->fw_em_filter_id != UINT64_MAX)
4104                 bnxt_hwrm_clear_em_filter(bp, filter);
4105
4106         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4107
4108         req.flags = rte_cpu_to_le_32(filter->flags);
4109
4110         enables = filter->enables |
4111               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4112         req.dst_id = rte_cpu_to_le_16(dst_id);
4113
4114         if (filter->ip_addr_type) {
4115                 req.ip_addr_type = filter->ip_addr_type;
4116                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4117         }
4118         if (enables &
4119             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4120                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4121         if (enables &
4122             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4123                 memcpy(req.src_macaddr, filter->src_macaddr,
4124                        RTE_ETHER_ADDR_LEN);
4125         if (enables &
4126             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4127                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4128                        RTE_ETHER_ADDR_LEN);
4129         if (enables &
4130             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4131                 req.ovlan_vid = filter->l2_ovlan;
4132         if (enables &
4133             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4134                 req.ivlan_vid = filter->l2_ivlan;
4135         if (enables &
4136             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4137                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4138         if (enables &
4139             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4140                 req.ip_protocol = filter->ip_protocol;
4141         if (enables &
4142             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4143                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4144         if (enables &
4145             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4146                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4147         if (enables &
4148             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4149                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4150         if (enables &
4151             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4152                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4153         if (enables &
4154             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4155                 req.mirror_vnic_id = filter->mirror_vnic_id;
4156
4157         req.enables = rte_cpu_to_le_32(enables);
4158
4159         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4160
4161         HWRM_CHECK_RESULT();
4162
4163         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4164         HWRM_UNLOCK();
4165
4166         return rc;
4167 }
4168
4169 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4170 {
4171         int rc = 0;
4172         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4173         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4174
4175         if (filter->fw_em_filter_id == UINT64_MAX)
4176                 return 0;
4177
4178         PMD_DRV_LOG(ERR, "Clear EM filter\n");
4179         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4180
4181         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4182
4183         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4184
4185         HWRM_CHECK_RESULT();
4186         HWRM_UNLOCK();
4187
4188         filter->fw_em_filter_id = UINT64_MAX;
4189         filter->fw_l2_filter_id = UINT64_MAX;
4190
4191         return 0;
4192 }
4193
4194 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4195                          uint16_t dst_id,
4196                          struct bnxt_filter_info *filter)
4197 {
4198         int rc = 0;
4199         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4200         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4201                                                 bp->hwrm_cmd_resp_addr;
4202         uint32_t enables = 0;
4203
4204         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4205                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4206
4207         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4208
4209         req.flags = rte_cpu_to_le_32(filter->flags);
4210
4211         enables = filter->enables |
4212               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4213         req.dst_id = rte_cpu_to_le_16(dst_id);
4214
4215
4216         if (filter->ip_addr_type) {
4217                 req.ip_addr_type = filter->ip_addr_type;
4218                 enables |=
4219                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4220         }
4221         if (enables &
4222             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4223                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4224         if (enables &
4225             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4226                 memcpy(req.src_macaddr, filter->src_macaddr,
4227                        RTE_ETHER_ADDR_LEN);
4228         //if (enables &
4229             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4230                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4231                        //RTE_ETHER_ADDR_LEN);
4232         if (enables &
4233             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4234                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4235         if (enables &
4236             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4237                 req.ip_protocol = filter->ip_protocol;
4238         if (enables &
4239             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4240                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4241         if (enables &
4242             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4243                 req.src_ipaddr_mask[0] =
4244                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4245         if (enables &
4246             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4247                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4248         if (enables &
4249             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4250                 req.dst_ipaddr_mask[0] =
4251                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4252         if (enables &
4253             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4254                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4255         if (enables &
4256             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4257                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4258         if (enables &
4259             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4260                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4261         if (enables &
4262             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4263                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4264         if (enables &
4265             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4266                 req.mirror_vnic_id = filter->mirror_vnic_id;
4267
4268         req.enables = rte_cpu_to_le_32(enables);
4269
4270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4271
4272         HWRM_CHECK_RESULT();
4273
4274         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4275         HWRM_UNLOCK();
4276
4277         return rc;
4278 }
4279
4280 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4281                                 struct bnxt_filter_info *filter)
4282 {
4283         int rc = 0;
4284         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4285         struct hwrm_cfa_ntuple_filter_free_output *resp =
4286                                                 bp->hwrm_cmd_resp_addr;
4287
4288         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4289                 return 0;
4290
4291         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4292
4293         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4294
4295         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4296
4297         HWRM_CHECK_RESULT();
4298         HWRM_UNLOCK();
4299
4300         filter->fw_ntuple_filter_id = UINT64_MAX;
4301
4302         return 0;
4303 }
4304
4305 static int
4306 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4307 {
4308         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4309         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4310         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4311         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4312         uint16_t *ring_tbl = vnic->rss_table;
4313         int nr_ctxs = vnic->num_lb_ctxts;
4314         int max_rings = bp->rx_nr_rings;
4315         int i, j, k, cnt;
4316         int rc = 0;
4317
4318         for (i = 0, k = 0; i < nr_ctxs; i++) {
4319                 struct bnxt_rx_ring_info *rxr;
4320                 struct bnxt_cp_ring_info *cpr;
4321
4322                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4323
4324                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4325                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4326                 req.hash_mode_flags = vnic->hash_mode;
4327
4328                 req.ring_grp_tbl_addr =
4329                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4330                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4331                                      2 * sizeof(*ring_tbl));
4332                 req.hash_key_tbl_addr =
4333                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4334
4335                 req.ring_table_pair_index = i;
4336                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4337
4338                 for (j = 0; j < 64; j++) {
4339                         uint16_t ring_id;
4340
4341                         /* Find next active ring. */
4342                         for (cnt = 0; cnt < max_rings; cnt++) {
4343                                 if (rx_queue_state[k] !=
4344                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4345                                         break;
4346                                 if (++k == max_rings)
4347                                         k = 0;
4348                         }
4349
4350                         /* Return if no rings are active. */
4351                         if (cnt == max_rings)
4352                                 return 0;
4353
4354                         /* Add rx/cp ring pair to RSS table. */
4355                         rxr = rxqs[k]->rx_ring;
4356                         cpr = rxqs[k]->cp_ring;
4357
4358                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4359                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4360                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4361                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4362
4363                         if (++k == max_rings)
4364                                 k = 0;
4365                 }
4366                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4367                                             BNXT_USE_CHIMP_MB);
4368
4369                 HWRM_CHECK_RESULT();
4370                 HWRM_UNLOCK();
4371         }
4372
4373         return rc;
4374 }
4375
4376 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4377 {
4378         unsigned int rss_idx, fw_idx, i;
4379
4380         if (!(vnic->rss_table && vnic->hash_type))
4381                 return 0;
4382
4383         if (BNXT_CHIP_THOR(bp))
4384                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4385
4386         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4387                 return 0;
4388
4389         if (vnic->rss_table && vnic->hash_type) {
4390                 /*
4391                  * Fill the RSS hash & redirection table with
4392                  * ring group ids for all VNICs
4393                  */
4394                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4395                         rss_idx++, fw_idx++) {
4396                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4397                                 fw_idx %= bp->rx_cp_nr_rings;
4398                                 if (vnic->fw_grp_ids[fw_idx] !=
4399                                     INVALID_HW_RING_ID)
4400                                         break;
4401                                 fw_idx++;
4402                         }
4403                         if (i == bp->rx_cp_nr_rings)
4404                                 return 0;
4405                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4406                 }
4407                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4408         }
4409
4410         return 0;
4411 }
4412
4413 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4414         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4415 {
4416         uint16_t flags;
4417
4418         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4419
4420         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4421         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4422
4423         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4424         req->num_cmpl_dma_aggr_during_int =
4425                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4426
4427         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4428
4429         /* min timer set to 1/2 of interrupt timer */
4430         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4431
4432         /* buf timer set to 1/4 of interrupt timer */
4433         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4434
4435         req->cmpl_aggr_dma_tmr_during_int =
4436                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4437
4438         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4439                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4440         req->flags = rte_cpu_to_le_16(flags);
4441 }
4442
4443 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4444                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4445 {
4446         struct hwrm_ring_aggint_qcaps_input req = {0};
4447         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4448         uint32_t enables;
4449         uint16_t flags;
4450         int rc;
4451
4452         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4453         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4454         HWRM_CHECK_RESULT();
4455
4456         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4457         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4458
4459         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4460                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4461         agg_req->flags = rte_cpu_to_le_16(flags);
4462         enables =
4463          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4464          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4465         agg_req->enables = rte_cpu_to_le_32(enables);
4466
4467         HWRM_UNLOCK();
4468         return rc;
4469 }
4470
4471 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4472                         struct bnxt_coal *coal, uint16_t ring_id)
4473 {
4474         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4475         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4476                                                 bp->hwrm_cmd_resp_addr;
4477         int rc;
4478
4479         /* Set ring coalesce parameters only for 100G NICs */
4480         if (BNXT_CHIP_THOR(bp)) {
4481                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4482                         return -1;
4483         } else if (bnxt_stratus_device(bp)) {
4484                 bnxt_hwrm_set_coal_params(coal, &req);
4485         } else {
4486                 return 0;
4487         }
4488
4489         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4490         req.ring_id = rte_cpu_to_le_16(ring_id);
4491         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4492         HWRM_CHECK_RESULT();
4493         HWRM_UNLOCK();
4494         return 0;
4495 }
4496
4497 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4498 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4499 {
4500         struct hwrm_func_backing_store_qcaps_input req = {0};
4501         struct hwrm_func_backing_store_qcaps_output *resp =
4502                 bp->hwrm_cmd_resp_addr;
4503         struct bnxt_ctx_pg_info *ctx_pg;
4504         struct bnxt_ctx_mem_info *ctx;
4505         int total_alloc_len;
4506         int rc, i;
4507
4508         if (!BNXT_CHIP_THOR(bp) ||
4509             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4510             BNXT_VF(bp) ||
4511             bp->ctx)
4512                 return 0;
4513
4514         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4515         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4516         HWRM_CHECK_RESULT_SILENT();
4517
4518         total_alloc_len = sizeof(*ctx);
4519         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4520                           RTE_CACHE_LINE_SIZE);
4521         if (!ctx) {
4522                 rc = -ENOMEM;
4523                 goto ctx_err;
4524         }
4525
4526         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4527                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4528                             RTE_CACHE_LINE_SIZE);
4529         if (!ctx_pg) {
4530                 rc = -ENOMEM;
4531                 goto ctx_err;
4532         }
4533         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4534                 ctx->tqm_mem[i] = ctx_pg;
4535
4536         bp->ctx = ctx;
4537         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4538         ctx->qp_min_qp1_entries =
4539                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4540         ctx->qp_max_l2_entries =
4541                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4542         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4543         ctx->srq_max_l2_entries =
4544                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4545         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4546         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4547         ctx->cq_max_l2_entries =
4548                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4549         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4550         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4551         ctx->vnic_max_vnic_entries =
4552                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4553         ctx->vnic_max_ring_table_entries =
4554                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4555         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4556         ctx->stat_max_entries =
4557                 rte_le_to_cpu_32(resp->stat_max_entries);
4558         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4559         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4560         ctx->tqm_min_entries_per_ring =
4561                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4562         ctx->tqm_max_entries_per_ring =
4563                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4564         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4565         if (!ctx->tqm_entries_multiple)
4566                 ctx->tqm_entries_multiple = 1;
4567         ctx->mrav_max_entries =
4568                 rte_le_to_cpu_32(resp->mrav_max_entries);
4569         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4570         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4571         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4572 ctx_err:
4573         HWRM_UNLOCK();
4574         return rc;
4575 }
4576
4577 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4578 {
4579         struct hwrm_func_backing_store_cfg_input req = {0};
4580         struct hwrm_func_backing_store_cfg_output *resp =
4581                 bp->hwrm_cmd_resp_addr;
4582         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4583         struct bnxt_ctx_pg_info *ctx_pg;
4584         uint32_t *num_entries;
4585         uint64_t *pg_dir;
4586         uint8_t *pg_attr;
4587         uint32_t ena;
4588         int i, rc;
4589
4590         if (!ctx)
4591                 return 0;
4592
4593         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4594         req.enables = rte_cpu_to_le_32(enables);
4595
4596         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4597                 ctx_pg = &ctx->qp_mem;
4598                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4599                 req.qp_num_qp1_entries =
4600                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4601                 req.qp_num_l2_entries =
4602                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4603                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4604                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4605                                       &req.qpc_pg_size_qpc_lvl,
4606                                       &req.qpc_page_dir);
4607         }
4608
4609         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4610                 ctx_pg = &ctx->srq_mem;
4611                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4612                 req.srq_num_l2_entries =
4613                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4614                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4615                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4616                                       &req.srq_pg_size_srq_lvl,
4617                                       &req.srq_page_dir);
4618         }
4619
4620         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4621                 ctx_pg = &ctx->cq_mem;
4622                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4623                 req.cq_num_l2_entries =
4624                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4625                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4626                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4627                                       &req.cq_pg_size_cq_lvl,
4628                                       &req.cq_page_dir);
4629         }
4630
4631         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4632                 ctx_pg = &ctx->vnic_mem;
4633                 req.vnic_num_vnic_entries =
4634                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4635                 req.vnic_num_ring_table_entries =
4636                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4637                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4638                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4639                                       &req.vnic_pg_size_vnic_lvl,
4640                                       &req.vnic_page_dir);
4641         }
4642
4643         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4644                 ctx_pg = &ctx->stat_mem;
4645                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4646                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4647                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4648                                       &req.stat_pg_size_stat_lvl,
4649                                       &req.stat_page_dir);
4650         }
4651
4652         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4653         num_entries = &req.tqm_sp_num_entries;
4654         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4655         pg_dir = &req.tqm_sp_page_dir;
4656         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4657         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4658                 if (!(enables & ena))
4659                         continue;
4660
4661                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4662
4663                 ctx_pg = ctx->tqm_mem[i];
4664                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4665                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4666         }
4667
4668         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4669         HWRM_CHECK_RESULT();
4670         HWRM_UNLOCK();
4671
4672         return rc;
4673 }
4674
4675 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4676 {
4677         struct hwrm_port_qstats_ext_input req = {0};
4678         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4679         struct bnxt_pf_info *pf = &bp->pf;
4680         int rc;
4681
4682         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4683               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4684                 return 0;
4685
4686         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4687
4688         req.port_id = rte_cpu_to_le_16(pf->port_id);
4689         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4690                 req.tx_stat_host_addr =
4691                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4692                 req.tx_stat_size =
4693                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4694         }
4695         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4696                 req.rx_stat_host_addr =
4697                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4698                 req.rx_stat_size =
4699                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4700         }
4701         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4702
4703         if (rc) {
4704                 bp->fw_rx_port_stats_ext_size = 0;
4705                 bp->fw_tx_port_stats_ext_size = 0;
4706         } else {
4707                 bp->fw_rx_port_stats_ext_size =
4708                         rte_le_to_cpu_16(resp->rx_stat_size);
4709                 bp->fw_tx_port_stats_ext_size =
4710                         rte_le_to_cpu_16(resp->tx_stat_size);
4711         }
4712
4713         HWRM_CHECK_RESULT();
4714         HWRM_UNLOCK();
4715
4716         return rc;
4717 }
4718
4719 int
4720 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4721 {
4722         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4723         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4724                 bp->hwrm_cmd_resp_addr;
4725         int rc = 0;
4726
4727         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4728         req.tunnel_type = type;
4729         req.dest_fid = bp->fw_fid;
4730         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4731         HWRM_CHECK_RESULT();
4732
4733         HWRM_UNLOCK();
4734
4735         return rc;
4736 }
4737
4738 int
4739 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4740 {
4741         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4742         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4743                 bp->hwrm_cmd_resp_addr;
4744         int rc = 0;
4745
4746         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4747         req.tunnel_type = type;
4748         req.dest_fid = bp->fw_fid;
4749         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4750         HWRM_CHECK_RESULT();
4751
4752         HWRM_UNLOCK();
4753
4754         return rc;
4755 }
4756
4757 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4758 {
4759         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4760         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4761                 bp->hwrm_cmd_resp_addr;
4762         int rc = 0;
4763
4764         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4765         req.src_fid = bp->fw_fid;
4766         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4767         HWRM_CHECK_RESULT();
4768
4769         if (type)
4770                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4771
4772         HWRM_UNLOCK();
4773
4774         return rc;
4775 }
4776
4777 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4778                                    uint16_t *dst_fid)
4779 {
4780         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4781         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4782                 bp->hwrm_cmd_resp_addr;
4783         int rc = 0;
4784
4785         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4786         req.src_fid = bp->fw_fid;
4787         req.tunnel_type = tun_type;
4788         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4789         HWRM_CHECK_RESULT();
4790
4791         if (dst_fid)
4792                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4793
4794         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4795
4796         HWRM_UNLOCK();
4797
4798         return rc;
4799 }
4800
4801 int bnxt_hwrm_set_mac(struct bnxt *bp)
4802 {
4803         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4804         struct hwrm_func_vf_cfg_input req = {0};
4805         int rc = 0;
4806
4807         if (!BNXT_VF(bp))
4808                 return 0;
4809
4810         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4811
4812         req.enables =
4813                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4814         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4815
4816         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4817
4818         HWRM_CHECK_RESULT();
4819
4820         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4821         HWRM_UNLOCK();
4822
4823         return rc;
4824 }
4825
4826 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4827 {
4828         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4829         struct hwrm_func_drv_if_change_input req = {0};
4830         uint32_t flags;
4831         int rc;
4832
4833         if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4834                 return 0;
4835
4836         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4837          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4838          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4839          */
4840         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4841                 return 0;
4842
4843         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4844
4845         if (up)
4846                 req.flags =
4847                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4848
4849         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4850
4851         HWRM_CHECK_RESULT();
4852         flags = rte_le_to_cpu_32(resp->flags);
4853         HWRM_UNLOCK();
4854
4855         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4856                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4857                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4858         }
4859
4860         return 0;
4861 }
4862
4863 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4864 {
4865         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4866         struct bnxt_error_recovery_info *info = bp->recovery_info;
4867         struct hwrm_error_recovery_qcfg_input req = {0};
4868         uint32_t flags = 0;
4869         unsigned int i;
4870         int rc;
4871
4872         /* Older FW does not have error recovery support */
4873         if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4874                 return 0;
4875
4876         if (!info) {
4877                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4878                                    sizeof(*info), 0);
4879                 bp->recovery_info = info;
4880                 if (info == NULL)
4881                         return -ENOMEM;
4882         } else {
4883                 memset(info, 0, sizeof(*info));
4884         }
4885
4886         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4887
4888         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4889
4890         HWRM_CHECK_RESULT();
4891
4892         flags = rte_le_to_cpu_32(resp->flags);
4893         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4894                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4895         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4896                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4897
4898         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4899             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4900                 rc = -EINVAL;
4901                 goto err;
4902         }
4903
4904         /* FW returned values are in units of 100msec */
4905         info->driver_polling_freq =
4906                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4907         info->master_func_wait_period =
4908                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4909         info->normal_func_wait_period =
4910                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4911         info->master_func_wait_period_after_reset =
4912                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4913         info->max_bailout_time_after_reset =
4914                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4915         info->status_regs[BNXT_FW_STATUS_REG] =
4916                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4917         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4918                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4919         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4920                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4921         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4922                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4923         info->reg_array_cnt =
4924                 rte_le_to_cpu_32(resp->reg_array_cnt);
4925
4926         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4927                 rc = -EINVAL;
4928                 goto err;
4929         }
4930
4931         for (i = 0; i < info->reg_array_cnt; i++) {
4932                 info->reset_reg[i] =
4933                         rte_le_to_cpu_32(resp->reset_reg[i]);
4934                 info->reset_reg_val[i] =
4935                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4936                 info->delay_after_reset[i] =
4937                         resp->delay_after_reset[i];
4938         }
4939 err:
4940         HWRM_UNLOCK();
4941
4942         /* Map the FW status registers */
4943         if (!rc)
4944                 rc = bnxt_map_fw_health_status_regs(bp);
4945
4946         if (rc) {
4947                 rte_free(bp->recovery_info);
4948                 bp->recovery_info = NULL;
4949         }
4950         return rc;
4951 }
4952
4953 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4954 {
4955         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4956         struct hwrm_fw_reset_input req = {0};
4957         int rc;
4958
4959         if (!BNXT_PF(bp))
4960                 return -EOPNOTSUPP;
4961
4962         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4963
4964         req.embedded_proc_type =
4965                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4966         req.selfrst_status =
4967                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4968         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4969
4970         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4971                                     BNXT_USE_KONG(bp));
4972
4973         HWRM_CHECK_RESULT();
4974         HWRM_UNLOCK();
4975
4976         return rc;
4977 }
4978
4979 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4980 {
4981         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4982         struct hwrm_port_ts_query_input req = {0};
4983         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4984         uint32_t flags = 0;
4985         int rc;
4986
4987         if (!ptp)
4988                 return 0;
4989
4990         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4991
4992         switch (path) {
4993         case BNXT_PTP_FLAGS_PATH_TX:
4994                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4995                 break;
4996         case BNXT_PTP_FLAGS_PATH_RX:
4997                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4998                 break;
4999         case BNXT_PTP_FLAGS_CURRENT_TIME:
5000                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5001                 break;
5002         }
5003
5004         req.flags = rte_cpu_to_le_32(flags);
5005         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5006
5007         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5008
5009         HWRM_CHECK_RESULT();
5010
5011         if (timestamp) {
5012                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5013                 *timestamp |=
5014                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5015         }
5016         HWRM_UNLOCK();
5017
5018         return rc;
5019 }
5020
5021 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5022 {
5023         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5024                                         bp->hwrm_cmd_resp_addr;
5025         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5026         uint32_t flags = 0;
5027         int rc = 0;
5028
5029         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5030                 return rc;
5031
5032         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5033                 PMD_DRV_LOG(DEBUG,
5034                             "Not a PF or trusted VF. Command not supported\n");
5035                 return 0;
5036         }
5037
5038         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5039         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5040
5041         HWRM_CHECK_RESULT();
5042         flags = rte_le_to_cpu_32(resp->flags);
5043         HWRM_UNLOCK();
5044
5045         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5046                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5047                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5048         }
5049
5050         return rc;
5051 }