1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SHORT_CMD_TIMEOUT 50000
31 #define HWRM_SPEC_CODE_1_8_3 0x10803
32 #define HWRM_VERSION_1_9_1 0x10901
33 #define HWRM_VERSION_1_9_2 0x10903
35 struct bnxt_plcmodes_cfg {
37 uint16_t jumbo_thresh;
39 uint16_t hds_threshold;
42 static int page_getenum(size_t size)
58 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
59 return sizeof(void *) * 8 - 1;
62 static int page_roundup(size_t size)
64 return 1 << page_getenum(size);
67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
71 if (rmem->nr_pages > 1) {
73 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
75 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
80 * HWRM Functions (sent to HWRM)
81 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
82 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
83 * command was failed by the ChiMP.
86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
87 uint32_t msg_len, bool use_kong_mb)
90 struct input *req = msg;
91 struct output *resp = bp->hwrm_cmd_resp_addr;
95 uint16_t max_req_len = bp->max_req_len;
96 struct hwrm_short_input short_input = { 0 };
97 uint16_t bar_offset = use_kong_mb ?
98 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
99 uint16_t mb_trigger_offset = use_kong_mb ?
100 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
103 /* Do not send HWRM commands to firmware in error state */
104 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
107 /* For VER_GET command, set timeout as 50ms */
108 if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
109 timeout = HWRM_SHORT_CMD_TIMEOUT;
111 timeout = HWRM_CMD_TIMEOUT;
113 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
114 msg_len > bp->max_req_len) {
115 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
117 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
118 memcpy(short_cmd_req, req, msg_len);
120 short_input.req_type = rte_cpu_to_le_16(req->req_type);
121 short_input.signature = rte_cpu_to_le_16(
122 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
123 short_input.size = rte_cpu_to_le_16(msg_len);
124 short_input.req_addr =
125 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
127 data = (uint32_t *)&short_input;
128 msg_len = sizeof(short_input);
130 /* Sync memory write before updating doorbell */
133 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
136 /* Write request msg to hwrm channel */
137 for (i = 0; i < msg_len; i += 4) {
138 bar = (uint8_t *)bp->bar0 + bar_offset + i;
139 rte_write32(*data, bar);
143 /* Zero the rest of the request space */
144 for (; i < max_req_len; i += 4) {
145 bar = (uint8_t *)bp->bar0 + bar_offset + i;
149 /* Ring channel doorbell */
150 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
153 /* Poll for the valid bit */
154 for (i = 0; i < timeout; i++) {
155 /* Sanity check on the resp->resp_len */
157 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
158 /* Last byte of resp contains the valid key */
159 valid = (uint8_t *)resp + resp->resp_len - 1;
160 if (*valid == HWRM_RESP_VALID_KEY)
167 /* Suppress VER_GET timeout messages during reset recovery */
168 if (bp->flags & BNXT_FLAG_FW_RESET &&
169 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
172 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
180 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
181 * spinlock, and does initial processing.
183 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
184 * releases the spinlock only if it returns. If the regular int return codes
185 * are not used by the function, HWRM_CHECK_RESULT() should not be used
186 * directly, rather it should be copied and modified to suit the function.
188 * HWRM_UNLOCK() must be called after all response processing is completed.
190 #define HWRM_PREP(req, type, kong) do { \
191 rte_spinlock_lock(&bp->hwrm_lock); \
192 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
193 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
194 req.cmpl_ring = rte_cpu_to_le_16(-1); \
195 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
196 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
197 req.target_id = rte_cpu_to_le_16(0xffff); \
198 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
201 #define HWRM_CHECK_RESULT_SILENT() do {\
203 rte_spinlock_unlock(&bp->hwrm_lock); \
206 if (resp->error_code) { \
207 rc = rte_le_to_cpu_16(resp->error_code); \
208 rte_spinlock_unlock(&bp->hwrm_lock); \
213 #define HWRM_CHECK_RESULT() do {\
215 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
216 rte_spinlock_unlock(&bp->hwrm_lock); \
217 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
223 if (resp->error_code) { \
224 rc = rte_le_to_cpu_16(resp->error_code); \
225 if (resp->resp_len >= 16) { \
226 struct hwrm_err_output *tmp_hwrm_err_op = \
229 "error %d:%d:%08x:%04x\n", \
230 rc, tmp_hwrm_err_op->cmd_err, \
232 tmp_hwrm_err_op->opaque_0), \
234 tmp_hwrm_err_op->opaque_1)); \
236 PMD_DRV_LOG(ERR, "error %d\n", rc); \
238 rte_spinlock_unlock(&bp->hwrm_lock); \
239 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
247 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
249 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
252 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
253 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
255 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
256 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
259 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
267 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
268 struct bnxt_vnic_info *vnic,
270 struct bnxt_vlan_table_entry *vlan_table)
273 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
274 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
277 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
280 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
281 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
283 /* FIXME add multicast flag, when multicast adding options is supported
286 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
287 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
288 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
289 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
290 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
291 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
292 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
293 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
294 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
295 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
296 if (vnic->mc_addr_cnt) {
297 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
298 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
299 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
302 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
303 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
304 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
305 rte_mem_virt2iova(vlan_table));
306 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
308 req.mask = rte_cpu_to_le_32(mask);
310 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
318 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
320 struct bnxt_vlan_antispoof_table_entry *vlan_table)
323 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
324 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
325 bp->hwrm_cmd_resp_addr;
328 * Older HWRM versions did not support this command, and the set_rx_mask
329 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
330 * removed from set_rx_mask call, and this command was added.
332 * This command is also present from 1.7.8.11 and higher,
335 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
336 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
337 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
342 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
343 req.fid = rte_cpu_to_le_16(fid);
345 req.vlan_tag_mask_tbl_addr =
346 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
347 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
349 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
357 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
358 struct bnxt_filter_info *filter)
361 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
362 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
364 if (filter->fw_l2_filter_id == UINT64_MAX)
367 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
369 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
371 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
376 filter->fw_l2_filter_id = UINT64_MAX;
381 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
383 struct bnxt_filter_info *filter)
386 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
387 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
388 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
389 const struct rte_eth_vmdq_rx_conf *conf =
390 &dev_conf->rx_adv_conf.vmdq_rx_conf;
391 uint32_t enables = 0;
392 uint16_t j = dst_id - 1;
394 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
395 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
396 conf->pool_map[j].pools & (1UL << j)) {
398 "Add vlan %u to vmdq pool %u\n",
399 conf->pool_map[j].vlan_id, j);
401 filter->l2_ivlan = conf->pool_map[j].vlan_id;
403 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
404 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
407 if (filter->fw_l2_filter_id != UINT64_MAX)
408 bnxt_hwrm_clear_l2_filter(bp, filter);
410 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
412 req.flags = rte_cpu_to_le_32(filter->flags);
414 rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
416 enables = filter->enables |
417 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
418 req.dst_id = rte_cpu_to_le_16(dst_id);
421 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
422 memcpy(req.l2_addr, filter->l2_addr,
425 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
426 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
429 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
430 req.l2_ovlan = filter->l2_ovlan;
432 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
433 req.l2_ivlan = filter->l2_ivlan;
435 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
436 req.l2_ovlan_mask = filter->l2_ovlan_mask;
438 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
439 req.l2_ivlan_mask = filter->l2_ivlan_mask;
440 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
441 req.src_id = rte_cpu_to_le_32(filter->src_id);
442 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
443 req.src_type = filter->src_type;
445 req.enables = rte_cpu_to_le_32(enables);
447 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
451 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
457 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
459 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
460 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
467 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
470 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
473 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
474 if (ptp->tx_tstamp_en)
475 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
478 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
479 req.flags = rte_cpu_to_le_32(flags);
480 req.enables = rte_cpu_to_le_32
481 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
482 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
484 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
490 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
493 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
494 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
495 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
497 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
501 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
503 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
505 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
509 if (!BNXT_CHIP_THOR(bp) &&
510 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
513 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
514 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
516 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
520 if (!BNXT_CHIP_THOR(bp)) {
521 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
522 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
523 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
524 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
525 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
526 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
527 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
528 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
529 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
530 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
531 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
532 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
533 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
534 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
535 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
536 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
537 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
538 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
547 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
550 struct hwrm_func_qcaps_input req = {.req_type = 0 };
551 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
552 uint16_t new_max_vfs;
556 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
558 req.fid = rte_cpu_to_le_16(0xffff);
560 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
564 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
565 flags = rte_le_to_cpu_32(resp->flags);
567 bp->pf.port_id = resp->port_id;
568 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
569 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
570 new_max_vfs = bp->pdev->max_vfs;
571 if (new_max_vfs != bp->pf.max_vfs) {
573 rte_free(bp->pf.vf_info);
574 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
575 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
576 bp->pf.max_vfs = new_max_vfs;
577 for (i = 0; i < new_max_vfs; i++) {
578 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
579 bp->pf.vf_info[i].vlan_table =
580 rte_zmalloc("VF VLAN table",
583 if (bp->pf.vf_info[i].vlan_table == NULL)
585 "Fail to alloc VLAN table for VF %d\n",
589 bp->pf.vf_info[i].vlan_table);
590 bp->pf.vf_info[i].vlan_as_table =
591 rte_zmalloc("VF VLAN AS table",
594 if (bp->pf.vf_info[i].vlan_as_table == NULL)
596 "Alloc VLAN AS table for VF %d fail\n",
600 bp->pf.vf_info[i].vlan_as_table);
601 STAILQ_INIT(&bp->pf.vf_info[i].filter);
606 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
607 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
608 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
609 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
610 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
611 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
612 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
613 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
615 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
616 /* TODO: For now, do not support VMDq/RFS on VFs. */
621 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
625 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
627 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
628 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
629 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
630 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
632 bnxt_hwrm_ptp_qcfg(bp);
636 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
637 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
639 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
640 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
641 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
643 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
646 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
647 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
649 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
656 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
660 rc = __bnxt_hwrm_func_qcaps(bp);
661 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
662 rc = bnxt_alloc_ctx_mem(bp);
666 rc = bnxt_hwrm_func_resc_qcaps(bp);
668 bp->flags |= BNXT_FLAG_NEW_RM;
674 int bnxt_hwrm_func_reset(struct bnxt *bp)
677 struct hwrm_func_reset_input req = {.req_type = 0 };
678 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
680 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
682 req.enables = rte_cpu_to_le_32(0);
684 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
692 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
696 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
697 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
699 if (bp->flags & BNXT_FLAG_REGISTERED)
702 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
703 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
704 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
706 /* PFs and trusted VFs should indicate the support of the
707 * Master capability on non Stingray platform
709 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
710 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
712 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
713 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
714 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
715 req.ver_maj = RTE_VER_YEAR;
716 req.ver_min = RTE_VER_MONTH;
717 req.ver_upd = RTE_VER_MINOR;
720 req.enables |= rte_cpu_to_le_32(
721 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
722 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
723 RTE_MIN(sizeof(req.vf_req_fwd),
724 sizeof(bp->pf.vf_req_fwd)));
727 * PF can sniff HWRM API issued by VF. This can be set up by
728 * linux driver and inherited by the DPDK PF driver. Clear
729 * this HWRM sniffer list in FW because DPDK PF driver does
732 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
735 req.flags = rte_cpu_to_le_32(flags);
737 req.async_event_fwd[0] |=
738 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
739 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
740 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
741 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
742 if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
743 req.async_event_fwd[0] |=
744 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
745 req.async_event_fwd[1] |=
746 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
747 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
749 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
753 flags = rte_le_to_cpu_32(resp->flags);
754 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
755 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
759 bp->flags |= BNXT_FLAG_REGISTERED;
764 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
766 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
769 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
772 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
777 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
778 struct hwrm_func_vf_cfg_input req = {0};
780 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
782 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
783 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
784 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
785 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
786 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
788 if (BNXT_HAS_RING_GRPS(bp)) {
789 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
790 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
793 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
794 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
795 AGG_RING_MULTIPLIER);
796 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
798 BNXT_NUM_ASYNC_CPR(bp));
799 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
801 BNXT_NUM_ASYNC_CPR(bp));
802 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
803 if (bp->vf_resv_strategy ==
804 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
805 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
806 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
807 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
808 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
809 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
810 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
814 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
815 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
816 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
817 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
818 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
819 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
821 if (test && BNXT_HAS_RING_GRPS(bp))
822 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
824 req.flags = rte_cpu_to_le_32(flags);
825 req.enables |= rte_cpu_to_le_32(enables);
827 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
830 HWRM_CHECK_RESULT_SILENT();
838 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
841 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
842 struct hwrm_func_resource_qcaps_input req = {0};
844 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
845 req.fid = rte_cpu_to_le_16(0xffff);
847 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
852 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
853 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
854 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
855 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
856 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
857 /* func_resource_qcaps does not return max_rx_em_flows.
858 * So use the value provided by func_qcaps.
861 rte_le_to_cpu_16(resp->max_l2_ctxs) +
863 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
864 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
866 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
867 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
868 if (bp->vf_resv_strategy >
869 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
870 bp->vf_resv_strategy =
871 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
877 int bnxt_hwrm_ver_get(struct bnxt *bp)
880 struct hwrm_ver_get_input req = {.req_type = 0 };
881 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
883 uint16_t max_resp_len;
884 char type[RTE_MEMZONE_NAMESIZE];
885 uint32_t dev_caps_cfg;
887 bp->max_req_len = HWRM_MAX_REQ_LEN;
888 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
890 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
891 req.hwrm_intf_min = HWRM_VERSION_MINOR;
892 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
894 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
896 if (bp->flags & BNXT_FLAG_FW_RESET)
897 HWRM_CHECK_RESULT_SILENT();
901 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
902 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
903 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
904 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
905 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
906 (resp->hwrm_fw_min_8b << 16) |
907 (resp->hwrm_fw_bld_8b << 8) |
908 resp->hwrm_fw_rsvd_8b;
909 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
910 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
912 fw_version = resp->hwrm_intf_maj_8b << 16;
913 fw_version |= resp->hwrm_intf_min_8b << 8;
914 fw_version |= resp->hwrm_intf_upd_8b;
915 bp->hwrm_spec_code = fw_version;
917 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
918 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
923 if (bp->max_req_len > resp->max_req_win_len) {
924 PMD_DRV_LOG(ERR, "Unsupported request length\n");
927 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
928 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
929 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
930 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
932 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
933 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
935 if (bp->max_resp_len != max_resp_len) {
936 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
937 bp->pdev->addr.domain, bp->pdev->addr.bus,
938 bp->pdev->addr.devid, bp->pdev->addr.function);
940 rte_free(bp->hwrm_cmd_resp_addr);
942 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
943 if (bp->hwrm_cmd_resp_addr == NULL) {
947 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
948 bp->hwrm_cmd_resp_dma_addr =
949 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
950 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
952 "Unable to map response buffer to physical memory.\n");
956 bp->max_resp_len = max_resp_len;
960 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
962 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
963 PMD_DRV_LOG(DEBUG, "Short command supported\n");
964 bp->flags |= BNXT_FLAG_SHORT_CMD;
968 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
970 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
971 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
972 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
973 bp->pdev->addr.domain, bp->pdev->addr.bus,
974 bp->pdev->addr.devid, bp->pdev->addr.function);
976 rte_free(bp->hwrm_short_cmd_req_addr);
978 bp->hwrm_short_cmd_req_addr =
979 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
980 if (bp->hwrm_short_cmd_req_addr == NULL) {
984 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
985 bp->hwrm_short_cmd_req_dma_addr =
986 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
987 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
988 rte_free(bp->hwrm_short_cmd_req_addr);
990 "Unable to map buffer to physical memory.\n");
996 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
997 bp->flags |= BNXT_FLAG_KONG_MB_EN;
998 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1001 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1002 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1009 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1012 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1013 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1015 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1018 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1021 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1023 HWRM_CHECK_RESULT();
1029 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1032 struct hwrm_port_phy_cfg_input req = {0};
1033 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1034 uint32_t enables = 0;
1036 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1038 if (conf->link_up) {
1039 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1040 if (bp->link_info.auto_mode && conf->link_speed) {
1041 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1042 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1045 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1046 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1047 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1049 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1050 * any auto mode, even "none".
1052 if (!conf->link_speed) {
1053 /* No speeds specified. Enable AutoNeg - all speeds */
1055 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1057 /* AutoNeg - Advertise speeds specified. */
1058 if (conf->auto_link_speed_mask &&
1059 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1061 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1062 req.auto_link_speed_mask =
1063 conf->auto_link_speed_mask;
1065 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1068 req.auto_duplex = conf->duplex;
1069 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1070 req.auto_pause = conf->auto_pause;
1071 req.force_pause = conf->force_pause;
1072 /* Set force_pause if there is no auto or if there is a force */
1073 if (req.auto_pause && !req.force_pause)
1074 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1076 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1078 req.enables = rte_cpu_to_le_32(enables);
1081 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1082 PMD_DRV_LOG(INFO, "Force Link Down\n");
1085 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1087 HWRM_CHECK_RESULT();
1093 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1094 struct bnxt_link_info *link_info)
1097 struct hwrm_port_phy_qcfg_input req = {0};
1098 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1100 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1102 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1104 HWRM_CHECK_RESULT();
1106 link_info->phy_link_status = resp->link;
1107 link_info->link_up =
1108 (link_info->phy_link_status ==
1109 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1110 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1111 link_info->duplex = resp->duplex_cfg;
1112 link_info->pause = resp->pause;
1113 link_info->auto_pause = resp->auto_pause;
1114 link_info->force_pause = resp->force_pause;
1115 link_info->auto_mode = resp->auto_mode;
1116 link_info->phy_type = resp->phy_type;
1117 link_info->media_type = resp->media_type;
1119 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1120 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1121 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1122 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1123 link_info->phy_ver[0] = resp->phy_maj;
1124 link_info->phy_ver[1] = resp->phy_min;
1125 link_info->phy_ver[2] = resp->phy_bld;
1129 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1130 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1131 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1132 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1133 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1134 link_info->auto_link_speed_mask);
1135 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1136 link_info->force_link_speed);
1141 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1144 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1145 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1148 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1150 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1151 /* HWRM Version >= 1.9.1 */
1152 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1154 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1155 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1157 HWRM_CHECK_RESULT();
1159 #define GET_QUEUE_INFO(x) \
1160 bp->cos_queue[x].id = resp->queue_id##x; \
1161 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1174 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1175 bp->tx_cosq_id = bp->cos_queue[0].id;
1177 /* iterate and find the COSq profile to use for Tx */
1178 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1179 if (bp->cos_queue[i].profile ==
1180 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1181 bp->tx_cosq_id = bp->cos_queue[i].id;
1187 bp->max_tc = resp->max_configurable_queues;
1188 bp->max_lltc = resp->max_configurable_lossless_queues;
1189 if (bp->max_tc > BNXT_MAX_QUEUE)
1190 bp->max_tc = BNXT_MAX_QUEUE;
1191 bp->max_q = bp->max_tc;
1193 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1198 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1199 struct bnxt_ring *ring,
1200 uint32_t ring_type, uint32_t map_index,
1201 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1204 uint32_t enables = 0;
1205 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1206 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1207 struct rte_mempool *mb_pool;
1208 uint16_t rx_buf_size;
1210 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1212 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1213 req.fbo = rte_cpu_to_le_32(0);
1214 /* Association of ring index with doorbell index */
1215 req.logical_id = rte_cpu_to_le_16(map_index);
1216 req.length = rte_cpu_to_le_32(ring->ring_size);
1218 switch (ring_type) {
1219 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1220 req.ring_type = ring_type;
1221 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1222 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1223 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1224 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1226 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1228 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1229 req.ring_type = ring_type;
1230 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1231 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1232 if (BNXT_CHIP_THOR(bp)) {
1233 mb_pool = bp->rx_queues[0]->mb_pool;
1234 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1235 RTE_PKTMBUF_HEADROOM;
1236 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1238 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1240 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1242 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1244 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1245 req.ring_type = ring_type;
1246 if (BNXT_HAS_NQ(bp)) {
1247 /* Association of cp ring with nq */
1248 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1250 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1252 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1254 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1255 req.ring_type = ring_type;
1256 req.page_size = BNXT_PAGE_SHFT;
1257 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1259 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1260 req.ring_type = ring_type;
1261 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1263 mb_pool = bp->rx_queues[0]->mb_pool;
1264 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1265 RTE_PKTMBUF_HEADROOM;
1266 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1268 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1269 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1270 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1271 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1274 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1279 req.enables = rte_cpu_to_le_32(enables);
1281 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1283 if (rc || resp->error_code) {
1284 if (rc == 0 && resp->error_code)
1285 rc = rte_le_to_cpu_16(resp->error_code);
1286 switch (ring_type) {
1287 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1289 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1292 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1294 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1297 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1299 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1303 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1305 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1308 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1310 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1314 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1320 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1325 int bnxt_hwrm_ring_free(struct bnxt *bp,
1326 struct bnxt_ring *ring, uint32_t ring_type)
1329 struct hwrm_ring_free_input req = {.req_type = 0 };
1330 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1332 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1334 req.ring_type = ring_type;
1335 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1337 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1339 if (rc || resp->error_code) {
1340 if (rc == 0 && resp->error_code)
1341 rc = rte_le_to_cpu_16(resp->error_code);
1344 switch (ring_type) {
1345 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1346 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1349 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1350 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1353 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1354 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1357 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1359 "hwrm_ring_free nq failed. rc:%d\n", rc);
1361 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1363 "hwrm_ring_free agg failed. rc:%d\n", rc);
1366 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1374 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1377 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1378 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1380 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1382 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1383 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1384 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1385 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1387 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1389 HWRM_CHECK_RESULT();
1391 bp->grp_info[idx].fw_grp_id =
1392 rte_le_to_cpu_16(resp->ring_group_id);
1399 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1402 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1403 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1405 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1407 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1409 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1411 HWRM_CHECK_RESULT();
1414 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1418 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1421 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1422 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1424 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1427 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1429 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1431 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1433 HWRM_CHECK_RESULT();
1439 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1440 unsigned int idx __rte_unused)
1443 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1444 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1446 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1448 req.update_period_ms = rte_cpu_to_le_32(0);
1450 req.stats_dma_addr =
1451 rte_cpu_to_le_64(cpr->hw_stats_map);
1453 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1455 HWRM_CHECK_RESULT();
1457 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1464 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1465 unsigned int idx __rte_unused)
1468 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1469 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1471 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1473 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1475 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1477 HWRM_CHECK_RESULT();
1483 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1486 struct hwrm_vnic_alloc_input req = { 0 };
1487 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1489 if (!BNXT_HAS_RING_GRPS(bp))
1490 goto skip_ring_grps;
1492 /* map ring groups to this vnic */
1493 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1494 vnic->start_grp_id, vnic->end_grp_id);
1495 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1496 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1498 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1499 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1500 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1501 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1504 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1505 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1506 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1508 if (vnic->func_default)
1510 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1511 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1513 HWRM_CHECK_RESULT();
1515 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1517 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1521 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1522 struct bnxt_vnic_info *vnic,
1523 struct bnxt_plcmodes_cfg *pmode)
1526 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1527 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1529 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1531 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1533 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1535 HWRM_CHECK_RESULT();
1537 pmode->flags = rte_le_to_cpu_32(resp->flags);
1538 /* dflt_vnic bit doesn't exist in the _cfg command */
1539 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1540 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1541 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1542 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1549 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1550 struct bnxt_vnic_info *vnic,
1551 struct bnxt_plcmodes_cfg *pmode)
1554 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1555 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1557 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1558 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1562 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1564 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1565 req.flags = rte_cpu_to_le_32(pmode->flags);
1566 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1567 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1568 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1569 req.enables = rte_cpu_to_le_32(
1570 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1571 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1572 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1575 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1577 HWRM_CHECK_RESULT();
1583 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1586 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1587 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1588 struct bnxt_plcmodes_cfg pmodes = { 0 };
1589 uint32_t ctx_enable_flag = 0;
1590 uint32_t enables = 0;
1592 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1593 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1597 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1601 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1603 if (BNXT_CHIP_THOR(bp)) {
1604 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1605 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1606 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1608 req.default_rx_ring_id =
1609 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1610 req.default_cmpl_ring_id =
1611 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1612 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1613 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1617 /* Only RSS support for now TBD: COS & LB */
1618 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1619 if (vnic->lb_rule != 0xffff)
1620 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1621 if (vnic->cos_rule != 0xffff)
1622 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1623 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1624 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1625 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1627 enables |= ctx_enable_flag;
1628 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1629 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1630 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1631 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1634 req.enables = rte_cpu_to_le_32(enables);
1635 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1636 req.mru = rte_cpu_to_le_16(vnic->mru);
1637 /* Configure default VNIC only once. */
1638 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1640 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1641 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1643 if (vnic->vlan_strip)
1645 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1648 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1649 if (vnic->roce_dual)
1650 req.flags |= rte_cpu_to_le_32(
1651 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1652 if (vnic->roce_only)
1653 req.flags |= rte_cpu_to_le_32(
1654 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1655 if (vnic->rss_dflt_cr)
1656 req.flags |= rte_cpu_to_le_32(
1657 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1659 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1661 HWRM_CHECK_RESULT();
1664 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1669 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1673 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1674 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1676 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1677 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1680 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1683 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1684 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1685 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1687 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1689 HWRM_CHECK_RESULT();
1691 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1692 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1693 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1694 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1695 vnic->mru = rte_le_to_cpu_16(resp->mru);
1696 vnic->func_default = rte_le_to_cpu_32(
1697 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1698 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1699 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1700 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1701 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1702 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1703 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1704 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1705 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1706 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1707 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1714 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1715 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1719 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1720 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1721 bp->hwrm_cmd_resp_addr;
1723 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1725 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1726 HWRM_CHECK_RESULT();
1728 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1729 if (!BNXT_HAS_RING_GRPS(bp))
1730 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1731 else if (ctx_idx == 0)
1732 vnic->rss_rule = ctx_id;
1739 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1740 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1743 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1744 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1745 bp->hwrm_cmd_resp_addr;
1747 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1748 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1751 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1753 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1755 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1757 HWRM_CHECK_RESULT();
1763 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1766 struct hwrm_vnic_free_input req = {.req_type = 0 };
1767 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1769 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1770 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1774 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1776 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1778 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1780 HWRM_CHECK_RESULT();
1783 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1784 /* Configure default VNIC again if necessary. */
1785 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1786 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1792 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1796 int nr_ctxs = vnic->num_lb_ctxts;
1797 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1798 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1800 for (i = 0; i < nr_ctxs; i++) {
1801 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1803 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1804 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1805 req.hash_mode_flags = vnic->hash_mode;
1807 req.hash_key_tbl_addr =
1808 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1810 req.ring_grp_tbl_addr =
1811 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1812 i * HW_HASH_INDEX_SIZE);
1813 req.ring_table_pair_index = i;
1814 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1816 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1819 HWRM_CHECK_RESULT();
1826 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1827 struct bnxt_vnic_info *vnic)
1830 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1831 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1833 if (!vnic->rss_table)
1836 if (BNXT_CHIP_THOR(bp))
1837 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1839 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1841 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1842 req.hash_mode_flags = vnic->hash_mode;
1844 req.ring_grp_tbl_addr =
1845 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1846 req.hash_key_tbl_addr =
1847 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1848 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1849 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1851 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1853 HWRM_CHECK_RESULT();
1859 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1860 struct bnxt_vnic_info *vnic)
1863 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1864 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1867 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1868 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1872 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1874 req.flags = rte_cpu_to_le_32(
1875 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1877 req.enables = rte_cpu_to_le_32(
1878 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1880 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1881 size -= RTE_PKTMBUF_HEADROOM;
1883 req.jumbo_thresh = rte_cpu_to_le_16(size);
1884 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1886 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1888 HWRM_CHECK_RESULT();
1894 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1895 struct bnxt_vnic_info *vnic, bool enable)
1898 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1899 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1901 if (BNXT_CHIP_THOR(bp))
1904 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1907 req.enables = rte_cpu_to_le_32(
1908 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1909 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1910 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1911 req.flags = rte_cpu_to_le_32(
1912 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1913 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1914 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1915 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1916 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1917 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1918 req.max_agg_segs = rte_cpu_to_le_16(5);
1920 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1921 req.min_agg_len = rte_cpu_to_le_32(512);
1923 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1925 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1927 HWRM_CHECK_RESULT();
1933 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1935 struct hwrm_func_cfg_input req = {0};
1936 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1939 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1940 req.enables = rte_cpu_to_le_32(
1941 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1942 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1943 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1945 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1947 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1948 HWRM_CHECK_RESULT();
1951 bp->pf.vf_info[vf].random_mac = false;
1956 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1960 struct hwrm_func_qstats_input req = {.req_type = 0};
1961 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1963 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1965 req.fid = rte_cpu_to_le_16(fid);
1967 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1969 HWRM_CHECK_RESULT();
1972 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1979 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1980 struct rte_eth_stats *stats)
1983 struct hwrm_func_qstats_input req = {.req_type = 0};
1984 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1986 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1988 req.fid = rte_cpu_to_le_16(fid);
1990 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1992 HWRM_CHECK_RESULT();
1994 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1995 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1996 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1997 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1998 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1999 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2001 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2002 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2003 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2004 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2005 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2006 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2008 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2009 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2010 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2017 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2020 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2021 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2023 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2025 req.fid = rte_cpu_to_le_16(fid);
2027 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2029 HWRM_CHECK_RESULT();
2036 * HWRM utility functions
2039 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2044 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2045 struct bnxt_tx_queue *txq;
2046 struct bnxt_rx_queue *rxq;
2047 struct bnxt_cp_ring_info *cpr;
2049 if (i >= bp->rx_cp_nr_rings) {
2050 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2053 rxq = bp->rx_queues[i];
2057 rc = bnxt_hwrm_stat_clear(bp, cpr);
2064 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2068 struct bnxt_cp_ring_info *cpr;
2070 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2072 if (i >= bp->rx_cp_nr_rings) {
2073 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2075 cpr = bp->rx_queues[i]->cp_ring;
2076 if (BNXT_HAS_RING_GRPS(bp))
2077 bp->grp_info[i].fw_stats_ctx = -1;
2079 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2080 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2081 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2089 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2094 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2095 struct bnxt_tx_queue *txq;
2096 struct bnxt_rx_queue *rxq;
2097 struct bnxt_cp_ring_info *cpr;
2099 if (i >= bp->rx_cp_nr_rings) {
2100 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2103 rxq = bp->rx_queues[i];
2107 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2115 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2120 if (!BNXT_HAS_RING_GRPS(bp))
2123 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2125 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2128 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2136 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2138 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2140 bnxt_hwrm_ring_free(bp, cp_ring,
2141 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2142 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2143 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2144 sizeof(*cpr->cp_desc_ring));
2145 cpr->cp_raw_cons = 0;
2149 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2151 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2153 bnxt_hwrm_ring_free(bp, cp_ring,
2154 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2155 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2156 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2157 sizeof(*cpr->cp_desc_ring));
2158 cpr->cp_raw_cons = 0;
2162 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2164 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2165 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2166 struct bnxt_ring *ring = rxr->rx_ring_struct;
2167 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2169 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2170 bnxt_hwrm_ring_free(bp, ring,
2171 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2172 ring->fw_ring_id = INVALID_HW_RING_ID;
2173 if (BNXT_HAS_RING_GRPS(bp))
2174 bp->grp_info[queue_index].rx_fw_ring_id =
2176 memset(rxr->rx_desc_ring, 0,
2177 rxr->rx_ring_struct->ring_size *
2178 sizeof(*rxr->rx_desc_ring));
2179 memset(rxr->rx_buf_ring, 0,
2180 rxr->rx_ring_struct->ring_size *
2181 sizeof(*rxr->rx_buf_ring));
2184 ring = rxr->ag_ring_struct;
2185 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2186 bnxt_hwrm_ring_free(bp, ring,
2187 BNXT_CHIP_THOR(bp) ?
2188 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2189 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2190 ring->fw_ring_id = INVALID_HW_RING_ID;
2191 memset(rxr->ag_buf_ring, 0,
2192 rxr->ag_ring_struct->ring_size *
2193 sizeof(*rxr->ag_buf_ring));
2195 if (BNXT_HAS_RING_GRPS(bp))
2196 bp->grp_info[queue_index].ag_fw_ring_id =
2199 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2200 bnxt_free_cp_ring(bp, cpr);
2202 bnxt_free_nq_ring(bp, rxq->nq_ring);
2205 if (BNXT_HAS_RING_GRPS(bp))
2206 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2209 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2213 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2214 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2215 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2216 struct bnxt_ring *ring = txr->tx_ring_struct;
2217 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2219 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2220 bnxt_hwrm_ring_free(bp, ring,
2221 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2222 ring->fw_ring_id = INVALID_HW_RING_ID;
2223 memset(txr->tx_desc_ring, 0,
2224 txr->tx_ring_struct->ring_size *
2225 sizeof(*txr->tx_desc_ring));
2226 memset(txr->tx_buf_ring, 0,
2227 txr->tx_ring_struct->ring_size *
2228 sizeof(*txr->tx_buf_ring));
2232 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2233 bnxt_free_cp_ring(bp, cpr);
2234 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2236 bnxt_free_nq_ring(bp, txq->nq_ring);
2240 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2241 bnxt_free_hwrm_rx_ring(bp, i);
2246 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2251 if (!BNXT_HAS_RING_GRPS(bp))
2254 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2255 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2262 void bnxt_free_hwrm_resources(struct bnxt *bp)
2264 /* Release memzone */
2265 rte_free(bp->hwrm_cmd_resp_addr);
2266 rte_free(bp->hwrm_short_cmd_req_addr);
2267 bp->hwrm_cmd_resp_addr = NULL;
2268 bp->hwrm_short_cmd_req_addr = NULL;
2269 bp->hwrm_cmd_resp_dma_addr = 0;
2270 bp->hwrm_short_cmd_req_dma_addr = 0;
2273 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2275 struct rte_pci_device *pdev = bp->pdev;
2276 char type[RTE_MEMZONE_NAMESIZE];
2278 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2279 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2280 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2281 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2282 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2283 if (bp->hwrm_cmd_resp_addr == NULL)
2285 bp->hwrm_cmd_resp_dma_addr =
2286 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2287 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2289 "unable to map response address to physical memory\n");
2292 rte_spinlock_init(&bp->hwrm_lock);
2297 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2299 struct bnxt_filter_info *filter;
2302 STAILQ_FOREACH(filter, &vnic->filter, next) {
2303 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2304 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2305 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2306 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2308 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2309 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2317 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2319 struct bnxt_filter_info *filter;
2320 struct rte_flow *flow;
2323 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2324 filter = flow->filter;
2325 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2326 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2327 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2328 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2329 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2331 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2333 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2341 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2343 struct bnxt_filter_info *filter;
2346 STAILQ_FOREACH(filter, &vnic->filter, next) {
2347 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2348 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2350 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2351 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2354 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2362 void bnxt_free_tunnel_ports(struct bnxt *bp)
2364 if (bp->vxlan_port_cnt)
2365 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2366 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2368 if (bp->geneve_port_cnt)
2369 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2370 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2371 bp->geneve_port = 0;
2374 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2378 if (bp->vnic_info == NULL)
2382 * Cleanup VNICs in reverse order, to make sure the L2 filter
2383 * from vnic0 is last to be cleaned up.
2385 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2386 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2388 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2389 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2393 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2395 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2397 if (BNXT_CHIP_THOR(bp)) {
2398 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2399 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2400 vnic->fw_grp_ids[j]);
2401 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2403 vnic->num_lb_ctxts = 0;
2405 bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2406 vnic->rss_rule = INVALID_HW_RING_ID;
2409 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2411 bnxt_hwrm_vnic_free(bp, vnic);
2413 rte_free(vnic->fw_grp_ids);
2415 /* Ring resources */
2416 bnxt_free_all_hwrm_rings(bp);
2417 bnxt_free_all_hwrm_ring_grps(bp);
2418 bnxt_free_all_hwrm_stat_ctxs(bp);
2419 bnxt_free_tunnel_ports(bp);
2422 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2424 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2426 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2427 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2429 switch (conf_link_speed) {
2430 case ETH_LINK_SPEED_10M_HD:
2431 case ETH_LINK_SPEED_100M_HD:
2433 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2435 return hw_link_duplex;
2438 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2440 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2443 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2445 uint16_t eth_link_speed = 0;
2447 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2448 return ETH_LINK_SPEED_AUTONEG;
2450 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2451 case ETH_LINK_SPEED_100M:
2452 case ETH_LINK_SPEED_100M_HD:
2455 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2457 case ETH_LINK_SPEED_1G:
2459 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2461 case ETH_LINK_SPEED_2_5G:
2463 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2465 case ETH_LINK_SPEED_10G:
2467 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2469 case ETH_LINK_SPEED_20G:
2471 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2473 case ETH_LINK_SPEED_25G:
2475 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2477 case ETH_LINK_SPEED_40G:
2479 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2481 case ETH_LINK_SPEED_50G:
2483 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2485 case ETH_LINK_SPEED_100G:
2487 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2491 "Unsupported link speed %d; default to AUTO\n",
2495 return eth_link_speed;
2498 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2499 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2500 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2501 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2503 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2507 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2510 if (link_speed & ETH_LINK_SPEED_FIXED) {
2511 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2513 if (one_speed & (one_speed - 1)) {
2515 "Invalid advertised speeds (%u) for port %u\n",
2516 link_speed, port_id);
2519 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2521 "Unsupported advertised speed (%u) for port %u\n",
2522 link_speed, port_id);
2526 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2528 "Unsupported advertised speeds (%u) for port %u\n",
2529 link_speed, port_id);
2537 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2541 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2542 if (bp->link_info.support_speeds)
2543 return bp->link_info.support_speeds;
2544 link_speed = BNXT_SUPPORTED_SPEEDS;
2547 if (link_speed & ETH_LINK_SPEED_100M)
2548 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2549 if (link_speed & ETH_LINK_SPEED_100M_HD)
2550 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2551 if (link_speed & ETH_LINK_SPEED_1G)
2552 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2553 if (link_speed & ETH_LINK_SPEED_2_5G)
2554 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2555 if (link_speed & ETH_LINK_SPEED_10G)
2556 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2557 if (link_speed & ETH_LINK_SPEED_20G)
2558 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2559 if (link_speed & ETH_LINK_SPEED_25G)
2560 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2561 if (link_speed & ETH_LINK_SPEED_40G)
2562 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2563 if (link_speed & ETH_LINK_SPEED_50G)
2564 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2565 if (link_speed & ETH_LINK_SPEED_100G)
2566 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2570 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2572 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2574 switch (hw_link_speed) {
2575 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2576 eth_link_speed = ETH_SPEED_NUM_100M;
2578 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2579 eth_link_speed = ETH_SPEED_NUM_1G;
2581 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2582 eth_link_speed = ETH_SPEED_NUM_2_5G;
2584 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2585 eth_link_speed = ETH_SPEED_NUM_10G;
2587 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2588 eth_link_speed = ETH_SPEED_NUM_20G;
2590 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2591 eth_link_speed = ETH_SPEED_NUM_25G;
2593 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2594 eth_link_speed = ETH_SPEED_NUM_40G;
2596 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2597 eth_link_speed = ETH_SPEED_NUM_50G;
2599 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2600 eth_link_speed = ETH_SPEED_NUM_100G;
2602 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2604 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2608 return eth_link_speed;
2611 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2613 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2615 switch (hw_link_duplex) {
2616 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2617 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2619 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2621 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2622 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2625 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2629 return eth_link_duplex;
2632 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2635 struct bnxt_link_info *link_info = &bp->link_info;
2637 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2640 "Get link config failed with rc %d\n", rc);
2643 if (link_info->link_speed)
2645 bnxt_parse_hw_link_speed(link_info->link_speed);
2647 link->link_speed = ETH_SPEED_NUM_NONE;
2648 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2649 link->link_status = link_info->link_up;
2650 link->link_autoneg = link_info->auto_mode ==
2651 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2652 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2657 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2660 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2661 struct bnxt_link_info link_req;
2662 uint16_t speed, autoneg;
2664 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2667 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2668 bp->eth_dev->data->port_id);
2672 memset(&link_req, 0, sizeof(link_req));
2673 link_req.link_up = link_up;
2677 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2678 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2679 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2680 /* Autoneg can be done only when the FW allows */
2681 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2682 bp->link_info.force_link_speed)) {
2683 link_req.phy_flags |=
2684 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2685 link_req.auto_link_speed_mask =
2686 bnxt_parse_eth_link_speed_mask(bp,
2687 dev_conf->link_speeds);
2689 if (bp->link_info.phy_type ==
2690 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2691 bp->link_info.phy_type ==
2692 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2693 bp->link_info.media_type ==
2694 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2695 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2699 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2700 /* If user wants a particular speed try that first. */
2702 link_req.link_speed = speed;
2703 else if (bp->link_info.force_link_speed)
2704 link_req.link_speed = bp->link_info.force_link_speed;
2706 link_req.link_speed = bp->link_info.auto_link_speed;
2708 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2709 link_req.auto_pause = bp->link_info.auto_pause;
2710 link_req.force_pause = bp->link_info.force_pause;
2713 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2716 "Set link config failed with rc %d\n", rc);
2724 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2726 struct hwrm_func_qcfg_input req = {0};
2727 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2731 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2732 req.fid = rte_cpu_to_le_16(0xffff);
2734 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2736 HWRM_CHECK_RESULT();
2738 /* Hard Coded.. 0xfff VLAN ID mask */
2739 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2740 flags = rte_le_to_cpu_16(resp->flags);
2741 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2742 bp->flags |= BNXT_FLAG_MULTI_HOST;
2744 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2745 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2746 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2747 } else if (BNXT_VF(bp) &&
2748 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2749 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2750 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2756 switch (resp->port_partition_type) {
2757 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2758 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2759 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2761 bp->port_partition_type = resp->port_partition_type;
2764 bp->port_partition_type = 0;
2773 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2774 struct hwrm_func_qcaps_output *qcaps)
2776 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2777 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2778 sizeof(qcaps->mac_address));
2779 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2780 qcaps->max_rx_rings = fcfg->num_rx_rings;
2781 qcaps->max_tx_rings = fcfg->num_tx_rings;
2782 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2783 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2785 qcaps->first_vf_id = 0;
2786 qcaps->max_vnics = fcfg->num_vnics;
2787 qcaps->max_decap_records = 0;
2788 qcaps->max_encap_records = 0;
2789 qcaps->max_tx_wm_flows = 0;
2790 qcaps->max_tx_em_flows = 0;
2791 qcaps->max_rx_wm_flows = 0;
2792 qcaps->max_rx_em_flows = 0;
2793 qcaps->max_flow_id = 0;
2794 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2795 qcaps->max_sp_tx_rings = 0;
2796 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2799 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2801 struct hwrm_func_cfg_input req = {0};
2802 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2806 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2807 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2808 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2809 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2810 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2811 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2812 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2813 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2814 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2816 if (BNXT_HAS_RING_GRPS(bp)) {
2817 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2818 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2819 } else if (BNXT_HAS_NQ(bp)) {
2820 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2821 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2824 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2825 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2826 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2827 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2829 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2830 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2831 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2832 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2833 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2834 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2835 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2836 req.fid = rte_cpu_to_le_16(0xffff);
2837 req.enables = rte_cpu_to_le_32(enables);
2839 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2841 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2843 HWRM_CHECK_RESULT();
2849 static void populate_vf_func_cfg_req(struct bnxt *bp,
2850 struct hwrm_func_cfg_input *req,
2853 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2854 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2855 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2856 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2857 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2858 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2859 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2860 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2861 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2862 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2864 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2865 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2867 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2868 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2870 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2872 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2873 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2875 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2876 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2877 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2878 /* TODO: For now, do not support VMDq/RFS on VFs. */
2879 req->num_vnics = rte_cpu_to_le_16(1);
2880 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2884 static void add_random_mac_if_needed(struct bnxt *bp,
2885 struct hwrm_func_cfg_input *cfg_req,
2888 struct rte_ether_addr mac;
2890 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2893 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2895 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2896 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2897 bp->pf.vf_info[vf].random_mac = true;
2899 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2900 RTE_ETHER_ADDR_LEN);
2904 static void reserve_resources_from_vf(struct bnxt *bp,
2905 struct hwrm_func_cfg_input *cfg_req,
2908 struct hwrm_func_qcaps_input req = {0};
2909 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2912 /* Get the actual allocated values now */
2913 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2914 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2915 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2918 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2919 copy_func_cfg_to_qcaps(cfg_req, resp);
2920 } else if (resp->error_code) {
2921 rc = rte_le_to_cpu_16(resp->error_code);
2922 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2923 copy_func_cfg_to_qcaps(cfg_req, resp);
2926 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2927 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2928 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2929 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2930 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2931 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2933 * TODO: While not supporting VMDq with VFs, max_vnics is always
2934 * forced to 1 in this case
2936 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2937 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2942 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2944 struct hwrm_func_qcfg_input req = {0};
2945 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2948 /* Check for zero MAC address */
2949 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2950 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2951 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2952 HWRM_CHECK_RESULT();
2953 rc = rte_le_to_cpu_16(resp->vlan);
2960 static int update_pf_resource_max(struct bnxt *bp)
2962 struct hwrm_func_qcfg_input req = {0};
2963 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2966 /* And copy the allocated numbers into the pf struct */
2967 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2968 req.fid = rte_cpu_to_le_16(0xffff);
2969 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2970 HWRM_CHECK_RESULT();
2972 /* Only TX ring value reflects actual allocation? TODO */
2973 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2974 bp->pf.evb_mode = resp->evb_mode;
2981 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2986 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2990 rc = bnxt_hwrm_func_qcaps(bp);
2994 bp->pf.func_cfg_flags &=
2995 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2996 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2997 bp->pf.func_cfg_flags |=
2998 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2999 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3000 rc = __bnxt_hwrm_func_qcaps(bp);
3004 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3006 struct hwrm_func_cfg_input req = {0};
3007 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3014 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3018 rc = bnxt_hwrm_func_qcaps(bp);
3023 bp->pf.active_vfs = num_vfs;
3026 * First, configure the PF to only use one TX ring. This ensures that
3027 * there are enough rings for all VFs.
3029 * If we don't do this, when we call func_alloc() later, we will lock
3030 * extra rings to the PF that won't be available during func_cfg() of
3033 * This has been fixed with firmware versions above 20.6.54
3035 bp->pf.func_cfg_flags &=
3036 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3037 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3038 bp->pf.func_cfg_flags |=
3039 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3040 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3045 * Now, create and register a buffer to hold forwarded VF requests
3047 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3048 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3049 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3050 if (bp->pf.vf_req_buf == NULL) {
3054 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3055 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3056 for (i = 0; i < num_vfs; i++)
3057 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3058 (i * HWRM_MAX_REQ_LEN);
3060 rc = bnxt_hwrm_func_buf_rgtr(bp);
3064 populate_vf_func_cfg_req(bp, &req, num_vfs);
3066 bp->pf.active_vfs = 0;
3067 for (i = 0; i < num_vfs; i++) {
3068 add_random_mac_if_needed(bp, &req, i);
3070 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3071 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3072 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3073 rc = bnxt_hwrm_send_message(bp,
3078 /* Clear enable flag for next pass */
3079 req.enables &= ~rte_cpu_to_le_32(
3080 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3082 if (rc || resp->error_code) {
3084 "Failed to initizlie VF %d\n", i);
3086 "Not all VFs available. (%d, %d)\n",
3087 rc, resp->error_code);
3094 reserve_resources_from_vf(bp, &req, i);
3095 bp->pf.active_vfs++;
3096 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3100 * Now configure the PF to use "the rest" of the resources
3101 * We're using STD_TX_RING_MODE here though which will limit the TX
3102 * rings. This will allow QoS to function properly. Not setting this
3103 * will cause PF rings to break bandwidth settings.
3105 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3109 rc = update_pf_resource_max(bp);
3116 bnxt_hwrm_func_buf_unrgtr(bp);
3120 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3122 struct hwrm_func_cfg_input req = {0};
3123 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3126 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3128 req.fid = rte_cpu_to_le_16(0xffff);
3129 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3130 req.evb_mode = bp->pf.evb_mode;
3132 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3133 HWRM_CHECK_RESULT();
3139 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3140 uint8_t tunnel_type)
3142 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3143 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3146 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3147 req.tunnel_type = tunnel_type;
3148 req.tunnel_dst_port_val = port;
3149 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3150 HWRM_CHECK_RESULT();
3152 switch (tunnel_type) {
3153 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3154 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3155 bp->vxlan_port = port;
3157 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3158 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3159 bp->geneve_port = port;
3170 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3171 uint8_t tunnel_type)
3173 struct hwrm_tunnel_dst_port_free_input req = {0};
3174 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3177 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3179 req.tunnel_type = tunnel_type;
3180 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3181 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3183 HWRM_CHECK_RESULT();
3189 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3192 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3193 struct hwrm_func_cfg_input req = {0};
3196 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3198 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3199 req.flags = rte_cpu_to_le_32(flags);
3200 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3202 HWRM_CHECK_RESULT();
3208 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3210 uint32_t *flag = flagp;
3212 vnic->flags = *flag;
3215 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3217 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3220 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3223 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3224 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3226 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3228 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3229 req.req_buf_page_size = rte_cpu_to_le_16(
3230 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3231 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3232 req.req_buf_page_addr0 =
3233 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3234 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3236 "unable to map buffer address to physical memory\n");
3240 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3242 HWRM_CHECK_RESULT();
3248 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3251 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3252 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3254 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3257 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3259 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3261 HWRM_CHECK_RESULT();
3267 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3269 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3270 struct hwrm_func_cfg_input req = {0};
3273 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3275 req.fid = rte_cpu_to_le_16(0xffff);
3276 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3277 req.enables = rte_cpu_to_le_32(
3278 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3279 req.async_event_cr = rte_cpu_to_le_16(
3280 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3281 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3283 HWRM_CHECK_RESULT();
3289 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3291 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3292 struct hwrm_func_vf_cfg_input req = {0};
3295 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3297 req.enables = rte_cpu_to_le_32(
3298 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3299 req.async_event_cr = rte_cpu_to_le_16(
3300 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3301 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3303 HWRM_CHECK_RESULT();
3309 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3311 struct hwrm_func_cfg_input req = {0};
3312 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3313 uint16_t dflt_vlan, fid;
3314 uint32_t func_cfg_flags;
3317 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3320 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3321 fid = bp->pf.vf_info[vf].fid;
3322 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3324 fid = rte_cpu_to_le_16(0xffff);
3325 func_cfg_flags = bp->pf.func_cfg_flags;
3326 dflt_vlan = bp->vlan;
3329 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3330 req.fid = rte_cpu_to_le_16(fid);
3331 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3332 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3334 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3336 HWRM_CHECK_RESULT();
3342 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3343 uint16_t max_bw, uint16_t enables)
3345 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3346 struct hwrm_func_cfg_input req = {0};
3349 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3351 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3352 req.enables |= rte_cpu_to_le_32(enables);
3353 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3354 req.max_bw = rte_cpu_to_le_32(max_bw);
3355 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3357 HWRM_CHECK_RESULT();
3363 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3365 struct hwrm_func_cfg_input req = {0};
3366 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3369 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3371 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3372 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3373 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3374 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3376 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3378 HWRM_CHECK_RESULT();
3384 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3389 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3391 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3396 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3397 void *encaped, size_t ec_size)
3400 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3401 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3403 if (ec_size > sizeof(req.encap_request))
3406 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3408 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3409 memcpy(req.encap_request, encaped, ec_size);
3411 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3413 HWRM_CHECK_RESULT();
3419 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3420 struct rte_ether_addr *mac)
3422 struct hwrm_func_qcfg_input req = {0};
3423 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3426 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3428 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3429 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3431 HWRM_CHECK_RESULT();
3433 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3440 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3441 void *encaped, size_t ec_size)
3444 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3445 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3447 if (ec_size > sizeof(req.encap_request))
3450 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3452 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3453 memcpy(req.encap_request, encaped, ec_size);
3455 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3457 HWRM_CHECK_RESULT();
3463 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3464 struct rte_eth_stats *stats, uint8_t rx)
3467 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3468 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3470 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3472 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3474 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3476 HWRM_CHECK_RESULT();
3479 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3480 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3481 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3482 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3483 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3484 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3485 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3486 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3488 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3489 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3490 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3491 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3492 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3493 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3502 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3504 struct hwrm_port_qstats_input req = {0};
3505 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3506 struct bnxt_pf_info *pf = &bp->pf;
3509 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3511 req.port_id = rte_cpu_to_le_16(pf->port_id);
3512 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3513 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3514 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3516 HWRM_CHECK_RESULT();
3522 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3524 struct hwrm_port_clr_stats_input req = {0};
3525 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3526 struct bnxt_pf_info *pf = &bp->pf;
3529 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3530 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3531 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3534 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3536 req.port_id = rte_cpu_to_le_16(pf->port_id);
3537 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3539 HWRM_CHECK_RESULT();
3545 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3547 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3548 struct hwrm_port_led_qcaps_input req = {0};
3554 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3555 req.port_id = bp->pf.port_id;
3556 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3558 HWRM_CHECK_RESULT();
3560 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3563 bp->num_leds = resp->num_leds;
3564 memcpy(bp->leds, &resp->led0_id,
3565 sizeof(bp->leds[0]) * bp->num_leds);
3566 for (i = 0; i < bp->num_leds; i++) {
3567 struct bnxt_led_info *led = &bp->leds[i];
3569 uint16_t caps = led->led_state_caps;
3571 if (!led->led_group_id ||
3572 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3584 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3586 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3587 struct hwrm_port_led_cfg_input req = {0};
3588 struct bnxt_led_cfg *led_cfg;
3589 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3590 uint16_t duration = 0;
3593 if (!bp->num_leds || BNXT_VF(bp))
3596 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3599 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3600 duration = rte_cpu_to_le_16(500);
3602 req.port_id = bp->pf.port_id;
3603 req.num_leds = bp->num_leds;
3604 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3605 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3606 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3607 led_cfg->led_id = bp->leds[i].led_id;
3608 led_cfg->led_state = led_state;
3609 led_cfg->led_blink_on = duration;
3610 led_cfg->led_blink_off = duration;
3611 led_cfg->led_group_id = bp->leds[i].led_group_id;
3614 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3616 HWRM_CHECK_RESULT();
3622 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3626 struct hwrm_nvm_get_dir_info_input req = {0};
3627 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3629 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3631 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3633 HWRM_CHECK_RESULT();
3635 *entries = rte_le_to_cpu_32(resp->entries);
3636 *length = rte_le_to_cpu_32(resp->entry_length);
3642 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3645 uint32_t dir_entries;
3646 uint32_t entry_length;
3649 rte_iova_t dma_handle;
3650 struct hwrm_nvm_get_dir_entries_input req = {0};
3651 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3653 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3657 *data++ = dir_entries;
3658 *data++ = entry_length;
3660 memset(data, 0xff, len);
3662 buflen = dir_entries * entry_length;
3663 buf = rte_malloc("nvm_dir", buflen, 0);
3664 rte_mem_lock_page(buf);
3667 dma_handle = rte_mem_virt2iova(buf);
3668 if (dma_handle == RTE_BAD_IOVA) {
3670 "unable to map response address to physical memory\n");
3673 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3674 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3675 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3678 memcpy(data, buf, len > buflen ? buflen : len);
3681 HWRM_CHECK_RESULT();
3687 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3688 uint32_t offset, uint32_t length,
3693 rte_iova_t dma_handle;
3694 struct hwrm_nvm_read_input req = {0};
3695 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3697 buf = rte_malloc("nvm_item", length, 0);
3698 rte_mem_lock_page(buf);
3702 dma_handle = rte_mem_virt2iova(buf);
3703 if (dma_handle == RTE_BAD_IOVA) {
3705 "unable to map response address to physical memory\n");
3708 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3709 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3710 req.dir_idx = rte_cpu_to_le_16(index);
3711 req.offset = rte_cpu_to_le_32(offset);
3712 req.len = rte_cpu_to_le_32(length);
3713 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3715 memcpy(data, buf, length);
3718 HWRM_CHECK_RESULT();
3724 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3727 struct hwrm_nvm_erase_dir_entry_input req = {0};
3728 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3730 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3731 req.dir_idx = rte_cpu_to_le_16(index);
3732 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3733 HWRM_CHECK_RESULT();
3740 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3741 uint16_t dir_ordinal, uint16_t dir_ext,
3742 uint16_t dir_attr, const uint8_t *data,
3746 struct hwrm_nvm_write_input req = {0};
3747 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3748 rte_iova_t dma_handle;
3751 buf = rte_malloc("nvm_write", data_len, 0);
3752 rte_mem_lock_page(buf);
3756 dma_handle = rte_mem_virt2iova(buf);
3757 if (dma_handle == RTE_BAD_IOVA) {
3759 "unable to map response address to physical memory\n");
3762 memcpy(buf, data, data_len);
3764 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3766 req.dir_type = rte_cpu_to_le_16(dir_type);
3767 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3768 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3769 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3770 req.dir_data_length = rte_cpu_to_le_32(data_len);
3771 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3773 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3776 HWRM_CHECK_RESULT();
3783 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3785 uint32_t *count = cbdata;
3787 *count = *count + 1;
3790 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3791 struct bnxt_vnic_info *vnic __rte_unused)
3796 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3800 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3801 &count, bnxt_vnic_count_hwrm_stub);
3806 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3809 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3810 struct hwrm_func_vf_vnic_ids_query_output *resp =
3811 bp->hwrm_cmd_resp_addr;
3814 /* First query all VNIC ids */
3815 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3817 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3818 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3819 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3821 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3824 "unable to map VNIC ID table address to physical memory\n");
3827 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3828 HWRM_CHECK_RESULT();
3829 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3837 * This function queries the VNIC IDs for a specified VF. It then calls
3838 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3839 * Then it calls the hwrm_cb function to program this new vnic configuration.
3841 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3842 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3843 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3845 struct bnxt_vnic_info vnic;
3847 int i, num_vnic_ids;
3852 /* First query all VNIC ids */
3853 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3854 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3855 RTE_CACHE_LINE_SIZE);
3856 if (vnic_ids == NULL)
3859 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3860 rte_mem_lock_page(((char *)vnic_ids) + sz);
3862 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3864 if (num_vnic_ids < 0)
3865 return num_vnic_ids;
3867 /* Retrieve VNIC, update bd_stall then update */
3869 for (i = 0; i < num_vnic_ids; i++) {
3870 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3871 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3872 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3875 if (vnic.mru <= 4) /* Indicates unallocated */
3878 vnic_cb(&vnic, cbdata);
3880 rc = hwrm_cb(bp, &vnic);
3890 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3893 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3894 struct hwrm_func_cfg_input req = {0};
3897 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3899 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3900 req.enables |= rte_cpu_to_le_32(
3901 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3902 req.vlan_antispoof_mode = on ?
3903 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3904 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3905 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3907 HWRM_CHECK_RESULT();
3913 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3915 struct bnxt_vnic_info vnic;
3918 int num_vnic_ids, i;
3922 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3923 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3924 RTE_CACHE_LINE_SIZE);
3925 if (vnic_ids == NULL)
3928 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3929 rte_mem_lock_page(((char *)vnic_ids) + sz);
3931 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3937 * Loop through to find the default VNIC ID.
3938 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3939 * by sending the hwrm_func_qcfg command to the firmware.
3941 for (i = 0; i < num_vnic_ids; i++) {
3942 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3943 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3944 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3945 bp->pf.first_vf_id + vf);
3948 if (vnic.func_default) {
3950 return vnic.fw_vnic_id;
3953 /* Could not find a default VNIC. */
3954 PMD_DRV_LOG(ERR, "No default VNIC\n");
3960 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3962 struct bnxt_filter_info *filter)
3965 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3966 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3967 uint32_t enables = 0;
3969 if (filter->fw_em_filter_id != UINT64_MAX)
3970 bnxt_hwrm_clear_em_filter(bp, filter);
3972 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3974 req.flags = rte_cpu_to_le_32(filter->flags);
3976 enables = filter->enables |
3977 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3978 req.dst_id = rte_cpu_to_le_16(dst_id);
3980 if (filter->ip_addr_type) {
3981 req.ip_addr_type = filter->ip_addr_type;
3982 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3985 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3986 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3988 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3989 memcpy(req.src_macaddr, filter->src_macaddr,
3990 RTE_ETHER_ADDR_LEN);
3992 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3993 memcpy(req.dst_macaddr, filter->dst_macaddr,
3994 RTE_ETHER_ADDR_LEN);
3996 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3997 req.ovlan_vid = filter->l2_ovlan;
3999 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4000 req.ivlan_vid = filter->l2_ivlan;
4002 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4003 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4005 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4006 req.ip_protocol = filter->ip_protocol;
4008 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4009 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4011 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4012 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4014 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4015 req.src_port = rte_cpu_to_be_16(filter->src_port);
4017 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4018 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4020 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4021 req.mirror_vnic_id = filter->mirror_vnic_id;
4023 req.enables = rte_cpu_to_le_32(enables);
4025 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4027 HWRM_CHECK_RESULT();
4029 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4035 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4038 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4039 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4041 if (filter->fw_em_filter_id == UINT64_MAX)
4044 PMD_DRV_LOG(ERR, "Clear EM filter\n");
4045 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4047 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4049 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4051 HWRM_CHECK_RESULT();
4054 filter->fw_em_filter_id = UINT64_MAX;
4055 filter->fw_l2_filter_id = UINT64_MAX;
4060 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4062 struct bnxt_filter_info *filter)
4065 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4066 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4067 bp->hwrm_cmd_resp_addr;
4068 uint32_t enables = 0;
4070 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4071 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4073 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4075 req.flags = rte_cpu_to_le_32(filter->flags);
4077 enables = filter->enables |
4078 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4079 req.dst_id = rte_cpu_to_le_16(dst_id);
4082 if (filter->ip_addr_type) {
4083 req.ip_addr_type = filter->ip_addr_type;
4085 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4088 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4089 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4091 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4092 memcpy(req.src_macaddr, filter->src_macaddr,
4093 RTE_ETHER_ADDR_LEN);
4095 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4096 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4097 //RTE_ETHER_ADDR_LEN);
4099 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4100 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4102 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4103 req.ip_protocol = filter->ip_protocol;
4105 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4106 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4108 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4109 req.src_ipaddr_mask[0] =
4110 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4112 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4113 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4115 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4116 req.dst_ipaddr_mask[0] =
4117 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4119 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4120 req.src_port = rte_cpu_to_le_16(filter->src_port);
4122 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4123 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4125 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4126 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4128 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4129 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4131 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4132 req.mirror_vnic_id = filter->mirror_vnic_id;
4134 req.enables = rte_cpu_to_le_32(enables);
4136 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4138 HWRM_CHECK_RESULT();
4140 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4146 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4147 struct bnxt_filter_info *filter)
4150 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4151 struct hwrm_cfa_ntuple_filter_free_output *resp =
4152 bp->hwrm_cmd_resp_addr;
4154 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4157 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4159 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4161 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4163 HWRM_CHECK_RESULT();
4166 filter->fw_ntuple_filter_id = UINT64_MAX;
4172 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4174 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4175 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4176 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4177 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4178 uint16_t *ring_tbl = vnic->rss_table;
4179 int nr_ctxs = vnic->num_lb_ctxts;
4180 int max_rings = bp->rx_nr_rings;
4184 for (i = 0, k = 0; i < nr_ctxs; i++) {
4185 struct bnxt_rx_ring_info *rxr;
4186 struct bnxt_cp_ring_info *cpr;
4188 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4190 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4191 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4192 req.hash_mode_flags = vnic->hash_mode;
4194 req.ring_grp_tbl_addr =
4195 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4196 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4197 2 * sizeof(*ring_tbl));
4198 req.hash_key_tbl_addr =
4199 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4201 req.ring_table_pair_index = i;
4202 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4204 for (j = 0; j < 64; j++) {
4207 /* Find next active ring. */
4208 for (cnt = 0; cnt < max_rings; cnt++) {
4209 if (rx_queue_state[k] !=
4210 RTE_ETH_QUEUE_STATE_STOPPED)
4212 if (++k == max_rings)
4216 /* Return if no rings are active. */
4217 if (cnt == max_rings)
4220 /* Add rx/cp ring pair to RSS table. */
4221 rxr = rxqs[k]->rx_ring;
4222 cpr = rxqs[k]->cp_ring;
4224 ring_id = rxr->rx_ring_struct->fw_ring_id;
4225 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4226 ring_id = cpr->cp_ring_struct->fw_ring_id;
4227 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4229 if (++k == max_rings)
4232 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4235 HWRM_CHECK_RESULT();
4242 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4244 unsigned int rss_idx, fw_idx, i;
4246 if (!(vnic->rss_table && vnic->hash_type))
4249 if (BNXT_CHIP_THOR(bp))
4250 return bnxt_vnic_rss_configure_thor(bp, vnic);
4253 * Fill the RSS hash & redirection table with
4254 * ring group ids for all VNICs
4256 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4257 rss_idx++, fw_idx++) {
4258 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4259 fw_idx %= bp->rx_cp_nr_rings;
4260 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4264 if (i == bp->rx_cp_nr_rings)
4266 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4268 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4271 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4272 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4276 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4278 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4279 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4281 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4282 req->num_cmpl_dma_aggr_during_int =
4283 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4285 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4287 /* min timer set to 1/2 of interrupt timer */
4288 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4290 /* buf timer set to 1/4 of interrupt timer */
4291 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4293 req->cmpl_aggr_dma_tmr_during_int =
4294 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4296 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4297 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4298 req->flags = rte_cpu_to_le_16(flags);
4301 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4302 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4304 struct hwrm_ring_aggint_qcaps_input req = {0};
4305 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4310 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4311 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4312 HWRM_CHECK_RESULT();
4314 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4315 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4317 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4318 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4319 agg_req->flags = rte_cpu_to_le_16(flags);
4321 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4322 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4323 agg_req->enables = rte_cpu_to_le_32(enables);
4329 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4330 struct bnxt_coal *coal, uint16_t ring_id)
4332 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4333 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4334 bp->hwrm_cmd_resp_addr;
4337 /* Set ring coalesce parameters only for 100G NICs */
4338 if (BNXT_CHIP_THOR(bp)) {
4339 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4341 } else if (bnxt_stratus_device(bp)) {
4342 bnxt_hwrm_set_coal_params(coal, &req);
4347 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4348 req.ring_id = rte_cpu_to_le_16(ring_id);
4349 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4350 HWRM_CHECK_RESULT();
4355 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4356 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4358 struct hwrm_func_backing_store_qcaps_input req = {0};
4359 struct hwrm_func_backing_store_qcaps_output *resp =
4360 bp->hwrm_cmd_resp_addr;
4363 if (!BNXT_CHIP_THOR(bp) ||
4364 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4369 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4370 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4371 HWRM_CHECK_RESULT_SILENT();
4374 struct bnxt_ctx_pg_info *ctx_pg;
4375 struct bnxt_ctx_mem_info *ctx;
4376 int total_alloc_len;
4379 total_alloc_len = sizeof(*ctx);
4380 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4381 RTE_CACHE_LINE_SIZE);
4386 memset(ctx, 0, total_alloc_len);
4388 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4389 sizeof(*ctx_pg) * BNXT_MAX_Q,
4390 RTE_CACHE_LINE_SIZE);
4395 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4396 ctx->tqm_mem[i] = ctx_pg;
4399 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4400 ctx->qp_min_qp1_entries =
4401 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4402 ctx->qp_max_l2_entries =
4403 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4404 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4405 ctx->srq_max_l2_entries =
4406 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4407 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4408 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4409 ctx->cq_max_l2_entries =
4410 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4411 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4412 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4413 ctx->vnic_max_vnic_entries =
4414 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4415 ctx->vnic_max_ring_table_entries =
4416 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4417 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4418 ctx->stat_max_entries =
4419 rte_le_to_cpu_32(resp->stat_max_entries);
4420 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4421 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4422 ctx->tqm_min_entries_per_ring =
4423 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4424 ctx->tqm_max_entries_per_ring =
4425 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4426 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4427 if (!ctx->tqm_entries_multiple)
4428 ctx->tqm_entries_multiple = 1;
4429 ctx->mrav_max_entries =
4430 rte_le_to_cpu_32(resp->mrav_max_entries);
4431 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4432 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4433 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4442 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4444 struct hwrm_func_backing_store_cfg_input req = {0};
4445 struct hwrm_func_backing_store_cfg_output *resp =
4446 bp->hwrm_cmd_resp_addr;
4447 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4448 struct bnxt_ctx_pg_info *ctx_pg;
4449 uint32_t *num_entries;
4458 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4459 req.enables = rte_cpu_to_le_32(enables);
4461 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4462 ctx_pg = &ctx->qp_mem;
4463 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4464 req.qp_num_qp1_entries =
4465 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4466 req.qp_num_l2_entries =
4467 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4468 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4469 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4470 &req.qpc_pg_size_qpc_lvl,
4474 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4475 ctx_pg = &ctx->srq_mem;
4476 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4477 req.srq_num_l2_entries =
4478 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4479 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4480 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4481 &req.srq_pg_size_srq_lvl,
4485 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4486 ctx_pg = &ctx->cq_mem;
4487 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4488 req.cq_num_l2_entries =
4489 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4490 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4491 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4492 &req.cq_pg_size_cq_lvl,
4496 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4497 ctx_pg = &ctx->vnic_mem;
4498 req.vnic_num_vnic_entries =
4499 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4500 req.vnic_num_ring_table_entries =
4501 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4502 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4503 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4504 &req.vnic_pg_size_vnic_lvl,
4505 &req.vnic_page_dir);
4508 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4509 ctx_pg = &ctx->stat_mem;
4510 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4511 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4512 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4513 &req.stat_pg_size_stat_lvl,
4514 &req.stat_page_dir);
4517 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4518 num_entries = &req.tqm_sp_num_entries;
4519 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4520 pg_dir = &req.tqm_sp_page_dir;
4521 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4522 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4523 if (!(enables & ena))
4526 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4528 ctx_pg = ctx->tqm_mem[i];
4529 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4530 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4533 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4534 HWRM_CHECK_RESULT();
4540 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4542 struct hwrm_port_qstats_ext_input req = {0};
4543 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4544 struct bnxt_pf_info *pf = &bp->pf;
4547 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4548 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4551 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4553 req.port_id = rte_cpu_to_le_16(pf->port_id);
4554 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4555 req.tx_stat_host_addr =
4556 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4558 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4560 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4561 req.rx_stat_host_addr =
4562 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4564 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4566 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4569 bp->fw_rx_port_stats_ext_size = 0;
4570 bp->fw_tx_port_stats_ext_size = 0;
4572 bp->fw_rx_port_stats_ext_size =
4573 rte_le_to_cpu_16(resp->rx_stat_size);
4574 bp->fw_tx_port_stats_ext_size =
4575 rte_le_to_cpu_16(resp->tx_stat_size);
4578 HWRM_CHECK_RESULT();
4585 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4587 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4588 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4589 bp->hwrm_cmd_resp_addr;
4592 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4593 req.tunnel_type = type;
4594 req.dest_fid = bp->fw_fid;
4595 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4596 HWRM_CHECK_RESULT();
4604 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4606 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4607 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4608 bp->hwrm_cmd_resp_addr;
4611 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4612 req.tunnel_type = type;
4613 req.dest_fid = bp->fw_fid;
4614 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4615 HWRM_CHECK_RESULT();
4622 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4624 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4625 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4626 bp->hwrm_cmd_resp_addr;
4629 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4630 req.src_fid = bp->fw_fid;
4631 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4632 HWRM_CHECK_RESULT();
4635 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4642 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4645 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4646 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4647 bp->hwrm_cmd_resp_addr;
4650 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4651 req.src_fid = bp->fw_fid;
4652 req.tunnel_type = tun_type;
4653 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4654 HWRM_CHECK_RESULT();
4657 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4659 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4666 int bnxt_hwrm_set_mac(struct bnxt *bp)
4668 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4669 struct hwrm_func_vf_cfg_input req = {0};
4675 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4678 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4679 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4681 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4683 HWRM_CHECK_RESULT();
4685 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4691 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4693 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4694 struct hwrm_func_drv_if_change_input req = {0};
4698 if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4701 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4702 * If we issue FUNC_DRV_IF_CHANGE with flags down before
4703 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4705 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4708 HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4712 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4714 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4716 HWRM_CHECK_RESULT();
4717 flags = rte_le_to_cpu_32(resp->flags);
4720 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4721 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4722 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4728 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4730 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4731 struct bnxt_error_recovery_info *info = bp->recovery_info;
4732 struct hwrm_error_recovery_qcfg_input req = {0};
4737 /* Older FW does not have error recovery support */
4738 if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4742 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4744 bp->recovery_info = info;
4748 memset(info, 0, sizeof(*info));
4751 HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4753 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4755 HWRM_CHECK_RESULT();
4757 flags = rte_le_to_cpu_32(resp->flags);
4758 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4759 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4760 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4761 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4763 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4764 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4769 /* FW returned values are in units of 100msec */
4770 info->driver_polling_freq =
4771 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4772 info->master_func_wait_period =
4773 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4774 info->normal_func_wait_period =
4775 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4776 info->master_func_wait_period_after_reset =
4777 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4778 info->max_bailout_time_after_reset =
4779 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4780 info->status_regs[BNXT_FW_STATUS_REG] =
4781 rte_le_to_cpu_32(resp->fw_health_status_reg);
4782 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4783 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4784 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4785 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4786 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4787 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4788 info->reg_array_cnt =
4789 rte_le_to_cpu_32(resp->reg_array_cnt);
4791 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4796 for (i = 0; i < info->reg_array_cnt; i++) {
4797 info->reset_reg[i] =
4798 rte_le_to_cpu_32(resp->reset_reg[i]);
4799 info->reset_reg_val[i] =
4800 rte_le_to_cpu_32(resp->reset_reg_val[i]);
4801 info->delay_after_reset[i] =
4802 resp->delay_after_reset[i];
4807 /* Map the FW status registers */
4809 rc = bnxt_map_fw_health_status_regs(bp);
4812 rte_free(bp->recovery_info);
4813 bp->recovery_info = NULL;
4818 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4820 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4821 struct hwrm_fw_reset_input req = {0};
4827 HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4829 req.embedded_proc_type =
4830 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4831 req.selfrst_status =
4832 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4833 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4835 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4838 HWRM_CHECK_RESULT();
4844 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4846 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4847 struct hwrm_port_ts_query_input req = {0};
4848 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4855 HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4858 case BNXT_PTP_FLAGS_PATH_TX:
4859 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4861 case BNXT_PTP_FLAGS_PATH_RX:
4862 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4864 case BNXT_PTP_FLAGS_CURRENT_TIME:
4865 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
4869 req.flags = rte_cpu_to_le_32(flags);
4870 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
4872 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4874 HWRM_CHECK_RESULT();
4877 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
4879 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;