drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SHORT_CMD_TIMEOUT          50000
  31 #define HWRM_SPEC_CODE_1_8_3            0x10803
  32 #define HWRM_VERSION_1_9_1              0x10901
  33 #define HWRM_VERSION_1_9_2              0x10903
  34
  35 struct bnxt_plcmodes_cfg {
  36         uint32_t        flags;
  37         uint16_t        jumbo_thresh;
  38         uint16_t        hds_offset;
  39         uint16_t        hds_threshold;
  40 };
  41
  42 static int page_getenum(size_t size)
  43 {
  44         if (size <= 1 << 4)
  45                 return 4;
  46         if (size <= 1 << 12)
  47                 return 12;
  48         if (size <= 1 << 13)
  49                 return 13;
  50         if (size <= 1 << 16)
  51                 return 16;
  52         if (size <= 1 << 21)
  53                 return 21;
  54         if (size <= 1 << 22)
  55                 return 22;
  56         if (size <= 1 << 30)
  57                 return 30;
  58         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  59         return sizeof(void *) * 8 - 1;
  60 }
  61
  62 static int page_roundup(size_t size)
  63 {
  64         return 1 << page_getenum(size);
  65 }
  66
  67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  68                                   uint8_t *pg_attr,
  69                                   uint64_t *pg_dir)
  70 {
  71         if (rmem->nr_pages > 1) {
  72                 *pg_attr = 1;
  73                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  74         } else {
  75                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  76         }
  77 }
  78
  79 /*
  80  * HWRM Functions (sent to HWRM)
  81  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  82  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  83  * command was failed by the ChiMP.
  84  */
  85
  86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  87                                   uint32_t msg_len, bool use_kong_mb)
  88 {
  89         unsigned int i;
  90         struct input *req = msg;
  91         struct output *resp = bp->hwrm_cmd_resp_addr;
  92         uint32_t *data = msg;
  93         uint8_t *bar;
  94         uint8_t *valid;
  95         uint16_t max_req_len = bp->max_req_len;
  96         struct hwrm_short_input short_input = { 0 };
  97         uint16_t bar_offset = use_kong_mb ?
  98                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  99         uint16_t mb_trigger_offset = use_kong_mb ?
 100                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 101         uint32_t timeout;
 102
 103         /* Do not send HWRM commands to firmware in error state */
 104         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 105                 return 0;
 106
 107         /* For VER_GET command, set timeout as 50ms */
 108         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 109                 timeout = HWRM_SHORT_CMD_TIMEOUT;
 110         else
 111                 timeout = HWRM_CMD_TIMEOUT;
 112
 113         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 114             msg_len > bp->max_req_len) {
 115                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 116
 117                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 118                 memcpy(short_cmd_req, req, msg_len);
 119
 120                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 121                 short_input.signature = rte_cpu_to_le_16(
 122                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 123                 short_input.size = rte_cpu_to_le_16(msg_len);
 124                 short_input.req_addr =
 125                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 126
 127                 data = (uint32_t *)&short_input;
 128                 msg_len = sizeof(short_input);
 129
 130                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 131         }
 132
 133         /* Write request msg to hwrm channel */
 134         for (i = 0; i < msg_len; i += 4) {
 135                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 136                 rte_write32(*data, bar);
 137                 data++;
 138         }
 139
 140         /* Zero the rest of the request space */
 141         for (; i < max_req_len; i += 4) {
 142                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 143                 rte_write32(0, bar);
 144         }
 145
 146         /* Ring channel doorbell */
 147         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 148         rte_write32(1, bar);
 149         /*
 150          * Make sure the channel doorbell ring command complete before
 151          * reading the response to avoid getting stale or invalid
 152          * responses.
 153          */
 154         rte_io_mb();
 155
 156         /* Poll for the valid bit */
 157         for (i = 0; i < timeout; i++) {
 158                 /* Sanity check on the resp->resp_len */
 159                 rte_cio_rmb();
 160                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 161                         /* Last byte of resp contains the valid key */
 162                         valid = (uint8_t *)resp + resp->resp_len - 1;
 163                         if (*valid == HWRM_RESP_VALID_KEY)
 164                                 break;
 165                 }
 166                 rte_delay_us(1);
 167         }
 168
 169         if (i >= timeout) {
 170                 /* Suppress VER_GET timeout messages during reset recovery */
 171                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 172                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 173                         return -ETIMEDOUT;
 174
 175                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 176                             req->req_type);
 177                 return -ETIMEDOUT;
 178         }
 179         return 0;
 180 }
 181
 182 /*
 183  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 184  * spinlock, and does initial processing.
 185  *
 186  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 187  * releases the spinlock only if it returns.  If the regular int return codes
 188  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 189  * directly, rather it should be copied and modified to suit the function.
 190  *
 191  * HWRM_UNLOCK() must be called after all response processing is completed.
 192  */
 193 #define HWRM_PREP(req, type, kong) do { \
 194         rte_spinlock_lock(&bp->hwrm_lock); \
 195         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 196         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 197         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 198         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 199                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 200         req.target_id = rte_cpu_to_le_16(0xffff); \
 201         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 202 } while (0)
 203
 204 #define HWRM_CHECK_RESULT_SILENT() do {\
 205         if (rc) { \
 206                 rte_spinlock_unlock(&bp->hwrm_lock); \
 207                 return rc; \
 208         } \
 209         if (resp->error_code) { \
 210                 rc = rte_le_to_cpu_16(resp->error_code); \
 211                 rte_spinlock_unlock(&bp->hwrm_lock); \
 212                 return rc; \
 213         } \
 214 } while (0)
 215
 216 #define HWRM_CHECK_RESULT() do {\
 217         if (rc) { \
 218                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 219                 rte_spinlock_unlock(&bp->hwrm_lock); \
 220                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 221                         rc = -EACCES; \
 222                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 223                         rc = -ENOSPC; \
 224                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 225                         rc = -EINVAL; \
 226                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 227                         rc = -ENOTSUP; \
 228                 else if (rc > 0) \
 229                         rc = -EIO; \
 230                 return rc; \
 231         } \
 232         if (resp->error_code) { \
 233                 rc = rte_le_to_cpu_16(resp->error_code); \
 234                 if (resp->resp_len >= 16) { \
 235                         struct hwrm_err_output *tmp_hwrm_err_op = \
 236                                                 (void *)resp; \
 237                         PMD_DRV_LOG(ERR, \
 238                                 "error %d:%d:%08x:%04x\n", \
 239                                 rc, tmp_hwrm_err_op->cmd_err, \
 240                                 rte_le_to_cpu_32(\
 241                                         tmp_hwrm_err_op->opaque_0), \
 242                                 rte_le_to_cpu_16(\
 243                                         tmp_hwrm_err_op->opaque_1)); \
 244                 } else { \
 245                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 246                 } \
 247                 rte_spinlock_unlock(&bp->hwrm_lock); \
 248                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 249                         rc = -EACCES; \
 250                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 251                         rc = -ENOSPC; \
 252                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 253                         rc = -EINVAL; \
 254                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 255                         rc = -ENOTSUP; \
 256                 else if (rc > 0) \
 257                         rc = -EIO; \
 258                 return rc; \
 259         } \
 260 } while (0)
 261
 262 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 263
 264 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 265 {
 266         int rc = 0;
 267         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 268         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 269
 270         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 271         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 272         req.mask = 0;
 273
 274         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 275
 276         HWRM_CHECK_RESULT();
 277         HWRM_UNLOCK();
 278
 279         return rc;
 280 }
 281
 282 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 283                                  struct bnxt_vnic_info *vnic,
 284                                  uint16_t vlan_count,
 285                                  struct bnxt_vlan_table_entry *vlan_table)
 286 {
 287         int rc = 0;
 288         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 289         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 290         uint32_t mask = 0;
 291
 292         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 293                 return rc;
 294
 295         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 296         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 297
 298         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 299                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 300         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 301                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 302
 303         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 304                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 305
 306         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 307                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 308         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 309                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 310                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 311                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 312         }
 313         if (vlan_table) {
 314                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 315                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 316                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 317                          rte_mem_virt2iova(vlan_table));
 318                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 319         }
 320         req.mask = rte_cpu_to_le_32(mask);
 321
 322         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 323
 324         HWRM_CHECK_RESULT();
 325         HWRM_UNLOCK();
 326
 327         return rc;
 328 }
 329
 330 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 331                         uint16_t vlan_count,
 332                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 333 {
 334         int rc = 0;
 335         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 336         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 337                                                 bp->hwrm_cmd_resp_addr;
 338
 339         /*
 340          * Older HWRM versions did not support this command, and the set_rx_mask
 341          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 342          * removed from set_rx_mask call, and this command was added.
 343          *
 344          * This command is also present from 1.7.8.11 and higher,
 345          * as well as 1.7.8.0
 346          */
 347         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 348                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 349                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 350                                         (11)))
 351                                 return 0;
 352                 }
 353         }
 354         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 355         req.fid = rte_cpu_to_le_16(fid);
 356
 357         req.vlan_tag_mask_tbl_addr =
 358                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 359         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 360
 361         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 362
 363         HWRM_CHECK_RESULT();
 364         HWRM_UNLOCK();
 365
 366         return rc;
 367 }
 368
 369 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 370                            struct bnxt_filter_info *filter)
 371 {
 372         int rc = 0;
 373         struct bnxt_filter_info *l2_filter = filter;
 374         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 375         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 376
 377         if (filter->fw_l2_filter_id == UINT64_MAX)
 378                 return 0;
 379
 380         if (filter->matching_l2_fltr_ptr)
 381                 l2_filter = filter->matching_l2_fltr_ptr;
 382
 383         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 384                     filter, l2_filter, l2_filter->l2_ref_cnt);
 385
 386         if (l2_filter->l2_ref_cnt > 0)
 387                 l2_filter->l2_ref_cnt--;
 388
 389         if (l2_filter->l2_ref_cnt > 0)
 390                 return 0;
 391
 392         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 393
 394         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 395
 396         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 397
 398         HWRM_CHECK_RESULT();
 399         HWRM_UNLOCK();
 400
 401         filter->fw_l2_filter_id = UINT64_MAX;
 402
 403         return 0;
 404 }
 405
 406 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 407                          uint16_t dst_id,
 408                          struct bnxt_filter_info *filter)
 409 {
 410         int rc = 0;
 411         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 412         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 413         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 414         const struct rte_eth_vmdq_rx_conf *conf =
 415                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 416         uint32_t enables = 0;
 417         uint16_t j = dst_id - 1;
 418
 419         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 420         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 421             conf->pool_map[j].pools & (1UL << j)) {
 422                 PMD_DRV_LOG(DEBUG,
 423                         "Add vlan %u to vmdq pool %u\n",
 424                         conf->pool_map[j].vlan_id, j);
 425
 426                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 427                 filter->enables |=
 428                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 429                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 430         }
 431
 432         if (filter->fw_l2_filter_id != UINT64_MAX)
 433                 bnxt_hwrm_clear_l2_filter(bp, filter);
 434
 435         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 436
 437         req.flags = rte_cpu_to_le_32(filter->flags);
 438
 439         enables = filter->enables |
 440               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 441         req.dst_id = rte_cpu_to_le_16(dst_id);
 442
 443         if (enables &
 444             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 445                 memcpy(req.l2_addr, filter->l2_addr,
 446                        RTE_ETHER_ADDR_LEN);
 447         if (enables &
 448             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 449                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 450                        RTE_ETHER_ADDR_LEN);
 451         if (enables &
 452             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 453                 req.l2_ovlan = filter->l2_ovlan;
 454         if (enables &
 455             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 456                 req.l2_ivlan = filter->l2_ivlan;
 457         if (enables &
 458             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 459                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 460         if (enables &
 461             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 462                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 463         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 464                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 465         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 466                 req.src_type = filter->src_type;
 467         if (filter->pri_hint) {
 468                 req.pri_hint = filter->pri_hint;
 469                 req.l2_filter_id_hint =
 470                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 471         }
 472
 473         req.enables = rte_cpu_to_le_32(enables);
 474
 475         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 476
 477         HWRM_CHECK_RESULT();
 478
 479         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 480         HWRM_UNLOCK();
 481
 482         return rc;
 483 }
 484
 485 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 486 {
 487         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 488         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 489         uint32_t flags = 0;
 490         int rc;
 491
 492         if (!ptp)
 493                 return 0;
 494
 495         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 496
 497         if (ptp->rx_filter)
 498                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 499         else
 500                 flags |=
 501                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 502         if (ptp->tx_tstamp_en)
 503                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 504         else
 505                 flags |=
 506                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 507         req.flags = rte_cpu_to_le_32(flags);
 508         req.enables = rte_cpu_to_le_32
 509                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 510         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 511
 512         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 513         HWRM_UNLOCK();
 514
 515         return rc;
 516 }
 517
 518 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 519 {
 520         int rc = 0;
 521         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 522         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 523         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 524
 525 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 526         if (ptp)
 527                 return 0;
 528
 529         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 530
 531         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 532
 533         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 534
 535         HWRM_CHECK_RESULT();
 536
 537         if (!BNXT_CHIP_THOR(bp) &&
 538             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 539                 return 0;
 540
 541         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 542                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 543
 544         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 545         if (!ptp)
 546                 return -ENOMEM;
 547
 548         if (!BNXT_CHIP_THOR(bp)) {
 549                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 550                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 551                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 552                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 553                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 554                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 555                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 556                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 557                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 558                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 559                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 560                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 561                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 562                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 563                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 564                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 565                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 566                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 567         }
 568
 569         ptp->bp = bp;
 570         bp->ptp_cfg = ptp;
 571
 572         return 0;
 573 }
 574
 575 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 576 {
 577         int rc = 0;
 578         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 579         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 580         uint16_t new_max_vfs;
 581         uint32_t flags;
 582         int i;
 583
 584         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 585
 586         req.fid = rte_cpu_to_le_16(0xffff);
 587
 588         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 589
 590         HWRM_CHECK_RESULT();
 591
 592         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 593         flags = rte_le_to_cpu_32(resp->flags);
 594         if (BNXT_PF(bp)) {
 595                 bp->pf.port_id = resp->port_id;
 596                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 597                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 598                 new_max_vfs = bp->pdev->max_vfs;
 599                 if (new_max_vfs != bp->pf.max_vfs) {
 600                         if (bp->pf.vf_info)
 601                                 rte_free(bp->pf.vf_info);
 602                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 603                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 604                         bp->pf.max_vfs = new_max_vfs;
 605                         for (i = 0; i < new_max_vfs; i++) {
 606                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 607                                 bp->pf.vf_info[i].vlan_table =
 608                                         rte_zmalloc("VF VLAN table",
 609                                                     getpagesize(),
 610                                                     getpagesize());
 611                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 612                                         PMD_DRV_LOG(ERR,
 613                                         "Fail to alloc VLAN table for VF %d\n",
 614                                         i);
 615                                 else
 616                                         rte_mem_lock_page(
 617                                                 bp->pf.vf_info[i].vlan_table);
 618                                 bp->pf.vf_info[i].vlan_as_table =
 619                                         rte_zmalloc("VF VLAN AS table",
 620                                                     getpagesize(),
 621                                                     getpagesize());
 622                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 623                                         PMD_DRV_LOG(ERR,
 624                                         "Alloc VLAN AS table for VF %d fail\n",
 625                                         i);
 626                                 else
 627                                         rte_mem_lock_page(
 628                                                bp->pf.vf_info[i].vlan_as_table);
 629                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 630                         }
 631                 }
 632         }
 633
 634         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 635         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 636         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 637         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 638         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 639         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 640         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 641         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 642         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 643         if (!BNXT_CHIP_THOR(bp))
 644                 bp->max_l2_ctx += bp->max_rx_em_flows;
 645         /* TODO: For now, do not support VMDq/RFS on VFs. */
 646         if (BNXT_PF(bp)) {
 647                 if (bp->pf.max_vfs)
 648                         bp->max_vnics = 1;
 649                 else
 650                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 651         } else {
 652                 bp->max_vnics = 1;
 653         }
 654         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 655         if (BNXT_PF(bp)) {
 656                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 657                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 658                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 659                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 660                         HWRM_UNLOCK();
 661                         bnxt_hwrm_ptp_qcfg(bp);
 662                 }
 663         }
 664
 665         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 666                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 667
 668         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 669                 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 670                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 671         } else {
 672                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 673         }
 674
 675         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 676                 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 677         else
 678                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 679
 680         HWRM_UNLOCK();
 681
 682         return rc;
 683 }
 684
 685 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 686 {
 687         int rc;
 688
 689         rc = __bnxt_hwrm_func_qcaps(bp);
 690         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 691                 rc = bnxt_alloc_ctx_mem(bp);
 692                 if (rc)
 693                         return rc;
 694
 695                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 696                 if (!rc)
 697                         bp->flags |= BNXT_FLAG_NEW_RM;
 698         }
 699
 700         return rc;
 701 }
 702
 703 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 704 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 705 {
 706         int rc = 0;
 707         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 708         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 709
 710         HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 711
 712         req.target_id = rte_cpu_to_le_16(0xffff);
 713
 714         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 715
 716         HWRM_CHECK_RESULT();
 717
 718         if (rte_le_to_cpu_32(resp->flags) &
 719             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 720                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 721                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 722         }
 723
 724         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 725
 726         HWRM_UNLOCK();
 727
 728         return rc;
 729 }
 730
 731 int bnxt_hwrm_func_reset(struct bnxt *bp)
 732 {
 733         int rc = 0;
 734         struct hwrm_func_reset_input req = {.req_type = 0 };
 735         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 736
 737         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 738
 739         req.enables = rte_cpu_to_le_32(0);
 740
 741         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 742
 743         HWRM_CHECK_RESULT();
 744         HWRM_UNLOCK();
 745
 746         return rc;
 747 }
 748
 749 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 750 {
 751         int rc;
 752         uint32_t flags = 0;
 753         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 754         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 755
 756         if (bp->flags & BNXT_FLAG_REGISTERED)
 757                 return 0;
 758
 759         flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 760         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 761                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 762
 763         /* PFs and trusted VFs should indicate the support of the
 764          * Master capability on non Stingray platform
 765          */
 766         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 767                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 768
 769         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 770         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 771                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 772         req.ver_maj = RTE_VER_YEAR;
 773         req.ver_min = RTE_VER_MONTH;
 774         req.ver_upd = RTE_VER_MINOR;
 775
 776         if (BNXT_PF(bp)) {
 777                 req.enables |= rte_cpu_to_le_32(
 778                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 779                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 780                        RTE_MIN(sizeof(req.vf_req_fwd),
 781                                sizeof(bp->pf.vf_req_fwd)));
 782
 783                 /*
 784                  * PF can sniff HWRM API issued by VF. This can be set up by
 785                  * linux driver and inherited by the DPDK PF driver. Clear
 786                  * this HWRM sniffer list in FW because DPDK PF driver does
 787                  * not support this.
 788                  */
 789                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 790         }
 791
 792         req.flags = rte_cpu_to_le_32(flags);
 793
 794         req.async_event_fwd[0] |=
 795                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 796                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 797                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 798                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 799                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 800         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 801                 req.async_event_fwd[0] |=
 802                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 803         req.async_event_fwd[1] |=
 804                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 805                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 806
 807         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 808
 809         HWRM_CHECK_RESULT();
 810
 811         flags = rte_le_to_cpu_32(resp->flags);
 812         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 813                 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
 814
 815         HWRM_UNLOCK();
 816
 817         bp->flags |= BNXT_FLAG_REGISTERED;
 818
 819         return rc;
 820 }
 821
 822 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 823 {
 824         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 825                 return 0;
 826
 827         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 828 }
 829
 830 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 831 {
 832         int rc;
 833         uint32_t flags = 0;
 834         uint32_t enables;
 835         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 836         struct hwrm_func_vf_cfg_input req = {0};
 837
 838         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 839
 840         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 841                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 842                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 843                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 844                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 845
 846         if (BNXT_HAS_RING_GRPS(bp)) {
 847                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 848                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 849         }
 850
 851         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 852         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 853                                             AGG_RING_MULTIPLIER);
 854         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
 855                                              bp->tx_nr_rings +
 856                                              BNXT_NUM_ASYNC_CPR(bp));
 857         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 858                                               bp->tx_nr_rings +
 859                                               BNXT_NUM_ASYNC_CPR(bp));
 860         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 861         if (bp->vf_resv_strategy ==
 862             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 863                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 864                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 865                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 866                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 867                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 868                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 869         }
 870
 871         if (test)
 872                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 873                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 874                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 875                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 876                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 877                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 878
 879         if (test && BNXT_HAS_RING_GRPS(bp))
 880                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 881
 882         req.flags = rte_cpu_to_le_32(flags);
 883         req.enables |= rte_cpu_to_le_32(enables);
 884
 885         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 886
 887         if (test)
 888                 HWRM_CHECK_RESULT_SILENT();
 889         else
 890                 HWRM_CHECK_RESULT();
 891
 892         HWRM_UNLOCK();
 893         return rc;
 894 }
 895
 896 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 897 {
 898         int rc;
 899         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 900         struct hwrm_func_resource_qcaps_input req = {0};
 901
 902         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 903         req.fid = rte_cpu_to_le_16(0xffff);
 904
 905         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 906
 907         HWRM_CHECK_RESULT();
 908
 909         if (BNXT_VF(bp)) {
 910                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 911                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 912                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 913                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 914                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 915                 /* func_resource_qcaps does not return max_rx_em_flows.
 916                  * So use the value provided by func_qcaps.
 917                  */
 918                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 919                 if (!BNXT_CHIP_THOR(bp))
 920                         bp->max_l2_ctx += bp->max_rx_em_flows;
 921                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 922                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 923         }
 924         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 925         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 926         if (bp->vf_resv_strategy >
 927             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 928                 bp->vf_resv_strategy =
 929                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 930
 931         HWRM_UNLOCK();
 932         return rc;
 933 }
 934
 935 int bnxt_hwrm_ver_get(struct bnxt *bp)
 936 {
 937         int rc = 0;
 938         struct hwrm_ver_get_input req = {.req_type = 0 };
 939         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 940         uint32_t fw_version;
 941         uint16_t max_resp_len;
 942         char type[RTE_MEMZONE_NAMESIZE];
 943         uint32_t dev_caps_cfg;
 944
 945         bp->max_req_len = HWRM_MAX_REQ_LEN;
 946         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 947
 948         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 949         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 950         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 951
 952         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 953
 954         if (bp->flags & BNXT_FLAG_FW_RESET)
 955                 HWRM_CHECK_RESULT_SILENT();
 956         else
 957                 HWRM_CHECK_RESULT();
 958
 959         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 960                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 961                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 962                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 963         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 964                      (resp->hwrm_fw_min_8b << 16) |
 965                      (resp->hwrm_fw_bld_8b << 8) |
 966                      resp->hwrm_fw_rsvd_8b;
 967         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 968                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 969
 970         fw_version = resp->hwrm_intf_maj_8b << 16;
 971         fw_version |= resp->hwrm_intf_min_8b << 8;
 972         fw_version |= resp->hwrm_intf_upd_8b;
 973         bp->hwrm_spec_code = fw_version;
 974
 975         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 976                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 977                 rc = -EINVAL;
 978                 goto error;
 979         }
 980
 981         if (bp->max_req_len > resp->max_req_win_len) {
 982                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 983                 rc = -EINVAL;
 984         }
 985         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 986         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 987         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 988                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 989
 990         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 991         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 992
 993         if (bp->max_resp_len != max_resp_len) {
 994                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 995                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 996                         bp->pdev->addr.devid, bp->pdev->addr.function);
 997
 998                 rte_free(bp->hwrm_cmd_resp_addr);
 999
1000                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1001                 if (bp->hwrm_cmd_resp_addr == NULL) {
1002                         rc = -ENOMEM;
1003                         goto error;
1004                 }
1005                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1006                 bp->hwrm_cmd_resp_dma_addr =
1007                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1008                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1009                         PMD_DRV_LOG(ERR,
1010                         "Unable to map response buffer to physical memory.\n");
1011                         rc = -ENOMEM;
1012                         goto error;
1013                 }
1014                 bp->max_resp_len = max_resp_len;
1015         }
1016
1017         if ((dev_caps_cfg &
1018                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1019             (dev_caps_cfg &
1020              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1021                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1022                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1023         }
1024
1025         if (((dev_caps_cfg &
1026               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1027              (dev_caps_cfg &
1028               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1029             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1030                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1031                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1032                         bp->pdev->addr.devid, bp->pdev->addr.function);
1033
1034                 rte_free(bp->hwrm_short_cmd_req_addr);
1035
1036                 bp->hwrm_short_cmd_req_addr =
1037                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1038                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1039                         rc = -ENOMEM;
1040                         goto error;
1041                 }
1042                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1043                 bp->hwrm_short_cmd_req_dma_addr =
1044                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1045                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1046                         rte_free(bp->hwrm_short_cmd_req_addr);
1047                         PMD_DRV_LOG(ERR,
1048                                 "Unable to map buffer to physical memory.\n");
1049                         rc = -ENOMEM;
1050                         goto error;
1051                 }
1052         }
1053         if (dev_caps_cfg &
1054             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1055                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1056                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1057         }
1058         if (dev_caps_cfg &
1059             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1060                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1061         if (dev_caps_cfg &
1062             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1063                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1064                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1065         }
1066
1067 error:
1068         HWRM_UNLOCK();
1069         return rc;
1070 }
1071
1072 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1073 {
1074         int rc;
1075         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1076         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1077
1078         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1079                 return 0;
1080
1081         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1082         req.flags = flags;
1083
1084         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1085
1086         HWRM_CHECK_RESULT();
1087         HWRM_UNLOCK();
1088
1089         return rc;
1090 }
1091
1092 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1093 {
1094         int rc = 0;
1095         struct hwrm_port_phy_cfg_input req = {0};
1096         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1097         uint32_t enables = 0;
1098
1099         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1100
1101         if (conf->link_up) {
1102                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1103                 if (bp->link_info.auto_mode && conf->link_speed) {
1104                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1105                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1106                 }
1107
1108                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1109                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1110                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1111                 /*
1112                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1113                  * any auto mode, even "none".
1114                  */
1115                 if (!conf->link_speed) {
1116                         /* No speeds specified. Enable AutoNeg - all speeds */
1117                         req.auto_mode =
1118                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1119                 }
1120                 /* AutoNeg - Advertise speeds specified. */
1121                 if (conf->auto_link_speed_mask &&
1122                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1123                         req.auto_mode =
1124                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1125                         req.auto_link_speed_mask =
1126                                 conf->auto_link_speed_mask;
1127                         enables |=
1128                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1129                 }
1130
1131                 req.auto_duplex = conf->duplex;
1132                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1133                 req.auto_pause = conf->auto_pause;
1134                 req.force_pause = conf->force_pause;
1135                 /* Set force_pause if there is no auto or if there is a force */
1136                 if (req.auto_pause && !req.force_pause)
1137                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1138                 else
1139                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1140
1141                 req.enables = rte_cpu_to_le_32(enables);
1142         } else {
1143                 req.flags =
1144                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1145                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1146         }
1147
1148         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1149
1150         HWRM_CHECK_RESULT();
1151         HWRM_UNLOCK();
1152
1153         return rc;
1154 }
1155
1156 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1157                                    struct bnxt_link_info *link_info)
1158 {
1159         int rc = 0;
1160         struct hwrm_port_phy_qcfg_input req = {0};
1161         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1162
1163         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1164
1165         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1166
1167         HWRM_CHECK_RESULT();
1168
1169         link_info->phy_link_status = resp->link;
1170         link_info->link_up =
1171                 (link_info->phy_link_status ==
1172                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1173         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1174         link_info->duplex = resp->duplex_cfg;
1175         link_info->pause = resp->pause;
1176         link_info->auto_pause = resp->auto_pause;
1177         link_info->force_pause = resp->force_pause;
1178         link_info->auto_mode = resp->auto_mode;
1179         link_info->phy_type = resp->phy_type;
1180         link_info->media_type = resp->media_type;
1181
1182         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1183         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1184         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1185         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1186         link_info->phy_ver[0] = resp->phy_maj;
1187         link_info->phy_ver[1] = resp->phy_min;
1188         link_info->phy_ver[2] = resp->phy_bld;
1189
1190         HWRM_UNLOCK();
1191
1192         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1193         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1194         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1195         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1196         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1197                     link_info->auto_link_speed_mask);
1198         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1199                     link_info->force_link_speed);
1200
1201         return rc;
1202 }
1203
1204 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1205 {
1206         int rc = 0;
1207         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1208         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1209         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1210         int i;
1211
1212 get_rx_info:
1213         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1214
1215         req.flags = rte_cpu_to_le_32(dir);
1216         /* HWRM Version >= 1.9.1 */
1217         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1218                 req.drv_qmap_cap =
1219                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1220         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1221
1222         HWRM_CHECK_RESULT();
1223
1224         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1225                 GET_TX_QUEUE_INFO(0);
1226                 GET_TX_QUEUE_INFO(1);
1227                 GET_TX_QUEUE_INFO(2);
1228                 GET_TX_QUEUE_INFO(3);
1229                 GET_TX_QUEUE_INFO(4);
1230                 GET_TX_QUEUE_INFO(5);
1231                 GET_TX_QUEUE_INFO(6);
1232                 GET_TX_QUEUE_INFO(7);
1233         } else  {
1234                 GET_RX_QUEUE_INFO(0);
1235                 GET_RX_QUEUE_INFO(1);
1236                 GET_RX_QUEUE_INFO(2);
1237                 GET_RX_QUEUE_INFO(3);
1238                 GET_RX_QUEUE_INFO(4);
1239                 GET_RX_QUEUE_INFO(5);
1240                 GET_RX_QUEUE_INFO(6);
1241                 GET_RX_QUEUE_INFO(7);
1242         }
1243
1244         HWRM_UNLOCK();
1245
1246         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1247                 goto done;
1248
1249         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1250                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1251         } else {
1252                 int j;
1253
1254                 /* iterate and find the COSq profile to use for Tx */
1255                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1256                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1257                                 if (bp->tx_cos_queue[i].id != 0xff)
1258                                         bp->tx_cosq_id[j++] =
1259                                                 bp->tx_cos_queue[i].id;
1260                         }
1261                 } else {
1262                         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1263                                 if (bp->tx_cos_queue[i].profile ==
1264                                         HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1265                                         bp->tx_cosq_id[0] =
1266                                                 bp->tx_cos_queue[i].id;
1267                                         break;
1268                                 }
1269                         }
1270                 }
1271         }
1272
1273         bp->max_tc = resp->max_configurable_queues;
1274         bp->max_lltc = resp->max_configurable_lossless_queues;
1275         if (bp->max_tc > BNXT_MAX_QUEUE)
1276                 bp->max_tc = BNXT_MAX_QUEUE;
1277         bp->max_q = bp->max_tc;
1278
1279         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1280                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1281                 goto get_rx_info;
1282         }
1283
1284 done:
1285         return rc;
1286 }
1287
1288 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1289                          struct bnxt_ring *ring,
1290                          uint32_t ring_type, uint32_t map_index,
1291                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1292                          uint16_t tx_cosq_id)
1293 {
1294         int rc = 0;
1295         uint32_t enables = 0;
1296         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1297         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1298         struct rte_mempool *mb_pool;
1299         uint16_t rx_buf_size;
1300
1301         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1302
1303         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1304         req.fbo = rte_cpu_to_le_32(0);
1305         /* Association of ring index with doorbell index */
1306         req.logical_id = rte_cpu_to_le_16(map_index);
1307         req.length = rte_cpu_to_le_32(ring->ring_size);
1308
1309         switch (ring_type) {
1310         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1311                 req.ring_type = ring_type;
1312                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1313                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1314                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1315                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1316                         enables |=
1317                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1318                 break;
1319         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1320                 req.ring_type = ring_type;
1321                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1322                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1323                 if (BNXT_CHIP_THOR(bp)) {
1324                         mb_pool = bp->rx_queues[0]->mb_pool;
1325                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1326                                       RTE_PKTMBUF_HEADROOM;
1327                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1328                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1329                         enables |=
1330                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1331                 }
1332                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1333                         enables |=
1334                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1335                 break;
1336         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1337                 req.ring_type = ring_type;
1338                 if (BNXT_HAS_NQ(bp)) {
1339                         /* Association of cp ring with nq */
1340                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1341                         enables |=
1342                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1343                 }
1344                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1345                 break;
1346         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1347                 req.ring_type = ring_type;
1348                 req.page_size = BNXT_PAGE_SHFT;
1349                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1350                 break;
1351         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1352                 req.ring_type = ring_type;
1353                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1354
1355                 mb_pool = bp->rx_queues[0]->mb_pool;
1356                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1357                               RTE_PKTMBUF_HEADROOM;
1358                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1359                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1360
1361                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1362                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1363                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1364                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1365                 break;
1366         default:
1367                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1368                         ring_type);
1369                 HWRM_UNLOCK();
1370                 return -EINVAL;
1371         }
1372         req.enables = rte_cpu_to_le_32(enables);
1373
1374         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1375
1376         if (rc || resp->error_code) {
1377                 if (rc == 0 && resp->error_code)
1378                         rc = rte_le_to_cpu_16(resp->error_code);
1379                 switch (ring_type) {
1380                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1381                         PMD_DRV_LOG(ERR,
1382                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1383                         HWRM_UNLOCK();
1384                         return rc;
1385                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1386                         PMD_DRV_LOG(ERR,
1387                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1388                         HWRM_UNLOCK();
1389                         return rc;
1390                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1391                         PMD_DRV_LOG(ERR,
1392                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1393                                     rc);
1394                         HWRM_UNLOCK();
1395                         return rc;
1396                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1397                         PMD_DRV_LOG(ERR,
1398                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1399                         HWRM_UNLOCK();
1400                         return rc;
1401                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1402                         PMD_DRV_LOG(ERR,
1403                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1404                         HWRM_UNLOCK();
1405                         return rc;
1406                 default:
1407                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1408                         HWRM_UNLOCK();
1409                         return rc;
1410                 }
1411         }
1412
1413         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1414         HWRM_UNLOCK();
1415         return rc;
1416 }
1417
1418 int bnxt_hwrm_ring_free(struct bnxt *bp,
1419                         struct bnxt_ring *ring, uint32_t ring_type)
1420 {
1421         int rc;
1422         struct hwrm_ring_free_input req = {.req_type = 0 };
1423         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1424
1425         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1426
1427         req.ring_type = ring_type;
1428         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1429
1430         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1431
1432         if (rc || resp->error_code) {
1433                 if (rc == 0 && resp->error_code)
1434                         rc = rte_le_to_cpu_16(resp->error_code);
1435                 HWRM_UNLOCK();
1436
1437                 switch (ring_type) {
1438                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1439                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1440                                 rc);
1441                         return rc;
1442                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1443                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1444                                 rc);
1445                         return rc;
1446                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1447                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1448                                 rc);
1449                         return rc;
1450                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1451                         PMD_DRV_LOG(ERR,
1452                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1453                         return rc;
1454                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1455                         PMD_DRV_LOG(ERR,
1456                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1457                         return rc;
1458                 default:
1459                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1460                         return rc;
1461                 }
1462         }
1463         HWRM_UNLOCK();
1464         return 0;
1465 }
1466
1467 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1468 {
1469         int rc = 0;
1470         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1471         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1472
1473         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1474
1475         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1476         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1477         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1478         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1479
1480         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1481
1482         HWRM_CHECK_RESULT();
1483
1484         bp->grp_info[idx].fw_grp_id =
1485             rte_le_to_cpu_16(resp->ring_group_id);
1486
1487         HWRM_UNLOCK();
1488
1489         return rc;
1490 }
1491
1492 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1493 {
1494         int rc;
1495         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1496         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1497
1498         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1499
1500         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1501
1502         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1503
1504         HWRM_CHECK_RESULT();
1505         HWRM_UNLOCK();
1506
1507         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1508         return rc;
1509 }
1510
1511 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1512 {
1513         int rc = 0;
1514         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1515         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1516
1517         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1518                 return rc;
1519
1520         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1521
1522         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1523
1524         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1525
1526         HWRM_CHECK_RESULT();
1527         HWRM_UNLOCK();
1528
1529         return rc;
1530 }
1531
1532 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1533                                 unsigned int idx __rte_unused)
1534 {
1535         int rc;
1536         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1537         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1538
1539         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1540
1541         req.update_period_ms = rte_cpu_to_le_32(0);
1542
1543         req.stats_dma_addr =
1544             rte_cpu_to_le_64(cpr->hw_stats_map);
1545
1546         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1547
1548         HWRM_CHECK_RESULT();
1549
1550         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1551
1552         HWRM_UNLOCK();
1553
1554         return rc;
1555 }
1556
1557 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1558                                 unsigned int idx __rte_unused)
1559 {
1560         int rc;
1561         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1562         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1563
1564         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1565
1566         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1567
1568         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1569
1570         HWRM_CHECK_RESULT();
1571         HWRM_UNLOCK();
1572
1573         return rc;
1574 }
1575
1576 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1577 {
1578         int rc = 0, i, j;
1579         struct hwrm_vnic_alloc_input req = { 0 };
1580         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1581
1582         if (!BNXT_HAS_RING_GRPS(bp))
1583                 goto skip_ring_grps;
1584
1585         /* map ring groups to this vnic */
1586         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1587                 vnic->start_grp_id, vnic->end_grp_id);
1588         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1589                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1590
1591         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1592         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1593         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1594         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1595
1596 skip_ring_grps:
1597         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1598                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1599         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1600
1601         if (vnic->func_default)
1602                 req.flags =
1603                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1604         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1605
1606         HWRM_CHECK_RESULT();
1607
1608         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1609         HWRM_UNLOCK();
1610         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1611         return rc;
1612 }
1613
1614 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1615                                         struct bnxt_vnic_info *vnic,
1616                                         struct bnxt_plcmodes_cfg *pmode)
1617 {
1618         int rc = 0;
1619         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1620         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1621
1622         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1623
1624         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1625
1626         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1627
1628         HWRM_CHECK_RESULT();
1629
1630         pmode->flags = rte_le_to_cpu_32(resp->flags);
1631         /* dflt_vnic bit doesn't exist in the _cfg command */
1632         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1633         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1634         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1635         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1636
1637         HWRM_UNLOCK();
1638
1639         return rc;
1640 }
1641
1642 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1643                                        struct bnxt_vnic_info *vnic,
1644                                        struct bnxt_plcmodes_cfg *pmode)
1645 {
1646         int rc = 0;
1647         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1648         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1649
1650         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1651                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1652                 return rc;
1653         }
1654
1655         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1656
1657         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1658         req.flags = rte_cpu_to_le_32(pmode->flags);
1659         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1660         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1661         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1662         req.enables = rte_cpu_to_le_32(
1663             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1664             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1665             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1666         );
1667
1668         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1669
1670         HWRM_CHECK_RESULT();
1671         HWRM_UNLOCK();
1672
1673         return rc;
1674 }
1675
1676 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1677 {
1678         int rc = 0;
1679         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1680         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1681         struct bnxt_plcmodes_cfg pmodes = { 0 };
1682         uint32_t ctx_enable_flag = 0;
1683         uint32_t enables = 0;
1684
1685         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1686                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1687                 return rc;
1688         }
1689
1690         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1691         if (rc)
1692                 return rc;
1693
1694         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1695
1696         if (BNXT_CHIP_THOR(bp)) {
1697                 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1698                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1699                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1700
1701                 req.default_rx_ring_id =
1702                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1703                 req.default_cmpl_ring_id =
1704                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1705                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1706                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1707                 goto config_mru;
1708         }
1709
1710         /* Only RSS support for now TBD: COS & LB */
1711         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1712         if (vnic->lb_rule != 0xffff)
1713                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1714         if (vnic->cos_rule != 0xffff)
1715                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1716         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1717                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1718                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1719         }
1720         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1721                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1722                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1723         }
1724
1725         enables |= ctx_enable_flag;
1726         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1727         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1728         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1729         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1730
1731 config_mru:
1732         req.enables = rte_cpu_to_le_32(enables);
1733         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1734         req.mru = rte_cpu_to_le_16(vnic->mru);
1735         /* Configure default VNIC only once. */
1736         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1737                 req.flags |=
1738                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1739                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1740         }
1741         if (vnic->vlan_strip)
1742                 req.flags |=
1743                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1744         if (vnic->bd_stall)
1745                 req.flags |=
1746                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1747         if (vnic->roce_dual)
1748                 req.flags |= rte_cpu_to_le_32(
1749                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1750         if (vnic->roce_only)
1751                 req.flags |= rte_cpu_to_le_32(
1752                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1753         if (vnic->rss_dflt_cr)
1754                 req.flags |= rte_cpu_to_le_32(
1755                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1756
1757         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1758
1759         HWRM_CHECK_RESULT();
1760         HWRM_UNLOCK();
1761
1762         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1763
1764         return rc;
1765 }
1766
1767 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1768                 int16_t fw_vf_id)
1769 {
1770         int rc = 0;
1771         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1772         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1773
1774         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1775                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1776                 return rc;
1777         }
1778         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1779
1780         req.enables =
1781                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1782         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1783         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1784
1785         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1786
1787         HWRM_CHECK_RESULT();
1788
1789         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1790         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1791         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1792         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1793         vnic->mru = rte_le_to_cpu_16(resp->mru);
1794         vnic->func_default = rte_le_to_cpu_32(
1795                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1796         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1797                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1798         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1799                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1800         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1801                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1802         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1803                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1804         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1805                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1806
1807         HWRM_UNLOCK();
1808
1809         return rc;
1810 }
1811
1812 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1813                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1814 {
1815         int rc = 0;
1816         uint16_t ctx_id;
1817         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1818         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1819                                                 bp->hwrm_cmd_resp_addr;
1820
1821         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1822
1823         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1824         HWRM_CHECK_RESULT();
1825
1826         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1827         if (!BNXT_HAS_RING_GRPS(bp))
1828                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1829         else if (ctx_idx == 0)
1830                 vnic->rss_rule = ctx_id;
1831
1832         HWRM_UNLOCK();
1833
1834         return rc;
1835 }
1836
1837 static
1838 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1839                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1840 {
1841         int rc = 0;
1842         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1843         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1844                                                 bp->hwrm_cmd_resp_addr;
1845
1846         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1847                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1848                 return rc;
1849         }
1850         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1851
1852         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1853
1854         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1855
1856         HWRM_CHECK_RESULT();
1857         HWRM_UNLOCK();
1858
1859         return rc;
1860 }
1861
1862 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1863 {
1864         int rc = 0;
1865
1866         if (BNXT_CHIP_THOR(bp)) {
1867                 int j;
1868
1869                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1870                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
1871                                                       vnic,
1872                                                       vnic->fw_grp_ids[j]);
1873                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1874                 }
1875                 vnic->num_lb_ctxts = 0;
1876         } else {
1877                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1878                 vnic->rss_rule = INVALID_HW_RING_ID;
1879         }
1880
1881         return rc;
1882 }
1883
1884 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1885 {
1886         int rc = 0;
1887         struct hwrm_vnic_free_input req = {.req_type = 0 };
1888         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1889
1890         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1891                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1892                 return rc;
1893         }
1894
1895         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1896
1897         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1898
1899         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1900
1901         HWRM_CHECK_RESULT();
1902         HWRM_UNLOCK();
1903
1904         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1905         /* Configure default VNIC again if necessary. */
1906         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1907                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1908
1909         return rc;
1910 }
1911
1912 static int
1913 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1914 {
1915         int i;
1916         int rc = 0;
1917         int nr_ctxs = vnic->num_lb_ctxts;
1918         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1919         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1920
1921         for (i = 0; i < nr_ctxs; i++) {
1922                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1923
1924                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1925                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1926                 req.hash_mode_flags = vnic->hash_mode;
1927
1928                 req.hash_key_tbl_addr =
1929                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1930
1931                 req.ring_grp_tbl_addr =
1932                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1933                                          i * HW_HASH_INDEX_SIZE);
1934                 req.ring_table_pair_index = i;
1935                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1936
1937                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1938                                             BNXT_USE_CHIMP_MB);
1939
1940                 HWRM_CHECK_RESULT();
1941                 HWRM_UNLOCK();
1942         }
1943
1944         return rc;
1945 }
1946
1947 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1948                            struct bnxt_vnic_info *vnic)
1949 {
1950         int rc = 0;
1951         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1952         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1953
1954         if (!vnic->rss_table)
1955                 return 0;
1956
1957         if (BNXT_CHIP_THOR(bp))
1958                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1959
1960         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1961
1962         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1963         req.hash_mode_flags = vnic->hash_mode;
1964
1965         req.ring_grp_tbl_addr =
1966             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1967         req.hash_key_tbl_addr =
1968             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1969         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1970         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1971
1972         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1973
1974         HWRM_CHECK_RESULT();
1975         HWRM_UNLOCK();
1976
1977         return rc;
1978 }
1979
1980 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1981                         struct bnxt_vnic_info *vnic)
1982 {
1983         int rc = 0;
1984         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1985         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1986         uint16_t size;
1987
1988         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1989                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1990                 return rc;
1991         }
1992
1993         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1994
1995         req.flags = rte_cpu_to_le_32(
1996                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1997
1998         req.enables = rte_cpu_to_le_32(
1999                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2000
2001         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2002         size -= RTE_PKTMBUF_HEADROOM;
2003         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2004
2005         req.jumbo_thresh = rte_cpu_to_le_16(size);
2006         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2007
2008         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2009
2010         HWRM_CHECK_RESULT();
2011         HWRM_UNLOCK();
2012
2013         return rc;
2014 }
2015
2016 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2017                         struct bnxt_vnic_info *vnic, bool enable)
2018 {
2019         int rc = 0;
2020         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2021         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2022
2023         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2024                 if (enable)
2025                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2026                 return -ENOTSUP;
2027         }
2028
2029         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2030                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2031                 return 0;
2032         }
2033
2034         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2035
2036         if (enable) {
2037                 req.enables = rte_cpu_to_le_32(
2038                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2039                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2040                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2041                 req.flags = rte_cpu_to_le_32(
2042                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2043                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2044                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2045                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2046                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2047                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2048                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2049                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2050                 req.min_agg_len = rte_cpu_to_le_32(512);
2051         }
2052         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2053
2054         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2055
2056         HWRM_CHECK_RESULT();
2057         HWRM_UNLOCK();
2058
2059         return rc;
2060 }
2061
2062 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2063 {
2064         struct hwrm_func_cfg_input req = {0};
2065         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2066         int rc;
2067
2068         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2069         req.enables = rte_cpu_to_le_32(
2070                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2071         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2072         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2073
2074         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2075
2076         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2077         HWRM_CHECK_RESULT();
2078         HWRM_UNLOCK();
2079
2080         bp->pf.vf_info[vf].random_mac = false;
2081
2082         return rc;
2083 }
2084
2085 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2086                                   uint64_t *dropped)
2087 {
2088         int rc = 0;
2089         struct hwrm_func_qstats_input req = {.req_type = 0};
2090         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2091
2092         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2093
2094         req.fid = rte_cpu_to_le_16(fid);
2095
2096         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2097
2098         HWRM_CHECK_RESULT();
2099
2100         if (dropped)
2101                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2102
2103         HWRM_UNLOCK();
2104
2105         return rc;
2106 }
2107
2108 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2109                           struct rte_eth_stats *stats)
2110 {
2111         int rc = 0;
2112         struct hwrm_func_qstats_input req = {.req_type = 0};
2113         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2114
2115         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2116
2117         req.fid = rte_cpu_to_le_16(fid);
2118
2119         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2120
2121         HWRM_CHECK_RESULT();
2122
2123         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2124         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2125         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2126         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2127         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2128         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2129
2130         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2131         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2132         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2133         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2134         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2135         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2136
2137         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2138         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2139         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2140
2141         HWRM_UNLOCK();
2142
2143         return rc;
2144 }
2145
2146 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2147 {
2148         int rc = 0;
2149         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2150         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2151
2152         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2153
2154         req.fid = rte_cpu_to_le_16(fid);
2155
2156         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2157
2158         HWRM_CHECK_RESULT();
2159         HWRM_UNLOCK();
2160
2161         return rc;
2162 }
2163
2164 /*
2165  * HWRM utility functions
2166  */
2167
2168 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2169 {
2170         unsigned int i;
2171         int rc = 0;
2172
2173         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2174                 struct bnxt_tx_queue *txq;
2175                 struct bnxt_rx_queue *rxq;
2176                 struct bnxt_cp_ring_info *cpr;
2177
2178                 if (i >= bp->rx_cp_nr_rings) {
2179                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2180                         cpr = txq->cp_ring;
2181                 } else {
2182                         rxq = bp->rx_queues[i];
2183                         cpr = rxq->cp_ring;
2184                 }
2185
2186                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2187                 if (rc)
2188                         return rc;
2189         }
2190         return 0;
2191 }
2192
2193 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2194 {
2195         int rc;
2196         unsigned int i;
2197         struct bnxt_cp_ring_info *cpr;
2198
2199         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2200
2201                 if (i >= bp->rx_cp_nr_rings) {
2202                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2203                 } else {
2204                         cpr = bp->rx_queues[i]->cp_ring;
2205                         if (BNXT_HAS_RING_GRPS(bp))
2206                                 bp->grp_info[i].fw_stats_ctx = -1;
2207                 }
2208                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2209                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2210                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2211                         if (rc)
2212                                 return rc;
2213                 }
2214         }
2215         return 0;
2216 }
2217
2218 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2219 {
2220         unsigned int i;
2221         int rc = 0;
2222
2223         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2224                 struct bnxt_tx_queue *txq;
2225                 struct bnxt_rx_queue *rxq;
2226                 struct bnxt_cp_ring_info *cpr;
2227
2228                 if (i >= bp->rx_cp_nr_rings) {
2229                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2230                         cpr = txq->cp_ring;
2231                 } else {
2232                         rxq = bp->rx_queues[i];
2233                         cpr = rxq->cp_ring;
2234                 }
2235
2236                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2237
2238                 if (rc)
2239                         return rc;
2240         }
2241         return rc;
2242 }
2243
2244 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2245 {
2246         uint16_t idx;
2247         uint32_t rc = 0;
2248
2249         if (!BNXT_HAS_RING_GRPS(bp))
2250                 return 0;
2251
2252         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2253
2254                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2255                         continue;
2256
2257                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2258
2259                 if (rc)
2260                         return rc;
2261         }
2262         return rc;
2263 }
2264
2265 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2266 {
2267         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2268
2269         bnxt_hwrm_ring_free(bp, cp_ring,
2270                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2271         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2272         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2273                                      sizeof(*cpr->cp_desc_ring));
2274         cpr->cp_raw_cons = 0;
2275         cpr->valid = 0;
2276 }
2277
2278 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2279 {
2280         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2281
2282         bnxt_hwrm_ring_free(bp, cp_ring,
2283                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2284         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2285         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2286                         sizeof(*cpr->cp_desc_ring));
2287         cpr->cp_raw_cons = 0;
2288         cpr->valid = 0;
2289 }
2290
2291 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2292 {
2293         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2294         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2295         struct bnxt_ring *ring = rxr->rx_ring_struct;
2296         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2297
2298         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2299                 bnxt_hwrm_ring_free(bp, ring,
2300                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2301                 ring->fw_ring_id = INVALID_HW_RING_ID;
2302                 if (BNXT_HAS_RING_GRPS(bp))
2303                         bp->grp_info[queue_index].rx_fw_ring_id =
2304                                                         INVALID_HW_RING_ID;
2305                 memset(rxr->rx_desc_ring, 0,
2306                        rxr->rx_ring_struct->ring_size *
2307                        sizeof(*rxr->rx_desc_ring));
2308                 memset(rxr->rx_buf_ring, 0,
2309                        rxr->rx_ring_struct->ring_size *
2310                        sizeof(*rxr->rx_buf_ring));
2311                 rxr->rx_prod = 0;
2312         }
2313         ring = rxr->ag_ring_struct;
2314         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2315                 bnxt_hwrm_ring_free(bp, ring,
2316                                     BNXT_CHIP_THOR(bp) ?
2317                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2318                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2319                 ring->fw_ring_id = INVALID_HW_RING_ID;
2320                 memset(rxr->ag_buf_ring, 0,
2321                        rxr->ag_ring_struct->ring_size *
2322                        sizeof(*rxr->ag_buf_ring));
2323                 rxr->ag_prod = 0;
2324                 if (BNXT_HAS_RING_GRPS(bp))
2325                         bp->grp_info[queue_index].ag_fw_ring_id =
2326                                                         INVALID_HW_RING_ID;
2327         }
2328         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2329                 bnxt_free_cp_ring(bp, cpr);
2330                 if (rxq->nq_ring)
2331                         bnxt_free_nq_ring(bp, rxq->nq_ring);
2332         }
2333
2334         if (BNXT_HAS_RING_GRPS(bp))
2335                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2336 }
2337
2338 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2339 {
2340         unsigned int i;
2341
2342         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2343                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2344                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2345                 struct bnxt_ring *ring = txr->tx_ring_struct;
2346                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2347
2348                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2349                         bnxt_hwrm_ring_free(bp, ring,
2350                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2351                         ring->fw_ring_id = INVALID_HW_RING_ID;
2352                         memset(txr->tx_desc_ring, 0,
2353                                         txr->tx_ring_struct->ring_size *
2354                                         sizeof(*txr->tx_desc_ring));
2355                         memset(txr->tx_buf_ring, 0,
2356                                         txr->tx_ring_struct->ring_size *
2357                                         sizeof(*txr->tx_buf_ring));
2358                         txr->tx_prod = 0;
2359                         txr->tx_cons = 0;
2360                 }
2361                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2362                         bnxt_free_cp_ring(bp, cpr);
2363                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2364                         if (txq->nq_ring)
2365                                 bnxt_free_nq_ring(bp, txq->nq_ring);
2366                 }
2367         }
2368
2369         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2370                 bnxt_free_hwrm_rx_ring(bp, i);
2371
2372         return 0;
2373 }
2374
2375 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2376 {
2377         uint16_t i;
2378         uint32_t rc = 0;
2379
2380         if (!BNXT_HAS_RING_GRPS(bp))
2381                 return 0;
2382
2383         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2384                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2385                 if (rc)
2386                         return rc;
2387         }
2388         return rc;
2389 }
2390
2391 void bnxt_free_hwrm_resources(struct bnxt *bp)
2392 {
2393         /* Release memzone */
2394         rte_free(bp->hwrm_cmd_resp_addr);
2395         rte_free(bp->hwrm_short_cmd_req_addr);
2396         bp->hwrm_cmd_resp_addr = NULL;
2397         bp->hwrm_short_cmd_req_addr = NULL;
2398         bp->hwrm_cmd_resp_dma_addr = 0;
2399         bp->hwrm_short_cmd_req_dma_addr = 0;
2400 }
2401
2402 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2403 {
2404         struct rte_pci_device *pdev = bp->pdev;
2405         char type[RTE_MEMZONE_NAMESIZE];
2406
2407         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2408                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2409         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2410         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2411         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2412         if (bp->hwrm_cmd_resp_addr == NULL)
2413                 return -ENOMEM;
2414         bp->hwrm_cmd_resp_dma_addr =
2415                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2416         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2417                 PMD_DRV_LOG(ERR,
2418                         "unable to map response address to physical memory\n");
2419                 return -ENOMEM;
2420         }
2421         rte_spinlock_init(&bp->hwrm_lock);
2422
2423         return 0;
2424 }
2425
2426 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2427 {
2428         struct bnxt_filter_info *filter;
2429         int rc = 0;
2430
2431         STAILQ_FOREACH(filter, &vnic->filter, next) {
2432                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2433                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2434                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2435                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2436                 else
2437                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2438                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2439                 bnxt_free_filter(bp, filter);
2440                 //if (rc)
2441                         //break;
2442         }
2443         return rc;
2444 }
2445
2446 static int
2447 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2448 {
2449         struct bnxt_filter_info *filter;
2450         struct rte_flow *flow;
2451         int rc = 0;
2452
2453         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2454                 flow = STAILQ_FIRST(&vnic->flow_list);
2455                 filter = flow->filter;
2456                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2457                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2458                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2459                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2460                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2461                 else
2462                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2463
2464                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2465                 rte_free(flow);
2466                 //if (rc)
2467                         //break;
2468         }
2469         return rc;
2470 }
2471
2472 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2473 {
2474         struct bnxt_filter_info *filter;
2475         int rc = 0;
2476
2477         STAILQ_FOREACH(filter, &vnic->filter, next) {
2478                 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2479                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2480                                                      filter);
2481                 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2482                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2483                                                          filter);
2484                 } else {
2485                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2486                                                      filter);
2487                         if (!rc)
2488                                 filter->dflt = 1;
2489                 }
2490                 if (rc)
2491                         break;
2492         }
2493         return rc;
2494 }
2495
2496 void bnxt_free_tunnel_ports(struct bnxt *bp)
2497 {
2498         if (bp->vxlan_port_cnt)
2499                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2500                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2501         bp->vxlan_port = 0;
2502         if (bp->geneve_port_cnt)
2503                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2504                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2505         bp->geneve_port = 0;
2506 }
2507
2508 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2509 {
2510         int i;
2511
2512         if (bp->vnic_info == NULL)
2513                 return;
2514
2515         /*
2516          * Cleanup VNICs in reverse order, to make sure the L2 filter
2517          * from vnic0 is last to be cleaned up.
2518          */
2519         for (i = bp->max_vnics - 1; i >= 0; i--) {
2520                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2521
2522                 // If the VNIC ID is invalid we are not currently using the VNIC
2523                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2524                         continue;
2525
2526                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2527
2528                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2529
2530                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2531
2532                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2533
2534                 bnxt_hwrm_vnic_free(bp, vnic);
2535
2536                 rte_free(vnic->fw_grp_ids);
2537         }
2538         /* Ring resources */
2539         bnxt_free_all_hwrm_rings(bp);
2540         bnxt_free_all_hwrm_ring_grps(bp);
2541         bnxt_free_all_hwrm_stat_ctxs(bp);
2542         bnxt_free_tunnel_ports(bp);
2543 }
2544
2545 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2546 {
2547         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2548
2549         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2550                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2551
2552         switch (conf_link_speed) {
2553         case ETH_LINK_SPEED_10M_HD:
2554         case ETH_LINK_SPEED_100M_HD:
2555                 /* FALLTHROUGH */
2556                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2557         }
2558         return hw_link_duplex;
2559 }
2560
2561 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2562 {
2563         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2564 }
2565
2566 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2567 {
2568         uint16_t eth_link_speed = 0;
2569
2570         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2571                 return ETH_LINK_SPEED_AUTONEG;
2572
2573         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2574         case ETH_LINK_SPEED_100M:
2575         case ETH_LINK_SPEED_100M_HD:
2576                 /* FALLTHROUGH */
2577                 eth_link_speed =
2578                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2579                 break;
2580         case ETH_LINK_SPEED_1G:
2581                 eth_link_speed =
2582                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2583                 break;
2584         case ETH_LINK_SPEED_2_5G:
2585                 eth_link_speed =
2586                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2587                 break;
2588         case ETH_LINK_SPEED_10G:
2589                 eth_link_speed =
2590                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2591                 break;
2592         case ETH_LINK_SPEED_20G:
2593                 eth_link_speed =
2594                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2595                 break;
2596         case ETH_LINK_SPEED_25G:
2597                 eth_link_speed =
2598                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2599                 break;
2600         case ETH_LINK_SPEED_40G:
2601                 eth_link_speed =
2602                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2603                 break;
2604         case ETH_LINK_SPEED_50G:
2605                 eth_link_speed =
2606                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2607                 break;
2608         case ETH_LINK_SPEED_100G:
2609                 eth_link_speed =
2610                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2611                 break;
2612         default:
2613                 PMD_DRV_LOG(ERR,
2614                         "Unsupported link speed %d; default to AUTO\n",
2615                         conf_link_speed);
2616                 break;
2617         }
2618         return eth_link_speed;
2619 }
2620
2621 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2622                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2623                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2624                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2625
2626 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2627 {
2628         uint32_t one_speed;
2629
2630         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2631                 return 0;
2632
2633         if (link_speed & ETH_LINK_SPEED_FIXED) {
2634                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2635
2636                 if (one_speed & (one_speed - 1)) {
2637                         PMD_DRV_LOG(ERR,
2638                                 "Invalid advertised speeds (%u) for port %u\n",
2639                                 link_speed, port_id);
2640                         return -EINVAL;
2641                 }
2642                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2643                         PMD_DRV_LOG(ERR,
2644                                 "Unsupported advertised speed (%u) for port %u\n",
2645                                 link_speed, port_id);
2646                         return -EINVAL;
2647                 }
2648         } else {
2649                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2650                         PMD_DRV_LOG(ERR,
2651                                 "Unsupported advertised speeds (%u) for port %u\n",
2652                                 link_speed, port_id);
2653                         return -EINVAL;
2654                 }
2655         }
2656         return 0;
2657 }
2658
2659 static uint16_t
2660 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2661 {
2662         uint16_t ret = 0;
2663
2664         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2665                 if (bp->link_info.support_speeds)
2666                         return bp->link_info.support_speeds;
2667                 link_speed = BNXT_SUPPORTED_SPEEDS;
2668         }
2669
2670         if (link_speed & ETH_LINK_SPEED_100M)
2671                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2672         if (link_speed & ETH_LINK_SPEED_100M_HD)
2673                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2674         if (link_speed & ETH_LINK_SPEED_1G)
2675                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2676         if (link_speed & ETH_LINK_SPEED_2_5G)
2677                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2678         if (link_speed & ETH_LINK_SPEED_10G)
2679                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2680         if (link_speed & ETH_LINK_SPEED_20G)
2681                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2682         if (link_speed & ETH_LINK_SPEED_25G)
2683                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2684         if (link_speed & ETH_LINK_SPEED_40G)
2685                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2686         if (link_speed & ETH_LINK_SPEED_50G)
2687                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2688         if (link_speed & ETH_LINK_SPEED_100G)
2689                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2690         return ret;
2691 }
2692
2693 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2694 {
2695         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2696
2697         switch (hw_link_speed) {
2698         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2699                 eth_link_speed = ETH_SPEED_NUM_100M;
2700                 break;
2701         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2702                 eth_link_speed = ETH_SPEED_NUM_1G;
2703                 break;
2704         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2705                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2706                 break;
2707         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2708                 eth_link_speed = ETH_SPEED_NUM_10G;
2709                 break;
2710         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2711                 eth_link_speed = ETH_SPEED_NUM_20G;
2712                 break;
2713         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2714                 eth_link_speed = ETH_SPEED_NUM_25G;
2715                 break;
2716         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2717                 eth_link_speed = ETH_SPEED_NUM_40G;
2718                 break;
2719         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2720                 eth_link_speed = ETH_SPEED_NUM_50G;
2721                 break;
2722         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2723                 eth_link_speed = ETH_SPEED_NUM_100G;
2724                 break;
2725         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2726         default:
2727                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2728                         hw_link_speed);
2729                 break;
2730         }
2731         return eth_link_speed;
2732 }
2733
2734 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2735 {
2736         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2737
2738         switch (hw_link_duplex) {
2739         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2740         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2741                 /* FALLTHROUGH */
2742                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2743                 break;
2744         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2745                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2746                 break;
2747         default:
2748                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2749                         hw_link_duplex);
2750                 break;
2751         }
2752         return eth_link_duplex;
2753 }
2754
2755 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2756 {
2757         int rc = 0;
2758         struct bnxt_link_info *link_info = &bp->link_info;
2759
2760         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2761         if (rc) {
2762                 PMD_DRV_LOG(ERR,
2763                         "Get link config failed with rc %d\n", rc);
2764                 goto exit;
2765         }
2766         if (link_info->link_speed)
2767                 link->link_speed =
2768                         bnxt_parse_hw_link_speed(link_info->link_speed);
2769         else
2770                 link->link_speed = ETH_SPEED_NUM_NONE;
2771         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2772         link->link_status = link_info->link_up;
2773         link->link_autoneg = link_info->auto_mode ==
2774                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2775                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2776 exit:
2777         return rc;
2778 }
2779
2780 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2781 {
2782         int rc = 0;
2783         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2784         struct bnxt_link_info link_req;
2785         uint16_t speed, autoneg;
2786
2787         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2788                 return 0;
2789
2790         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2791                         bp->eth_dev->data->port_id);
2792         if (rc)
2793                 goto error;
2794
2795         memset(&link_req, 0, sizeof(link_req));
2796         link_req.link_up = link_up;
2797         if (!link_up)
2798                 goto port_phy_cfg;
2799
2800         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2801         if (BNXT_CHIP_THOR(bp) &&
2802             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2803                 /* 40G is not supported as part of media auto detect.
2804                  * The speed should be forced and autoneg disabled
2805                  * to configure 40G speed.
2806                  */
2807                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2808                 autoneg = 0;
2809         }
2810
2811         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2812         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2813         /* Autoneg can be done only when the FW allows.
2814          * When user configures fixed speed of 40G and later changes to
2815          * any other speed, auto_link_speed/force_link_speed is still set
2816          * to 40G until link comes up at new speed.
2817          */
2818         if (autoneg == 1 &&
2819             !(!BNXT_CHIP_THOR(bp) &&
2820               (bp->link_info.auto_link_speed ||
2821                bp->link_info.force_link_speed))) {
2822                 link_req.phy_flags |=
2823                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2824                 link_req.auto_link_speed_mask =
2825                         bnxt_parse_eth_link_speed_mask(bp,
2826                                                        dev_conf->link_speeds);
2827         } else {
2828                 if (bp->link_info.phy_type ==
2829                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2830                     bp->link_info.phy_type ==
2831                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2832                     bp->link_info.media_type ==
2833                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2834                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2835                         return -EINVAL;
2836                 }
2837
2838                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2839                 /* If user wants a particular speed try that first. */
2840                 if (speed)
2841                         link_req.link_speed = speed;
2842                 else if (bp->link_info.force_link_speed)
2843                         link_req.link_speed = bp->link_info.force_link_speed;
2844                 else
2845                         link_req.link_speed = bp->link_info.auto_link_speed;
2846         }
2847         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2848         link_req.auto_pause = bp->link_info.auto_pause;
2849         link_req.force_pause = bp->link_info.force_pause;
2850
2851 port_phy_cfg:
2852         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2853         if (rc) {
2854                 PMD_DRV_LOG(ERR,
2855                         "Set link config failed with rc %d\n", rc);
2856         }
2857
2858 error:
2859         return rc;
2860 }
2861
2862 /* JIRA 22088 */
2863 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2864 {
2865         struct hwrm_func_qcfg_input req = {0};
2866         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2867         uint16_t flags;
2868         int rc = 0;
2869
2870         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2871         req.fid = rte_cpu_to_le_16(0xffff);
2872
2873         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2874
2875         HWRM_CHECK_RESULT();
2876
2877         /* Hard Coded.. 0xfff VLAN ID mask */
2878         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2879         flags = rte_le_to_cpu_16(resp->flags);
2880         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2881                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2882
2883         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2884                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2885                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2886         } else if (BNXT_VF(bp) &&
2887                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2888                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2889                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2890         }
2891
2892         if (mtu)
2893                 *mtu = resp->mtu;
2894
2895         switch (resp->port_partition_type) {
2896         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2897         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2898         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2899                 /* FALLTHROUGH */
2900                 bp->port_partition_type = resp->port_partition_type;
2901                 break;
2902         default:
2903                 bp->port_partition_type = 0;
2904                 break;
2905         }
2906
2907         HWRM_UNLOCK();
2908
2909         return rc;
2910 }
2911
2912 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2913                                    struct hwrm_func_qcaps_output *qcaps)
2914 {
2915         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2916         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2917                sizeof(qcaps->mac_address));
2918         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2919         qcaps->max_rx_rings = fcfg->num_rx_rings;
2920         qcaps->max_tx_rings = fcfg->num_tx_rings;
2921         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2922         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2923         qcaps->max_vfs = 0;
2924         qcaps->first_vf_id = 0;
2925         qcaps->max_vnics = fcfg->num_vnics;
2926         qcaps->max_decap_records = 0;
2927         qcaps->max_encap_records = 0;
2928         qcaps->max_tx_wm_flows = 0;
2929         qcaps->max_tx_em_flows = 0;
2930         qcaps->max_rx_wm_flows = 0;
2931         qcaps->max_rx_em_flows = 0;
2932         qcaps->max_flow_id = 0;
2933         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2934         qcaps->max_sp_tx_rings = 0;
2935         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2936 }
2937
2938 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2939 {
2940         struct hwrm_func_cfg_input req = {0};
2941         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2942         uint32_t enables;
2943         int rc;
2944
2945         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2946                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2947                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2948                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2949                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2950                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2951                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2952                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2953                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2954
2955         if (BNXT_HAS_RING_GRPS(bp)) {
2956                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2957                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2958         } else if (BNXT_HAS_NQ(bp)) {
2959                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2960                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2961         }
2962
2963         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2964         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2965         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2966                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2967                                    BNXT_NUM_VLANS);
2968         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2969         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2970         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2971         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2972         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2973         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2974         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2975         req.fid = rte_cpu_to_le_16(0xffff);
2976         req.enables = rte_cpu_to_le_32(enables);
2977
2978         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2979
2980         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2981
2982         HWRM_CHECK_RESULT();
2983         HWRM_UNLOCK();
2984
2985         return rc;
2986 }
2987
2988 static void populate_vf_func_cfg_req(struct bnxt *bp,
2989                                      struct hwrm_func_cfg_input *req,
2990                                      int num_vfs)
2991 {
2992         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2993                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2994                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2995                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2996                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2997                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2998                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2999                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3000                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3001                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3002
3003         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3004                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3005                                     BNXT_NUM_VLANS);
3006         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3007                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3008                                     BNXT_NUM_VLANS);
3009         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3010                                                 (num_vfs + 1));
3011         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3012         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3013                                                (num_vfs + 1));
3014         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3015         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3016         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3017         /* TODO: For now, do not support VMDq/RFS on VFs. */
3018         req->num_vnics = rte_cpu_to_le_16(1);
3019         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3020                                                  (num_vfs + 1));
3021 }
3022
3023 static void add_random_mac_if_needed(struct bnxt *bp,
3024                                      struct hwrm_func_cfg_input *cfg_req,
3025                                      int vf)
3026 {
3027         struct rte_ether_addr mac;
3028
3029         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3030                 return;
3031
3032         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3033                 cfg_req->enables |=
3034                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3035                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3036                 bp->pf.vf_info[vf].random_mac = true;
3037         } else {
3038                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3039                         RTE_ETHER_ADDR_LEN);
3040         }
3041 }
3042
3043 static void reserve_resources_from_vf(struct bnxt *bp,
3044                                       struct hwrm_func_cfg_input *cfg_req,
3045                                       int vf)
3046 {
3047         struct hwrm_func_qcaps_input req = {0};
3048         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3049         int rc;
3050
3051         /* Get the actual allocated values now */
3052         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3053         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3054         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3055
3056         if (rc) {
3057                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3058                 copy_func_cfg_to_qcaps(cfg_req, resp);
3059         } else if (resp->error_code) {
3060                 rc = rte_le_to_cpu_16(resp->error_code);
3061                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3062                 copy_func_cfg_to_qcaps(cfg_req, resp);
3063         }
3064
3065         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3066         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3067         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3068         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3069         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3070         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3071         /*
3072          * TODO: While not supporting VMDq with VFs, max_vnics is always
3073          * forced to 1 in this case
3074          */
3075         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3076         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3077
3078         HWRM_UNLOCK();
3079 }
3080
3081 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3082 {
3083         struct hwrm_func_qcfg_input req = {0};
3084         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3085         int rc;
3086
3087         /* Check for zero MAC address */
3088         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3089         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3090         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3091         HWRM_CHECK_RESULT();
3092         rc = rte_le_to_cpu_16(resp->vlan);
3093
3094         HWRM_UNLOCK();
3095
3096         return rc;
3097 }
3098
3099 static int update_pf_resource_max(struct bnxt *bp)
3100 {
3101         struct hwrm_func_qcfg_input req = {0};
3102         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3103         int rc;
3104
3105         /* And copy the allocated numbers into the pf struct */
3106         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3107         req.fid = rte_cpu_to_le_16(0xffff);
3108         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3109         HWRM_CHECK_RESULT();
3110
3111         /* Only TX ring value reflects actual allocation? TODO */
3112         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3113         bp->pf.evb_mode = resp->evb_mode;
3114
3115         HWRM_UNLOCK();
3116
3117         return rc;
3118 }
3119
3120 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3121 {
3122         int rc;
3123
3124         if (!BNXT_PF(bp)) {
3125                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3126                 return -EINVAL;
3127         }
3128
3129         rc = bnxt_hwrm_func_qcaps(bp);
3130         if (rc)
3131                 return rc;
3132
3133         bp->pf.func_cfg_flags &=
3134                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3135                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3136         bp->pf.func_cfg_flags |=
3137                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3138         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3139         rc = __bnxt_hwrm_func_qcaps(bp);
3140         return rc;
3141 }
3142
3143 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3144 {
3145         struct hwrm_func_cfg_input req = {0};
3146         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3147         int i;
3148         size_t sz;
3149         int rc = 0;
3150         size_t req_buf_sz;
3151
3152         if (!BNXT_PF(bp)) {
3153                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3154                 return -EINVAL;
3155         }
3156
3157         rc = bnxt_hwrm_func_qcaps(bp);
3158
3159         if (rc)
3160                 return rc;
3161
3162         bp->pf.active_vfs = num_vfs;
3163
3164         /*
3165          * First, configure the PF to only use one TX ring.  This ensures that
3166          * there are enough rings for all VFs.
3167          *
3168          * If we don't do this, when we call func_alloc() later, we will lock
3169          * extra rings to the PF that won't be available during func_cfg() of
3170          * the VFs.
3171          *
3172          * This has been fixed with firmware versions above 20.6.54
3173          */
3174         bp->pf.func_cfg_flags &=
3175                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3176                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3177         bp->pf.func_cfg_flags |=
3178                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3179         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3180         if (rc)
3181                 return rc;
3182
3183         /*
3184          * Now, create and register a buffer to hold forwarded VF requests
3185          */
3186         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3187         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3188                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3189         if (bp->pf.vf_req_buf == NULL) {
3190                 rc = -ENOMEM;
3191                 goto error_free;
3192         }
3193         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3194                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3195         for (i = 0; i < num_vfs; i++)
3196                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3197                                         (i * HWRM_MAX_REQ_LEN);
3198
3199         rc = bnxt_hwrm_func_buf_rgtr(bp);
3200         if (rc)
3201                 goto error_free;
3202
3203         populate_vf_func_cfg_req(bp, &req, num_vfs);
3204
3205         bp->pf.active_vfs = 0;
3206         for (i = 0; i < num_vfs; i++) {
3207                 add_random_mac_if_needed(bp, &req, i);
3208
3209                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3210                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3211                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3212                 rc = bnxt_hwrm_send_message(bp,
3213                                             &req,
3214                                             sizeof(req),
3215                                             BNXT_USE_CHIMP_MB);
3216
3217                 /* Clear enable flag for next pass */
3218                 req.enables &= ~rte_cpu_to_le_32(
3219                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3220
3221                 if (rc || resp->error_code) {
3222                         PMD_DRV_LOG(ERR,
3223                                 "Failed to initizlie VF %d\n", i);
3224                         PMD_DRV_LOG(ERR,
3225                                 "Not all VFs available. (%d, %d)\n",
3226                                 rc, resp->error_code);
3227                         HWRM_UNLOCK();
3228                         break;
3229                 }
3230
3231                 HWRM_UNLOCK();
3232
3233                 reserve_resources_from_vf(bp, &req, i);
3234                 bp->pf.active_vfs++;
3235                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3236         }
3237
3238         /*
3239          * Now configure the PF to use "the rest" of the resources
3240          * We're using STD_TX_RING_MODE here though which will limit the TX
3241          * rings.  This will allow QoS to function properly.  Not setting this
3242          * will cause PF rings to break bandwidth settings.
3243          */
3244         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3245         if (rc)
3246                 goto error_free;
3247
3248         rc = update_pf_resource_max(bp);
3249         if (rc)
3250                 goto error_free;
3251
3252         return rc;
3253
3254 error_free:
3255         bnxt_hwrm_func_buf_unrgtr(bp);
3256         return rc;
3257 }
3258
3259 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3260 {
3261         struct hwrm_func_cfg_input req = {0};
3262         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3263         int rc;
3264
3265         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3266
3267         req.fid = rte_cpu_to_le_16(0xffff);
3268         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3269         req.evb_mode = bp->pf.evb_mode;
3270
3271         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3272         HWRM_CHECK_RESULT();
3273         HWRM_UNLOCK();
3274
3275         return rc;
3276 }
3277
3278 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3279                                 uint8_t tunnel_type)
3280 {
3281         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3282         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3283         int rc = 0;
3284
3285         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3286         req.tunnel_type = tunnel_type;
3287         req.tunnel_dst_port_val = port;
3288         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3289         HWRM_CHECK_RESULT();
3290
3291         switch (tunnel_type) {
3292         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3293                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3294                 bp->vxlan_port = port;
3295                 break;
3296         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3297                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3298                 bp->geneve_port = port;
3299                 break;
3300         default:
3301                 break;
3302         }
3303
3304         HWRM_UNLOCK();
3305
3306         return rc;
3307 }
3308
3309 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3310                                 uint8_t tunnel_type)
3311 {
3312         struct hwrm_tunnel_dst_port_free_input req = {0};
3313         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3314         int rc = 0;
3315
3316         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3317
3318         req.tunnel_type = tunnel_type;
3319         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3320         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3321
3322         HWRM_CHECK_RESULT();
3323         HWRM_UNLOCK();
3324
3325         return rc;
3326 }
3327
3328 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3329                                         uint32_t flags)
3330 {
3331         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3332         struct hwrm_func_cfg_input req = {0};
3333         int rc;
3334
3335         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3336
3337         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3338         req.flags = rte_cpu_to_le_32(flags);
3339         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3340
3341         HWRM_CHECK_RESULT();
3342         HWRM_UNLOCK();
3343
3344         return rc;
3345 }
3346
3347 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3348 {
3349         uint32_t *flag = flagp;
3350
3351         vnic->flags = *flag;
3352 }
3353
3354 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3355 {
3356         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3357 }
3358
3359 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3360 {
3361         int rc = 0;
3362         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3363         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3364
3365         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3366
3367         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3368         req.req_buf_page_size = rte_cpu_to_le_16(
3369                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3370         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3371         req.req_buf_page_addr0 =
3372                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3373         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3374                 PMD_DRV_LOG(ERR,
3375                         "unable to map buffer address to physical memory\n");
3376                 return -ENOMEM;
3377         }
3378
3379         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3380
3381         HWRM_CHECK_RESULT();
3382         HWRM_UNLOCK();
3383
3384         return rc;
3385 }
3386
3387 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3388 {
3389         int rc = 0;
3390         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3391         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3392
3393         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3394                 return 0;
3395
3396         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3397
3398         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3399
3400         HWRM_CHECK_RESULT();
3401         HWRM_UNLOCK();
3402
3403         return rc;
3404 }
3405
3406 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3407 {
3408         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3409         struct hwrm_func_cfg_input req = {0};
3410         int rc;
3411
3412         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3413
3414         req.fid = rte_cpu_to_le_16(0xffff);
3415         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3416         req.enables = rte_cpu_to_le_32(
3417                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3418         req.async_event_cr = rte_cpu_to_le_16(
3419                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3420         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3421
3422         HWRM_CHECK_RESULT();
3423         HWRM_UNLOCK();
3424
3425         return rc;
3426 }
3427
3428 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3429 {
3430         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3431         struct hwrm_func_vf_cfg_input req = {0};
3432         int rc;
3433
3434         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3435
3436         req.enables = rte_cpu_to_le_32(
3437                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3438         req.async_event_cr = rte_cpu_to_le_16(
3439                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3441
3442         HWRM_CHECK_RESULT();
3443         HWRM_UNLOCK();
3444
3445         return rc;
3446 }
3447
3448 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3449 {
3450         struct hwrm_func_cfg_input req = {0};
3451         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3452         uint16_t dflt_vlan, fid;
3453         uint32_t func_cfg_flags;
3454         int rc = 0;
3455
3456         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3457
3458         if (is_vf) {
3459                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3460                 fid = bp->pf.vf_info[vf].fid;
3461                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3462         } else {
3463                 fid = rte_cpu_to_le_16(0xffff);
3464                 func_cfg_flags = bp->pf.func_cfg_flags;
3465                 dflt_vlan = bp->vlan;
3466         }
3467
3468         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3469         req.fid = rte_cpu_to_le_16(fid);
3470         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3471         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3472
3473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3474
3475         HWRM_CHECK_RESULT();
3476         HWRM_UNLOCK();
3477
3478         return rc;
3479 }
3480
3481 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3482                         uint16_t max_bw, uint16_t enables)
3483 {
3484         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3485         struct hwrm_func_cfg_input req = {0};
3486         int rc;
3487
3488         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3489
3490         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3491         req.enables |= rte_cpu_to_le_32(enables);
3492         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3493         req.max_bw = rte_cpu_to_le_32(max_bw);
3494         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3495
3496         HWRM_CHECK_RESULT();
3497         HWRM_UNLOCK();
3498
3499         return rc;
3500 }
3501
3502 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3503 {
3504         struct hwrm_func_cfg_input req = {0};
3505         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3506         int rc = 0;
3507
3508         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3509
3510         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3511         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3512         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3513         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3514
3515         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3516
3517         HWRM_CHECK_RESULT();
3518         HWRM_UNLOCK();
3519
3520         return rc;
3521 }
3522
3523 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3524 {
3525         int rc;
3526
3527         if (BNXT_PF(bp))
3528                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3529         else
3530                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3531
3532         return rc;
3533 }
3534
3535 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3536                               void *encaped, size_t ec_size)
3537 {
3538         int rc = 0;
3539         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3540         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3541
3542         if (ec_size > sizeof(req.encap_request))
3543                 return -1;
3544
3545         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3546
3547         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3548         memcpy(req.encap_request, encaped, ec_size);
3549
3550         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3551
3552         HWRM_CHECK_RESULT();
3553         HWRM_UNLOCK();
3554
3555         return rc;
3556 }
3557
3558 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3559                                        struct rte_ether_addr *mac)
3560 {
3561         struct hwrm_func_qcfg_input req = {0};
3562         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3563         int rc;
3564
3565         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3566
3567         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3568         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3569
3570         HWRM_CHECK_RESULT();
3571
3572         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3573
3574         HWRM_UNLOCK();
3575
3576         return rc;
3577 }
3578
3579 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3580                             void *encaped, size_t ec_size)
3581 {
3582         int rc = 0;
3583         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3584         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3585
3586         if (ec_size > sizeof(req.encap_request))
3587                 return -1;
3588
3589         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3590
3591         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3592         memcpy(req.encap_request, encaped, ec_size);
3593
3594         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3595
3596         HWRM_CHECK_RESULT();
3597         HWRM_UNLOCK();
3598
3599         return rc;
3600 }
3601
3602 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3603                          struct rte_eth_stats *stats, uint8_t rx)
3604 {
3605         int rc = 0;
3606         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3607         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3608
3609         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3610
3611         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3612
3613         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3614
3615         HWRM_CHECK_RESULT();
3616
3617         if (rx) {
3618                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3619                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3620                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3621                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3622                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3623                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3624                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3625                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3626         } else {
3627                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3628                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3629                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3630                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3631                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3632                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3633         }
3634
3635
3636         HWRM_UNLOCK();
3637
3638         return rc;
3639 }
3640
3641 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3642 {
3643         struct hwrm_port_qstats_input req = {0};
3644         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3645         struct bnxt_pf_info *pf = &bp->pf;
3646         int rc;
3647
3648         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3649
3650         req.port_id = rte_cpu_to_le_16(pf->port_id);
3651         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3652         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3653         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3654
3655         HWRM_CHECK_RESULT();
3656         HWRM_UNLOCK();
3657
3658         return rc;
3659 }
3660
3661 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3662 {
3663         struct hwrm_port_clr_stats_input req = {0};
3664         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3665         struct bnxt_pf_info *pf = &bp->pf;
3666         int rc;
3667
3668         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3669         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3670             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3671                 return 0;
3672
3673         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3674
3675         req.port_id = rte_cpu_to_le_16(pf->port_id);
3676         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3677
3678         HWRM_CHECK_RESULT();
3679         HWRM_UNLOCK();
3680
3681         return rc;
3682 }
3683
3684 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3685 {
3686         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3687         struct hwrm_port_led_qcaps_input req = {0};
3688         int rc;
3689
3690         if (BNXT_VF(bp))
3691                 return 0;
3692
3693         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3694         req.port_id = bp->pf.port_id;
3695         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3696
3697         HWRM_CHECK_RESULT();
3698
3699         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3700                 unsigned int i;
3701
3702                 bp->num_leds = resp->num_leds;
3703                 memcpy(bp->leds, &resp->led0_id,
3704                         sizeof(bp->leds[0]) * bp->num_leds);
3705                 for (i = 0; i < bp->num_leds; i++) {
3706                         struct bnxt_led_info *led = &bp->leds[i];
3707
3708                         uint16_t caps = led->led_state_caps;
3709
3710                         if (!led->led_group_id ||
3711                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3712                                 bp->num_leds = 0;
3713                                 break;
3714                         }
3715                 }
3716         }
3717
3718         HWRM_UNLOCK();
3719
3720         return rc;
3721 }
3722
3723 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3724 {
3725         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3726         struct hwrm_port_led_cfg_input req = {0};
3727         struct bnxt_led_cfg *led_cfg;
3728         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3729         uint16_t duration = 0;
3730         int rc, i;
3731
3732         if (!bp->num_leds || BNXT_VF(bp))
3733                 return -EOPNOTSUPP;
3734
3735         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3736
3737         if (led_on) {
3738                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3739                 duration = rte_cpu_to_le_16(500);
3740         }
3741         req.port_id = bp->pf.port_id;
3742         req.num_leds = bp->num_leds;
3743         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3744         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3745                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3746                 led_cfg->led_id = bp->leds[i].led_id;
3747                 led_cfg->led_state = led_state;
3748                 led_cfg->led_blink_on = duration;
3749                 led_cfg->led_blink_off = duration;
3750                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3751         }
3752
3753         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3754
3755         HWRM_CHECK_RESULT();
3756         HWRM_UNLOCK();
3757
3758         return rc;
3759 }
3760
3761 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3762                                uint32_t *length)
3763 {
3764         int rc;
3765         struct hwrm_nvm_get_dir_info_input req = {0};
3766         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3767
3768         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3769
3770         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3771
3772         HWRM_CHECK_RESULT();
3773
3774         *entries = rte_le_to_cpu_32(resp->entries);
3775         *length = rte_le_to_cpu_32(resp->entry_length);
3776
3777         HWRM_UNLOCK();
3778         return rc;
3779 }
3780
3781 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3782 {
3783         int rc;
3784         uint32_t dir_entries;
3785         uint32_t entry_length;
3786         uint8_t *buf;
3787         size_t buflen;
3788         rte_iova_t dma_handle;
3789         struct hwrm_nvm_get_dir_entries_input req = {0};
3790         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3791
3792         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3793         if (rc != 0)
3794                 return rc;
3795
3796         *data++ = dir_entries;
3797         *data++ = entry_length;
3798         len -= 2;
3799         memset(data, 0xff, len);
3800
3801         buflen = dir_entries * entry_length;
3802         buf = rte_malloc("nvm_dir", buflen, 0);
3803         rte_mem_lock_page(buf);
3804         if (buf == NULL)
3805                 return -ENOMEM;
3806         dma_handle = rte_mem_virt2iova(buf);
3807         if (dma_handle == RTE_BAD_IOVA) {
3808                 PMD_DRV_LOG(ERR,
3809                         "unable to map response address to physical memory\n");
3810                 return -ENOMEM;
3811         }
3812         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3813         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3814         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3815
3816         if (rc == 0)
3817                 memcpy(data, buf, len > buflen ? buflen : len);
3818
3819         rte_free(buf);
3820         HWRM_CHECK_RESULT();
3821         HWRM_UNLOCK();
3822
3823         return rc;
3824 }
3825
3826 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3827                              uint32_t offset, uint32_t length,
3828                              uint8_t *data)
3829 {
3830         int rc;
3831         uint8_t *buf;
3832         rte_iova_t dma_handle;
3833         struct hwrm_nvm_read_input req = {0};
3834         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3835
3836         buf = rte_malloc("nvm_item", length, 0);
3837         rte_mem_lock_page(buf);
3838         if (!buf)
3839                 return -ENOMEM;
3840
3841         dma_handle = rte_mem_virt2iova(buf);
3842         if (dma_handle == RTE_BAD_IOVA) {
3843                 PMD_DRV_LOG(ERR,
3844                         "unable to map response address to physical memory\n");
3845                 return -ENOMEM;
3846         }
3847         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3848         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3849         req.dir_idx = rte_cpu_to_le_16(index);
3850         req.offset = rte_cpu_to_le_32(offset);
3851         req.len = rte_cpu_to_le_32(length);
3852         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3853         if (rc == 0)
3854                 memcpy(data, buf, length);
3855
3856         rte_free(buf);
3857         HWRM_CHECK_RESULT();
3858         HWRM_UNLOCK();
3859
3860         return rc;
3861 }
3862
3863 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3864 {
3865         int rc;
3866         struct hwrm_nvm_erase_dir_entry_input req = {0};
3867         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3868
3869         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3870         req.dir_idx = rte_cpu_to_le_16(index);
3871         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3872         HWRM_CHECK_RESULT();
3873         HWRM_UNLOCK();
3874
3875         return rc;
3876 }
3877
3878
3879 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3880                           uint16_t dir_ordinal, uint16_t dir_ext,
3881                           uint16_t dir_attr, const uint8_t *data,
3882                           size_t data_len)
3883 {
3884         int rc;
3885         struct hwrm_nvm_write_input req = {0};
3886         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3887         rte_iova_t dma_handle;
3888         uint8_t *buf;
3889
3890         buf = rte_malloc("nvm_write", data_len, 0);
3891         rte_mem_lock_page(buf);
3892         if (!buf)
3893                 return -ENOMEM;
3894
3895         dma_handle = rte_mem_virt2iova(buf);
3896         if (dma_handle == RTE_BAD_IOVA) {
3897                 PMD_DRV_LOG(ERR,
3898                         "unable to map response address to physical memory\n");
3899                 return -ENOMEM;
3900         }
3901         memcpy(buf, data, data_len);
3902
3903         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3904
3905         req.dir_type = rte_cpu_to_le_16(dir_type);
3906         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3907         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3908         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3909         req.dir_data_length = rte_cpu_to_le_32(data_len);
3910         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3911
3912         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3913
3914         rte_free(buf);
3915         HWRM_CHECK_RESULT();
3916         HWRM_UNLOCK();
3917
3918         return rc;
3919 }
3920
3921 static void
3922 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3923 {
3924         uint32_t *count = cbdata;
3925
3926         *count = *count + 1;
3927 }
3928
3929 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3930                                      struct bnxt_vnic_info *vnic __rte_unused)
3931 {
3932         return 0;
3933 }
3934
3935 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3936 {
3937         uint32_t count = 0;
3938
3939         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3940             &count, bnxt_vnic_count_hwrm_stub);
3941
3942         return count;
3943 }
3944
3945 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3946                                         uint16_t *vnic_ids)
3947 {
3948         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3949         struct hwrm_func_vf_vnic_ids_query_output *resp =
3950                                                 bp->hwrm_cmd_resp_addr;
3951         int rc;
3952
3953         /* First query all VNIC ids */
3954         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3955
3956         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3957         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3958         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3959
3960         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3961                 HWRM_UNLOCK();
3962                 PMD_DRV_LOG(ERR,
3963                 "unable to map VNIC ID table address to physical memory\n");
3964                 return -ENOMEM;
3965         }
3966         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3967         HWRM_CHECK_RESULT();
3968         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3969
3970         HWRM_UNLOCK();
3971
3972         return rc;
3973 }
3974
3975 /*
3976  * This function queries the VNIC IDs  for a specified VF. It then calls
3977  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3978  * Then it calls the hwrm_cb function to program this new vnic configuration.
3979  */
3980 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3981         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3982         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3983 {
3984         struct bnxt_vnic_info vnic;
3985         int rc = 0;
3986         int i, num_vnic_ids;
3987         uint16_t *vnic_ids;
3988         size_t vnic_id_sz;
3989         size_t sz;
3990
3991         /* First query all VNIC ids */
3992         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3993         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3994                         RTE_CACHE_LINE_SIZE);
3995         if (vnic_ids == NULL)
3996                 return -ENOMEM;
3997
3998         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3999                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4000
4001         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4002
4003         if (num_vnic_ids < 0)
4004                 return num_vnic_ids;
4005
4006         /* Retrieve VNIC, update bd_stall then update */
4007
4008         for (i = 0; i < num_vnic_ids; i++) {
4009                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4010                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4011                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4012                 if (rc)
4013                         break;
4014                 if (vnic.mru <= 4)      /* Indicates unallocated */
4015                         continue;
4016
4017                 vnic_cb(&vnic, cbdata);
4018
4019                 rc = hwrm_cb(bp, &vnic);
4020                 if (rc)
4021                         break;
4022         }
4023
4024         rte_free(vnic_ids);
4025
4026         return rc;
4027 }
4028
4029 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4030                                               bool on)
4031 {
4032         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4033         struct hwrm_func_cfg_input req = {0};
4034         int rc;
4035
4036         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4037
4038         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4039         req.enables |= rte_cpu_to_le_32(
4040                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4041         req.vlan_antispoof_mode = on ?
4042                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4043                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4044         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4045
4046         HWRM_CHECK_RESULT();
4047         HWRM_UNLOCK();
4048
4049         return rc;
4050 }
4051
4052 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4053 {
4054         struct bnxt_vnic_info vnic;
4055         uint16_t *vnic_ids;
4056         size_t vnic_id_sz;
4057         int num_vnic_ids, i;
4058         size_t sz;
4059         int rc;
4060
4061         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4062         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4063                         RTE_CACHE_LINE_SIZE);
4064         if (vnic_ids == NULL)
4065                 return -ENOMEM;
4066
4067         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4068                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4069
4070         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4071         if (rc <= 0)
4072                 goto exit;
4073         num_vnic_ids = rc;
4074
4075         /*
4076          * Loop through to find the default VNIC ID.
4077          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4078          * by sending the hwrm_func_qcfg command to the firmware.
4079          */
4080         for (i = 0; i < num_vnic_ids; i++) {
4081                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4082                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4083                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4084                                         bp->pf.first_vf_id + vf);
4085                 if (rc)
4086                         goto exit;
4087                 if (vnic.func_default) {
4088                         rte_free(vnic_ids);
4089                         return vnic.fw_vnic_id;
4090                 }
4091         }
4092         /* Could not find a default VNIC. */
4093         PMD_DRV_LOG(ERR, "No default VNIC\n");
4094 exit:
4095         rte_free(vnic_ids);
4096         return rc;
4097 }
4098
4099 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4100                          uint16_t dst_id,
4101                          struct bnxt_filter_info *filter)
4102 {
4103         int rc = 0;
4104         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4105         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4106         uint32_t enables = 0;
4107
4108         if (filter->fw_em_filter_id != UINT64_MAX)
4109                 bnxt_hwrm_clear_em_filter(bp, filter);
4110
4111         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4112
4113         req.flags = rte_cpu_to_le_32(filter->flags);
4114
4115         enables = filter->enables |
4116               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4117         req.dst_id = rte_cpu_to_le_16(dst_id);
4118
4119         if (filter->ip_addr_type) {
4120                 req.ip_addr_type = filter->ip_addr_type;
4121                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4122         }
4123         if (enables &
4124             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4125                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4126         if (enables &
4127             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4128                 memcpy(req.src_macaddr, filter->src_macaddr,
4129                        RTE_ETHER_ADDR_LEN);
4130         if (enables &
4131             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4132                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4133                        RTE_ETHER_ADDR_LEN);
4134         if (enables &
4135             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4136                 req.ovlan_vid = filter->l2_ovlan;
4137         if (enables &
4138             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4139                 req.ivlan_vid = filter->l2_ivlan;
4140         if (enables &
4141             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4142                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4143         if (enables &
4144             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4145                 req.ip_protocol = filter->ip_protocol;
4146         if (enables &
4147             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4148                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4149         if (enables &
4150             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4151                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4152         if (enables &
4153             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4154                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4155         if (enables &
4156             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4157                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4158         if (enables &
4159             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4160                 req.mirror_vnic_id = filter->mirror_vnic_id;
4161
4162         req.enables = rte_cpu_to_le_32(enables);
4163
4164         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4165
4166         HWRM_CHECK_RESULT();
4167
4168         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4169         HWRM_UNLOCK();
4170
4171         return rc;
4172 }
4173
4174 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4175 {
4176         int rc = 0;
4177         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4178         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4179
4180         if (filter->fw_em_filter_id == UINT64_MAX)
4181                 return 0;
4182
4183         PMD_DRV_LOG(ERR, "Clear EM filter\n");
4184         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4185
4186         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4187
4188         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4189
4190         HWRM_CHECK_RESULT();
4191         HWRM_UNLOCK();
4192
4193         filter->fw_em_filter_id = UINT64_MAX;
4194         filter->fw_l2_filter_id = UINT64_MAX;
4195
4196         return 0;
4197 }
4198
4199 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4200                          uint16_t dst_id,
4201                          struct bnxt_filter_info *filter)
4202 {
4203         int rc = 0;
4204         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4205         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4206                                                 bp->hwrm_cmd_resp_addr;
4207         uint32_t enables = 0;
4208
4209         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4210                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4211
4212         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4213
4214         req.flags = rte_cpu_to_le_32(filter->flags);
4215
4216         enables = filter->enables |
4217               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4218         req.dst_id = rte_cpu_to_le_16(dst_id);
4219
4220
4221         if (filter->ip_addr_type) {
4222                 req.ip_addr_type = filter->ip_addr_type;
4223                 enables |=
4224                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4225         }
4226         if (enables &
4227             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4228                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4229         if (enables &
4230             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4231                 memcpy(req.src_macaddr, filter->src_macaddr,
4232                        RTE_ETHER_ADDR_LEN);
4233         //if (enables &
4234             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4235                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4236                        //RTE_ETHER_ADDR_LEN);
4237         if (enables &
4238             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4239                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4240         if (enables &
4241             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4242                 req.ip_protocol = filter->ip_protocol;
4243         if (enables &
4244             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4245                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4246         if (enables &
4247             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4248                 req.src_ipaddr_mask[0] =
4249                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4250         if (enables &
4251             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4252                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4253         if (enables &
4254             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4255                 req.dst_ipaddr_mask[0] =
4256                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4257         if (enables &
4258             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4259                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4260         if (enables &
4261             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4262                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4263         if (enables &
4264             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4265                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4266         if (enables &
4267             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4268                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4269         if (enables &
4270             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4271                 req.mirror_vnic_id = filter->mirror_vnic_id;
4272
4273         req.enables = rte_cpu_to_le_32(enables);
4274
4275         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4276
4277         HWRM_CHECK_RESULT();
4278
4279         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4280         HWRM_UNLOCK();
4281
4282         return rc;
4283 }
4284
4285 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4286                                 struct bnxt_filter_info *filter)
4287 {
4288         int rc = 0;
4289         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4290         struct hwrm_cfa_ntuple_filter_free_output *resp =
4291                                                 bp->hwrm_cmd_resp_addr;
4292
4293         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4294                 return 0;
4295
4296         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4297
4298         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4299
4300         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4301
4302         HWRM_CHECK_RESULT();
4303         HWRM_UNLOCK();
4304
4305         filter->fw_ntuple_filter_id = UINT64_MAX;
4306
4307         return 0;
4308 }
4309
4310 static int
4311 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4312 {
4313         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4314         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4315         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4316         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4317         uint16_t *ring_tbl = vnic->rss_table;
4318         int nr_ctxs = vnic->num_lb_ctxts;
4319         int max_rings = bp->rx_nr_rings;
4320         int i, j, k, cnt;
4321         int rc = 0;
4322
4323         for (i = 0, k = 0; i < nr_ctxs; i++) {
4324                 struct bnxt_rx_ring_info *rxr;
4325                 struct bnxt_cp_ring_info *cpr;
4326
4327                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4328
4329                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4330                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4331                 req.hash_mode_flags = vnic->hash_mode;
4332
4333                 req.ring_grp_tbl_addr =
4334                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4335                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4336                                      2 * sizeof(*ring_tbl));
4337                 req.hash_key_tbl_addr =
4338                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4339
4340                 req.ring_table_pair_index = i;
4341                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4342
4343                 for (j = 0; j < 64; j++) {
4344                         uint16_t ring_id;
4345
4346                         /* Find next active ring. */
4347                         for (cnt = 0; cnt < max_rings; cnt++) {
4348                                 if (rx_queue_state[k] !=
4349                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4350                                         break;
4351                                 if (++k == max_rings)
4352                                         k = 0;
4353                         }
4354
4355                         /* Return if no rings are active. */
4356                         if (cnt == max_rings)
4357                                 return 0;
4358
4359                         /* Add rx/cp ring pair to RSS table. */
4360                         rxr = rxqs[k]->rx_ring;
4361                         cpr = rxqs[k]->cp_ring;
4362
4363                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4364                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4365                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4366                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4367
4368                         if (++k == max_rings)
4369                                 k = 0;
4370                 }
4371                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4372                                             BNXT_USE_CHIMP_MB);
4373
4374                 HWRM_CHECK_RESULT();
4375                 HWRM_UNLOCK();
4376         }
4377
4378         return rc;
4379 }
4380
4381 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4382 {
4383         unsigned int rss_idx, fw_idx, i;
4384
4385         if (!(vnic->rss_table && vnic->hash_type))
4386                 return 0;
4387
4388         if (BNXT_CHIP_THOR(bp))
4389                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4390
4391         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4392                 return 0;
4393
4394         if (vnic->rss_table && vnic->hash_type) {
4395                 /*
4396                  * Fill the RSS hash & redirection table with
4397                  * ring group ids for all VNICs
4398                  */
4399                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4400                         rss_idx++, fw_idx++) {
4401                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4402                                 fw_idx %= bp->rx_cp_nr_rings;
4403                                 if (vnic->fw_grp_ids[fw_idx] !=
4404                                     INVALID_HW_RING_ID)
4405                                         break;
4406                                 fw_idx++;
4407                         }
4408                         if (i == bp->rx_cp_nr_rings)
4409                                 return 0;
4410                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4411                 }
4412                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4413         }
4414
4415         return 0;
4416 }
4417
4418 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4419         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4420 {
4421         uint16_t flags;
4422
4423         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4424
4425         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4426         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4427
4428         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4429         req->num_cmpl_dma_aggr_during_int =
4430                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4431
4432         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4433
4434         /* min timer set to 1/2 of interrupt timer */
4435         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4436
4437         /* buf timer set to 1/4 of interrupt timer */
4438         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4439
4440         req->cmpl_aggr_dma_tmr_during_int =
4441                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4442
4443         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4444                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4445         req->flags = rte_cpu_to_le_16(flags);
4446 }
4447
4448 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4449                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4450 {
4451         struct hwrm_ring_aggint_qcaps_input req = {0};
4452         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4453         uint32_t enables;
4454         uint16_t flags;
4455         int rc;
4456
4457         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4458         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4459         HWRM_CHECK_RESULT();
4460
4461         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4462         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4463
4464         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4465                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4466         agg_req->flags = rte_cpu_to_le_16(flags);
4467         enables =
4468          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4469          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4470         agg_req->enables = rte_cpu_to_le_32(enables);
4471
4472         HWRM_UNLOCK();
4473         return rc;
4474 }
4475
4476 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4477                         struct bnxt_coal *coal, uint16_t ring_id)
4478 {
4479         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4480         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4481                                                 bp->hwrm_cmd_resp_addr;
4482         int rc;
4483
4484         /* Set ring coalesce parameters only for 100G NICs */
4485         if (BNXT_CHIP_THOR(bp)) {
4486                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4487                         return -1;
4488         } else if (bnxt_stratus_device(bp)) {
4489                 bnxt_hwrm_set_coal_params(coal, &req);
4490         } else {
4491                 return 0;
4492         }
4493
4494         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4495         req.ring_id = rte_cpu_to_le_16(ring_id);
4496         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4497         HWRM_CHECK_RESULT();
4498         HWRM_UNLOCK();
4499         return 0;
4500 }
4501
4502 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4503 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4504 {
4505         struct hwrm_func_backing_store_qcaps_input req = {0};
4506         struct hwrm_func_backing_store_qcaps_output *resp =
4507                 bp->hwrm_cmd_resp_addr;
4508         struct bnxt_ctx_pg_info *ctx_pg;
4509         struct bnxt_ctx_mem_info *ctx;
4510         int total_alloc_len;
4511         int rc, i;
4512
4513         if (!BNXT_CHIP_THOR(bp) ||
4514             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4515             BNXT_VF(bp) ||
4516             bp->ctx)
4517                 return 0;
4518
4519         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4520         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4521         HWRM_CHECK_RESULT_SILENT();
4522
4523         total_alloc_len = sizeof(*ctx);
4524         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4525                           RTE_CACHE_LINE_SIZE);
4526         if (!ctx) {
4527                 rc = -ENOMEM;
4528                 goto ctx_err;
4529         }
4530
4531         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4532                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4533                             RTE_CACHE_LINE_SIZE);
4534         if (!ctx_pg) {
4535                 rc = -ENOMEM;
4536                 goto ctx_err;
4537         }
4538         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4539                 ctx->tqm_mem[i] = ctx_pg;
4540
4541         bp->ctx = ctx;
4542         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4543         ctx->qp_min_qp1_entries =
4544                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4545         ctx->qp_max_l2_entries =
4546                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4547         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4548         ctx->srq_max_l2_entries =
4549                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4550         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4551         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4552         ctx->cq_max_l2_entries =
4553                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4554         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4555         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4556         ctx->vnic_max_vnic_entries =
4557                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4558         ctx->vnic_max_ring_table_entries =
4559                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4560         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4561         ctx->stat_max_entries =
4562                 rte_le_to_cpu_32(resp->stat_max_entries);
4563         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4564         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4565         ctx->tqm_min_entries_per_ring =
4566                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4567         ctx->tqm_max_entries_per_ring =
4568                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4569         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4570         if (!ctx->tqm_entries_multiple)
4571                 ctx->tqm_entries_multiple = 1;
4572         ctx->mrav_max_entries =
4573                 rte_le_to_cpu_32(resp->mrav_max_entries);
4574         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4575         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4576         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4577 ctx_err:
4578         HWRM_UNLOCK();
4579         return rc;
4580 }
4581
4582 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4583 {
4584         struct hwrm_func_backing_store_cfg_input req = {0};
4585         struct hwrm_func_backing_store_cfg_output *resp =
4586                 bp->hwrm_cmd_resp_addr;
4587         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4588         struct bnxt_ctx_pg_info *ctx_pg;
4589         uint32_t *num_entries;
4590         uint64_t *pg_dir;
4591         uint8_t *pg_attr;
4592         uint32_t ena;
4593         int i, rc;
4594
4595         if (!ctx)
4596                 return 0;
4597
4598         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4599         req.enables = rte_cpu_to_le_32(enables);
4600
4601         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4602                 ctx_pg = &ctx->qp_mem;
4603                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4604                 req.qp_num_qp1_entries =
4605                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4606                 req.qp_num_l2_entries =
4607                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4608                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4609                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4610                                       &req.qpc_pg_size_qpc_lvl,
4611                                       &req.qpc_page_dir);
4612         }
4613
4614         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4615                 ctx_pg = &ctx->srq_mem;
4616                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4617                 req.srq_num_l2_entries =
4618                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4619                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4620                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4621                                       &req.srq_pg_size_srq_lvl,
4622                                       &req.srq_page_dir);
4623         }
4624
4625         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4626                 ctx_pg = &ctx->cq_mem;
4627                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4628                 req.cq_num_l2_entries =
4629                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4630                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4631                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4632                                       &req.cq_pg_size_cq_lvl,
4633                                       &req.cq_page_dir);
4634         }
4635
4636         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4637                 ctx_pg = &ctx->vnic_mem;
4638                 req.vnic_num_vnic_entries =
4639                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4640                 req.vnic_num_ring_table_entries =
4641                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4642                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4643                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4644                                       &req.vnic_pg_size_vnic_lvl,
4645                                       &req.vnic_page_dir);
4646         }
4647
4648         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4649                 ctx_pg = &ctx->stat_mem;
4650                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4651                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4652                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4653                                       &req.stat_pg_size_stat_lvl,
4654                                       &req.stat_page_dir);
4655         }
4656
4657         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4658         num_entries = &req.tqm_sp_num_entries;
4659         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4660         pg_dir = &req.tqm_sp_page_dir;
4661         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4662         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4663                 if (!(enables & ena))
4664                         continue;
4665
4666                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4667
4668                 ctx_pg = ctx->tqm_mem[i];
4669                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4670                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4671         }
4672
4673         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4674         HWRM_CHECK_RESULT();
4675         HWRM_UNLOCK();
4676
4677         return rc;
4678 }
4679
4680 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4681 {
4682         struct hwrm_port_qstats_ext_input req = {0};
4683         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4684         struct bnxt_pf_info *pf = &bp->pf;
4685         int rc;
4686
4687         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4688               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4689                 return 0;
4690
4691         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4692
4693         req.port_id = rte_cpu_to_le_16(pf->port_id);
4694         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4695                 req.tx_stat_host_addr =
4696                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4697                 req.tx_stat_size =
4698                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4699         }
4700         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4701                 req.rx_stat_host_addr =
4702                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4703                 req.rx_stat_size =
4704                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4705         }
4706         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4707
4708         if (rc) {
4709                 bp->fw_rx_port_stats_ext_size = 0;
4710                 bp->fw_tx_port_stats_ext_size = 0;
4711         } else {
4712                 bp->fw_rx_port_stats_ext_size =
4713                         rte_le_to_cpu_16(resp->rx_stat_size);
4714                 bp->fw_tx_port_stats_ext_size =
4715                         rte_le_to_cpu_16(resp->tx_stat_size);
4716         }
4717
4718         HWRM_CHECK_RESULT();
4719         HWRM_UNLOCK();
4720
4721         return rc;
4722 }
4723
4724 int
4725 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4726 {
4727         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4728         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4729                 bp->hwrm_cmd_resp_addr;
4730         int rc = 0;
4731
4732         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4733         req.tunnel_type = type;
4734         req.dest_fid = bp->fw_fid;
4735         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4736         HWRM_CHECK_RESULT();
4737
4738         HWRM_UNLOCK();
4739
4740         return rc;
4741 }
4742
4743 int
4744 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4745 {
4746         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4747         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4748                 bp->hwrm_cmd_resp_addr;
4749         int rc = 0;
4750
4751         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4752         req.tunnel_type = type;
4753         req.dest_fid = bp->fw_fid;
4754         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4755         HWRM_CHECK_RESULT();
4756
4757         HWRM_UNLOCK();
4758
4759         return rc;
4760 }
4761
4762 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4763 {
4764         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4765         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4766                 bp->hwrm_cmd_resp_addr;
4767         int rc = 0;
4768
4769         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4770         req.src_fid = bp->fw_fid;
4771         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4772         HWRM_CHECK_RESULT();
4773
4774         if (type)
4775                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4776
4777         HWRM_UNLOCK();
4778
4779         return rc;
4780 }
4781
4782 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4783                                    uint16_t *dst_fid)
4784 {
4785         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4786         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4787                 bp->hwrm_cmd_resp_addr;
4788         int rc = 0;
4789
4790         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4791         req.src_fid = bp->fw_fid;
4792         req.tunnel_type = tun_type;
4793         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4794         HWRM_CHECK_RESULT();
4795
4796         if (dst_fid)
4797                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4798
4799         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4800
4801         HWRM_UNLOCK();
4802
4803         return rc;
4804 }
4805
4806 int bnxt_hwrm_set_mac(struct bnxt *bp)
4807 {
4808         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4809         struct hwrm_func_vf_cfg_input req = {0};
4810         int rc = 0;
4811
4812         if (!BNXT_VF(bp))
4813                 return 0;
4814
4815         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4816
4817         req.enables =
4818                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4819         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4820
4821         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4822
4823         HWRM_CHECK_RESULT();
4824
4825         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4826         HWRM_UNLOCK();
4827
4828         return rc;
4829 }
4830
4831 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4832 {
4833         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4834         struct hwrm_func_drv_if_change_input req = {0};
4835         uint32_t flags;
4836         int rc;
4837
4838         if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4839                 return 0;
4840
4841         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4842          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4843          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4844          */
4845         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4846                 return 0;
4847
4848         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4849
4850         if (up)
4851                 req.flags =
4852                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4853
4854         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4855
4856         HWRM_CHECK_RESULT();
4857         flags = rte_le_to_cpu_32(resp->flags);
4858         HWRM_UNLOCK();
4859
4860         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4861                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4862                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4863         }
4864
4865         return 0;
4866 }
4867
4868 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4869 {
4870         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4871         struct bnxt_error_recovery_info *info = bp->recovery_info;
4872         struct hwrm_error_recovery_qcfg_input req = {0};
4873         uint32_t flags = 0;
4874         unsigned int i;
4875         int rc;
4876
4877         /* Older FW does not have error recovery support */
4878         if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4879                 return 0;
4880
4881         if (!info) {
4882                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4883                                    sizeof(*info), 0);
4884                 bp->recovery_info = info;
4885                 if (info == NULL)
4886                         return -ENOMEM;
4887         } else {
4888                 memset(info, 0, sizeof(*info));
4889         }
4890
4891         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4892
4893         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4894
4895         HWRM_CHECK_RESULT();
4896
4897         flags = rte_le_to_cpu_32(resp->flags);
4898         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4899                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4900         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4901                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4902
4903         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4904             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4905                 rc = -EINVAL;
4906                 goto err;
4907         }
4908
4909         /* FW returned values are in units of 100msec */
4910         info->driver_polling_freq =
4911                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4912         info->master_func_wait_period =
4913                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4914         info->normal_func_wait_period =
4915                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4916         info->master_func_wait_period_after_reset =
4917                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4918         info->max_bailout_time_after_reset =
4919                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4920         info->status_regs[BNXT_FW_STATUS_REG] =
4921                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4922         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4923                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4924         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4925                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4926         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4927                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4928         info->reg_array_cnt =
4929                 rte_le_to_cpu_32(resp->reg_array_cnt);
4930
4931         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4932                 rc = -EINVAL;
4933                 goto err;
4934         }
4935
4936         for (i = 0; i < info->reg_array_cnt; i++) {
4937                 info->reset_reg[i] =
4938                         rte_le_to_cpu_32(resp->reset_reg[i]);
4939                 info->reset_reg_val[i] =
4940                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4941                 info->delay_after_reset[i] =
4942                         resp->delay_after_reset[i];
4943         }
4944 err:
4945         HWRM_UNLOCK();
4946
4947         /* Map the FW status registers */
4948         if (!rc)
4949                 rc = bnxt_map_fw_health_status_regs(bp);
4950
4951         if (rc) {
4952                 rte_free(bp->recovery_info);
4953                 bp->recovery_info = NULL;
4954         }
4955         return rc;
4956 }
4957
4958 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4959 {
4960         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4961         struct hwrm_fw_reset_input req = {0};
4962         int rc;
4963
4964         if (!BNXT_PF(bp))
4965                 return -EOPNOTSUPP;
4966
4967         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4968
4969         req.embedded_proc_type =
4970                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4971         req.selfrst_status =
4972                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4973         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4974
4975         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4976                                     BNXT_USE_KONG(bp));
4977
4978         HWRM_CHECK_RESULT();
4979         HWRM_UNLOCK();
4980
4981         return rc;
4982 }
4983
4984 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4985 {
4986         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4987         struct hwrm_port_ts_query_input req = {0};
4988         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4989         uint32_t flags = 0;
4990         int rc;
4991
4992         if (!ptp)
4993                 return 0;
4994
4995         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4996
4997         switch (path) {
4998         case BNXT_PTP_FLAGS_PATH_TX:
4999                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5000                 break;
5001         case BNXT_PTP_FLAGS_PATH_RX:
5002                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5003                 break;
5004         case BNXT_PTP_FLAGS_CURRENT_TIME:
5005                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5006                 break;
5007         }
5008
5009         req.flags = rte_cpu_to_le_32(flags);
5010         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5011
5012         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5013
5014         HWRM_CHECK_RESULT();
5015
5016         if (timestamp) {
5017                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5018                 *timestamp |=
5019                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5020         }
5021         HWRM_UNLOCK();
5022
5023         return rc;
5024 }
5025
5026 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5027 {
5028         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5029                                         bp->hwrm_cmd_resp_addr;
5030         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5031         uint32_t flags = 0;
5032         int rc = 0;
5033
5034         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5035                 return rc;
5036
5037         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5038                 PMD_DRV_LOG(DEBUG,
5039                             "Not a PF or trusted VF. Command not supported\n");
5040                 return 0;
5041         }
5042
5043         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5044         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5045
5046         HWRM_CHECK_RESULT();
5047         flags = rte_le_to_cpu_32(resp->flags);
5048         HWRM_UNLOCK();
5049
5050         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5051                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5052                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5053         }
5054
5055         return rc;
5056 }