1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 10000
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(void *) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
64 * HWRM Functions (sent to HWRM)
65 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
66 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
67 * command was failed by the ChiMP.
70 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
74 struct input *req = msg;
75 struct output *resp = bp->hwrm_cmd_resp_addr;
79 uint16_t max_req_len = bp->max_req_len;
80 struct hwrm_short_input short_input = { 0 };
82 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
83 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
85 memset(short_cmd_req, 0, bp->max_req_len);
86 memcpy(short_cmd_req, req, msg_len);
88 short_input.req_type = rte_cpu_to_le_16(req->req_type);
89 short_input.signature = rte_cpu_to_le_16(
90 HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
91 short_input.size = rte_cpu_to_le_16(msg_len);
92 short_input.req_addr =
93 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
95 data = (uint32_t *)&short_input;
96 msg_len = sizeof(short_input);
98 /* Sync memory write before updating doorbell */
101 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
104 /* Write request msg to hwrm channel */
105 for (i = 0; i < msg_len; i += 4) {
106 bar = (uint8_t *)bp->bar0 + i;
107 rte_write32(*data, bar);
111 /* Zero the rest of the request space */
112 for (; i < max_req_len; i += 4) {
113 bar = (uint8_t *)bp->bar0 + i;
117 /* Ring channel doorbell */
118 bar = (uint8_t *)bp->bar0 + 0x100;
121 /* Poll for the valid bit */
122 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
123 /* Sanity check on the resp->resp_len */
125 if (resp->resp_len && resp->resp_len <=
127 /* Last byte of resp contains the valid key */
128 valid = (uint8_t *)resp + resp->resp_len - 1;
129 if (*valid == HWRM_RESP_VALID_KEY)
135 if (i >= HWRM_CMD_TIMEOUT) {
136 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
147 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
148 * spinlock, and does initial processing.
150 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
151 * releases the spinlock only if it returns. If the regular int return codes
152 * are not used by the function, HWRM_CHECK_RESULT() should not be used
153 * directly, rather it should be copied and modified to suit the function.
155 * HWRM_UNLOCK() must be called after all response processing is completed.
157 #define HWRM_PREP(req, type) do { \
158 rte_spinlock_lock(&bp->hwrm_lock); \
159 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
160 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
161 req.cmpl_ring = rte_cpu_to_le_16(-1); \
162 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
163 req.target_id = rte_cpu_to_le_16(0xffff); \
164 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
167 #define HWRM_CHECK_RESULT() do {\
169 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
170 rte_spinlock_unlock(&bp->hwrm_lock); \
173 if (resp->error_code) { \
174 rc = rte_le_to_cpu_16(resp->error_code); \
175 if (resp->resp_len >= 16) { \
176 struct hwrm_err_output *tmp_hwrm_err_op = \
179 "error %d:%d:%08x:%04x\n", \
180 rc, tmp_hwrm_err_op->cmd_err, \
182 tmp_hwrm_err_op->opaque_0), \
184 tmp_hwrm_err_op->opaque_1)); \
186 PMD_DRV_LOG(ERR, "error %d\n", rc); \
188 rte_spinlock_unlock(&bp->hwrm_lock); \
193 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
195 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
198 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
199 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
201 HWRM_PREP(req, CFA_L2_SET_RX_MASK);
202 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
205 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
213 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
214 struct bnxt_vnic_info *vnic,
216 struct bnxt_vlan_table_entry *vlan_table)
219 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
220 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
223 HWRM_PREP(req, CFA_L2_SET_RX_MASK);
224 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
226 /* FIXME add multicast flag, when multicast adding options is supported
229 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
230 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
231 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
232 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
233 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
234 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
235 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
236 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
237 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
238 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
239 if (vnic->mc_addr_cnt) {
240 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
241 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
242 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
245 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
246 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
247 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
248 rte_mem_virt2iova(vlan_table));
249 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
251 req.mask = rte_cpu_to_le_32(mask);
253 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
261 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
263 struct bnxt_vlan_antispoof_table_entry *vlan_table)
266 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
267 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
268 bp->hwrm_cmd_resp_addr;
271 * Older HWRM versions did not support this command, and the set_rx_mask
272 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
273 * removed from set_rx_mask call, and this command was added.
275 * This command is also present from 1.7.8.11 and higher,
278 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
279 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
280 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
285 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG);
286 req.fid = rte_cpu_to_le_16(fid);
288 req.vlan_tag_mask_tbl_addr =
289 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
290 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
292 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
300 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
301 struct bnxt_filter_info *filter)
304 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
305 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
307 if (filter->fw_l2_filter_id == UINT64_MAX)
310 HWRM_PREP(req, CFA_L2_FILTER_FREE);
312 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
314 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
319 filter->fw_l2_filter_id = -1;
324 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
326 struct bnxt_filter_info *filter)
329 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
330 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
331 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
332 const struct rte_eth_vmdq_rx_conf *conf =
333 &dev_conf->rx_adv_conf.vmdq_rx_conf;
334 uint32_t enables = 0;
335 uint16_t j = dst_id - 1;
337 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
338 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
339 conf->pool_map[j].pools & (1UL << j)) {
341 "Add vlan %u to vmdq pool %u\n",
342 conf->pool_map[j].vlan_id, j);
344 filter->l2_ivlan = conf->pool_map[j].vlan_id;
346 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
347 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
350 if (filter->fw_l2_filter_id != UINT64_MAX)
351 bnxt_hwrm_clear_l2_filter(bp, filter);
353 HWRM_PREP(req, CFA_L2_FILTER_ALLOC);
355 req.flags = rte_cpu_to_le_32(filter->flags);
357 enables = filter->enables |
358 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
359 req.dst_id = rte_cpu_to_le_16(dst_id);
362 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
363 memcpy(req.l2_addr, filter->l2_addr,
366 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
367 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
370 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
371 req.l2_ovlan = filter->l2_ovlan;
373 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
374 req.l2_ovlan = filter->l2_ivlan;
376 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
377 req.l2_ovlan_mask = filter->l2_ovlan_mask;
379 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
380 req.l2_ovlan_mask = filter->l2_ivlan_mask;
381 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
382 req.src_id = rte_cpu_to_le_32(filter->src_id);
383 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
384 req.src_type = filter->src_type;
386 req.enables = rte_cpu_to_le_32(enables);
388 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
392 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
398 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
400 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
401 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
408 HWRM_PREP(req, PORT_MAC_CFG);
411 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
413 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
414 if (ptp->tx_tstamp_en)
415 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
417 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
418 req.flags = rte_cpu_to_le_32(flags);
420 rte_cpu_to_le_32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
421 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
423 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
429 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
432 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
433 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
434 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
436 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
440 HWRM_PREP(req, PORT_MAC_PTP_QCFG);
442 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
444 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
448 if (!(resp->flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS))
451 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
455 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
456 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
457 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
458 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
459 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
460 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
461 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
462 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
463 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
464 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
465 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
466 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
467 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
468 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
469 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
470 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
471 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
472 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
480 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
483 struct hwrm_func_qcaps_input req = {.req_type = 0 };
484 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
485 uint16_t new_max_vfs;
489 HWRM_PREP(req, FUNC_QCAPS);
491 req.fid = rte_cpu_to_le_16(0xffff);
493 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
497 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
498 flags = rte_le_to_cpu_32(resp->flags);
500 bp->pf.port_id = resp->port_id;
501 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
502 new_max_vfs = bp->pdev->max_vfs;
503 if (new_max_vfs != bp->pf.max_vfs) {
505 rte_free(bp->pf.vf_info);
506 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
507 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
508 bp->pf.max_vfs = new_max_vfs;
509 for (i = 0; i < new_max_vfs; i++) {
510 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
511 bp->pf.vf_info[i].vlan_table =
512 rte_zmalloc("VF VLAN table",
515 if (bp->pf.vf_info[i].vlan_table == NULL)
517 "Fail to alloc VLAN table for VF %d\n",
521 bp->pf.vf_info[i].vlan_table);
522 bp->pf.vf_info[i].vlan_as_table =
523 rte_zmalloc("VF VLAN AS table",
526 if (bp->pf.vf_info[i].vlan_as_table == NULL)
528 "Alloc VLAN AS table for VF %d fail\n",
532 bp->pf.vf_info[i].vlan_as_table);
533 STAILQ_INIT(&bp->pf.vf_info[i].filter);
538 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
539 memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
540 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
541 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
542 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
543 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
544 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
545 /* TODO: For now, do not support VMDq/RFS on VFs. */
550 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
554 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
556 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
557 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
558 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
559 PMD_DRV_LOG(INFO, "PTP SUPPORTED\n");
561 bnxt_hwrm_ptp_qcfg(bp);
570 int bnxt_hwrm_func_reset(struct bnxt *bp)
573 struct hwrm_func_reset_input req = {.req_type = 0 };
574 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
576 HWRM_PREP(req, FUNC_RESET);
578 req.enables = rte_cpu_to_le_32(0);
580 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
588 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
591 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
592 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
594 if (bp->flags & BNXT_FLAG_REGISTERED)
597 HWRM_PREP(req, FUNC_DRV_RGTR);
598 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
599 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
600 req.ver_maj = RTE_VER_YEAR;
601 req.ver_min = RTE_VER_MONTH;
602 req.ver_upd = RTE_VER_MINOR;
605 req.enables |= rte_cpu_to_le_32(
606 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
607 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
608 RTE_MIN(sizeof(req.vf_req_fwd),
609 sizeof(bp->pf.vf_req_fwd)));
612 req.async_event_fwd[0] |=
613 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
614 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
615 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
616 req.async_event_fwd[1] |=
617 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
618 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
620 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
625 bp->flags |= BNXT_FLAG_REGISTERED;
630 int bnxt_hwrm_ver_get(struct bnxt *bp)
633 struct hwrm_ver_get_input req = {.req_type = 0 };
634 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
637 uint16_t max_resp_len;
638 char type[RTE_MEMZONE_NAMESIZE];
639 uint32_t dev_caps_cfg;
641 bp->max_req_len = HWRM_MAX_REQ_LEN;
642 HWRM_PREP(req, VER_GET);
644 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
645 req.hwrm_intf_min = HWRM_VERSION_MINOR;
646 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
648 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
652 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
653 resp->hwrm_intf_maj, resp->hwrm_intf_min,
655 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
656 bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
657 (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
658 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
659 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
661 my_version = HWRM_VERSION_MAJOR << 16;
662 my_version |= HWRM_VERSION_MINOR << 8;
663 my_version |= HWRM_VERSION_UPDATE;
665 fw_version = resp->hwrm_intf_maj << 16;
666 fw_version |= resp->hwrm_intf_min << 8;
667 fw_version |= resp->hwrm_intf_upd;
669 if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
670 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
675 if (my_version != fw_version) {
676 PMD_DRV_LOG(INFO, "BNXT Driver/HWRM API mismatch.\n");
677 if (my_version < fw_version) {
679 "Firmware API version is newer than driver.\n");
681 "The driver may be missing features.\n");
684 "Firmware API version is older than driver.\n");
686 "Not all driver features may be functional.\n");
690 if (bp->max_req_len > resp->max_req_win_len) {
691 PMD_DRV_LOG(ERR, "Unsupported request length\n");
694 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
695 max_resp_len = resp->max_resp_len;
696 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
698 if (bp->max_resp_len != max_resp_len) {
699 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
700 bp->pdev->addr.domain, bp->pdev->addr.bus,
701 bp->pdev->addr.devid, bp->pdev->addr.function);
703 rte_free(bp->hwrm_cmd_resp_addr);
705 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
706 if (bp->hwrm_cmd_resp_addr == NULL) {
710 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
711 bp->hwrm_cmd_resp_dma_addr =
712 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
713 if (bp->hwrm_cmd_resp_dma_addr == 0) {
715 "Unable to map response buffer to physical memory.\n");
719 bp->max_resp_len = max_resp_len;
723 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
725 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
726 PMD_DRV_LOG(DEBUG, "Short command supported\n");
728 rte_free(bp->hwrm_short_cmd_req_addr);
730 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
732 if (bp->hwrm_short_cmd_req_addr == NULL) {
736 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
737 bp->hwrm_short_cmd_req_dma_addr =
738 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
739 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
740 rte_free(bp->hwrm_short_cmd_req_addr);
742 "Unable to map buffer to physical memory.\n");
747 bp->flags |= BNXT_FLAG_SHORT_CMD;
755 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
758 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
759 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
761 if (!(bp->flags & BNXT_FLAG_REGISTERED))
764 HWRM_PREP(req, FUNC_DRV_UNRGTR);
767 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
772 bp->flags &= ~BNXT_FLAG_REGISTERED;
777 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
780 struct hwrm_port_phy_cfg_input req = {0};
781 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
782 uint32_t enables = 0;
784 HWRM_PREP(req, PORT_PHY_CFG);
787 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
788 if (bp->link_info.auto_mode && conf->link_speed) {
789 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
790 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
793 req.flags = rte_cpu_to_le_32(conf->phy_flags);
794 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
795 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
797 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
798 * any auto mode, even "none".
800 if (!conf->link_speed) {
801 /* No speeds specified. Enable AutoNeg - all speeds */
803 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
805 /* AutoNeg - Advertise speeds specified. */
806 if (conf->auto_link_speed_mask &&
807 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
809 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
810 req.auto_link_speed_mask =
811 conf->auto_link_speed_mask;
813 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
816 req.auto_duplex = conf->duplex;
817 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
818 req.auto_pause = conf->auto_pause;
819 req.force_pause = conf->force_pause;
820 /* Set force_pause if there is no auto or if there is a force */
821 if (req.auto_pause && !req.force_pause)
822 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
824 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
826 req.enables = rte_cpu_to_le_32(enables);
829 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
830 PMD_DRV_LOG(INFO, "Force Link Down\n");
833 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
841 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
842 struct bnxt_link_info *link_info)
845 struct hwrm_port_phy_qcfg_input req = {0};
846 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
848 HWRM_PREP(req, PORT_PHY_QCFG);
850 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
854 link_info->phy_link_status = resp->link;
856 (link_info->phy_link_status ==
857 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
858 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
859 link_info->duplex = resp->duplex_cfg;
860 link_info->pause = resp->pause;
861 link_info->auto_pause = resp->auto_pause;
862 link_info->force_pause = resp->force_pause;
863 link_info->auto_mode = resp->auto_mode;
864 link_info->phy_type = resp->phy_type;
865 link_info->media_type = resp->media_type;
867 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
868 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
869 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
870 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
871 link_info->phy_ver[0] = resp->phy_maj;
872 link_info->phy_ver[1] = resp->phy_min;
873 link_info->phy_ver[2] = resp->phy_bld;
877 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
878 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
879 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
880 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
881 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
882 link_info->auto_link_speed_mask);
883 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
884 link_info->force_link_speed);
889 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
892 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
893 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
895 HWRM_PREP(req, QUEUE_QPORTCFG);
897 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
901 #define GET_QUEUE_INFO(x) \
902 bp->cos_queue[x].id = resp->queue_id##x; \
903 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
919 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
920 struct bnxt_ring *ring,
921 uint32_t ring_type, uint32_t map_index,
922 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
925 uint32_t enables = 0;
926 struct hwrm_ring_alloc_input req = {.req_type = 0 };
927 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
929 HWRM_PREP(req, RING_ALLOC);
931 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
932 req.fbo = rte_cpu_to_le_32(0);
933 /* Association of ring index with doorbell index */
934 req.logical_id = rte_cpu_to_le_16(map_index);
935 req.length = rte_cpu_to_le_32(ring->ring_size);
938 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
939 req.queue_id = bp->cos_queue[0].id;
941 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
942 req.ring_type = ring_type;
943 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
944 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
945 if (stats_ctx_id != INVALID_STATS_CTX_ID)
947 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
949 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
950 req.ring_type = ring_type;
952 * TODO: Some HWRM versions crash with
953 * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
955 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
958 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
963 req.enables = rte_cpu_to_le_32(enables);
965 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
967 if (rc || resp->error_code) {
968 if (rc == 0 && resp->error_code)
969 rc = rte_le_to_cpu_16(resp->error_code);
971 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
973 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
976 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
978 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
981 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
983 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
987 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
993 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
998 int bnxt_hwrm_ring_free(struct bnxt *bp,
999 struct bnxt_ring *ring, uint32_t ring_type)
1002 struct hwrm_ring_free_input req = {.req_type = 0 };
1003 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1005 HWRM_PREP(req, RING_FREE);
1007 req.ring_type = ring_type;
1008 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1010 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1012 if (rc || resp->error_code) {
1013 if (rc == 0 && resp->error_code)
1014 rc = rte_le_to_cpu_16(resp->error_code);
1017 switch (ring_type) {
1018 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1019 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1022 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1023 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1026 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1027 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1031 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1039 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1042 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1043 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1045 HWRM_PREP(req, RING_GRP_ALLOC);
1047 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1048 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1049 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1050 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1052 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1054 HWRM_CHECK_RESULT();
1056 bp->grp_info[idx].fw_grp_id =
1057 rte_le_to_cpu_16(resp->ring_group_id);
1064 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1067 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1068 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1070 HWRM_PREP(req, RING_GRP_FREE);
1072 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1074 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1076 HWRM_CHECK_RESULT();
1079 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1083 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1086 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1087 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1089 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1092 HWRM_PREP(req, STAT_CTX_CLR_STATS);
1094 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1096 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1098 HWRM_CHECK_RESULT();
1104 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1105 unsigned int idx __rte_unused)
1108 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1109 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1111 HWRM_PREP(req, STAT_CTX_ALLOC);
1113 req.update_period_ms = rte_cpu_to_le_32(0);
1115 req.stats_dma_addr =
1116 rte_cpu_to_le_64(cpr->hw_stats_map);
1118 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1120 HWRM_CHECK_RESULT();
1122 cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
1129 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1130 unsigned int idx __rte_unused)
1133 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1134 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1136 HWRM_PREP(req, STAT_CTX_FREE);
1138 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1140 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1142 HWRM_CHECK_RESULT();
1148 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1151 struct hwrm_vnic_alloc_input req = { 0 };
1152 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1154 /* map ring groups to this vnic */
1155 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1156 vnic->start_grp_id, vnic->end_grp_id);
1157 for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
1158 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1159 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1160 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1161 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1162 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1163 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1164 ETHER_CRC_LEN + VLAN_TAG_SIZE;
1165 HWRM_PREP(req, VNIC_ALLOC);
1167 if (vnic->func_default)
1169 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1170 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1172 HWRM_CHECK_RESULT();
1174 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1176 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1180 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1181 struct bnxt_vnic_info *vnic,
1182 struct bnxt_plcmodes_cfg *pmode)
1185 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1186 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1188 HWRM_PREP(req, VNIC_PLCMODES_QCFG);
1190 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1192 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1194 HWRM_CHECK_RESULT();
1196 pmode->flags = rte_le_to_cpu_32(resp->flags);
1197 /* dflt_vnic bit doesn't exist in the _cfg command */
1198 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1199 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1200 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1201 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1208 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1209 struct bnxt_vnic_info *vnic,
1210 struct bnxt_plcmodes_cfg *pmode)
1213 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1214 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1216 HWRM_PREP(req, VNIC_PLCMODES_CFG);
1218 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1219 req.flags = rte_cpu_to_le_32(pmode->flags);
1220 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1221 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1222 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1223 req.enables = rte_cpu_to_le_32(
1224 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1225 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1226 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1229 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1231 HWRM_CHECK_RESULT();
1237 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1240 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1241 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1242 uint32_t ctx_enable_flag = 0;
1243 struct bnxt_plcmodes_cfg pmodes;
1245 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1246 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1250 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1254 HWRM_PREP(req, VNIC_CFG);
1256 /* Only RSS support for now TBD: COS & LB */
1258 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP);
1259 if (vnic->lb_rule != 0xffff)
1260 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1261 if (vnic->cos_rule != 0xffff)
1262 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1263 if (vnic->rss_rule != 0xffff) {
1264 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1265 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1267 req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1268 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1269 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1270 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1271 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1272 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1273 req.mru = rte_cpu_to_le_16(vnic->mru);
1274 if (vnic->func_default)
1276 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1277 if (vnic->vlan_strip)
1279 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1282 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1283 if (vnic->roce_dual)
1284 req.flags |= rte_cpu_to_le_32(
1285 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1286 if (vnic->roce_only)
1287 req.flags |= rte_cpu_to_le_32(
1288 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1289 if (vnic->rss_dflt_cr)
1290 req.flags |= rte_cpu_to_le_32(
1291 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1293 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1295 HWRM_CHECK_RESULT();
1298 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1303 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1307 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1308 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1310 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1311 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1314 HWRM_PREP(req, VNIC_QCFG);
1317 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1318 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1319 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1321 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1323 HWRM_CHECK_RESULT();
1325 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1326 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1327 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1328 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1329 vnic->mru = rte_le_to_cpu_16(resp->mru);
1330 vnic->func_default = rte_le_to_cpu_32(
1331 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1332 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1333 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1334 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1335 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1336 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1337 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1338 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1339 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1340 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1341 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1348 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1351 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1352 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1353 bp->hwrm_cmd_resp_addr;
1355 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC);
1357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1359 HWRM_CHECK_RESULT();
1361 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1363 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1368 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1371 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1372 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1373 bp->hwrm_cmd_resp_addr;
1375 if (vnic->rss_rule == 0xffff) {
1376 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1379 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE);
1381 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1383 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1385 HWRM_CHECK_RESULT();
1388 vnic->rss_rule = INVALID_HW_RING_ID;
1393 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1396 struct hwrm_vnic_free_input req = {.req_type = 0 };
1397 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1399 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1400 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1404 HWRM_PREP(req, VNIC_FREE);
1406 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1408 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1410 HWRM_CHECK_RESULT();
1413 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1417 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1418 struct bnxt_vnic_info *vnic)
1421 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1422 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1424 HWRM_PREP(req, VNIC_RSS_CFG);
1426 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1428 req.ring_grp_tbl_addr =
1429 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1430 req.hash_key_tbl_addr =
1431 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1432 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1434 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1436 HWRM_CHECK_RESULT();
1442 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1443 struct bnxt_vnic_info *vnic)
1446 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1447 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1450 HWRM_PREP(req, VNIC_PLCMODES_CFG);
1452 req.flags = rte_cpu_to_le_32(
1453 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1455 req.enables = rte_cpu_to_le_32(
1456 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1458 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1459 size -= RTE_PKTMBUF_HEADROOM;
1461 req.jumbo_thresh = rte_cpu_to_le_16(size);
1462 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1464 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1466 HWRM_CHECK_RESULT();
1472 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1473 struct bnxt_vnic_info *vnic, bool enable)
1476 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1477 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1479 HWRM_PREP(req, VNIC_TPA_CFG);
1482 req.enables = rte_cpu_to_le_32(
1483 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1484 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1485 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1486 req.flags = rte_cpu_to_le_32(
1487 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1488 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1489 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1490 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1491 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1492 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1493 req.max_agg_segs = rte_cpu_to_le_16(5);
1495 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1496 req.min_agg_len = rte_cpu_to_le_32(512);
1498 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1500 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1502 HWRM_CHECK_RESULT();
1508 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1510 struct hwrm_func_cfg_input req = {0};
1511 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1514 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1515 req.enables = rte_cpu_to_le_32(
1516 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1517 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1518 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1520 HWRM_PREP(req, FUNC_CFG);
1522 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1523 HWRM_CHECK_RESULT();
1526 bp->pf.vf_info[vf].random_mac = false;
1531 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1535 struct hwrm_func_qstats_input req = {.req_type = 0};
1536 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1538 HWRM_PREP(req, FUNC_QSTATS);
1540 req.fid = rte_cpu_to_le_16(fid);
1542 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1544 HWRM_CHECK_RESULT();
1547 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1554 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1555 struct rte_eth_stats *stats)
1558 struct hwrm_func_qstats_input req = {.req_type = 0};
1559 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1561 HWRM_PREP(req, FUNC_QSTATS);
1563 req.fid = rte_cpu_to_le_16(fid);
1565 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1567 HWRM_CHECK_RESULT();
1569 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1570 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1571 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1572 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1573 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1574 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1576 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1577 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1578 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1579 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1580 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1581 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1583 stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1584 stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1586 stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1593 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1596 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1597 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1599 HWRM_PREP(req, FUNC_CLR_STATS);
1601 req.fid = rte_cpu_to_le_16(fid);
1603 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1605 HWRM_CHECK_RESULT();
1612 * HWRM utility functions
1615 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1620 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1621 struct bnxt_tx_queue *txq;
1622 struct bnxt_rx_queue *rxq;
1623 struct bnxt_cp_ring_info *cpr;
1625 if (i >= bp->rx_cp_nr_rings) {
1626 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1629 rxq = bp->rx_queues[i];
1633 rc = bnxt_hwrm_stat_clear(bp, cpr);
1640 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1644 struct bnxt_cp_ring_info *cpr;
1646 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1648 if (i >= bp->rx_cp_nr_rings) {
1649 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1651 cpr = bp->rx_queues[i]->cp_ring;
1652 bp->grp_info[i].fw_stats_ctx = -1;
1654 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1655 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1656 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1664 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1669 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1670 struct bnxt_tx_queue *txq;
1671 struct bnxt_rx_queue *rxq;
1672 struct bnxt_cp_ring_info *cpr;
1674 if (i >= bp->rx_cp_nr_rings) {
1675 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1678 rxq = bp->rx_queues[i];
1682 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1690 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1695 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1697 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1700 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1708 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1709 unsigned int idx __rte_unused)
1711 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1713 bnxt_hwrm_ring_free(bp, cp_ring,
1714 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1715 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1716 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1717 sizeof(*cpr->cp_desc_ring));
1718 cpr->cp_raw_cons = 0;
1721 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1726 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1727 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1728 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1729 struct bnxt_ring *ring = txr->tx_ring_struct;
1730 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1731 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1733 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1734 bnxt_hwrm_ring_free(bp, ring,
1735 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1736 ring->fw_ring_id = INVALID_HW_RING_ID;
1737 memset(txr->tx_desc_ring, 0,
1738 txr->tx_ring_struct->ring_size *
1739 sizeof(*txr->tx_desc_ring));
1740 memset(txr->tx_buf_ring, 0,
1741 txr->tx_ring_struct->ring_size *
1742 sizeof(*txr->tx_buf_ring));
1746 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1747 bnxt_free_cp_ring(bp, cpr, idx);
1748 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1752 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1753 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1754 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1755 struct bnxt_ring *ring = rxr->rx_ring_struct;
1756 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1757 unsigned int idx = i + 1;
1759 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1760 bnxt_hwrm_ring_free(bp, ring,
1761 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1762 ring->fw_ring_id = INVALID_HW_RING_ID;
1763 bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1764 memset(rxr->rx_desc_ring, 0,
1765 rxr->rx_ring_struct->ring_size *
1766 sizeof(*rxr->rx_desc_ring));
1767 memset(rxr->rx_buf_ring, 0,
1768 rxr->rx_ring_struct->ring_size *
1769 sizeof(*rxr->rx_buf_ring));
1772 ring = rxr->ag_ring_struct;
1773 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1774 bnxt_hwrm_ring_free(bp, ring,
1775 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1776 ring->fw_ring_id = INVALID_HW_RING_ID;
1777 memset(rxr->ag_buf_ring, 0,
1778 rxr->ag_ring_struct->ring_size *
1779 sizeof(*rxr->ag_buf_ring));
1781 bp->grp_info[i].ag_fw_ring_id = INVALID_HW_RING_ID;
1783 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1784 bnxt_free_cp_ring(bp, cpr, idx);
1785 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1786 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1790 /* Default completion ring */
1792 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1794 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1795 bnxt_free_cp_ring(bp, cpr, 0);
1796 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1803 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1808 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1809 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1816 void bnxt_free_hwrm_resources(struct bnxt *bp)
1818 /* Release memzone */
1819 rte_free(bp->hwrm_cmd_resp_addr);
1820 rte_free(bp->hwrm_short_cmd_req_addr);
1821 bp->hwrm_cmd_resp_addr = NULL;
1822 bp->hwrm_short_cmd_req_addr = NULL;
1823 bp->hwrm_cmd_resp_dma_addr = 0;
1824 bp->hwrm_short_cmd_req_dma_addr = 0;
1827 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1829 struct rte_pci_device *pdev = bp->pdev;
1830 char type[RTE_MEMZONE_NAMESIZE];
1832 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1833 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1834 bp->max_resp_len = HWRM_MAX_RESP_LEN;
1835 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1836 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1837 if (bp->hwrm_cmd_resp_addr == NULL)
1839 bp->hwrm_cmd_resp_dma_addr =
1840 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1841 if (bp->hwrm_cmd_resp_dma_addr == 0) {
1843 "unable to map response address to physical memory\n");
1846 rte_spinlock_init(&bp->hwrm_lock);
1851 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1853 struct bnxt_filter_info *filter;
1856 STAILQ_FOREACH(filter, &vnic->filter, next) {
1857 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1858 rc = bnxt_hwrm_clear_em_filter(bp, filter);
1859 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1860 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1862 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1870 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1872 struct bnxt_filter_info *filter;
1873 struct rte_flow *flow;
1876 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
1877 filter = flow->filter;
1878 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
1879 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1880 rc = bnxt_hwrm_clear_em_filter(bp, filter);
1881 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1882 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1884 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1886 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
1894 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1896 struct bnxt_filter_info *filter;
1899 STAILQ_FOREACH(filter, &vnic->filter, next) {
1900 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1901 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
1903 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1904 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
1907 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
1915 void bnxt_free_tunnel_ports(struct bnxt *bp)
1917 if (bp->vxlan_port_cnt)
1918 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1919 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1921 if (bp->geneve_port_cnt)
1922 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1923 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1924 bp->geneve_port = 0;
1927 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1931 if (bp->vnic_info == NULL)
1935 * Cleanup VNICs in reverse order, to make sure the L2 filter
1936 * from vnic0 is last to be cleaned up.
1938 for (i = bp->nr_vnics - 1; i >= 0; i--) {
1939 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1941 bnxt_clear_hwrm_vnic_flows(bp, vnic);
1943 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1945 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1947 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1949 bnxt_hwrm_vnic_free(bp, vnic);
1951 /* Ring resources */
1952 bnxt_free_all_hwrm_rings(bp);
1953 bnxt_free_all_hwrm_ring_grps(bp);
1954 bnxt_free_all_hwrm_stat_ctxs(bp);
1955 bnxt_free_tunnel_ports(bp);
1958 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1960 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1962 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1963 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1965 switch (conf_link_speed) {
1966 case ETH_LINK_SPEED_10M_HD:
1967 case ETH_LINK_SPEED_100M_HD:
1968 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1970 return hw_link_duplex;
1973 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
1975 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
1978 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1980 uint16_t eth_link_speed = 0;
1982 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1983 return ETH_LINK_SPEED_AUTONEG;
1985 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1986 case ETH_LINK_SPEED_100M:
1987 case ETH_LINK_SPEED_100M_HD:
1989 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1991 case ETH_LINK_SPEED_1G:
1993 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1995 case ETH_LINK_SPEED_2_5G:
1997 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1999 case ETH_LINK_SPEED_10G:
2001 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2003 case ETH_LINK_SPEED_20G:
2005 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2007 case ETH_LINK_SPEED_25G:
2009 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2011 case ETH_LINK_SPEED_40G:
2013 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2015 case ETH_LINK_SPEED_50G:
2017 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2019 case ETH_LINK_SPEED_100G:
2021 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2025 "Unsupported link speed %d; default to AUTO\n",
2029 return eth_link_speed;
2032 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2033 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2034 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2035 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2037 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2041 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2044 if (link_speed & ETH_LINK_SPEED_FIXED) {
2045 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2047 if (one_speed & (one_speed - 1)) {
2049 "Invalid advertised speeds (%u) for port %u\n",
2050 link_speed, port_id);
2053 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2055 "Unsupported advertised speed (%u) for port %u\n",
2056 link_speed, port_id);
2060 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2062 "Unsupported advertised speeds (%u) for port %u\n",
2063 link_speed, port_id);
2071 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2075 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2076 if (bp->link_info.support_speeds)
2077 return bp->link_info.support_speeds;
2078 link_speed = BNXT_SUPPORTED_SPEEDS;
2081 if (link_speed & ETH_LINK_SPEED_100M)
2082 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2083 if (link_speed & ETH_LINK_SPEED_100M_HD)
2084 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2085 if (link_speed & ETH_LINK_SPEED_1G)
2086 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2087 if (link_speed & ETH_LINK_SPEED_2_5G)
2088 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2089 if (link_speed & ETH_LINK_SPEED_10G)
2090 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2091 if (link_speed & ETH_LINK_SPEED_20G)
2092 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2093 if (link_speed & ETH_LINK_SPEED_25G)
2094 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2095 if (link_speed & ETH_LINK_SPEED_40G)
2096 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2097 if (link_speed & ETH_LINK_SPEED_50G)
2098 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2099 if (link_speed & ETH_LINK_SPEED_100G)
2100 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2104 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2106 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2108 switch (hw_link_speed) {
2109 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2110 eth_link_speed = ETH_SPEED_NUM_100M;
2112 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2113 eth_link_speed = ETH_SPEED_NUM_1G;
2115 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2116 eth_link_speed = ETH_SPEED_NUM_2_5G;
2118 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2119 eth_link_speed = ETH_SPEED_NUM_10G;
2121 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2122 eth_link_speed = ETH_SPEED_NUM_20G;
2124 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2125 eth_link_speed = ETH_SPEED_NUM_25G;
2127 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2128 eth_link_speed = ETH_SPEED_NUM_40G;
2130 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2131 eth_link_speed = ETH_SPEED_NUM_50G;
2133 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2134 eth_link_speed = ETH_SPEED_NUM_100G;
2136 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2138 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2142 return eth_link_speed;
2145 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2147 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2149 switch (hw_link_duplex) {
2150 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2151 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2152 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2154 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2155 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2158 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2162 return eth_link_duplex;
2165 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2168 struct bnxt_link_info *link_info = &bp->link_info;
2170 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2173 "Get link config failed with rc %d\n", rc);
2176 if (link_info->link_speed)
2178 bnxt_parse_hw_link_speed(link_info->link_speed);
2180 link->link_speed = ETH_SPEED_NUM_NONE;
2181 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2182 link->link_status = link_info->link_up;
2183 link->link_autoneg = link_info->auto_mode ==
2184 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2185 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2190 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2193 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2194 struct bnxt_link_info link_req;
2195 uint16_t speed, autoneg;
2197 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2200 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2201 bp->eth_dev->data->port_id);
2205 memset(&link_req, 0, sizeof(link_req));
2206 link_req.link_up = link_up;
2210 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2211 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2212 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2213 /* Autoneg can be done only when the FW allows */
2214 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2215 bp->link_info.force_link_speed)) {
2216 link_req.phy_flags |=
2217 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2218 link_req.auto_link_speed_mask =
2219 bnxt_parse_eth_link_speed_mask(bp,
2220 dev_conf->link_speeds);
2222 if (bp->link_info.phy_type ==
2223 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2224 bp->link_info.phy_type ==
2225 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2226 bp->link_info.media_type ==
2227 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2228 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2232 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2233 /* If user wants a particular speed try that first. */
2235 link_req.link_speed = speed;
2236 else if (bp->link_info.force_link_speed)
2237 link_req.link_speed = bp->link_info.force_link_speed;
2239 link_req.link_speed = bp->link_info.auto_link_speed;
2241 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2242 link_req.auto_pause = bp->link_info.auto_pause;
2243 link_req.force_pause = bp->link_info.force_pause;
2246 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2249 "Set link config failed with rc %d\n", rc);
2257 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2259 struct hwrm_func_qcfg_input req = {0};
2260 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2264 HWRM_PREP(req, FUNC_QCFG);
2265 req.fid = rte_cpu_to_le_16(0xffff);
2267 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2269 HWRM_CHECK_RESULT();
2271 /* Hard Coded.. 0xfff VLAN ID mask */
2272 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2273 flags = rte_le_to_cpu_16(resp->flags);
2274 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2275 bp->flags |= BNXT_FLAG_MULTI_HOST;
2277 switch (resp->port_partition_type) {
2278 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2279 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2280 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2281 bp->port_partition_type = resp->port_partition_type;
2284 bp->port_partition_type = 0;
2293 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2294 struct hwrm_func_qcaps_output *qcaps)
2296 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2297 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2298 sizeof(qcaps->mac_address));
2299 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2300 qcaps->max_rx_rings = fcfg->num_rx_rings;
2301 qcaps->max_tx_rings = fcfg->num_tx_rings;
2302 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2303 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2305 qcaps->first_vf_id = 0;
2306 qcaps->max_vnics = fcfg->num_vnics;
2307 qcaps->max_decap_records = 0;
2308 qcaps->max_encap_records = 0;
2309 qcaps->max_tx_wm_flows = 0;
2310 qcaps->max_tx_em_flows = 0;
2311 qcaps->max_rx_wm_flows = 0;
2312 qcaps->max_rx_em_flows = 0;
2313 qcaps->max_flow_id = 0;
2314 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2315 qcaps->max_sp_tx_rings = 0;
2316 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2319 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2321 struct hwrm_func_cfg_input req = {0};
2322 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2325 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2326 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2327 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2328 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2329 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2330 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2331 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2332 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2333 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2334 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2335 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2336 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2337 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2338 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2339 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2340 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2341 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2342 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2343 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2344 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2345 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2346 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2347 req.fid = rte_cpu_to_le_16(0xffff);
2349 HWRM_PREP(req, FUNC_CFG);
2351 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2353 HWRM_CHECK_RESULT();
2359 static void populate_vf_func_cfg_req(struct bnxt *bp,
2360 struct hwrm_func_cfg_input *req,
2363 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2364 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2365 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2366 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2367 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2368 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2369 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2370 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2371 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2372 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2374 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2375 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2376 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2377 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2378 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2380 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2381 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2383 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2384 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2385 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2386 /* TODO: For now, do not support VMDq/RFS on VFs. */
2387 req->num_vnics = rte_cpu_to_le_16(1);
2388 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2392 static void add_random_mac_if_needed(struct bnxt *bp,
2393 struct hwrm_func_cfg_input *cfg_req,
2396 struct ether_addr mac;
2398 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2401 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2403 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2404 eth_random_addr(cfg_req->dflt_mac_addr);
2405 bp->pf.vf_info[vf].random_mac = true;
2407 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2411 static void reserve_resources_from_vf(struct bnxt *bp,
2412 struct hwrm_func_cfg_input *cfg_req,
2415 struct hwrm_func_qcaps_input req = {0};
2416 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2419 /* Get the actual allocated values now */
2420 HWRM_PREP(req, FUNC_QCAPS);
2421 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2422 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2425 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2426 copy_func_cfg_to_qcaps(cfg_req, resp);
2427 } else if (resp->error_code) {
2428 rc = rte_le_to_cpu_16(resp->error_code);
2429 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2430 copy_func_cfg_to_qcaps(cfg_req, resp);
2433 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2434 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2435 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2436 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2437 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2438 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2440 * TODO: While not supporting VMDq with VFs, max_vnics is always
2441 * forced to 1 in this case
2443 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2444 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2449 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2451 struct hwrm_func_qcfg_input req = {0};
2452 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2455 /* Check for zero MAC address */
2456 HWRM_PREP(req, FUNC_QCFG);
2457 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2458 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2460 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2462 } else if (resp->error_code) {
2463 rc = rte_le_to_cpu_16(resp->error_code);
2464 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2467 rc = rte_le_to_cpu_16(resp->vlan);
2474 static int update_pf_resource_max(struct bnxt *bp)
2476 struct hwrm_func_qcfg_input req = {0};
2477 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2480 /* And copy the allocated numbers into the pf struct */
2481 HWRM_PREP(req, FUNC_QCFG);
2482 req.fid = rte_cpu_to_le_16(0xffff);
2483 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2484 HWRM_CHECK_RESULT();
2486 /* Only TX ring value reflects actual allocation? TODO */
2487 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2488 bp->pf.evb_mode = resp->evb_mode;
2495 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2500 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2504 rc = bnxt_hwrm_func_qcaps(bp);
2508 bp->pf.func_cfg_flags &=
2509 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2510 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2511 bp->pf.func_cfg_flags |=
2512 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2513 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2517 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2519 struct hwrm_func_cfg_input req = {0};
2520 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2527 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2531 rc = bnxt_hwrm_func_qcaps(bp);
2536 bp->pf.active_vfs = num_vfs;
2539 * First, configure the PF to only use one TX ring. This ensures that
2540 * there are enough rings for all VFs.
2542 * If we don't do this, when we call func_alloc() later, we will lock
2543 * extra rings to the PF that won't be available during func_cfg() of
2546 * This has been fixed with firmware versions above 20.6.54
2548 bp->pf.func_cfg_flags &=
2549 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2550 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2551 bp->pf.func_cfg_flags |=
2552 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2553 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2558 * Now, create and register a buffer to hold forwarded VF requests
2560 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2561 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2562 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2563 if (bp->pf.vf_req_buf == NULL) {
2567 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2568 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2569 for (i = 0; i < num_vfs; i++)
2570 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2571 (i * HWRM_MAX_REQ_LEN);
2573 rc = bnxt_hwrm_func_buf_rgtr(bp);
2577 populate_vf_func_cfg_req(bp, &req, num_vfs);
2579 bp->pf.active_vfs = 0;
2580 for (i = 0; i < num_vfs; i++) {
2581 add_random_mac_if_needed(bp, &req, i);
2583 HWRM_PREP(req, FUNC_CFG);
2584 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2585 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2586 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2588 /* Clear enable flag for next pass */
2589 req.enables &= ~rte_cpu_to_le_32(
2590 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2592 if (rc || resp->error_code) {
2594 "Failed to initizlie VF %d\n", i);
2596 "Not all VFs available. (%d, %d)\n",
2597 rc, resp->error_code);
2604 reserve_resources_from_vf(bp, &req, i);
2605 bp->pf.active_vfs++;
2606 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2610 * Now configure the PF to use "the rest" of the resources
2611 * We're using STD_TX_RING_MODE here though which will limit the TX
2612 * rings. This will allow QoS to function properly. Not setting this
2613 * will cause PF rings to break bandwidth settings.
2615 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2619 rc = update_pf_resource_max(bp);
2626 bnxt_hwrm_func_buf_unrgtr(bp);
2630 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2632 struct hwrm_func_cfg_input req = {0};
2633 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2636 HWRM_PREP(req, FUNC_CFG);
2638 req.fid = rte_cpu_to_le_16(0xffff);
2639 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2640 req.evb_mode = bp->pf.evb_mode;
2642 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2643 HWRM_CHECK_RESULT();
2649 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2650 uint8_t tunnel_type)
2652 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2653 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2656 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC);
2657 req.tunnel_type = tunnel_type;
2658 req.tunnel_dst_port_val = port;
2659 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2660 HWRM_CHECK_RESULT();
2662 switch (tunnel_type) {
2663 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2664 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2665 bp->vxlan_port = port;
2667 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2668 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2669 bp->geneve_port = port;
2680 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2681 uint8_t tunnel_type)
2683 struct hwrm_tunnel_dst_port_free_input req = {0};
2684 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2687 HWRM_PREP(req, TUNNEL_DST_PORT_FREE);
2689 req.tunnel_type = tunnel_type;
2690 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2691 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2693 HWRM_CHECK_RESULT();
2699 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2702 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2703 struct hwrm_func_cfg_input req = {0};
2706 HWRM_PREP(req, FUNC_CFG);
2708 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2709 req.flags = rte_cpu_to_le_32(flags);
2710 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2712 HWRM_CHECK_RESULT();
2718 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2720 uint32_t *flag = flagp;
2722 vnic->flags = *flag;
2725 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2727 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2730 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2733 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2734 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2736 HWRM_PREP(req, FUNC_BUF_RGTR);
2738 req.req_buf_num_pages = rte_cpu_to_le_16(1);
2739 req.req_buf_page_size = rte_cpu_to_le_16(
2740 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2741 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2742 req.req_buf_page_addr[0] =
2743 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
2744 if (req.req_buf_page_addr[0] == 0) {
2746 "unable to map buffer address to physical memory\n");
2750 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2752 HWRM_CHECK_RESULT();
2758 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2761 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2762 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2764 HWRM_PREP(req, FUNC_BUF_UNRGTR);
2766 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2768 HWRM_CHECK_RESULT();
2774 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2776 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2777 struct hwrm_func_cfg_input req = {0};
2780 HWRM_PREP(req, FUNC_CFG);
2782 req.fid = rte_cpu_to_le_16(0xffff);
2783 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2784 req.enables = rte_cpu_to_le_32(
2785 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2786 req.async_event_cr = rte_cpu_to_le_16(
2787 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2788 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2790 HWRM_CHECK_RESULT();
2796 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2798 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2799 struct hwrm_func_vf_cfg_input req = {0};
2802 HWRM_PREP(req, FUNC_VF_CFG);
2804 req.enables = rte_cpu_to_le_32(
2805 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2806 req.async_event_cr = rte_cpu_to_le_16(
2807 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2808 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2810 HWRM_CHECK_RESULT();
2816 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2818 struct hwrm_func_cfg_input req = {0};
2819 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2820 uint16_t dflt_vlan, fid;
2821 uint32_t func_cfg_flags;
2824 HWRM_PREP(req, FUNC_CFG);
2827 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2828 fid = bp->pf.vf_info[vf].fid;
2829 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2831 fid = rte_cpu_to_le_16(0xffff);
2832 func_cfg_flags = bp->pf.func_cfg_flags;
2833 dflt_vlan = bp->vlan;
2836 req.flags = rte_cpu_to_le_32(func_cfg_flags);
2837 req.fid = rte_cpu_to_le_16(fid);
2838 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2839 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2841 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2843 HWRM_CHECK_RESULT();
2849 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2850 uint16_t max_bw, uint16_t enables)
2852 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2853 struct hwrm_func_cfg_input req = {0};
2856 HWRM_PREP(req, FUNC_CFG);
2858 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2859 req.enables |= rte_cpu_to_le_32(enables);
2860 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2861 req.max_bw = rte_cpu_to_le_32(max_bw);
2862 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2864 HWRM_CHECK_RESULT();
2870 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2872 struct hwrm_func_cfg_input req = {0};
2873 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2876 HWRM_PREP(req, FUNC_CFG);
2878 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2879 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2880 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2881 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2883 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2885 HWRM_CHECK_RESULT();
2891 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2892 void *encaped, size_t ec_size)
2895 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2896 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2898 if (ec_size > sizeof(req.encap_request))
2901 HWRM_PREP(req, REJECT_FWD_RESP);
2903 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2904 memcpy(req.encap_request, encaped, ec_size);
2906 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2908 HWRM_CHECK_RESULT();
2914 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2915 struct ether_addr *mac)
2917 struct hwrm_func_qcfg_input req = {0};
2918 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2921 HWRM_PREP(req, FUNC_QCFG);
2923 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2924 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2926 HWRM_CHECK_RESULT();
2928 memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2935 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2936 void *encaped, size_t ec_size)
2939 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2940 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2942 if (ec_size > sizeof(req.encap_request))
2945 HWRM_PREP(req, EXEC_FWD_RESP);
2947 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2948 memcpy(req.encap_request, encaped, ec_size);
2950 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2952 HWRM_CHECK_RESULT();
2958 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2959 struct rte_eth_stats *stats, uint8_t rx)
2962 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2963 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2965 HWRM_PREP(req, STAT_CTX_QUERY);
2967 req.stat_ctx_id = rte_cpu_to_le_32(cid);
2969 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2971 HWRM_CHECK_RESULT();
2974 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2975 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2976 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2977 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2978 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2979 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2980 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2981 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2983 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2984 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2985 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2986 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2987 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2988 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2989 stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
2998 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3000 struct hwrm_port_qstats_input req = {0};
3001 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3002 struct bnxt_pf_info *pf = &bp->pf;
3005 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
3008 HWRM_PREP(req, PORT_QSTATS);
3010 req.port_id = rte_cpu_to_le_16(pf->port_id);
3011 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3012 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3013 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3015 HWRM_CHECK_RESULT();
3021 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3023 struct hwrm_port_clr_stats_input req = {0};
3024 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3025 struct bnxt_pf_info *pf = &bp->pf;
3028 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
3031 HWRM_PREP(req, PORT_CLR_STATS);
3033 req.port_id = rte_cpu_to_le_16(pf->port_id);
3034 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3036 HWRM_CHECK_RESULT();
3042 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3044 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3045 struct hwrm_port_led_qcaps_input req = {0};
3051 HWRM_PREP(req, PORT_LED_QCAPS);
3052 req.port_id = bp->pf.port_id;
3053 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3055 HWRM_CHECK_RESULT();
3057 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3060 bp->num_leds = resp->num_leds;
3061 memcpy(bp->leds, &resp->led0_id,
3062 sizeof(bp->leds[0]) * bp->num_leds);
3063 for (i = 0; i < bp->num_leds; i++) {
3064 struct bnxt_led_info *led = &bp->leds[i];
3066 uint16_t caps = led->led_state_caps;
3068 if (!led->led_group_id ||
3069 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3081 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3083 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3084 struct hwrm_port_led_cfg_input req = {0};
3085 struct bnxt_led_cfg *led_cfg;
3086 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3087 uint16_t duration = 0;
3090 if (!bp->num_leds || BNXT_VF(bp))
3093 HWRM_PREP(req, PORT_LED_CFG);
3096 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3097 duration = rte_cpu_to_le_16(500);
3099 req.port_id = bp->pf.port_id;
3100 req.num_leds = bp->num_leds;
3101 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3102 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3103 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3104 led_cfg->led_id = bp->leds[i].led_id;
3105 led_cfg->led_state = led_state;
3106 led_cfg->led_blink_on = duration;
3107 led_cfg->led_blink_off = duration;
3108 led_cfg->led_group_id = bp->leds[i].led_group_id;
3111 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3113 HWRM_CHECK_RESULT();
3119 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3123 struct hwrm_nvm_get_dir_info_input req = {0};
3124 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3126 HWRM_PREP(req, NVM_GET_DIR_INFO);
3128 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3130 HWRM_CHECK_RESULT();
3134 *entries = rte_le_to_cpu_32(resp->entries);
3135 *length = rte_le_to_cpu_32(resp->entry_length);
3140 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3143 uint32_t dir_entries;
3144 uint32_t entry_length;
3147 rte_iova_t dma_handle;
3148 struct hwrm_nvm_get_dir_entries_input req = {0};
3149 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3151 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3155 *data++ = dir_entries;
3156 *data++ = entry_length;
3158 memset(data, 0xff, len);
3160 buflen = dir_entries * entry_length;
3161 buf = rte_malloc("nvm_dir", buflen, 0);
3162 rte_mem_lock_page(buf);
3165 dma_handle = rte_mem_virt2iova(buf);
3166 if (dma_handle == 0) {
3168 "unable to map response address to physical memory\n");
3171 HWRM_PREP(req, NVM_GET_DIR_ENTRIES);
3172 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3173 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3175 HWRM_CHECK_RESULT();
3179 memcpy(data, buf, len > buflen ? buflen : len);
3186 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3187 uint32_t offset, uint32_t length,
3192 rte_iova_t dma_handle;
3193 struct hwrm_nvm_read_input req = {0};
3194 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3196 buf = rte_malloc("nvm_item", length, 0);
3197 rte_mem_lock_page(buf);
3201 dma_handle = rte_mem_virt2iova(buf);
3202 if (dma_handle == 0) {
3204 "unable to map response address to physical memory\n");
3207 HWRM_PREP(req, NVM_READ);
3208 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3209 req.dir_idx = rte_cpu_to_le_16(index);
3210 req.offset = rte_cpu_to_le_32(offset);
3211 req.len = rte_cpu_to_le_32(length);
3212 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3213 HWRM_CHECK_RESULT();
3216 memcpy(data, buf, length);
3222 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3225 struct hwrm_nvm_erase_dir_entry_input req = {0};
3226 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3228 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY);
3229 req.dir_idx = rte_cpu_to_le_16(index);
3230 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3231 HWRM_CHECK_RESULT();
3238 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3239 uint16_t dir_ordinal, uint16_t dir_ext,
3240 uint16_t dir_attr, const uint8_t *data,
3244 struct hwrm_nvm_write_input req = {0};
3245 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3246 rte_iova_t dma_handle;
3249 HWRM_PREP(req, NVM_WRITE);
3251 req.dir_type = rte_cpu_to_le_16(dir_type);
3252 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3253 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3254 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3255 req.dir_data_length = rte_cpu_to_le_32(data_len);
3257 buf = rte_malloc("nvm_write", data_len, 0);
3258 rte_mem_lock_page(buf);
3262 dma_handle = rte_mem_virt2iova(buf);
3263 if (dma_handle == 0) {
3265 "unable to map response address to physical memory\n");
3268 memcpy(buf, data, data_len);
3269 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3271 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3273 HWRM_CHECK_RESULT();
3281 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3283 uint32_t *count = cbdata;
3285 *count = *count + 1;
3288 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3289 struct bnxt_vnic_info *vnic __rte_unused)
3294 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3298 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3299 &count, bnxt_vnic_count_hwrm_stub);
3304 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3307 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3308 struct hwrm_func_vf_vnic_ids_query_output *resp =
3309 bp->hwrm_cmd_resp_addr;
3312 /* First query all VNIC ids */
3313 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY);
3315 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3316 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3317 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3319 if (req.vnic_id_tbl_addr == 0) {
3322 "unable to map VNIC ID table address to physical memory\n");
3325 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3328 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3330 } else if (resp->error_code) {
3331 rc = rte_le_to_cpu_16(resp->error_code);
3333 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3336 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3344 * This function queries the VNIC IDs for a specified VF. It then calls
3345 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3346 * Then it calls the hwrm_cb function to program this new vnic configuration.
3348 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3349 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3350 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3352 struct bnxt_vnic_info vnic;
3354 int i, num_vnic_ids;
3359 /* First query all VNIC ids */
3360 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3361 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3362 RTE_CACHE_LINE_SIZE);
3363 if (vnic_ids == NULL) {
3367 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3368 rte_mem_lock_page(((char *)vnic_ids) + sz);
3370 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3372 if (num_vnic_ids < 0)
3373 return num_vnic_ids;
3375 /* Retrieve VNIC, update bd_stall then update */
3377 for (i = 0; i < num_vnic_ids; i++) {
3378 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3379 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3380 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3383 if (vnic.mru <= 4) /* Indicates unallocated */
3386 vnic_cb(&vnic, cbdata);
3388 rc = hwrm_cb(bp, &vnic);
3398 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3401 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3402 struct hwrm_func_cfg_input req = {0};
3405 HWRM_PREP(req, FUNC_CFG);
3407 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3408 req.enables |= rte_cpu_to_le_32(
3409 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3410 req.vlan_antispoof_mode = on ?
3411 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3412 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3413 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3415 HWRM_CHECK_RESULT();
3421 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3423 struct bnxt_vnic_info vnic;
3426 int num_vnic_ids, i;
3430 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3431 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3432 RTE_CACHE_LINE_SIZE);
3433 if (vnic_ids == NULL) {
3438 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3439 rte_mem_lock_page(((char *)vnic_ids) + sz);
3441 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3447 * Loop through to find the default VNIC ID.
3448 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3449 * by sending the hwrm_func_qcfg command to the firmware.
3451 for (i = 0; i < num_vnic_ids; i++) {
3452 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3453 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3454 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3455 bp->pf.first_vf_id + vf);
3458 if (vnic.func_default) {
3460 return vnic.fw_vnic_id;
3463 /* Could not find a default VNIC. */
3464 PMD_DRV_LOG(ERR, "No default VNIC\n");
3470 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3472 struct bnxt_filter_info *filter)
3475 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3476 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3477 uint32_t enables = 0;
3479 if (filter->fw_em_filter_id != UINT64_MAX)
3480 bnxt_hwrm_clear_em_filter(bp, filter);
3482 HWRM_PREP(req, CFA_EM_FLOW_ALLOC);
3484 req.flags = rte_cpu_to_le_32(filter->flags);
3486 enables = filter->enables |
3487 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3488 req.dst_id = rte_cpu_to_le_16(dst_id);
3490 if (filter->ip_addr_type) {
3491 req.ip_addr_type = filter->ip_addr_type;
3492 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3495 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3496 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3498 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3499 memcpy(req.src_macaddr, filter->src_macaddr,
3502 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3503 memcpy(req.dst_macaddr, filter->dst_macaddr,
3506 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3507 req.ovlan_vid = filter->l2_ovlan;
3509 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3510 req.ivlan_vid = filter->l2_ivlan;
3512 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3513 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3515 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3516 req.ip_protocol = filter->ip_protocol;
3518 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3519 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3521 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3522 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3524 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3525 req.src_port = rte_cpu_to_be_16(filter->src_port);
3527 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3528 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3530 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3531 req.mirror_vnic_id = filter->mirror_vnic_id;
3533 req.enables = rte_cpu_to_le_32(enables);
3535 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3537 HWRM_CHECK_RESULT();
3539 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3545 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3548 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3549 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3551 if (filter->fw_em_filter_id == UINT64_MAX)
3554 PMD_DRV_LOG(ERR, "Clear EM filter\n");
3555 HWRM_PREP(req, CFA_EM_FLOW_FREE);
3557 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3559 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3561 HWRM_CHECK_RESULT();
3564 filter->fw_em_filter_id = -1;
3565 filter->fw_l2_filter_id = -1;
3570 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3572 struct bnxt_filter_info *filter)
3575 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3576 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3577 bp->hwrm_cmd_resp_addr;
3578 uint32_t enables = 0;
3580 if (filter->fw_ntuple_filter_id != UINT64_MAX)
3581 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3583 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC);
3585 req.flags = rte_cpu_to_le_32(filter->flags);
3587 enables = filter->enables |
3588 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3589 req.dst_id = rte_cpu_to_le_16(dst_id);
3592 if (filter->ip_addr_type) {
3593 req.ip_addr_type = filter->ip_addr_type;
3595 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3598 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3599 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3601 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3602 memcpy(req.src_macaddr, filter->src_macaddr,
3605 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3606 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3609 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3610 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3612 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3613 req.ip_protocol = filter->ip_protocol;
3615 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3616 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3618 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3619 req.src_ipaddr_mask[0] =
3620 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3622 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3623 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3625 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3626 req.dst_ipaddr_mask[0] =
3627 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3629 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3630 req.src_port = rte_cpu_to_le_16(filter->src_port);
3632 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3633 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3635 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3636 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3638 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3639 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3641 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3642 req.mirror_vnic_id = filter->mirror_vnic_id;
3644 req.enables = rte_cpu_to_le_32(enables);
3646 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3648 HWRM_CHECK_RESULT();
3650 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
3656 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
3657 struct bnxt_filter_info *filter)
3660 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
3661 struct hwrm_cfa_ntuple_filter_free_output *resp =
3662 bp->hwrm_cmd_resp_addr;
3664 if (filter->fw_ntuple_filter_id == UINT64_MAX)
3667 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE);
3669 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
3671 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3673 HWRM_CHECK_RESULT();
3676 filter->fw_ntuple_filter_id = -1;
3681 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3683 unsigned int rss_idx, fw_idx, i;
3685 if (vnic->rss_table && vnic->hash_type) {
3687 * Fill the RSS hash & redirection table with
3688 * ring group ids for all VNICs
3690 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
3691 rss_idx++, fw_idx++) {
3692 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
3693 fw_idx %= bp->rx_cp_nr_rings;
3694 if (vnic->fw_grp_ids[fw_idx] !=
3699 if (i == bp->rx_cp_nr_rings)
3701 vnic->rss_table[rss_idx] =
3702 vnic->fw_grp_ids[fw_idx];
3704 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);