drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         timeout = bp->hwrm_cmd_timeout;
 104
 105         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 106             msg_len > bp->max_req_len) {
 107                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 108
 109                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 110                 memcpy(short_cmd_req, req, msg_len);
 111
 112                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 113                 short_input.signature = rte_cpu_to_le_16(
 114                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 115                 short_input.size = rte_cpu_to_le_16(msg_len);
 116                 short_input.req_addr =
 117                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 118
 119                 data = (uint32_t *)&short_input;
 120                 msg_len = sizeof(short_input);
 121
 122                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 123         }
 124
 125         /* Write request msg to hwrm channel */
 126         for (i = 0; i < msg_len; i += 4) {
 127                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 128                 rte_write32(*data, bar);
 129                 data++;
 130         }
 131
 132         /* Zero the rest of the request space */
 133         for (; i < max_req_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 135                 rte_write32(0, bar);
 136         }
 137
 138         /* Ring channel doorbell */
 139         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 140         rte_write32(1, bar);
 141         /*
 142          * Make sure the channel doorbell ring command complete before
 143          * reading the response to avoid getting stale or invalid
 144          * responses.
 145          */
 146         rte_io_mb();
 147
 148         /* Poll for the valid bit */
 149         for (i = 0; i < timeout; i++) {
 150                 /* Sanity check on the resp->resp_len */
 151                 rte_cio_rmb();
 152                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 153                         /* Last byte of resp contains the valid key */
 154                         valid = (uint8_t *)resp + resp->resp_len - 1;
 155                         if (*valid == HWRM_RESP_VALID_KEY)
 156                                 break;
 157                 }
 158                 rte_delay_us(1);
 159         }
 160
 161         if (i >= timeout) {
 162                 /* Suppress VER_GET timeout messages during reset recovery */
 163                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 164                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 165                         return -ETIMEDOUT;
 166
 167                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 168                             req->req_type);
 169                 return -ETIMEDOUT;
 170         }
 171         return 0;
 172 }
 173
 174 /*
 175  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 176  * spinlock, and does initial processing.
 177  *
 178  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 179  * releases the spinlock only if it returns. If the regular int return codes
 180  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 181  * directly, rather it should be copied and modified to suit the function.
 182  *
 183  * HWRM_UNLOCK() must be called after all response processing is completed.
 184  */
 185 #define HWRM_PREP(req, type, kong) do { \
 186         rte_spinlock_lock(&bp->hwrm_lock); \
 187         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 188         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 189         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 190         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 191                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 192         req.target_id = rte_cpu_to_le_16(0xffff); \
 193         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 194 } while (0)
 195
 196 #define HWRM_CHECK_RESULT_SILENT() do {\
 197         if (rc) { \
 198                 rte_spinlock_unlock(&bp->hwrm_lock); \
 199                 return rc; \
 200         } \
 201         if (resp->error_code) { \
 202                 rc = rte_le_to_cpu_16(resp->error_code); \
 203                 rte_spinlock_unlock(&bp->hwrm_lock); \
 204                 return rc; \
 205         } \
 206 } while (0)
 207
 208 #define HWRM_CHECK_RESULT() do {\
 209         if (rc) { \
 210                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 211                 rte_spinlock_unlock(&bp->hwrm_lock); \
 212                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 213                         rc = -EACCES; \
 214                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 215                         rc = -ENOSPC; \
 216                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 217                         rc = -EINVAL; \
 218                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 219                         rc = -ENOTSUP; \
 220                 else if (rc > 0) \
 221                         rc = -EIO; \
 222                 return rc; \
 223         } \
 224         if (resp->error_code) { \
 225                 rc = rte_le_to_cpu_16(resp->error_code); \
 226                 if (resp->resp_len >= 16) { \
 227                         struct hwrm_err_output *tmp_hwrm_err_op = \
 228                                                 (void *)resp; \
 229                         PMD_DRV_LOG(ERR, \
 230                                 "error %d:%d:%08x:%04x\n", \
 231                                 rc, tmp_hwrm_err_op->cmd_err, \
 232                                 rte_le_to_cpu_32(\
 233                                         tmp_hwrm_err_op->opaque_0), \
 234                                 rte_le_to_cpu_16(\
 235                                         tmp_hwrm_err_op->opaque_1)); \
 236                 } else { \
 237                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 238                 } \
 239                 rte_spinlock_unlock(&bp->hwrm_lock); \
 240                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 241                         rc = -EACCES; \
 242                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 243                         rc = -ENOSPC; \
 244                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 245                         rc = -EINVAL; \
 246                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 247                         rc = -ENOTSUP; \
 248                 else if (rc > 0) \
 249                         rc = -EIO; \
 250                 return rc; \
 251         } \
 252 } while (0)
 253
 254 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 255
 256 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 257 {
 258         int rc = 0;
 259         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 260         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 261
 262         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 263         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 264         req.mask = 0;
 265
 266         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 267
 268         HWRM_CHECK_RESULT();
 269         HWRM_UNLOCK();
 270
 271         return rc;
 272 }
 273
 274 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 275                                  struct bnxt_vnic_info *vnic,
 276                                  uint16_t vlan_count,
 277                                  struct bnxt_vlan_table_entry *vlan_table)
 278 {
 279         int rc = 0;
 280         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 281         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 282         uint32_t mask = 0;
 283
 284         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 285                 return rc;
 286
 287         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 288         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 289
 290         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 291                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 292         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 293                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 294
 295         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 296                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 297
 298         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 299                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 300         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 301                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 302                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 303                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 304         }
 305         if (vlan_table) {
 306                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 307                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 308                 req.vlan_tag_tbl_addr =
 309                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 310                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 311         }
 312         req.mask = rte_cpu_to_le_32(mask);
 313
 314         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 315
 316         HWRM_CHECK_RESULT();
 317         HWRM_UNLOCK();
 318
 319         return rc;
 320 }
 321
 322 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 323                         uint16_t vlan_count,
 324                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 325 {
 326         int rc = 0;
 327         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 328         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 329                                                 bp->hwrm_cmd_resp_addr;
 330
 331         /*
 332          * Older HWRM versions did not support this command, and the set_rx_mask
 333          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 334          * removed from set_rx_mask call, and this command was added.
 335          *
 336          * This command is also present from 1.7.8.11 and higher,
 337          * as well as 1.7.8.0
 338          */
 339         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 340                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 341                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 342                                         (11)))
 343                                 return 0;
 344                 }
 345         }
 346         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 347         req.fid = rte_cpu_to_le_16(fid);
 348
 349         req.vlan_tag_mask_tbl_addr =
 350                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 351         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 352
 353         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 354
 355         HWRM_CHECK_RESULT();
 356         HWRM_UNLOCK();
 357
 358         return rc;
 359 }
 360
 361 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 362                              struct bnxt_filter_info *filter)
 363 {
 364         int rc = 0;
 365         struct bnxt_filter_info *l2_filter = filter;
 366         struct bnxt_vnic_info *vnic = NULL;
 367         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 368         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 369
 370         if (filter->fw_l2_filter_id == UINT64_MAX)
 371                 return 0;
 372
 373         if (filter->matching_l2_fltr_ptr)
 374                 l2_filter = filter->matching_l2_fltr_ptr;
 375
 376         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 377                     filter, l2_filter, l2_filter->l2_ref_cnt);
 378
 379         if (l2_filter->l2_ref_cnt == 0)
 380                 return 0;
 381
 382         if (l2_filter->l2_ref_cnt > 0)
 383                 l2_filter->l2_ref_cnt--;
 384
 385         if (l2_filter->l2_ref_cnt > 0)
 386                 return 0;
 387
 388         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 389
 390         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 391
 392         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 393
 394         HWRM_CHECK_RESULT();
 395         HWRM_UNLOCK();
 396
 397         filter->fw_l2_filter_id = UINT64_MAX;
 398         if (l2_filter->l2_ref_cnt == 0) {
 399                 vnic = l2_filter->vnic;
 400                 if (vnic) {
 401                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 402                                       bnxt_filter_info, next);
 403                         bnxt_free_filter(bp, l2_filter);
 404                 }
 405         }
 406
 407         return 0;
 408 }
 409
 410 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 411                          uint16_t dst_id,
 412                          struct bnxt_filter_info *filter)
 413 {
 414         int rc = 0;
 415         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 416         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 417         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 418         const struct rte_eth_vmdq_rx_conf *conf =
 419                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 420         uint32_t enables = 0;
 421         uint16_t j = dst_id - 1;
 422
 423         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 424         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 425             conf->pool_map[j].pools & (1UL << j)) {
 426                 PMD_DRV_LOG(DEBUG,
 427                         "Add vlan %u to vmdq pool %u\n",
 428                         conf->pool_map[j].vlan_id, j);
 429
 430                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 431                 filter->enables |=
 432                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 433                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 434         }
 435
 436         if (filter->fw_l2_filter_id != UINT64_MAX)
 437                 bnxt_hwrm_clear_l2_filter(bp, filter);
 438
 439         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 440
 441         req.flags = rte_cpu_to_le_32(filter->flags);
 442
 443         enables = filter->enables |
 444               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 445         req.dst_id = rte_cpu_to_le_16(dst_id);
 446
 447         if (enables &
 448             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 449                 memcpy(req.l2_addr, filter->l2_addr,
 450                        RTE_ETHER_ADDR_LEN);
 451         if (enables &
 452             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 453                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 454                        RTE_ETHER_ADDR_LEN);
 455         if (enables &
 456             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 457                 req.l2_ovlan = filter->l2_ovlan;
 458         if (enables &
 459             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 460                 req.l2_ivlan = filter->l2_ivlan;
 461         if (enables &
 462             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 463                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 464         if (enables &
 465             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 466                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 467         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 468                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 469         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 470                 req.src_type = filter->src_type;
 471         if (filter->pri_hint) {
 472                 req.pri_hint = filter->pri_hint;
 473                 req.l2_filter_id_hint =
 474                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 475         }
 476
 477         req.enables = rte_cpu_to_le_32(enables);
 478
 479         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 480
 481         HWRM_CHECK_RESULT();
 482
 483         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 484         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 485         HWRM_UNLOCK();
 486
 487         filter->l2_ref_cnt++;
 488
 489         return rc;
 490 }
 491
 492 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 493 {
 494         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 495         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 496         uint32_t flags = 0;
 497         int rc;
 498
 499         if (!ptp)
 500                 return 0;
 501
 502         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 503
 504         if (ptp->rx_filter)
 505                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 506         else
 507                 flags |=
 508                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 509         if (ptp->tx_tstamp_en)
 510                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 511         else
 512                 flags |=
 513                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 514         req.flags = rte_cpu_to_le_32(flags);
 515         req.enables = rte_cpu_to_le_32
 516                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 517         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 518
 519         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 520         HWRM_UNLOCK();
 521
 522         return rc;
 523 }
 524
 525 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 526 {
 527         int rc = 0;
 528         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 529         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 530         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 531
 532         if (ptp)
 533                 return 0;
 534
 535         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 536
 537         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 538
 539         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 540
 541         HWRM_CHECK_RESULT();
 542
 543         if (!BNXT_CHIP_THOR(bp) &&
 544             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 545                 return 0;
 546
 547         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 548                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 549
 550         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 551         if (!ptp)
 552                 return -ENOMEM;
 553
 554         if (!BNXT_CHIP_THOR(bp)) {
 555                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 556                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 557                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 558                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 559                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 560                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 561                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 562                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 563                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 564                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 565                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 566                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 567                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 568                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 569                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 570                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 571                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 572                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 573         }
 574
 575         ptp->bp = bp;
 576         bp->ptp_cfg = ptp;
 577
 578         return 0;
 579 }
 580
 581 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 582 {
 583         int rc = 0;
 584         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 585         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 586         uint16_t new_max_vfs;
 587         uint32_t flags;
 588         int i;
 589
 590         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 591
 592         req.fid = rte_cpu_to_le_16(0xffff);
 593
 594         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 595
 596         HWRM_CHECK_RESULT();
 597
 598         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 599         flags = rte_le_to_cpu_32(resp->flags);
 600         if (BNXT_PF(bp)) {
 601                 bp->pf.port_id = resp->port_id;
 602                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 603                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 604                 new_max_vfs = bp->pdev->max_vfs;
 605                 if (new_max_vfs != bp->pf.max_vfs) {
 606                         if (bp->pf.vf_info)
 607                                 rte_free(bp->pf.vf_info);
 608                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 609                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 610                         bp->pf.max_vfs = new_max_vfs;
 611                         for (i = 0; i < new_max_vfs; i++) {
 612                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 613                                 bp->pf.vf_info[i].vlan_table =
 614                                         rte_zmalloc("VF VLAN table",
 615                                                     getpagesize(),
 616                                                     getpagesize());
 617                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 618                                         PMD_DRV_LOG(ERR,
 619                                         "Fail to alloc VLAN table for VF %d\n",
 620                                         i);
 621                                 else
 622                                         rte_mem_lock_page(
 623                                                 bp->pf.vf_info[i].vlan_table);
 624                                 bp->pf.vf_info[i].vlan_as_table =
 625                                         rte_zmalloc("VF VLAN AS table",
 626                                                     getpagesize(),
 627                                                     getpagesize());
 628                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 629                                         PMD_DRV_LOG(ERR,
 630                                         "Alloc VLAN AS table for VF %d fail\n",
 631                                         i);
 632                                 else
 633                                         rte_mem_lock_page(
 634                                                bp->pf.vf_info[i].vlan_as_table);
 635                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 636                         }
 637                 }
 638         }
 639
 640         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 641         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 642         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 643         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 644         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 645         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 646         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 647         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 648         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 649         if (!BNXT_CHIP_THOR(bp))
 650                 bp->max_l2_ctx += bp->max_rx_em_flows;
 651         /* TODO: For now, do not support VMDq/RFS on VFs. */
 652         if (BNXT_PF(bp)) {
 653                 if (bp->pf.max_vfs)
 654                         bp->max_vnics = 1;
 655                 else
 656                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 657         } else {
 658                 bp->max_vnics = 1;
 659         }
 660         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 661         if (BNXT_PF(bp)) {
 662                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 663                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 664                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 665                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 666                         HWRM_UNLOCK();
 667                         bnxt_hwrm_ptp_qcfg(bp);
 668                 }
 669         }
 670
 671         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 672                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 673
 674         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 675                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 676                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 677         }
 678
 679         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 680                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 681
 682         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 683                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 684
 685         HWRM_UNLOCK();
 686
 687         return rc;
 688 }
 689
 690 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 691 {
 692         int rc;
 693
 694         rc = __bnxt_hwrm_func_qcaps(bp);
 695         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 696                 rc = bnxt_alloc_ctx_mem(bp);
 697                 if (rc)
 698                         return rc;
 699
 700                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 701                 if (!rc)
 702                         bp->flags |= BNXT_FLAG_NEW_RM;
 703         }
 704
 705         /* On older FW,
 706          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 707          * But the error can be ignored. Return success.
 708          */
 709
 710         return 0;
 711 }
 712
 713 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 714 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 715 {
 716         int rc = 0;
 717         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 718         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 719
 720         HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 721
 722         req.target_id = rte_cpu_to_le_16(0xffff);
 723
 724         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 725
 726         HWRM_CHECK_RESULT();
 727
 728         if (rte_le_to_cpu_32(resp->flags) &
 729             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 730                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 731                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 732         }
 733
 734         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 735
 736         HWRM_UNLOCK();
 737
 738         return rc;
 739 }
 740
 741 int bnxt_hwrm_func_reset(struct bnxt *bp)
 742 {
 743         int rc = 0;
 744         struct hwrm_func_reset_input req = {.req_type = 0 };
 745         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 746
 747         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 748
 749         req.enables = rte_cpu_to_le_32(0);
 750
 751         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 752
 753         HWRM_CHECK_RESULT();
 754         HWRM_UNLOCK();
 755
 756         return rc;
 757 }
 758
 759 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 760 {
 761         int rc;
 762         uint32_t flags = 0;
 763         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 764         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 765
 766         if (bp->flags & BNXT_FLAG_REGISTERED)
 767                 return 0;
 768
 769         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 770                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 771         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 772                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 773
 774         /* PFs and trusted VFs should indicate the support of the
 775          * Master capability on non Stingray platform
 776          */
 777         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 778                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 779
 780         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 781         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 782                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 783         req.ver_maj = RTE_VER_YEAR;
 784         req.ver_min = RTE_VER_MONTH;
 785         req.ver_upd = RTE_VER_MINOR;
 786
 787         if (BNXT_PF(bp)) {
 788                 req.enables |= rte_cpu_to_le_32(
 789                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 790                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 791                        RTE_MIN(sizeof(req.vf_req_fwd),
 792                                sizeof(bp->pf.vf_req_fwd)));
 793
 794                 /*
 795                  * PF can sniff HWRM API issued by VF. This can be set up by
 796                  * linux driver and inherited by the DPDK PF driver. Clear
 797                  * this HWRM sniffer list in FW because DPDK PF driver does
 798                  * not support this.
 799                  */
 800                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 801         }
 802
 803         req.flags = rte_cpu_to_le_32(flags);
 804
 805         req.async_event_fwd[0] |=
 806                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 807                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 808                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 809                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 810                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 811         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 812                 req.async_event_fwd[0] |=
 813                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 814         req.async_event_fwd[1] |=
 815                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 816                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 817
 818         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 819
 820         HWRM_CHECK_RESULT();
 821
 822         flags = rte_le_to_cpu_32(resp->flags);
 823         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 824                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 825
 826         HWRM_UNLOCK();
 827
 828         bp->flags |= BNXT_FLAG_REGISTERED;
 829
 830         return rc;
 831 }
 832
 833 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 834 {
 835         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 836                 return 0;
 837
 838         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 839 }
 840
 841 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 842 {
 843         int rc;
 844         uint32_t flags = 0;
 845         uint32_t enables;
 846         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 847         struct hwrm_func_vf_cfg_input req = {0};
 848
 849         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 850
 851         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 852                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 853                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 854                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 855                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 856
 857         if (BNXT_HAS_RING_GRPS(bp)) {
 858                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 859                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 860         }
 861
 862         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 863         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 864                                             AGG_RING_MULTIPLIER);
 865         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 866         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 867                                               bp->tx_nr_rings +
 868                                               BNXT_NUM_ASYNC_CPR(bp));
 869         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 870         if (bp->vf_resv_strategy ==
 871             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 872                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 873                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 874                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 875                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 876                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 877                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 878         } else if (bp->vf_resv_strategy ==
 879                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 880                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 881                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 882         }
 883
 884         if (test)
 885                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 886                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 887                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 888                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 889                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 890                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 891
 892         if (test && BNXT_HAS_RING_GRPS(bp))
 893                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 894
 895         req.flags = rte_cpu_to_le_32(flags);
 896         req.enables |= rte_cpu_to_le_32(enables);
 897
 898         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 899
 900         if (test)
 901                 HWRM_CHECK_RESULT_SILENT();
 902         else
 903                 HWRM_CHECK_RESULT();
 904
 905         HWRM_UNLOCK();
 906         return rc;
 907 }
 908
 909 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 910 {
 911         int rc;
 912         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 913         struct hwrm_func_resource_qcaps_input req = {0};
 914
 915         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 916         req.fid = rte_cpu_to_le_16(0xffff);
 917
 918         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 919
 920         HWRM_CHECK_RESULT_SILENT();
 921
 922         if (BNXT_VF(bp)) {
 923                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 924                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 925                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 926                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 927                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 928                 /* func_resource_qcaps does not return max_rx_em_flows.
 929                  * So use the value provided by func_qcaps.
 930                  */
 931                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 932                 if (!BNXT_CHIP_THOR(bp))
 933                         bp->max_l2_ctx += bp->max_rx_em_flows;
 934                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 935                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 936         }
 937         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 938         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 939         if (bp->vf_resv_strategy >
 940             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 941                 bp->vf_resv_strategy =
 942                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 943
 944         HWRM_UNLOCK();
 945         return rc;
 946 }
 947
 948 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
 949 {
 950         int rc = 0;
 951         struct hwrm_ver_get_input req = {.req_type = 0 };
 952         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 953         uint32_t fw_version;
 954         uint16_t max_resp_len;
 955         char type[RTE_MEMZONE_NAMESIZE];
 956         uint32_t dev_caps_cfg;
 957
 958         bp->max_req_len = HWRM_MAX_REQ_LEN;
 959         bp->hwrm_cmd_timeout = timeout;
 960         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 961
 962         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 963         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 964         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 965
 966         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 967
 968         if (bp->flags & BNXT_FLAG_FW_RESET)
 969                 HWRM_CHECK_RESULT_SILENT();
 970         else
 971                 HWRM_CHECK_RESULT();
 972
 973         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 974                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 975                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 976                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 977         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 978                      (resp->hwrm_fw_min_8b << 16) |
 979                      (resp->hwrm_fw_bld_8b << 8) |
 980                      resp->hwrm_fw_rsvd_8b;
 981         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 982                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 983
 984         fw_version = resp->hwrm_intf_maj_8b << 16;
 985         fw_version |= resp->hwrm_intf_min_8b << 8;
 986         fw_version |= resp->hwrm_intf_upd_8b;
 987         bp->hwrm_spec_code = fw_version;
 988
 989         /* def_req_timeout value is in milliseconds */
 990         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
 991         /* convert timeout to usec */
 992         bp->hwrm_cmd_timeout *= 1000;
 993         if (!bp->hwrm_cmd_timeout)
 994                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
 995
 996         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 997                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 998                 rc = -EINVAL;
 999                 goto error;
1000         }
1001
1002         if (bp->max_req_len > resp->max_req_win_len) {
1003                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1004                 rc = -EINVAL;
1005         }
1006         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1007         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1008         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1009                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1010
1011         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1012         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1013
1014         if (bp->max_resp_len != max_resp_len) {
1015                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
1016                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1017                         bp->pdev->addr.devid, bp->pdev->addr.function);
1018
1019                 rte_free(bp->hwrm_cmd_resp_addr);
1020
1021                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1022                 if (bp->hwrm_cmd_resp_addr == NULL) {
1023                         rc = -ENOMEM;
1024                         goto error;
1025                 }
1026                 bp->hwrm_cmd_resp_dma_addr =
1027                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1028                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1029                         PMD_DRV_LOG(ERR,
1030                         "Unable to map response buffer to physical memory.\n");
1031                         rc = -ENOMEM;
1032                         goto error;
1033                 }
1034                 bp->max_resp_len = max_resp_len;
1035         }
1036
1037         if ((dev_caps_cfg &
1038                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1039             (dev_caps_cfg &
1040              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1041                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1042                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1043         }
1044
1045         if (((dev_caps_cfg &
1046               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1047              (dev_caps_cfg &
1048               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1049             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1050                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1051                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1052                         bp->pdev->addr.devid, bp->pdev->addr.function);
1053
1054                 rte_free(bp->hwrm_short_cmd_req_addr);
1055
1056                 bp->hwrm_short_cmd_req_addr =
1057                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1058                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1059                         rc = -ENOMEM;
1060                         goto error;
1061                 }
1062                 bp->hwrm_short_cmd_req_dma_addr =
1063                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1064                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1065                         rte_free(bp->hwrm_short_cmd_req_addr);
1066                         PMD_DRV_LOG(ERR,
1067                                 "Unable to map buffer to physical memory.\n");
1068                         rc = -ENOMEM;
1069                         goto error;
1070                 }
1071         }
1072         if (dev_caps_cfg &
1073             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1074                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1075                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1076         }
1077         if (dev_caps_cfg &
1078             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1079                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1080         if (dev_caps_cfg &
1081             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1082                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1083                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1084         }
1085
1086 error:
1087         HWRM_UNLOCK();
1088         return rc;
1089 }
1090
1091 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1092 {
1093         int rc;
1094         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1095         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1096
1097         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1098                 return 0;
1099
1100         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1101         req.flags = flags;
1102
1103         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1104
1105         HWRM_CHECK_RESULT();
1106         HWRM_UNLOCK();
1107
1108         return rc;
1109 }
1110
1111 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1112 {
1113         int rc = 0;
1114         struct hwrm_port_phy_cfg_input req = {0};
1115         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1116         uint32_t enables = 0;
1117
1118         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1119
1120         if (conf->link_up) {
1121                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1122                 if (bp->link_info.auto_mode && conf->link_speed) {
1123                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1124                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1125                 }
1126
1127                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1128                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1129                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1130                 /*
1131                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1132                  * any auto mode, even "none".
1133                  */
1134                 if (!conf->link_speed) {
1135                         /* No speeds specified. Enable AutoNeg - all speeds */
1136                         req.auto_mode =
1137                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1138                 }
1139                 /* AutoNeg - Advertise speeds specified. */
1140                 if (conf->auto_link_speed_mask &&
1141                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1142                         req.auto_mode =
1143                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1144                         req.auto_link_speed_mask =
1145                                 conf->auto_link_speed_mask;
1146                         enables |=
1147                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1148                 }
1149
1150                 req.auto_duplex = conf->duplex;
1151                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1152                 req.auto_pause = conf->auto_pause;
1153                 req.force_pause = conf->force_pause;
1154                 /* Set force_pause if there is no auto or if there is a force */
1155                 if (req.auto_pause && !req.force_pause)
1156                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1157                 else
1158                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1159
1160                 req.enables = rte_cpu_to_le_32(enables);
1161         } else {
1162                 req.flags =
1163                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1164                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1165         }
1166
1167         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1168
1169         HWRM_CHECK_RESULT();
1170         HWRM_UNLOCK();
1171
1172         return rc;
1173 }
1174
1175 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1176                                    struct bnxt_link_info *link_info)
1177 {
1178         int rc = 0;
1179         struct hwrm_port_phy_qcfg_input req = {0};
1180         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1181
1182         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1183
1184         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1185
1186         HWRM_CHECK_RESULT();
1187
1188         link_info->phy_link_status = resp->link;
1189         link_info->link_up =
1190                 (link_info->phy_link_status ==
1191                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1192         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1193         link_info->duplex = resp->duplex_cfg;
1194         link_info->pause = resp->pause;
1195         link_info->auto_pause = resp->auto_pause;
1196         link_info->force_pause = resp->force_pause;
1197         link_info->auto_mode = resp->auto_mode;
1198         link_info->phy_type = resp->phy_type;
1199         link_info->media_type = resp->media_type;
1200
1201         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1202         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1203         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1204         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1205         link_info->phy_ver[0] = resp->phy_maj;
1206         link_info->phy_ver[1] = resp->phy_min;
1207         link_info->phy_ver[2] = resp->phy_bld;
1208
1209         HWRM_UNLOCK();
1210
1211         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1212         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1213         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1214         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1215         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1216                     link_info->auto_link_speed_mask);
1217         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1218                     link_info->force_link_speed);
1219
1220         return rc;
1221 }
1222
1223 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1224 {
1225         int i = 0;
1226
1227         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1228                 if (bp->tx_cos_queue[i].profile ==
1229                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1230                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1231                         return true;
1232                 }
1233         }
1234         return false;
1235 }
1236
1237 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1238 {
1239         int i = 0;
1240
1241         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1242                 if (bp->tx_cos_queue[i].profile !=
1243                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1244                     bp->tx_cos_queue[i].id !=
1245                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1246                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1247                         break;
1248                 }
1249         }
1250 }
1251
1252 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1253 {
1254         int rc = 0;
1255         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1256         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1257         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1258         int i;
1259
1260 get_rx_info:
1261         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1262
1263         req.flags = rte_cpu_to_le_32(dir);
1264         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1265         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1266             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1267                 req.drv_qmap_cap =
1268                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1269         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1270
1271         HWRM_CHECK_RESULT();
1272
1273         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1274                 GET_TX_QUEUE_INFO(0);
1275                 GET_TX_QUEUE_INFO(1);
1276                 GET_TX_QUEUE_INFO(2);
1277                 GET_TX_QUEUE_INFO(3);
1278                 GET_TX_QUEUE_INFO(4);
1279                 GET_TX_QUEUE_INFO(5);
1280                 GET_TX_QUEUE_INFO(6);
1281                 GET_TX_QUEUE_INFO(7);
1282         } else  {
1283                 GET_RX_QUEUE_INFO(0);
1284                 GET_RX_QUEUE_INFO(1);
1285                 GET_RX_QUEUE_INFO(2);
1286                 GET_RX_QUEUE_INFO(3);
1287                 GET_RX_QUEUE_INFO(4);
1288                 GET_RX_QUEUE_INFO(5);
1289                 GET_RX_QUEUE_INFO(6);
1290                 GET_RX_QUEUE_INFO(7);
1291         }
1292
1293         HWRM_UNLOCK();
1294
1295         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1296                 goto done;
1297
1298         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1299                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1300         } else {
1301                 int j;
1302
1303                 /* iterate and find the COSq profile to use for Tx */
1304                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1305                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1306                                 if (bp->tx_cos_queue[i].id != 0xff)
1307                                         bp->tx_cosq_id[j++] =
1308                                                 bp->tx_cos_queue[i].id;
1309                         }
1310                 } else {
1311                         /* When CoS classification is disabled, for normal NIC
1312                          * operations, ideally we should look to use LOSSY.
1313                          * If not found, fallback to the first valid profile
1314                          */
1315                         if (!bnxt_find_lossy_profile(bp))
1316                                 bnxt_find_first_valid_profile(bp);
1317
1318                 }
1319         }
1320
1321         bp->max_tc = resp->max_configurable_queues;
1322         bp->max_lltc = resp->max_configurable_lossless_queues;
1323         if (bp->max_tc > BNXT_MAX_QUEUE)
1324                 bp->max_tc = BNXT_MAX_QUEUE;
1325         bp->max_q = bp->max_tc;
1326
1327         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1328                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1329                 goto get_rx_info;
1330         }
1331
1332 done:
1333         return rc;
1334 }
1335
1336 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1337                          struct bnxt_ring *ring,
1338                          uint32_t ring_type, uint32_t map_index,
1339                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1340                          uint16_t tx_cosq_id)
1341 {
1342         int rc = 0;
1343         uint32_t enables = 0;
1344         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1345         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1346         struct rte_mempool *mb_pool;
1347         uint16_t rx_buf_size;
1348
1349         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1350
1351         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1352         req.fbo = rte_cpu_to_le_32(0);
1353         /* Association of ring index with doorbell index */
1354         req.logical_id = rte_cpu_to_le_16(map_index);
1355         req.length = rte_cpu_to_le_32(ring->ring_size);
1356
1357         switch (ring_type) {
1358         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1359                 req.ring_type = ring_type;
1360                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1361                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1362                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1363                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1364                         enables |=
1365                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1366                 break;
1367         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1368                 req.ring_type = ring_type;
1369                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1370                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1371                 if (BNXT_CHIP_THOR(bp)) {
1372                         mb_pool = bp->rx_queues[0]->mb_pool;
1373                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1374                                       RTE_PKTMBUF_HEADROOM;
1375                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1376                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1377                         enables |=
1378                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1379                 }
1380                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1381                         enables |=
1382                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1383                 break;
1384         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1385                 req.ring_type = ring_type;
1386                 if (BNXT_HAS_NQ(bp)) {
1387                         /* Association of cp ring with nq */
1388                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1389                         enables |=
1390                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1391                 }
1392                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1393                 break;
1394         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1395                 req.ring_type = ring_type;
1396                 req.page_size = BNXT_PAGE_SHFT;
1397                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1398                 break;
1399         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1400                 req.ring_type = ring_type;
1401                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1402
1403                 mb_pool = bp->rx_queues[0]->mb_pool;
1404                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1405                               RTE_PKTMBUF_HEADROOM;
1406                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1407                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1408
1409                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1410                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1411                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1412                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1413                 break;
1414         default:
1415                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1416                         ring_type);
1417                 HWRM_UNLOCK();
1418                 return -EINVAL;
1419         }
1420         req.enables = rte_cpu_to_le_32(enables);
1421
1422         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1423
1424         if (rc || resp->error_code) {
1425                 if (rc == 0 && resp->error_code)
1426                         rc = rte_le_to_cpu_16(resp->error_code);
1427                 switch (ring_type) {
1428                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1429                         PMD_DRV_LOG(ERR,
1430                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1431                         HWRM_UNLOCK();
1432                         return rc;
1433                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1434                         PMD_DRV_LOG(ERR,
1435                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1436                         HWRM_UNLOCK();
1437                         return rc;
1438                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1439                         PMD_DRV_LOG(ERR,
1440                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1441                                     rc);
1442                         HWRM_UNLOCK();
1443                         return rc;
1444                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1445                         PMD_DRV_LOG(ERR,
1446                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1447                         HWRM_UNLOCK();
1448                         return rc;
1449                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1450                         PMD_DRV_LOG(ERR,
1451                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1452                         HWRM_UNLOCK();
1453                         return rc;
1454                 default:
1455                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1456                         HWRM_UNLOCK();
1457                         return rc;
1458                 }
1459         }
1460
1461         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1462         HWRM_UNLOCK();
1463         return rc;
1464 }
1465
1466 int bnxt_hwrm_ring_free(struct bnxt *bp,
1467                         struct bnxt_ring *ring, uint32_t ring_type)
1468 {
1469         int rc;
1470         struct hwrm_ring_free_input req = {.req_type = 0 };
1471         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1472
1473         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1474
1475         req.ring_type = ring_type;
1476         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1477
1478         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1479
1480         if (rc || resp->error_code) {
1481                 if (rc == 0 && resp->error_code)
1482                         rc = rte_le_to_cpu_16(resp->error_code);
1483                 HWRM_UNLOCK();
1484
1485                 switch (ring_type) {
1486                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1487                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1488                                 rc);
1489                         return rc;
1490                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1491                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1492                                 rc);
1493                         return rc;
1494                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1495                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1496                                 rc);
1497                         return rc;
1498                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1499                         PMD_DRV_LOG(ERR,
1500                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1501                         return rc;
1502                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1503                         PMD_DRV_LOG(ERR,
1504                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1505                         return rc;
1506                 default:
1507                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1508                         return rc;
1509                 }
1510         }
1511         HWRM_UNLOCK();
1512         return 0;
1513 }
1514
1515 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1516 {
1517         int rc = 0;
1518         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1519         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1520
1521         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1522
1523         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1524         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1525         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1526         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1527
1528         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1529
1530         HWRM_CHECK_RESULT();
1531
1532         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1533
1534         HWRM_UNLOCK();
1535
1536         return rc;
1537 }
1538
1539 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1540 {
1541         int rc;
1542         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1543         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1544
1545         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1546
1547         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1548
1549         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1550
1551         HWRM_CHECK_RESULT();
1552         HWRM_UNLOCK();
1553
1554         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1555         return rc;
1556 }
1557
1558 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1559 {
1560         int rc = 0;
1561         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1562         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1563
1564         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1565                 return rc;
1566
1567         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1568
1569         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1570
1571         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1572
1573         HWRM_CHECK_RESULT();
1574         HWRM_UNLOCK();
1575
1576         return rc;
1577 }
1578
1579 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1580                                 unsigned int idx __rte_unused)
1581 {
1582         int rc;
1583         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1584         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1585
1586         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1587
1588         req.update_period_ms = rte_cpu_to_le_32(0);
1589
1590         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1591
1592         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1593
1594         HWRM_CHECK_RESULT();
1595
1596         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1597
1598         HWRM_UNLOCK();
1599
1600         return rc;
1601 }
1602
1603 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1604                                 unsigned int idx __rte_unused)
1605 {
1606         int rc;
1607         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1608         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1609
1610         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1611
1612         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1613
1614         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1615
1616         HWRM_CHECK_RESULT();
1617         HWRM_UNLOCK();
1618
1619         return rc;
1620 }
1621
1622 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1623 {
1624         int rc = 0, i, j;
1625         struct hwrm_vnic_alloc_input req = { 0 };
1626         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1627
1628         if (!BNXT_HAS_RING_GRPS(bp))
1629                 goto skip_ring_grps;
1630
1631         /* map ring groups to this vnic */
1632         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1633                 vnic->start_grp_id, vnic->end_grp_id);
1634         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1635                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1636
1637         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1638         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1639         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1640         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1641
1642 skip_ring_grps:
1643         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1644         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1645
1646         if (vnic->func_default)
1647                 req.flags =
1648                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1649         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1650
1651         HWRM_CHECK_RESULT();
1652
1653         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1654         HWRM_UNLOCK();
1655         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1656         return rc;
1657 }
1658
1659 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1660                                         struct bnxt_vnic_info *vnic,
1661                                         struct bnxt_plcmodes_cfg *pmode)
1662 {
1663         int rc = 0;
1664         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1665         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1666
1667         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1668
1669         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1670
1671         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1672
1673         HWRM_CHECK_RESULT();
1674
1675         pmode->flags = rte_le_to_cpu_32(resp->flags);
1676         /* dflt_vnic bit doesn't exist in the _cfg command */
1677         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1678         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1679         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1680         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1681
1682         HWRM_UNLOCK();
1683
1684         return rc;
1685 }
1686
1687 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1688                                        struct bnxt_vnic_info *vnic,
1689                                        struct bnxt_plcmodes_cfg *pmode)
1690 {
1691         int rc = 0;
1692         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1693         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1694
1695         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1696                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1697                 return rc;
1698         }
1699
1700         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1701
1702         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1703         req.flags = rte_cpu_to_le_32(pmode->flags);
1704         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1705         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1706         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1707         req.enables = rte_cpu_to_le_32(
1708             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1709             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1710             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1711         );
1712
1713         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1714
1715         HWRM_CHECK_RESULT();
1716         HWRM_UNLOCK();
1717
1718         return rc;
1719 }
1720
1721 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1722 {
1723         int rc = 0;
1724         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1725         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1726         struct bnxt_plcmodes_cfg pmodes = { 0 };
1727         uint32_t ctx_enable_flag = 0;
1728         uint32_t enables = 0;
1729
1730         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1731                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1732                 return rc;
1733         }
1734
1735         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1736         if (rc)
1737                 return rc;
1738
1739         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1740
1741         if (BNXT_CHIP_THOR(bp)) {
1742                 int dflt_rxq = vnic->start_grp_id;
1743                 struct bnxt_rx_ring_info *rxr;
1744                 struct bnxt_cp_ring_info *cpr;
1745                 struct bnxt_rx_queue *rxq;
1746                 int i;
1747
1748                 /*
1749                  * The first active receive ring is used as the VNIC
1750                  * default receive ring. If there are no active receive
1751                  * rings (all corresponding receive queues are stopped),
1752                  * the first receive ring is used.
1753                  */
1754                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1755                         rxq = bp->eth_dev->data->rx_queues[i];
1756                         if (rxq->rx_started) {
1757                                 dflt_rxq = i;
1758                                 break;
1759                         }
1760                 }
1761
1762                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1763                 rxr = rxq->rx_ring;
1764                 cpr = rxq->cp_ring;
1765
1766                 req.default_rx_ring_id =
1767                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1768                 req.default_cmpl_ring_id =
1769                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1770                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1771                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1772                 goto config_mru;
1773         }
1774
1775         /* Only RSS support for now TBD: COS & LB */
1776         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1777         if (vnic->lb_rule != 0xffff)
1778                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1779         if (vnic->cos_rule != 0xffff)
1780                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1781         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1782                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1783                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1784         }
1785         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1786                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1787                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1788         }
1789
1790         enables |= ctx_enable_flag;
1791         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1792         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1793         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1794         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1795
1796 config_mru:
1797         req.enables = rte_cpu_to_le_32(enables);
1798         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1799         req.mru = rte_cpu_to_le_16(vnic->mru);
1800         /* Configure default VNIC only once. */
1801         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1802                 req.flags |=
1803                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1804                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1805         }
1806         if (vnic->vlan_strip)
1807                 req.flags |=
1808                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1809         if (vnic->bd_stall)
1810                 req.flags |=
1811                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1812         if (vnic->roce_dual)
1813                 req.flags |= rte_cpu_to_le_32(
1814                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1815         if (vnic->roce_only)
1816                 req.flags |= rte_cpu_to_le_32(
1817                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1818         if (vnic->rss_dflt_cr)
1819                 req.flags |= rte_cpu_to_le_32(
1820                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1821
1822         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1823
1824         HWRM_CHECK_RESULT();
1825         HWRM_UNLOCK();
1826
1827         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1828
1829         return rc;
1830 }
1831
1832 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1833                 int16_t fw_vf_id)
1834 {
1835         int rc = 0;
1836         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1837         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1838
1839         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1840                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1841                 return rc;
1842         }
1843         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1844
1845         req.enables =
1846                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1847         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1848         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1849
1850         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1851
1852         HWRM_CHECK_RESULT();
1853
1854         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1855         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1856         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1857         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1858         vnic->mru = rte_le_to_cpu_16(resp->mru);
1859         vnic->func_default = rte_le_to_cpu_32(
1860                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1861         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1862                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1863         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1864                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1865         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1866                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1867         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1868                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1869         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1870                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1871
1872         HWRM_UNLOCK();
1873
1874         return rc;
1875 }
1876
1877 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1878                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1879 {
1880         int rc = 0;
1881         uint16_t ctx_id;
1882         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1883         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1884                                                 bp->hwrm_cmd_resp_addr;
1885
1886         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1887
1888         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1889         HWRM_CHECK_RESULT();
1890
1891         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1892         if (!BNXT_HAS_RING_GRPS(bp))
1893                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1894         else if (ctx_idx == 0)
1895                 vnic->rss_rule = ctx_id;
1896
1897         HWRM_UNLOCK();
1898
1899         return rc;
1900 }
1901
1902 static
1903 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1904                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1905 {
1906         int rc = 0;
1907         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1908         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1909                                                 bp->hwrm_cmd_resp_addr;
1910
1911         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1912                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1913                 return rc;
1914         }
1915         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1916
1917         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1918
1919         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1920
1921         HWRM_CHECK_RESULT();
1922         HWRM_UNLOCK();
1923
1924         return rc;
1925 }
1926
1927 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1928 {
1929         int rc = 0;
1930
1931         if (BNXT_CHIP_THOR(bp)) {
1932                 int j;
1933
1934                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1935                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
1936                                                       vnic,
1937                                                       vnic->fw_grp_ids[j]);
1938                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1939                 }
1940                 vnic->num_lb_ctxts = 0;
1941         } else {
1942                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1943                 vnic->rss_rule = INVALID_HW_RING_ID;
1944         }
1945
1946         return rc;
1947 }
1948
1949 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1950 {
1951         int rc = 0;
1952         struct hwrm_vnic_free_input req = {.req_type = 0 };
1953         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1954
1955         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1956                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1957                 return rc;
1958         }
1959
1960         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1961
1962         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1963
1964         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1965
1966         HWRM_CHECK_RESULT();
1967         HWRM_UNLOCK();
1968
1969         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1970         /* Configure default VNIC again if necessary. */
1971         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1972                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1973
1974         return rc;
1975 }
1976
1977 static int
1978 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1979 {
1980         int i;
1981         int rc = 0;
1982         int nr_ctxs = vnic->num_lb_ctxts;
1983         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1984         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1985
1986         for (i = 0; i < nr_ctxs; i++) {
1987                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1988
1989                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1990                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1991                 req.hash_mode_flags = vnic->hash_mode;
1992
1993                 req.hash_key_tbl_addr =
1994                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1995
1996                 req.ring_grp_tbl_addr =
1997                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1998                                          i * HW_HASH_INDEX_SIZE);
1999                 req.ring_table_pair_index = i;
2000                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2001
2002                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2003                                             BNXT_USE_CHIMP_MB);
2004
2005                 HWRM_CHECK_RESULT();
2006                 HWRM_UNLOCK();
2007         }
2008
2009         return rc;
2010 }
2011
2012 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2013                            struct bnxt_vnic_info *vnic)
2014 {
2015         int rc = 0;
2016         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2017         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2018
2019         if (!vnic->rss_table)
2020                 return 0;
2021
2022         if (BNXT_CHIP_THOR(bp))
2023                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2024
2025         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2026
2027         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2028         req.hash_mode_flags = vnic->hash_mode;
2029
2030         req.ring_grp_tbl_addr =
2031             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2032         req.hash_key_tbl_addr =
2033             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2034         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2035         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2036
2037         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2038
2039         HWRM_CHECK_RESULT();
2040         HWRM_UNLOCK();
2041
2042         return rc;
2043 }
2044
2045 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2046                         struct bnxt_vnic_info *vnic)
2047 {
2048         int rc = 0;
2049         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2050         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2051         uint16_t size;
2052
2053         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2054                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2055                 return rc;
2056         }
2057
2058         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2059
2060         req.flags = rte_cpu_to_le_32(
2061                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2062
2063         req.enables = rte_cpu_to_le_32(
2064                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2065
2066         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2067         size -= RTE_PKTMBUF_HEADROOM;
2068         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2069
2070         req.jumbo_thresh = rte_cpu_to_le_16(size);
2071         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2072
2073         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2074
2075         HWRM_CHECK_RESULT();
2076         HWRM_UNLOCK();
2077
2078         return rc;
2079 }
2080
2081 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2082                         struct bnxt_vnic_info *vnic, bool enable)
2083 {
2084         int rc = 0;
2085         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2086         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2087
2088         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2089                 if (enable)
2090                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2091                 return -ENOTSUP;
2092         }
2093
2094         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2095                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2096                 return 0;
2097         }
2098
2099         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2100
2101         if (enable) {
2102                 req.enables = rte_cpu_to_le_32(
2103                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2104                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2105                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2106                 req.flags = rte_cpu_to_le_32(
2107                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2108                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2109                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2110                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2111                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2112                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2113                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2114                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2115                 req.min_agg_len = rte_cpu_to_le_32(512);
2116         }
2117         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2118
2119         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2120
2121         HWRM_CHECK_RESULT();
2122         HWRM_UNLOCK();
2123
2124         return rc;
2125 }
2126
2127 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2128 {
2129         struct hwrm_func_cfg_input req = {0};
2130         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2131         int rc;
2132
2133         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2134         req.enables = rte_cpu_to_le_32(
2135                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2136         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2137         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2138
2139         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2140
2141         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2142         HWRM_CHECK_RESULT();
2143         HWRM_UNLOCK();
2144
2145         bp->pf.vf_info[vf].random_mac = false;
2146
2147         return rc;
2148 }
2149
2150 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2151                                   uint64_t *dropped)
2152 {
2153         int rc = 0;
2154         struct hwrm_func_qstats_input req = {.req_type = 0};
2155         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2156
2157         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2158
2159         req.fid = rte_cpu_to_le_16(fid);
2160
2161         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2162
2163         HWRM_CHECK_RESULT();
2164
2165         if (dropped)
2166                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2167
2168         HWRM_UNLOCK();
2169
2170         return rc;
2171 }
2172
2173 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2174                           struct rte_eth_stats *stats)
2175 {
2176         int rc = 0;
2177         struct hwrm_func_qstats_input req = {.req_type = 0};
2178         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2179
2180         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2181
2182         req.fid = rte_cpu_to_le_16(fid);
2183
2184         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2185
2186         HWRM_CHECK_RESULT();
2187
2188         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2189         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2190         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2191         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2192         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2193         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2194
2195         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2196         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2197         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2198         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2199         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2200         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2201
2202         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2203         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2204         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2205
2206         HWRM_UNLOCK();
2207
2208         return rc;
2209 }
2210
2211 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2212 {
2213         int rc = 0;
2214         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2215         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2216
2217         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2218
2219         req.fid = rte_cpu_to_le_16(fid);
2220
2221         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2222
2223         HWRM_CHECK_RESULT();
2224         HWRM_UNLOCK();
2225
2226         return rc;
2227 }
2228
2229 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2230 {
2231         unsigned int i;
2232         int rc = 0;
2233
2234         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2235                 struct bnxt_tx_queue *txq;
2236                 struct bnxt_rx_queue *rxq;
2237                 struct bnxt_cp_ring_info *cpr;
2238
2239                 if (i >= bp->rx_cp_nr_rings) {
2240                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2241                         cpr = txq->cp_ring;
2242                 } else {
2243                         rxq = bp->rx_queues[i];
2244                         cpr = rxq->cp_ring;
2245                 }
2246
2247                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2248                 if (rc)
2249                         return rc;
2250         }
2251         return 0;
2252 }
2253
2254 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2255 {
2256         int rc;
2257         unsigned int i;
2258         struct bnxt_cp_ring_info *cpr;
2259
2260         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2261
2262                 if (i >= bp->rx_cp_nr_rings) {
2263                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2264                 } else {
2265                         cpr = bp->rx_queues[i]->cp_ring;
2266                         if (BNXT_HAS_RING_GRPS(bp))
2267                                 bp->grp_info[i].fw_stats_ctx = -1;
2268                 }
2269                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2270                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2271                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2272                         if (rc)
2273                                 return rc;
2274                 }
2275         }
2276         return 0;
2277 }
2278
2279 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2280 {
2281         unsigned int i;
2282         int rc = 0;
2283
2284         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2285                 struct bnxt_tx_queue *txq;
2286                 struct bnxt_rx_queue *rxq;
2287                 struct bnxt_cp_ring_info *cpr;
2288
2289                 if (i >= bp->rx_cp_nr_rings) {
2290                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2291                         cpr = txq->cp_ring;
2292                 } else {
2293                         rxq = bp->rx_queues[i];
2294                         cpr = rxq->cp_ring;
2295                 }
2296
2297                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2298
2299                 if (rc)
2300                         return rc;
2301         }
2302         return rc;
2303 }
2304
2305 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2306 {
2307         uint16_t idx;
2308         uint32_t rc = 0;
2309
2310         if (!BNXT_HAS_RING_GRPS(bp))
2311                 return 0;
2312
2313         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2314
2315                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2316                         continue;
2317
2318                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2319
2320                 if (rc)
2321                         return rc;
2322         }
2323         return rc;
2324 }
2325
2326 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2327 {
2328         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2329
2330         bnxt_hwrm_ring_free(bp, cp_ring,
2331                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2332         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2333         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2334                                      sizeof(*cpr->cp_desc_ring));
2335         cpr->cp_raw_cons = 0;
2336         cpr->valid = 0;
2337 }
2338
2339 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2340 {
2341         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2342
2343         bnxt_hwrm_ring_free(bp, cp_ring,
2344                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2345         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2346         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2347                         sizeof(*cpr->cp_desc_ring));
2348         cpr->cp_raw_cons = 0;
2349         cpr->valid = 0;
2350 }
2351
2352 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2353 {
2354         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2355         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2356         struct bnxt_ring *ring = rxr->rx_ring_struct;
2357         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2358
2359         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2360                 bnxt_hwrm_ring_free(bp, ring,
2361                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2362                 ring->fw_ring_id = INVALID_HW_RING_ID;
2363                 if (BNXT_HAS_RING_GRPS(bp))
2364                         bp->grp_info[queue_index].rx_fw_ring_id =
2365                                                         INVALID_HW_RING_ID;
2366                 memset(rxr->rx_desc_ring, 0,
2367                        rxr->rx_ring_struct->ring_size *
2368                        sizeof(*rxr->rx_desc_ring));
2369                 memset(rxr->rx_buf_ring, 0,
2370                        rxr->rx_ring_struct->ring_size *
2371                        sizeof(*rxr->rx_buf_ring));
2372                 rxr->rx_prod = 0;
2373         }
2374         ring = rxr->ag_ring_struct;
2375         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2376                 bnxt_hwrm_ring_free(bp, ring,
2377                                     BNXT_CHIP_THOR(bp) ?
2378                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2379                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2380                 ring->fw_ring_id = INVALID_HW_RING_ID;
2381                 memset(rxr->ag_buf_ring, 0,
2382                        rxr->ag_ring_struct->ring_size *
2383                        sizeof(*rxr->ag_buf_ring));
2384                 rxr->ag_prod = 0;
2385                 if (BNXT_HAS_RING_GRPS(bp))
2386                         bp->grp_info[queue_index].ag_fw_ring_id =
2387                                                         INVALID_HW_RING_ID;
2388         }
2389         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2390                 bnxt_free_cp_ring(bp, cpr);
2391
2392         if (BNXT_HAS_RING_GRPS(bp))
2393                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2394 }
2395
2396 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2397 {
2398         unsigned int i;
2399
2400         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2401                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2402                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2403                 struct bnxt_ring *ring = txr->tx_ring_struct;
2404                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2405
2406                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2407                         bnxt_hwrm_ring_free(bp, ring,
2408                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2409                         ring->fw_ring_id = INVALID_HW_RING_ID;
2410                         memset(txr->tx_desc_ring, 0,
2411                                         txr->tx_ring_struct->ring_size *
2412                                         sizeof(*txr->tx_desc_ring));
2413                         memset(txr->tx_buf_ring, 0,
2414                                         txr->tx_ring_struct->ring_size *
2415                                         sizeof(*txr->tx_buf_ring));
2416                         txr->tx_prod = 0;
2417                         txr->tx_cons = 0;
2418                 }
2419                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2420                         bnxt_free_cp_ring(bp, cpr);
2421                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2422                 }
2423         }
2424
2425         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2426                 bnxt_free_hwrm_rx_ring(bp, i);
2427
2428         return 0;
2429 }
2430
2431 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2432 {
2433         uint16_t i;
2434         uint32_t rc = 0;
2435
2436         if (!BNXT_HAS_RING_GRPS(bp))
2437                 return 0;
2438
2439         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2440                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2441                 if (rc)
2442                         return rc;
2443         }
2444         return rc;
2445 }
2446
2447 /*
2448  * HWRM utility functions
2449  */
2450
2451 void bnxt_free_hwrm_resources(struct bnxt *bp)
2452 {
2453         /* Release memzone */
2454         rte_free(bp->hwrm_cmd_resp_addr);
2455         rte_free(bp->hwrm_short_cmd_req_addr);
2456         bp->hwrm_cmd_resp_addr = NULL;
2457         bp->hwrm_short_cmd_req_addr = NULL;
2458         bp->hwrm_cmd_resp_dma_addr = 0;
2459         bp->hwrm_short_cmd_req_dma_addr = 0;
2460 }
2461
2462 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2463 {
2464         struct rte_pci_device *pdev = bp->pdev;
2465         char type[RTE_MEMZONE_NAMESIZE];
2466
2467         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2468                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2469         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2470         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2471         if (bp->hwrm_cmd_resp_addr == NULL)
2472                 return -ENOMEM;
2473         bp->hwrm_cmd_resp_dma_addr =
2474                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2475         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2476                 PMD_DRV_LOG(ERR,
2477                         "unable to map response address to physical memory\n");
2478                 return -ENOMEM;
2479         }
2480         rte_spinlock_init(&bp->hwrm_lock);
2481
2482         return 0;
2483 }
2484
2485 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2486 {
2487         struct bnxt_filter_info *filter;
2488         int rc = 0;
2489
2490         STAILQ_FOREACH(filter, &vnic->filter, next) {
2491                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2492                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2493                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2494                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2495                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2496                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2497                 bnxt_free_filter(bp, filter);
2498         }
2499         return rc;
2500 }
2501
2502 static int
2503 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2504 {
2505         struct bnxt_filter_info *filter;
2506         struct rte_flow *flow;
2507         int rc = 0;
2508
2509         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2510                 flow = STAILQ_FIRST(&vnic->flow_list);
2511                 filter = flow->filter;
2512                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2513                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2514                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2515                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2516                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2517                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2518
2519                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2520                 rte_free(flow);
2521         }
2522         return rc;
2523 }
2524
2525 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2526 {
2527         struct bnxt_filter_info *filter;
2528         int rc = 0;
2529
2530         STAILQ_FOREACH(filter, &vnic->filter, next) {
2531                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2532                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2533                                                      filter);
2534                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2535                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2536                                                          filter);
2537                 else
2538                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2539                                                      filter);
2540                 if (rc)
2541                         break;
2542         }
2543         return rc;
2544 }
2545
2546 void bnxt_free_tunnel_ports(struct bnxt *bp)
2547 {
2548         if (bp->vxlan_port_cnt)
2549                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2550                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2551         bp->vxlan_port = 0;
2552         if (bp->geneve_port_cnt)
2553                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2554                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2555         bp->geneve_port = 0;
2556 }
2557
2558 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2559 {
2560         int i;
2561
2562         if (bp->vnic_info == NULL)
2563                 return;
2564
2565         /*
2566          * Cleanup VNICs in reverse order, to make sure the L2 filter
2567          * from vnic0 is last to be cleaned up.
2568          */
2569         for (i = bp->max_vnics - 1; i >= 0; i--) {
2570                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2571
2572                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2573                         continue;
2574
2575                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2576
2577                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2578
2579                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2580
2581                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2582
2583                 bnxt_hwrm_vnic_free(bp, vnic);
2584
2585                 rte_free(vnic->fw_grp_ids);
2586         }
2587         /* Ring resources */
2588         bnxt_free_all_hwrm_rings(bp);
2589         bnxt_free_all_hwrm_ring_grps(bp);
2590         bnxt_free_all_hwrm_stat_ctxs(bp);
2591         bnxt_free_tunnel_ports(bp);
2592 }
2593
2594 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2595 {
2596         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2597
2598         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2599                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2600
2601         switch (conf_link_speed) {
2602         case ETH_LINK_SPEED_10M_HD:
2603         case ETH_LINK_SPEED_100M_HD:
2604                 /* FALLTHROUGH */
2605                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2606         }
2607         return hw_link_duplex;
2608 }
2609
2610 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2611 {
2612         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2613 }
2614
2615 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2616 {
2617         uint16_t eth_link_speed = 0;
2618
2619         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2620                 return ETH_LINK_SPEED_AUTONEG;
2621
2622         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2623         case ETH_LINK_SPEED_100M:
2624         case ETH_LINK_SPEED_100M_HD:
2625                 /* FALLTHROUGH */
2626                 eth_link_speed =
2627                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2628                 break;
2629         case ETH_LINK_SPEED_1G:
2630                 eth_link_speed =
2631                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2632                 break;
2633         case ETH_LINK_SPEED_2_5G:
2634                 eth_link_speed =
2635                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2636                 break;
2637         case ETH_LINK_SPEED_10G:
2638                 eth_link_speed =
2639                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2640                 break;
2641         case ETH_LINK_SPEED_20G:
2642                 eth_link_speed =
2643                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2644                 break;
2645         case ETH_LINK_SPEED_25G:
2646                 eth_link_speed =
2647                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2648                 break;
2649         case ETH_LINK_SPEED_40G:
2650                 eth_link_speed =
2651                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2652                 break;
2653         case ETH_LINK_SPEED_50G:
2654                 eth_link_speed =
2655                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2656                 break;
2657         case ETH_LINK_SPEED_100G:
2658                 eth_link_speed =
2659                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2660                 break;
2661         default:
2662                 PMD_DRV_LOG(ERR,
2663                         "Unsupported link speed %d; default to AUTO\n",
2664                         conf_link_speed);
2665                 break;
2666         }
2667         return eth_link_speed;
2668 }
2669
2670 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2671                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2672                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2673                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2674
2675 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2676 {
2677         uint32_t one_speed;
2678
2679         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2680                 return 0;
2681
2682         if (link_speed & ETH_LINK_SPEED_FIXED) {
2683                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2684
2685                 if (one_speed & (one_speed - 1)) {
2686                         PMD_DRV_LOG(ERR,
2687                                 "Invalid advertised speeds (%u) for port %u\n",
2688                                 link_speed, port_id);
2689                         return -EINVAL;
2690                 }
2691                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2692                         PMD_DRV_LOG(ERR,
2693                                 "Unsupported advertised speed (%u) for port %u\n",
2694                                 link_speed, port_id);
2695                         return -EINVAL;
2696                 }
2697         } else {
2698                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2699                         PMD_DRV_LOG(ERR,
2700                                 "Unsupported advertised speeds (%u) for port %u\n",
2701                                 link_speed, port_id);
2702                         return -EINVAL;
2703                 }
2704         }
2705         return 0;
2706 }
2707
2708 static uint16_t
2709 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2710 {
2711         uint16_t ret = 0;
2712
2713         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2714                 if (bp->link_info.support_speeds)
2715                         return bp->link_info.support_speeds;
2716                 link_speed = BNXT_SUPPORTED_SPEEDS;
2717         }
2718
2719         if (link_speed & ETH_LINK_SPEED_100M)
2720                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2721         if (link_speed & ETH_LINK_SPEED_100M_HD)
2722                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2723         if (link_speed & ETH_LINK_SPEED_1G)
2724                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2725         if (link_speed & ETH_LINK_SPEED_2_5G)
2726                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2727         if (link_speed & ETH_LINK_SPEED_10G)
2728                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2729         if (link_speed & ETH_LINK_SPEED_20G)
2730                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2731         if (link_speed & ETH_LINK_SPEED_25G)
2732                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2733         if (link_speed & ETH_LINK_SPEED_40G)
2734                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2735         if (link_speed & ETH_LINK_SPEED_50G)
2736                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2737         if (link_speed & ETH_LINK_SPEED_100G)
2738                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2739         return ret;
2740 }
2741
2742 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2743 {
2744         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2745
2746         switch (hw_link_speed) {
2747         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2748                 eth_link_speed = ETH_SPEED_NUM_100M;
2749                 break;
2750         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2751                 eth_link_speed = ETH_SPEED_NUM_1G;
2752                 break;
2753         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2754                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2755                 break;
2756         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2757                 eth_link_speed = ETH_SPEED_NUM_10G;
2758                 break;
2759         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2760                 eth_link_speed = ETH_SPEED_NUM_20G;
2761                 break;
2762         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2763                 eth_link_speed = ETH_SPEED_NUM_25G;
2764                 break;
2765         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2766                 eth_link_speed = ETH_SPEED_NUM_40G;
2767                 break;
2768         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2769                 eth_link_speed = ETH_SPEED_NUM_50G;
2770                 break;
2771         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2772                 eth_link_speed = ETH_SPEED_NUM_100G;
2773                 break;
2774         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2775         default:
2776                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2777                         hw_link_speed);
2778                 break;
2779         }
2780         return eth_link_speed;
2781 }
2782
2783 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2784 {
2785         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2786
2787         switch (hw_link_duplex) {
2788         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2789         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2790                 /* FALLTHROUGH */
2791                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2792                 break;
2793         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2794                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2795                 break;
2796         default:
2797                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2798                         hw_link_duplex);
2799                 break;
2800         }
2801         return eth_link_duplex;
2802 }
2803
2804 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2805 {
2806         int rc = 0;
2807         struct bnxt_link_info *link_info = &bp->link_info;
2808
2809         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2810         if (rc) {
2811                 PMD_DRV_LOG(ERR,
2812                         "Get link config failed with rc %d\n", rc);
2813                 goto exit;
2814         }
2815         if (link_info->link_speed)
2816                 link->link_speed =
2817                         bnxt_parse_hw_link_speed(link_info->link_speed);
2818         else
2819                 link->link_speed = ETH_SPEED_NUM_NONE;
2820         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2821         link->link_status = link_info->link_up;
2822         link->link_autoneg = link_info->auto_mode ==
2823                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2824                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2825 exit:
2826         return rc;
2827 }
2828
2829 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2830 {
2831         int rc = 0;
2832         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2833         struct bnxt_link_info link_req;
2834         uint16_t speed, autoneg;
2835
2836         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2837                 return 0;
2838
2839         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2840                         bp->eth_dev->data->port_id);
2841         if (rc)
2842                 goto error;
2843
2844         memset(&link_req, 0, sizeof(link_req));
2845         link_req.link_up = link_up;
2846         if (!link_up)
2847                 goto port_phy_cfg;
2848
2849         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2850         if (BNXT_CHIP_THOR(bp) &&
2851             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2852                 /* 40G is not supported as part of media auto detect.
2853                  * The speed should be forced and autoneg disabled
2854                  * to configure 40G speed.
2855                  */
2856                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2857                 autoneg = 0;
2858         }
2859
2860         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2861         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2862         /* Autoneg can be done only when the FW allows.
2863          * When user configures fixed speed of 40G and later changes to
2864          * any other speed, auto_link_speed/force_link_speed is still set
2865          * to 40G until link comes up at new speed.
2866          */
2867         if (autoneg == 1 &&
2868             !(!BNXT_CHIP_THOR(bp) &&
2869               (bp->link_info.auto_link_speed ||
2870                bp->link_info.force_link_speed))) {
2871                 link_req.phy_flags |=
2872                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2873                 link_req.auto_link_speed_mask =
2874                         bnxt_parse_eth_link_speed_mask(bp,
2875                                                        dev_conf->link_speeds);
2876         } else {
2877                 if (bp->link_info.phy_type ==
2878                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2879                     bp->link_info.phy_type ==
2880                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2881                     bp->link_info.media_type ==
2882                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2883                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2884                         return -EINVAL;
2885                 }
2886
2887                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2888                 /* If user wants a particular speed try that first. */
2889                 if (speed)
2890                         link_req.link_speed = speed;
2891                 else if (bp->link_info.force_link_speed)
2892                         link_req.link_speed = bp->link_info.force_link_speed;
2893                 else
2894                         link_req.link_speed = bp->link_info.auto_link_speed;
2895         }
2896         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2897         link_req.auto_pause = bp->link_info.auto_pause;
2898         link_req.force_pause = bp->link_info.force_pause;
2899
2900 port_phy_cfg:
2901         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2902         if (rc) {
2903                 PMD_DRV_LOG(ERR,
2904                         "Set link config failed with rc %d\n", rc);
2905         }
2906
2907 error:
2908         return rc;
2909 }
2910
2911 /* JIRA 22088 */
2912 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2913 {
2914         struct hwrm_func_qcfg_input req = {0};
2915         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2916         uint16_t flags;
2917         int rc = 0;
2918
2919         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2920         req.fid = rte_cpu_to_le_16(0xffff);
2921
2922         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2923
2924         HWRM_CHECK_RESULT();
2925
2926         /* Hard Coded.. 0xfff VLAN ID mask */
2927         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2928         flags = rte_le_to_cpu_16(resp->flags);
2929         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2930                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2931
2932         if (BNXT_VF(bp) &&
2933             !BNXT_VF_IS_TRUSTED(bp) &&
2934             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2935                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2936                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2937         } else if (BNXT_VF(bp) &&
2938                    BNXT_VF_IS_TRUSTED(bp) &&
2939                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2940                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2941                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2942         }
2943
2944         if (mtu)
2945                 *mtu = rte_le_to_cpu_16(resp->mtu);
2946
2947         switch (resp->port_partition_type) {
2948         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2949         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2950         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2951                 /* FALLTHROUGH */
2952                 bp->flags |= BNXT_FLAG_NPAR_PF;
2953                 break;
2954         default:
2955                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
2956                 break;
2957         }
2958
2959         HWRM_UNLOCK();
2960
2961         return rc;
2962 }
2963
2964 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2965                                    struct hwrm_func_qcaps_output *qcaps)
2966 {
2967         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2968         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2969                sizeof(qcaps->mac_address));
2970         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2971         qcaps->max_rx_rings = fcfg->num_rx_rings;
2972         qcaps->max_tx_rings = fcfg->num_tx_rings;
2973         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2974         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2975         qcaps->max_vfs = 0;
2976         qcaps->first_vf_id = 0;
2977         qcaps->max_vnics = fcfg->num_vnics;
2978         qcaps->max_decap_records = 0;
2979         qcaps->max_encap_records = 0;
2980         qcaps->max_tx_wm_flows = 0;
2981         qcaps->max_tx_em_flows = 0;
2982         qcaps->max_rx_wm_flows = 0;
2983         qcaps->max_rx_em_flows = 0;
2984         qcaps->max_flow_id = 0;
2985         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2986         qcaps->max_sp_tx_rings = 0;
2987         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2988 }
2989
2990 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2991 {
2992         struct hwrm_func_cfg_input req = {0};
2993         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2994         uint32_t enables;
2995         int rc;
2996
2997         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2998                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2999                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3000                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3001                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3002                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3003                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3004                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3005                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3006
3007         if (BNXT_HAS_RING_GRPS(bp)) {
3008                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3009                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3010         } else if (BNXT_HAS_NQ(bp)) {
3011                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3012                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3013         }
3014
3015         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3016         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3017         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3018         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3019         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3020         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3021         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3022         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3023         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3024         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3025         req.fid = rte_cpu_to_le_16(0xffff);
3026         req.enables = rte_cpu_to_le_32(enables);
3027
3028         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3029
3030         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3031
3032         HWRM_CHECK_RESULT();
3033         HWRM_UNLOCK();
3034
3035         return rc;
3036 }
3037
3038 static void populate_vf_func_cfg_req(struct bnxt *bp,
3039                                      struct hwrm_func_cfg_input *req,
3040                                      int num_vfs)
3041 {
3042         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3043                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3044                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3045                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3046                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3047                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3048                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3049                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3050                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3051                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3052
3053         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3054                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3055                                     BNXT_NUM_VLANS);
3056         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3057         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3058                                                 (num_vfs + 1));
3059         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3060         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3061                                                (num_vfs + 1));
3062         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3063         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3064         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3065         /* TODO: For now, do not support VMDq/RFS on VFs. */
3066         req->num_vnics = rte_cpu_to_le_16(1);
3067         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3068                                                  (num_vfs + 1));
3069 }
3070
3071 static void add_random_mac_if_needed(struct bnxt *bp,
3072                                      struct hwrm_func_cfg_input *cfg_req,
3073                                      int vf)
3074 {
3075         struct rte_ether_addr mac;
3076
3077         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3078                 return;
3079
3080         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3081                 cfg_req->enables |=
3082                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3083                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3084                 bp->pf.vf_info[vf].random_mac = true;
3085         } else {
3086                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3087                         RTE_ETHER_ADDR_LEN);
3088         }
3089 }
3090
3091 static void reserve_resources_from_vf(struct bnxt *bp,
3092                                       struct hwrm_func_cfg_input *cfg_req,
3093                                       int vf)
3094 {
3095         struct hwrm_func_qcaps_input req = {0};
3096         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3097         int rc;
3098
3099         /* Get the actual allocated values now */
3100         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3101         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3102         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3103
3104         if (rc) {
3105                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3106                 copy_func_cfg_to_qcaps(cfg_req, resp);
3107         } else if (resp->error_code) {
3108                 rc = rte_le_to_cpu_16(resp->error_code);
3109                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3110                 copy_func_cfg_to_qcaps(cfg_req, resp);
3111         }
3112
3113         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3114         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3115         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3116         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3117         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3118         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3119         /*
3120          * TODO: While not supporting VMDq with VFs, max_vnics is always
3121          * forced to 1 in this case
3122          */
3123         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3124         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3125
3126         HWRM_UNLOCK();
3127 }
3128
3129 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3130 {
3131         struct hwrm_func_qcfg_input req = {0};
3132         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3133         int rc;
3134
3135         /* Check for zero MAC address */
3136         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3137         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3138         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3139         HWRM_CHECK_RESULT();
3140         rc = rte_le_to_cpu_16(resp->vlan);
3141
3142         HWRM_UNLOCK();
3143
3144         return rc;
3145 }
3146
3147 static int update_pf_resource_max(struct bnxt *bp)
3148 {
3149         struct hwrm_func_qcfg_input req = {0};
3150         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3151         int rc;
3152
3153         /* And copy the allocated numbers into the pf struct */
3154         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3155         req.fid = rte_cpu_to_le_16(0xffff);
3156         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3157         HWRM_CHECK_RESULT();
3158
3159         /* Only TX ring value reflects actual allocation? TODO */
3160         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3161         bp->pf.evb_mode = resp->evb_mode;
3162
3163         HWRM_UNLOCK();
3164
3165         return rc;
3166 }
3167
3168 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3169 {
3170         int rc;
3171
3172         if (!BNXT_PF(bp)) {
3173                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3174                 return -EINVAL;
3175         }
3176
3177         rc = bnxt_hwrm_func_qcaps(bp);
3178         if (rc)
3179                 return rc;
3180
3181         bp->pf.func_cfg_flags &=
3182                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3183                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3184         bp->pf.func_cfg_flags |=
3185                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3186         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3187         rc = __bnxt_hwrm_func_qcaps(bp);
3188         return rc;
3189 }
3190
3191 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3192 {
3193         struct hwrm_func_cfg_input req = {0};
3194         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3195         int i;
3196         size_t sz;
3197         int rc = 0;
3198         size_t req_buf_sz;
3199
3200         if (!BNXT_PF(bp)) {
3201                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3202                 return -EINVAL;
3203         }
3204
3205         rc = bnxt_hwrm_func_qcaps(bp);
3206
3207         if (rc)
3208                 return rc;
3209
3210         bp->pf.active_vfs = num_vfs;
3211
3212         /*
3213          * First, configure the PF to only use one TX ring.  This ensures that
3214          * there are enough rings for all VFs.
3215          *
3216          * If we don't do this, when we call func_alloc() later, we will lock
3217          * extra rings to the PF that won't be available during func_cfg() of
3218          * the VFs.
3219          *
3220          * This has been fixed with firmware versions above 20.6.54
3221          */
3222         bp->pf.func_cfg_flags &=
3223                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3224                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3225         bp->pf.func_cfg_flags |=
3226                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3227         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3228         if (rc)
3229                 return rc;
3230
3231         /*
3232          * Now, create and register a buffer to hold forwarded VF requests
3233          */
3234         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3235         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3236                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3237         if (bp->pf.vf_req_buf == NULL) {
3238                 rc = -ENOMEM;
3239                 goto error_free;
3240         }
3241         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3242                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3243         for (i = 0; i < num_vfs; i++)
3244                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3245                                         (i * HWRM_MAX_REQ_LEN);
3246
3247         rc = bnxt_hwrm_func_buf_rgtr(bp);
3248         if (rc)
3249                 goto error_free;
3250
3251         populate_vf_func_cfg_req(bp, &req, num_vfs);
3252
3253         bp->pf.active_vfs = 0;
3254         for (i = 0; i < num_vfs; i++) {
3255                 add_random_mac_if_needed(bp, &req, i);
3256
3257                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3258                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3259                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3260                 rc = bnxt_hwrm_send_message(bp,
3261                                             &req,
3262                                             sizeof(req),
3263                                             BNXT_USE_CHIMP_MB);
3264
3265                 /* Clear enable flag for next pass */
3266                 req.enables &= ~rte_cpu_to_le_32(
3267                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3268
3269                 if (rc || resp->error_code) {
3270                         PMD_DRV_LOG(ERR,
3271                                 "Failed to initizlie VF %d\n", i);
3272                         PMD_DRV_LOG(ERR,
3273                                 "Not all VFs available. (%d, %d)\n",
3274                                 rc, resp->error_code);
3275                         HWRM_UNLOCK();
3276                         break;
3277                 }
3278
3279                 HWRM_UNLOCK();
3280
3281                 reserve_resources_from_vf(bp, &req, i);
3282                 bp->pf.active_vfs++;
3283                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3284         }
3285
3286         /*
3287          * Now configure the PF to use "the rest" of the resources
3288          * We're using STD_TX_RING_MODE here though which will limit the TX
3289          * rings.  This will allow QoS to function properly.  Not setting this
3290          * will cause PF rings to break bandwidth settings.
3291          */
3292         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3293         if (rc)
3294                 goto error_free;
3295
3296         rc = update_pf_resource_max(bp);
3297         if (rc)
3298                 goto error_free;
3299
3300         return rc;
3301
3302 error_free:
3303         bnxt_hwrm_func_buf_unrgtr(bp);
3304         return rc;
3305 }
3306
3307 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3308 {
3309         struct hwrm_func_cfg_input req = {0};
3310         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3311         int rc;
3312
3313         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3314
3315         req.fid = rte_cpu_to_le_16(0xffff);
3316         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3317         req.evb_mode = bp->pf.evb_mode;
3318
3319         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3320         HWRM_CHECK_RESULT();
3321         HWRM_UNLOCK();
3322
3323         return rc;
3324 }
3325
3326 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3327                                 uint8_t tunnel_type)
3328 {
3329         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3330         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3331         int rc = 0;
3332
3333         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3334         req.tunnel_type = tunnel_type;
3335         req.tunnel_dst_port_val = port;
3336         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3337         HWRM_CHECK_RESULT();
3338
3339         switch (tunnel_type) {
3340         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3341                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3342                 bp->vxlan_port = port;
3343                 break;
3344         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3345                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3346                 bp->geneve_port = port;
3347                 break;
3348         default:
3349                 break;
3350         }
3351
3352         HWRM_UNLOCK();
3353
3354         return rc;
3355 }
3356
3357 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3358                                 uint8_t tunnel_type)
3359 {
3360         struct hwrm_tunnel_dst_port_free_input req = {0};
3361         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3362         int rc = 0;
3363
3364         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3365
3366         req.tunnel_type = tunnel_type;
3367         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3368         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3369
3370         HWRM_CHECK_RESULT();
3371         HWRM_UNLOCK();
3372
3373         return rc;
3374 }
3375
3376 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3377                                         uint32_t flags)
3378 {
3379         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3380         struct hwrm_func_cfg_input req = {0};
3381         int rc;
3382
3383         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3384
3385         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3386         req.flags = rte_cpu_to_le_32(flags);
3387         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3388
3389         HWRM_CHECK_RESULT();
3390         HWRM_UNLOCK();
3391
3392         return rc;
3393 }
3394
3395 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3396 {
3397         uint32_t *flag = flagp;
3398
3399         vnic->flags = *flag;
3400 }
3401
3402 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3403 {
3404         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3405 }
3406
3407 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3408 {
3409         int rc = 0;
3410         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3411         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3412
3413         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3414
3415         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3416         req.req_buf_page_size = rte_cpu_to_le_16(
3417                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3418         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3419         req.req_buf_page_addr0 =
3420                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf.vf_req_buf));
3421         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3422                 PMD_DRV_LOG(ERR,
3423                         "unable to map buffer address to physical memory\n");
3424                 return -ENOMEM;
3425         }
3426
3427         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3428
3429         HWRM_CHECK_RESULT();
3430         HWRM_UNLOCK();
3431
3432         return rc;
3433 }
3434
3435 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3436 {
3437         int rc = 0;
3438         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3439         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3440
3441         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3442                 return 0;
3443
3444         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3445
3446         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3447
3448         HWRM_CHECK_RESULT();
3449         HWRM_UNLOCK();
3450
3451         return rc;
3452 }
3453
3454 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3455 {
3456         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3457         struct hwrm_func_cfg_input req = {0};
3458         int rc;
3459
3460         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3461
3462         req.fid = rte_cpu_to_le_16(0xffff);
3463         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3464         req.enables = rte_cpu_to_le_32(
3465                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3466         req.async_event_cr = rte_cpu_to_le_16(
3467                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3468         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3469
3470         HWRM_CHECK_RESULT();
3471         HWRM_UNLOCK();
3472
3473         return rc;
3474 }
3475
3476 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3477 {
3478         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3479         struct hwrm_func_vf_cfg_input req = {0};
3480         int rc;
3481
3482         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3483
3484         req.enables = rte_cpu_to_le_32(
3485                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3486         req.async_event_cr = rte_cpu_to_le_16(
3487                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3488         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3489
3490         HWRM_CHECK_RESULT();
3491         HWRM_UNLOCK();
3492
3493         return rc;
3494 }
3495
3496 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3497 {
3498         struct hwrm_func_cfg_input req = {0};
3499         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3500         uint16_t dflt_vlan, fid;
3501         uint32_t func_cfg_flags;
3502         int rc = 0;
3503
3504         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3505
3506         if (is_vf) {
3507                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3508                 fid = bp->pf.vf_info[vf].fid;
3509                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3510         } else {
3511                 fid = rte_cpu_to_le_16(0xffff);
3512                 func_cfg_flags = bp->pf.func_cfg_flags;
3513                 dflt_vlan = bp->vlan;
3514         }
3515
3516         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3517         req.fid = rte_cpu_to_le_16(fid);
3518         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3519         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3520
3521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3522
3523         HWRM_CHECK_RESULT();
3524         HWRM_UNLOCK();
3525
3526         return rc;
3527 }
3528
3529 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3530                         uint16_t max_bw, uint16_t enables)
3531 {
3532         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3533         struct hwrm_func_cfg_input req = {0};
3534         int rc;
3535
3536         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3537
3538         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3539         req.enables |= rte_cpu_to_le_32(enables);
3540         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3541         req.max_bw = rte_cpu_to_le_32(max_bw);
3542         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3543
3544         HWRM_CHECK_RESULT();
3545         HWRM_UNLOCK();
3546
3547         return rc;
3548 }
3549
3550 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3551 {
3552         struct hwrm_func_cfg_input req = {0};
3553         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3554         int rc = 0;
3555
3556         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3557
3558         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3559         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3560         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3561         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3562
3563         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3564
3565         HWRM_CHECK_RESULT();
3566         HWRM_UNLOCK();
3567
3568         return rc;
3569 }
3570
3571 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3572 {
3573         int rc;
3574
3575         if (BNXT_PF(bp))
3576                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3577         else
3578                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3579
3580         return rc;
3581 }
3582
3583 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3584                               void *encaped, size_t ec_size)
3585 {
3586         int rc = 0;
3587         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3588         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3589
3590         if (ec_size > sizeof(req.encap_request))
3591                 return -1;
3592
3593         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3594
3595         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3596         memcpy(req.encap_request, encaped, ec_size);
3597
3598         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3599
3600         HWRM_CHECK_RESULT();
3601         HWRM_UNLOCK();
3602
3603         return rc;
3604 }
3605
3606 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3607                                        struct rte_ether_addr *mac)
3608 {
3609         struct hwrm_func_qcfg_input req = {0};
3610         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3611         int rc;
3612
3613         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3614
3615         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3616         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3617
3618         HWRM_CHECK_RESULT();
3619
3620         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3621
3622         HWRM_UNLOCK();
3623
3624         return rc;
3625 }
3626
3627 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3628                             void *encaped, size_t ec_size)
3629 {
3630         int rc = 0;
3631         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3632         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3633
3634         if (ec_size > sizeof(req.encap_request))
3635                 return -1;
3636
3637         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3638
3639         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3640         memcpy(req.encap_request, encaped, ec_size);
3641
3642         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3643
3644         HWRM_CHECK_RESULT();
3645         HWRM_UNLOCK();
3646
3647         return rc;
3648 }
3649
3650 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3651                          struct rte_eth_stats *stats, uint8_t rx)
3652 {
3653         int rc = 0;
3654         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3655         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3656
3657         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3658
3659         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3660
3661         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3662
3663         HWRM_CHECK_RESULT();
3664
3665         if (rx) {
3666                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3667                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3668                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3669                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3670                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3671                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3672                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3673                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3674         } else {
3675                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3676                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3677                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3678                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3679                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3680                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3681         }
3682
3683         HWRM_UNLOCK();
3684
3685         return rc;
3686 }
3687
3688 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3689 {
3690         struct hwrm_port_qstats_input req = {0};
3691         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3692         struct bnxt_pf_info *pf = &bp->pf;
3693         int rc;
3694
3695         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3696
3697         req.port_id = rte_cpu_to_le_16(pf->port_id);
3698         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3699         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3700         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3701
3702         HWRM_CHECK_RESULT();
3703         HWRM_UNLOCK();
3704
3705         return rc;
3706 }
3707
3708 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3709 {
3710         struct hwrm_port_clr_stats_input req = {0};
3711         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3712         struct bnxt_pf_info *pf = &bp->pf;
3713         int rc;
3714
3715         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3716         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3717             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3718                 return 0;
3719
3720         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3721
3722         req.port_id = rte_cpu_to_le_16(pf->port_id);
3723         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3724
3725         HWRM_CHECK_RESULT();
3726         HWRM_UNLOCK();
3727
3728         return rc;
3729 }
3730
3731 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3732 {
3733         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3734         struct hwrm_port_led_qcaps_input req = {0};
3735         int rc;
3736
3737         if (BNXT_VF(bp))
3738                 return 0;
3739
3740         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3741         req.port_id = bp->pf.port_id;
3742         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3743
3744         HWRM_CHECK_RESULT();
3745
3746         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3747                 unsigned int i;
3748
3749                 bp->num_leds = resp->num_leds;
3750                 memcpy(bp->leds, &resp->led0_id,
3751                         sizeof(bp->leds[0]) * bp->num_leds);
3752                 for (i = 0; i < bp->num_leds; i++) {
3753                         struct bnxt_led_info *led = &bp->leds[i];
3754
3755                         uint16_t caps = led->led_state_caps;
3756
3757                         if (!led->led_group_id ||
3758                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3759                                 bp->num_leds = 0;
3760                                 break;
3761                         }
3762                 }
3763         }
3764
3765         HWRM_UNLOCK();
3766
3767         return rc;
3768 }
3769
3770 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3771 {
3772         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3773         struct hwrm_port_led_cfg_input req = {0};
3774         struct bnxt_led_cfg *led_cfg;
3775         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3776         uint16_t duration = 0;
3777         int rc, i;
3778
3779         if (!bp->num_leds || BNXT_VF(bp))
3780                 return -EOPNOTSUPP;
3781
3782         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3783
3784         if (led_on) {
3785                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3786                 duration = rte_cpu_to_le_16(500);
3787         }
3788         req.port_id = bp->pf.port_id;
3789         req.num_leds = bp->num_leds;
3790         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3791         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3792                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3793                 led_cfg->led_id = bp->leds[i].led_id;
3794                 led_cfg->led_state = led_state;
3795                 led_cfg->led_blink_on = duration;
3796                 led_cfg->led_blink_off = duration;
3797                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3798         }
3799
3800         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3801
3802         HWRM_CHECK_RESULT();
3803         HWRM_UNLOCK();
3804
3805         return rc;
3806 }
3807
3808 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3809                                uint32_t *length)
3810 {
3811         int rc;
3812         struct hwrm_nvm_get_dir_info_input req = {0};
3813         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3814
3815         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3816
3817         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3818
3819         HWRM_CHECK_RESULT();
3820
3821         *entries = rte_le_to_cpu_32(resp->entries);
3822         *length = rte_le_to_cpu_32(resp->entry_length);
3823
3824         HWRM_UNLOCK();
3825         return rc;
3826 }
3827
3828 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3829 {
3830         int rc;
3831         uint32_t dir_entries;
3832         uint32_t entry_length;
3833         uint8_t *buf;
3834         size_t buflen;
3835         rte_iova_t dma_handle;
3836         struct hwrm_nvm_get_dir_entries_input req = {0};
3837         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3838
3839         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3840         if (rc != 0)
3841                 return rc;
3842
3843         *data++ = dir_entries;
3844         *data++ = entry_length;
3845         len -= 2;
3846         memset(data, 0xff, len);
3847
3848         buflen = dir_entries * entry_length;
3849         buf = rte_malloc("nvm_dir", buflen, 0);
3850         if (buf == NULL)
3851                 return -ENOMEM;
3852         dma_handle = rte_malloc_virt2iova(buf);
3853         if (dma_handle == RTE_BAD_IOVA) {
3854                 PMD_DRV_LOG(ERR,
3855                         "unable to map response address to physical memory\n");
3856                 return -ENOMEM;
3857         }
3858         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3859         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3860         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3861
3862         if (rc == 0)
3863                 memcpy(data, buf, len > buflen ? buflen : len);
3864
3865         rte_free(buf);
3866         HWRM_CHECK_RESULT();
3867         HWRM_UNLOCK();
3868
3869         return rc;
3870 }
3871
3872 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3873                              uint32_t offset, uint32_t length,
3874                              uint8_t *data)
3875 {
3876         int rc;
3877         uint8_t *buf;
3878         rte_iova_t dma_handle;
3879         struct hwrm_nvm_read_input req = {0};
3880         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3881
3882         buf = rte_malloc("nvm_item", length, 0);
3883         if (!buf)
3884                 return -ENOMEM;
3885
3886         dma_handle = rte_malloc_virt2iova(buf);
3887         if (dma_handle == RTE_BAD_IOVA) {
3888                 PMD_DRV_LOG(ERR,
3889                         "unable to map response address to physical memory\n");
3890                 return -ENOMEM;
3891         }
3892         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3893         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3894         req.dir_idx = rte_cpu_to_le_16(index);
3895         req.offset = rte_cpu_to_le_32(offset);
3896         req.len = rte_cpu_to_le_32(length);
3897         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3898         if (rc == 0)
3899                 memcpy(data, buf, length);
3900
3901         rte_free(buf);
3902         HWRM_CHECK_RESULT();
3903         HWRM_UNLOCK();
3904
3905         return rc;
3906 }
3907
3908 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3909 {
3910         int rc;
3911         struct hwrm_nvm_erase_dir_entry_input req = {0};
3912         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3913
3914         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3915         req.dir_idx = rte_cpu_to_le_16(index);
3916         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3917         HWRM_CHECK_RESULT();
3918         HWRM_UNLOCK();
3919
3920         return rc;
3921 }
3922
3923
3924 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3925                           uint16_t dir_ordinal, uint16_t dir_ext,
3926                           uint16_t dir_attr, const uint8_t *data,
3927                           size_t data_len)
3928 {
3929         int rc;
3930         struct hwrm_nvm_write_input req = {0};
3931         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3932         rte_iova_t dma_handle;
3933         uint8_t *buf;
3934
3935         buf = rte_malloc("nvm_write", data_len, 0);
3936         if (!buf)
3937                 return -ENOMEM;
3938
3939         dma_handle = rte_malloc_virt2iova(buf);
3940         if (dma_handle == RTE_BAD_IOVA) {
3941                 PMD_DRV_LOG(ERR,
3942                         "unable to map response address to physical memory\n");
3943                 return -ENOMEM;
3944         }
3945         memcpy(buf, data, data_len);
3946
3947         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3948
3949         req.dir_type = rte_cpu_to_le_16(dir_type);
3950         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3951         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3952         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3953         req.dir_data_length = rte_cpu_to_le_32(data_len);
3954         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3955
3956         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3957
3958         rte_free(buf);
3959         HWRM_CHECK_RESULT();
3960         HWRM_UNLOCK();
3961
3962         return rc;
3963 }
3964
3965 static void
3966 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3967 {
3968         uint32_t *count = cbdata;
3969
3970         *count = *count + 1;
3971 }
3972
3973 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3974                                      struct bnxt_vnic_info *vnic __rte_unused)
3975 {
3976         return 0;
3977 }
3978
3979 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3980 {
3981         uint32_t count = 0;
3982
3983         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3984             &count, bnxt_vnic_count_hwrm_stub);
3985
3986         return count;
3987 }
3988
3989 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3990                                         uint16_t *vnic_ids)
3991 {
3992         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3993         struct hwrm_func_vf_vnic_ids_query_output *resp =
3994                                                 bp->hwrm_cmd_resp_addr;
3995         int rc;
3996
3997         /* First query all VNIC ids */
3998         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3999
4000         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
4001         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
4002         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4003
4004         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4005                 HWRM_UNLOCK();
4006                 PMD_DRV_LOG(ERR,
4007                 "unable to map VNIC ID table address to physical memory\n");
4008                 return -ENOMEM;
4009         }
4010         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4011         HWRM_CHECK_RESULT();
4012         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4013
4014         HWRM_UNLOCK();
4015
4016         return rc;
4017 }
4018
4019 /*
4020  * This function queries the VNIC IDs  for a specified VF. It then calls
4021  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4022  * Then it calls the hwrm_cb function to program this new vnic configuration.
4023  */
4024 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4025         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4026         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4027 {
4028         struct bnxt_vnic_info vnic;
4029         int rc = 0;
4030         int i, num_vnic_ids;
4031         uint16_t *vnic_ids;
4032         size_t vnic_id_sz;
4033         size_t sz;
4034
4035         /* First query all VNIC ids */
4036         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4037         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4038                         RTE_CACHE_LINE_SIZE);
4039         if (vnic_ids == NULL)
4040                 return -ENOMEM;
4041
4042         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4043                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4044
4045         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4046
4047         if (num_vnic_ids < 0)
4048                 return num_vnic_ids;
4049
4050         /* Retrieve VNIC, update bd_stall then update */
4051
4052         for (i = 0; i < num_vnic_ids; i++) {
4053                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4054                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4055                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4056                 if (rc)
4057                         break;
4058                 if (vnic.mru <= 4)      /* Indicates unallocated */
4059                         continue;
4060
4061                 vnic_cb(&vnic, cbdata);
4062
4063                 rc = hwrm_cb(bp, &vnic);
4064                 if (rc)
4065                         break;
4066         }
4067
4068         rte_free(vnic_ids);
4069
4070         return rc;
4071 }
4072
4073 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4074                                               bool on)
4075 {
4076         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4077         struct hwrm_func_cfg_input req = {0};
4078         int rc;
4079
4080         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4081
4082         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4083         req.enables |= rte_cpu_to_le_32(
4084                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4085         req.vlan_antispoof_mode = on ?
4086                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4087                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4088         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4089
4090         HWRM_CHECK_RESULT();
4091         HWRM_UNLOCK();
4092
4093         return rc;
4094 }
4095
4096 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4097 {
4098         struct bnxt_vnic_info vnic;
4099         uint16_t *vnic_ids;
4100         size_t vnic_id_sz;
4101         int num_vnic_ids, i;
4102         size_t sz;
4103         int rc;
4104
4105         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4106         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4107                         RTE_CACHE_LINE_SIZE);
4108         if (vnic_ids == NULL)
4109                 return -ENOMEM;
4110
4111         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4112                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4113
4114         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4115         if (rc <= 0)
4116                 goto exit;
4117         num_vnic_ids = rc;
4118
4119         /*
4120          * Loop through to find the default VNIC ID.
4121          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4122          * by sending the hwrm_func_qcfg command to the firmware.
4123          */
4124         for (i = 0; i < num_vnic_ids; i++) {
4125                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4126                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4127                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4128                                         bp->pf.first_vf_id + vf);
4129                 if (rc)
4130                         goto exit;
4131                 if (vnic.func_default) {
4132                         rte_free(vnic_ids);
4133                         return vnic.fw_vnic_id;
4134                 }
4135         }
4136         /* Could not find a default VNIC. */
4137         PMD_DRV_LOG(ERR, "No default VNIC\n");
4138 exit:
4139         rte_free(vnic_ids);
4140         return rc;
4141 }
4142
4143 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4144                          uint16_t dst_id,
4145                          struct bnxt_filter_info *filter)
4146 {
4147         int rc = 0;
4148         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4149         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4150         uint32_t enables = 0;
4151
4152         if (filter->fw_em_filter_id != UINT64_MAX)
4153                 bnxt_hwrm_clear_em_filter(bp, filter);
4154
4155         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4156
4157         req.flags = rte_cpu_to_le_32(filter->flags);
4158
4159         enables = filter->enables |
4160               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4161         req.dst_id = rte_cpu_to_le_16(dst_id);
4162
4163         if (filter->ip_addr_type) {
4164                 req.ip_addr_type = filter->ip_addr_type;
4165                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4166         }
4167         if (enables &
4168             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4169                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4170         if (enables &
4171             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4172                 memcpy(req.src_macaddr, filter->src_macaddr,
4173                        RTE_ETHER_ADDR_LEN);
4174         if (enables &
4175             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4176                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4177                        RTE_ETHER_ADDR_LEN);
4178         if (enables &
4179             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4180                 req.ovlan_vid = filter->l2_ovlan;
4181         if (enables &
4182             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4183                 req.ivlan_vid = filter->l2_ivlan;
4184         if (enables &
4185             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4186                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4187         if (enables &
4188             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4189                 req.ip_protocol = filter->ip_protocol;
4190         if (enables &
4191             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4192                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4193         if (enables &
4194             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4195                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4196         if (enables &
4197             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4198                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4199         if (enables &
4200             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4201                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4202         if (enables &
4203             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4204                 req.mirror_vnic_id = filter->mirror_vnic_id;
4205
4206         req.enables = rte_cpu_to_le_32(enables);
4207
4208         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4209
4210         HWRM_CHECK_RESULT();
4211
4212         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4213         HWRM_UNLOCK();
4214
4215         return rc;
4216 }
4217
4218 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4219 {
4220         int rc = 0;
4221         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4222         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4223
4224         if (filter->fw_em_filter_id == UINT64_MAX)
4225                 return 0;
4226
4227         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4228
4229         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4230
4231         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4232
4233         HWRM_CHECK_RESULT();
4234         HWRM_UNLOCK();
4235
4236         filter->fw_em_filter_id = UINT64_MAX;
4237         filter->fw_l2_filter_id = UINT64_MAX;
4238
4239         return 0;
4240 }
4241
4242 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4243                          uint16_t dst_id,
4244                          struct bnxt_filter_info *filter)
4245 {
4246         int rc = 0;
4247         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4248         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4249                                                 bp->hwrm_cmd_resp_addr;
4250         uint32_t enables = 0;
4251
4252         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4253                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4254
4255         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4256
4257         req.flags = rte_cpu_to_le_32(filter->flags);
4258
4259         enables = filter->enables |
4260               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4261         req.dst_id = rte_cpu_to_le_16(dst_id);
4262
4263         if (filter->ip_addr_type) {
4264                 req.ip_addr_type = filter->ip_addr_type;
4265                 enables |=
4266                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4267         }
4268         if (enables &
4269             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4270                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4271         if (enables &
4272             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4273                 memcpy(req.src_macaddr, filter->src_macaddr,
4274                        RTE_ETHER_ADDR_LEN);
4275         if (enables &
4276             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4277                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4278         if (enables &
4279             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4280                 req.ip_protocol = filter->ip_protocol;
4281         if (enables &
4282             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4283                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4284         if (enables &
4285             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4286                 req.src_ipaddr_mask[0] =
4287                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4288         if (enables &
4289             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4290                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4291         if (enables &
4292             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4293                 req.dst_ipaddr_mask[0] =
4294                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4295         if (enables &
4296             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4297                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4298         if (enables &
4299             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4300                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4301         if (enables &
4302             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4303                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4304         if (enables &
4305             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4306                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4307         if (enables &
4308             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4309                 req.mirror_vnic_id = filter->mirror_vnic_id;
4310
4311         req.enables = rte_cpu_to_le_32(enables);
4312
4313         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4314
4315         HWRM_CHECK_RESULT();
4316
4317         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4318         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4319         HWRM_UNLOCK();
4320
4321         return rc;
4322 }
4323
4324 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4325                                 struct bnxt_filter_info *filter)
4326 {
4327         int rc = 0;
4328         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4329         struct hwrm_cfa_ntuple_filter_free_output *resp =
4330                                                 bp->hwrm_cmd_resp_addr;
4331
4332         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4333                 return 0;
4334
4335         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4336
4337         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4338
4339         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4340
4341         HWRM_CHECK_RESULT();
4342         HWRM_UNLOCK();
4343
4344         filter->fw_ntuple_filter_id = UINT64_MAX;
4345
4346         return 0;
4347 }
4348
4349 static int
4350 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4351 {
4352         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4353         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4354         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4355         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4356         uint16_t *ring_tbl = vnic->rss_table;
4357         int nr_ctxs = vnic->num_lb_ctxts;
4358         int max_rings = bp->rx_nr_rings;
4359         int i, j, k, cnt;
4360         int rc = 0;
4361
4362         for (i = 0, k = 0; i < nr_ctxs; i++) {
4363                 struct bnxt_rx_ring_info *rxr;
4364                 struct bnxt_cp_ring_info *cpr;
4365
4366                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4367
4368                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4369                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4370                 req.hash_mode_flags = vnic->hash_mode;
4371
4372                 req.ring_grp_tbl_addr =
4373                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4374                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4375                                      2 * sizeof(*ring_tbl));
4376                 req.hash_key_tbl_addr =
4377                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4378
4379                 req.ring_table_pair_index = i;
4380                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4381
4382                 for (j = 0; j < 64; j++) {
4383                         uint16_t ring_id;
4384
4385                         /* Find next active ring. */
4386                         for (cnt = 0; cnt < max_rings; cnt++) {
4387                                 if (rx_queue_state[k] !=
4388                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4389                                         break;
4390                                 if (++k == max_rings)
4391                                         k = 0;
4392                         }
4393
4394                         /* Return if no rings are active. */
4395                         if (cnt == max_rings) {
4396                                 HWRM_UNLOCK();
4397                                 return 0;
4398                         }
4399
4400                         /* Add rx/cp ring pair to RSS table. */
4401                         rxr = rxqs[k]->rx_ring;
4402                         cpr = rxqs[k]->cp_ring;
4403
4404                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4405                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4406                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4407                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4408
4409                         if (++k == max_rings)
4410                                 k = 0;
4411                 }
4412                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4413                                             BNXT_USE_CHIMP_MB);
4414
4415                 HWRM_CHECK_RESULT();
4416                 HWRM_UNLOCK();
4417         }
4418
4419         return rc;
4420 }
4421
4422 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4423 {
4424         unsigned int rss_idx, fw_idx, i;
4425
4426         if (!(vnic->rss_table && vnic->hash_type))
4427                 return 0;
4428
4429         if (BNXT_CHIP_THOR(bp))
4430                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4431
4432         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4433                 return 0;
4434
4435         if (vnic->rss_table && vnic->hash_type) {
4436                 /*
4437                  * Fill the RSS hash & redirection table with
4438                  * ring group ids for all VNICs
4439                  */
4440                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4441                         rss_idx++, fw_idx++) {
4442                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4443                                 fw_idx %= bp->rx_cp_nr_rings;
4444                                 if (vnic->fw_grp_ids[fw_idx] !=
4445                                     INVALID_HW_RING_ID)
4446                                         break;
4447                                 fw_idx++;
4448                         }
4449                         if (i == bp->rx_cp_nr_rings)
4450                                 return 0;
4451                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4452                 }
4453                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4454         }
4455
4456         return 0;
4457 }
4458
4459 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4460         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4461 {
4462         uint16_t flags;
4463
4464         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4465
4466         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4467         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4468
4469         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4470         req->num_cmpl_dma_aggr_during_int =
4471                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4472
4473         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4474
4475         /* min timer set to 1/2 of interrupt timer */
4476         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4477
4478         /* buf timer set to 1/4 of interrupt timer */
4479         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4480
4481         req->cmpl_aggr_dma_tmr_during_int =
4482                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4483
4484         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4485                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4486         req->flags = rte_cpu_to_le_16(flags);
4487 }
4488
4489 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4490                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4491 {
4492         struct hwrm_ring_aggint_qcaps_input req = {0};
4493         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4494         uint32_t enables;
4495         uint16_t flags;
4496         int rc;
4497
4498         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4499         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4500         HWRM_CHECK_RESULT();
4501
4502         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4503         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4504
4505         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4506                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4507         agg_req->flags = rte_cpu_to_le_16(flags);
4508         enables =
4509          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4510          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4511         agg_req->enables = rte_cpu_to_le_32(enables);
4512
4513         HWRM_UNLOCK();
4514         return rc;
4515 }
4516
4517 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4518                         struct bnxt_coal *coal, uint16_t ring_id)
4519 {
4520         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4521         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4522                                                 bp->hwrm_cmd_resp_addr;
4523         int rc;
4524
4525         /* Set ring coalesce parameters only for 100G NICs */
4526         if (BNXT_CHIP_THOR(bp)) {
4527                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4528                         return -1;
4529         } else if (bnxt_stratus_device(bp)) {
4530                 bnxt_hwrm_set_coal_params(coal, &req);
4531         } else {
4532                 return 0;
4533         }
4534
4535         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4536         req.ring_id = rte_cpu_to_le_16(ring_id);
4537         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4538         HWRM_CHECK_RESULT();
4539         HWRM_UNLOCK();
4540         return 0;
4541 }
4542
4543 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4544 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4545 {
4546         struct hwrm_func_backing_store_qcaps_input req = {0};
4547         struct hwrm_func_backing_store_qcaps_output *resp =
4548                 bp->hwrm_cmd_resp_addr;
4549         struct bnxt_ctx_pg_info *ctx_pg;
4550         struct bnxt_ctx_mem_info *ctx;
4551         int total_alloc_len;
4552         int rc, i;
4553
4554         if (!BNXT_CHIP_THOR(bp) ||
4555             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4556             BNXT_VF(bp) ||
4557             bp->ctx)
4558                 return 0;
4559
4560         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4561         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4562         HWRM_CHECK_RESULT_SILENT();
4563
4564         total_alloc_len = sizeof(*ctx);
4565         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4566                           RTE_CACHE_LINE_SIZE);
4567         if (!ctx) {
4568                 rc = -ENOMEM;
4569                 goto ctx_err;
4570         }
4571
4572         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4573                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4574                             RTE_CACHE_LINE_SIZE);
4575         if (!ctx_pg) {
4576                 rc = -ENOMEM;
4577                 goto ctx_err;
4578         }
4579         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4580                 ctx->tqm_mem[i] = ctx_pg;
4581
4582         bp->ctx = ctx;
4583         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4584         ctx->qp_min_qp1_entries =
4585                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4586         ctx->qp_max_l2_entries =
4587                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4588         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4589         ctx->srq_max_l2_entries =
4590                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4591         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4592         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4593         ctx->cq_max_l2_entries =
4594                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4595         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4596         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4597         ctx->vnic_max_vnic_entries =
4598                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4599         ctx->vnic_max_ring_table_entries =
4600                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4601         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4602         ctx->stat_max_entries =
4603                 rte_le_to_cpu_32(resp->stat_max_entries);
4604         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4605         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4606         ctx->tqm_min_entries_per_ring =
4607                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4608         ctx->tqm_max_entries_per_ring =
4609                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4610         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4611         if (!ctx->tqm_entries_multiple)
4612                 ctx->tqm_entries_multiple = 1;
4613         ctx->mrav_max_entries =
4614                 rte_le_to_cpu_32(resp->mrav_max_entries);
4615         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4616         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4617         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4618 ctx_err:
4619         HWRM_UNLOCK();
4620         return rc;
4621 }
4622
4623 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4624 {
4625         struct hwrm_func_backing_store_cfg_input req = {0};
4626         struct hwrm_func_backing_store_cfg_output *resp =
4627                 bp->hwrm_cmd_resp_addr;
4628         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4629         struct bnxt_ctx_pg_info *ctx_pg;
4630         uint32_t *num_entries;
4631         uint64_t *pg_dir;
4632         uint8_t *pg_attr;
4633         uint32_t ena;
4634         int i, rc;
4635
4636         if (!ctx)
4637                 return 0;
4638
4639         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4640         req.enables = rte_cpu_to_le_32(enables);
4641
4642         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4643                 ctx_pg = &ctx->qp_mem;
4644                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4645                 req.qp_num_qp1_entries =
4646                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4647                 req.qp_num_l2_entries =
4648                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4649                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4650                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4651                                       &req.qpc_pg_size_qpc_lvl,
4652                                       &req.qpc_page_dir);
4653         }
4654
4655         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4656                 ctx_pg = &ctx->srq_mem;
4657                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4658                 req.srq_num_l2_entries =
4659                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4660                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4661                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4662                                       &req.srq_pg_size_srq_lvl,
4663                                       &req.srq_page_dir);
4664         }
4665
4666         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4667                 ctx_pg = &ctx->cq_mem;
4668                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4669                 req.cq_num_l2_entries =
4670                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4671                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4672                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4673                                       &req.cq_pg_size_cq_lvl,
4674                                       &req.cq_page_dir);
4675         }
4676
4677         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4678                 ctx_pg = &ctx->vnic_mem;
4679                 req.vnic_num_vnic_entries =
4680                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4681                 req.vnic_num_ring_table_entries =
4682                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4683                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4684                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4685                                       &req.vnic_pg_size_vnic_lvl,
4686                                       &req.vnic_page_dir);
4687         }
4688
4689         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4690                 ctx_pg = &ctx->stat_mem;
4691                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4692                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4693                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4694                                       &req.stat_pg_size_stat_lvl,
4695                                       &req.stat_page_dir);
4696         }
4697
4698         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4699         num_entries = &req.tqm_sp_num_entries;
4700         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4701         pg_dir = &req.tqm_sp_page_dir;
4702         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4703         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4704                 if (!(enables & ena))
4705                         continue;
4706
4707                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4708
4709                 ctx_pg = ctx->tqm_mem[i];
4710                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4711                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4712         }
4713
4714         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4715         HWRM_CHECK_RESULT();
4716         HWRM_UNLOCK();
4717
4718         return rc;
4719 }
4720
4721 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4722 {
4723         struct hwrm_port_qstats_ext_input req = {0};
4724         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4725         struct bnxt_pf_info *pf = &bp->pf;
4726         int rc;
4727
4728         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4729               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4730                 return 0;
4731
4732         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4733
4734         req.port_id = rte_cpu_to_le_16(pf->port_id);
4735         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4736                 req.tx_stat_host_addr =
4737                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4738                 req.tx_stat_size =
4739                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4740         }
4741         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4742                 req.rx_stat_host_addr =
4743                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4744                 req.rx_stat_size =
4745                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4746         }
4747         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4748
4749         if (rc) {
4750                 bp->fw_rx_port_stats_ext_size = 0;
4751                 bp->fw_tx_port_stats_ext_size = 0;
4752         } else {
4753                 bp->fw_rx_port_stats_ext_size =
4754                         rte_le_to_cpu_16(resp->rx_stat_size);
4755                 bp->fw_tx_port_stats_ext_size =
4756                         rte_le_to_cpu_16(resp->tx_stat_size);
4757         }
4758
4759         HWRM_CHECK_RESULT();
4760         HWRM_UNLOCK();
4761
4762         return rc;
4763 }
4764
4765 int
4766 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4767 {
4768         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4769         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4770                 bp->hwrm_cmd_resp_addr;
4771         int rc = 0;
4772
4773         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4774         req.tunnel_type = type;
4775         req.dest_fid = bp->fw_fid;
4776         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4777         HWRM_CHECK_RESULT();
4778
4779         HWRM_UNLOCK();
4780
4781         return rc;
4782 }
4783
4784 int
4785 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4786 {
4787         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4788         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4789                 bp->hwrm_cmd_resp_addr;
4790         int rc = 0;
4791
4792         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4793         req.tunnel_type = type;
4794         req.dest_fid = bp->fw_fid;
4795         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4796         HWRM_CHECK_RESULT();
4797
4798         HWRM_UNLOCK();
4799
4800         return rc;
4801 }
4802
4803 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4804 {
4805         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4806         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4807                 bp->hwrm_cmd_resp_addr;
4808         int rc = 0;
4809
4810         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4811         req.src_fid = bp->fw_fid;
4812         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4813         HWRM_CHECK_RESULT();
4814
4815         if (type)
4816                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4817
4818         HWRM_UNLOCK();
4819
4820         return rc;
4821 }
4822
4823 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4824                                    uint16_t *dst_fid)
4825 {
4826         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4827         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4828                 bp->hwrm_cmd_resp_addr;
4829         int rc = 0;
4830
4831         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4832         req.src_fid = bp->fw_fid;
4833         req.tunnel_type = tun_type;
4834         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4835         HWRM_CHECK_RESULT();
4836
4837         if (dst_fid)
4838                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4839
4840         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4841
4842         HWRM_UNLOCK();
4843
4844         return rc;
4845 }
4846
4847 int bnxt_hwrm_set_mac(struct bnxt *bp)
4848 {
4849         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4850         struct hwrm_func_vf_cfg_input req = {0};
4851         int rc = 0;
4852
4853         if (!BNXT_VF(bp))
4854                 return 0;
4855
4856         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4857
4858         req.enables =
4859                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4860         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4861
4862         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4863
4864         HWRM_CHECK_RESULT();
4865
4866         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4867         HWRM_UNLOCK();
4868
4869         return rc;
4870 }
4871
4872 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4873 {
4874         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4875         struct hwrm_func_drv_if_change_input req = {0};
4876         uint32_t flags;
4877         int rc;
4878
4879         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
4880                 return 0;
4881
4882         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4883          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4884          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4885          */
4886         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4887                 return 0;
4888
4889         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4890
4891         if (up)
4892                 req.flags =
4893                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4894
4895         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4896
4897         HWRM_CHECK_RESULT();
4898         flags = rte_le_to_cpu_32(resp->flags);
4899         HWRM_UNLOCK();
4900
4901         if (!up)
4902                 return 0;
4903
4904         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4905                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4906                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4907         }
4908
4909         return 0;
4910 }
4911
4912 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4913 {
4914         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4915         struct bnxt_error_recovery_info *info = bp->recovery_info;
4916         struct hwrm_error_recovery_qcfg_input req = {0};
4917         uint32_t flags = 0;
4918         unsigned int i;
4919         int rc;
4920
4921         /* Older FW does not have error recovery support */
4922         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4923                 return 0;
4924
4925         if (!info) {
4926                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4927                                    sizeof(*info), 0);
4928                 bp->recovery_info = info;
4929                 if (info == NULL)
4930                         return -ENOMEM;
4931         } else {
4932                 memset(info, 0, sizeof(*info));
4933         }
4934
4935         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4936
4937         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4938
4939         HWRM_CHECK_RESULT();
4940
4941         flags = rte_le_to_cpu_32(resp->flags);
4942         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4943                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4944         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4945                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4946
4947         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4948             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4949                 rc = -EINVAL;
4950                 goto err;
4951         }
4952
4953         /* FW returned values are in units of 100msec */
4954         info->driver_polling_freq =
4955                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4956         info->master_func_wait_period =
4957                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4958         info->normal_func_wait_period =
4959                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4960         info->master_func_wait_period_after_reset =
4961                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4962         info->max_bailout_time_after_reset =
4963                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4964         info->status_regs[BNXT_FW_STATUS_REG] =
4965                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4966         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4967                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4968         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4969                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4970         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4971                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4972         info->reg_array_cnt =
4973                 rte_le_to_cpu_32(resp->reg_array_cnt);
4974
4975         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4976                 rc = -EINVAL;
4977                 goto err;
4978         }
4979
4980         for (i = 0; i < info->reg_array_cnt; i++) {
4981                 info->reset_reg[i] =
4982                         rte_le_to_cpu_32(resp->reset_reg[i]);
4983                 info->reset_reg_val[i] =
4984                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4985                 info->delay_after_reset[i] =
4986                         resp->delay_after_reset[i];
4987         }
4988 err:
4989         HWRM_UNLOCK();
4990
4991         /* Map the FW status registers */
4992         if (!rc)
4993                 rc = bnxt_map_fw_health_status_regs(bp);
4994
4995         if (rc) {
4996                 rte_free(bp->recovery_info);
4997                 bp->recovery_info = NULL;
4998         }
4999         return rc;
5000 }
5001
5002 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5003 {
5004         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5005         struct hwrm_fw_reset_input req = {0};
5006         int rc;
5007
5008         if (!BNXT_PF(bp))
5009                 return -EOPNOTSUPP;
5010
5011         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
5012
5013         req.embedded_proc_type =
5014                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5015         req.selfrst_status =
5016                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5017         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5018
5019         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5020                                     BNXT_USE_KONG(bp));
5021
5022         HWRM_CHECK_RESULT();
5023         HWRM_UNLOCK();
5024
5025         return rc;
5026 }
5027
5028 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5029 {
5030         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5031         struct hwrm_port_ts_query_input req = {0};
5032         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5033         uint32_t flags = 0;
5034         int rc;
5035
5036         if (!ptp)
5037                 return 0;
5038
5039         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5040
5041         switch (path) {
5042         case BNXT_PTP_FLAGS_PATH_TX:
5043                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5044                 break;
5045         case BNXT_PTP_FLAGS_PATH_RX:
5046                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5047                 break;
5048         case BNXT_PTP_FLAGS_CURRENT_TIME:
5049                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5050                 break;
5051         }
5052
5053         req.flags = rte_cpu_to_le_32(flags);
5054         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5055
5056         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5057
5058         HWRM_CHECK_RESULT();
5059
5060         if (timestamp) {
5061                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5062                 *timestamp |=
5063                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5064         }
5065         HWRM_UNLOCK();
5066
5067         return rc;
5068 }
5069
5070 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5071 {
5072         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5073                                         bp->hwrm_cmd_resp_addr;
5074         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5075         uint32_t flags = 0;
5076         int rc = 0;
5077
5078         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5079                 return rc;
5080
5081         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5082                 PMD_DRV_LOG(DEBUG,
5083                             "Not a PF or trusted VF. Command not supported\n");
5084                 return 0;
5085         }
5086
5087         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5088         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5089
5090         HWRM_CHECK_RESULT();
5091         flags = rte_le_to_cpu_32(resp->flags);
5092         HWRM_UNLOCK();
5093
5094         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5095                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5096                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5097         }
5098
5099         return rc;
5100 }