1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 6000000
30 #define HWRM_SHORT_CMD_TIMEOUT 50000
31 #define HWRM_SPEC_CODE_1_8_3 0x10803
32 #define HWRM_VERSION_1_9_1 0x10901
33 #define HWRM_VERSION_1_9_2 0x10903
35 struct bnxt_plcmodes_cfg {
37 uint16_t jumbo_thresh;
39 uint16_t hds_threshold;
42 static int page_getenum(size_t size)
58 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
59 return sizeof(void *) * 8 - 1;
62 static int page_roundup(size_t size)
64 return 1 << page_getenum(size);
67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
71 if (rmem->nr_pages > 1) {
73 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
75 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
80 * HWRM Functions (sent to HWRM)
81 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
82 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
83 * command was failed by the ChiMP.
86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
87 uint32_t msg_len, bool use_kong_mb)
90 struct input *req = msg;
91 struct output *resp = bp->hwrm_cmd_resp_addr;
95 uint16_t max_req_len = bp->max_req_len;
96 struct hwrm_short_input short_input = { 0 };
97 uint16_t bar_offset = use_kong_mb ?
98 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
99 uint16_t mb_trigger_offset = use_kong_mb ?
100 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
103 /* Do not send HWRM commands to firmware in error state */
104 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
107 /* For VER_GET command, set timeout as 50ms */
108 if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
109 timeout = HWRM_SHORT_CMD_TIMEOUT;
111 timeout = HWRM_CMD_TIMEOUT;
113 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
114 msg_len > bp->max_req_len) {
115 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
117 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
118 memcpy(short_cmd_req, req, msg_len);
120 short_input.req_type = rte_cpu_to_le_16(req->req_type);
121 short_input.signature = rte_cpu_to_le_16(
122 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
123 short_input.size = rte_cpu_to_le_16(msg_len);
124 short_input.req_addr =
125 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
127 data = (uint32_t *)&short_input;
128 msg_len = sizeof(short_input);
130 /* Sync memory write before updating doorbell */
133 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
136 /* Write request msg to hwrm channel */
137 for (i = 0; i < msg_len; i += 4) {
138 bar = (uint8_t *)bp->bar0 + bar_offset + i;
139 rte_write32(*data, bar);
143 /* Zero the rest of the request space */
144 for (; i < max_req_len; i += 4) {
145 bar = (uint8_t *)bp->bar0 + bar_offset + i;
149 /* Ring channel doorbell */
150 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
153 /* Poll for the valid bit */
154 for (i = 0; i < timeout; i++) {
155 /* Sanity check on the resp->resp_len */
157 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
158 /* Last byte of resp contains the valid key */
159 valid = (uint8_t *)resp + resp->resp_len - 1;
160 if (*valid == HWRM_RESP_VALID_KEY)
167 /* Suppress VER_GET timeout messages during reset recovery */
168 if (bp->flags & BNXT_FLAG_FW_RESET &&
169 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
172 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
180 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
181 * spinlock, and does initial processing.
183 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
184 * releases the spinlock only if it returns. If the regular int return codes
185 * are not used by the function, HWRM_CHECK_RESULT() should not be used
186 * directly, rather it should be copied and modified to suit the function.
188 * HWRM_UNLOCK() must be called after all response processing is completed.
190 #define HWRM_PREP(req, type, kong) do { \
191 rte_spinlock_lock(&bp->hwrm_lock); \
192 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
193 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
194 req.cmpl_ring = rte_cpu_to_le_16(-1); \
195 req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
196 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
197 req.target_id = rte_cpu_to_le_16(0xffff); \
198 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
201 #define HWRM_CHECK_RESULT_SILENT() do {\
203 rte_spinlock_unlock(&bp->hwrm_lock); \
206 if (resp->error_code) { \
207 rc = rte_le_to_cpu_16(resp->error_code); \
208 rte_spinlock_unlock(&bp->hwrm_lock); \
213 #define HWRM_CHECK_RESULT() do {\
215 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
216 rte_spinlock_unlock(&bp->hwrm_lock); \
217 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
223 if (resp->error_code) { \
224 rc = rte_le_to_cpu_16(resp->error_code); \
225 if (resp->resp_len >= 16) { \
226 struct hwrm_err_output *tmp_hwrm_err_op = \
229 "error %d:%d:%08x:%04x\n", \
230 rc, tmp_hwrm_err_op->cmd_err, \
232 tmp_hwrm_err_op->opaque_0), \
234 tmp_hwrm_err_op->opaque_1)); \
236 PMD_DRV_LOG(ERR, "error %d\n", rc); \
238 rte_spinlock_unlock(&bp->hwrm_lock); \
239 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
247 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
249 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
252 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
253 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
255 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
256 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
259 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
267 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
268 struct bnxt_vnic_info *vnic,
270 struct bnxt_vlan_table_entry *vlan_table)
273 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
274 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
277 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
280 HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
281 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
283 /* FIXME add multicast flag, when multicast adding options is supported
286 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
287 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
288 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
289 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
290 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
291 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
292 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
293 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
294 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
295 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
296 if (vnic->mc_addr_cnt) {
297 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
298 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
299 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
302 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
303 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
304 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
305 rte_mem_virt2iova(vlan_table));
306 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
308 req.mask = rte_cpu_to_le_32(mask);
310 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
318 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
320 struct bnxt_vlan_antispoof_table_entry *vlan_table)
323 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
324 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
325 bp->hwrm_cmd_resp_addr;
328 * Older HWRM versions did not support this command, and the set_rx_mask
329 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
330 * removed from set_rx_mask call, and this command was added.
332 * This command is also present from 1.7.8.11 and higher,
335 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
336 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
337 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
342 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
343 req.fid = rte_cpu_to_le_16(fid);
345 req.vlan_tag_mask_tbl_addr =
346 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
347 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
349 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
357 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
358 struct bnxt_filter_info *filter)
361 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
362 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
364 if (filter->fw_l2_filter_id == UINT64_MAX)
367 HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
369 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
371 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
376 filter->fw_l2_filter_id = UINT64_MAX;
381 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
383 struct bnxt_filter_info *filter)
386 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
387 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
388 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
389 const struct rte_eth_vmdq_rx_conf *conf =
390 &dev_conf->rx_adv_conf.vmdq_rx_conf;
391 uint32_t enables = 0;
392 uint16_t j = dst_id - 1;
394 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
395 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
396 conf->pool_map[j].pools & (1UL << j)) {
398 "Add vlan %u to vmdq pool %u\n",
399 conf->pool_map[j].vlan_id, j);
401 filter->l2_ivlan = conf->pool_map[j].vlan_id;
403 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
404 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
407 if (filter->fw_l2_filter_id != UINT64_MAX)
408 bnxt_hwrm_clear_l2_filter(bp, filter);
410 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
412 req.flags = rte_cpu_to_le_32(filter->flags);
414 rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
416 enables = filter->enables |
417 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
418 req.dst_id = rte_cpu_to_le_16(dst_id);
421 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
422 memcpy(req.l2_addr, filter->l2_addr,
425 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
426 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
429 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
430 req.l2_ovlan = filter->l2_ovlan;
432 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
433 req.l2_ivlan = filter->l2_ivlan;
435 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
436 req.l2_ovlan_mask = filter->l2_ovlan_mask;
438 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
439 req.l2_ivlan_mask = filter->l2_ivlan_mask;
440 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
441 req.src_id = rte_cpu_to_le_32(filter->src_id);
442 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
443 req.src_type = filter->src_type;
445 req.enables = rte_cpu_to_le_32(enables);
447 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
451 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
457 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
459 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
460 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
467 HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
470 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
473 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
474 if (ptp->tx_tstamp_en)
475 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
478 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
479 req.flags = rte_cpu_to_le_32(flags);
480 req.enables = rte_cpu_to_le_32
481 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
482 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
484 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
490 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
493 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
494 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
495 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
497 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
501 HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
503 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
505 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
509 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
512 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
516 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
517 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
518 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
519 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
520 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
521 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
522 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
523 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
524 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
525 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
526 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
527 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
528 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
529 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
530 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
531 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
532 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
533 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
541 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
544 struct hwrm_func_qcaps_input req = {.req_type = 0 };
545 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
546 uint16_t new_max_vfs;
550 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
552 req.fid = rte_cpu_to_le_16(0xffff);
554 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
558 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
559 flags = rte_le_to_cpu_32(resp->flags);
561 bp->pf.port_id = resp->port_id;
562 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
563 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
564 new_max_vfs = bp->pdev->max_vfs;
565 if (new_max_vfs != bp->pf.max_vfs) {
567 rte_free(bp->pf.vf_info);
568 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
569 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
570 bp->pf.max_vfs = new_max_vfs;
571 for (i = 0; i < new_max_vfs; i++) {
572 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
573 bp->pf.vf_info[i].vlan_table =
574 rte_zmalloc("VF VLAN table",
577 if (bp->pf.vf_info[i].vlan_table == NULL)
579 "Fail to alloc VLAN table for VF %d\n",
583 bp->pf.vf_info[i].vlan_table);
584 bp->pf.vf_info[i].vlan_as_table =
585 rte_zmalloc("VF VLAN AS table",
588 if (bp->pf.vf_info[i].vlan_as_table == NULL)
590 "Alloc VLAN AS table for VF %d fail\n",
594 bp->pf.vf_info[i].vlan_as_table);
595 STAILQ_INIT(&bp->pf.vf_info[i].filter);
600 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
601 memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
602 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
603 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
604 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
605 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
606 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
607 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
609 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
610 /* TODO: For now, do not support VMDq/RFS on VFs. */
615 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
619 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
621 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
622 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
623 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
624 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
626 bnxt_hwrm_ptp_qcfg(bp);
630 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
631 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
633 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
634 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
635 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
637 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
645 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
649 rc = __bnxt_hwrm_func_qcaps(bp);
650 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
651 rc = bnxt_alloc_ctx_mem(bp);
655 rc = bnxt_hwrm_func_resc_qcaps(bp);
657 bp->flags |= BNXT_FLAG_NEW_RM;
663 int bnxt_hwrm_func_reset(struct bnxt *bp)
666 struct hwrm_func_reset_input req = {.req_type = 0 };
667 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
669 HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
671 req.enables = rte_cpu_to_le_32(0);
673 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
681 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
685 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
686 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
688 if (bp->flags & BNXT_FLAG_REGISTERED)
691 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
693 /* PFs and trusted VFs should indicate the support of the
694 * Master capability on non Stingray platform
696 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
697 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
699 HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
700 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
701 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
702 req.ver_maj = RTE_VER_YEAR;
703 req.ver_min = RTE_VER_MONTH;
704 req.ver_upd = RTE_VER_MINOR;
707 req.enables |= rte_cpu_to_le_32(
708 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
709 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
710 RTE_MIN(sizeof(req.vf_req_fwd),
711 sizeof(bp->pf.vf_req_fwd)));
714 * PF can sniff HWRM API issued by VF. This can be set up by
715 * linux driver and inherited by the DPDK PF driver. Clear
716 * this HWRM sniffer list in FW because DPDK PF driver does
719 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
722 req.flags = rte_cpu_to_le_32(flags);
724 req.async_event_fwd[0] |=
725 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
726 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
727 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
728 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
729 req.async_event_fwd[1] |=
730 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
731 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
733 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
737 flags = rte_le_to_cpu_32(resp->flags);
738 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
739 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
743 bp->flags |= BNXT_FLAG_REGISTERED;
748 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
750 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
753 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
756 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
761 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
762 struct hwrm_func_vf_cfg_input req = {0};
764 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
766 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
767 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
768 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
769 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
770 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
772 if (BNXT_HAS_RING_GRPS(bp)) {
773 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
774 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
777 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
778 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
779 AGG_RING_MULTIPLIER);
780 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
782 BNXT_NUM_ASYNC_CPR(bp));
783 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
785 BNXT_NUM_ASYNC_CPR(bp));
786 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
787 if (bp->vf_resv_strategy ==
788 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
789 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
790 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
791 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
792 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
793 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
794 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
798 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
799 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
800 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
801 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
802 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
803 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
805 if (test && BNXT_HAS_RING_GRPS(bp))
806 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
808 req.flags = rte_cpu_to_le_32(flags);
809 req.enables |= rte_cpu_to_le_32(enables);
811 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
814 HWRM_CHECK_RESULT_SILENT();
822 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
825 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
826 struct hwrm_func_resource_qcaps_input req = {0};
828 HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
829 req.fid = rte_cpu_to_le_16(0xffff);
831 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
836 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
837 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
838 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
839 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
840 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
841 /* func_resource_qcaps does not return max_rx_em_flows.
842 * So use the value provided by func_qcaps.
845 rte_le_to_cpu_16(resp->max_l2_ctxs) +
847 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
848 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
850 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
851 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
852 if (bp->vf_resv_strategy >
853 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
854 bp->vf_resv_strategy =
855 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
861 int bnxt_hwrm_ver_get(struct bnxt *bp)
864 struct hwrm_ver_get_input req = {.req_type = 0 };
865 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
867 uint16_t max_resp_len;
868 char type[RTE_MEMZONE_NAMESIZE];
869 uint32_t dev_caps_cfg;
871 bp->max_req_len = HWRM_MAX_REQ_LEN;
872 HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
874 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
875 req.hwrm_intf_min = HWRM_VERSION_MINOR;
876 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
878 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
880 if (bp->flags & BNXT_FLAG_FW_RESET)
881 HWRM_CHECK_RESULT_SILENT();
885 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
886 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
887 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
888 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
889 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
890 (resp->hwrm_fw_min_8b << 16) |
891 (resp->hwrm_fw_bld_8b << 8) |
892 resp->hwrm_fw_rsvd_8b;
893 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
894 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
896 fw_version = resp->hwrm_intf_maj_8b << 16;
897 fw_version |= resp->hwrm_intf_min_8b << 8;
898 fw_version |= resp->hwrm_intf_upd_8b;
899 bp->hwrm_spec_code = fw_version;
901 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
902 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
907 if (bp->max_req_len > resp->max_req_win_len) {
908 PMD_DRV_LOG(ERR, "Unsupported request length\n");
911 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
912 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
913 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
914 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
916 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
917 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
919 if (bp->max_resp_len != max_resp_len) {
920 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
921 bp->pdev->addr.domain, bp->pdev->addr.bus,
922 bp->pdev->addr.devid, bp->pdev->addr.function);
924 rte_free(bp->hwrm_cmd_resp_addr);
926 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
927 if (bp->hwrm_cmd_resp_addr == NULL) {
931 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
932 bp->hwrm_cmd_resp_dma_addr =
933 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
934 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
936 "Unable to map response buffer to physical memory.\n");
940 bp->max_resp_len = max_resp_len;
944 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
946 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
947 PMD_DRV_LOG(DEBUG, "Short command supported\n");
948 bp->flags |= BNXT_FLAG_SHORT_CMD;
952 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
954 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
955 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
956 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
957 bp->pdev->addr.domain, bp->pdev->addr.bus,
958 bp->pdev->addr.devid, bp->pdev->addr.function);
960 rte_free(bp->hwrm_short_cmd_req_addr);
962 bp->hwrm_short_cmd_req_addr =
963 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
964 if (bp->hwrm_short_cmd_req_addr == NULL) {
968 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
969 bp->hwrm_short_cmd_req_dma_addr =
970 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
971 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
972 rte_free(bp->hwrm_short_cmd_req_addr);
974 "Unable to map buffer to physical memory.\n");
980 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
981 bp->flags |= BNXT_FLAG_KONG_MB_EN;
982 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
985 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
986 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
993 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
996 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
997 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
999 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1002 HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1005 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1007 HWRM_CHECK_RESULT();
1013 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1016 struct hwrm_port_phy_cfg_input req = {0};
1017 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1018 uint32_t enables = 0;
1020 HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1022 if (conf->link_up) {
1023 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1024 if (bp->link_info.auto_mode && conf->link_speed) {
1025 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1026 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1029 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1030 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1031 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1033 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1034 * any auto mode, even "none".
1036 if (!conf->link_speed) {
1037 /* No speeds specified. Enable AutoNeg - all speeds */
1039 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1041 /* AutoNeg - Advertise speeds specified. */
1042 if (conf->auto_link_speed_mask &&
1043 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1045 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1046 req.auto_link_speed_mask =
1047 conf->auto_link_speed_mask;
1049 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1052 req.auto_duplex = conf->duplex;
1053 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1054 req.auto_pause = conf->auto_pause;
1055 req.force_pause = conf->force_pause;
1056 /* Set force_pause if there is no auto or if there is a force */
1057 if (req.auto_pause && !req.force_pause)
1058 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1060 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1062 req.enables = rte_cpu_to_le_32(enables);
1065 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1066 PMD_DRV_LOG(INFO, "Force Link Down\n");
1069 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1071 HWRM_CHECK_RESULT();
1077 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1078 struct bnxt_link_info *link_info)
1081 struct hwrm_port_phy_qcfg_input req = {0};
1082 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1084 HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1086 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1088 HWRM_CHECK_RESULT();
1090 link_info->phy_link_status = resp->link;
1091 link_info->link_up =
1092 (link_info->phy_link_status ==
1093 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1094 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1095 link_info->duplex = resp->duplex_cfg;
1096 link_info->pause = resp->pause;
1097 link_info->auto_pause = resp->auto_pause;
1098 link_info->force_pause = resp->force_pause;
1099 link_info->auto_mode = resp->auto_mode;
1100 link_info->phy_type = resp->phy_type;
1101 link_info->media_type = resp->media_type;
1103 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1104 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1105 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1106 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1107 link_info->phy_ver[0] = resp->phy_maj;
1108 link_info->phy_ver[1] = resp->phy_min;
1109 link_info->phy_ver[2] = resp->phy_bld;
1113 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1114 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1115 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1116 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1117 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1118 link_info->auto_link_speed_mask);
1119 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1120 link_info->force_link_speed);
1125 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1128 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1129 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1132 HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1134 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1135 /* HWRM Version >= 1.9.1 */
1136 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1138 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1139 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1141 HWRM_CHECK_RESULT();
1143 #define GET_QUEUE_INFO(x) \
1144 bp->cos_queue[x].id = resp->queue_id##x; \
1145 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1158 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1159 bp->tx_cosq_id = bp->cos_queue[0].id;
1161 /* iterate and find the COSq profile to use for Tx */
1162 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1163 if (bp->cos_queue[i].profile ==
1164 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1165 bp->tx_cosq_id = bp->cos_queue[i].id;
1171 bp->max_tc = resp->max_configurable_queues;
1172 bp->max_lltc = resp->max_configurable_lossless_queues;
1173 if (bp->max_tc > BNXT_MAX_QUEUE)
1174 bp->max_tc = BNXT_MAX_QUEUE;
1175 bp->max_q = bp->max_tc;
1177 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1182 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1183 struct bnxt_ring *ring,
1184 uint32_t ring_type, uint32_t map_index,
1185 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1188 uint32_t enables = 0;
1189 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1190 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1191 struct rte_mempool *mb_pool;
1192 uint16_t rx_buf_size;
1194 HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1196 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1197 req.fbo = rte_cpu_to_le_32(0);
1198 /* Association of ring index with doorbell index */
1199 req.logical_id = rte_cpu_to_le_16(map_index);
1200 req.length = rte_cpu_to_le_32(ring->ring_size);
1202 switch (ring_type) {
1203 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1204 req.ring_type = ring_type;
1205 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1206 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1207 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1208 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1210 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1212 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1213 req.ring_type = ring_type;
1214 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1215 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1216 if (BNXT_CHIP_THOR(bp)) {
1217 mb_pool = bp->rx_queues[0]->mb_pool;
1218 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1219 RTE_PKTMBUF_HEADROOM;
1220 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1222 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1224 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1226 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1228 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1229 req.ring_type = ring_type;
1230 if (BNXT_HAS_NQ(bp)) {
1231 /* Association of cp ring with nq */
1232 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1234 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1236 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1238 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1239 req.ring_type = ring_type;
1240 req.page_size = BNXT_PAGE_SHFT;
1241 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1243 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1244 req.ring_type = ring_type;
1245 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1247 mb_pool = bp->rx_queues[0]->mb_pool;
1248 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1249 RTE_PKTMBUF_HEADROOM;
1250 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1252 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1253 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1254 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1255 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1258 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1263 req.enables = rte_cpu_to_le_32(enables);
1265 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1267 if (rc || resp->error_code) {
1268 if (rc == 0 && resp->error_code)
1269 rc = rte_le_to_cpu_16(resp->error_code);
1270 switch (ring_type) {
1271 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1273 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1276 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1278 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1281 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1283 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1287 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1289 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1292 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1294 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1298 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1304 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1309 int bnxt_hwrm_ring_free(struct bnxt *bp,
1310 struct bnxt_ring *ring, uint32_t ring_type)
1313 struct hwrm_ring_free_input req = {.req_type = 0 };
1314 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1316 HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1318 req.ring_type = ring_type;
1319 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1321 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1323 if (rc || resp->error_code) {
1324 if (rc == 0 && resp->error_code)
1325 rc = rte_le_to_cpu_16(resp->error_code);
1328 switch (ring_type) {
1329 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1330 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1333 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1334 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1337 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1338 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1341 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1343 "hwrm_ring_free nq failed. rc:%d\n", rc);
1345 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1347 "hwrm_ring_free agg failed. rc:%d\n", rc);
1350 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1358 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1361 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1362 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1364 HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1366 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1367 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1368 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1369 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1371 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1373 HWRM_CHECK_RESULT();
1375 bp->grp_info[idx].fw_grp_id =
1376 rte_le_to_cpu_16(resp->ring_group_id);
1383 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1386 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1387 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1389 HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1391 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1393 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1395 HWRM_CHECK_RESULT();
1398 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1402 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1405 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1406 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1408 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1411 HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1413 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1415 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1417 HWRM_CHECK_RESULT();
1423 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1424 unsigned int idx __rte_unused)
1427 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1428 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1430 HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1432 req.update_period_ms = rte_cpu_to_le_32(0);
1434 req.stats_dma_addr =
1435 rte_cpu_to_le_64(cpr->hw_stats_map);
1437 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1439 HWRM_CHECK_RESULT();
1441 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1448 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1449 unsigned int idx __rte_unused)
1452 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1453 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1455 HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1457 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1459 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1461 HWRM_CHECK_RESULT();
1467 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1470 struct hwrm_vnic_alloc_input req = { 0 };
1471 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1473 if (!BNXT_HAS_RING_GRPS(bp))
1474 goto skip_ring_grps;
1476 /* map ring groups to this vnic */
1477 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1478 vnic->start_grp_id, vnic->end_grp_id);
1479 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1480 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1482 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1483 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1484 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1485 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1488 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1489 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1490 HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1492 if (vnic->func_default)
1494 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1495 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1497 HWRM_CHECK_RESULT();
1499 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1501 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1505 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1506 struct bnxt_vnic_info *vnic,
1507 struct bnxt_plcmodes_cfg *pmode)
1510 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1511 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1513 HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1515 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1517 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1519 HWRM_CHECK_RESULT();
1521 pmode->flags = rte_le_to_cpu_32(resp->flags);
1522 /* dflt_vnic bit doesn't exist in the _cfg command */
1523 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1524 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1525 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1526 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1533 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1534 struct bnxt_vnic_info *vnic,
1535 struct bnxt_plcmodes_cfg *pmode)
1538 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1539 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1541 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1542 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1546 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1548 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1549 req.flags = rte_cpu_to_le_32(pmode->flags);
1550 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1551 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1552 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1553 req.enables = rte_cpu_to_le_32(
1554 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1555 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1556 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1559 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1561 HWRM_CHECK_RESULT();
1567 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1570 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1571 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1572 struct bnxt_plcmodes_cfg pmodes = { 0 };
1573 uint32_t ctx_enable_flag = 0;
1574 uint32_t enables = 0;
1576 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1577 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1581 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1585 HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1587 if (BNXT_CHIP_THOR(bp)) {
1588 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1589 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1590 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1592 req.default_rx_ring_id =
1593 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1594 req.default_cmpl_ring_id =
1595 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1596 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1597 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1601 /* Only RSS support for now TBD: COS & LB */
1602 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1603 if (vnic->lb_rule != 0xffff)
1604 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1605 if (vnic->cos_rule != 0xffff)
1606 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1607 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1608 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1609 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1611 enables |= ctx_enable_flag;
1612 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1613 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1614 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1615 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1618 req.enables = rte_cpu_to_le_32(enables);
1619 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1620 req.mru = rte_cpu_to_le_16(vnic->mru);
1621 /* Configure default VNIC only once. */
1622 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1624 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1625 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1627 if (vnic->vlan_strip)
1629 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1632 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1633 if (vnic->roce_dual)
1634 req.flags |= rte_cpu_to_le_32(
1635 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1636 if (vnic->roce_only)
1637 req.flags |= rte_cpu_to_le_32(
1638 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1639 if (vnic->rss_dflt_cr)
1640 req.flags |= rte_cpu_to_le_32(
1641 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1643 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1645 HWRM_CHECK_RESULT();
1648 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1653 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1657 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1658 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1660 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1661 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1664 HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1667 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1668 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1669 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1671 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1673 HWRM_CHECK_RESULT();
1675 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1676 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1677 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1678 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1679 vnic->mru = rte_le_to_cpu_16(resp->mru);
1680 vnic->func_default = rte_le_to_cpu_32(
1681 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1682 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1683 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1684 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1685 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1686 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1687 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1688 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1689 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1690 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1691 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1698 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1699 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1703 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1704 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1705 bp->hwrm_cmd_resp_addr;
1707 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1709 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1710 HWRM_CHECK_RESULT();
1712 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1713 if (!BNXT_HAS_RING_GRPS(bp))
1714 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1715 else if (ctx_idx == 0)
1716 vnic->rss_rule = ctx_id;
1723 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1724 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1727 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1728 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1729 bp->hwrm_cmd_resp_addr;
1731 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1732 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1735 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1737 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1739 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1741 HWRM_CHECK_RESULT();
1747 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1750 struct hwrm_vnic_free_input req = {.req_type = 0 };
1751 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1753 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1754 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1758 HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1760 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1762 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1764 HWRM_CHECK_RESULT();
1767 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1768 /* Configure default VNIC again if necessary. */
1769 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1770 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1776 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1780 int nr_ctxs = vnic->num_lb_ctxts;
1781 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1782 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1784 for (i = 0; i < nr_ctxs; i++) {
1785 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1787 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1788 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1789 req.hash_mode_flags = vnic->hash_mode;
1791 req.hash_key_tbl_addr =
1792 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1794 req.ring_grp_tbl_addr =
1795 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1796 i * HW_HASH_INDEX_SIZE);
1797 req.ring_table_pair_index = i;
1798 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1800 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1803 HWRM_CHECK_RESULT();
1810 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1811 struct bnxt_vnic_info *vnic)
1814 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1815 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1817 if (!vnic->rss_table)
1820 if (BNXT_CHIP_THOR(bp))
1821 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1823 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1825 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1826 req.hash_mode_flags = vnic->hash_mode;
1828 req.ring_grp_tbl_addr =
1829 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1830 req.hash_key_tbl_addr =
1831 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1832 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1833 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1835 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1837 HWRM_CHECK_RESULT();
1843 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1844 struct bnxt_vnic_info *vnic)
1847 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1848 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1851 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1852 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1856 HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1858 req.flags = rte_cpu_to_le_32(
1859 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1861 req.enables = rte_cpu_to_le_32(
1862 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1864 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1865 size -= RTE_PKTMBUF_HEADROOM;
1867 req.jumbo_thresh = rte_cpu_to_le_16(size);
1868 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1870 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1872 HWRM_CHECK_RESULT();
1878 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1879 struct bnxt_vnic_info *vnic, bool enable)
1882 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1883 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1885 if (BNXT_CHIP_THOR(bp))
1888 HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1891 req.enables = rte_cpu_to_le_32(
1892 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1893 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1894 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1895 req.flags = rte_cpu_to_le_32(
1896 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1897 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1898 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1899 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1900 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1901 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1902 req.max_agg_segs = rte_cpu_to_le_16(5);
1904 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1905 req.min_agg_len = rte_cpu_to_le_32(512);
1907 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1909 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1911 HWRM_CHECK_RESULT();
1917 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1919 struct hwrm_func_cfg_input req = {0};
1920 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1923 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1924 req.enables = rte_cpu_to_le_32(
1925 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1926 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1927 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1929 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1931 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1932 HWRM_CHECK_RESULT();
1935 bp->pf.vf_info[vf].random_mac = false;
1940 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1944 struct hwrm_func_qstats_input req = {.req_type = 0};
1945 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1947 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1949 req.fid = rte_cpu_to_le_16(fid);
1951 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1953 HWRM_CHECK_RESULT();
1956 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1963 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1964 struct rte_eth_stats *stats)
1967 struct hwrm_func_qstats_input req = {.req_type = 0};
1968 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1970 HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1972 req.fid = rte_cpu_to_le_16(fid);
1974 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1976 HWRM_CHECK_RESULT();
1978 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1979 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1980 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1981 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1982 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1983 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1985 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1986 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1987 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1988 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1989 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1990 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1992 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1993 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1994 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2001 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2004 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2005 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2007 HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2009 req.fid = rte_cpu_to_le_16(fid);
2011 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2013 HWRM_CHECK_RESULT();
2020 * HWRM utility functions
2023 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2028 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2029 struct bnxt_tx_queue *txq;
2030 struct bnxt_rx_queue *rxq;
2031 struct bnxt_cp_ring_info *cpr;
2033 if (i >= bp->rx_cp_nr_rings) {
2034 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2037 rxq = bp->rx_queues[i];
2041 rc = bnxt_hwrm_stat_clear(bp, cpr);
2048 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2052 struct bnxt_cp_ring_info *cpr;
2054 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2056 if (i >= bp->rx_cp_nr_rings) {
2057 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2059 cpr = bp->rx_queues[i]->cp_ring;
2060 if (BNXT_HAS_RING_GRPS(bp))
2061 bp->grp_info[i].fw_stats_ctx = -1;
2063 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2064 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2065 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2073 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2078 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2079 struct bnxt_tx_queue *txq;
2080 struct bnxt_rx_queue *rxq;
2081 struct bnxt_cp_ring_info *cpr;
2083 if (i >= bp->rx_cp_nr_rings) {
2084 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2087 rxq = bp->rx_queues[i];
2091 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2099 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2104 if (!BNXT_HAS_RING_GRPS(bp))
2107 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2109 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2112 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2120 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2122 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2124 bnxt_hwrm_ring_free(bp, cp_ring,
2125 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2126 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2127 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2128 sizeof(*cpr->cp_desc_ring));
2129 cpr->cp_raw_cons = 0;
2133 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2135 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2137 bnxt_hwrm_ring_free(bp, cp_ring,
2138 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2139 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2140 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2141 sizeof(*cpr->cp_desc_ring));
2142 cpr->cp_raw_cons = 0;
2146 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2148 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2149 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2150 struct bnxt_ring *ring = rxr->rx_ring_struct;
2151 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2153 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2154 bnxt_hwrm_ring_free(bp, ring,
2155 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2156 ring->fw_ring_id = INVALID_HW_RING_ID;
2157 if (BNXT_HAS_RING_GRPS(bp))
2158 bp->grp_info[queue_index].rx_fw_ring_id =
2160 memset(rxr->rx_desc_ring, 0,
2161 rxr->rx_ring_struct->ring_size *
2162 sizeof(*rxr->rx_desc_ring));
2163 memset(rxr->rx_buf_ring, 0,
2164 rxr->rx_ring_struct->ring_size *
2165 sizeof(*rxr->rx_buf_ring));
2168 ring = rxr->ag_ring_struct;
2169 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2170 bnxt_hwrm_ring_free(bp, ring,
2171 BNXT_CHIP_THOR(bp) ?
2172 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2173 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2174 ring->fw_ring_id = INVALID_HW_RING_ID;
2175 memset(rxr->ag_buf_ring, 0,
2176 rxr->ag_ring_struct->ring_size *
2177 sizeof(*rxr->ag_buf_ring));
2179 if (BNXT_HAS_RING_GRPS(bp))
2180 bp->grp_info[queue_index].ag_fw_ring_id =
2183 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2184 bnxt_free_cp_ring(bp, cpr);
2186 bnxt_free_nq_ring(bp, rxq->nq_ring);
2189 if (BNXT_HAS_RING_GRPS(bp))
2190 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2193 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2197 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2198 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2199 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2200 struct bnxt_ring *ring = txr->tx_ring_struct;
2201 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2203 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2204 bnxt_hwrm_ring_free(bp, ring,
2205 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2206 ring->fw_ring_id = INVALID_HW_RING_ID;
2207 memset(txr->tx_desc_ring, 0,
2208 txr->tx_ring_struct->ring_size *
2209 sizeof(*txr->tx_desc_ring));
2210 memset(txr->tx_buf_ring, 0,
2211 txr->tx_ring_struct->ring_size *
2212 sizeof(*txr->tx_buf_ring));
2216 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2217 bnxt_free_cp_ring(bp, cpr);
2218 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2220 bnxt_free_nq_ring(bp, txq->nq_ring);
2224 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2225 bnxt_free_hwrm_rx_ring(bp, i);
2230 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2235 if (!BNXT_HAS_RING_GRPS(bp))
2238 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2239 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2246 void bnxt_free_hwrm_resources(struct bnxt *bp)
2248 /* Release memzone */
2249 rte_free(bp->hwrm_cmd_resp_addr);
2250 rte_free(bp->hwrm_short_cmd_req_addr);
2251 bp->hwrm_cmd_resp_addr = NULL;
2252 bp->hwrm_short_cmd_req_addr = NULL;
2253 bp->hwrm_cmd_resp_dma_addr = 0;
2254 bp->hwrm_short_cmd_req_dma_addr = 0;
2257 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2259 struct rte_pci_device *pdev = bp->pdev;
2260 char type[RTE_MEMZONE_NAMESIZE];
2262 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2263 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2264 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2265 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2266 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2267 if (bp->hwrm_cmd_resp_addr == NULL)
2269 bp->hwrm_cmd_resp_dma_addr =
2270 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2271 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2273 "unable to map response address to physical memory\n");
2276 rte_spinlock_init(&bp->hwrm_lock);
2281 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2283 struct bnxt_filter_info *filter;
2286 STAILQ_FOREACH(filter, &vnic->filter, next) {
2287 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2288 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2289 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2290 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2292 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2293 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2301 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2303 struct bnxt_filter_info *filter;
2304 struct rte_flow *flow;
2307 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2308 filter = flow->filter;
2309 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2310 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2311 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2312 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2313 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2315 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2317 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2325 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2327 struct bnxt_filter_info *filter;
2330 STAILQ_FOREACH(filter, &vnic->filter, next) {
2331 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2332 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2334 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2335 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2338 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2346 void bnxt_free_tunnel_ports(struct bnxt *bp)
2348 if (bp->vxlan_port_cnt)
2349 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2350 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2352 if (bp->geneve_port_cnt)
2353 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2354 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2355 bp->geneve_port = 0;
2358 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2362 if (bp->vnic_info == NULL)
2366 * Cleanup VNICs in reverse order, to make sure the L2 filter
2367 * from vnic0 is last to be cleaned up.
2369 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2370 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2372 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2373 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2377 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2379 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2381 if (BNXT_CHIP_THOR(bp)) {
2382 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2383 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2384 vnic->fw_grp_ids[j]);
2385 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2387 vnic->num_lb_ctxts = 0;
2389 bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2390 vnic->rss_rule = INVALID_HW_RING_ID;
2393 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2395 bnxt_hwrm_vnic_free(bp, vnic);
2397 rte_free(vnic->fw_grp_ids);
2399 /* Ring resources */
2400 bnxt_free_all_hwrm_rings(bp);
2401 bnxt_free_all_hwrm_ring_grps(bp);
2402 bnxt_free_all_hwrm_stat_ctxs(bp);
2403 bnxt_free_tunnel_ports(bp);
2406 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2408 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2410 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2411 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2413 switch (conf_link_speed) {
2414 case ETH_LINK_SPEED_10M_HD:
2415 case ETH_LINK_SPEED_100M_HD:
2417 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2419 return hw_link_duplex;
2422 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2424 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2427 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2429 uint16_t eth_link_speed = 0;
2431 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2432 return ETH_LINK_SPEED_AUTONEG;
2434 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2435 case ETH_LINK_SPEED_100M:
2436 case ETH_LINK_SPEED_100M_HD:
2439 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2441 case ETH_LINK_SPEED_1G:
2443 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2445 case ETH_LINK_SPEED_2_5G:
2447 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2449 case ETH_LINK_SPEED_10G:
2451 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2453 case ETH_LINK_SPEED_20G:
2455 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2457 case ETH_LINK_SPEED_25G:
2459 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2461 case ETH_LINK_SPEED_40G:
2463 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2465 case ETH_LINK_SPEED_50G:
2467 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2469 case ETH_LINK_SPEED_100G:
2471 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2475 "Unsupported link speed %d; default to AUTO\n",
2479 return eth_link_speed;
2482 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2483 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2484 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2485 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2487 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2491 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2494 if (link_speed & ETH_LINK_SPEED_FIXED) {
2495 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2497 if (one_speed & (one_speed - 1)) {
2499 "Invalid advertised speeds (%u) for port %u\n",
2500 link_speed, port_id);
2503 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2505 "Unsupported advertised speed (%u) for port %u\n",
2506 link_speed, port_id);
2510 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2512 "Unsupported advertised speeds (%u) for port %u\n",
2513 link_speed, port_id);
2521 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2525 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2526 if (bp->link_info.support_speeds)
2527 return bp->link_info.support_speeds;
2528 link_speed = BNXT_SUPPORTED_SPEEDS;
2531 if (link_speed & ETH_LINK_SPEED_100M)
2532 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2533 if (link_speed & ETH_LINK_SPEED_100M_HD)
2534 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2535 if (link_speed & ETH_LINK_SPEED_1G)
2536 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2537 if (link_speed & ETH_LINK_SPEED_2_5G)
2538 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2539 if (link_speed & ETH_LINK_SPEED_10G)
2540 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2541 if (link_speed & ETH_LINK_SPEED_20G)
2542 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2543 if (link_speed & ETH_LINK_SPEED_25G)
2544 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2545 if (link_speed & ETH_LINK_SPEED_40G)
2546 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2547 if (link_speed & ETH_LINK_SPEED_50G)
2548 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2549 if (link_speed & ETH_LINK_SPEED_100G)
2550 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2554 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2556 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2558 switch (hw_link_speed) {
2559 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2560 eth_link_speed = ETH_SPEED_NUM_100M;
2562 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2563 eth_link_speed = ETH_SPEED_NUM_1G;
2565 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2566 eth_link_speed = ETH_SPEED_NUM_2_5G;
2568 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2569 eth_link_speed = ETH_SPEED_NUM_10G;
2571 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2572 eth_link_speed = ETH_SPEED_NUM_20G;
2574 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2575 eth_link_speed = ETH_SPEED_NUM_25G;
2577 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2578 eth_link_speed = ETH_SPEED_NUM_40G;
2580 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2581 eth_link_speed = ETH_SPEED_NUM_50G;
2583 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2584 eth_link_speed = ETH_SPEED_NUM_100G;
2586 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2588 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2592 return eth_link_speed;
2595 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2597 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2599 switch (hw_link_duplex) {
2600 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2601 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2603 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2605 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2606 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2609 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2613 return eth_link_duplex;
2616 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2619 struct bnxt_link_info *link_info = &bp->link_info;
2621 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2624 "Get link config failed with rc %d\n", rc);
2627 if (link_info->link_speed)
2629 bnxt_parse_hw_link_speed(link_info->link_speed);
2631 link->link_speed = ETH_SPEED_NUM_NONE;
2632 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2633 link->link_status = link_info->link_up;
2634 link->link_autoneg = link_info->auto_mode ==
2635 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2636 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2641 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2644 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2645 struct bnxt_link_info link_req;
2646 uint16_t speed, autoneg;
2648 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2651 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2652 bp->eth_dev->data->port_id);
2656 memset(&link_req, 0, sizeof(link_req));
2657 link_req.link_up = link_up;
2661 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2662 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2663 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2664 /* Autoneg can be done only when the FW allows */
2665 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2666 bp->link_info.force_link_speed)) {
2667 link_req.phy_flags |=
2668 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2669 link_req.auto_link_speed_mask =
2670 bnxt_parse_eth_link_speed_mask(bp,
2671 dev_conf->link_speeds);
2673 if (bp->link_info.phy_type ==
2674 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2675 bp->link_info.phy_type ==
2676 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2677 bp->link_info.media_type ==
2678 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2679 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2683 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2684 /* If user wants a particular speed try that first. */
2686 link_req.link_speed = speed;
2687 else if (bp->link_info.force_link_speed)
2688 link_req.link_speed = bp->link_info.force_link_speed;
2690 link_req.link_speed = bp->link_info.auto_link_speed;
2692 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2693 link_req.auto_pause = bp->link_info.auto_pause;
2694 link_req.force_pause = bp->link_info.force_pause;
2697 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2700 "Set link config failed with rc %d\n", rc);
2708 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2710 struct hwrm_func_qcfg_input req = {0};
2711 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2715 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2716 req.fid = rte_cpu_to_le_16(0xffff);
2718 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2720 HWRM_CHECK_RESULT();
2722 /* Hard Coded.. 0xfff VLAN ID mask */
2723 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2724 flags = rte_le_to_cpu_16(resp->flags);
2725 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2726 bp->flags |= BNXT_FLAG_MULTI_HOST;
2728 if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2729 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2730 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2731 } else if (BNXT_VF(bp) &&
2732 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2733 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2734 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2740 switch (resp->port_partition_type) {
2741 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2742 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2743 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2745 bp->port_partition_type = resp->port_partition_type;
2748 bp->port_partition_type = 0;
2757 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2758 struct hwrm_func_qcaps_output *qcaps)
2760 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2761 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2762 sizeof(qcaps->mac_address));
2763 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2764 qcaps->max_rx_rings = fcfg->num_rx_rings;
2765 qcaps->max_tx_rings = fcfg->num_tx_rings;
2766 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2767 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2769 qcaps->first_vf_id = 0;
2770 qcaps->max_vnics = fcfg->num_vnics;
2771 qcaps->max_decap_records = 0;
2772 qcaps->max_encap_records = 0;
2773 qcaps->max_tx_wm_flows = 0;
2774 qcaps->max_tx_em_flows = 0;
2775 qcaps->max_rx_wm_flows = 0;
2776 qcaps->max_rx_em_flows = 0;
2777 qcaps->max_flow_id = 0;
2778 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2779 qcaps->max_sp_tx_rings = 0;
2780 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2783 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2785 struct hwrm_func_cfg_input req = {0};
2786 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2790 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2791 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2792 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2793 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2794 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2795 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2796 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2797 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2798 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2800 if (BNXT_HAS_RING_GRPS(bp)) {
2801 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2802 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2803 } else if (BNXT_HAS_NQ(bp)) {
2804 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2805 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2808 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2809 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2810 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2811 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2813 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2814 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2815 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2816 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2817 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2818 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2819 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2820 req.fid = rte_cpu_to_le_16(0xffff);
2821 req.enables = rte_cpu_to_le_32(enables);
2823 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2825 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2827 HWRM_CHECK_RESULT();
2833 static void populate_vf_func_cfg_req(struct bnxt *bp,
2834 struct hwrm_func_cfg_input *req,
2837 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2838 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2839 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2840 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2841 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2842 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2843 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2844 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2845 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2846 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2848 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2849 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2851 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2852 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2854 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2856 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2857 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2859 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2860 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2861 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2862 /* TODO: For now, do not support VMDq/RFS on VFs. */
2863 req->num_vnics = rte_cpu_to_le_16(1);
2864 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2868 static void add_random_mac_if_needed(struct bnxt *bp,
2869 struct hwrm_func_cfg_input *cfg_req,
2872 struct rte_ether_addr mac;
2874 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2877 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2879 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2880 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2881 bp->pf.vf_info[vf].random_mac = true;
2883 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2884 RTE_ETHER_ADDR_LEN);
2888 static void reserve_resources_from_vf(struct bnxt *bp,
2889 struct hwrm_func_cfg_input *cfg_req,
2892 struct hwrm_func_qcaps_input req = {0};
2893 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2896 /* Get the actual allocated values now */
2897 HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2898 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2899 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2902 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2903 copy_func_cfg_to_qcaps(cfg_req, resp);
2904 } else if (resp->error_code) {
2905 rc = rte_le_to_cpu_16(resp->error_code);
2906 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2907 copy_func_cfg_to_qcaps(cfg_req, resp);
2910 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2911 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2912 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2913 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2914 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2915 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2917 * TODO: While not supporting VMDq with VFs, max_vnics is always
2918 * forced to 1 in this case
2920 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2921 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2926 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2928 struct hwrm_func_qcfg_input req = {0};
2929 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2932 /* Check for zero MAC address */
2933 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2934 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2935 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2936 HWRM_CHECK_RESULT();
2937 rc = rte_le_to_cpu_16(resp->vlan);
2944 static int update_pf_resource_max(struct bnxt *bp)
2946 struct hwrm_func_qcfg_input req = {0};
2947 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2950 /* And copy the allocated numbers into the pf struct */
2951 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2952 req.fid = rte_cpu_to_le_16(0xffff);
2953 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2954 HWRM_CHECK_RESULT();
2956 /* Only TX ring value reflects actual allocation? TODO */
2957 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2958 bp->pf.evb_mode = resp->evb_mode;
2965 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2970 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2974 rc = bnxt_hwrm_func_qcaps(bp);
2978 bp->pf.func_cfg_flags &=
2979 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2980 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2981 bp->pf.func_cfg_flags |=
2982 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2983 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2984 rc = __bnxt_hwrm_func_qcaps(bp);
2988 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2990 struct hwrm_func_cfg_input req = {0};
2991 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2998 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3002 rc = bnxt_hwrm_func_qcaps(bp);
3007 bp->pf.active_vfs = num_vfs;
3010 * First, configure the PF to only use one TX ring. This ensures that
3011 * there are enough rings for all VFs.
3013 * If we don't do this, when we call func_alloc() later, we will lock
3014 * extra rings to the PF that won't be available during func_cfg() of
3017 * This has been fixed with firmware versions above 20.6.54
3019 bp->pf.func_cfg_flags &=
3020 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3021 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3022 bp->pf.func_cfg_flags |=
3023 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3024 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3029 * Now, create and register a buffer to hold forwarded VF requests
3031 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3032 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3033 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3034 if (bp->pf.vf_req_buf == NULL) {
3038 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3039 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3040 for (i = 0; i < num_vfs; i++)
3041 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3042 (i * HWRM_MAX_REQ_LEN);
3044 rc = bnxt_hwrm_func_buf_rgtr(bp);
3048 populate_vf_func_cfg_req(bp, &req, num_vfs);
3050 bp->pf.active_vfs = 0;
3051 for (i = 0; i < num_vfs; i++) {
3052 add_random_mac_if_needed(bp, &req, i);
3054 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3055 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3056 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3057 rc = bnxt_hwrm_send_message(bp,
3062 /* Clear enable flag for next pass */
3063 req.enables &= ~rte_cpu_to_le_32(
3064 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3066 if (rc || resp->error_code) {
3068 "Failed to initizlie VF %d\n", i);
3070 "Not all VFs available. (%d, %d)\n",
3071 rc, resp->error_code);
3078 reserve_resources_from_vf(bp, &req, i);
3079 bp->pf.active_vfs++;
3080 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3084 * Now configure the PF to use "the rest" of the resources
3085 * We're using STD_TX_RING_MODE here though which will limit the TX
3086 * rings. This will allow QoS to function properly. Not setting this
3087 * will cause PF rings to break bandwidth settings.
3089 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3093 rc = update_pf_resource_max(bp);
3100 bnxt_hwrm_func_buf_unrgtr(bp);
3104 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3106 struct hwrm_func_cfg_input req = {0};
3107 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3110 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3112 req.fid = rte_cpu_to_le_16(0xffff);
3113 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3114 req.evb_mode = bp->pf.evb_mode;
3116 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3117 HWRM_CHECK_RESULT();
3123 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3124 uint8_t tunnel_type)
3126 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3127 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3130 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3131 req.tunnel_type = tunnel_type;
3132 req.tunnel_dst_port_val = port;
3133 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3134 HWRM_CHECK_RESULT();
3136 switch (tunnel_type) {
3137 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3138 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3139 bp->vxlan_port = port;
3141 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3142 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3143 bp->geneve_port = port;
3154 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3155 uint8_t tunnel_type)
3157 struct hwrm_tunnel_dst_port_free_input req = {0};
3158 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3161 HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3163 req.tunnel_type = tunnel_type;
3164 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3165 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3167 HWRM_CHECK_RESULT();
3173 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3176 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3177 struct hwrm_func_cfg_input req = {0};
3180 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3182 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3183 req.flags = rte_cpu_to_le_32(flags);
3184 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3186 HWRM_CHECK_RESULT();
3192 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3194 uint32_t *flag = flagp;
3196 vnic->flags = *flag;
3199 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3201 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3204 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3207 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3208 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3210 HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3212 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3213 req.req_buf_page_size = rte_cpu_to_le_16(
3214 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3215 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3216 req.req_buf_page_addr0 =
3217 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3218 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3220 "unable to map buffer address to physical memory\n");
3224 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3226 HWRM_CHECK_RESULT();
3232 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3235 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3236 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3238 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3241 HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3243 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3245 HWRM_CHECK_RESULT();
3251 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3253 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3254 struct hwrm_func_cfg_input req = {0};
3257 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3259 req.fid = rte_cpu_to_le_16(0xffff);
3260 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3261 req.enables = rte_cpu_to_le_32(
3262 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3263 req.async_event_cr = rte_cpu_to_le_16(
3264 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3265 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3267 HWRM_CHECK_RESULT();
3273 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3275 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3276 struct hwrm_func_vf_cfg_input req = {0};
3279 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3281 req.enables = rte_cpu_to_le_32(
3282 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3283 req.async_event_cr = rte_cpu_to_le_16(
3284 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3285 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3287 HWRM_CHECK_RESULT();
3293 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3295 struct hwrm_func_cfg_input req = {0};
3296 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3297 uint16_t dflt_vlan, fid;
3298 uint32_t func_cfg_flags;
3301 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3304 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3305 fid = bp->pf.vf_info[vf].fid;
3306 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3308 fid = rte_cpu_to_le_16(0xffff);
3309 func_cfg_flags = bp->pf.func_cfg_flags;
3310 dflt_vlan = bp->vlan;
3313 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3314 req.fid = rte_cpu_to_le_16(fid);
3315 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3316 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3318 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3320 HWRM_CHECK_RESULT();
3326 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3327 uint16_t max_bw, uint16_t enables)
3329 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3330 struct hwrm_func_cfg_input req = {0};
3333 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3335 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3336 req.enables |= rte_cpu_to_le_32(enables);
3337 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3338 req.max_bw = rte_cpu_to_le_32(max_bw);
3339 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3341 HWRM_CHECK_RESULT();
3347 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3349 struct hwrm_func_cfg_input req = {0};
3350 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3353 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3355 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3356 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3357 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3358 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3360 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3362 HWRM_CHECK_RESULT();
3368 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3373 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3375 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3380 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3381 void *encaped, size_t ec_size)
3384 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3385 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3387 if (ec_size > sizeof(req.encap_request))
3390 HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3392 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3393 memcpy(req.encap_request, encaped, ec_size);
3395 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3397 HWRM_CHECK_RESULT();
3403 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3404 struct rte_ether_addr *mac)
3406 struct hwrm_func_qcfg_input req = {0};
3407 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3410 HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3412 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3413 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3415 HWRM_CHECK_RESULT();
3417 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3424 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3425 void *encaped, size_t ec_size)
3428 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3429 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3431 if (ec_size > sizeof(req.encap_request))
3434 HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3436 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3437 memcpy(req.encap_request, encaped, ec_size);
3439 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3441 HWRM_CHECK_RESULT();
3447 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3448 struct rte_eth_stats *stats, uint8_t rx)
3451 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3452 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3454 HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3456 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3458 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3460 HWRM_CHECK_RESULT();
3463 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3464 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3465 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3466 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3467 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3468 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3469 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3470 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3472 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3473 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3474 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3475 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3476 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3477 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3486 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3488 struct hwrm_port_qstats_input req = {0};
3489 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3490 struct bnxt_pf_info *pf = &bp->pf;
3493 HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3495 req.port_id = rte_cpu_to_le_16(pf->port_id);
3496 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3497 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3498 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3500 HWRM_CHECK_RESULT();
3506 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3508 struct hwrm_port_clr_stats_input req = {0};
3509 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3510 struct bnxt_pf_info *pf = &bp->pf;
3513 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3514 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3515 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3518 HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3520 req.port_id = rte_cpu_to_le_16(pf->port_id);
3521 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3523 HWRM_CHECK_RESULT();
3529 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3531 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3532 struct hwrm_port_led_qcaps_input req = {0};
3538 HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3539 req.port_id = bp->pf.port_id;
3540 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3542 HWRM_CHECK_RESULT();
3544 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3547 bp->num_leds = resp->num_leds;
3548 memcpy(bp->leds, &resp->led0_id,
3549 sizeof(bp->leds[0]) * bp->num_leds);
3550 for (i = 0; i < bp->num_leds; i++) {
3551 struct bnxt_led_info *led = &bp->leds[i];
3553 uint16_t caps = led->led_state_caps;
3555 if (!led->led_group_id ||
3556 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3568 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3570 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3571 struct hwrm_port_led_cfg_input req = {0};
3572 struct bnxt_led_cfg *led_cfg;
3573 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3574 uint16_t duration = 0;
3577 if (!bp->num_leds || BNXT_VF(bp))
3580 HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3583 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3584 duration = rte_cpu_to_le_16(500);
3586 req.port_id = bp->pf.port_id;
3587 req.num_leds = bp->num_leds;
3588 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3589 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3590 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3591 led_cfg->led_id = bp->leds[i].led_id;
3592 led_cfg->led_state = led_state;
3593 led_cfg->led_blink_on = duration;
3594 led_cfg->led_blink_off = duration;
3595 led_cfg->led_group_id = bp->leds[i].led_group_id;
3598 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3600 HWRM_CHECK_RESULT();
3606 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3610 struct hwrm_nvm_get_dir_info_input req = {0};
3611 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3613 HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3615 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3617 HWRM_CHECK_RESULT();
3619 *entries = rte_le_to_cpu_32(resp->entries);
3620 *length = rte_le_to_cpu_32(resp->entry_length);
3626 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3629 uint32_t dir_entries;
3630 uint32_t entry_length;
3633 rte_iova_t dma_handle;
3634 struct hwrm_nvm_get_dir_entries_input req = {0};
3635 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3637 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3641 *data++ = dir_entries;
3642 *data++ = entry_length;
3644 memset(data, 0xff, len);
3646 buflen = dir_entries * entry_length;
3647 buf = rte_malloc("nvm_dir", buflen, 0);
3648 rte_mem_lock_page(buf);
3651 dma_handle = rte_mem_virt2iova(buf);
3652 if (dma_handle == RTE_BAD_IOVA) {
3654 "unable to map response address to physical memory\n");
3657 HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3658 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3659 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3662 memcpy(data, buf, len > buflen ? buflen : len);
3665 HWRM_CHECK_RESULT();
3671 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3672 uint32_t offset, uint32_t length,
3677 rte_iova_t dma_handle;
3678 struct hwrm_nvm_read_input req = {0};
3679 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3681 buf = rte_malloc("nvm_item", length, 0);
3682 rte_mem_lock_page(buf);
3686 dma_handle = rte_mem_virt2iova(buf);
3687 if (dma_handle == RTE_BAD_IOVA) {
3689 "unable to map response address to physical memory\n");
3692 HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3693 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3694 req.dir_idx = rte_cpu_to_le_16(index);
3695 req.offset = rte_cpu_to_le_32(offset);
3696 req.len = rte_cpu_to_le_32(length);
3697 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3699 memcpy(data, buf, length);
3702 HWRM_CHECK_RESULT();
3708 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3711 struct hwrm_nvm_erase_dir_entry_input req = {0};
3712 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3714 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3715 req.dir_idx = rte_cpu_to_le_16(index);
3716 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3717 HWRM_CHECK_RESULT();
3724 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3725 uint16_t dir_ordinal, uint16_t dir_ext,
3726 uint16_t dir_attr, const uint8_t *data,
3730 struct hwrm_nvm_write_input req = {0};
3731 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3732 rte_iova_t dma_handle;
3735 buf = rte_malloc("nvm_write", data_len, 0);
3736 rte_mem_lock_page(buf);
3740 dma_handle = rte_mem_virt2iova(buf);
3741 if (dma_handle == RTE_BAD_IOVA) {
3743 "unable to map response address to physical memory\n");
3746 memcpy(buf, data, data_len);
3748 HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3750 req.dir_type = rte_cpu_to_le_16(dir_type);
3751 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3752 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3753 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3754 req.dir_data_length = rte_cpu_to_le_32(data_len);
3755 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3757 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3760 HWRM_CHECK_RESULT();
3767 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3769 uint32_t *count = cbdata;
3771 *count = *count + 1;
3774 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3775 struct bnxt_vnic_info *vnic __rte_unused)
3780 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3784 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3785 &count, bnxt_vnic_count_hwrm_stub);
3790 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3793 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3794 struct hwrm_func_vf_vnic_ids_query_output *resp =
3795 bp->hwrm_cmd_resp_addr;
3798 /* First query all VNIC ids */
3799 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3801 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3802 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3803 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3805 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3808 "unable to map VNIC ID table address to physical memory\n");
3811 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3812 HWRM_CHECK_RESULT();
3813 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3821 * This function queries the VNIC IDs for a specified VF. It then calls
3822 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3823 * Then it calls the hwrm_cb function to program this new vnic configuration.
3825 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3826 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3827 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3829 struct bnxt_vnic_info vnic;
3831 int i, num_vnic_ids;
3836 /* First query all VNIC ids */
3837 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3838 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3839 RTE_CACHE_LINE_SIZE);
3840 if (vnic_ids == NULL)
3843 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3844 rte_mem_lock_page(((char *)vnic_ids) + sz);
3846 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3848 if (num_vnic_ids < 0)
3849 return num_vnic_ids;
3851 /* Retrieve VNIC, update bd_stall then update */
3853 for (i = 0; i < num_vnic_ids; i++) {
3854 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3855 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3856 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3859 if (vnic.mru <= 4) /* Indicates unallocated */
3862 vnic_cb(&vnic, cbdata);
3864 rc = hwrm_cb(bp, &vnic);
3874 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3877 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3878 struct hwrm_func_cfg_input req = {0};
3881 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3883 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3884 req.enables |= rte_cpu_to_le_32(
3885 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3886 req.vlan_antispoof_mode = on ?
3887 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3888 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3889 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3891 HWRM_CHECK_RESULT();
3897 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3899 struct bnxt_vnic_info vnic;
3902 int num_vnic_ids, i;
3906 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3907 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3908 RTE_CACHE_LINE_SIZE);
3909 if (vnic_ids == NULL)
3912 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3913 rte_mem_lock_page(((char *)vnic_ids) + sz);
3915 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3921 * Loop through to find the default VNIC ID.
3922 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3923 * by sending the hwrm_func_qcfg command to the firmware.
3925 for (i = 0; i < num_vnic_ids; i++) {
3926 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3927 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3928 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3929 bp->pf.first_vf_id + vf);
3932 if (vnic.func_default) {
3934 return vnic.fw_vnic_id;
3937 /* Could not find a default VNIC. */
3938 PMD_DRV_LOG(ERR, "No default VNIC\n");
3944 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3946 struct bnxt_filter_info *filter)
3949 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3950 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3951 uint32_t enables = 0;
3953 if (filter->fw_em_filter_id != UINT64_MAX)
3954 bnxt_hwrm_clear_em_filter(bp, filter);
3956 HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3958 req.flags = rte_cpu_to_le_32(filter->flags);
3960 enables = filter->enables |
3961 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3962 req.dst_id = rte_cpu_to_le_16(dst_id);
3964 if (filter->ip_addr_type) {
3965 req.ip_addr_type = filter->ip_addr_type;
3966 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3969 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3970 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3972 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3973 memcpy(req.src_macaddr, filter->src_macaddr,
3974 RTE_ETHER_ADDR_LEN);
3976 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3977 memcpy(req.dst_macaddr, filter->dst_macaddr,
3978 RTE_ETHER_ADDR_LEN);
3980 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3981 req.ovlan_vid = filter->l2_ovlan;
3983 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3984 req.ivlan_vid = filter->l2_ivlan;
3986 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3987 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3989 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3990 req.ip_protocol = filter->ip_protocol;
3992 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3993 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3995 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3996 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3998 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3999 req.src_port = rte_cpu_to_be_16(filter->src_port);
4001 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4002 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4004 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4005 req.mirror_vnic_id = filter->mirror_vnic_id;
4007 req.enables = rte_cpu_to_le_32(enables);
4009 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4011 HWRM_CHECK_RESULT();
4013 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4019 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4022 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4023 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4025 if (filter->fw_em_filter_id == UINT64_MAX)
4028 PMD_DRV_LOG(ERR, "Clear EM filter\n");
4029 HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4031 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4033 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4035 HWRM_CHECK_RESULT();
4038 filter->fw_em_filter_id = UINT64_MAX;
4039 filter->fw_l2_filter_id = UINT64_MAX;
4044 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4046 struct bnxt_filter_info *filter)
4049 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4050 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4051 bp->hwrm_cmd_resp_addr;
4052 uint32_t enables = 0;
4054 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4055 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4057 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4059 req.flags = rte_cpu_to_le_32(filter->flags);
4061 enables = filter->enables |
4062 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4063 req.dst_id = rte_cpu_to_le_16(dst_id);
4066 if (filter->ip_addr_type) {
4067 req.ip_addr_type = filter->ip_addr_type;
4069 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4072 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4073 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4075 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4076 memcpy(req.src_macaddr, filter->src_macaddr,
4077 RTE_ETHER_ADDR_LEN);
4079 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4080 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4081 //RTE_ETHER_ADDR_LEN);
4083 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4084 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4086 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4087 req.ip_protocol = filter->ip_protocol;
4089 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4090 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4092 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4093 req.src_ipaddr_mask[0] =
4094 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4096 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4097 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4099 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4100 req.dst_ipaddr_mask[0] =
4101 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4103 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4104 req.src_port = rte_cpu_to_le_16(filter->src_port);
4106 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4107 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4109 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4110 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4112 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4113 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4115 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4116 req.mirror_vnic_id = filter->mirror_vnic_id;
4118 req.enables = rte_cpu_to_le_32(enables);
4120 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4122 HWRM_CHECK_RESULT();
4124 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4130 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4131 struct bnxt_filter_info *filter)
4134 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4135 struct hwrm_cfa_ntuple_filter_free_output *resp =
4136 bp->hwrm_cmd_resp_addr;
4138 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4141 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4143 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4145 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4147 HWRM_CHECK_RESULT();
4150 filter->fw_ntuple_filter_id = UINT64_MAX;
4156 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4158 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4159 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4160 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4161 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4162 uint16_t *ring_tbl = vnic->rss_table;
4163 int nr_ctxs = vnic->num_lb_ctxts;
4164 int max_rings = bp->rx_nr_rings;
4168 for (i = 0, k = 0; i < nr_ctxs; i++) {
4169 struct bnxt_rx_ring_info *rxr;
4170 struct bnxt_cp_ring_info *cpr;
4172 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4174 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4175 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4176 req.hash_mode_flags = vnic->hash_mode;
4178 req.ring_grp_tbl_addr =
4179 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4180 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4181 2 * sizeof(*ring_tbl));
4182 req.hash_key_tbl_addr =
4183 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4185 req.ring_table_pair_index = i;
4186 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4188 for (j = 0; j < 64; j++) {
4191 /* Find next active ring. */
4192 for (cnt = 0; cnt < max_rings; cnt++) {
4193 if (rx_queue_state[k] !=
4194 RTE_ETH_QUEUE_STATE_STOPPED)
4196 if (++k == max_rings)
4200 /* Return if no rings are active. */
4201 if (cnt == max_rings)
4204 /* Add rx/cp ring pair to RSS table. */
4205 rxr = rxqs[k]->rx_ring;
4206 cpr = rxqs[k]->cp_ring;
4208 ring_id = rxr->rx_ring_struct->fw_ring_id;
4209 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4210 ring_id = cpr->cp_ring_struct->fw_ring_id;
4211 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4213 if (++k == max_rings)
4216 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4219 HWRM_CHECK_RESULT();
4226 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4228 unsigned int rss_idx, fw_idx, i;
4230 if (!(vnic->rss_table && vnic->hash_type))
4233 if (BNXT_CHIP_THOR(bp))
4234 return bnxt_vnic_rss_configure_thor(bp, vnic);
4237 * Fill the RSS hash & redirection table with
4238 * ring group ids for all VNICs
4240 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4241 rss_idx++, fw_idx++) {
4242 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4243 fw_idx %= bp->rx_cp_nr_rings;
4244 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4248 if (i == bp->rx_cp_nr_rings)
4250 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4252 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4255 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4256 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4260 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4262 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4263 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4265 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4266 req->num_cmpl_dma_aggr_during_int =
4267 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4269 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4271 /* min timer set to 1/2 of interrupt timer */
4272 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4274 /* buf timer set to 1/4 of interrupt timer */
4275 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4277 req->cmpl_aggr_dma_tmr_during_int =
4278 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4280 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4281 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4282 req->flags = rte_cpu_to_le_16(flags);
4285 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4286 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4288 struct hwrm_ring_aggint_qcaps_input req = {0};
4289 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4294 HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4295 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4296 HWRM_CHECK_RESULT();
4298 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4299 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4301 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4302 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4303 agg_req->flags = rte_cpu_to_le_16(flags);
4305 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4306 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4307 agg_req->enables = rte_cpu_to_le_32(enables);
4313 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4314 struct bnxt_coal *coal, uint16_t ring_id)
4316 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4317 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4318 bp->hwrm_cmd_resp_addr;
4321 /* Set ring coalesce parameters only for 100G NICs */
4322 if (BNXT_CHIP_THOR(bp)) {
4323 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4325 } else if (bnxt_stratus_device(bp)) {
4326 bnxt_hwrm_set_coal_params(coal, &req);
4331 HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4332 req.ring_id = rte_cpu_to_le_16(ring_id);
4333 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4334 HWRM_CHECK_RESULT();
4339 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4340 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4342 struct hwrm_func_backing_store_qcaps_input req = {0};
4343 struct hwrm_func_backing_store_qcaps_output *resp =
4344 bp->hwrm_cmd_resp_addr;
4347 if (!BNXT_CHIP_THOR(bp) ||
4348 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4353 HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4354 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4355 HWRM_CHECK_RESULT_SILENT();
4358 struct bnxt_ctx_pg_info *ctx_pg;
4359 struct bnxt_ctx_mem_info *ctx;
4360 int total_alloc_len;
4363 total_alloc_len = sizeof(*ctx);
4364 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4365 RTE_CACHE_LINE_SIZE);
4370 memset(ctx, 0, total_alloc_len);
4372 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4373 sizeof(*ctx_pg) * BNXT_MAX_Q,
4374 RTE_CACHE_LINE_SIZE);
4379 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4380 ctx->tqm_mem[i] = ctx_pg;
4383 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4384 ctx->qp_min_qp1_entries =
4385 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4386 ctx->qp_max_l2_entries =
4387 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4388 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4389 ctx->srq_max_l2_entries =
4390 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4391 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4392 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4393 ctx->cq_max_l2_entries =
4394 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4395 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4396 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4397 ctx->vnic_max_vnic_entries =
4398 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4399 ctx->vnic_max_ring_table_entries =
4400 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4401 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4402 ctx->stat_max_entries =
4403 rte_le_to_cpu_32(resp->stat_max_entries);
4404 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4405 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4406 ctx->tqm_min_entries_per_ring =
4407 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4408 ctx->tqm_max_entries_per_ring =
4409 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4410 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4411 if (!ctx->tqm_entries_multiple)
4412 ctx->tqm_entries_multiple = 1;
4413 ctx->mrav_max_entries =
4414 rte_le_to_cpu_32(resp->mrav_max_entries);
4415 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4416 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4417 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4426 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4428 struct hwrm_func_backing_store_cfg_input req = {0};
4429 struct hwrm_func_backing_store_cfg_output *resp =
4430 bp->hwrm_cmd_resp_addr;
4431 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4432 struct bnxt_ctx_pg_info *ctx_pg;
4433 uint32_t *num_entries;
4442 HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4443 req.enables = rte_cpu_to_le_32(enables);
4445 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4446 ctx_pg = &ctx->qp_mem;
4447 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4448 req.qp_num_qp1_entries =
4449 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4450 req.qp_num_l2_entries =
4451 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4452 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4453 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4454 &req.qpc_pg_size_qpc_lvl,
4458 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4459 ctx_pg = &ctx->srq_mem;
4460 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4461 req.srq_num_l2_entries =
4462 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4463 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4464 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4465 &req.srq_pg_size_srq_lvl,
4469 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4470 ctx_pg = &ctx->cq_mem;
4471 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4472 req.cq_num_l2_entries =
4473 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4474 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4475 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4476 &req.cq_pg_size_cq_lvl,
4480 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4481 ctx_pg = &ctx->vnic_mem;
4482 req.vnic_num_vnic_entries =
4483 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4484 req.vnic_num_ring_table_entries =
4485 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4486 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4487 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4488 &req.vnic_pg_size_vnic_lvl,
4489 &req.vnic_page_dir);
4492 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4493 ctx_pg = &ctx->stat_mem;
4494 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4495 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4496 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4497 &req.stat_pg_size_stat_lvl,
4498 &req.stat_page_dir);
4501 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4502 num_entries = &req.tqm_sp_num_entries;
4503 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4504 pg_dir = &req.tqm_sp_page_dir;
4505 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4506 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4507 if (!(enables & ena))
4510 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4512 ctx_pg = ctx->tqm_mem[i];
4513 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4514 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4517 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4518 HWRM_CHECK_RESULT();
4524 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4526 struct hwrm_port_qstats_ext_input req = {0};
4527 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4528 struct bnxt_pf_info *pf = &bp->pf;
4531 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4532 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4535 HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4537 req.port_id = rte_cpu_to_le_16(pf->port_id);
4538 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4539 req.tx_stat_host_addr =
4540 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4542 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4544 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4545 req.rx_stat_host_addr =
4546 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4548 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4550 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4553 bp->fw_rx_port_stats_ext_size = 0;
4554 bp->fw_tx_port_stats_ext_size = 0;
4556 bp->fw_rx_port_stats_ext_size =
4557 rte_le_to_cpu_16(resp->rx_stat_size);
4558 bp->fw_tx_port_stats_ext_size =
4559 rte_le_to_cpu_16(resp->tx_stat_size);
4562 HWRM_CHECK_RESULT();
4569 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4571 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4572 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4573 bp->hwrm_cmd_resp_addr;
4576 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4577 req.tunnel_type = type;
4578 req.dest_fid = bp->fw_fid;
4579 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4580 HWRM_CHECK_RESULT();
4588 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4590 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4591 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4592 bp->hwrm_cmd_resp_addr;
4595 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4596 req.tunnel_type = type;
4597 req.dest_fid = bp->fw_fid;
4598 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4599 HWRM_CHECK_RESULT();
4606 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4608 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4609 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4610 bp->hwrm_cmd_resp_addr;
4613 HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4614 req.src_fid = bp->fw_fid;
4615 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4616 HWRM_CHECK_RESULT();
4619 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4626 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4629 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4630 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4631 bp->hwrm_cmd_resp_addr;
4634 HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4635 req.src_fid = bp->fw_fid;
4636 req.tunnel_type = tun_type;
4637 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4638 HWRM_CHECK_RESULT();
4641 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4643 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4650 int bnxt_hwrm_set_mac(struct bnxt *bp)
4652 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4653 struct hwrm_func_vf_cfg_input req = {0};
4659 HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4662 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4663 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4665 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4667 HWRM_CHECK_RESULT();
4669 memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4675 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4677 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4678 struct hwrm_func_drv_if_change_input req = {0};
4682 if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4685 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4686 * If we issue FUNC_DRV_IF_CHANGE with flags down before
4687 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4689 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4692 HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4696 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4698 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4700 HWRM_CHECK_RESULT();
4701 flags = rte_le_to_cpu_32(resp->flags);
4704 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4705 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4706 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4712 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4714 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4715 struct bnxt_error_recovery_info *info = bp->recovery_info;
4716 struct hwrm_error_recovery_qcfg_input req = {0};
4721 /* Older FW does not have error recovery support */
4722 if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4726 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4728 bp->recovery_info = info;
4732 memset(info, 0, sizeof(*info));
4735 HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4737 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4739 HWRM_CHECK_RESULT();
4741 flags = rte_le_to_cpu_32(resp->flags);
4742 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4743 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4744 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4745 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4747 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4748 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4753 /* FW returned values are in units of 100msec */
4754 info->driver_polling_freq =
4755 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4756 info->master_func_wait_period =
4757 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4758 info->normal_func_wait_period =
4759 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4760 info->master_func_wait_period_after_reset =
4761 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4762 info->max_bailout_time_after_reset =
4763 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4764 info->status_regs[BNXT_FW_STATUS_REG] =
4765 rte_le_to_cpu_32(resp->fw_health_status_reg);
4766 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4767 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4768 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4769 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4770 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4771 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4772 info->reg_array_cnt =
4773 rte_le_to_cpu_32(resp->reg_array_cnt);
4775 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4780 for (i = 0; i < info->reg_array_cnt; i++) {
4781 info->reset_reg[i] =
4782 rte_le_to_cpu_32(resp->reset_reg[i]);
4783 info->reset_reg_val[i] =
4784 rte_le_to_cpu_32(resp->reset_reg_val[i]);
4785 info->delay_after_reset[i] =
4786 resp->delay_after_reset[i];
4792 rte_free(bp->recovery_info);
4793 bp->recovery_info = NULL;