1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
6 #include <rte_bitmap.h>
7 #include <rte_memzone.h>
8 #include <rte_malloc.h>
12 #include "bnxt_hwrm.h"
13 #include "bnxt_ring.h"
19 #include "hsi_struct_def_dpdk.h"
22 * Generic ring handling
25 void bnxt_free_ring(struct bnxt_ring *ring)
30 if (ring->vmem_size && *ring->vmem) {
31 memset((char *)*ring->vmem, 0, ring->vmem_size);
34 ring->mem_zone = NULL;
41 static void bnxt_init_ring_grps(struct bnxt *bp)
45 for (i = 0; i < bp->max_ring_grps; i++)
46 memset(&bp->grp_info[i], (uint8_t)HWRM_NA_SIGNATURE,
47 sizeof(struct bnxt_ring_grp_info));
50 int bnxt_alloc_ring_grps(struct bnxt *bp)
52 if (bp->max_tx_rings == 0) {
53 PMD_DRV_LOG(ERR, "No TX rings available!\n");
57 /* THOR does not support ring groups.
58 * But we will use the array to save RSS context IDs.
60 if (BNXT_CHIP_P5(bp)) {
61 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
62 } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
63 /* 1 ring is for default completion ring */
64 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
68 if (BNXT_HAS_RING_GRPS(bp)) {
69 bp->grp_info = rte_zmalloc("bnxt_grp_info",
70 sizeof(*bp->grp_info) *
71 bp->max_ring_grps, 0);
74 "Failed to alloc grp info tbl.\n");
77 bnxt_init_ring_grps(bp);
84 * Allocates a completion ring with vmem and stats optionally also allocating
85 * a TX and/or RX ring. Passing NULL as tx_ring_info and/or rx_ring_info
86 * to not allocate them.
88 * Order in the allocation is:
89 * stats - Always non-zero length
90 * cp vmem - Always zero-length, supported for the bnxt_ring abstraction
91 * tx vmem - Only non-zero length if tx_ring_info is not NULL
92 * rx vmem - Only non-zero length if rx_ring_info is not NULL
93 * cp bd ring - Always non-zero length
94 * tx bd ring - Only non-zero length if tx_ring_info is not NULL
95 * rx bd ring - Only non-zero length if rx_ring_info is not NULL
97 int bnxt_alloc_rings(struct bnxt *bp, uint16_t qidx,
98 struct bnxt_tx_queue *txq,
99 struct bnxt_rx_queue *rxq,
100 struct bnxt_cp_ring_info *cp_ring_info,
101 struct bnxt_cp_ring_info *nq_ring_info,
104 struct bnxt_ring *cp_ring = cp_ring_info->cp_ring_struct;
105 struct bnxt_rx_ring_info *rx_ring_info = rxq ? rxq->rx_ring : NULL;
106 struct bnxt_tx_ring_info *tx_ring_info = txq ? txq->tx_ring : NULL;
107 struct bnxt_ring *tx_ring;
108 struct bnxt_ring *rx_ring;
109 struct rte_pci_device *pdev = bp->pdev;
110 uint64_t rx_offloads = bp->eth_dev->data->dev_conf.rxmode.offloads;
111 const struct rte_memzone *mz = NULL;
112 char mz_name[RTE_MEMZONE_NAMESIZE];
113 rte_iova_t mz_phys_addr;
115 int stats_len = (tx_ring_info || rx_ring_info) ?
116 RTE_CACHE_LINE_ROUNDUP(sizeof(struct hwrm_stat_ctx_query_output) -
117 sizeof (struct hwrm_resp_hdr)) : 0;
118 stats_len = RTE_ALIGN(stats_len, 128);
120 int cp_vmem_start = stats_len;
121 int cp_vmem_len = RTE_CACHE_LINE_ROUNDUP(cp_ring->vmem_size);
122 cp_vmem_len = RTE_ALIGN(cp_vmem_len, 128);
124 int nq_vmem_len = nq_ring_info ?
125 RTE_CACHE_LINE_ROUNDUP(cp_ring->vmem_size) : 0;
126 nq_vmem_len = RTE_ALIGN(nq_vmem_len, 128);
128 int nq_vmem_start = cp_vmem_start + cp_vmem_len;
130 int tx_vmem_start = nq_vmem_start + nq_vmem_len;
132 tx_ring_info ? RTE_CACHE_LINE_ROUNDUP(tx_ring_info->
133 tx_ring_struct->vmem_size) : 0;
134 tx_vmem_len = RTE_ALIGN(tx_vmem_len, 128);
136 int rx_vmem_start = tx_vmem_start + tx_vmem_len;
137 int rx_vmem_len = rx_ring_info ?
138 RTE_CACHE_LINE_ROUNDUP(rx_ring_info->
139 rx_ring_struct->vmem_size) : 0;
140 rx_vmem_len = RTE_ALIGN(rx_vmem_len, 128);
141 int ag_vmem_start = 0;
143 int cp_ring_start = 0;
144 int nq_ring_start = 0;
146 ag_vmem_start = rx_vmem_start + rx_vmem_len;
147 ag_vmem_len = rx_ring_info ? RTE_CACHE_LINE_ROUNDUP(
148 rx_ring_info->ag_ring_struct->vmem_size) : 0;
149 cp_ring_start = ag_vmem_start + ag_vmem_len;
150 cp_ring_start = RTE_ALIGN(cp_ring_start, 4096);
152 int cp_ring_len = RTE_CACHE_LINE_ROUNDUP(cp_ring->ring_size *
153 sizeof(struct cmpl_base));
154 cp_ring_len = RTE_ALIGN(cp_ring_len, 128);
155 nq_ring_start = cp_ring_start + cp_ring_len;
156 nq_ring_start = RTE_ALIGN(nq_ring_start, 4096);
158 int nq_ring_len = nq_ring_info ? cp_ring_len : 0;
160 int tx_ring_start = nq_ring_start + nq_ring_len;
161 tx_ring_start = RTE_ALIGN(tx_ring_start, 4096);
162 int tx_ring_len = tx_ring_info ?
163 RTE_CACHE_LINE_ROUNDUP(tx_ring_info->tx_ring_struct->ring_size *
164 sizeof(struct tx_bd_long)) : 0;
165 tx_ring_len = RTE_ALIGN(tx_ring_len, 4096);
167 int rx_ring_start = tx_ring_start + tx_ring_len;
168 rx_ring_start = RTE_ALIGN(rx_ring_start, 4096);
169 int rx_ring_len = rx_ring_info ?
170 RTE_CACHE_LINE_ROUNDUP(rx_ring_info->rx_ring_struct->ring_size *
171 sizeof(struct rx_prod_pkt_bd)) : 0;
172 rx_ring_len = RTE_ALIGN(rx_ring_len, 4096);
174 int ag_ring_start = rx_ring_start + rx_ring_len;
175 ag_ring_start = RTE_ALIGN(ag_ring_start, 4096);
176 int ag_ring_len = rx_ring_len * AGG_RING_SIZE_FACTOR;
177 ag_ring_len = RTE_ALIGN(ag_ring_len, 4096);
179 int ag_bitmap_start = ag_ring_start + ag_ring_len;
180 int ag_bitmap_len = rx_ring_info ?
181 RTE_CACHE_LINE_ROUNDUP(rte_bitmap_get_memory_footprint(
182 rx_ring_info->rx_ring_struct->ring_size *
183 AGG_RING_SIZE_FACTOR)) : 0;
185 int tpa_info_start = ag_bitmap_start + ag_bitmap_len;
186 int tpa_info_len = 0;
188 if (rx_ring_info && (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)) {
189 int tpa_max = BNXT_TPA_MAX_AGGS(bp);
191 tpa_info_len = tpa_max * sizeof(struct bnxt_tpa_info);
192 tpa_info_len = RTE_CACHE_LINE_ROUNDUP(tpa_info_len);
195 int total_alloc_len = tpa_info_start;
196 total_alloc_len += tpa_info_len;
198 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
199 "bnxt_" PCI_PRI_FMT "-%04x_%s", pdev->addr.domain,
200 pdev->addr.bus, pdev->addr.devid, pdev->addr.function, qidx,
202 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
203 mz = rte_memzone_lookup(mz_name);
205 mz = rte_memzone_reserve_aligned(mz_name, total_alloc_len,
208 RTE_MEMZONE_SIZE_HINT_ONLY |
209 RTE_MEMZONE_IOVA_CONTIG,
214 memset(mz->addr, 0, mz->len);
215 mz_phys_addr = mz->iova;
219 tx_ring = tx_ring_info->tx_ring_struct;
221 tx_ring->bd = ((char *)mz->addr + tx_ring_start);
222 tx_ring_info->tx_desc_ring = (struct tx_bd_long *)tx_ring->bd;
223 tx_ring->bd_dma = mz_phys_addr + tx_ring_start;
224 tx_ring_info->tx_desc_mapping = tx_ring->bd_dma;
225 tx_ring->mem_zone = (const void *)mz;
229 if (tx_ring->vmem_size) {
231 (void **)((char *)mz->addr + tx_vmem_start);
232 tx_ring_info->tx_buf_ring =
233 (struct bnxt_sw_tx_bd *)tx_ring->vmem;
239 rx_ring = rx_ring_info->rx_ring_struct;
241 rx_ring->bd = ((char *)mz->addr + rx_ring_start);
242 rx_ring_info->rx_desc_ring =
243 (struct rx_prod_pkt_bd *)rx_ring->bd;
244 rx_ring->bd_dma = mz_phys_addr + rx_ring_start;
245 rx_ring_info->rx_desc_mapping = rx_ring->bd_dma;
246 rx_ring->mem_zone = (const void *)mz;
250 if (rx_ring->vmem_size) {
252 (void **)((char *)mz->addr + rx_vmem_start);
253 rx_ring_info->rx_buf_ring =
254 (struct rte_mbuf **)rx_ring->vmem;
257 rx_ring = rx_ring_info->ag_ring_struct;
259 rx_ring->bd = ((char *)mz->addr + ag_ring_start);
260 rx_ring_info->ag_desc_ring =
261 (struct rx_prod_pkt_bd *)rx_ring->bd;
262 rx_ring->bd_dma = mz->iova + ag_ring_start;
263 rx_ring_info->ag_desc_mapping = rx_ring->bd_dma;
264 rx_ring->mem_zone = (const void *)mz;
268 if (rx_ring->vmem_size) {
270 (void **)((char *)mz->addr + ag_vmem_start);
271 rx_ring_info->ag_buf_ring =
272 (struct rte_mbuf **)rx_ring->vmem;
275 rx_ring_info->ag_bitmap =
276 rte_bitmap_init(rx_ring_info->rx_ring_struct->ring_size *
277 AGG_RING_SIZE_FACTOR, (uint8_t *)mz->addr +
278 ag_bitmap_start, ag_bitmap_len);
281 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
282 rx_ring_info->tpa_info =
283 ((struct bnxt_tpa_info *)((char *)mz->addr +
287 cp_ring->bd = ((char *)mz->addr + cp_ring_start);
288 cp_ring->bd_dma = mz_phys_addr + cp_ring_start;
289 cp_ring_info->cp_desc_ring = cp_ring->bd;
290 cp_ring_info->cp_desc_mapping = cp_ring->bd_dma;
291 cp_ring->mem_zone = (const void *)mz;
295 if (cp_ring->vmem_size)
296 *cp_ring->vmem = ((char *)mz->addr + stats_len);
298 cp_ring_info->hw_stats = mz->addr;
299 cp_ring_info->hw_stats_map = mz_phys_addr;
301 cp_ring_info->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
304 struct bnxt_ring *nq_ring = nq_ring_info->cp_ring_struct;
306 nq_ring->bd = (char *)mz->addr + nq_ring_start;
307 nq_ring->bd_dma = mz_phys_addr + nq_ring_start;
308 nq_ring_info->cp_desc_ring = nq_ring->bd;
309 nq_ring_info->cp_desc_mapping = nq_ring->bd_dma;
310 nq_ring->mem_zone = (const void *)mz;
314 if (nq_ring->vmem_size)
315 *nq_ring->vmem = (char *)mz->addr + nq_vmem_start;
317 nq_ring_info->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
323 static void bnxt_init_dflt_coal(struct bnxt_coal *coal)
325 /* Tick values in micro seconds.
326 * 1 coal_buf x bufs_per_record = 1 completion record.
328 coal->num_cmpl_aggr_int = BNXT_NUM_CMPL_AGGR_INT;
329 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
330 coal->num_cmpl_dma_aggr = BNXT_NUM_CMPL_DMA_AGGR;
331 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
332 coal->num_cmpl_dma_aggr_during_int = BNXT_NUM_CMPL_DMA_AGGR_DURING_INT;
333 coal->int_lat_tmr_max = BNXT_INT_LAT_TMR_MAX;
334 /* min timer set to 1/2 of interrupt timer */
335 coal->int_lat_tmr_min = BNXT_INT_LAT_TMR_MIN;
336 /* buf timer set to 1/4 of interrupt timer */
337 coal->cmpl_aggr_dma_tmr = BNXT_CMPL_AGGR_DMA_TMR;
338 coal->cmpl_aggr_dma_tmr_during_int = BNXT_CMPL_AGGR_DMA_TMR_DURING_INT;
341 static void bnxt_set_db(struct bnxt *bp,
342 struct bnxt_db_info *db,
348 if (BNXT_CHIP_P5(bp)) {
350 db->doorbell = (char *)bp->doorbell_base + 0x10000;
352 db->doorbell = (char *)bp->doorbell_base + 0x4000;
354 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
355 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
357 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
358 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
359 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
361 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
362 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_CQ;
364 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
365 db->db_key64 = DBR_PATH_L2;
368 db->db_key64 |= (uint64_t)fid << DBR_XID_SFT;
371 db->doorbell = (char *)bp->doorbell_base + map_idx * 0x80;
373 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
374 db->db_key32 = DB_KEY_TX;
376 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
377 db->db_key32 = DB_KEY_RX;
379 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
380 db->db_key32 = DB_KEY_CP;
385 db->db_ring_mask = ring_mask;
388 static int bnxt_alloc_cmpl_ring(struct bnxt *bp, int queue_index,
389 struct bnxt_cp_ring_info *cpr)
391 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
392 uint32_t nq_ring_id = HWRM_NA_SIGNATURE;
393 int cp_ring_index = queue_index + BNXT_RX_VEC_START;
394 struct bnxt_cp_ring_info *nqr = bp->rxtx_nq_ring;
398 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL;
400 if (BNXT_HAS_NQ(bp)) {
402 nq_ring_id = nqr->cp_ring_struct->fw_ring_id;
404 PMD_DRV_LOG(ERR, "NQ ring is NULL\n");
409 rc = bnxt_hwrm_ring_alloc(bp, cp_ring, ring_type, cp_ring_index,
410 HWRM_NA_SIGNATURE, nq_ring_id, 0);
414 cpr->cp_raw_cons = 0;
415 bnxt_set_db(bp, &cpr->cp_db, ring_type, cp_ring_index,
416 cp_ring->fw_ring_id, cp_ring->ring_mask);
422 int bnxt_alloc_rxtx_nq_ring(struct bnxt *bp)
424 struct bnxt_cp_ring_info *nqr;
425 struct bnxt_ring *ring;
426 int ring_index = BNXT_NUM_ASYNC_CPR(bp);
427 unsigned int socket_id;
431 if (!BNXT_HAS_NQ(bp) || bp->rxtx_nq_ring)
434 socket_id = rte_lcore_to_socket_id(rte_get_main_lcore());
436 nqr = rte_zmalloc_socket("nqr",
437 sizeof(struct bnxt_cp_ring_info),
438 RTE_CACHE_LINE_SIZE, socket_id);
442 ring = rte_zmalloc_socket("bnxt_cp_ring_struct",
443 sizeof(struct bnxt_ring),
444 RTE_CACHE_LINE_SIZE, socket_id);
450 ring->bd = (void *)nqr->cp_desc_ring;
451 ring->bd_dma = nqr->cp_desc_mapping;
452 ring->ring_size = rte_align32pow2(DEFAULT_CP_RING_SIZE);
453 ring->ring_mask = ring->ring_size - 1;
456 ring->fw_ring_id = INVALID_HW_RING_ID;
458 nqr->cp_ring_struct = ring;
459 rc = bnxt_alloc_rings(bp, 0, NULL, NULL, nqr, NULL, "l2_nqr");
466 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ;
468 rc = bnxt_hwrm_ring_alloc(bp, ring, ring_type, ring_index,
469 HWRM_NA_SIGNATURE, HWRM_NA_SIGNATURE, 0);
476 bnxt_set_db(bp, &nqr->cp_db, ring_type, ring_index,
477 ring->fw_ring_id, ring->ring_mask);
480 bp->rxtx_nq_ring = nqr;
485 /* Free RX/TX NQ ring. */
486 void bnxt_free_rxtx_nq_ring(struct bnxt *bp)
488 struct bnxt_cp_ring_info *nqr = bp->rxtx_nq_ring;
493 bnxt_free_nq_ring(bp, nqr);
495 bnxt_free_ring(nqr->cp_ring_struct);
496 rte_free(nqr->cp_ring_struct);
497 nqr->cp_ring_struct = NULL;
499 bp->rxtx_nq_ring = NULL;
502 static int bnxt_alloc_rx_ring(struct bnxt *bp, int queue_index)
504 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
505 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
506 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
507 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
508 struct bnxt_ring *ring = rxr->rx_ring_struct;
512 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_RX;
514 rc = bnxt_hwrm_ring_alloc(bp, ring, ring_type,
515 queue_index, cpr->hw_stats_ctx_id,
516 cp_ring->fw_ring_id, 0);
520 rxr->rx_raw_prod = 0;
521 if (BNXT_HAS_RING_GRPS(bp))
522 bp->grp_info[queue_index].rx_fw_ring_id = ring->fw_ring_id;
523 bnxt_set_db(bp, &rxr->rx_db, ring_type, queue_index, ring->fw_ring_id,
525 bnxt_db_write(&rxr->rx_db, rxr->rx_raw_prod);
530 static int bnxt_alloc_rx_agg_ring(struct bnxt *bp, int queue_index)
532 unsigned int map_idx = queue_index + bp->rx_cp_nr_rings;
533 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
534 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
535 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
536 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
537 struct bnxt_ring *ring = rxr->ag_ring_struct;
538 uint32_t hw_stats_ctx_id = HWRM_NA_SIGNATURE;
542 ring->fw_rx_ring_id = rxr->rx_ring_struct->fw_ring_id;
544 if (BNXT_CHIP_P5(bp)) {
545 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG;
546 hw_stats_ctx_id = cpr->hw_stats_ctx_id;
548 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_RX;
551 rc = bnxt_hwrm_ring_alloc(bp, ring, ring_type, map_idx,
552 hw_stats_ctx_id, cp_ring->fw_ring_id, 0);
557 rxr->ag_raw_prod = 0;
558 if (BNXT_HAS_RING_GRPS(bp))
559 bp->grp_info[queue_index].ag_fw_ring_id = ring->fw_ring_id;
560 bnxt_set_db(bp, &rxr->ag_db, ring_type, map_idx, ring->fw_ring_id,
562 bnxt_db_write(&rxr->ag_db, rxr->ag_raw_prod);
567 int bnxt_alloc_hwrm_rx_ring(struct bnxt *bp, int queue_index)
569 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
570 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
571 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
572 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
575 rc = bnxt_alloc_cmpl_ring(bp, queue_index, cpr);
579 if (BNXT_HAS_RING_GRPS(bp)) {
580 bp->grp_info[queue_index].fw_stats_ctx = cpr->hw_stats_ctx_id;
581 bp->grp_info[queue_index].cp_fw_ring_id = cp_ring->fw_ring_id;
584 if (!BNXT_NUM_ASYNC_CPR(bp) && !queue_index) {
586 * If a dedicated async event completion ring is not enabled,
587 * use the first completion ring from PF or VF as the default
588 * completion ring for async event handling.
590 bp->async_cp_ring = cpr;
591 rc = bnxt_hwrm_set_async_event_cr(bp);
596 rc = bnxt_alloc_rx_ring(bp, queue_index);
600 rc = bnxt_alloc_rx_agg_ring(bp, queue_index);
604 if (rxq->rx_started) {
605 if (bnxt_init_one_rx_ring(rxq)) {
606 PMD_DRV_LOG(ERR, "bnxt_init_one_rx_ring failed!\n");
607 bnxt_rx_queue_release_op(rxq);
611 bnxt_db_write(&rxr->rx_db, rxr->rx_raw_prod);
612 bnxt_db_write(&rxr->ag_db, rxr->ag_raw_prod);
614 rxq->index = queue_index;
615 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
616 bnxt_rxq_vec_setup(rxq);
623 "Failed to allocate receive queue %d, rc %d.\n",
628 /* Initialise all rings to -1, its used to free rings later if allocation
629 * of few rings fails.
631 static void bnxt_init_all_rings(struct bnxt *bp)
634 struct bnxt_rx_queue *rxq;
635 struct bnxt_ring *cp_ring;
636 struct bnxt_ring *ring;
637 struct bnxt_rx_ring_info *rxr;
638 struct bnxt_tx_queue *txq;
640 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
641 rxq = bp->rx_queues[i];
643 cp_ring = rxq->cp_ring->cp_ring_struct;
644 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
647 ring = rxr->rx_ring_struct;
648 ring->fw_ring_id = INVALID_HW_RING_ID;
650 ring = rxr->ag_ring_struct;
651 ring->fw_ring_id = INVALID_HW_RING_ID;
653 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
654 txq = bp->tx_queues[i];
656 cp_ring = txq->cp_ring->cp_ring_struct;
657 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
659 ring = txq->tx_ring->tx_ring_struct;
660 ring->fw_ring_id = INVALID_HW_RING_ID;
665 * [0] = default completion ring
666 * [1 -> +rx_cp_nr_rings] = rx_cp, rx rings
667 * [1+rx_cp_nr_rings + 1 -> +tx_cp_nr_rings] = tx_cp, tx rings
669 int bnxt_alloc_hwrm_rings(struct bnxt *bp)
671 struct bnxt_coal coal;
676 bnxt_init_dflt_coal(&coal);
677 bnxt_init_all_rings(bp);
679 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
680 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
681 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
682 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
683 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
685 if (bnxt_alloc_cmpl_ring(bp, i, cpr))
688 if (BNXT_HAS_RING_GRPS(bp)) {
689 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
690 bp->grp_info[i].cp_fw_ring_id = cp_ring->fw_ring_id;
693 bnxt_hwrm_set_ring_coal(bp, &coal, cp_ring->fw_ring_id);
694 if (!BNXT_NUM_ASYNC_CPR(bp) && !i) {
696 * If a dedicated async event completion ring is not
697 * enabled, use the first completion ring as the default
698 * completion ring for async event handling.
700 bp->async_cp_ring = cpr;
701 rc = bnxt_hwrm_set_async_event_cr(bp);
706 if (bnxt_alloc_rx_ring(bp, i))
709 if (bnxt_alloc_rx_agg_ring(bp, i))
712 if (bnxt_init_one_rx_ring(rxq)) {
713 PMD_DRV_LOG(ERR, "bnxt_init_one_rx_ring failed!\n");
714 bnxt_rx_queue_release_op(rxq);
717 bnxt_db_write(&rxr->rx_db, rxr->rx_raw_prod);
718 bnxt_db_write(&rxr->ag_db, rxr->ag_raw_prod);
720 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
721 bnxt_rxq_vec_setup(rxq);
725 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
726 struct bnxt_tx_queue *txq = bp->tx_queues[i];
727 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
728 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
729 struct bnxt_tx_ring_info *txr = txq->tx_ring;
730 struct bnxt_ring *ring = txr->tx_ring_struct;
731 unsigned int idx = i + bp->rx_cp_nr_rings;
732 uint16_t tx_cosq_id = 0;
734 if (bnxt_alloc_cmpl_ring(bp, idx, cpr))
737 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY)
738 tx_cosq_id = bp->tx_cosq_id[i < bp->max_lltc ? i : 0];
740 tx_cosq_id = bp->tx_cosq_id[0];
742 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_TX;
743 rc = bnxt_hwrm_ring_alloc(bp, ring,
745 i, cpr->hw_stats_ctx_id,
751 bnxt_set_db(bp, &txr->tx_db, ring_type, i, ring->fw_ring_id,
754 bnxt_hwrm_set_ring_coal(bp, &coal, cp_ring->fw_ring_id);
761 /* Allocate dedicated async completion ring. */
762 int bnxt_alloc_async_cp_ring(struct bnxt *bp)
764 struct bnxt_cp_ring_info *cpr = bp->async_cp_ring;
765 struct bnxt_ring *cp_ring;
769 if (BNXT_NUM_ASYNC_CPR(bp) == 0 || cpr == NULL)
772 cp_ring = cpr->cp_ring_struct;
775 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ;
777 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL;
779 rc = bnxt_hwrm_ring_alloc(bp, cp_ring, ring_type, 0,
780 HWRM_NA_SIGNATURE, HWRM_NA_SIGNATURE, 0);
785 cpr->cp_raw_cons = 0;
787 bnxt_set_db(bp, &cpr->cp_db, ring_type, 0,
788 cp_ring->fw_ring_id, cp_ring->ring_mask);
795 return bnxt_hwrm_set_async_event_cr(bp);
798 /* Free dedicated async completion ring. */
799 void bnxt_free_async_cp_ring(struct bnxt *bp)
801 struct bnxt_cp_ring_info *cpr = bp->async_cp_ring;
803 if (BNXT_NUM_ASYNC_CPR(bp) == 0 || cpr == NULL)
807 bnxt_free_nq_ring(bp, cpr);
809 bnxt_free_cp_ring(bp, cpr);
811 bnxt_free_ring(cpr->cp_ring_struct);
812 rte_free(cpr->cp_ring_struct);
813 cpr->cp_ring_struct = NULL;
815 bp->async_cp_ring = NULL;
818 int bnxt_alloc_async_ring_struct(struct bnxt *bp)
820 struct bnxt_cp_ring_info *cpr = NULL;
821 struct bnxt_ring *ring = NULL;
822 unsigned int socket_id;
824 if (BNXT_NUM_ASYNC_CPR(bp) == 0)
827 socket_id = rte_lcore_to_socket_id(rte_get_main_lcore());
829 cpr = rte_zmalloc_socket("cpr",
830 sizeof(struct bnxt_cp_ring_info),
831 RTE_CACHE_LINE_SIZE, socket_id);
835 ring = rte_zmalloc_socket("bnxt_cp_ring_struct",
836 sizeof(struct bnxt_ring),
837 RTE_CACHE_LINE_SIZE, socket_id);
843 ring->bd = (void *)cpr->cp_desc_ring;
844 ring->bd_dma = cpr->cp_desc_mapping;
845 ring->ring_size = rte_align32pow2(DEFAULT_CP_RING_SIZE);
846 ring->ring_mask = ring->ring_size - 1;
850 bp->async_cp_ring = cpr;
851 cpr->cp_ring_struct = ring;
853 return bnxt_alloc_rings(bp, 0, NULL, NULL,
854 bp->async_cp_ring, NULL,