1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
6 #include <rte_bitmap.h>
7 #include <rte_memzone.h>
8 #include <rte_malloc.h>
13 #include "bnxt_hwrm.h"
14 #include "bnxt_ring.h"
20 #include "hsi_struct_def_dpdk.h"
23 * Generic ring handling
26 void bnxt_free_ring(struct bnxt_ring *ring)
31 if (ring->vmem_size && *ring->vmem) {
32 memset((char *)*ring->vmem, 0, ring->vmem_size);
35 ring->mem_zone = NULL;
42 int bnxt_init_ring_grps(struct bnxt *bp)
46 for (i = 0; i < bp->max_ring_grps; i++)
47 memset(&bp->grp_info[i], (uint8_t)HWRM_NA_SIGNATURE,
48 sizeof(struct bnxt_ring_grp_info));
53 int bnxt_alloc_ring_grps(struct bnxt *bp)
55 if (bp->max_tx_rings == 0) {
56 PMD_DRV_LOG(ERR, "No TX rings available!\n");
60 /* THOR does not support ring groups.
61 * But we will use the array to save RSS context IDs.
63 if (BNXT_CHIP_THOR(bp)) {
64 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
65 } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
66 /* 1 ring is for default completion ring */
67 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
71 if (BNXT_HAS_RING_GRPS(bp)) {
72 bp->grp_info = rte_zmalloc("bnxt_grp_info",
73 sizeof(*bp->grp_info) *
74 bp->max_ring_grps, 0);
77 "Failed to alloc grp info tbl.\n");
86 * Allocates a completion ring with vmem and stats optionally also allocating
87 * a TX and/or RX ring. Passing NULL as tx_ring_info and/or rx_ring_info
88 * to not allocate them.
90 * Order in the allocation is:
91 * stats - Always non-zero length
92 * cp vmem - Always zero-length, supported for the bnxt_ring abstraction
93 * tx vmem - Only non-zero length if tx_ring_info is not NULL
94 * rx vmem - Only non-zero length if rx_ring_info is not NULL
95 * cp bd ring - Always non-zero length
96 * tx bd ring - Only non-zero length if tx_ring_info is not NULL
97 * rx bd ring - Only non-zero length if rx_ring_info is not NULL
99 int bnxt_alloc_rings(struct bnxt *bp, uint16_t qidx,
100 struct bnxt_tx_queue *txq,
101 struct bnxt_rx_queue *rxq,
102 struct bnxt_cp_ring_info *cp_ring_info,
103 struct bnxt_cp_ring_info *nq_ring_info,
106 struct bnxt_ring *cp_ring = cp_ring_info->cp_ring_struct;
107 struct bnxt_rx_ring_info *rx_ring_info = rxq ? rxq->rx_ring : NULL;
108 struct bnxt_tx_ring_info *tx_ring_info = txq ? txq->tx_ring : NULL;
109 struct bnxt_ring *tx_ring;
110 struct bnxt_ring *rx_ring;
111 struct rte_pci_device *pdev = bp->pdev;
112 uint64_t rx_offloads = bp->eth_dev->data->dev_conf.rxmode.offloads;
113 const struct rte_memzone *mz = NULL;
114 char mz_name[RTE_MEMZONE_NAMESIZE];
115 rte_iova_t mz_phys_addr_base;
116 rte_iova_t mz_phys_addr;
119 int stats_len = (tx_ring_info || rx_ring_info) ?
120 RTE_CACHE_LINE_ROUNDUP(sizeof(struct hwrm_stat_ctx_query_output) -
121 sizeof (struct hwrm_resp_hdr)) : 0;
122 stats_len = RTE_ALIGN(stats_len, 128);
124 int cp_vmem_start = stats_len;
125 int cp_vmem_len = RTE_CACHE_LINE_ROUNDUP(cp_ring->vmem_size);
126 cp_vmem_len = RTE_ALIGN(cp_vmem_len, 128);
128 int nq_vmem_len = BNXT_CHIP_THOR(bp) ?
129 RTE_CACHE_LINE_ROUNDUP(cp_ring->vmem_size) : 0;
130 nq_vmem_len = RTE_ALIGN(nq_vmem_len, 128);
132 int nq_vmem_start = cp_vmem_start + cp_vmem_len;
134 int tx_vmem_start = nq_vmem_start + nq_vmem_len;
136 tx_ring_info ? RTE_CACHE_LINE_ROUNDUP(tx_ring_info->
137 tx_ring_struct->vmem_size) : 0;
138 tx_vmem_len = RTE_ALIGN(tx_vmem_len, 128);
140 int rx_vmem_start = tx_vmem_start + tx_vmem_len;
141 int rx_vmem_len = rx_ring_info ?
142 RTE_CACHE_LINE_ROUNDUP(rx_ring_info->
143 rx_ring_struct->vmem_size) : 0;
144 rx_vmem_len = RTE_ALIGN(rx_vmem_len, 128);
145 int ag_vmem_start = 0;
147 int cp_ring_start = 0;
148 int nq_ring_start = 0;
150 ag_vmem_start = rx_vmem_start + rx_vmem_len;
151 ag_vmem_len = rx_ring_info ? RTE_CACHE_LINE_ROUNDUP(
152 rx_ring_info->ag_ring_struct->vmem_size) : 0;
153 cp_ring_start = ag_vmem_start + ag_vmem_len;
154 cp_ring_start = RTE_ALIGN(cp_ring_start, 4096);
156 int cp_ring_len = RTE_CACHE_LINE_ROUNDUP(cp_ring->ring_size *
157 sizeof(struct cmpl_base));
158 cp_ring_len = RTE_ALIGN(cp_ring_len, 128);
159 nq_ring_start = cp_ring_start + cp_ring_len;
160 nq_ring_start = RTE_ALIGN(nq_ring_start, 4096);
162 int nq_ring_len = BNXT_CHIP_THOR(bp) ? cp_ring_len : 0;
164 int tx_ring_start = nq_ring_start + nq_ring_len;
165 tx_ring_start = RTE_ALIGN(tx_ring_start, 4096);
166 int tx_ring_len = tx_ring_info ?
167 RTE_CACHE_LINE_ROUNDUP(tx_ring_info->tx_ring_struct->ring_size *
168 sizeof(struct tx_bd_long)) : 0;
169 tx_ring_len = RTE_ALIGN(tx_ring_len, 4096);
171 int rx_ring_start = tx_ring_start + tx_ring_len;
172 rx_ring_start = RTE_ALIGN(rx_ring_start, 4096);
173 int rx_ring_len = rx_ring_info ?
174 RTE_CACHE_LINE_ROUNDUP(rx_ring_info->rx_ring_struct->ring_size *
175 sizeof(struct rx_prod_pkt_bd)) : 0;
176 rx_ring_len = RTE_ALIGN(rx_ring_len, 4096);
178 int ag_ring_start = rx_ring_start + rx_ring_len;
179 ag_ring_start = RTE_ALIGN(ag_ring_start, 4096);
180 int ag_ring_len = rx_ring_len * AGG_RING_SIZE_FACTOR;
181 ag_ring_len = RTE_ALIGN(ag_ring_len, 4096);
183 int ag_bitmap_start = ag_ring_start + ag_ring_len;
184 int ag_bitmap_len = rx_ring_info ?
185 RTE_CACHE_LINE_ROUNDUP(rte_bitmap_get_memory_footprint(
186 rx_ring_info->rx_ring_struct->ring_size *
187 AGG_RING_SIZE_FACTOR)) : 0;
189 int tpa_info_start = ag_bitmap_start + ag_bitmap_len;
190 int tpa_info_len = rx_ring_info ?
191 RTE_CACHE_LINE_ROUNDUP(BNXT_TPA_MAX *
192 sizeof(struct bnxt_tpa_info)) : 0;
194 int total_alloc_len = tpa_info_start;
195 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
196 total_alloc_len += tpa_info_len;
198 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
199 "bnxt_%04x:%02x:%02x:%02x-%04x_%s", pdev->addr.domain,
200 pdev->addr.bus, pdev->addr.devid, pdev->addr.function, qidx,
202 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
203 mz = rte_memzone_lookup(mz_name);
205 mz = rte_memzone_reserve_aligned(mz_name, total_alloc_len,
208 RTE_MEMZONE_SIZE_HINT_ONLY |
209 RTE_MEMZONE_IOVA_CONTIG,
214 memset(mz->addr, 0, mz->len);
215 mz_phys_addr_base = mz->iova;
216 mz_phys_addr = mz->iova;
217 if ((unsigned long)mz->addr == mz_phys_addr_base) {
219 "Memzone physical address same as virtual.\n");
220 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
221 for (sz = 0; sz < total_alloc_len; sz += getpagesize())
222 rte_mem_lock_page(((char *)mz->addr) + sz);
223 mz_phys_addr_base = rte_mem_virt2iova(mz->addr);
224 mz_phys_addr = rte_mem_virt2iova(mz->addr);
225 if (mz_phys_addr == RTE_BAD_IOVA) {
227 "unable to map ring address to physical memory\n");
234 tx_ring = tx_ring_info->tx_ring_struct;
236 tx_ring->bd = ((char *)mz->addr + tx_ring_start);
237 tx_ring_info->tx_desc_ring = (struct tx_bd_long *)tx_ring->bd;
238 tx_ring->bd_dma = mz_phys_addr + tx_ring_start;
239 tx_ring_info->tx_desc_mapping = tx_ring->bd_dma;
240 tx_ring->mem_zone = (const void *)mz;
244 if (tx_ring->vmem_size) {
246 (void **)((char *)mz->addr + tx_vmem_start);
247 tx_ring_info->tx_buf_ring =
248 (struct bnxt_sw_tx_bd *)tx_ring->vmem;
254 rx_ring = rx_ring_info->rx_ring_struct;
256 rx_ring->bd = ((char *)mz->addr + rx_ring_start);
257 rx_ring_info->rx_desc_ring =
258 (struct rx_prod_pkt_bd *)rx_ring->bd;
259 rx_ring->bd_dma = mz_phys_addr + rx_ring_start;
260 rx_ring_info->rx_desc_mapping = rx_ring->bd_dma;
261 rx_ring->mem_zone = (const void *)mz;
265 if (rx_ring->vmem_size) {
267 (void **)((char *)mz->addr + rx_vmem_start);
268 rx_ring_info->rx_buf_ring =
269 (struct bnxt_sw_rx_bd *)rx_ring->vmem;
272 rx_ring = rx_ring_info->ag_ring_struct;
274 rx_ring->bd = ((char *)mz->addr + ag_ring_start);
275 rx_ring_info->ag_desc_ring =
276 (struct rx_prod_pkt_bd *)rx_ring->bd;
277 rx_ring->bd_dma = mz->iova + ag_ring_start;
278 rx_ring_info->ag_desc_mapping = rx_ring->bd_dma;
279 rx_ring->mem_zone = (const void *)mz;
283 if (rx_ring->vmem_size) {
285 (void **)((char *)mz->addr + ag_vmem_start);
286 rx_ring_info->ag_buf_ring =
287 (struct bnxt_sw_rx_bd *)rx_ring->vmem;
290 rx_ring_info->ag_bitmap =
291 rte_bitmap_init(rx_ring_info->rx_ring_struct->ring_size *
292 AGG_RING_SIZE_FACTOR, (uint8_t *)mz->addr +
293 ag_bitmap_start, ag_bitmap_len);
296 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
297 rx_ring_info->tpa_info =
298 ((struct bnxt_tpa_info *)((char *)mz->addr +
302 cp_ring->bd = ((char *)mz->addr + cp_ring_start);
303 cp_ring->bd_dma = mz_phys_addr + cp_ring_start;
304 cp_ring_info->cp_desc_ring = cp_ring->bd;
305 cp_ring_info->cp_desc_mapping = cp_ring->bd_dma;
306 cp_ring->mem_zone = (const void *)mz;
310 if (cp_ring->vmem_size)
311 *cp_ring->vmem = ((char *)mz->addr + stats_len);
313 cp_ring_info->hw_stats = mz->addr;
314 cp_ring_info->hw_stats_map = mz_phys_addr;
316 cp_ring_info->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
319 struct bnxt_ring *nq_ring = nq_ring_info->cp_ring_struct;
321 nq_ring->bd = (char *)mz->addr + nq_ring_start;
322 nq_ring->bd_dma = mz_phys_addr + nq_ring_start;
323 nq_ring_info->cp_desc_ring = nq_ring->bd;
324 nq_ring_info->cp_desc_mapping = nq_ring->bd_dma;
325 nq_ring->mem_zone = (const void *)mz;
329 if (nq_ring->vmem_size)
330 *nq_ring->vmem = (char *)mz->addr + nq_vmem_start;
332 nq_ring_info->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
338 static void bnxt_init_dflt_coal(struct bnxt_coal *coal)
340 /* Tick values in micro seconds.
341 * 1 coal_buf x bufs_per_record = 1 completion record.
343 coal->num_cmpl_aggr_int = BNXT_NUM_CMPL_AGGR_INT;
344 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
345 coal->num_cmpl_dma_aggr = BNXT_NUM_CMPL_DMA_AGGR;
346 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
347 coal->num_cmpl_dma_aggr_during_int = BNXT_NUM_CMPL_DMA_AGGR_DURING_INT;
348 coal->int_lat_tmr_max = BNXT_INT_LAT_TMR_MAX;
349 /* min timer set to 1/2 of interrupt timer */
350 coal->int_lat_tmr_min = BNXT_INT_LAT_TMR_MIN;
351 /* buf timer set to 1/4 of interrupt timer */
352 coal->cmpl_aggr_dma_tmr = BNXT_CMPL_AGGR_DMA_TMR;
353 coal->cmpl_aggr_dma_tmr_during_int = BNXT_CMPL_AGGR_DMA_TMR_DURING_INT;
356 static void bnxt_set_db(struct bnxt *bp,
357 struct bnxt_db_info *db,
362 if (BNXT_CHIP_THOR(bp)) {
364 db->doorbell = (char *)bp->doorbell_base + 0x10000;
366 db->doorbell = (char *)bp->doorbell_base + 0x4000;
368 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
369 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
371 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
372 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
373 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
375 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
376 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_CQ;
378 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
379 db->db_key64 = DBR_PATH_L2;
382 db->db_key64 |= (uint64_t)fid << DBR_XID_SFT;
385 db->doorbell = (char *)bp->doorbell_base + map_idx * 0x80;
387 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
388 db->db_key32 = DB_KEY_TX;
390 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
391 db->db_key32 = DB_KEY_RX;
393 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
394 db->db_key32 = DB_KEY_CP;
401 static int bnxt_alloc_cmpl_ring(struct bnxt *bp, int queue_index,
402 struct bnxt_cp_ring_info *cpr,
403 struct bnxt_cp_ring_info *nqr)
405 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
406 uint32_t nq_ring_id = HWRM_NA_SIGNATURE;
407 int cp_ring_index = queue_index + BNXT_NUM_ASYNC_CPR(bp);
411 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL;
413 if (BNXT_HAS_NQ(bp)) {
415 nq_ring_id = nqr->cp_ring_struct->fw_ring_id;
417 PMD_DRV_LOG(ERR, "NQ ring is NULL\n");
422 rc = bnxt_hwrm_ring_alloc(bp, cp_ring, ring_type, cp_ring_index,
423 HWRM_NA_SIGNATURE, nq_ring_id);
428 bnxt_set_db(bp, &cpr->cp_db, ring_type, cp_ring_index,
429 cp_ring->fw_ring_id);
435 static int bnxt_alloc_nq_ring(struct bnxt *bp, int queue_index,
436 struct bnxt_cp_ring_info *nqr)
438 struct bnxt_ring *nq_ring = nqr->cp_ring_struct;
439 int nq_ring_index = queue_index + BNXT_NUM_ASYNC_CPR(bp);
443 if (!BNXT_HAS_NQ(bp))
446 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ;
448 rc = bnxt_hwrm_ring_alloc(bp, nq_ring, ring_type, nq_ring_index,
449 HWRM_NA_SIGNATURE, HWRM_NA_SIGNATURE);
453 bnxt_set_db(bp, &nqr->cp_db, ring_type, nq_ring_index,
454 nq_ring->fw_ring_id);
460 static int bnxt_alloc_rx_ring(struct bnxt *bp, int queue_index)
462 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
463 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
464 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
465 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
466 struct bnxt_ring *ring = rxr->rx_ring_struct;
470 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_RX;
472 rc = bnxt_hwrm_ring_alloc(bp, ring, ring_type,
473 queue_index, cpr->hw_stats_ctx_id,
474 cp_ring->fw_ring_id);
479 if (BNXT_HAS_RING_GRPS(bp))
480 bp->grp_info[queue_index].rx_fw_ring_id = ring->fw_ring_id;
481 bnxt_set_db(bp, &rxr->rx_db, ring_type, queue_index, ring->fw_ring_id);
482 bnxt_db_write(&rxr->rx_db, rxr->rx_prod);
487 static int bnxt_alloc_rx_agg_ring(struct bnxt *bp, int queue_index)
489 unsigned int map_idx = queue_index + bp->rx_cp_nr_rings;
490 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
491 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
492 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
493 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
494 struct bnxt_ring *ring = rxr->ag_ring_struct;
495 uint32_t hw_stats_ctx_id = HWRM_NA_SIGNATURE;
499 ring->fw_rx_ring_id = rxr->rx_ring_struct->fw_ring_id;
501 if (BNXT_CHIP_THOR(bp)) {
502 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG;
503 hw_stats_ctx_id = cpr->hw_stats_ctx_id;
505 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_RX;
508 rc = bnxt_hwrm_ring_alloc(bp, ring, ring_type, map_idx,
509 hw_stats_ctx_id, cp_ring->fw_ring_id);
515 if (BNXT_HAS_RING_GRPS(bp))
516 bp->grp_info[queue_index].ag_fw_ring_id = ring->fw_ring_id;
517 bnxt_set_db(bp, &rxr->ag_db, ring_type, map_idx, ring->fw_ring_id);
518 bnxt_db_write(&rxr->ag_db, rxr->ag_prod);
523 int bnxt_alloc_hwrm_rx_ring(struct bnxt *bp, int queue_index)
525 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
526 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
527 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
528 struct bnxt_cp_ring_info *nqr = rxq->nq_ring;
529 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
532 if (BNXT_HAS_NQ(bp)) {
533 rc = bnxt_alloc_nq_ring(bp, queue_index, nqr);
538 rc = bnxt_alloc_cmpl_ring(bp, queue_index, cpr, nqr);
542 if (BNXT_HAS_RING_GRPS(bp)) {
543 bp->grp_info[queue_index].fw_stats_ctx = cpr->hw_stats_ctx_id;
544 bp->grp_info[queue_index].cp_fw_ring_id = cp_ring->fw_ring_id;
547 if (!BNXT_NUM_ASYNC_CPR(bp) && !queue_index) {
549 * If a dedicated async event completion ring is not enabled,
550 * use the first completion ring from PF or VF as the default
551 * completion ring for async event handling.
553 bp->async_cp_ring = cpr;
554 rc = bnxt_hwrm_set_async_event_cr(bp);
559 rc = bnxt_alloc_rx_ring(bp, queue_index);
563 rc = bnxt_alloc_rx_agg_ring(bp, queue_index);
567 if (rxq->rx_started) {
568 if (bnxt_init_one_rx_ring(rxq)) {
570 "bnxt_init_one_rx_ring failed!\n");
571 bnxt_rx_queue_release_op(rxq);
575 bnxt_db_write(&rxr->rx_db, rxr->rx_prod);
576 bnxt_db_write(&rxr->ag_db, rxr->ag_prod);
578 rxq->index = queue_index;
584 "Failed to allocate receive queue %d, rc %d.\n",
589 /* Initialise all rings to -1, its used to free rings later if allocation
590 * of few rings fails.
592 static void bnxt_init_all_rings(struct bnxt *bp)
595 struct bnxt_rx_queue *rxq;
596 struct bnxt_ring *cp_ring;
597 struct bnxt_ring *ring;
598 struct bnxt_rx_ring_info *rxr;
599 struct bnxt_tx_queue *txq;
601 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
602 rxq = bp->rx_queues[i];
604 cp_ring = rxq->cp_ring->cp_ring_struct;
605 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
608 ring = rxr->rx_ring_struct;
609 ring->fw_ring_id = INVALID_HW_RING_ID;
611 ring = rxr->ag_ring_struct;
612 ring->fw_ring_id = INVALID_HW_RING_ID;
614 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
615 txq = bp->tx_queues[i];
617 cp_ring = txq->cp_ring->cp_ring_struct;
618 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
620 ring = txq->tx_ring->tx_ring_struct;
621 ring->fw_ring_id = INVALID_HW_RING_ID;
626 * [0] = default completion ring
627 * [1 -> +rx_cp_nr_rings] = rx_cp, rx rings
628 * [1+rx_cp_nr_rings + 1 -> +tx_cp_nr_rings] = tx_cp, tx rings
630 int bnxt_alloc_hwrm_rings(struct bnxt *bp)
632 struct bnxt_coal coal;
637 bnxt_init_dflt_coal(&coal);
638 bnxt_init_all_rings(bp);
640 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
641 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
642 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
643 struct bnxt_cp_ring_info *nqr = rxq->nq_ring;
644 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
645 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
647 if (BNXT_HAS_NQ(bp)) {
648 if (bnxt_alloc_nq_ring(bp, i, nqr))
652 if (bnxt_alloc_cmpl_ring(bp, i, cpr, nqr))
655 if (BNXT_HAS_RING_GRPS(bp)) {
656 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
657 bp->grp_info[i].cp_fw_ring_id = cp_ring->fw_ring_id;
660 bnxt_hwrm_set_ring_coal(bp, &coal, cp_ring->fw_ring_id);
661 if (!BNXT_NUM_ASYNC_CPR(bp) && !i) {
663 * If a dedicated async event completion ring is not
664 * enabled, use the first completion ring as the default
665 * completion ring for async event handling.
667 bp->async_cp_ring = cpr;
668 rc = bnxt_hwrm_set_async_event_cr(bp);
673 if (bnxt_alloc_rx_ring(bp, i))
676 if (bnxt_alloc_rx_agg_ring(bp, i))
679 if (bnxt_init_one_rx_ring(rxq)) {
680 PMD_DRV_LOG(ERR, "bnxt_init_one_rx_ring failed!\n");
681 bnxt_rx_queue_release_op(rxq);
684 bnxt_db_write(&rxr->rx_db, rxr->rx_prod);
685 bnxt_db_write(&rxr->ag_db, rxr->ag_prod);
688 bnxt_rxq_vec_setup(rxq);
692 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
693 struct bnxt_tx_queue *txq = bp->tx_queues[i];
694 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
695 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
696 struct bnxt_cp_ring_info *nqr = txq->nq_ring;
697 struct bnxt_tx_ring_info *txr = txq->tx_ring;
698 struct bnxt_ring *ring = txr->tx_ring_struct;
699 unsigned int idx = i + bp->rx_cp_nr_rings;
701 if (BNXT_HAS_NQ(bp)) {
702 if (bnxt_alloc_nq_ring(bp, idx, nqr))
706 if (bnxt_alloc_cmpl_ring(bp, idx, cpr, nqr))
710 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_TX;
711 rc = bnxt_hwrm_ring_alloc(bp, ring,
713 i, cpr->hw_stats_ctx_id,
714 cp_ring->fw_ring_id);
718 bnxt_set_db(bp, &txr->tx_db, ring_type, i, ring->fw_ring_id);
720 bnxt_hwrm_set_ring_coal(bp, &coal, cp_ring->fw_ring_id);
727 /* Allocate dedicated async completion ring. */
728 int bnxt_alloc_async_cp_ring(struct bnxt *bp)
730 struct bnxt_cp_ring_info *cpr = bp->async_cp_ring;
731 struct bnxt_ring *cp_ring;
735 if (BNXT_NUM_ASYNC_CPR(bp) == 0 || cpr == NULL)
738 cp_ring = cpr->cp_ring_struct;
741 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ;
743 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL;
745 rc = bnxt_hwrm_ring_alloc(bp, cp_ring, ring_type, 0,
746 HWRM_NA_SIGNATURE, HWRM_NA_SIGNATURE);
753 bnxt_set_db(bp, &cpr->cp_db, ring_type, 0,
754 cp_ring->fw_ring_id);
761 return bnxt_hwrm_set_async_event_cr(bp);
764 /* Free dedicated async completion ring. */
765 void bnxt_free_async_cp_ring(struct bnxt *bp)
767 struct bnxt_cp_ring_info *cpr = bp->async_cp_ring;
769 if (BNXT_NUM_ASYNC_CPR(bp) == 0 || cpr == NULL)
773 bnxt_free_nq_ring(bp, cpr);
775 bnxt_free_cp_ring(bp, cpr);
777 bnxt_free_ring(cpr->cp_ring_struct);
778 rte_free(cpr->cp_ring_struct);
779 cpr->cp_ring_struct = NULL;
781 bp->async_cp_ring = NULL;
784 int bnxt_alloc_async_ring_struct(struct bnxt *bp)
786 struct bnxt_cp_ring_info *cpr = NULL;
787 struct bnxt_ring *ring = NULL;
788 unsigned int socket_id;
790 if (BNXT_NUM_ASYNC_CPR(bp) == 0)
793 socket_id = rte_lcore_to_socket_id(rte_get_master_lcore());
795 cpr = rte_zmalloc_socket("cpr",
796 sizeof(struct bnxt_cp_ring_info),
797 RTE_CACHE_LINE_SIZE, socket_id);
801 ring = rte_zmalloc_socket("bnxt_cp_ring_struct",
802 sizeof(struct bnxt_ring),
803 RTE_CACHE_LINE_SIZE, socket_id);
809 ring->bd = (void *)cpr->cp_desc_ring;
810 ring->bd_dma = cpr->cp_desc_mapping;
811 ring->ring_size = rte_align32pow2(DEFAULT_CP_RING_SIZE);
812 ring->ring_mask = ring->ring_size - 1;
816 bp->async_cp_ring = cpr;
817 cpr->cp_ring_struct = ring;
819 return bnxt_alloc_rings(bp, 0, NULL, NULL,
820 bp->async_cp_ring, NULL,