1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
9 #include <rte_bitmap.h>
10 #include <rte_byteorder.h>
11 #include <rte_malloc.h>
12 #include <rte_memory.h>
15 #include "bnxt_ring.h"
18 #include "hsi_struct_def_dpdk.h"
19 #ifdef RTE_LIBRTE_IEEE1588
20 #include "bnxt_hwrm.h"
23 #include <bnxt_tf_common.h>
24 #include <ulp_mark_mgr.h>
30 static inline struct rte_mbuf *__bnxt_alloc_rx_data(struct rte_mempool *mb)
32 struct rte_mbuf *data;
34 data = rte_mbuf_raw_alloc(mb);
39 static inline int bnxt_alloc_rx_data(struct bnxt_rx_queue *rxq,
40 struct bnxt_rx_ring_info *rxr,
43 struct rx_prod_pkt_bd *rxbd = &rxr->rx_desc_ring[prod];
44 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
45 struct rte_mbuf *mbuf;
47 mbuf = __bnxt_alloc_rx_data(rxq->mb_pool);
49 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
54 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
56 rxbd->address = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
61 static inline int bnxt_alloc_ag_data(struct bnxt_rx_queue *rxq,
62 struct bnxt_rx_ring_info *rxr,
65 struct rx_prod_pkt_bd *rxbd = &rxr->ag_desc_ring[prod];
66 struct bnxt_sw_rx_bd *rx_buf = &rxr->ag_buf_ring[prod];
67 struct rte_mbuf *mbuf;
70 PMD_DRV_LOG(ERR, "Jumbo Frame. rxbd is NULL\n");
75 PMD_DRV_LOG(ERR, "Jumbo Frame. rx_buf is NULL\n");
79 mbuf = __bnxt_alloc_rx_data(rxq->mb_pool);
81 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
86 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
88 rxbd->address = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
93 static inline void bnxt_reuse_rx_mbuf(struct bnxt_rx_ring_info *rxr,
94 struct rte_mbuf *mbuf)
96 uint16_t prod = RING_NEXT(rxr->rx_ring_struct, rxr->rx_prod);
97 struct bnxt_sw_rx_bd *prod_rx_buf;
98 struct rx_prod_pkt_bd *prod_bd;
100 prod_rx_buf = &rxr->rx_buf_ring[prod];
102 RTE_ASSERT(prod_rx_buf->mbuf == NULL);
103 RTE_ASSERT(mbuf != NULL);
105 prod_rx_buf->mbuf = mbuf;
107 prod_bd = &rxr->rx_desc_ring[prod];
109 prod_bd->address = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
115 struct rte_mbuf *bnxt_consume_rx_buf(struct bnxt_rx_ring_info *rxr,
118 struct bnxt_sw_rx_bd *cons_rx_buf;
119 struct rte_mbuf *mbuf;
121 cons_rx_buf = &rxr->rx_buf_ring[cons];
122 RTE_ASSERT(cons_rx_buf->mbuf != NULL);
123 mbuf = cons_rx_buf->mbuf;
124 cons_rx_buf->mbuf = NULL;
128 static void bnxt_tpa_start(struct bnxt_rx_queue *rxq,
129 struct rx_tpa_start_cmpl *tpa_start,
130 struct rx_tpa_start_cmpl_hi *tpa_start1)
132 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
135 struct bnxt_tpa_info *tpa_info;
136 struct rte_mbuf *mbuf;
138 agg_id = bnxt_tpa_start_agg_id(rxq->bp, tpa_start);
140 data_cons = tpa_start->opaque;
141 tpa_info = &rxr->tpa_info[agg_id];
143 mbuf = bnxt_consume_rx_buf(rxr, data_cons);
145 bnxt_reuse_rx_mbuf(rxr, tpa_info->mbuf);
147 tpa_info->agg_count = 0;
148 tpa_info->mbuf = mbuf;
149 tpa_info->len = rte_le_to_cpu_32(tpa_start->len);
153 mbuf->pkt_len = rte_le_to_cpu_32(tpa_start->len);
154 mbuf->data_len = mbuf->pkt_len;
155 mbuf->port = rxq->port_id;
156 mbuf->ol_flags = PKT_RX_LRO;
157 if (likely(tpa_start->flags_type &
158 rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS_RSS_VALID))) {
159 mbuf->hash.rss = rte_le_to_cpu_32(tpa_start->rss_hash);
160 mbuf->ol_flags |= PKT_RX_RSS_HASH;
162 mbuf->hash.fdir.id = rte_le_to_cpu_16(tpa_start1->cfa_code);
163 mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
165 if (tpa_start1->flags2 &
166 rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN)) {
167 mbuf->vlan_tci = rte_le_to_cpu_32(tpa_start1->metadata);
168 mbuf->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
170 if (likely(tpa_start1->flags2 &
171 rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC)))
172 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
174 /* recycle next mbuf */
175 data_cons = RING_NEXT(rxr->rx_ring_struct, data_cons);
176 bnxt_reuse_rx_mbuf(rxr, bnxt_consume_rx_buf(rxr, data_cons));
179 static int bnxt_agg_bufs_valid(struct bnxt_cp_ring_info *cpr,
180 uint8_t agg_bufs, uint32_t raw_cp_cons)
182 uint16_t last_cp_cons;
183 struct rx_pkt_cmpl *agg_cmpl;
185 raw_cp_cons = ADV_RAW_CMP(raw_cp_cons, agg_bufs);
186 last_cp_cons = RING_CMP(cpr->cp_ring_struct, raw_cp_cons);
187 agg_cmpl = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[last_cp_cons];
188 cpr->valid = FLIP_VALID(raw_cp_cons,
189 cpr->cp_ring_struct->ring_mask,
191 return CMP_VALID(agg_cmpl, raw_cp_cons, cpr->cp_ring_struct);
194 /* TPA consume agg buffer out of order, allocate connected data only */
195 static int bnxt_prod_ag_mbuf(struct bnxt_rx_queue *rxq)
197 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
198 uint16_t next = RING_NEXT(rxr->ag_ring_struct, rxr->ag_prod);
200 /* TODO batch allocation for better performance */
201 while (rte_bitmap_get(rxr->ag_bitmap, next)) {
202 if (unlikely(bnxt_alloc_ag_data(rxq, rxr, next))) {
204 "agg mbuf alloc failed: prod=0x%x\n", next);
207 rte_bitmap_clear(rxr->ag_bitmap, next);
209 next = RING_NEXT(rxr->ag_ring_struct, next);
215 static int bnxt_rx_pages(struct bnxt_rx_queue *rxq,
216 struct rte_mbuf *mbuf, uint32_t *tmp_raw_cons,
217 uint8_t agg_buf, struct bnxt_tpa_info *tpa_info)
219 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
220 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
222 uint16_t cp_cons, ag_cons;
223 struct rx_pkt_cmpl *rxcmp;
224 struct rte_mbuf *last = mbuf;
225 bool is_thor_tpa = tpa_info && BNXT_CHIP_THOR(rxq->bp);
227 for (i = 0; i < agg_buf; i++) {
228 struct bnxt_sw_rx_bd *ag_buf;
229 struct rte_mbuf *ag_mbuf;
232 rxcmp = (void *)&tpa_info->agg_arr[i];
234 *tmp_raw_cons = NEXT_RAW_CMP(*tmp_raw_cons);
235 cp_cons = RING_CMP(cpr->cp_ring_struct, *tmp_raw_cons);
236 rxcmp = (struct rx_pkt_cmpl *)
237 &cpr->cp_desc_ring[cp_cons];
241 bnxt_dump_cmpl(cp_cons, rxcmp);
244 ag_cons = rxcmp->opaque;
245 RTE_ASSERT(ag_cons <= rxr->ag_ring_struct->ring_mask);
246 ag_buf = &rxr->ag_buf_ring[ag_cons];
247 ag_mbuf = ag_buf->mbuf;
248 RTE_ASSERT(ag_mbuf != NULL);
250 ag_mbuf->data_len = rte_le_to_cpu_16(rxcmp->len);
253 mbuf->pkt_len += ag_mbuf->data_len;
255 last->next = ag_mbuf;
261 * As aggregation buffer consumed out of order in TPA module,
262 * use bitmap to track freed slots to be allocated and notified
265 rte_bitmap_set(rxr->ag_bitmap, ag_cons);
267 bnxt_prod_ag_mbuf(rxq);
271 static inline struct rte_mbuf *bnxt_tpa_end(
272 struct bnxt_rx_queue *rxq,
273 uint32_t *raw_cp_cons,
274 struct rx_tpa_end_cmpl *tpa_end,
275 struct rx_tpa_end_cmpl_hi *tpa_end1)
277 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
278 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
280 struct rte_mbuf *mbuf;
282 uint8_t payload_offset;
283 struct bnxt_tpa_info *tpa_info;
285 if (BNXT_CHIP_THOR(rxq->bp)) {
286 struct rx_tpa_v2_end_cmpl *th_tpa_end;
287 struct rx_tpa_v2_end_cmpl_hi *th_tpa_end1;
289 th_tpa_end = (void *)tpa_end;
290 th_tpa_end1 = (void *)tpa_end1;
291 agg_id = BNXT_TPA_END_AGG_ID_TH(th_tpa_end);
292 agg_bufs = BNXT_TPA_END_AGG_BUFS_TH(th_tpa_end1);
293 payload_offset = th_tpa_end1->payload_offset;
295 agg_id = BNXT_TPA_END_AGG_ID(tpa_end);
296 agg_bufs = BNXT_TPA_END_AGG_BUFS(tpa_end);
297 if (!bnxt_agg_bufs_valid(cpr, agg_bufs, *raw_cp_cons))
299 payload_offset = tpa_end->payload_offset;
302 tpa_info = &rxr->tpa_info[agg_id];
303 mbuf = tpa_info->mbuf;
304 RTE_ASSERT(mbuf != NULL);
308 bnxt_rx_pages(rxq, mbuf, raw_cp_cons, agg_bufs, tpa_info);
310 mbuf->l4_len = payload_offset;
312 struct rte_mbuf *new_data = __bnxt_alloc_rx_data(rxq->mb_pool);
313 RTE_ASSERT(new_data != NULL);
315 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
318 tpa_info->mbuf = new_data;
324 bnxt_parse_pkt_type(struct rx_pkt_cmpl *rxcmp, struct rx_pkt_cmpl_hi *rxcmp1)
326 uint32_t l3, pkt_type = 0;
327 uint32_t t_ipcs = 0, ip6 = 0, vlan = 0;
330 vlan = !!(rxcmp1->flags2 &
331 rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN));
332 pkt_type |= vlan ? RTE_PTYPE_L2_ETHER_VLAN : RTE_PTYPE_L2_ETHER;
334 t_ipcs = !!(rxcmp1->flags2 &
335 rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC));
336 ip6 = !!(rxcmp1->flags2 &
337 rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_TYPE));
339 flags_type = rxcmp->flags_type &
340 rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS_ITYPE_MASK);
343 l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
344 else if (!t_ipcs && ip6)
345 l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
346 else if (t_ipcs && !ip6)
347 l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
349 l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
351 switch (flags_type) {
352 case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_ICMP):
354 pkt_type |= l3 | RTE_PTYPE_L4_ICMP;
356 pkt_type |= l3 | RTE_PTYPE_INNER_L4_ICMP;
359 case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_TCP):
361 pkt_type |= l3 | RTE_PTYPE_L4_TCP;
363 pkt_type |= l3 | RTE_PTYPE_INNER_L4_TCP;
366 case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_UDP):
368 pkt_type |= l3 | RTE_PTYPE_L4_UDP;
370 pkt_type |= l3 | RTE_PTYPE_INNER_L4_UDP;
373 case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_IP):
381 #ifdef RTE_LIBRTE_IEEE1588
383 bnxt_get_rx_ts_thor(struct bnxt *bp, uint32_t rx_ts_cmpl)
385 uint64_t systime_cycles = 0;
387 if (!BNXT_CHIP_THOR(bp))
390 /* On Thor, Rx timestamps are provided directly in the
391 * Rx completion records to the driver. Only 32 bits of
392 * the timestamp is present in the completion. Driver needs
393 * to read the current 48 bit free running timer using the
394 * HWRM_PORT_TS_QUERY command and combine the upper 16 bits
395 * from the HWRM response with the lower 32 bits in the
396 * Rx completion to produce the 48 bit timestamp for the Rx packet
398 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
400 bp->ptp_cfg->rx_timestamp = (systime_cycles & 0xFFFF00000000);
401 bp->ptp_cfg->rx_timestamp |= rx_ts_cmpl;
406 bnxt_ulp_set_mark_in_mbuf(struct bnxt *bp, struct rx_pkt_cmpl_hi *rxcmp1,
407 struct rte_mbuf *mbuf)
417 cfa_code = rte_le_to_cpu_16(rxcmp1->cfa_code);
418 flags2 = rte_le_to_cpu_32(rxcmp1->flags2);
419 meta = rte_le_to_cpu_32(rxcmp1->metadata);
422 * The flags field holds extra bits of info from [6:4]
423 * which indicate if the flow is in TCAM or EM or EEM
425 meta_fmt = (flags2 & BNXT_CFA_META_FMT_MASK) >>
426 BNXT_CFA_META_FMT_SHFT;
430 /* Not an LFID or GFID, a flush cmd. */
436 * Assume that EM doesn't support Mark due to GFID
437 * collisions with EEM. Simply return without setting the mark
440 if (BNXT_CFA_META_EM_TEST(meta))
443 * It is a TCAM entry, so it is an LFID. The TCAM IDX and Mode
444 * can also be determined by decoding the meta_data. We are not
445 * using these for now.
450 /* EEM Case, only using gfid in EEM for now. */
454 * For EEM flows, The first part of cfa_code is 16 bits.
455 * The second part is embedded in the
456 * metadata field from bit 19 onwards. The driver needs to
457 * ignore the first 19 bits of metadata and use the next 12
458 * bits as higher 12 bits of cfa_code.
460 meta >>= BNXT_RX_META_CFA_CODE_SHIFT;
461 cfa_code |= meta << BNXT_CFA_CODE_META_SHIFT;
464 /* For other values, the cfa_code is assumed to be an LFID. */
468 rc = ulp_mark_db_mark_get(bp->ulp_ctx, gfid,
471 /* Got the mark, write it to the mbuf and return */
472 mbuf->hash.fdir.hi = mark_id;
473 mbuf->udata64 = (cfa_code & 0xffffffffull) << 32;
474 mbuf->hash.fdir.id = rxcmp1->cfa_code;
475 mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
480 mbuf->hash.fdir.hi = 0;
481 mbuf->hash.fdir.id = 0;
484 void bnxt_set_mark_in_mbuf(struct bnxt *bp,
485 struct rx_pkt_cmpl_hi *rxcmp1,
486 struct rte_mbuf *mbuf)
488 uint32_t cfa_code = 0;
489 uint8_t meta_fmt = 0;
493 cfa_code = rte_le_to_cpu_16(rxcmp1->cfa_code);
497 if (cfa_code && !bp->mark_table[cfa_code].valid)
500 flags2 = rte_le_to_cpu_16(rxcmp1->flags2);
501 meta = rte_le_to_cpu_32(rxcmp1->metadata);
503 meta >>= BNXT_RX_META_CFA_CODE_SHIFT;
505 /* The flags field holds extra bits of info from [6:4]
506 * which indicate if the flow is in TCAM or EM or EEM
508 meta_fmt = (flags2 & BNXT_CFA_META_FMT_MASK) >>
509 BNXT_CFA_META_FMT_SHFT;
511 /* meta_fmt == 4 => 'b100 => 'b10x => EM.
512 * meta_fmt == 5 => 'b101 => 'b10x => EM + VLAN
513 * meta_fmt == 6 => 'b110 => 'b11x => EEM
514 * meta_fmt == 7 => 'b111 => 'b11x => EEM + VLAN.
516 meta_fmt >>= BNXT_CFA_META_FMT_EM_EEM_SHFT;
519 mbuf->hash.fdir.hi = bp->mark_table[cfa_code].mark_id;
520 mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
523 static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
524 struct bnxt_rx_queue *rxq, uint32_t *raw_cons)
526 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
527 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
528 struct rx_pkt_cmpl *rxcmp;
529 struct rx_pkt_cmpl_hi *rxcmp1;
530 uint32_t tmp_raw_cons = *raw_cons;
531 uint16_t cons, prod, cp_cons =
532 RING_CMP(cpr->cp_ring_struct, tmp_raw_cons);
533 struct rte_mbuf *mbuf;
537 uint32_t flags2_f = 0;
539 struct bnxt *bp = rxq->bp;
541 rxcmp = (struct rx_pkt_cmpl *)
542 &cpr->cp_desc_ring[cp_cons];
544 cmp_type = CMP_TYPE(rxcmp);
546 if (cmp_type == RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG) {
547 struct rx_tpa_v2_abuf_cmpl *rx_agg = (void *)rxcmp;
548 uint16_t agg_id = rte_cpu_to_le_16(rx_agg->agg_id);
549 struct bnxt_tpa_info *tpa_info;
551 tpa_info = &rxr->tpa_info[agg_id];
552 RTE_ASSERT(tpa_info->agg_count < 16);
553 tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg;
554 rc = -EINVAL; /* Continue w/o new mbuf */
558 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
559 cp_cons = RING_CMP(cpr->cp_ring_struct, tmp_raw_cons);
560 rxcmp1 = (struct rx_pkt_cmpl_hi *)&cpr->cp_desc_ring[cp_cons];
562 if (!CMP_VALID(rxcmp1, tmp_raw_cons, cpr->cp_ring_struct))
565 cpr->valid = FLIP_VALID(cp_cons,
566 cpr->cp_ring_struct->ring_mask,
569 if (cmp_type == RX_TPA_START_CMPL_TYPE_RX_TPA_START) {
570 bnxt_tpa_start(rxq, (struct rx_tpa_start_cmpl *)rxcmp,
571 (struct rx_tpa_start_cmpl_hi *)rxcmp1);
572 rc = -EINVAL; /* Continue w/o new mbuf */
574 } else if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
575 mbuf = bnxt_tpa_end(rxq, &tmp_raw_cons,
576 (struct rx_tpa_end_cmpl *)rxcmp,
577 (struct rx_tpa_end_cmpl_hi *)rxcmp1);
582 } else if (cmp_type != 0x11) {
587 agg_buf = (rxcmp->agg_bufs_v1 & RX_PKT_CMPL_AGG_BUFS_MASK)
588 >> RX_PKT_CMPL_AGG_BUFS_SFT;
589 if (agg_buf && !bnxt_agg_bufs_valid(cpr, agg_buf, tmp_raw_cons))
594 cons = rxcmp->opaque;
595 mbuf = bnxt_consume_rx_buf(rxr, cons);
601 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
604 mbuf->pkt_len = rxcmp->len;
605 mbuf->data_len = mbuf->pkt_len;
606 mbuf->port = rxq->port_id;
609 flags_type = rte_le_to_cpu_16(rxcmp->flags_type);
610 if (flags_type & RX_PKT_CMPL_FLAGS_RSS_VALID) {
611 mbuf->hash.rss = rxcmp->rss_hash;
612 mbuf->ol_flags |= PKT_RX_RSS_HASH;
615 if (BNXT_TRUFLOW_EN(bp))
616 bnxt_ulp_set_mark_in_mbuf(rxq->bp, rxcmp1, mbuf);
618 bnxt_set_mark_in_mbuf(rxq->bp, rxcmp1, mbuf);
620 #ifdef RTE_LIBRTE_IEEE1588
621 if (unlikely((flags_type & RX_PKT_CMPL_FLAGS_MASK) ==
622 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP)) {
623 mbuf->ol_flags |= PKT_RX_IEEE1588_PTP | PKT_RX_IEEE1588_TMST;
624 bnxt_get_rx_ts_thor(rxq->bp, rxcmp1->reorder);
628 bnxt_rx_pages(rxq, mbuf, &tmp_raw_cons, agg_buf, NULL);
630 if (rxcmp1->flags2 & RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN) {
631 mbuf->vlan_tci = rxcmp1->metadata &
632 (RX_PKT_CMPL_METADATA_VID_MASK |
633 RX_PKT_CMPL_METADATA_DE |
634 RX_PKT_CMPL_METADATA_PRI_MASK);
635 mbuf->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
638 flags2_f = flags2_0xf(rxcmp1);
640 if (likely(IS_IP_NONTUNNEL_PKT(flags2_f))) {
641 if (unlikely(RX_CMP_IP_CS_ERROR(rxcmp1)))
642 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
643 else if (unlikely(RX_CMP_IP_CS_UNKNOWN(rxcmp1)))
644 mbuf->ol_flags |= PKT_RX_IP_CKSUM_UNKNOWN;
646 mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
647 } else if (IS_IP_TUNNEL_PKT(flags2_f)) {
648 if (unlikely(RX_CMP_IP_OUTER_CS_ERROR(rxcmp1) ||
649 RX_CMP_IP_CS_ERROR(rxcmp1)))
650 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
651 else if (unlikely(RX_CMP_IP_CS_UNKNOWN(rxcmp1)))
652 mbuf->ol_flags |= PKT_RX_IP_CKSUM_UNKNOWN;
654 mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
658 if (likely(IS_L4_NONTUNNEL_PKT(flags2_f))) {
659 if (unlikely(RX_CMP_L4_INNER_CS_ERR2(rxcmp1)))
660 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
662 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
663 } else if (IS_L4_TUNNEL_PKT(flags2_f)) {
664 if (unlikely(RX_CMP_L4_INNER_CS_ERR2(rxcmp1)))
665 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
667 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
668 if (unlikely(RX_CMP_L4_OUTER_CS_ERR2(rxcmp1))) {
669 mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
670 } else if (unlikely(IS_L4_TUNNEL_PKT_ONLY_INNER_L4_CS
672 mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_UNKNOWN;
674 mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
676 } else if (unlikely(RX_CMP_L4_CS_UNKNOWN(rxcmp1))) {
677 mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
680 mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);
683 if (rxcmp1->errors_v2 & RX_CMP_L2_ERRORS) {
684 /* Re-install the mbuf back to the rx ring */
685 bnxt_reuse_rx_mbuf(rxr, cons, mbuf);
692 * TODO: Redesign this....
693 * If the allocation fails, the packet does not get received.
694 * Simply returning this will result in slowly falling behind
695 * on the producer ring buffers.
696 * Instead, "filling up" the producer just before ringing the
697 * doorbell could be a better solution since it will let the
698 * producer ring starve until memory is available again pushing
699 * the drops into hardware and getting them out of the driver
700 * allowing recovery to a full producer ring.
702 * This could also help with cache usage by preventing per-packet
703 * calls in favour of a tight loop with the same function being called
706 prod = RING_NEXT(rxr->rx_ring_struct, prod);
707 if (bnxt_alloc_rx_data(rxq, rxr, prod)) {
708 PMD_DRV_LOG(ERR, "mbuf alloc failed with prod=0x%x\n", prod);
714 * All MBUFs are allocated with the same size under DPDK,
715 * no optimization for rx_copy_thresh
722 *raw_cons = tmp_raw_cons;
727 uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
730 struct bnxt_rx_queue *rxq = rx_queue;
731 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
732 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
733 uint32_t raw_cons = cpr->cp_raw_cons;
736 struct rx_pkt_cmpl *rxcmp;
737 uint16_t prod = rxr->rx_prod;
738 uint16_t ag_prod = rxr->ag_prod;
742 if (unlikely(is_bnxt_in_error(rxq->bp)))
745 /* If Rx Q was stopped return */
746 if (unlikely(!rxq->rx_started ||
747 !rte_spinlock_trylock(&rxq->lock)))
750 /* Handle RX burst request */
752 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
753 rte_prefetch0(&cpr->cp_desc_ring[cons]);
754 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
756 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
758 cpr->valid = FLIP_VALID(cons,
759 cpr->cp_ring_struct->ring_mask,
762 /* TODO: Avoid magic numbers... */
763 if ((CMP_TYPE(rxcmp) & 0x30) == 0x10) {
764 rc = bnxt_rx_pkt(&rx_pkts[nb_rx_pkts], rxq, &raw_cons);
765 if (likely(!rc) || rc == -ENOMEM)
767 if (rc == -EBUSY) /* partial completion */
769 } else if (!BNXT_NUM_ASYNC_CPR(rxq->bp)) {
771 bnxt_event_hwrm_resp_handler(rxq->bp,
772 (struct cmpl_base *)rxcmp);
773 /* If the async event is Fatal error, return */
774 if (unlikely(is_bnxt_in_error(rxq->bp)))
778 raw_cons = NEXT_RAW_CMP(raw_cons);
779 if (nb_rx_pkts == nb_pkts || evt)
781 /* Post some Rx buf early in case of larger burst processing */
782 if (nb_rx_pkts == BNXT_RX_POST_THRESH)
783 bnxt_db_write(&rxr->rx_db, rxr->rx_prod);
786 cpr->cp_raw_cons = raw_cons;
787 if (!nb_rx_pkts && !evt) {
789 * For PMD, there is no need to keep on pushing to REARM
790 * the doorbell if there are no new completions
795 if (prod != rxr->rx_prod)
796 bnxt_db_write(&rxr->rx_db, rxr->rx_prod);
798 /* Ring the AGG ring DB */
799 if (ag_prod != rxr->ag_prod)
800 bnxt_db_write(&rxr->ag_db, rxr->ag_prod);
804 /* Attempt to alloc Rx buf in case of a previous allocation failure. */
806 int i = RING_NEXT(rxr->rx_ring_struct, prod);
807 int cnt = nb_rx_pkts;
810 i = RING_NEXT(rxr->rx_ring_struct, i), cnt--) {
811 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[i];
813 /* Buffer already allocated for this index. */
814 if (rx_buf->mbuf != NULL)
817 /* This slot is empty. Alloc buffer for Rx */
818 if (!bnxt_alloc_rx_data(rxq, rxr, i)) {
820 bnxt_db_write(&rxr->rx_db, rxr->rx_prod);
822 PMD_DRV_LOG(ERR, "Alloc mbuf failed\n");
829 rte_spinlock_unlock(&rxq->lock);
835 * Dummy DPDK callback for RX.
837 * This function is used to temporarily replace the real callback during
838 * unsafe control operations on the queue, or in case of error.
841 bnxt_dummy_recv_pkts(void *rx_queue __rte_unused,
842 struct rte_mbuf **rx_pkts __rte_unused,
843 uint16_t nb_pkts __rte_unused)
848 void bnxt_free_rx_rings(struct bnxt *bp)
851 struct bnxt_rx_queue *rxq;
856 for (i = 0; i < (int)bp->rx_nr_rings; i++) {
857 rxq = bp->rx_queues[i];
861 bnxt_free_ring(rxq->rx_ring->rx_ring_struct);
862 rte_free(rxq->rx_ring->rx_ring_struct);
864 /* Free the Aggregator ring */
865 bnxt_free_ring(rxq->rx_ring->ag_ring_struct);
866 rte_free(rxq->rx_ring->ag_ring_struct);
867 rxq->rx_ring->ag_ring_struct = NULL;
869 rte_free(rxq->rx_ring);
871 bnxt_free_ring(rxq->cp_ring->cp_ring_struct);
872 rte_free(rxq->cp_ring->cp_ring_struct);
873 rte_free(rxq->cp_ring);
876 bp->rx_queues[i] = NULL;
880 int bnxt_init_rx_ring_struct(struct bnxt_rx_queue *rxq, unsigned int socket_id)
882 struct bnxt_cp_ring_info *cpr;
883 struct bnxt_rx_ring_info *rxr;
884 struct bnxt_ring *ring;
886 rxq->rx_buf_size = BNXT_MAX_PKT_LEN + sizeof(struct rte_mbuf);
888 rxr = rte_zmalloc_socket("bnxt_rx_ring",
889 sizeof(struct bnxt_rx_ring_info),
890 RTE_CACHE_LINE_SIZE, socket_id);
895 ring = rte_zmalloc_socket("bnxt_rx_ring_struct",
896 sizeof(struct bnxt_ring),
897 RTE_CACHE_LINE_SIZE, socket_id);
900 rxr->rx_ring_struct = ring;
901 ring->ring_size = rte_align32pow2(rxq->nb_rx_desc);
902 ring->ring_mask = ring->ring_size - 1;
903 ring->bd = (void *)rxr->rx_desc_ring;
904 ring->bd_dma = rxr->rx_desc_mapping;
905 ring->vmem_size = ring->ring_size * sizeof(struct bnxt_sw_rx_bd);
906 ring->vmem = (void **)&rxr->rx_buf_ring;
908 cpr = rte_zmalloc_socket("bnxt_rx_ring",
909 sizeof(struct bnxt_cp_ring_info),
910 RTE_CACHE_LINE_SIZE, socket_id);
915 ring = rte_zmalloc_socket("bnxt_rx_ring_struct",
916 sizeof(struct bnxt_ring),
917 RTE_CACHE_LINE_SIZE, socket_id);
920 cpr->cp_ring_struct = ring;
921 ring->ring_size = rte_align32pow2(rxr->rx_ring_struct->ring_size *
922 (2 + AGG_RING_SIZE_FACTOR));
923 ring->ring_mask = ring->ring_size - 1;
924 ring->bd = (void *)cpr->cp_desc_ring;
925 ring->bd_dma = cpr->cp_desc_mapping;
929 /* Allocate Aggregator rings */
930 ring = rte_zmalloc_socket("bnxt_rx_ring_struct",
931 sizeof(struct bnxt_ring),
932 RTE_CACHE_LINE_SIZE, socket_id);
935 rxr->ag_ring_struct = ring;
936 ring->ring_size = rte_align32pow2(rxq->nb_rx_desc *
937 AGG_RING_SIZE_FACTOR);
938 ring->ring_mask = ring->ring_size - 1;
939 ring->bd = (void *)rxr->ag_desc_ring;
940 ring->bd_dma = rxr->ag_desc_mapping;
941 ring->vmem_size = ring->ring_size * sizeof(struct bnxt_sw_rx_bd);
942 ring->vmem = (void **)&rxr->ag_buf_ring;
947 static void bnxt_init_rxbds(struct bnxt_ring *ring, uint32_t type,
951 struct rx_prod_pkt_bd *rx_bd_ring = (struct rx_prod_pkt_bd *)ring->bd;
955 for (j = 0; j < ring->ring_size; j++) {
956 rx_bd_ring[j].flags_type = rte_cpu_to_le_16(type);
957 rx_bd_ring[j].len = rte_cpu_to_le_16(len);
958 rx_bd_ring[j].opaque = j;
962 int bnxt_init_one_rx_ring(struct bnxt_rx_queue *rxq)
964 struct bnxt_rx_ring_info *rxr;
965 struct bnxt_ring *ring;
970 size = rte_pktmbuf_data_room_size(rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
971 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
973 type = RX_PROD_PKT_BD_TYPE_RX_PROD_PKT | RX_PROD_PKT_BD_FLAGS_EOP_PAD;
976 ring = rxr->rx_ring_struct;
977 bnxt_init_rxbds(ring, type, size);
980 for (i = 0; i < ring->ring_size; i++) {
981 if (unlikely(!rxr->rx_buf_ring[i].mbuf)) {
982 if (bnxt_alloc_rx_data(rxq, rxr, prod) != 0) {
984 "init'ed rx ring %d with %d/%d mbufs only\n",
985 rxq->queue_id, i, ring->ring_size);
990 prod = RING_NEXT(rxr->rx_ring_struct, prod);
993 ring = rxr->ag_ring_struct;
994 type = RX_PROD_AGG_BD_TYPE_RX_PROD_AGG;
995 bnxt_init_rxbds(ring, type, size);
998 for (i = 0; i < ring->ring_size; i++) {
999 if (unlikely(!rxr->ag_buf_ring[i].mbuf)) {
1000 if (bnxt_alloc_ag_data(rxq, rxr, prod) != 0) {
1001 PMD_DRV_LOG(WARNING,
1002 "init'ed AG ring %d with %d/%d mbufs only\n",
1003 rxq->queue_id, i, ring->ring_size);
1007 rxr->ag_prod = prod;
1008 prod = RING_NEXT(rxr->ag_ring_struct, prod);
1010 PMD_DRV_LOG(DEBUG, "AGG Done!\n");
1012 if (rxr->tpa_info) {
1013 unsigned int max_aggs = BNXT_TPA_MAX_AGGS(rxq->bp);
1015 for (i = 0; i < max_aggs; i++) {
1016 if (unlikely(!rxr->tpa_info[i].mbuf)) {
1017 rxr->tpa_info[i].mbuf =
1018 __bnxt_alloc_rx_data(rxq->mb_pool);
1019 if (!rxr->tpa_info[i].mbuf) {
1020 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
1026 PMD_DRV_LOG(DEBUG, "TPA alloc Done!\n");