1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
9 #include <rte_bitmap.h>
10 #include <rte_byteorder.h>
11 #include <rte_malloc.h>
12 #include <rte_memory.h>
15 #include "bnxt_reps.h"
16 #include "bnxt_ring.h"
19 #include "hsi_struct_def_dpdk.h"
20 #ifdef RTE_LIBRTE_IEEE1588
21 #include "bnxt_hwrm.h"
24 #include <bnxt_tf_common.h>
25 #include <ulp_mark_mgr.h>
31 static inline struct rte_mbuf *__bnxt_alloc_rx_data(struct rte_mempool *mb)
33 struct rte_mbuf *data;
35 data = rte_mbuf_raw_alloc(mb);
40 static inline int bnxt_alloc_rx_data(struct bnxt_rx_queue *rxq,
41 struct bnxt_rx_ring_info *rxr,
44 uint16_t prod = RING_IDX(rxr->rx_ring_struct, raw_prod);
45 struct rx_prod_pkt_bd *rxbd;
46 struct rte_mbuf **rx_buf;
47 struct rte_mbuf *mbuf;
49 rxbd = &rxr->rx_desc_ring[prod];
50 rx_buf = &rxr->rx_buf_ring[prod];
51 mbuf = __bnxt_alloc_rx_data(rxq->mb_pool);
53 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
58 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
60 rxbd->address = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
65 static inline int bnxt_alloc_ag_data(struct bnxt_rx_queue *rxq,
66 struct bnxt_rx_ring_info *rxr,
69 uint16_t prod = RING_IDX(rxr->ag_ring_struct, raw_prod);
70 struct rx_prod_pkt_bd *rxbd;
71 struct rte_mbuf **rx_buf;
72 struct rte_mbuf *mbuf;
74 rxbd = &rxr->ag_desc_ring[prod];
75 rx_buf = &rxr->ag_buf_ring[prod];
77 PMD_DRV_LOG(ERR, "Jumbo Frame. rxbd is NULL\n");
82 PMD_DRV_LOG(ERR, "Jumbo Frame. rx_buf is NULL\n");
86 mbuf = __bnxt_alloc_rx_data(rxq->mb_pool);
88 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
93 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
95 rxbd->address = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
100 static inline void bnxt_reuse_rx_mbuf(struct bnxt_rx_ring_info *rxr,
101 struct rte_mbuf *mbuf)
103 uint16_t prod, raw_prod = RING_NEXT(rxr->rx_raw_prod);
104 struct rte_mbuf **prod_rx_buf;
105 struct rx_prod_pkt_bd *prod_bd;
107 prod = RING_IDX(rxr->rx_ring_struct, raw_prod);
108 prod_rx_buf = &rxr->rx_buf_ring[prod];
110 RTE_ASSERT(*prod_rx_buf == NULL);
111 RTE_ASSERT(mbuf != NULL);
115 prod_bd = &rxr->rx_desc_ring[prod];
117 prod_bd->address = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
119 rxr->rx_raw_prod = raw_prod;
123 struct rte_mbuf *bnxt_consume_rx_buf(struct bnxt_rx_ring_info *rxr,
126 struct rte_mbuf **cons_rx_buf;
127 struct rte_mbuf *mbuf;
129 cons_rx_buf = &rxr->rx_buf_ring[RING_IDX(rxr->rx_ring_struct, cons)];
130 RTE_ASSERT(*cons_rx_buf != NULL);
137 static void bnxt_tpa_get_metadata(struct bnxt *bp,
138 struct bnxt_tpa_info *tpa_info,
139 struct rx_tpa_start_cmpl *tpa_start,
140 struct rx_tpa_start_cmpl_hi *tpa_start1)
142 tpa_info->cfa_code_valid = 0;
143 tpa_info->vlan_valid = 0;
144 tpa_info->hash_valid = 0;
145 tpa_info->l4_csum_valid = 0;
147 if (likely(tpa_start->flags_type &
148 rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS_RSS_VALID))) {
149 tpa_info->hash_valid = 1;
150 tpa_info->rss_hash = rte_le_to_cpu_32(tpa_start->rss_hash);
153 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
154 struct rx_tpa_start_v2_cmpl *v2_tpa_start = (void *)tpa_start;
155 struct rx_tpa_start_v2_cmpl_hi *v2_tpa_start1 =
158 if (v2_tpa_start->agg_id &
159 RX_TPA_START_V2_CMPL_METADATA1_VALID) {
160 tpa_info->vlan_valid = 1;
162 rte_le_to_cpu_16(v2_tpa_start1->metadata0);
165 if (v2_tpa_start1->flags2 & RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK)
166 tpa_info->l4_csum_valid = 1;
171 tpa_info->cfa_code_valid = 1;
172 tpa_info->cfa_code = rte_le_to_cpu_16(tpa_start1->cfa_code);
173 if (tpa_start1->flags2 &
174 rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN)) {
175 tpa_info->vlan_valid = 1;
176 tpa_info->vlan = rte_le_to_cpu_32(tpa_start1->metadata);
179 if (likely(tpa_start1->flags2 &
180 rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC)))
181 tpa_info->l4_csum_valid = 1;
184 static void bnxt_tpa_start(struct bnxt_rx_queue *rxq,
185 struct rx_tpa_start_cmpl *tpa_start,
186 struct rx_tpa_start_cmpl_hi *tpa_start1)
188 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
191 struct bnxt_tpa_info *tpa_info;
192 struct rte_mbuf *mbuf;
194 agg_id = bnxt_tpa_start_agg_id(rxq->bp, tpa_start);
196 data_cons = tpa_start->opaque;
197 tpa_info = &rxr->tpa_info[agg_id];
199 mbuf = bnxt_consume_rx_buf(rxr, data_cons);
201 bnxt_reuse_rx_mbuf(rxr, tpa_info->mbuf);
203 tpa_info->agg_count = 0;
204 tpa_info->mbuf = mbuf;
205 tpa_info->len = rte_le_to_cpu_32(tpa_start->len);
207 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
210 mbuf->pkt_len = rte_le_to_cpu_32(tpa_start->len);
211 mbuf->data_len = mbuf->pkt_len;
212 mbuf->port = rxq->port_id;
213 mbuf->ol_flags = PKT_RX_LRO;
215 bnxt_tpa_get_metadata(rxq->bp, tpa_info, tpa_start, tpa_start1);
217 if (likely(tpa_info->hash_valid)) {
218 mbuf->hash.rss = tpa_info->rss_hash;
219 mbuf->ol_flags |= PKT_RX_RSS_HASH;
220 } else if (tpa_info->cfa_code_valid) {
221 mbuf->hash.fdir.id = tpa_info->cfa_code;
222 mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
225 if (tpa_info->vlan_valid) {
226 mbuf->vlan_tci = tpa_info->vlan;
227 mbuf->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
230 if (likely(tpa_info->l4_csum_valid))
231 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
233 /* recycle next mbuf */
234 data_cons = RING_NEXT(data_cons);
235 bnxt_reuse_rx_mbuf(rxr, bnxt_consume_rx_buf(rxr, data_cons));
238 static int bnxt_agg_bufs_valid(struct bnxt_cp_ring_info *cpr,
239 uint8_t agg_bufs, uint32_t raw_cp_cons)
241 uint16_t last_cp_cons;
242 struct rx_pkt_cmpl *agg_cmpl;
244 raw_cp_cons = ADV_RAW_CMP(raw_cp_cons, agg_bufs);
245 last_cp_cons = RING_CMP(cpr->cp_ring_struct, raw_cp_cons);
246 agg_cmpl = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[last_cp_cons];
247 cpr->valid = FLIP_VALID(raw_cp_cons,
248 cpr->cp_ring_struct->ring_mask,
250 return CMP_VALID(agg_cmpl, raw_cp_cons, cpr->cp_ring_struct);
253 /* TPA consume agg buffer out of order, allocate connected data only */
254 static int bnxt_prod_ag_mbuf(struct bnxt_rx_queue *rxq)
256 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
257 uint16_t raw_next = RING_NEXT(rxr->ag_raw_prod);
258 uint16_t bmap_next = RING_IDX(rxr->ag_ring_struct, raw_next);
260 /* TODO batch allocation for better performance */
261 while (rte_bitmap_get(rxr->ag_bitmap, bmap_next)) {
262 if (unlikely(bnxt_alloc_ag_data(rxq, rxr, raw_next))) {
263 PMD_DRV_LOG(ERR, "agg mbuf alloc failed: prod=0x%x\n",
267 rte_bitmap_clear(rxr->ag_bitmap, bmap_next);
268 rxr->ag_raw_prod = raw_next;
269 raw_next = RING_NEXT(raw_next);
270 bmap_next = RING_IDX(rxr->ag_ring_struct, raw_next);
276 static int bnxt_rx_pages(struct bnxt_rx_queue *rxq,
277 struct rte_mbuf *mbuf, uint32_t *tmp_raw_cons,
278 uint8_t agg_buf, struct bnxt_tpa_info *tpa_info)
280 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
281 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
283 uint16_t cp_cons, ag_cons;
284 struct rx_pkt_cmpl *rxcmp;
285 struct rte_mbuf *last = mbuf;
286 bool is_p5_tpa = tpa_info && BNXT_CHIP_P5(rxq->bp);
288 for (i = 0; i < agg_buf; i++) {
289 struct rte_mbuf **ag_buf;
290 struct rte_mbuf *ag_mbuf;
293 rxcmp = (void *)&tpa_info->agg_arr[i];
295 *tmp_raw_cons = NEXT_RAW_CMP(*tmp_raw_cons);
296 cp_cons = RING_CMP(cpr->cp_ring_struct, *tmp_raw_cons);
297 rxcmp = (struct rx_pkt_cmpl *)
298 &cpr->cp_desc_ring[cp_cons];
302 bnxt_dump_cmpl(cp_cons, rxcmp);
305 ag_cons = rxcmp->opaque;
306 RTE_ASSERT(ag_cons <= rxr->ag_ring_struct->ring_mask);
307 ag_buf = &rxr->ag_buf_ring[ag_cons];
309 RTE_ASSERT(ag_mbuf != NULL);
311 ag_mbuf->data_len = rte_le_to_cpu_16(rxcmp->len);
314 mbuf->pkt_len += ag_mbuf->data_len;
316 last->next = ag_mbuf;
322 * As aggregation buffer consumed out of order in TPA module,
323 * use bitmap to track freed slots to be allocated and notified
326 rte_bitmap_set(rxr->ag_bitmap, ag_cons);
328 bnxt_prod_ag_mbuf(rxq);
332 static inline struct rte_mbuf *bnxt_tpa_end(
333 struct bnxt_rx_queue *rxq,
334 uint32_t *raw_cp_cons,
335 struct rx_tpa_end_cmpl *tpa_end,
336 struct rx_tpa_end_cmpl_hi *tpa_end1)
338 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
339 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
341 struct rte_mbuf *mbuf;
343 uint8_t payload_offset;
344 struct bnxt_tpa_info *tpa_info;
346 if (BNXT_CHIP_P5(rxq->bp)) {
347 struct rx_tpa_v2_end_cmpl *th_tpa_end;
348 struct rx_tpa_v2_end_cmpl_hi *th_tpa_end1;
350 th_tpa_end = (void *)tpa_end;
351 th_tpa_end1 = (void *)tpa_end1;
352 agg_id = BNXT_TPA_END_AGG_ID_TH(th_tpa_end);
353 agg_bufs = BNXT_TPA_END_AGG_BUFS_TH(th_tpa_end1);
354 payload_offset = th_tpa_end1->payload_offset;
356 agg_id = BNXT_TPA_END_AGG_ID(tpa_end);
357 agg_bufs = BNXT_TPA_END_AGG_BUFS(tpa_end);
358 if (!bnxt_agg_bufs_valid(cpr, agg_bufs, *raw_cp_cons))
360 payload_offset = tpa_end->payload_offset;
363 tpa_info = &rxr->tpa_info[agg_id];
364 mbuf = tpa_info->mbuf;
365 RTE_ASSERT(mbuf != NULL);
368 bnxt_rx_pages(rxq, mbuf, raw_cp_cons, agg_bufs, tpa_info);
370 mbuf->l4_len = payload_offset;
372 struct rte_mbuf *new_data = __bnxt_alloc_rx_data(rxq->mb_pool);
373 RTE_ASSERT(new_data != NULL);
375 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
378 tpa_info->mbuf = new_data;
383 uint32_t bnxt_ptype_table[BNXT_PTYPE_TBL_DIM] __rte_cache_aligned;
385 static void __rte_cold
386 bnxt_init_ptype_table(void)
388 uint32_t *pt = bnxt_ptype_table;
389 static bool initialized;
397 for (i = 0; i < BNXT_PTYPE_TBL_DIM; i++) {
398 if (i & (RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN >> 2))
399 pt[i] = RTE_PTYPE_L2_ETHER_VLAN;
401 pt[i] = RTE_PTYPE_L2_ETHER;
403 ip6 = i & (RX_PKT_CMPL_FLAGS2_IP_TYPE >> 7);
404 tun = i & (RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC >> 2);
405 type = (i & 0x38) << 9;
408 l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
409 else if (!tun && ip6)
410 l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
411 else if (tun && !ip6)
412 l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
414 l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
417 case RX_PKT_CMPL_FLAGS_ITYPE_ICMP:
419 pt[i] |= l3 | RTE_PTYPE_INNER_L4_ICMP;
421 pt[i] |= l3 | RTE_PTYPE_L4_ICMP;
423 case RX_PKT_CMPL_FLAGS_ITYPE_TCP:
425 pt[i] |= l3 | RTE_PTYPE_INNER_L4_TCP;
427 pt[i] |= l3 | RTE_PTYPE_L4_TCP;
429 case RX_PKT_CMPL_FLAGS_ITYPE_UDP:
431 pt[i] |= l3 | RTE_PTYPE_INNER_L4_UDP;
433 pt[i] |= l3 | RTE_PTYPE_L4_UDP;
435 case RX_PKT_CMPL_FLAGS_ITYPE_IP:
444 bnxt_parse_pkt_type(struct rx_pkt_cmpl *rxcmp, struct rx_pkt_cmpl_hi *rxcmp1)
446 uint32_t flags_type, flags2;
449 flags_type = rte_le_to_cpu_16(rxcmp->flags_type);
450 flags2 = rte_le_to_cpu_32(rxcmp1->flags2);
454 * bit 0: RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC
455 * bit 1: RX_CMPL_FLAGS2_IP_TYPE
456 * bit 2: RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN
457 * bits 3-6: RX_PKT_CMPL_FLAGS_ITYPE
459 index = ((flags_type & RX_PKT_CMPL_FLAGS_ITYPE_MASK) >> 9) |
460 ((flags2 & (RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN |
461 RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC)) >> 2) |
462 ((flags2 & RX_PKT_CMPL_FLAGS2_IP_TYPE) >> 7);
464 return bnxt_ptype_table[index];
467 static void __rte_cold
468 bnxt_init_ol_flags_tables(struct bnxt_rx_queue *rxq)
470 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
471 struct rte_eth_conf *dev_conf;
472 bool outer_cksum_enabled;
477 dev_conf = &rxq->bp->eth_dev->data->dev_conf;
478 offloads = dev_conf->rxmode.offloads;
480 outer_cksum_enabled = !!(offloads & (DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
481 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM));
483 /* Initialize ol_flags table. */
484 pt = rxr->ol_flags_table;
485 for (i = 0; i < BNXT_OL_FLAGS_TBL_DIM; i++) {
488 if (i & RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN)
489 pt[i] |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
491 if (i & (RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC << 3)) {
493 if (outer_cksum_enabled) {
494 if (i & RX_PKT_CMPL_FLAGS2_IP_CS_CALC)
495 pt[i] |= PKT_RX_IP_CKSUM_GOOD;
497 if (i & RX_PKT_CMPL_FLAGS2_L4_CS_CALC)
498 pt[i] |= PKT_RX_L4_CKSUM_GOOD;
500 if (i & RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC)
501 pt[i] |= PKT_RX_OUTER_L4_CKSUM_GOOD;
503 if (i & RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC)
504 pt[i] |= PKT_RX_IP_CKSUM_GOOD;
506 if (i & RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC)
507 pt[i] |= PKT_RX_L4_CKSUM_GOOD;
510 /* Non-tunnel case. */
511 if (i & RX_PKT_CMPL_FLAGS2_IP_CS_CALC)
512 pt[i] |= PKT_RX_IP_CKSUM_GOOD;
514 if (i & RX_PKT_CMPL_FLAGS2_L4_CS_CALC)
515 pt[i] |= PKT_RX_L4_CKSUM_GOOD;
519 /* Initialize checksum error table. */
520 pt = rxr->ol_flags_err_table;
521 for (i = 0; i < BNXT_OL_FLAGS_ERR_TBL_DIM; i++) {
524 if (i & (RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC << 2)) {
526 if (outer_cksum_enabled) {
527 if (i & (RX_PKT_CMPL_ERRORS_IP_CS_ERROR >> 4))
528 pt[i] |= PKT_RX_IP_CKSUM_BAD;
530 if (i & (RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR >> 4))
531 pt[i] |= PKT_RX_EIP_CKSUM_BAD;
533 if (i & (RX_PKT_CMPL_ERRORS_L4_CS_ERROR >> 4))
534 pt[i] |= PKT_RX_L4_CKSUM_BAD;
536 if (i & (RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR >> 4))
537 pt[i] |= PKT_RX_OUTER_L4_CKSUM_BAD;
539 if (i & (RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR >> 4))
540 pt[i] |= PKT_RX_IP_CKSUM_BAD;
542 if (i & (RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR >> 4))
543 pt[i] |= PKT_RX_L4_CKSUM_BAD;
546 /* Non-tunnel case. */
547 if (i & (RX_PKT_CMPL_ERRORS_IP_CS_ERROR >> 4))
548 pt[i] |= PKT_RX_IP_CKSUM_BAD;
550 if (i & (RX_PKT_CMPL_ERRORS_L4_CS_ERROR >> 4))
551 pt[i] |= PKT_RX_L4_CKSUM_BAD;
557 bnxt_set_ol_flags(struct bnxt_rx_ring_info *rxr, struct rx_pkt_cmpl *rxcmp,
558 struct rx_pkt_cmpl_hi *rxcmp1, struct rte_mbuf *mbuf)
560 uint16_t flags_type, errors, flags;
563 flags_type = rte_le_to_cpu_16(rxcmp->flags_type);
565 flags = rte_le_to_cpu_32(rxcmp1->flags2) &
566 (RX_PKT_CMPL_FLAGS2_IP_CS_CALC |
567 RX_PKT_CMPL_FLAGS2_L4_CS_CALC |
568 RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC |
569 RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC |
570 RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN);
572 flags |= (flags & RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC) << 3;
573 errors = rte_le_to_cpu_16(rxcmp1->errors_v2) &
574 (RX_PKT_CMPL_ERRORS_IP_CS_ERROR |
575 RX_PKT_CMPL_ERRORS_L4_CS_ERROR |
576 RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR |
577 RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR);
578 errors = (errors >> 4) & flags;
580 ol_flags = rxr->ol_flags_table[flags & ~errors];
582 if (unlikely(errors)) {
583 errors |= (flags & RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC) << 2;
584 ol_flags |= rxr->ol_flags_err_table[errors];
587 if (flags_type & RX_PKT_CMPL_FLAGS_RSS_VALID) {
588 mbuf->hash.rss = rte_le_to_cpu_32(rxcmp->rss_hash);
589 ol_flags |= PKT_RX_RSS_HASH;
592 mbuf->ol_flags = ol_flags;
595 #ifdef RTE_LIBRTE_IEEE1588
597 bnxt_get_rx_ts_p5(struct bnxt *bp, uint32_t rx_ts_cmpl)
599 uint64_t systime_cycles = 0;
601 if (!BNXT_CHIP_P5(bp))
604 /* On Thor, Rx timestamps are provided directly in the
605 * Rx completion records to the driver. Only 32 bits of
606 * the timestamp is present in the completion. Driver needs
607 * to read the current 48 bit free running timer using the
608 * HWRM_PORT_TS_QUERY command and combine the upper 16 bits
609 * from the HWRM response with the lower 32 bits in the
610 * Rx completion to produce the 48 bit timestamp for the Rx packet
612 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
614 bp->ptp_cfg->rx_timestamp = (systime_cycles & 0xFFFF00000000);
615 bp->ptp_cfg->rx_timestamp |= rx_ts_cmpl;
620 bnxt_ulp_set_mark_in_mbuf(struct bnxt *bp, struct rx_pkt_cmpl_hi *rxcmp1,
621 struct rte_mbuf *mbuf, uint32_t *vfr_flag)
629 uint32_t gfid_support = 0;
632 if (BNXT_GFID_ENABLED(bp))
635 cfa_code = rte_le_to_cpu_16(rxcmp1->cfa_code);
636 flags2 = rte_le_to_cpu_32(rxcmp1->flags2);
637 meta = rte_le_to_cpu_32(rxcmp1->metadata);
640 * The flags field holds extra bits of info from [6:4]
641 * which indicate if the flow is in TCAM or EM or EEM
643 meta_fmt = (flags2 & BNXT_CFA_META_FMT_MASK) >>
644 BNXT_CFA_META_FMT_SHFT;
649 /* Not an LFID or GFID, a flush cmd. */
652 /* LFID mode, no vlan scenario */
660 * Assume that EM doesn't support Mark due to GFID
661 * collisions with EEM. Simply return without setting the mark
664 if (BNXT_CFA_META_EM_TEST(meta)) {
665 /*This is EM hit {EM(1), GFID[27:16], 19'd0 or vtag } */
667 meta >>= BNXT_RX_META_CFA_CODE_SHIFT;
668 cfa_code |= meta << BNXT_CFA_CODE_META_SHIFT;
671 * It is a TCAM entry, so it is an LFID.
672 * The TCAM IDX and Mode can also be determined
673 * by decoding the meta_data. We are not
674 * using these for now.
680 /* EEM Case, only using gfid in EEM for now. */
684 * For EEM flows, The first part of cfa_code is 16 bits.
685 * The second part is embedded in the
686 * metadata field from bit 19 onwards. The driver needs to
687 * ignore the first 19 bits of metadata and use the next 12
688 * bits as higher 12 bits of cfa_code.
690 meta >>= BNXT_RX_META_CFA_CODE_SHIFT;
691 cfa_code |= meta << BNXT_CFA_CODE_META_SHIFT;
694 /* For other values, the cfa_code is assumed to be an LFID. */
698 rc = ulp_mark_db_mark_get(bp->ulp_ctx, gfid,
699 cfa_code, vfr_flag, &mark_id);
701 /* VF to VFR Rx path. So, skip mark_id injection in mbuf */
702 if (vfr_flag && *vfr_flag)
704 /* Got the mark, write it to the mbuf and return */
705 mbuf->hash.fdir.hi = mark_id;
706 *bnxt_cfa_code_dynfield(mbuf) = cfa_code & 0xffffffffull;
707 mbuf->hash.fdir.id = rxcmp1->cfa_code;
708 mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
713 mbuf->hash.fdir.hi = 0;
714 mbuf->hash.fdir.id = 0;
719 void bnxt_set_mark_in_mbuf(struct bnxt *bp,
720 struct rx_pkt_cmpl_hi *rxcmp1,
721 struct rte_mbuf *mbuf)
723 uint32_t cfa_code = 0;
724 uint8_t meta_fmt = 0;
728 cfa_code = rte_le_to_cpu_16(rxcmp1->cfa_code);
732 if (cfa_code && !bp->mark_table[cfa_code].valid)
735 flags2 = rte_le_to_cpu_16(rxcmp1->flags2);
736 meta = rte_le_to_cpu_32(rxcmp1->metadata);
738 meta >>= BNXT_RX_META_CFA_CODE_SHIFT;
740 /* The flags field holds extra bits of info from [6:4]
741 * which indicate if the flow is in TCAM or EM or EEM
743 meta_fmt = (flags2 & BNXT_CFA_META_FMT_MASK) >>
744 BNXT_CFA_META_FMT_SHFT;
746 /* meta_fmt == 4 => 'b100 => 'b10x => EM.
747 * meta_fmt == 5 => 'b101 => 'b10x => EM + VLAN
748 * meta_fmt == 6 => 'b110 => 'b11x => EEM
749 * meta_fmt == 7 => 'b111 => 'b11x => EEM + VLAN.
751 meta_fmt >>= BNXT_CFA_META_FMT_EM_EEM_SHFT;
754 mbuf->hash.fdir.hi = bp->mark_table[cfa_code].mark_id;
755 mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
758 static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
759 struct bnxt_rx_queue *rxq, uint32_t *raw_cons)
761 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
762 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
763 struct rx_pkt_cmpl *rxcmp;
764 struct rx_pkt_cmpl_hi *rxcmp1;
765 uint32_t tmp_raw_cons = *raw_cons;
766 uint16_t cons, raw_prod, cp_cons =
767 RING_CMP(cpr->cp_ring_struct, tmp_raw_cons);
768 struct rte_mbuf *mbuf;
772 uint32_t vfr_flag = 0, mark_id = 0;
773 struct bnxt *bp = rxq->bp;
775 rxcmp = (struct rx_pkt_cmpl *)
776 &cpr->cp_desc_ring[cp_cons];
778 cmp_type = CMP_TYPE(rxcmp);
780 if (cmp_type == RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG) {
781 struct rx_tpa_v2_abuf_cmpl *rx_agg = (void *)rxcmp;
782 uint16_t agg_id = rte_cpu_to_le_16(rx_agg->agg_id);
783 struct bnxt_tpa_info *tpa_info;
785 tpa_info = &rxr->tpa_info[agg_id];
786 RTE_ASSERT(tpa_info->agg_count < 16);
787 tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg;
788 rc = -EINVAL; /* Continue w/o new mbuf */
792 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
793 cp_cons = RING_CMP(cpr->cp_ring_struct, tmp_raw_cons);
794 rxcmp1 = (struct rx_pkt_cmpl_hi *)&cpr->cp_desc_ring[cp_cons];
796 if (!CMP_VALID(rxcmp1, tmp_raw_cons, cpr->cp_ring_struct))
799 cpr->valid = FLIP_VALID(cp_cons,
800 cpr->cp_ring_struct->ring_mask,
803 if (cmp_type == RX_TPA_START_CMPL_TYPE_RX_TPA_START ||
804 cmp_type == RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2) {
805 bnxt_tpa_start(rxq, (struct rx_tpa_start_cmpl *)rxcmp,
806 (struct rx_tpa_start_cmpl_hi *)rxcmp1);
807 rc = -EINVAL; /* Continue w/o new mbuf */
809 } else if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
810 mbuf = bnxt_tpa_end(rxq, &tmp_raw_cons,
811 (struct rx_tpa_end_cmpl *)rxcmp,
812 (struct rx_tpa_end_cmpl_hi *)rxcmp1);
817 } else if ((cmp_type != CMPL_BASE_TYPE_RX_L2) &&
818 (cmp_type != CMPL_BASE_TYPE_RX_L2_V2)) {
823 agg_buf = (rxcmp->agg_bufs_v1 & RX_PKT_CMPL_AGG_BUFS_MASK)
824 >> RX_PKT_CMPL_AGG_BUFS_SFT;
825 if (agg_buf && !bnxt_agg_bufs_valid(cpr, agg_buf, tmp_raw_cons))
828 raw_prod = rxr->rx_raw_prod;
830 cons = rxcmp->opaque;
831 mbuf = bnxt_consume_rx_buf(rxr, cons);
835 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
838 mbuf->pkt_len = rxcmp->len;
839 mbuf->data_len = mbuf->pkt_len;
840 mbuf->port = rxq->port_id;
842 #ifdef RTE_LIBRTE_IEEE1588
843 if (unlikely((rte_le_to_cpu_16(rxcmp->flags_type) &
844 RX_PKT_CMPL_FLAGS_MASK) ==
845 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP)) {
846 mbuf->ol_flags |= PKT_RX_IEEE1588_PTP | PKT_RX_IEEE1588_TMST;
847 bnxt_get_rx_ts_p5(rxq->bp, rxcmp1->reorder);
851 if (cmp_type == CMPL_BASE_TYPE_RX_L2_V2) {
852 bnxt_parse_csum_v2(mbuf, rxcmp1);
853 bnxt_parse_pkt_type_v2(mbuf, rxcmp, rxcmp1);
854 bnxt_rx_vlan_v2(mbuf, rxcmp, rxcmp1);
855 /* TODO Add support for cfa_code parsing */
859 bnxt_set_ol_flags(rxr, rxcmp, rxcmp1, mbuf);
861 mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);
863 if (BNXT_TRUFLOW_EN(bp))
864 mark_id = bnxt_ulp_set_mark_in_mbuf(rxq->bp, rxcmp1, mbuf,
867 bnxt_set_mark_in_mbuf(rxq->bp, rxcmp1, mbuf);
871 bnxt_rx_pages(rxq, mbuf, &tmp_raw_cons, agg_buf, NULL);
874 if (rxcmp1->errors_v2 & RX_CMP_L2_ERRORS) {
875 /* Re-install the mbuf back to the rx ring */
876 bnxt_reuse_rx_mbuf(rxr, cons, mbuf);
883 * TODO: Redesign this....
884 * If the allocation fails, the packet does not get received.
885 * Simply returning this will result in slowly falling behind
886 * on the producer ring buffers.
887 * Instead, "filling up" the producer just before ringing the
888 * doorbell could be a better solution since it will let the
889 * producer ring starve until memory is available again pushing
890 * the drops into hardware and getting them out of the driver
891 * allowing recovery to a full producer ring.
893 * This could also help with cache usage by preventing per-packet
894 * calls in favour of a tight loop with the same function being called
897 raw_prod = RING_NEXT(raw_prod);
898 if (bnxt_alloc_rx_data(rxq, rxr, raw_prod)) {
899 PMD_DRV_LOG(ERR, "mbuf alloc failed with prod=0x%x\n",
904 rxr->rx_raw_prod = raw_prod;
906 if (BNXT_TRUFLOW_EN(bp) && (BNXT_VF_IS_TRUSTED(bp) || BNXT_PF(bp)) &&
908 bnxt_vfr_recv(mark_id, rxq->queue_id, mbuf);
909 /* Now return an error so that nb_rx_pkts is not
911 * This packet was meant to be given to the representor.
912 * So no need to account the packet and give it to
913 * parent Rx burst function.
919 * All MBUFs are allocated with the same size under DPDK,
920 * no optimization for rx_copy_thresh
927 *raw_cons = tmp_raw_cons;
932 uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
935 struct bnxt_rx_queue *rxq = rx_queue;
936 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
937 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
938 uint16_t rx_raw_prod = rxr->rx_raw_prod;
939 uint16_t ag_raw_prod = rxr->ag_raw_prod;
940 uint32_t raw_cons = cpr->cp_raw_cons;
941 bool alloc_failed = false;
944 int nb_rep_rx_pkts = 0;
945 struct rx_pkt_cmpl *rxcmp;
949 if (unlikely(is_bnxt_in_error(rxq->bp)))
952 /* If Rx Q was stopped return */
953 if (unlikely(!rxq->rx_started))
956 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
958 * Replenish buffers if needed when a transition has been made from
959 * vector- to non-vector- receive processing.
961 while (unlikely(rxq->rxrearm_nb)) {
962 if (!bnxt_alloc_rx_data(rxq, rxr, rxq->rxrearm_start)) {
963 rxr->rx_raw_prod = rxq->rxrearm_start;
964 bnxt_db_write(&rxr->rx_db, rxr->rx_raw_prod);
965 rxq->rxrearm_start++;
968 /* Retry allocation on next call. */
974 /* Handle RX burst request */
976 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
977 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
979 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
981 cpr->valid = FLIP_VALID(cons,
982 cpr->cp_ring_struct->ring_mask,
985 if ((CMP_TYPE(rxcmp) >= CMPL_BASE_TYPE_RX_TPA_START_V2) &&
986 (CMP_TYPE(rxcmp) <= RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG)) {
987 rc = bnxt_rx_pkt(&rx_pkts[nb_rx_pkts], rxq, &raw_cons);
990 else if (rc == -EBUSY) /* partial completion */
992 else if (rc == -ENODEV) /* completion for representor */
994 else if (rc == -ENOMEM) {
998 } else if (!BNXT_NUM_ASYNC_CPR(rxq->bp)) {
1000 bnxt_event_hwrm_resp_handler(rxq->bp,
1001 (struct cmpl_base *)rxcmp);
1002 /* If the async event is Fatal error, return */
1003 if (unlikely(is_bnxt_in_error(rxq->bp)))
1007 raw_cons = NEXT_RAW_CMP(raw_cons);
1008 if (nb_rx_pkts == nb_pkts || nb_rep_rx_pkts == nb_pkts || evt)
1010 /* Post some Rx buf early in case of larger burst processing */
1011 if (nb_rx_pkts == BNXT_RX_POST_THRESH)
1012 bnxt_db_write(&rxr->rx_db, rxr->rx_raw_prod);
1015 cpr->cp_raw_cons = raw_cons;
1016 if (!nb_rx_pkts && !nb_rep_rx_pkts && !evt) {
1018 * For PMD, there is no need to keep on pushing to REARM
1019 * the doorbell if there are no new completions
1024 /* Ring the completion queue doorbell. */
1027 /* Ring the receive descriptor doorbell. */
1028 if (rx_raw_prod != rxr->rx_raw_prod)
1029 bnxt_db_write(&rxr->rx_db, rxr->rx_raw_prod);
1031 /* Ring the AGG ring DB */
1032 if (ag_raw_prod != rxr->ag_raw_prod)
1033 bnxt_db_write(&rxr->ag_db, rxr->ag_raw_prod);
1035 /* Attempt to alloc Rx buf in case of a previous allocation failure. */
1039 rx_raw_prod = RING_NEXT(rx_raw_prod);
1040 for (cnt = 0; cnt < nb_rx_pkts + nb_rep_rx_pkts; cnt++) {
1041 struct rte_mbuf **rx_buf;
1044 ndx = RING_IDX(rxr->rx_ring_struct, rx_raw_prod + cnt);
1045 rx_buf = &rxr->rx_buf_ring[ndx];
1047 /* Buffer already allocated for this index. */
1048 if (*rx_buf != NULL && *rx_buf != &rxq->fake_mbuf)
1051 /* This slot is empty. Alloc buffer for Rx */
1052 if (!bnxt_alloc_rx_data(rxq, rxr, rx_raw_prod + cnt)) {
1053 rxr->rx_raw_prod = rx_raw_prod + cnt;
1054 bnxt_db_write(&rxr->rx_db, rxr->rx_raw_prod);
1056 PMD_DRV_LOG(ERR, "Alloc mbuf failed\n");
1067 * Dummy DPDK callback for RX.
1069 * This function is used to temporarily replace the real callback during
1070 * unsafe control operations on the queue, or in case of error.
1073 bnxt_dummy_recv_pkts(void *rx_queue __rte_unused,
1074 struct rte_mbuf **rx_pkts __rte_unused,
1075 uint16_t nb_pkts __rte_unused)
1080 void bnxt_free_rx_rings(struct bnxt *bp)
1083 struct bnxt_rx_queue *rxq;
1088 for (i = 0; i < (int)bp->rx_nr_rings; i++) {
1089 rxq = bp->rx_queues[i];
1093 bnxt_free_ring(rxq->rx_ring->rx_ring_struct);
1094 rte_free(rxq->rx_ring->rx_ring_struct);
1096 /* Free the Aggregator ring */
1097 bnxt_free_ring(rxq->rx_ring->ag_ring_struct);
1098 rte_free(rxq->rx_ring->ag_ring_struct);
1099 rxq->rx_ring->ag_ring_struct = NULL;
1101 rte_free(rxq->rx_ring);
1103 bnxt_free_ring(rxq->cp_ring->cp_ring_struct);
1104 rte_free(rxq->cp_ring->cp_ring_struct);
1105 rte_free(rxq->cp_ring);
1108 bp->rx_queues[i] = NULL;
1112 int bnxt_init_rx_ring_struct(struct bnxt_rx_queue *rxq, unsigned int socket_id)
1114 struct rte_eth_dev *eth_dev = rxq->bp->eth_dev;
1115 struct rte_eth_rxmode *rxmode;
1116 struct bnxt_cp_ring_info *cpr;
1117 struct bnxt_rx_ring_info *rxr;
1118 struct bnxt_ring *ring;
1121 rxq->rx_buf_size = BNXT_MAX_PKT_LEN + sizeof(struct rte_mbuf);
1123 rxr = rte_zmalloc_socket("bnxt_rx_ring",
1124 sizeof(struct bnxt_rx_ring_info),
1125 RTE_CACHE_LINE_SIZE, socket_id);
1130 ring = rte_zmalloc_socket("bnxt_rx_ring_struct",
1131 sizeof(struct bnxt_ring),
1132 RTE_CACHE_LINE_SIZE, socket_id);
1135 rxr->rx_ring_struct = ring;
1136 ring->ring_size = rte_align32pow2(rxq->nb_rx_desc);
1137 ring->ring_mask = ring->ring_size - 1;
1138 ring->bd = (void *)rxr->rx_desc_ring;
1139 ring->bd_dma = rxr->rx_desc_mapping;
1141 /* Allocate extra rx ring entries for vector rx. */
1142 ring->vmem_size = sizeof(struct rte_mbuf *) *
1143 (ring->ring_size + RTE_BNXT_DESCS_PER_LOOP);
1145 ring->vmem = (void **)&rxr->rx_buf_ring;
1146 ring->fw_ring_id = INVALID_HW_RING_ID;
1148 cpr = rte_zmalloc_socket("bnxt_rx_ring",
1149 sizeof(struct bnxt_cp_ring_info),
1150 RTE_CACHE_LINE_SIZE, socket_id);
1155 ring = rte_zmalloc_socket("bnxt_rx_ring_struct",
1156 sizeof(struct bnxt_ring),
1157 RTE_CACHE_LINE_SIZE, socket_id);
1160 cpr->cp_ring_struct = ring;
1162 rxmode = ð_dev->data->dev_conf.rxmode;
1163 use_agg_ring = (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) ||
1164 (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) ||
1165 (rxmode->max_rx_pkt_len >
1166 (uint32_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1167 RTE_PKTMBUF_HEADROOM));
1169 /* Allocate two completion slots per entry in desc ring. */
1170 ring->ring_size = rxr->rx_ring_struct->ring_size * 2;
1172 /* Allocate additional slots if aggregation ring is in use. */
1174 ring->ring_size *= AGG_RING_SIZE_FACTOR;
1176 ring->ring_size = rte_align32pow2(ring->ring_size);
1177 ring->ring_mask = ring->ring_size - 1;
1178 ring->bd = (void *)cpr->cp_desc_ring;
1179 ring->bd_dma = cpr->cp_desc_mapping;
1180 ring->vmem_size = 0;
1182 ring->fw_ring_id = INVALID_HW_RING_ID;
1184 /* Allocate Aggregator rings */
1185 ring = rte_zmalloc_socket("bnxt_rx_ring_struct",
1186 sizeof(struct bnxt_ring),
1187 RTE_CACHE_LINE_SIZE, socket_id);
1190 rxr->ag_ring_struct = ring;
1191 ring->ring_size = rte_align32pow2(rxq->nb_rx_desc *
1192 AGG_RING_SIZE_FACTOR);
1193 ring->ring_mask = ring->ring_size - 1;
1194 ring->bd = (void *)rxr->ag_desc_ring;
1195 ring->bd_dma = rxr->ag_desc_mapping;
1196 ring->vmem_size = ring->ring_size * sizeof(struct rte_mbuf *);
1197 ring->vmem = (void **)&rxr->ag_buf_ring;
1198 ring->fw_ring_id = INVALID_HW_RING_ID;
1203 static void bnxt_init_rxbds(struct bnxt_ring *ring, uint32_t type,
1207 struct rx_prod_pkt_bd *rx_bd_ring = (struct rx_prod_pkt_bd *)ring->bd;
1211 for (j = 0; j < ring->ring_size; j++) {
1212 rx_bd_ring[j].flags_type = rte_cpu_to_le_16(type);
1213 rx_bd_ring[j].len = rte_cpu_to_le_16(len);
1214 rx_bd_ring[j].opaque = j;
1218 int bnxt_init_one_rx_ring(struct bnxt_rx_queue *rxq)
1220 struct bnxt_rx_ring_info *rxr;
1221 struct bnxt_ring *ring;
1222 uint32_t raw_prod, type;
1226 /* Initialize packet type table. */
1227 bnxt_init_ptype_table();
1229 size = rte_pktmbuf_data_room_size(rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
1230 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
1232 type = RX_PROD_PKT_BD_TYPE_RX_PROD_PKT;
1235 ring = rxr->rx_ring_struct;
1236 bnxt_init_rxbds(ring, type, size);
1238 /* Initialize offload flags parsing table. */
1239 bnxt_init_ol_flags_tables(rxq);
1241 raw_prod = rxr->rx_raw_prod;
1242 for (i = 0; i < ring->ring_size; i++) {
1243 if (unlikely(!rxr->rx_buf_ring[i])) {
1244 if (bnxt_alloc_rx_data(rxq, rxr, raw_prod) != 0) {
1245 PMD_DRV_LOG(WARNING,
1246 "init'ed rx ring %d with %d/%d mbufs only\n",
1247 rxq->queue_id, i, ring->ring_size);
1251 rxr->rx_raw_prod = raw_prod;
1252 raw_prod = RING_NEXT(raw_prod);
1255 /* Initialize dummy mbuf pointers for vector mode rx. */
1256 for (i = ring->ring_size;
1257 i < ring->ring_size + RTE_BNXT_DESCS_PER_LOOP; i++) {
1258 rxr->rx_buf_ring[i] = &rxq->fake_mbuf;
1261 ring = rxr->ag_ring_struct;
1262 type = RX_PROD_AGG_BD_TYPE_RX_PROD_AGG;
1263 bnxt_init_rxbds(ring, type, size);
1264 raw_prod = rxr->ag_raw_prod;
1266 for (i = 0; i < ring->ring_size; i++) {
1267 if (unlikely(!rxr->ag_buf_ring[i])) {
1268 if (bnxt_alloc_ag_data(rxq, rxr, raw_prod) != 0) {
1269 PMD_DRV_LOG(WARNING,
1270 "init'ed AG ring %d with %d/%d mbufs only\n",
1271 rxq->queue_id, i, ring->ring_size);
1275 rxr->ag_raw_prod = raw_prod;
1276 raw_prod = RING_NEXT(raw_prod);
1278 PMD_DRV_LOG(DEBUG, "AGG Done!\n");
1280 if (rxr->tpa_info) {
1281 unsigned int max_aggs = BNXT_TPA_MAX_AGGS(rxq->bp);
1283 for (i = 0; i < max_aggs; i++) {
1284 if (unlikely(!rxr->tpa_info[i].mbuf)) {
1285 rxr->tpa_info[i].mbuf =
1286 __bnxt_alloc_rx_data(rxq->mb_pool);
1287 if (!rxr->tpa_info[i].mbuf) {
1288 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
1294 PMD_DRV_LOG(DEBUG, "TPA alloc Done!\n");