1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
9 #include <rte_bitmap.h>
10 #include <rte_byteorder.h>
11 #include <rte_malloc.h>
12 #include <rte_memory.h>
15 #include "bnxt_ring.h"
18 #include "hsi_struct_def_dpdk.h"
19 #ifdef RTE_LIBRTE_IEEE1588
20 #include "bnxt_hwrm.h"
27 static inline struct rte_mbuf *__bnxt_alloc_rx_data(struct rte_mempool *mb)
29 struct rte_mbuf *data;
31 data = rte_mbuf_raw_alloc(mb);
36 static inline int bnxt_alloc_rx_data(struct bnxt_rx_queue *rxq,
37 struct bnxt_rx_ring_info *rxr,
40 struct rx_prod_pkt_bd *rxbd = &rxr->rx_desc_ring[prod];
41 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
42 struct rte_mbuf *mbuf;
44 mbuf = __bnxt_alloc_rx_data(rxq->mb_pool);
46 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
51 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
53 rxbd->address = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
58 static inline int bnxt_alloc_ag_data(struct bnxt_rx_queue *rxq,
59 struct bnxt_rx_ring_info *rxr,
62 struct rx_prod_pkt_bd *rxbd = &rxr->ag_desc_ring[prod];
63 struct bnxt_sw_rx_bd *rx_buf = &rxr->ag_buf_ring[prod];
64 struct rte_mbuf *mbuf;
66 mbuf = __bnxt_alloc_rx_data(rxq->mb_pool);
68 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
73 PMD_DRV_LOG(ERR, "Jumbo Frame. rxbd is NULL\n");
75 PMD_DRV_LOG(ERR, "Jumbo Frame. rx_buf is NULL\n");
79 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
81 rxbd->address = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
86 static inline void bnxt_reuse_rx_mbuf(struct bnxt_rx_ring_info *rxr,
87 struct rte_mbuf *mbuf)
89 uint16_t prod = RING_NEXT(rxr->rx_ring_struct, rxr->rx_prod);
90 struct bnxt_sw_rx_bd *prod_rx_buf;
91 struct rx_prod_pkt_bd *prod_bd;
93 prod_rx_buf = &rxr->rx_buf_ring[prod];
95 RTE_ASSERT(prod_rx_buf->mbuf == NULL);
96 RTE_ASSERT(mbuf != NULL);
98 prod_rx_buf->mbuf = mbuf;
100 prod_bd = &rxr->rx_desc_ring[prod];
102 prod_bd->address = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
108 struct rte_mbuf *bnxt_consume_rx_buf(struct bnxt_rx_ring_info *rxr,
111 struct bnxt_sw_rx_bd *cons_rx_buf;
112 struct rte_mbuf *mbuf;
114 cons_rx_buf = &rxr->rx_buf_ring[cons];
115 RTE_ASSERT(cons_rx_buf->mbuf != NULL);
116 mbuf = cons_rx_buf->mbuf;
117 cons_rx_buf->mbuf = NULL;
121 static void bnxt_tpa_start(struct bnxt_rx_queue *rxq,
122 struct rx_tpa_start_cmpl *tpa_start,
123 struct rx_tpa_start_cmpl_hi *tpa_start1)
125 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
128 struct bnxt_tpa_info *tpa_info;
129 struct rte_mbuf *mbuf;
131 agg_id = bnxt_tpa_start_agg_id(rxq->bp, tpa_start);
133 data_cons = tpa_start->opaque;
134 tpa_info = &rxr->tpa_info[agg_id];
136 mbuf = bnxt_consume_rx_buf(rxr, data_cons);
138 bnxt_reuse_rx_mbuf(rxr, tpa_info->mbuf);
140 tpa_info->agg_count = 0;
141 tpa_info->mbuf = mbuf;
142 tpa_info->len = rte_le_to_cpu_32(tpa_start->len);
146 mbuf->pkt_len = rte_le_to_cpu_32(tpa_start->len);
147 mbuf->data_len = mbuf->pkt_len;
148 mbuf->port = rxq->port_id;
149 mbuf->ol_flags = PKT_RX_LRO;
150 if (likely(tpa_start->flags_type &
151 rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS_RSS_VALID))) {
152 mbuf->hash.rss = rte_le_to_cpu_32(tpa_start->rss_hash);
153 mbuf->ol_flags |= PKT_RX_RSS_HASH;
155 mbuf->hash.fdir.id = rte_le_to_cpu_16(tpa_start1->cfa_code);
156 mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
158 if (tpa_start1->flags2 &
159 rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN)) {
160 mbuf->vlan_tci = rte_le_to_cpu_32(tpa_start1->metadata);
161 mbuf->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
163 if (likely(tpa_start1->flags2 &
164 rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC)))
165 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
167 /* recycle next mbuf */
168 data_cons = RING_NEXT(rxr->rx_ring_struct, data_cons);
169 bnxt_reuse_rx_mbuf(rxr, bnxt_consume_rx_buf(rxr, data_cons));
172 static int bnxt_agg_bufs_valid(struct bnxt_cp_ring_info *cpr,
173 uint8_t agg_bufs, uint32_t raw_cp_cons)
175 uint16_t last_cp_cons;
176 struct rx_pkt_cmpl *agg_cmpl;
178 raw_cp_cons = ADV_RAW_CMP(raw_cp_cons, agg_bufs);
179 last_cp_cons = RING_CMP(cpr->cp_ring_struct, raw_cp_cons);
180 agg_cmpl = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[last_cp_cons];
181 cpr->valid = FLIP_VALID(raw_cp_cons,
182 cpr->cp_ring_struct->ring_mask,
184 return CMP_VALID(agg_cmpl, raw_cp_cons, cpr->cp_ring_struct);
187 /* TPA consume agg buffer out of order, allocate connected data only */
188 static int bnxt_prod_ag_mbuf(struct bnxt_rx_queue *rxq)
190 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
191 uint16_t next = RING_NEXT(rxr->ag_ring_struct, rxr->ag_prod);
193 /* TODO batch allocation for better performance */
194 while (rte_bitmap_get(rxr->ag_bitmap, next)) {
195 if (unlikely(bnxt_alloc_ag_data(rxq, rxr, next))) {
197 "agg mbuf alloc failed: prod=0x%x\n", next);
200 rte_bitmap_clear(rxr->ag_bitmap, next);
202 next = RING_NEXT(rxr->ag_ring_struct, next);
208 static int bnxt_rx_pages(struct bnxt_rx_queue *rxq,
209 struct rte_mbuf *mbuf, uint32_t *tmp_raw_cons,
210 uint8_t agg_buf, struct bnxt_tpa_info *tpa_info)
212 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
213 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
215 uint16_t cp_cons, ag_cons;
216 struct rx_pkt_cmpl *rxcmp;
217 struct rte_mbuf *last = mbuf;
218 bool is_thor_tpa = tpa_info && BNXT_CHIP_THOR(rxq->bp);
220 for (i = 0; i < agg_buf; i++) {
221 struct bnxt_sw_rx_bd *ag_buf;
222 struct rte_mbuf *ag_mbuf;
225 rxcmp = (void *)&tpa_info->agg_arr[i];
227 *tmp_raw_cons = NEXT_RAW_CMP(*tmp_raw_cons);
228 cp_cons = RING_CMP(cpr->cp_ring_struct, *tmp_raw_cons);
229 rxcmp = (struct rx_pkt_cmpl *)
230 &cpr->cp_desc_ring[cp_cons];
234 bnxt_dump_cmpl(cp_cons, rxcmp);
237 ag_cons = rxcmp->opaque;
238 RTE_ASSERT(ag_cons <= rxr->ag_ring_struct->ring_mask);
239 ag_buf = &rxr->ag_buf_ring[ag_cons];
240 ag_mbuf = ag_buf->mbuf;
241 RTE_ASSERT(ag_mbuf != NULL);
243 ag_mbuf->data_len = rte_le_to_cpu_16(rxcmp->len);
246 mbuf->pkt_len += ag_mbuf->data_len;
248 last->next = ag_mbuf;
254 * As aggregation buffer consumed out of order in TPA module,
255 * use bitmap to track freed slots to be allocated and notified
258 rte_bitmap_set(rxr->ag_bitmap, ag_cons);
260 bnxt_prod_ag_mbuf(rxq);
264 static inline struct rte_mbuf *bnxt_tpa_end(
265 struct bnxt_rx_queue *rxq,
266 uint32_t *raw_cp_cons,
267 struct rx_tpa_end_cmpl *tpa_end,
268 struct rx_tpa_end_cmpl_hi *tpa_end1)
270 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
271 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
273 struct rte_mbuf *mbuf;
275 uint8_t payload_offset;
276 struct bnxt_tpa_info *tpa_info;
278 if (BNXT_CHIP_THOR(rxq->bp)) {
279 struct rx_tpa_v2_end_cmpl *th_tpa_end;
280 struct rx_tpa_v2_end_cmpl_hi *th_tpa_end1;
282 th_tpa_end = (void *)tpa_end;
283 th_tpa_end1 = (void *)tpa_end1;
284 agg_id = BNXT_TPA_END_AGG_ID_TH(th_tpa_end);
285 agg_bufs = BNXT_TPA_END_AGG_BUFS_TH(th_tpa_end1);
286 payload_offset = th_tpa_end1->payload_offset;
288 agg_id = BNXT_TPA_END_AGG_ID(tpa_end);
289 agg_bufs = BNXT_TPA_END_AGG_BUFS(tpa_end);
290 if (!bnxt_agg_bufs_valid(cpr, agg_bufs, *raw_cp_cons))
292 payload_offset = tpa_end->payload_offset;
295 tpa_info = &rxr->tpa_info[agg_id];
296 mbuf = tpa_info->mbuf;
297 RTE_ASSERT(mbuf != NULL);
301 bnxt_rx_pages(rxq, mbuf, raw_cp_cons, agg_bufs, tpa_info);
303 mbuf->l4_len = payload_offset;
305 struct rte_mbuf *new_data = __bnxt_alloc_rx_data(rxq->mb_pool);
306 RTE_ASSERT(new_data != NULL);
308 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
311 tpa_info->mbuf = new_data;
317 bnxt_parse_pkt_type(struct rx_pkt_cmpl *rxcmp, struct rx_pkt_cmpl_hi *rxcmp1)
319 uint32_t l3, pkt_type = 0;
320 uint32_t t_ipcs = 0, ip6 = 0, vlan = 0;
323 vlan = !!(rxcmp1->flags2 &
324 rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN));
325 pkt_type |= vlan ? RTE_PTYPE_L2_ETHER_VLAN : RTE_PTYPE_L2_ETHER;
327 t_ipcs = !!(rxcmp1->flags2 &
328 rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC));
329 ip6 = !!(rxcmp1->flags2 &
330 rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_TYPE));
332 flags_type = rxcmp->flags_type &
333 rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS_ITYPE_MASK);
336 l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
337 else if (!t_ipcs && ip6)
338 l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
339 else if (t_ipcs && !ip6)
340 l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
342 l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
344 switch (flags_type) {
345 case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_ICMP):
347 pkt_type |= l3 | RTE_PTYPE_L4_ICMP;
349 pkt_type |= l3 | RTE_PTYPE_INNER_L4_ICMP;
352 case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_TCP):
354 pkt_type |= l3 | RTE_PTYPE_L4_TCP;
356 pkt_type |= l3 | RTE_PTYPE_INNER_L4_TCP;
359 case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_UDP):
361 pkt_type |= l3 | RTE_PTYPE_L4_UDP;
363 pkt_type |= l3 | RTE_PTYPE_INNER_L4_UDP;
366 case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_IP):
374 #ifdef RTE_LIBRTE_IEEE1588
376 bnxt_get_rx_ts_thor(struct bnxt *bp, uint32_t rx_ts_cmpl)
378 uint64_t systime_cycles = 0;
380 if (!BNXT_CHIP_THOR(bp))
383 /* On Thor, Rx timestamps are provided directly in the
384 * Rx completion records to the driver. Only 32 bits of
385 * the timestamp is present in the completion. Driver needs
386 * to read the current 48 bit free running timer using the
387 * HWRM_PORT_TS_QUERY command and combine the upper 16 bits
388 * from the HWRM response with the lower 32 bits in the
389 * Rx completion to produce the 48 bit timestamp for the Rx packet
391 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
393 bp->ptp_cfg->rx_timestamp = (systime_cycles & 0xFFFF00000000);
394 bp->ptp_cfg->rx_timestamp |= rx_ts_cmpl;
398 static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
399 struct bnxt_rx_queue *rxq, uint32_t *raw_cons)
401 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
402 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
403 struct rx_pkt_cmpl *rxcmp;
404 struct rx_pkt_cmpl_hi *rxcmp1;
405 uint32_t tmp_raw_cons = *raw_cons;
406 uint16_t cons, prod, cp_cons =
407 RING_CMP(cpr->cp_ring_struct, tmp_raw_cons);
408 struct rte_mbuf *mbuf;
412 uint32_t flags2_f = 0;
415 rxcmp = (struct rx_pkt_cmpl *)
416 &cpr->cp_desc_ring[cp_cons];
418 cmp_type = CMP_TYPE(rxcmp);
420 if (cmp_type == RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG) {
421 struct rx_tpa_v2_abuf_cmpl *rx_agg = (void *)rxcmp;
422 uint16_t agg_id = rte_cpu_to_le_16(rx_agg->agg_id);
423 struct bnxt_tpa_info *tpa_info;
425 tpa_info = &rxr->tpa_info[agg_id];
426 RTE_ASSERT(tpa_info->agg_count < 16);
427 tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg;
428 rc = -EINVAL; /* Continue w/o new mbuf */
432 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
433 cp_cons = RING_CMP(cpr->cp_ring_struct, tmp_raw_cons);
434 rxcmp1 = (struct rx_pkt_cmpl_hi *)&cpr->cp_desc_ring[cp_cons];
436 if (!CMP_VALID(rxcmp1, tmp_raw_cons, cpr->cp_ring_struct))
439 cpr->valid = FLIP_VALID(cp_cons,
440 cpr->cp_ring_struct->ring_mask,
443 if (cmp_type == RX_TPA_START_CMPL_TYPE_RX_TPA_START) {
444 bnxt_tpa_start(rxq, (struct rx_tpa_start_cmpl *)rxcmp,
445 (struct rx_tpa_start_cmpl_hi *)rxcmp1);
446 rc = -EINVAL; /* Continue w/o new mbuf */
448 } else if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
449 mbuf = bnxt_tpa_end(rxq, &tmp_raw_cons,
450 (struct rx_tpa_end_cmpl *)rxcmp,
451 (struct rx_tpa_end_cmpl_hi *)rxcmp1);
456 } else if (cmp_type != 0x11) {
461 agg_buf = (rxcmp->agg_bufs_v1 & RX_PKT_CMPL_AGG_BUFS_MASK)
462 >> RX_PKT_CMPL_AGG_BUFS_SFT;
463 if (agg_buf && !bnxt_agg_bufs_valid(cpr, agg_buf, tmp_raw_cons))
468 cons = rxcmp->opaque;
469 mbuf = bnxt_consume_rx_buf(rxr, cons);
475 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
478 mbuf->pkt_len = rxcmp->len;
479 mbuf->data_len = mbuf->pkt_len;
480 mbuf->port = rxq->port_id;
483 flags_type = rte_le_to_cpu_16(rxcmp->flags_type);
484 if (flags_type & RX_PKT_CMPL_FLAGS_RSS_VALID) {
485 mbuf->hash.rss = rxcmp->rss_hash;
486 mbuf->ol_flags |= PKT_RX_RSS_HASH;
488 mbuf->hash.fdir.id = rxcmp1->cfa_code;
489 mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
491 #ifdef RTE_LIBRTE_IEEE1588
492 if (unlikely((flags_type & RX_PKT_CMPL_FLAGS_MASK) ==
493 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP)) {
494 mbuf->ol_flags |= PKT_RX_IEEE1588_PTP | PKT_RX_IEEE1588_TMST;
495 bnxt_get_rx_ts_thor(rxq->bp, rxcmp1->reorder);
499 bnxt_rx_pages(rxq, mbuf, &tmp_raw_cons, agg_buf, NULL);
501 if (rxcmp1->flags2 & RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN) {
502 mbuf->vlan_tci = rxcmp1->metadata &
503 (RX_PKT_CMPL_METADATA_VID_MASK |
504 RX_PKT_CMPL_METADATA_DE |
505 RX_PKT_CMPL_METADATA_PRI_MASK);
506 mbuf->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
509 flags2_f = flags2_0xf(rxcmp1);
511 if (unlikely(((IS_IP_NONTUNNEL_PKT(flags2_f)) &&
512 (RX_CMP_IP_CS_ERROR(rxcmp1))) ||
513 (IS_IP_TUNNEL_PKT(flags2_f) &&
514 (RX_CMP_IP_OUTER_CS_ERROR(rxcmp1))))) {
515 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
516 } else if (unlikely(RX_CMP_IP_CS_UNKNOWN(rxcmp1))) {
517 mbuf->ol_flags |= PKT_RX_IP_CKSUM_UNKNOWN;
519 mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
523 if (likely(IS_L4_NONTUNNEL_PKT(flags2_f))) {
524 if (unlikely(RX_CMP_L4_INNER_CS_ERR2(rxcmp1)))
525 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
527 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
528 } else if (IS_L4_TUNNEL_PKT(flags2_f)) {
529 if (unlikely(RX_CMP_L4_INNER_CS_ERR2(rxcmp1)))
530 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
532 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
533 if (unlikely(RX_CMP_L4_OUTER_CS_ERR2(rxcmp1))) {
534 mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
535 } else if (unlikely(IS_L4_TUNNEL_PKT_ONLY_INNER_L4_CS
537 mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_UNKNOWN;
539 mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
541 } else if (unlikely(RX_CMP_L4_CS_UNKNOWN(rxcmp1))) {
542 mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
545 mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);
548 if (rxcmp1->errors_v2 & RX_CMP_L2_ERRORS) {
549 /* Re-install the mbuf back to the rx ring */
550 bnxt_reuse_rx_mbuf(rxr, cons, mbuf);
557 * TODO: Redesign this....
558 * If the allocation fails, the packet does not get received.
559 * Simply returning this will result in slowly falling behind
560 * on the producer ring buffers.
561 * Instead, "filling up" the producer just before ringing the
562 * doorbell could be a better solution since it will let the
563 * producer ring starve until memory is available again pushing
564 * the drops into hardware and getting them out of the driver
565 * allowing recovery to a full producer ring.
567 * This could also help with cache usage by preventing per-packet
568 * calls in favour of a tight loop with the same function being called
571 prod = RING_NEXT(rxr->rx_ring_struct, prod);
572 if (bnxt_alloc_rx_data(rxq, rxr, prod)) {
573 PMD_DRV_LOG(ERR, "mbuf alloc failed with prod=0x%x\n", prod);
579 * All MBUFs are allocated with the same size under DPDK,
580 * no optimization for rx_copy_thresh
587 *raw_cons = tmp_raw_cons;
592 uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
595 struct bnxt_rx_queue *rxq = rx_queue;
596 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
597 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
598 uint32_t raw_cons = cpr->cp_raw_cons;
601 struct rx_pkt_cmpl *rxcmp;
602 uint16_t prod = rxr->rx_prod;
603 uint16_t ag_prod = rxr->ag_prod;
607 if (unlikely(is_bnxt_in_error(rxq->bp)))
610 /* If Rx Q was stopped return */
611 if (unlikely(!rxq->rx_started ||
612 !rte_spinlock_trylock(&rxq->lock)))
615 /* Handle RX burst request */
617 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
618 rte_prefetch0(&cpr->cp_desc_ring[cons]);
619 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
621 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
623 cpr->valid = FLIP_VALID(cons,
624 cpr->cp_ring_struct->ring_mask,
627 /* TODO: Avoid magic numbers... */
628 if ((CMP_TYPE(rxcmp) & 0x30) == 0x10) {
629 rc = bnxt_rx_pkt(&rx_pkts[nb_rx_pkts], rxq, &raw_cons);
630 if (likely(!rc) || rc == -ENOMEM)
632 if (rc == -EBUSY) /* partial completion */
634 } else if (!BNXT_NUM_ASYNC_CPR(rxq->bp)) {
636 bnxt_event_hwrm_resp_handler(rxq->bp,
637 (struct cmpl_base *)rxcmp);
640 raw_cons = NEXT_RAW_CMP(raw_cons);
641 if (nb_rx_pkts == nb_pkts || evt)
643 /* Post some Rx buf early in case of larger burst processing */
644 if (nb_rx_pkts == BNXT_RX_POST_THRESH)
645 bnxt_db_write(&rxr->rx_db, rxr->rx_prod);
648 cpr->cp_raw_cons = raw_cons;
649 if (!nb_rx_pkts && !evt) {
651 * For PMD, there is no need to keep on pushing to REARM
652 * the doorbell if there are no new completions
657 if (prod != rxr->rx_prod)
658 bnxt_db_write(&rxr->rx_db, rxr->rx_prod);
660 /* Ring the AGG ring DB */
661 if (ag_prod != rxr->ag_prod)
662 bnxt_db_write(&rxr->ag_db, rxr->ag_prod);
666 /* Attempt to alloc Rx buf in case of a previous allocation failure. */
670 for (i = prod; i <= nb_rx_pkts;
671 i = RING_NEXT(rxr->rx_ring_struct, i)) {
672 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[i];
674 /* Buffer already allocated for this index. */
675 if (rx_buf->mbuf != NULL)
678 /* This slot is empty. Alloc buffer for Rx */
679 if (!bnxt_alloc_rx_data(rxq, rxr, i)) {
681 bnxt_db_write(&rxr->rx_db, rxr->rx_prod);
683 PMD_DRV_LOG(ERR, "Alloc mbuf failed\n");
690 rte_spinlock_unlock(&rxq->lock);
696 * Dummy DPDK callback for RX.
698 * This function is used to temporarily replace the real callback during
699 * unsafe control operations on the queue, or in case of error.
702 bnxt_dummy_recv_pkts(void *rx_queue __rte_unused,
703 struct rte_mbuf **rx_pkts __rte_unused,
704 uint16_t nb_pkts __rte_unused)
709 void bnxt_free_rx_rings(struct bnxt *bp)
712 struct bnxt_rx_queue *rxq;
717 for (i = 0; i < (int)bp->rx_nr_rings; i++) {
718 rxq = bp->rx_queues[i];
722 bnxt_free_ring(rxq->rx_ring->rx_ring_struct);
723 rte_free(rxq->rx_ring->rx_ring_struct);
725 /* Free the Aggregator ring */
726 bnxt_free_ring(rxq->rx_ring->ag_ring_struct);
727 rte_free(rxq->rx_ring->ag_ring_struct);
728 rxq->rx_ring->ag_ring_struct = NULL;
730 rte_free(rxq->rx_ring);
732 bnxt_free_ring(rxq->cp_ring->cp_ring_struct);
733 rte_free(rxq->cp_ring->cp_ring_struct);
734 rte_free(rxq->cp_ring);
737 bp->rx_queues[i] = NULL;
741 int bnxt_init_rx_ring_struct(struct bnxt_rx_queue *rxq, unsigned int socket_id)
743 struct bnxt_cp_ring_info *cpr;
744 struct bnxt_rx_ring_info *rxr;
745 struct bnxt_ring *ring;
747 rxq->rx_buf_size = BNXT_MAX_PKT_LEN + sizeof(struct rte_mbuf);
749 rxr = rte_zmalloc_socket("bnxt_rx_ring",
750 sizeof(struct bnxt_rx_ring_info),
751 RTE_CACHE_LINE_SIZE, socket_id);
756 ring = rte_zmalloc_socket("bnxt_rx_ring_struct",
757 sizeof(struct bnxt_ring),
758 RTE_CACHE_LINE_SIZE, socket_id);
761 rxr->rx_ring_struct = ring;
762 ring->ring_size = rte_align32pow2(rxq->nb_rx_desc);
763 ring->ring_mask = ring->ring_size - 1;
764 ring->bd = (void *)rxr->rx_desc_ring;
765 ring->bd_dma = rxr->rx_desc_mapping;
766 ring->vmem_size = ring->ring_size * sizeof(struct bnxt_sw_rx_bd);
767 ring->vmem = (void **)&rxr->rx_buf_ring;
769 cpr = rte_zmalloc_socket("bnxt_rx_ring",
770 sizeof(struct bnxt_cp_ring_info),
771 RTE_CACHE_LINE_SIZE, socket_id);
776 ring = rte_zmalloc_socket("bnxt_rx_ring_struct",
777 sizeof(struct bnxt_ring),
778 RTE_CACHE_LINE_SIZE, socket_id);
781 cpr->cp_ring_struct = ring;
782 ring->ring_size = rte_align32pow2(rxr->rx_ring_struct->ring_size *
783 (2 + AGG_RING_SIZE_FACTOR));
784 ring->ring_mask = ring->ring_size - 1;
785 ring->bd = (void *)cpr->cp_desc_ring;
786 ring->bd_dma = cpr->cp_desc_mapping;
790 /* Allocate Aggregator rings */
791 ring = rte_zmalloc_socket("bnxt_rx_ring_struct",
792 sizeof(struct bnxt_ring),
793 RTE_CACHE_LINE_SIZE, socket_id);
796 rxr->ag_ring_struct = ring;
797 ring->ring_size = rte_align32pow2(rxq->nb_rx_desc *
798 AGG_RING_SIZE_FACTOR);
799 ring->ring_mask = ring->ring_size - 1;
800 ring->bd = (void *)rxr->ag_desc_ring;
801 ring->bd_dma = rxr->ag_desc_mapping;
802 ring->vmem_size = ring->ring_size * sizeof(struct bnxt_sw_rx_bd);
803 ring->vmem = (void **)&rxr->ag_buf_ring;
808 static void bnxt_init_rxbds(struct bnxt_ring *ring, uint32_t type,
812 struct rx_prod_pkt_bd *rx_bd_ring = (struct rx_prod_pkt_bd *)ring->bd;
816 for (j = 0; j < ring->ring_size; j++) {
817 rx_bd_ring[j].flags_type = rte_cpu_to_le_16(type);
818 rx_bd_ring[j].len = rte_cpu_to_le_16(len);
819 rx_bd_ring[j].opaque = j;
823 int bnxt_init_one_rx_ring(struct bnxt_rx_queue *rxq)
825 struct bnxt_rx_ring_info *rxr;
826 struct bnxt_ring *ring;
831 size = rte_pktmbuf_data_room_size(rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
832 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
834 type = RX_PROD_PKT_BD_TYPE_RX_PROD_PKT | RX_PROD_PKT_BD_FLAGS_EOP_PAD;
837 ring = rxr->rx_ring_struct;
838 bnxt_init_rxbds(ring, type, size);
841 for (i = 0; i < ring->ring_size; i++) {
842 if (bnxt_alloc_rx_data(rxq, rxr, prod) != 0) {
844 "init'ed rx ring %d with %d/%d mbufs only\n",
845 rxq->queue_id, i, ring->ring_size);
849 prod = RING_NEXT(rxr->rx_ring_struct, prod);
852 ring = rxr->ag_ring_struct;
853 type = RX_PROD_AGG_BD_TYPE_RX_PROD_AGG;
854 bnxt_init_rxbds(ring, type, size);
857 for (i = 0; i < ring->ring_size; i++) {
858 if (bnxt_alloc_ag_data(rxq, rxr, prod) != 0) {
860 "init'ed AG ring %d with %d/%d mbufs only\n",
861 rxq->queue_id, i, ring->ring_size);
865 prod = RING_NEXT(rxr->ag_ring_struct, prod);
867 PMD_DRV_LOG(DEBUG, "AGG Done!\n");
870 unsigned int max_aggs = BNXT_TPA_MAX_AGGS(rxq->bp);
872 for (i = 0; i < max_aggs; i++) {
873 rxr->tpa_info[i].mbuf =
874 __bnxt_alloc_rx_data(rxq->mb_pool);
875 if (!rxr->tpa_info[i].mbuf) {
876 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
881 PMD_DRV_LOG(DEBUG, "TPA alloc Done!\n");