1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
9 #include <rte_bitmap.h>
10 #include <rte_byteorder.h>
11 #include <rte_malloc.h>
12 #include <rte_memory.h>
15 #include "bnxt_reps.h"
16 #include "bnxt_ring.h"
19 #include "hsi_struct_def_dpdk.h"
20 #ifdef RTE_LIBRTE_IEEE1588
21 #include "bnxt_hwrm.h"
24 #include <bnxt_tf_common.h>
25 #include <ulp_mark_mgr.h>
31 static inline struct rte_mbuf *__bnxt_alloc_rx_data(struct rte_mempool *mb)
33 struct rte_mbuf *data;
35 data = rte_mbuf_raw_alloc(mb);
40 static inline int bnxt_alloc_rx_data(struct bnxt_rx_queue *rxq,
41 struct bnxt_rx_ring_info *rxr,
44 uint16_t prod = RING_IDX(rxr->rx_ring_struct, raw_prod);
45 struct rx_prod_pkt_bd *rxbd;
46 struct rte_mbuf **rx_buf;
47 struct rte_mbuf *mbuf;
49 rxbd = &rxr->rx_desc_ring[prod];
50 rx_buf = &rxr->rx_buf_ring[prod];
51 mbuf = __bnxt_alloc_rx_data(rxq->mb_pool);
53 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
58 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
60 rxbd->address = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
65 static inline int bnxt_alloc_ag_data(struct bnxt_rx_queue *rxq,
66 struct bnxt_rx_ring_info *rxr,
69 uint16_t prod = RING_IDX(rxr->ag_ring_struct, raw_prod);
70 struct rx_prod_pkt_bd *rxbd;
71 struct rte_mbuf **rx_buf;
72 struct rte_mbuf *mbuf;
74 rxbd = &rxr->ag_desc_ring[prod];
75 rx_buf = &rxr->ag_buf_ring[prod];
77 PMD_DRV_LOG(ERR, "Jumbo Frame. rxbd is NULL\n");
82 PMD_DRV_LOG(ERR, "Jumbo Frame. rx_buf is NULL\n");
86 mbuf = __bnxt_alloc_rx_data(rxq->mb_pool);
88 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
93 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
95 rxbd->address = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
100 static inline void bnxt_reuse_rx_mbuf(struct bnxt_rx_ring_info *rxr,
101 struct rte_mbuf *mbuf)
103 uint16_t prod, raw_prod = RING_NEXT(rxr->rx_raw_prod);
104 struct rte_mbuf **prod_rx_buf;
105 struct rx_prod_pkt_bd *prod_bd;
107 prod = RING_IDX(rxr->rx_ring_struct, raw_prod);
108 prod_rx_buf = &rxr->rx_buf_ring[prod];
110 RTE_ASSERT(*prod_rx_buf == NULL);
111 RTE_ASSERT(mbuf != NULL);
115 prod_bd = &rxr->rx_desc_ring[prod];
117 prod_bd->address = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
119 rxr->rx_raw_prod = raw_prod;
123 struct rte_mbuf *bnxt_consume_rx_buf(struct bnxt_rx_ring_info *rxr,
126 struct rte_mbuf **cons_rx_buf;
127 struct rte_mbuf *mbuf;
129 cons_rx_buf = &rxr->rx_buf_ring[RING_IDX(rxr->rx_ring_struct, cons)];
130 RTE_ASSERT(*cons_rx_buf != NULL);
137 static void bnxt_tpa_start(struct bnxt_rx_queue *rxq,
138 struct rx_tpa_start_cmpl *tpa_start,
139 struct rx_tpa_start_cmpl_hi *tpa_start1)
141 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
144 struct bnxt_tpa_info *tpa_info;
145 struct rte_mbuf *mbuf;
147 agg_id = bnxt_tpa_start_agg_id(rxq->bp, tpa_start);
149 data_cons = tpa_start->opaque;
150 tpa_info = &rxr->tpa_info[agg_id];
152 mbuf = bnxt_consume_rx_buf(rxr, data_cons);
154 bnxt_reuse_rx_mbuf(rxr, tpa_info->mbuf);
156 tpa_info->agg_count = 0;
157 tpa_info->mbuf = mbuf;
158 tpa_info->len = rte_le_to_cpu_32(tpa_start->len);
160 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
163 mbuf->pkt_len = rte_le_to_cpu_32(tpa_start->len);
164 mbuf->data_len = mbuf->pkt_len;
165 mbuf->port = rxq->port_id;
166 mbuf->ol_flags = PKT_RX_LRO;
167 if (likely(tpa_start->flags_type &
168 rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS_RSS_VALID))) {
169 mbuf->hash.rss = rte_le_to_cpu_32(tpa_start->rss_hash);
170 mbuf->ol_flags |= PKT_RX_RSS_HASH;
172 mbuf->hash.fdir.id = rte_le_to_cpu_16(tpa_start1->cfa_code);
173 mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
175 if (tpa_start1->flags2 &
176 rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN)) {
177 mbuf->vlan_tci = rte_le_to_cpu_32(tpa_start1->metadata);
178 mbuf->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
180 if (likely(tpa_start1->flags2 &
181 rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC)))
182 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
184 /* recycle next mbuf */
185 data_cons = RING_NEXT(data_cons);
186 bnxt_reuse_rx_mbuf(rxr, bnxt_consume_rx_buf(rxr, data_cons));
189 static int bnxt_agg_bufs_valid(struct bnxt_cp_ring_info *cpr,
190 uint8_t agg_bufs, uint32_t raw_cp_cons)
192 uint16_t last_cp_cons;
193 struct rx_pkt_cmpl *agg_cmpl;
195 raw_cp_cons = ADV_RAW_CMP(raw_cp_cons, agg_bufs);
196 last_cp_cons = RING_CMP(cpr->cp_ring_struct, raw_cp_cons);
197 agg_cmpl = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[last_cp_cons];
198 cpr->valid = FLIP_VALID(raw_cp_cons,
199 cpr->cp_ring_struct->ring_mask,
201 return CMP_VALID(agg_cmpl, raw_cp_cons, cpr->cp_ring_struct);
204 /* TPA consume agg buffer out of order, allocate connected data only */
205 static int bnxt_prod_ag_mbuf(struct bnxt_rx_queue *rxq)
207 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
208 uint16_t raw_next = RING_NEXT(rxr->ag_raw_prod);
209 uint16_t bmap_next = RING_IDX(rxr->ag_ring_struct, raw_next);
211 /* TODO batch allocation for better performance */
212 while (rte_bitmap_get(rxr->ag_bitmap, bmap_next)) {
213 if (unlikely(bnxt_alloc_ag_data(rxq, rxr, raw_next))) {
214 PMD_DRV_LOG(ERR, "agg mbuf alloc failed: prod=0x%x\n",
218 rte_bitmap_clear(rxr->ag_bitmap, bmap_next);
219 rxr->ag_raw_prod = raw_next;
220 raw_next = RING_NEXT(raw_next);
221 bmap_next = RING_IDX(rxr->ag_ring_struct, raw_next);
227 static int bnxt_rx_pages(struct bnxt_rx_queue *rxq,
228 struct rte_mbuf *mbuf, uint32_t *tmp_raw_cons,
229 uint8_t agg_buf, struct bnxt_tpa_info *tpa_info)
231 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
232 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
234 uint16_t cp_cons, ag_cons;
235 struct rx_pkt_cmpl *rxcmp;
236 struct rte_mbuf *last = mbuf;
237 bool is_p5_tpa = tpa_info && BNXT_CHIP_P5(rxq->bp);
239 for (i = 0; i < agg_buf; i++) {
240 struct rte_mbuf **ag_buf;
241 struct rte_mbuf *ag_mbuf;
244 rxcmp = (void *)&tpa_info->agg_arr[i];
246 *tmp_raw_cons = NEXT_RAW_CMP(*tmp_raw_cons);
247 cp_cons = RING_CMP(cpr->cp_ring_struct, *tmp_raw_cons);
248 rxcmp = (struct rx_pkt_cmpl *)
249 &cpr->cp_desc_ring[cp_cons];
253 bnxt_dump_cmpl(cp_cons, rxcmp);
256 ag_cons = rxcmp->opaque;
257 RTE_ASSERT(ag_cons <= rxr->ag_ring_struct->ring_mask);
258 ag_buf = &rxr->ag_buf_ring[ag_cons];
260 RTE_ASSERT(ag_mbuf != NULL);
262 ag_mbuf->data_len = rte_le_to_cpu_16(rxcmp->len);
265 mbuf->pkt_len += ag_mbuf->data_len;
267 last->next = ag_mbuf;
273 * As aggregation buffer consumed out of order in TPA module,
274 * use bitmap to track freed slots to be allocated and notified
277 rte_bitmap_set(rxr->ag_bitmap, ag_cons);
279 bnxt_prod_ag_mbuf(rxq);
283 static inline struct rte_mbuf *bnxt_tpa_end(
284 struct bnxt_rx_queue *rxq,
285 uint32_t *raw_cp_cons,
286 struct rx_tpa_end_cmpl *tpa_end,
287 struct rx_tpa_end_cmpl_hi *tpa_end1)
289 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
290 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
292 struct rte_mbuf *mbuf;
294 uint8_t payload_offset;
295 struct bnxt_tpa_info *tpa_info;
297 if (BNXT_CHIP_P5(rxq->bp)) {
298 struct rx_tpa_v2_end_cmpl *th_tpa_end;
299 struct rx_tpa_v2_end_cmpl_hi *th_tpa_end1;
301 th_tpa_end = (void *)tpa_end;
302 th_tpa_end1 = (void *)tpa_end1;
303 agg_id = BNXT_TPA_END_AGG_ID_TH(th_tpa_end);
304 agg_bufs = BNXT_TPA_END_AGG_BUFS_TH(th_tpa_end1);
305 payload_offset = th_tpa_end1->payload_offset;
307 agg_id = BNXT_TPA_END_AGG_ID(tpa_end);
308 agg_bufs = BNXT_TPA_END_AGG_BUFS(tpa_end);
309 if (!bnxt_agg_bufs_valid(cpr, agg_bufs, *raw_cp_cons))
311 payload_offset = tpa_end->payload_offset;
314 tpa_info = &rxr->tpa_info[agg_id];
315 mbuf = tpa_info->mbuf;
316 RTE_ASSERT(mbuf != NULL);
319 bnxt_rx_pages(rxq, mbuf, raw_cp_cons, agg_bufs, tpa_info);
321 mbuf->l4_len = payload_offset;
323 struct rte_mbuf *new_data = __bnxt_alloc_rx_data(rxq->mb_pool);
324 RTE_ASSERT(new_data != NULL);
326 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
329 tpa_info->mbuf = new_data;
334 uint32_t bnxt_ptype_table[BNXT_PTYPE_TBL_DIM] __rte_cache_aligned;
336 static void __rte_cold
337 bnxt_init_ptype_table(void)
339 uint32_t *pt = bnxt_ptype_table;
340 static bool initialized;
348 for (i = 0; i < BNXT_PTYPE_TBL_DIM; i++) {
349 if (i & (RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN >> 2))
350 pt[i] = RTE_PTYPE_L2_ETHER_VLAN;
352 pt[i] = RTE_PTYPE_L2_ETHER;
354 ip6 = i & (RX_PKT_CMPL_FLAGS2_IP_TYPE >> 7);
355 tun = i & (RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC >> 2);
356 type = (i & 0x38) << 9;
359 l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
360 else if (!tun && ip6)
361 l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
362 else if (tun && !ip6)
363 l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
365 l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
368 case RX_PKT_CMPL_FLAGS_ITYPE_ICMP:
370 pt[i] |= l3 | RTE_PTYPE_INNER_L4_ICMP;
372 pt[i] |= l3 | RTE_PTYPE_L4_ICMP;
374 case RX_PKT_CMPL_FLAGS_ITYPE_TCP:
376 pt[i] |= l3 | RTE_PTYPE_INNER_L4_TCP;
378 pt[i] |= l3 | RTE_PTYPE_L4_TCP;
380 case RX_PKT_CMPL_FLAGS_ITYPE_UDP:
382 pt[i] |= l3 | RTE_PTYPE_INNER_L4_UDP;
384 pt[i] |= l3 | RTE_PTYPE_L4_UDP;
386 case RX_PKT_CMPL_FLAGS_ITYPE_IP:
395 bnxt_parse_pkt_type(struct rx_pkt_cmpl *rxcmp, struct rx_pkt_cmpl_hi *rxcmp1)
397 uint32_t flags_type, flags2;
400 flags_type = rte_le_to_cpu_16(rxcmp->flags_type);
401 flags2 = rte_le_to_cpu_32(rxcmp1->flags2);
405 * bit 0: RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC
406 * bit 1: RX_CMPL_FLAGS2_IP_TYPE
407 * bit 2: RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN
408 * bits 3-6: RX_PKT_CMPL_FLAGS_ITYPE
410 index = ((flags_type & RX_PKT_CMPL_FLAGS_ITYPE_MASK) >> 9) |
411 ((flags2 & (RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN |
412 RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC)) >> 2) |
413 ((flags2 & RX_PKT_CMPL_FLAGS2_IP_TYPE) >> 7);
415 return bnxt_ptype_table[index];
419 bnxt_ol_flags_table[BNXT_OL_FLAGS_TBL_DIM] __rte_cache_aligned;
422 bnxt_ol_flags_err_table[BNXT_OL_FLAGS_ERR_TBL_DIM] __rte_cache_aligned;
424 static void __rte_cold
425 bnxt_init_ol_flags_tables(void)
427 static bool initialized;
434 /* Initialize ol_flags table. */
435 pt = bnxt_ol_flags_table;
436 for (i = 0; i < BNXT_OL_FLAGS_TBL_DIM; i++) {
438 if (i & RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN)
439 pt[i] |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
441 if (i & RX_PKT_CMPL_FLAGS2_IP_CS_CALC)
442 pt[i] |= PKT_RX_IP_CKSUM_GOOD;
444 if (i & RX_PKT_CMPL_FLAGS2_L4_CS_CALC)
445 pt[i] |= PKT_RX_L4_CKSUM_GOOD;
447 if (i & RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC)
448 pt[i] |= PKT_RX_OUTER_L4_CKSUM_GOOD;
451 /* Initialize checksum error table. */
452 pt = bnxt_ol_flags_err_table;
453 for (i = 0; i < BNXT_OL_FLAGS_ERR_TBL_DIM; i++) {
455 if (i & (RX_PKT_CMPL_ERRORS_IP_CS_ERROR >> 4))
456 pt[i] |= PKT_RX_IP_CKSUM_BAD;
458 if (i & (RX_PKT_CMPL_ERRORS_L4_CS_ERROR >> 4))
459 pt[i] |= PKT_RX_L4_CKSUM_BAD;
461 if (i & (RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR >> 4))
462 pt[i] |= PKT_RX_EIP_CKSUM_BAD;
464 if (i & (RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR >> 4))
465 pt[i] |= PKT_RX_OUTER_L4_CKSUM_BAD;
472 bnxt_set_ol_flags(struct rx_pkt_cmpl *rxcmp, struct rx_pkt_cmpl_hi *rxcmp1,
473 struct rte_mbuf *mbuf)
475 uint16_t flags_type, errors, flags;
478 flags_type = rte_le_to_cpu_16(rxcmp->flags_type);
480 flags = rte_le_to_cpu_32(rxcmp1->flags2) &
481 (RX_PKT_CMPL_FLAGS2_IP_CS_CALC |
482 RX_PKT_CMPL_FLAGS2_L4_CS_CALC |
483 RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC |
484 RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC |
485 RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN);
487 errors = rte_le_to_cpu_16(rxcmp1->errors_v2) &
488 (RX_PKT_CMPL_ERRORS_IP_CS_ERROR |
489 RX_PKT_CMPL_ERRORS_L4_CS_ERROR |
490 RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR |
491 RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR);
492 errors = (errors >> 4) & flags;
494 ol_flags = bnxt_ol_flags_table[flags & ~errors];
497 ol_flags |= bnxt_ol_flags_err_table[errors];
499 if (flags_type & RX_PKT_CMPL_FLAGS_RSS_VALID) {
500 mbuf->hash.rss = rte_le_to_cpu_32(rxcmp->rss_hash);
501 ol_flags |= PKT_RX_RSS_HASH;
504 mbuf->ol_flags = ol_flags;
507 #ifdef RTE_LIBRTE_IEEE1588
509 bnxt_get_rx_ts_p5(struct bnxt *bp, uint32_t rx_ts_cmpl)
511 uint64_t systime_cycles = 0;
513 if (!BNXT_CHIP_P5(bp))
516 /* On Thor, Rx timestamps are provided directly in the
517 * Rx completion records to the driver. Only 32 bits of
518 * the timestamp is present in the completion. Driver needs
519 * to read the current 48 bit free running timer using the
520 * HWRM_PORT_TS_QUERY command and combine the upper 16 bits
521 * from the HWRM response with the lower 32 bits in the
522 * Rx completion to produce the 48 bit timestamp for the Rx packet
524 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
526 bp->ptp_cfg->rx_timestamp = (systime_cycles & 0xFFFF00000000);
527 bp->ptp_cfg->rx_timestamp |= rx_ts_cmpl;
532 bnxt_ulp_set_mark_in_mbuf(struct bnxt *bp, struct rx_pkt_cmpl_hi *rxcmp1,
533 struct rte_mbuf *mbuf, uint32_t *vfr_flag)
541 uint32_t gfid_support = 0;
544 if (BNXT_GFID_ENABLED(bp))
547 cfa_code = rte_le_to_cpu_16(rxcmp1->cfa_code);
548 flags2 = rte_le_to_cpu_32(rxcmp1->flags2);
549 meta = rte_le_to_cpu_32(rxcmp1->metadata);
552 * The flags field holds extra bits of info from [6:4]
553 * which indicate if the flow is in TCAM or EM or EEM
555 meta_fmt = (flags2 & BNXT_CFA_META_FMT_MASK) >>
556 BNXT_CFA_META_FMT_SHFT;
561 /* Not an LFID or GFID, a flush cmd. */
564 /* LFID mode, no vlan scenario */
572 * Assume that EM doesn't support Mark due to GFID
573 * collisions with EEM. Simply return without setting the mark
576 if (BNXT_CFA_META_EM_TEST(meta)) {
577 /*This is EM hit {EM(1), GFID[27:16], 19'd0 or vtag } */
579 meta >>= BNXT_RX_META_CFA_CODE_SHIFT;
580 cfa_code |= meta << BNXT_CFA_CODE_META_SHIFT;
583 * It is a TCAM entry, so it is an LFID.
584 * The TCAM IDX and Mode can also be determined
585 * by decoding the meta_data. We are not
586 * using these for now.
592 /* EEM Case, only using gfid in EEM for now. */
596 * For EEM flows, The first part of cfa_code is 16 bits.
597 * The second part is embedded in the
598 * metadata field from bit 19 onwards. The driver needs to
599 * ignore the first 19 bits of metadata and use the next 12
600 * bits as higher 12 bits of cfa_code.
602 meta >>= BNXT_RX_META_CFA_CODE_SHIFT;
603 cfa_code |= meta << BNXT_CFA_CODE_META_SHIFT;
606 /* For other values, the cfa_code is assumed to be an LFID. */
610 rc = ulp_mark_db_mark_get(bp->ulp_ctx, gfid,
611 cfa_code, vfr_flag, &mark_id);
613 /* VF to VFR Rx path. So, skip mark_id injection in mbuf */
614 if (vfr_flag && *vfr_flag)
616 /* Got the mark, write it to the mbuf and return */
617 mbuf->hash.fdir.hi = mark_id;
618 *bnxt_cfa_code_dynfield(mbuf) = cfa_code & 0xffffffffull;
619 mbuf->hash.fdir.id = rxcmp1->cfa_code;
620 mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
625 mbuf->hash.fdir.hi = 0;
626 mbuf->hash.fdir.id = 0;
631 void bnxt_set_mark_in_mbuf(struct bnxt *bp,
632 struct rx_pkt_cmpl_hi *rxcmp1,
633 struct rte_mbuf *mbuf)
635 uint32_t cfa_code = 0;
636 uint8_t meta_fmt = 0;
640 cfa_code = rte_le_to_cpu_16(rxcmp1->cfa_code);
644 if (cfa_code && !bp->mark_table[cfa_code].valid)
647 flags2 = rte_le_to_cpu_16(rxcmp1->flags2);
648 meta = rte_le_to_cpu_32(rxcmp1->metadata);
650 meta >>= BNXT_RX_META_CFA_CODE_SHIFT;
652 /* The flags field holds extra bits of info from [6:4]
653 * which indicate if the flow is in TCAM or EM or EEM
655 meta_fmt = (flags2 & BNXT_CFA_META_FMT_MASK) >>
656 BNXT_CFA_META_FMT_SHFT;
658 /* meta_fmt == 4 => 'b100 => 'b10x => EM.
659 * meta_fmt == 5 => 'b101 => 'b10x => EM + VLAN
660 * meta_fmt == 6 => 'b110 => 'b11x => EEM
661 * meta_fmt == 7 => 'b111 => 'b11x => EEM + VLAN.
663 meta_fmt >>= BNXT_CFA_META_FMT_EM_EEM_SHFT;
666 mbuf->hash.fdir.hi = bp->mark_table[cfa_code].mark_id;
667 mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
670 static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
671 struct bnxt_rx_queue *rxq, uint32_t *raw_cons)
673 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
674 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
675 struct rx_pkt_cmpl *rxcmp;
676 struct rx_pkt_cmpl_hi *rxcmp1;
677 uint32_t tmp_raw_cons = *raw_cons;
678 uint16_t cons, raw_prod, cp_cons =
679 RING_CMP(cpr->cp_ring_struct, tmp_raw_cons);
680 struct rte_mbuf *mbuf;
684 uint32_t vfr_flag = 0, mark_id = 0;
685 struct bnxt *bp = rxq->bp;
687 rxcmp = (struct rx_pkt_cmpl *)
688 &cpr->cp_desc_ring[cp_cons];
690 cmp_type = CMP_TYPE(rxcmp);
692 if (cmp_type == RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG) {
693 struct rx_tpa_v2_abuf_cmpl *rx_agg = (void *)rxcmp;
694 uint16_t agg_id = rte_cpu_to_le_16(rx_agg->agg_id);
695 struct bnxt_tpa_info *tpa_info;
697 tpa_info = &rxr->tpa_info[agg_id];
698 RTE_ASSERT(tpa_info->agg_count < 16);
699 tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg;
700 rc = -EINVAL; /* Continue w/o new mbuf */
704 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
705 cp_cons = RING_CMP(cpr->cp_ring_struct, tmp_raw_cons);
706 rxcmp1 = (struct rx_pkt_cmpl_hi *)&cpr->cp_desc_ring[cp_cons];
708 if (!CMP_VALID(rxcmp1, tmp_raw_cons, cpr->cp_ring_struct))
711 cpr->valid = FLIP_VALID(cp_cons,
712 cpr->cp_ring_struct->ring_mask,
715 if (cmp_type == RX_TPA_START_CMPL_TYPE_RX_TPA_START) {
716 bnxt_tpa_start(rxq, (struct rx_tpa_start_cmpl *)rxcmp,
717 (struct rx_tpa_start_cmpl_hi *)rxcmp1);
718 rc = -EINVAL; /* Continue w/o new mbuf */
720 } else if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
721 mbuf = bnxt_tpa_end(rxq, &tmp_raw_cons,
722 (struct rx_tpa_end_cmpl *)rxcmp,
723 (struct rx_tpa_end_cmpl_hi *)rxcmp1);
728 } else if (cmp_type != 0x11) {
733 agg_buf = (rxcmp->agg_bufs_v1 & RX_PKT_CMPL_AGG_BUFS_MASK)
734 >> RX_PKT_CMPL_AGG_BUFS_SFT;
735 if (agg_buf && !bnxt_agg_bufs_valid(cpr, agg_buf, tmp_raw_cons))
738 raw_prod = rxr->rx_raw_prod;
740 cons = rxcmp->opaque;
741 mbuf = bnxt_consume_rx_buf(rxr, cons);
745 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
748 mbuf->pkt_len = rxcmp->len;
749 mbuf->data_len = mbuf->pkt_len;
750 mbuf->port = rxq->port_id;
752 bnxt_set_ol_flags(rxcmp, rxcmp1, mbuf);
754 #ifdef RTE_LIBRTE_IEEE1588
755 if (unlikely((rte_le_to_cpu_16(rxcmp->flags_type) &
756 RX_PKT_CMPL_FLAGS_MASK) ==
757 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP)) {
758 mbuf->ol_flags |= PKT_RX_IEEE1588_PTP | PKT_RX_IEEE1588_TMST;
759 bnxt_get_rx_ts_p5(rxq->bp, rxcmp1->reorder);
763 if (BNXT_TRUFLOW_EN(bp))
764 mark_id = bnxt_ulp_set_mark_in_mbuf(rxq->bp, rxcmp1, mbuf,
767 bnxt_set_mark_in_mbuf(rxq->bp, rxcmp1, mbuf);
770 bnxt_rx_pages(rxq, mbuf, &tmp_raw_cons, agg_buf, NULL);
772 mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);
775 if (rxcmp1->errors_v2 & RX_CMP_L2_ERRORS) {
776 /* Re-install the mbuf back to the rx ring */
777 bnxt_reuse_rx_mbuf(rxr, cons, mbuf);
784 * TODO: Redesign this....
785 * If the allocation fails, the packet does not get received.
786 * Simply returning this will result in slowly falling behind
787 * on the producer ring buffers.
788 * Instead, "filling up" the producer just before ringing the
789 * doorbell could be a better solution since it will let the
790 * producer ring starve until memory is available again pushing
791 * the drops into hardware and getting them out of the driver
792 * allowing recovery to a full producer ring.
794 * This could also help with cache usage by preventing per-packet
795 * calls in favour of a tight loop with the same function being called
798 raw_prod = RING_NEXT(raw_prod);
799 if (bnxt_alloc_rx_data(rxq, rxr, raw_prod)) {
800 PMD_DRV_LOG(ERR, "mbuf alloc failed with prod=0x%x\n",
805 rxr->rx_raw_prod = raw_prod;
807 if (BNXT_TRUFLOW_EN(bp) && (BNXT_VF_IS_TRUSTED(bp) || BNXT_PF(bp)) &&
809 bnxt_vfr_recv(mark_id, rxq->queue_id, mbuf);
810 /* Now return an error so that nb_rx_pkts is not
812 * This packet was meant to be given to the representor.
813 * So no need to account the packet and give it to
814 * parent Rx burst function.
820 * All MBUFs are allocated with the same size under DPDK,
821 * no optimization for rx_copy_thresh
828 *raw_cons = tmp_raw_cons;
833 uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
836 struct bnxt_rx_queue *rxq = rx_queue;
837 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
838 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
839 uint16_t rx_raw_prod = rxr->rx_raw_prod;
840 uint16_t ag_raw_prod = rxr->ag_raw_prod;
841 uint32_t raw_cons = cpr->cp_raw_cons;
844 int nb_rep_rx_pkts = 0;
845 struct rx_pkt_cmpl *rxcmp;
849 if (unlikely(is_bnxt_in_error(rxq->bp)))
852 /* If Rx Q was stopped return */
853 if (unlikely(!rxq->rx_started))
856 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
858 * Replenish buffers if needed when a transition has been made from
859 * vector- to non-vector- receive processing.
861 while (unlikely(rxq->rxrearm_nb)) {
862 if (!bnxt_alloc_rx_data(rxq, rxr, rxq->rxrearm_start)) {
863 rxr->rx_raw_prod = rxq->rxrearm_start;
864 bnxt_db_write(&rxr->rx_db, rxr->rx_raw_prod);
865 rxq->rxrearm_start++;
868 /* Retry allocation on next call. */
874 /* Handle RX burst request */
876 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
877 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
879 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
881 cpr->valid = FLIP_VALID(cons,
882 cpr->cp_ring_struct->ring_mask,
885 /* TODO: Avoid magic numbers... */
886 if ((CMP_TYPE(rxcmp) & 0x30) == 0x10) {
887 rc = bnxt_rx_pkt(&rx_pkts[nb_rx_pkts], rxq, &raw_cons);
888 if (likely(!rc) || rc == -ENOMEM)
890 if (rc == -EBUSY) /* partial completion */
892 if (rc == -ENODEV) /* completion for representor */
894 } else if (!BNXT_NUM_ASYNC_CPR(rxq->bp)) {
896 bnxt_event_hwrm_resp_handler(rxq->bp,
897 (struct cmpl_base *)rxcmp);
898 /* If the async event is Fatal error, return */
899 if (unlikely(is_bnxt_in_error(rxq->bp)))
903 raw_cons = NEXT_RAW_CMP(raw_cons);
904 if (nb_rx_pkts == nb_pkts || nb_rep_rx_pkts == nb_pkts || evt)
906 /* Post some Rx buf early in case of larger burst processing */
907 if (nb_rx_pkts == BNXT_RX_POST_THRESH)
908 bnxt_db_write(&rxr->rx_db, rxr->rx_raw_prod);
911 cpr->cp_raw_cons = raw_cons;
912 if (!nb_rx_pkts && !nb_rep_rx_pkts && !evt) {
914 * For PMD, there is no need to keep on pushing to REARM
915 * the doorbell if there are no new completions
920 /* Ring the completion queue doorbell. */
923 /* Ring the receive descriptor doorbell. */
924 if (rx_raw_prod != rxr->rx_raw_prod)
925 bnxt_db_write(&rxr->rx_db, rxr->rx_raw_prod);
927 /* Ring the AGG ring DB */
928 if (ag_raw_prod != rxr->ag_raw_prod)
929 bnxt_db_write(&rxr->ag_db, rxr->ag_raw_prod);
931 /* Attempt to alloc Rx buf in case of a previous allocation failure. */
933 int i = RING_NEXT(rx_raw_prod);
934 int cnt = nb_rx_pkts;
936 for (; nb_rx_pkts; i = RING_NEXT(i), cnt--) {
937 struct rte_mbuf **rx_buf;
938 uint16_t rx_raw_prod = RING_IDX(rxr->rx_ring_struct, i);
940 rx_buf = &rxr->rx_buf_ring[rx_raw_prod];
942 /* Buffer already allocated for this index. */
943 if (*rx_buf != NULL && *rx_buf != &rxq->fake_mbuf)
946 /* This slot is empty. Alloc buffer for Rx */
947 if (!bnxt_alloc_rx_data(rxq, rxr, i)) {
948 rxr->rx_raw_prod = i;
949 bnxt_db_write(&rxr->rx_db, rxr->rx_raw_prod);
951 PMD_DRV_LOG(ERR, "Alloc mbuf failed\n");
962 * Dummy DPDK callback for RX.
964 * This function is used to temporarily replace the real callback during
965 * unsafe control operations on the queue, or in case of error.
968 bnxt_dummy_recv_pkts(void *rx_queue __rte_unused,
969 struct rte_mbuf **rx_pkts __rte_unused,
970 uint16_t nb_pkts __rte_unused)
975 void bnxt_free_rx_rings(struct bnxt *bp)
978 struct bnxt_rx_queue *rxq;
983 for (i = 0; i < (int)bp->rx_nr_rings; i++) {
984 rxq = bp->rx_queues[i];
988 bnxt_free_ring(rxq->rx_ring->rx_ring_struct);
989 rte_free(rxq->rx_ring->rx_ring_struct);
991 /* Free the Aggregator ring */
992 bnxt_free_ring(rxq->rx_ring->ag_ring_struct);
993 rte_free(rxq->rx_ring->ag_ring_struct);
994 rxq->rx_ring->ag_ring_struct = NULL;
996 rte_free(rxq->rx_ring);
998 bnxt_free_ring(rxq->cp_ring->cp_ring_struct);
999 rte_free(rxq->cp_ring->cp_ring_struct);
1000 rte_free(rxq->cp_ring);
1003 bp->rx_queues[i] = NULL;
1007 int bnxt_init_rx_ring_struct(struct bnxt_rx_queue *rxq, unsigned int socket_id)
1009 struct rte_eth_dev *eth_dev = rxq->bp->eth_dev;
1010 struct rte_eth_rxmode *rxmode;
1011 struct bnxt_cp_ring_info *cpr;
1012 struct bnxt_rx_ring_info *rxr;
1013 struct bnxt_ring *ring;
1016 rxq->rx_buf_size = BNXT_MAX_PKT_LEN + sizeof(struct rte_mbuf);
1018 rxr = rte_zmalloc_socket("bnxt_rx_ring",
1019 sizeof(struct bnxt_rx_ring_info),
1020 RTE_CACHE_LINE_SIZE, socket_id);
1025 ring = rte_zmalloc_socket("bnxt_rx_ring_struct",
1026 sizeof(struct bnxt_ring),
1027 RTE_CACHE_LINE_SIZE, socket_id);
1030 rxr->rx_ring_struct = ring;
1031 ring->ring_size = rte_align32pow2(rxq->nb_rx_desc);
1032 ring->ring_mask = ring->ring_size - 1;
1033 ring->bd = (void *)rxr->rx_desc_ring;
1034 ring->bd_dma = rxr->rx_desc_mapping;
1036 /* Allocate extra rx ring entries for vector rx. */
1037 ring->vmem_size = sizeof(struct rte_mbuf *) *
1038 (ring->ring_size + RTE_BNXT_DESCS_PER_LOOP);
1040 ring->vmem = (void **)&rxr->rx_buf_ring;
1041 ring->fw_ring_id = INVALID_HW_RING_ID;
1043 cpr = rte_zmalloc_socket("bnxt_rx_ring",
1044 sizeof(struct bnxt_cp_ring_info),
1045 RTE_CACHE_LINE_SIZE, socket_id);
1050 ring = rte_zmalloc_socket("bnxt_rx_ring_struct",
1051 sizeof(struct bnxt_ring),
1052 RTE_CACHE_LINE_SIZE, socket_id);
1055 cpr->cp_ring_struct = ring;
1057 rxmode = ð_dev->data->dev_conf.rxmode;
1058 use_agg_ring = (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) ||
1059 (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) ||
1060 (rxmode->max_rx_pkt_len >
1061 (uint32_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1062 RTE_PKTMBUF_HEADROOM));
1064 /* Allocate two completion slots per entry in desc ring. */
1065 ring->ring_size = rxr->rx_ring_struct->ring_size * 2;
1067 /* Allocate additional slots if aggregation ring is in use. */
1069 ring->ring_size *= AGG_RING_SIZE_FACTOR;
1071 ring->ring_size = rte_align32pow2(ring->ring_size);
1072 ring->ring_mask = ring->ring_size - 1;
1073 ring->bd = (void *)cpr->cp_desc_ring;
1074 ring->bd_dma = cpr->cp_desc_mapping;
1075 ring->vmem_size = 0;
1077 ring->fw_ring_id = INVALID_HW_RING_ID;
1079 /* Allocate Aggregator rings */
1080 ring = rte_zmalloc_socket("bnxt_rx_ring_struct",
1081 sizeof(struct bnxt_ring),
1082 RTE_CACHE_LINE_SIZE, socket_id);
1085 rxr->ag_ring_struct = ring;
1086 ring->ring_size = rte_align32pow2(rxq->nb_rx_desc *
1087 AGG_RING_SIZE_FACTOR);
1088 ring->ring_mask = ring->ring_size - 1;
1089 ring->bd = (void *)rxr->ag_desc_ring;
1090 ring->bd_dma = rxr->ag_desc_mapping;
1091 ring->vmem_size = ring->ring_size * sizeof(struct rte_mbuf *);
1092 ring->vmem = (void **)&rxr->ag_buf_ring;
1093 ring->fw_ring_id = INVALID_HW_RING_ID;
1098 static void bnxt_init_rxbds(struct bnxt_ring *ring, uint32_t type,
1102 struct rx_prod_pkt_bd *rx_bd_ring = (struct rx_prod_pkt_bd *)ring->bd;
1106 for (j = 0; j < ring->ring_size; j++) {
1107 rx_bd_ring[j].flags_type = rte_cpu_to_le_16(type);
1108 rx_bd_ring[j].len = rte_cpu_to_le_16(len);
1109 rx_bd_ring[j].opaque = j;
1113 int bnxt_init_one_rx_ring(struct bnxt_rx_queue *rxq)
1115 struct bnxt_rx_ring_info *rxr;
1116 struct bnxt_ring *ring;
1117 uint32_t raw_prod, type;
1121 /* Initialize packet type table. */
1122 bnxt_init_ptype_table();
1124 /* Initialize offload flags parsing table. */
1125 bnxt_init_ol_flags_tables();
1127 size = rte_pktmbuf_data_room_size(rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
1128 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
1130 type = RX_PROD_PKT_BD_TYPE_RX_PROD_PKT;
1133 ring = rxr->rx_ring_struct;
1134 bnxt_init_rxbds(ring, type, size);
1136 raw_prod = rxr->rx_raw_prod;
1137 for (i = 0; i < ring->ring_size; i++) {
1138 if (unlikely(!rxr->rx_buf_ring[i])) {
1139 if (bnxt_alloc_rx_data(rxq, rxr, raw_prod) != 0) {
1140 PMD_DRV_LOG(WARNING,
1141 "init'ed rx ring %d with %d/%d mbufs only\n",
1142 rxq->queue_id, i, ring->ring_size);
1146 rxr->rx_raw_prod = raw_prod;
1147 raw_prod = RING_NEXT(raw_prod);
1150 /* Initialize dummy mbuf pointers for vector mode rx. */
1151 for (i = ring->ring_size;
1152 i < ring->ring_size + RTE_BNXT_DESCS_PER_LOOP; i++) {
1153 rxr->rx_buf_ring[i] = &rxq->fake_mbuf;
1156 ring = rxr->ag_ring_struct;
1157 type = RX_PROD_AGG_BD_TYPE_RX_PROD_AGG;
1158 bnxt_init_rxbds(ring, type, size);
1159 raw_prod = rxr->ag_raw_prod;
1161 for (i = 0; i < ring->ring_size; i++) {
1162 if (unlikely(!rxr->ag_buf_ring[i])) {
1163 if (bnxt_alloc_ag_data(rxq, rxr, raw_prod) != 0) {
1164 PMD_DRV_LOG(WARNING,
1165 "init'ed AG ring %d with %d/%d mbufs only\n",
1166 rxq->queue_id, i, ring->ring_size);
1170 rxr->ag_raw_prod = raw_prod;
1171 raw_prod = RING_NEXT(raw_prod);
1173 PMD_DRV_LOG(DEBUG, "AGG Done!\n");
1175 if (rxr->tpa_info) {
1176 unsigned int max_aggs = BNXT_TPA_MAX_AGGS(rxq->bp);
1178 for (i = 0; i < max_aggs; i++) {
1179 if (unlikely(!rxr->tpa_info[i].mbuf)) {
1180 rxr->tpa_info[i].mbuf =
1181 __bnxt_alloc_rx_data(rxq->mb_pool);
1182 if (!rxr->tpa_info[i].mbuf) {
1183 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
1189 PMD_DRV_LOG(DEBUG, "TPA alloc Done!\n");