drivers/net/bnxt/bnxt_rxr.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _BNXT_RXR_H_
   7 #define _BNXT_RXR_H_
   8 #include "hsi_struct_def_dpdk.h"
   9
  10 #define BNXT_TPA_START_AGG_ID_PRE_TH(cmp) \
  11         ((rte_le_to_cpu_16((cmp)->agg_id) & RX_TPA_START_CMPL_AGG_ID_MASK) >> \
  12          RX_TPA_START_CMPL_AGG_ID_SFT)
  13
  14 #define BNXT_TPA_START_AGG_ID_TH(cmp) \
  15         rte_le_to_cpu_16((cmp)->agg_id)
  16
  17 static inline uint16_t bnxt_tpa_start_agg_id(struct bnxt *bp,
  18                                              struct rx_tpa_start_cmpl *cmp)
  19 {
  20         if (BNXT_CHIP_P5(bp))
  21                 return BNXT_TPA_START_AGG_ID_TH(cmp);
  22         else
  23                 return BNXT_TPA_START_AGG_ID_PRE_TH(cmp);
  24 }
  25
  26 #define BNXT_TPA_END_AGG_BUFS(cmp) \
  27         (((cmp)->agg_bufs_v1 & RX_TPA_END_CMPL_AGG_BUFS_MASK) \
  28          >> RX_TPA_END_CMPL_AGG_BUFS_SFT)
  29
  30 #define BNXT_TPA_END_AGG_BUFS_TH(cmp) \
  31         ((cmp)->tpa_agg_bufs)
  32
  33 #define BNXT_TPA_END_AGG_ID(cmp) \
  34         (((cmp)->agg_id & RX_TPA_END_CMPL_AGG_ID_MASK) >> \
  35          RX_TPA_END_CMPL_AGG_ID_SFT)
  36
  37 #define BNXT_TPA_END_AGG_ID_TH(cmp) \
  38         rte_le_to_cpu_16((cmp)->agg_id)
  39
  40 #define BNXT_RX_POST_THRESH     32
  41
  42 /* Number of descriptors to process per inner loop in vector mode. */
  43 #define RTE_BNXT_DESCS_PER_LOOP         4U
  44
  45 #define BNXT_OL_FLAGS_TBL_DIM   64
  46 #define BNXT_OL_FLAGS_ERR_TBL_DIM 32
  47
  48 struct bnxt_tpa_info {
  49         struct rte_mbuf                 *mbuf;
  50         uint16_t                        len;
  51         uint32_t                        agg_count;
  52         struct rx_tpa_v2_abuf_cmpl      agg_arr[TPA_MAX_NUM_SEGS];
  53
  54         uint32_t                        rss_hash;
  55         uint32_t                        vlan;
  56         uint16_t                        cfa_code;
  57         uint8_t                         hash_valid:1;
  58         uint8_t                         vlan_valid:1;
  59         uint8_t                         cfa_code_valid:1;
  60         uint8_t                         l4_csum_valid:1;
  61 };
  62
  63 struct bnxt_rx_ring_info {
  64         uint16_t                rx_raw_prod;
  65         uint16_t                ag_raw_prod;
  66         uint16_t                rx_cons; /* Needed for representor */
  67         struct bnxt_db_info     rx_db;
  68         struct bnxt_db_info     ag_db;
  69
  70         struct rx_prod_pkt_bd   *rx_desc_ring;
  71         struct rx_prod_pkt_bd   *ag_desc_ring;
  72         struct rte_mbuf         **rx_buf_ring; /* sw ring */
  73         struct rte_mbuf         **ag_buf_ring; /* sw ring */
  74
  75         rte_iova_t              rx_desc_mapping;
  76         rte_iova_t              ag_desc_mapping;
  77
  78         struct bnxt_ring        *rx_ring_struct;
  79         struct bnxt_ring        *ag_ring_struct;
  80
  81         /*
  82          * To deal with out of order return from TPA, use free buffer indicator
  83          */
  84         struct rte_bitmap       *ag_bitmap;
  85
  86         struct bnxt_tpa_info *tpa_info;
  87
  88         uint32_t ol_flags_table[BNXT_OL_FLAGS_TBL_DIM];
  89         uint32_t ol_flags_err_table[BNXT_OL_FLAGS_ERR_TBL_DIM];
  90 };
  91
  92 uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  93                                uint16_t nb_pkts);
  94 void bnxt_free_rx_rings(struct bnxt *bp);
  95 int bnxt_init_rx_ring_struct(struct bnxt_rx_queue *rxq, unsigned int socket_id);
  96 int bnxt_init_one_rx_ring(struct bnxt_rx_queue *rxq);
  97 int bnxt_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
  98 int bnxt_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
  99
 100 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
 101 uint16_t bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 102                             uint16_t nb_pkts);
 103 int bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq);
 104 #endif
 105
 106 void bnxt_set_mark_in_mbuf(struct bnxt *bp,
 107                            struct rx_pkt_cmpl_hi *rxcmp1,
 108                            struct rte_mbuf *mbuf);
 109
 110 typedef uint32_t bnxt_cfa_code_dynfield_t;
 111 extern int bnxt_cfa_code_dynfield_offset;
 112
 113 static inline bnxt_cfa_code_dynfield_t *
 114 bnxt_cfa_code_dynfield(struct rte_mbuf *mbuf)
 115 {
 116         return RTE_MBUF_DYNFIELD(mbuf,
 117                 bnxt_cfa_code_dynfield_offset, bnxt_cfa_code_dynfield_t *);
 118 }
 119
 120 #define BNXT_RX_META_CFA_CODE_SHIFT             19
 121 #define BNXT_CFA_CODE_META_SHIFT                16
 122 #define BNXT_RX_META_CFA_CODE_INT_ACT_REC_BIT   0x8000000
 123 #define BNXT_RX_META_CFA_CODE_EEM_BIT           0x4000000
 124 #define BNXT_CFA_META_FMT_MASK                  0x70
 125 #define BNXT_CFA_META_FMT_SHFT                  4
 126 #define BNXT_CFA_META_FMT_EM_EEM_SHFT           1
 127 #define BNXT_CFA_META_FMT_EEM                   3
 128 #define BNXT_CFA_META_EEM_TCAM_SHIFT            31
 129 #define BNXT_CFA_META_EM_TEST(x) ((x) >> BNXT_CFA_META_EEM_TCAM_SHIFT)
 130
 131 #define BNXT_PTYPE_TBL_DIM      128
 132 extern uint32_t bnxt_ptype_table[BNXT_PTYPE_TBL_DIM];
 133
 134 #define RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK       (0x1 << 14)
 135 #endif /*  _BNXT_RXR_H_ */