drivers/net/bnxt/bnxt_rxr.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _BNXT_RXR_H_
   7 #define _BNXT_RXR_H_
   8 #include "hsi_struct_def_dpdk.h"
   9
  10 #define BNXT_TPA_START_AGG_ID_PRE_TH(cmp) \
  11         ((rte_le_to_cpu_16((cmp)->agg_id) & RX_TPA_START_CMPL_AGG_ID_MASK) >> \
  12          RX_TPA_START_CMPL_AGG_ID_SFT)
  13
  14 #define BNXT_TPA_START_AGG_ID_TH(cmp) \
  15         rte_le_to_cpu_16((cmp)->agg_id)
  16
  17 static inline uint16_t bnxt_tpa_start_agg_id(struct bnxt *bp,
  18                                              struct rx_tpa_start_cmpl *cmp)
  19 {
  20         if (BNXT_CHIP_P5(bp))
  21                 return BNXT_TPA_START_AGG_ID_TH(cmp);
  22         else
  23                 return BNXT_TPA_START_AGG_ID_PRE_TH(cmp);
  24 }
  25
  26 #define BNXT_TPA_END_AGG_BUFS(cmp) \
  27         (((cmp)->agg_bufs_v1 & RX_TPA_END_CMPL_AGG_BUFS_MASK) \
  28          >> RX_TPA_END_CMPL_AGG_BUFS_SFT)
  29
  30 #define BNXT_TPA_END_AGG_BUFS_TH(cmp) \
  31         ((cmp)->tpa_agg_bufs)
  32
  33 #define BNXT_TPA_END_AGG_ID(cmp) \
  34         (((cmp)->agg_id & RX_TPA_END_CMPL_AGG_ID_MASK) >> \
  35          RX_TPA_END_CMPL_AGG_ID_SFT)
  36
  37 #define BNXT_TPA_END_AGG_ID_TH(cmp) \
  38         rte_le_to_cpu_16((cmp)->agg_id)
  39
  40 #define BNXT_RX_L2_AGG_BUFS(cmp) \
  41         (((cmp)->agg_bufs_v1 & RX_PKT_CMPL_AGG_BUFS_MASK) >> \
  42                 RX_PKT_CMPL_AGG_BUFS_SFT)
  43
  44 /* Number of descriptors to process per inner loop in vector mode. */
  45 #define BNXT_RX_DESCS_PER_LOOP_VEC128   4U /* SSE, Neon */
  46 #define BNXT_RX_DESCS_PER_LOOP_VEC256   8U /* AVX2 */
  47
  48 /* Number of extra Rx mbuf ring entries to allocate for vector mode. */
  49 #define BNXT_RX_EXTRA_MBUF_ENTRIES \
  50         RTE_MAX(BNXT_RX_DESCS_PER_LOOP_VEC128, BNXT_RX_DESCS_PER_LOOP_VEC256)
  51
  52 #define BNXT_OL_FLAGS_TBL_DIM   64
  53 #define BNXT_OL_FLAGS_ERR_TBL_DIM 32
  54
  55 struct bnxt_tpa_info {
  56         struct rte_mbuf                 *mbuf;
  57         uint16_t                        len;
  58         uint32_t                        agg_count;
  59         struct rx_tpa_v2_abuf_cmpl      agg_arr[TPA_MAX_NUM_SEGS];
  60
  61         uint32_t                        rss_hash;
  62         uint32_t                        vlan;
  63         uint16_t                        cfa_code;
  64         uint8_t                         hash_valid:1;
  65         uint8_t                         vlan_valid:1;
  66         uint8_t                         cfa_code_valid:1;
  67         uint8_t                         l4_csum_valid:1;
  68 };
  69
  70 struct bnxt_rx_ring_info {
  71         uint16_t                rx_raw_prod;
  72         uint16_t                ag_raw_prod;
  73         uint16_t                rx_cons; /* Needed for representor */
  74         struct bnxt_db_info     rx_db;
  75         struct bnxt_db_info     ag_db;
  76
  77         struct rx_prod_pkt_bd   *rx_desc_ring;
  78         struct rx_prod_pkt_bd   *ag_desc_ring;
  79         struct rte_mbuf         **rx_buf_ring; /* sw ring */
  80         struct rte_mbuf         **ag_buf_ring; /* sw ring */
  81
  82         rte_iova_t              rx_desc_mapping;
  83         rte_iova_t              ag_desc_mapping;
  84
  85         struct bnxt_ring        *rx_ring_struct;
  86         struct bnxt_ring        *ag_ring_struct;
  87
  88         /*
  89          * To deal with out of order return from TPA, use free buffer indicator
  90          */
  91         struct rte_bitmap       *ag_bitmap;
  92
  93         struct bnxt_tpa_info *tpa_info;
  94
  95         uint32_t ol_flags_table[BNXT_OL_FLAGS_TBL_DIM];
  96         uint32_t ol_flags_err_table[BNXT_OL_FLAGS_ERR_TBL_DIM];
  97 };
  98
  99 uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 100                                uint16_t nb_pkts);
 101 void bnxt_free_rx_rings(struct bnxt *bp);
 102 int bnxt_init_rx_ring_struct(struct bnxt_rx_queue *rxq, unsigned int socket_id);
 103 int bnxt_init_one_rx_ring(struct bnxt_rx_queue *rxq);
 104 int bnxt_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 105 int bnxt_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 106 int bnxt_flush_rx_cmp(struct bnxt_cp_ring_info *cpr);
 107
 108 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
 109 uint16_t bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 110                             uint16_t nb_pkts);
 111 int bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq);
 112 #endif
 113
 114 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
 115 uint16_t bnxt_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 116                                  uint16_t nb_pkts);
 117 #endif
 118 void bnxt_set_mark_in_mbuf(struct bnxt *bp,
 119                            struct rx_pkt_cmpl_hi *rxcmp1,
 120                            struct rte_mbuf *mbuf);
 121
 122 typedef uint32_t bnxt_cfa_code_dynfield_t;
 123 extern int bnxt_cfa_code_dynfield_offset;
 124
 125 static inline bnxt_cfa_code_dynfield_t *
 126 bnxt_cfa_code_dynfield(struct rte_mbuf *mbuf)
 127 {
 128         return RTE_MBUF_DYNFIELD(mbuf,
 129                 bnxt_cfa_code_dynfield_offset, bnxt_cfa_code_dynfield_t *);
 130 }
 131
 132 #define BNXT_RX_META_CFA_CODE_SHIFT             19
 133 #define BNXT_CFA_CODE_META_SHIFT                16
 134 #define BNXT_RX_META_CFA_CODE_INT_ACT_REC_BIT   0x8000000
 135 #define BNXT_RX_META_CFA_CODE_EEM_BIT           0x4000000
 136 #define BNXT_CFA_META_FMT_MASK                  0x70
 137 #define BNXT_CFA_META_FMT_SHFT                  4
 138 #define BNXT_CFA_META_FMT_EM_EEM_SHFT           1
 139 #define BNXT_CFA_META_FMT_EEM                   3
 140 #define BNXT_CFA_META_EEM_TCAM_SHIFT            31
 141 #define BNXT_CFA_META_EM_TEST(x) ((x) >> BNXT_CFA_META_EEM_TCAM_SHIFT)
 142
 143 /* Definitions for translation of hardware packet type to mbuf ptype. */
 144 #define BNXT_PTYPE_TBL_DIM              128
 145 #define BNXT_PTYPE_TBL_TUN_SFT          0 /* Set if tunneled packet. */
 146 #define BNXT_PTYPE_TBL_TUN_MSK          BIT(BNXT_PTYPE_TBL_TUN_SFT)
 147 #define BNXT_PTYPE_TBL_IP_VER_SFT       1 /* Set if IPv6, clear if IPv4. */
 148 #define BNXT_PTYPE_TBL_IP_VER_MSK       BIT(BNXT_PTYPE_TBL_IP_VER_SFT)
 149 #define BNXT_PTYPE_TBL_VLAN_SFT         2 /* Set if VLAN encapsulated. */
 150 #define BNXT_PTYPE_TBL_VLAN_MSK         BIT(BNXT_PTYPE_TBL_VLAN_SFT)
 151 #define BNXT_PTYPE_TBL_TYPE_SFT         3 /* Hardware packet type field. */
 152 #define BNXT_PTYPE_TBL_TYPE_MSK         0x78 /* Hardware itype field mask. */
 153 #define BNXT_PTYPE_TBL_TYPE_IP          1
 154 #define BNXT_PTYPE_TBL_TYPE_TCP         2
 155 #define BNXT_PTYPE_TBL_TYPE_UDP         3
 156 #define BNXT_PTYPE_TBL_TYPE_ICMP        7
 157
 158 #define RX_PKT_CMPL_FLAGS2_IP_TYPE_SFT  8
 159 #define CMPL_FLAGS2_VLAN_TUN_MSK \
 160         (RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN | RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC)
 161
 162 #define BNXT_CMPL_ITYPE_TO_IDX(ft) \
 163         (((ft) & RX_PKT_CMPL_FLAGS_ITYPE_MASK) >> \
 164           (RX_PKT_CMPL_FLAGS_ITYPE_SFT - BNXT_PTYPE_TBL_TYPE_SFT))
 165
 166 #define BNXT_CMPL_VLAN_TUN_TO_IDX(f2) \
 167         (((f2) & CMPL_FLAGS2_VLAN_TUN_MSK) >> \
 168          (RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT - BNXT_PTYPE_TBL_VLAN_SFT))
 169
 170 #define BNXT_CMPL_IP_VER_TO_IDX(f2) \
 171         (((f2) & RX_PKT_CMPL_FLAGS2_IP_TYPE) >> \
 172          (RX_PKT_CMPL_FLAGS2_IP_TYPE_SFT - BNXT_PTYPE_TBL_IP_VER_SFT))
 173
 174 static inline void
 175 bnxt_check_ptype_constants(void)
 176 {
 177         RTE_BUILD_BUG_ON(BNXT_CMPL_ITYPE_TO_IDX(RX_PKT_CMPL_FLAGS_ITYPE_MASK) !=
 178                          BNXT_PTYPE_TBL_TYPE_MSK);
 179         RTE_BUILD_BUG_ON(BNXT_CMPL_VLAN_TUN_TO_IDX(CMPL_FLAGS2_VLAN_TUN_MSK) !=
 180                          (BNXT_PTYPE_TBL_VLAN_MSK | BNXT_PTYPE_TBL_TUN_MSK));
 181         RTE_BUILD_BUG_ON(BNXT_CMPL_IP_VER_TO_IDX(RX_PKT_CMPL_FLAGS2_IP_TYPE) !=
 182                          BNXT_PTYPE_TBL_IP_VER_MSK);
 183 }
 184
 185 extern uint32_t bnxt_ptype_table[BNXT_PTYPE_TBL_DIM];
 186
 187 /* Stingray2 specific code for RX completion parsing */
 188 #define RX_CMP_VLAN_VALID(rxcmp)        \
 189         (((struct rx_pkt_v2_cmpl *)rxcmp)->metadata1_payload_offset &   \
 190          RX_PKT_V2_CMPL_METADATA1_VALID)
 191
 192 #define RX_CMP_METADATA0_VID(rxcmp1)                            \
 193         ((((struct rx_pkt_v2_cmpl_hi *)rxcmp1)->metadata0) &    \
 194          (RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK |                \
 195           RX_PKT_V2_CMPL_HI_METADATA0_DE  |                     \
 196           RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK))
 197
 198 static inline void bnxt_rx_vlan_v2(struct rte_mbuf *mbuf,
 199                                    struct rx_pkt_cmpl *rxcmp,
 200                                    struct rx_pkt_cmpl_hi *rxcmp1)
 201 {
 202         if (RX_CMP_VLAN_VALID(rxcmp)) {
 203                 mbuf->vlan_tci = RX_CMP_METADATA0_VID(rxcmp1);
 204                 mbuf->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
 205         }
 206 }
 207
 208 #define RX_CMP_FLAGS2_CS_ALL_OK_MODE_MASK       (0x1 << 3)
 209 #define RX_CMP_FLAGS2_CS_OK_HDR_CNT_MASK        (0x7 << 10)
 210 #define RX_CMP_FLAGS2_IP_CSUM_ALL_OK_MASK       (0x1 << 13)
 211 #define RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK       (0x1 << 14)
 212
 213 #define RX_CMP_V2_CS_OK_HDR_CNT(flags)                          \
 214         (((flags) & RX_CMP_FLAGS2_CS_OK_HDR_CNT_MASK) >>        \
 215          RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_SFT)
 216
 217 #define RX_CMP_V2_CS_ALL_OK_MODE(flags)                         \
 218         (((flags) & RX_CMP_FLAGS2_CS_ALL_OK_MODE_MASK))
 219
 220 #define RX_CMP_FLAGS2_L3_CS_OK_MASK             (0x7 << 10)
 221 #define RX_CMP_FLAGS2_L4_CS_OK_MASK             (0x38 << 10)
 222 #define RX_CMP_FLAGS2_L3_CS_OK_SFT              10
 223 #define RX_CMP_FLAGS2_L4_CS_OK_SFT              13
 224
 225 #define RX_CMP_V2_L4_CS_OK(flags2)                      \
 226         (((flags2) & RX_CMP_FLAGS2_L4_CS_OK_MASK) >>    \
 227          RX_CMP_FLAGS2_L4_CS_OK_SFT)
 228
 229 #define RX_CMP_V2_L3_CS_OK(flags2)                      \
 230         (((flags2) & RX_CMP_FLAGS2_L3_CS_OK_MASK) >>    \
 231          RX_CMP_FLAGS2_L3_CS_OK_SFT)
 232
 233 #define RX_CMP_V2_L4_CS_ERR(err)                                \
 234         (((err) & RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK)  ==  \
 235          RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR)
 236
 237 #define RX_CMP_V2_L3_CS_ERR(err)                                \
 238         (((err) & RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK) ==   \
 239          RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR)
 240
 241 #define RX_CMP_V2_T_IP_CS_ERR(err)                              \
 242         (((err) & RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK) == \
 243          RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR)
 244
 245 #define RX_CMP_V2_T_L4_CS_ERR(err)                              \
 246         (((err) & RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK) == \
 247          RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR)
 248
 249 #define RX_CMP_V2_OT_L4_CS_ERR(err)                                     \
 250         (((err) & RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK) ==        \
 251          RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR)
 252
 253 static inline void bnxt_parse_csum_v2(struct rte_mbuf *mbuf,
 254                                       struct rx_pkt_cmpl_hi *rxcmp1)
 255 {
 256         struct rx_pkt_v2_cmpl_hi *v2_cmp =
 257                 (struct rx_pkt_v2_cmpl_hi *)(rxcmp1);
 258         uint16_t error_v2 = rte_le_to_cpu_16(v2_cmp->errors_v2);
 259         uint32_t flags2 = rte_le_to_cpu_32(v2_cmp->flags2);
 260         uint32_t hdr_cnt = 0, t_pkt = 0;
 261
 262         if (RX_CMP_V2_CS_ALL_OK_MODE(flags2)) {
 263                 hdr_cnt = RX_CMP_V2_CS_OK_HDR_CNT(flags2);
 264                 if (hdr_cnt > 1)
 265                         t_pkt = 1;
 266
 267                 if (unlikely(RX_CMP_V2_L4_CS_ERR(error_v2)))
 268                         mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
 269                 else if (flags2 & RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK)
 270                         mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
 271                 else
 272                         mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 273
 274                 if (unlikely(RX_CMP_V2_L3_CS_ERR(error_v2)))
 275                         mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
 276                 else if (flags2 & RX_CMP_FLAGS2_IP_CSUM_ALL_OK_MASK)
 277                         mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
 278                 else
 279                         mbuf->ol_flags |= PKT_RX_IP_CKSUM_UNKNOWN;
 280         } else {
 281                 hdr_cnt = RX_CMP_V2_L4_CS_OK(flags2);
 282                 if (hdr_cnt > 1)
 283                         t_pkt = 1;
 284
 285                 if (RX_CMP_V2_L4_CS_OK(flags2))
 286                         mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
 287                 else if (RX_CMP_V2_L4_CS_ERR(error_v2))
 288                         mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
 289                 else
 290                         mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 291
 292                 if (RX_CMP_V2_L3_CS_OK(flags2))
 293                         mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
 294                 else if (RX_CMP_V2_L3_CS_ERR(error_v2))
 295                         mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
 296                 else
 297                         mbuf->ol_flags |= PKT_RX_IP_CKSUM_UNKNOWN;
 298         }
 299
 300         if (t_pkt) {
 301                 if (unlikely(RX_CMP_V2_OT_L4_CS_ERR(error_v2) ||
 302                                         RX_CMP_V2_T_L4_CS_ERR(error_v2)))
 303                         mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
 304                 else
 305                         mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
 306
 307                 if (unlikely(RX_CMP_V2_T_IP_CS_ERR(error_v2)))
 308                         mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
 309         }
 310 }
 311
 312 static inline void
 313 bnxt_parse_pkt_type_v2(struct rte_mbuf *mbuf,
 314                        struct rx_pkt_cmpl *rxcmp,
 315                        struct rx_pkt_cmpl_hi *rxcmp1)
 316 {
 317         struct rx_pkt_v2_cmpl *v2_cmp =
 318                 (struct rx_pkt_v2_cmpl *)(rxcmp);
 319         struct rx_pkt_v2_cmpl_hi *v2_cmp1 =
 320                 (struct rx_pkt_v2_cmpl_hi *)(rxcmp1);
 321         uint16_t flags_type = v2_cmp->flags_type &
 322                 rte_cpu_to_le_32(RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK);
 323         uint32_t flags2 = rte_le_to_cpu_32(v2_cmp1->flags2);
 324         uint32_t l3, pkt_type = 0, vlan = 0;
 325         uint32_t ip6 = 0, t_pkt = 0;
 326         uint32_t hdr_cnt, csum_count;
 327
 328         if (RX_CMP_V2_CS_ALL_OK_MODE(flags2)) {
 329                 hdr_cnt = RX_CMP_V2_CS_OK_HDR_CNT(flags2);
 330                 if (hdr_cnt > 1)
 331                         t_pkt = 1;
 332         } else {
 333                 csum_count = RX_CMP_V2_L4_CS_OK(flags2);
 334                 if (csum_count > 1)
 335                         t_pkt = 1;
 336         }
 337
 338         vlan = !!RX_CMP_VLAN_VALID(rxcmp);
 339         pkt_type |= vlan ? RTE_PTYPE_L2_ETHER_VLAN : RTE_PTYPE_L2_ETHER;
 340
 341         ip6 = !!(flags2 & RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE);
 342
 343         if (!t_pkt && !ip6)
 344                 l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
 345         else if (!t_pkt && ip6)
 346                 l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
 347         else if (t_pkt && !ip6)
 348                 l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
 349         else
 350                 l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
 351
 352         switch (flags_type) {
 353         case RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP):
 354                 if (!t_pkt)
 355                         pkt_type |= l3 | RTE_PTYPE_L4_ICMP;
 356                 else
 357                         pkt_type |= l3 | RTE_PTYPE_INNER_L4_ICMP;
 358                 break;
 359         case RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP):
 360                 if (!t_pkt)
 361                         pkt_type |= l3 | RTE_PTYPE_L4_TCP;
 362                 else
 363                         pkt_type |= l3 | RTE_PTYPE_INNER_L4_TCP;
 364                 break;
 365         case RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP):
 366                 if (!t_pkt)
 367                         pkt_type |= l3 | RTE_PTYPE_L4_UDP;
 368                 else
 369                         pkt_type |= l3 | RTE_PTYPE_INNER_L4_UDP;
 370                 break;
 371         case RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_IP):
 372                 pkt_type |= l3;
 373                 break;
 374         }
 375
 376         mbuf->packet_type = pkt_type;
 377 }
 378
 379 #endif /*  _BNXT_RXR_H_ */