1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2021 Broadcom
8 #include "hsi_struct_def_dpdk.h"
10 #define BNXT_TPA_START_AGG_ID_PRE_TH(cmp) \
11 ((rte_le_to_cpu_16((cmp)->agg_id) & RX_TPA_START_CMPL_AGG_ID_MASK) >> \
12 RX_TPA_START_CMPL_AGG_ID_SFT)
14 #define BNXT_TPA_START_AGG_ID_TH(cmp) \
15 rte_le_to_cpu_16((cmp)->agg_id)
17 static inline uint16_t bnxt_tpa_start_agg_id(struct bnxt *bp,
18 struct rx_tpa_start_cmpl *cmp)
21 return BNXT_TPA_START_AGG_ID_TH(cmp);
23 return BNXT_TPA_START_AGG_ID_PRE_TH(cmp);
26 #define BNXT_TPA_END_AGG_BUFS(cmp) \
27 (((cmp)->agg_bufs_v1 & RX_TPA_END_CMPL_AGG_BUFS_MASK) \
28 >> RX_TPA_END_CMPL_AGG_BUFS_SFT)
30 #define BNXT_TPA_END_AGG_BUFS_TH(cmp) \
33 #define BNXT_TPA_END_AGG_ID(cmp) \
34 (((cmp)->agg_id & RX_TPA_END_CMPL_AGG_ID_MASK) >> \
35 RX_TPA_END_CMPL_AGG_ID_SFT)
37 #define BNXT_TPA_END_AGG_ID_TH(cmp) \
38 rte_le_to_cpu_16((cmp)->agg_id)
40 #define BNXT_RX_L2_AGG_BUFS(cmp) \
41 (((cmp)->agg_bufs_v1 & RX_PKT_CMPL_AGG_BUFS_MASK) >> \
42 RX_PKT_CMPL_AGG_BUFS_SFT)
44 #define BNXT_RX_POST_THRESH 32
46 /* Number of descriptors to process per inner loop in vector mode. */
47 #define RTE_BNXT_DESCS_PER_LOOP 4U
49 #define BNXT_OL_FLAGS_TBL_DIM 64
50 #define BNXT_OL_FLAGS_ERR_TBL_DIM 32
52 struct bnxt_tpa_info {
53 struct rte_mbuf *mbuf;
56 struct rx_tpa_v2_abuf_cmpl agg_arr[TPA_MAX_NUM_SEGS];
63 uint8_t cfa_code_valid:1;
64 uint8_t l4_csum_valid:1;
67 struct bnxt_rx_ring_info {
70 uint16_t rx_cons; /* Needed for representor */
71 struct bnxt_db_info rx_db;
72 struct bnxt_db_info ag_db;
74 struct rx_prod_pkt_bd *rx_desc_ring;
75 struct rx_prod_pkt_bd *ag_desc_ring;
76 struct rte_mbuf **rx_buf_ring; /* sw ring */
77 struct rte_mbuf **ag_buf_ring; /* sw ring */
79 rte_iova_t rx_desc_mapping;
80 rte_iova_t ag_desc_mapping;
82 struct bnxt_ring *rx_ring_struct;
83 struct bnxt_ring *ag_ring_struct;
86 * To deal with out of order return from TPA, use free buffer indicator
88 struct rte_bitmap *ag_bitmap;
90 struct bnxt_tpa_info *tpa_info;
92 uint32_t ol_flags_table[BNXT_OL_FLAGS_TBL_DIM];
93 uint32_t ol_flags_err_table[BNXT_OL_FLAGS_ERR_TBL_DIM];
96 uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
98 void bnxt_free_rx_rings(struct bnxt *bp);
99 int bnxt_init_rx_ring_struct(struct bnxt_rx_queue *rxq, unsigned int socket_id);
100 int bnxt_init_one_rx_ring(struct bnxt_rx_queue *rxq);
101 int bnxt_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
102 int bnxt_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
104 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
105 uint16_t bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
107 int bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq);
110 void bnxt_set_mark_in_mbuf(struct bnxt *bp,
111 struct rx_pkt_cmpl_hi *rxcmp1,
112 struct rte_mbuf *mbuf);
114 typedef uint32_t bnxt_cfa_code_dynfield_t;
115 extern int bnxt_cfa_code_dynfield_offset;
117 static inline bnxt_cfa_code_dynfield_t *
118 bnxt_cfa_code_dynfield(struct rte_mbuf *mbuf)
120 return RTE_MBUF_DYNFIELD(mbuf,
121 bnxt_cfa_code_dynfield_offset, bnxt_cfa_code_dynfield_t *);
124 #define BNXT_RX_META_CFA_CODE_SHIFT 19
125 #define BNXT_CFA_CODE_META_SHIFT 16
126 #define BNXT_RX_META_CFA_CODE_INT_ACT_REC_BIT 0x8000000
127 #define BNXT_RX_META_CFA_CODE_EEM_BIT 0x4000000
128 #define BNXT_CFA_META_FMT_MASK 0x70
129 #define BNXT_CFA_META_FMT_SHFT 4
130 #define BNXT_CFA_META_FMT_EM_EEM_SHFT 1
131 #define BNXT_CFA_META_FMT_EEM 3
132 #define BNXT_CFA_META_EEM_TCAM_SHIFT 31
133 #define BNXT_CFA_META_EM_TEST(x) ((x) >> BNXT_CFA_META_EEM_TCAM_SHIFT)
135 #define BNXT_PTYPE_TBL_DIM 128
136 extern uint32_t bnxt_ptype_table[BNXT_PTYPE_TBL_DIM];
138 /* Stingray2 specific code for RX completion parsing */
139 #define RX_CMP_VLAN_VALID(rxcmp) \
140 (((struct rx_pkt_v2_cmpl *)rxcmp)->metadata1_payload_offset & \
141 RX_PKT_V2_CMPL_METADATA1_VALID)
143 #define RX_CMP_METADATA0_VID(rxcmp1) \
144 ((((struct rx_pkt_v2_cmpl_hi *)rxcmp1)->metadata0) & \
145 (RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK | \
146 RX_PKT_V2_CMPL_HI_METADATA0_DE | \
147 RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK))
149 static inline void bnxt_rx_vlan_v2(struct rte_mbuf *mbuf,
150 struct rx_pkt_cmpl *rxcmp,
151 struct rx_pkt_cmpl_hi *rxcmp1)
153 if (RX_CMP_VLAN_VALID(rxcmp)) {
154 mbuf->vlan_tci = RX_CMP_METADATA0_VID(rxcmp1);
155 mbuf->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
159 #define RX_CMP_FLAGS2_CS_ALL_OK_MODE_MASK (0x1 << 3)
160 #define RX_CMP_FLAGS2_CS_OK_HDR_CNT_MASK (0x7 << 10)
161 #define RX_CMP_FLAGS2_IP_CSUM_ALL_OK_MASK (0x1 << 13)
162 #define RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK (0x1 << 14)
164 #define RX_CMP_V2_CS_OK_HDR_CNT(flags) \
165 (((flags) & RX_CMP_FLAGS2_CS_OK_HDR_CNT_MASK) >> \
166 RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_SFT)
168 #define RX_CMP_V2_CS_ALL_OK_MODE(flags) \
169 (((flags) & RX_CMP_FLAGS2_CS_ALL_OK_MODE_MASK))
171 #define RX_CMP_FLAGS2_L3_CS_OK_MASK (0x7 << 10)
172 #define RX_CMP_FLAGS2_L4_CS_OK_MASK (0x38 << 10)
173 #define RX_CMP_FLAGS2_L3_CS_OK_SFT 10
174 #define RX_CMP_FLAGS2_L4_CS_OK_SFT 13
176 #define RX_CMP_V2_L4_CS_OK(flags2) \
177 (((flags2) & RX_CMP_FLAGS2_L4_CS_OK_MASK) >> \
178 RX_CMP_FLAGS2_L4_CS_OK_SFT)
180 #define RX_CMP_V2_L3_CS_OK(flags2) \
181 (((flags2) & RX_CMP_FLAGS2_L3_CS_OK_MASK) >> \
182 RX_CMP_FLAGS2_L3_CS_OK_SFT)
184 #define RX_CMP_V2_L4_CS_ERR(err) \
185 (((err) & RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK) == \
186 RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR)
188 #define RX_CMP_V2_L3_CS_ERR(err) \
189 (((err) & RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK) == \
190 RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR)
192 #define RX_CMP_V2_T_IP_CS_ERR(err) \
193 (((err) & RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK) == \
194 RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR)
196 #define RX_CMP_V2_T_L4_CS_ERR(err) \
197 (((err) & RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK) == \
198 RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR)
200 #define RX_CMP_V2_OT_L4_CS_ERR(err) \
201 (((err) & RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK) == \
202 RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR)
204 static inline void bnxt_parse_csum_v2(struct rte_mbuf *mbuf,
205 struct rx_pkt_cmpl_hi *rxcmp1)
207 struct rx_pkt_v2_cmpl_hi *v2_cmp =
208 (struct rx_pkt_v2_cmpl_hi *)(rxcmp1);
209 uint16_t error_v2 = rte_le_to_cpu_16(v2_cmp->errors_v2);
210 uint32_t flags2 = rte_le_to_cpu_32(v2_cmp->flags2);
211 uint32_t hdr_cnt = 0, t_pkt = 0;
213 if (RX_CMP_V2_CS_ALL_OK_MODE(flags2)) {
214 hdr_cnt = RX_CMP_V2_CS_OK_HDR_CNT(flags2);
218 if (unlikely(RX_CMP_V2_L4_CS_ERR(error_v2)))
219 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
220 else if (flags2 & RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK)
221 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
223 mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
225 if (unlikely(RX_CMP_V2_L3_CS_ERR(error_v2)))
226 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
227 else if (flags2 & RX_CMP_FLAGS2_IP_CSUM_ALL_OK_MASK)
228 mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
230 mbuf->ol_flags |= PKT_RX_IP_CKSUM_UNKNOWN;
232 hdr_cnt = RX_CMP_V2_L4_CS_OK(flags2);
236 if (RX_CMP_V2_L4_CS_OK(flags2))
237 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
238 else if (RX_CMP_V2_L4_CS_ERR(error_v2))
239 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
241 mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
243 if (RX_CMP_V2_L3_CS_OK(flags2))
244 mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
245 else if (RX_CMP_V2_L3_CS_ERR(error_v2))
246 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
248 mbuf->ol_flags |= PKT_RX_IP_CKSUM_UNKNOWN;
252 if (unlikely(RX_CMP_V2_OT_L4_CS_ERR(error_v2) ||
253 RX_CMP_V2_T_L4_CS_ERR(error_v2)))
254 mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
256 mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
258 if (unlikely(RX_CMP_V2_T_IP_CS_ERR(error_v2)))
259 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
264 bnxt_parse_pkt_type_v2(struct rte_mbuf *mbuf,
265 struct rx_pkt_cmpl *rxcmp,
266 struct rx_pkt_cmpl_hi *rxcmp1)
268 struct rx_pkt_v2_cmpl *v2_cmp =
269 (struct rx_pkt_v2_cmpl *)(rxcmp);
270 struct rx_pkt_v2_cmpl_hi *v2_cmp1 =
271 (struct rx_pkt_v2_cmpl_hi *)(rxcmp1);
272 uint16_t flags_type = v2_cmp->flags_type &
273 rte_cpu_to_le_32(RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK);
274 uint32_t flags2 = rte_le_to_cpu_32(v2_cmp1->flags2);
275 uint32_t l3, pkt_type = 0, vlan = 0;
276 uint32_t ip6 = 0, t_pkt = 0;
277 uint32_t hdr_cnt, csum_count;
279 if (RX_CMP_V2_CS_ALL_OK_MODE(flags2)) {
280 hdr_cnt = RX_CMP_V2_CS_OK_HDR_CNT(flags2);
284 csum_count = RX_CMP_V2_L4_CS_OK(flags2);
289 vlan = !!RX_CMP_VLAN_VALID(rxcmp);
290 pkt_type |= vlan ? RTE_PTYPE_L2_ETHER_VLAN : RTE_PTYPE_L2_ETHER;
292 ip6 = !!(flags2 & RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE);
295 l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
296 else if (!t_pkt && ip6)
297 l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
298 else if (t_pkt && !ip6)
299 l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
301 l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
303 switch (flags_type) {
304 case RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP):
306 pkt_type |= l3 | RTE_PTYPE_L4_ICMP;
308 pkt_type |= l3 | RTE_PTYPE_INNER_L4_ICMP;
310 case RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP):
312 pkt_type |= l3 | RTE_PTYPE_L4_TCP;
314 pkt_type |= l3 | RTE_PTYPE_INNER_L4_TCP;
316 case RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP):
318 pkt_type |= l3 | RTE_PTYPE_L4_UDP;
320 pkt_type |= l3 | RTE_PTYPE_INNER_L4_UDP;
322 case RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_IP):
327 mbuf->packet_type = pkt_type;
330 #endif /* _BNXT_RXR_H_ */