1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2019-2021 Broadcom All rights reserved. */
7 #include <rte_bitmap.h>
8 #include <rte_byteorder.h>
9 #include <rte_malloc.h>
10 #include <rte_memory.h>
15 #include "bnxt_ring.h"
19 #include "bnxt_rxtx_vec_common.h"
23 recv_burst_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
25 struct bnxt_rx_queue *rxq = rx_queue;
26 const __m256i mbuf_init =
27 _mm256_set_epi64x(0, 0, 0, rxq->mbuf_initializer);
28 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
29 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
30 uint16_t cp_ring_size = cpr->cp_ring_struct->ring_size;
31 uint16_t rx_ring_size = rxr->rx_ring_struct->ring_size;
32 struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
33 uint64_t valid, desc_valid_mask = ~0ULL;
34 const __m256i info3_v_mask = _mm256_set1_epi32(CMPL_BASE_V);
35 uint32_t raw_cons = cpr->cp_raw_cons;
36 uint32_t cons, mbcons;
39 const __m256i valid_target =
40 _mm256_set1_epi32(!!(raw_cons & cp_ring_size));
41 const __m256i dsc_shuf_msk =
42 _mm256_set_epi8(0xff, 0xff, 0xff, 0xff, /* Zeroes. */
43 7, 6, /* metadata type */
44 9, 8, /* flags2 low 16 */
47 0xff, 0xff, 0xff, 0xff, /* Zeroes. */
48 0xff, 0xff, 0xff, 0xff, /* Zeroes. */
49 7, 6, /* metadata type */
50 9, 8, /* flags2 low 16 */
53 0xff, 0xff, 0xff, 0xff); /* Zeroes. */
54 const __m256i shuf_msk =
55 _mm256_set_epi8(15, 14, 13, 12, /* rss */
58 0xFF, 0xFF, 3, 2, /* pkt_len */
59 0xFF, 0xFF, 0xFF, 0xFF, /* pkt_type (zeroes) */
60 15, 14, 13, 12, /* rss */
63 0xFF, 0xFF, 3, 2, /* pkt_len */
64 0xFF, 0xFF, 0xFF, 0xFF); /* pkt_type (zeroes) */
65 const __m256i flags_type_mask =
66 _mm256_set1_epi32(RX_PKT_CMPL_FLAGS_ITYPE_MASK);
67 const __m256i flags2_mask1 =
68 _mm256_set1_epi32(CMPL_FLAGS2_VLAN_TUN_MSK);
69 const __m256i flags2_mask2 =
70 _mm256_set1_epi32(RX_PKT_CMPL_FLAGS2_IP_TYPE);
71 const __m256i rss_mask =
72 _mm256_set1_epi32(RX_PKT_CMPL_FLAGS_RSS_VALID);
73 __m256i t0, t1, flags_type, flags2, index, errors;
74 __m256i ptype_idx, ptypes, is_tunnel;
75 __m256i mbuf01, mbuf23, mbuf45, mbuf67;
76 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5, rearm6, rearm7;
77 __m256i ol_flags, ol_flags_hi;
80 /* Validate ptype table indexing at build time. */
81 bnxt_check_ptype_constants();
83 /* If Rx Q was stopped return */
84 if (unlikely(!rxq->rx_started))
87 if (rxq->rxrearm_nb >= rxq->rx_free_thresh)
88 bnxt_rxq_rearm(rxq, rxr);
90 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, BNXT_RX_DESCS_PER_LOOP_VEC256);
92 cons = raw_cons & (cp_ring_size - 1);
93 mbcons = (raw_cons / 2) & (rx_ring_size - 1);
95 /* Return immediately if there is not at least one completed packet. */
96 if (!bnxt_cpr_cmp_valid(&cp_desc_ring[cons], raw_cons, cp_ring_size))
99 /* Ensure that we do not go past the ends of the rings. */
100 nb_pkts = RTE_MIN(nb_pkts, RTE_MIN(rx_ring_size - mbcons,
101 (cp_ring_size - cons) / 2));
103 * If we are at the end of the ring, ensure that descriptors after the
104 * last valid entry are not treated as valid. Otherwise, force the
105 * maximum number of packets to receive to be a multiple of the per-
108 if (nb_pkts < BNXT_RX_DESCS_PER_LOOP_VEC256) {
110 CHAR_BIT * (BNXT_RX_DESCS_PER_LOOP_VEC256 - nb_pkts);
113 RTE_ALIGN_FLOOR(nb_pkts, BNXT_RX_DESCS_PER_LOOP_VEC256);
116 /* Handle RX burst request */
117 for (i = 0; i < nb_pkts; i += BNXT_RX_DESCS_PER_LOOP_VEC256,
118 cons += BNXT_RX_DESCS_PER_LOOP_VEC256 * 2,
119 mbcons += BNXT_RX_DESCS_PER_LOOP_VEC256) {
120 __m256i desc0, desc1, desc2, desc3, desc4, desc5, desc6, desc7;
121 __m256i rxcmp0_1, rxcmp2_3, rxcmp4_5, rxcmp6_7, info3_v;
125 /* Copy eight mbuf pointers to output array. */
126 t0 = _mm256_loadu_si256((void *)&rxr->rx_buf_ring[mbcons]);
127 _mm256_storeu_si256((void *)&rx_pkts[i], t0);
128 #ifdef RTE_ARCH_X86_64
129 t0 = _mm256_loadu_si256((void *)&rxr->rx_buf_ring[mbcons + 4]);
130 _mm256_storeu_si256((void *)&rx_pkts[i + 4], t0);
134 * Load eight receive completion descriptors into 256-bit
135 * registers. Loads are issued in reverse order in order to
136 * ensure consistent state.
138 desc7 = _mm256_load_si256((void *)&cp_desc_ring[cons + 14]);
139 rte_compiler_barrier();
140 desc6 = _mm256_load_si256((void *)&cp_desc_ring[cons + 12]);
141 rte_compiler_barrier();
142 desc5 = _mm256_load_si256((void *)&cp_desc_ring[cons + 10]);
143 rte_compiler_barrier();
144 desc4 = _mm256_load_si256((void *)&cp_desc_ring[cons + 8]);
145 rte_compiler_barrier();
146 desc3 = _mm256_load_si256((void *)&cp_desc_ring[cons + 6]);
147 rte_compiler_barrier();
148 desc2 = _mm256_load_si256((void *)&cp_desc_ring[cons + 4]);
149 rte_compiler_barrier();
150 desc1 = _mm256_load_si256((void *)&cp_desc_ring[cons + 2]);
151 rte_compiler_barrier();
152 desc0 = _mm256_load_si256((void *)&cp_desc_ring[cons + 0]);
155 * Pack needed fields from each descriptor into a compressed
156 * 128-bit layout and pair two compressed descriptors into
157 * 256-bit registers. The 128-bit compressed layout is as
159 * Bits 0-15: flags_type field from low completion record.
160 * Bits 16-31: len field from low completion record.
161 * Bits 32-47: flags2 (low 16 bits) from high completion.
162 * Bits 48-79: metadata from high completion record.
163 * Bits 80-95: errors_v2 from high completion record.
164 * Bits 96-127: rss hash from low completion record.
166 t0 = _mm256_permute2f128_si256(desc6, desc7, 0x20);
167 t1 = _mm256_permute2f128_si256(desc6, desc7, 0x31);
168 t1 = _mm256_shuffle_epi8(t1, dsc_shuf_msk);
169 rxcmp6_7 = _mm256_blend_epi32(t0, t1, 0x66);
171 t0 = _mm256_permute2f128_si256(desc4, desc5, 0x20);
172 t1 = _mm256_permute2f128_si256(desc4, desc5, 0x31);
173 t1 = _mm256_shuffle_epi8(t1, dsc_shuf_msk);
174 rxcmp4_5 = _mm256_blend_epi32(t0, t1, 0x66);
176 t0 = _mm256_permute2f128_si256(desc2, desc3, 0x20);
177 t1 = _mm256_permute2f128_si256(desc2, desc3, 0x31);
178 t1 = _mm256_shuffle_epi8(t1, dsc_shuf_msk);
179 rxcmp2_3 = _mm256_blend_epi32(t0, t1, 0x66);
181 t0 = _mm256_permute2f128_si256(desc0, desc1, 0x20);
182 t1 = _mm256_permute2f128_si256(desc0, desc1, 0x31);
183 t1 = _mm256_shuffle_epi8(t1, dsc_shuf_msk);
184 rxcmp0_1 = _mm256_blend_epi32(t0, t1, 0x66);
186 /* Compute packet type table indices for eight packets. */
187 t0 = _mm256_unpacklo_epi32(rxcmp0_1, rxcmp2_3);
188 t1 = _mm256_unpacklo_epi32(rxcmp4_5, rxcmp6_7);
189 flags_type = _mm256_unpacklo_epi64(t0, t1);
190 ptype_idx = _mm256_and_si256(flags_type, flags_type_mask);
191 ptype_idx = _mm256_srli_epi32(ptype_idx,
192 RX_PKT_CMPL_FLAGS_ITYPE_SFT -
193 BNXT_PTYPE_TBL_TYPE_SFT);
195 t0 = _mm256_unpacklo_epi32(rxcmp0_1, rxcmp2_3);
196 t1 = _mm256_unpacklo_epi32(rxcmp4_5, rxcmp6_7);
197 flags2 = _mm256_unpackhi_epi64(t0, t1);
199 t0 = _mm256_srli_epi32(_mm256_and_si256(flags2, flags2_mask1),
200 RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT -
201 BNXT_PTYPE_TBL_VLAN_SFT);
202 ptype_idx = _mm256_or_si256(ptype_idx, t0);
204 t0 = _mm256_srli_epi32(_mm256_and_si256(flags2, flags2_mask2),
205 RX_PKT_CMPL_FLAGS2_IP_TYPE_SFT -
206 BNXT_PTYPE_TBL_IP_VER_SFT);
207 ptype_idx = _mm256_or_si256(ptype_idx, t0);
210 * Load ptypes for eight packets using gather. Gather operations
211 * have extremely high latency (~19 cycles), execution and use
212 * of result should be separated as much as possible.
214 ptypes = _mm256_i32gather_epi32((int *)bnxt_ptype_table,
215 ptype_idx, sizeof(uint32_t));
217 * Compute ol_flags and checksum error table indices for eight
220 is_tunnel = _mm256_and_si256(flags2, _mm256_set1_epi32(4));
221 is_tunnel = _mm256_slli_epi32(is_tunnel, 3);
222 flags2 = _mm256_and_si256(flags2, _mm256_set1_epi32(0x1F));
224 /* Extract errors_v2 fields for eight packets. */
225 t0 = _mm256_unpackhi_epi32(rxcmp0_1, rxcmp2_3);
226 t1 = _mm256_unpackhi_epi32(rxcmp4_5, rxcmp6_7);
227 errors_v2 = _mm256_unpacklo_epi64(t0, t1);
229 errors = _mm256_srli_epi32(errors_v2, 4);
230 errors = _mm256_and_si256(errors, _mm256_set1_epi32(0xF));
231 errors = _mm256_and_si256(errors, flags2);
233 index = _mm256_andnot_si256(errors, flags2);
234 errors = _mm256_or_si256(errors,
235 _mm256_srli_epi32(is_tunnel, 1));
236 index = _mm256_or_si256(index, is_tunnel);
239 * Load ol_flags for eight packets using gather. Gather
240 * operations have extremely high latency (~19 cycles),
241 * execution and use of result should be separated as much
244 ol_flags = _mm256_i32gather_epi32((int *)rxr->ol_flags_table,
245 index, sizeof(uint32_t));
246 errors = _mm256_i32gather_epi32((int *)rxr->ol_flags_err_table,
247 errors, sizeof(uint32_t));
250 * Pack the 128-bit array of valid descriptor flags into 64
251 * bits and count the number of set bits in order to determine
252 * the number of valid descriptors.
254 const __m256i perm_msk =
255 _mm256_set_epi32(7, 3, 6, 2, 5, 1, 4, 0);
256 info3_v = _mm256_permutevar8x32_epi32(errors_v2, perm_msk);
257 info3_v = _mm256_and_si256(errors_v2, info3_v_mask);
258 info3_v = _mm256_xor_si256(info3_v, valid_target);
260 info3_v = _mm256_packs_epi32(info3_v, _mm256_setzero_si256());
261 valid = _mm_cvtsi128_si64(_mm256_extracti128_si256(info3_v, 1));
262 valid = (valid << CHAR_BIT) |
263 _mm_cvtsi128_si64(_mm256_castsi256_si128(info3_v));
264 num_valid = __builtin_popcountll(valid & desc_valid_mask);
269 /* Update mbuf rearm_data for eight packets. */
270 mbuf01 = _mm256_shuffle_epi8(rxcmp0_1, shuf_msk);
271 mbuf23 = _mm256_shuffle_epi8(rxcmp2_3, shuf_msk);
272 mbuf45 = _mm256_shuffle_epi8(rxcmp4_5, shuf_msk);
273 mbuf67 = _mm256_shuffle_epi8(rxcmp6_7, shuf_msk);
275 /* Blend in ptype field for two mbufs at a time. */
276 mbuf01 = _mm256_blend_epi32(mbuf01, ptypes, 0x11);
277 mbuf23 = _mm256_blend_epi32(mbuf23,
278 _mm256_srli_si256(ptypes, 4), 0x11);
279 mbuf45 = _mm256_blend_epi32(mbuf45,
280 _mm256_srli_si256(ptypes, 8), 0x11);
281 mbuf67 = _mm256_blend_epi32(mbuf67,
282 _mm256_srli_si256(ptypes, 12), 0x11);
284 /* Unpack rearm data, set fixed fields for first four mbufs. */
285 rearm0 = _mm256_permute2f128_si256(mbuf_init, mbuf01, 0x20);
286 rearm1 = _mm256_blend_epi32(mbuf_init, mbuf01, 0xF0);
287 rearm2 = _mm256_permute2f128_si256(mbuf_init, mbuf23, 0x20);
288 rearm3 = _mm256_blend_epi32(mbuf_init, mbuf23, 0xF0);
290 /* Compute final ol_flags values for eight packets. */
291 rss_flags = _mm256_and_si256(flags_type, rss_mask);
292 rss_flags = _mm256_srli_epi32(rss_flags, 9);
293 ol_flags = _mm256_or_si256(ol_flags, errors);
294 ol_flags = _mm256_or_si256(ol_flags, rss_flags);
295 ol_flags_hi = _mm256_permute2f128_si256(ol_flags,
298 /* Set ol_flags fields for first four packets. */
299 rearm0 = _mm256_blend_epi32(rearm0,
300 _mm256_slli_si256(ol_flags, 8),
302 rearm1 = _mm256_blend_epi32(rearm1,
303 _mm256_slli_si256(ol_flags_hi, 8),
305 rearm2 = _mm256_blend_epi32(rearm2,
306 _mm256_slli_si256(ol_flags, 4),
308 rearm3 = _mm256_blend_epi32(rearm3,
309 _mm256_slli_si256(ol_flags_hi, 4),
312 /* Store all mbuf fields for first four packets. */
313 _mm256_storeu_si256((void *)&rx_pkts[i + 0]->rearm_data,
315 _mm256_storeu_si256((void *)&rx_pkts[i + 1]->rearm_data,
317 _mm256_storeu_si256((void *)&rx_pkts[i + 2]->rearm_data,
319 _mm256_storeu_si256((void *)&rx_pkts[i + 3]->rearm_data,
322 /* Unpack rearm data, set fixed fields for final four mbufs. */
323 rearm4 = _mm256_permute2f128_si256(mbuf_init, mbuf45, 0x20);
324 rearm5 = _mm256_blend_epi32(mbuf_init, mbuf45, 0xF0);
325 rearm6 = _mm256_permute2f128_si256(mbuf_init, mbuf67, 0x20);
326 rearm7 = _mm256_blend_epi32(mbuf_init, mbuf67, 0xF0);
328 /* Set ol_flags fields for final four packets. */
329 rearm4 = _mm256_blend_epi32(rearm4, ol_flags, 0x04);
330 rearm5 = _mm256_blend_epi32(rearm5, ol_flags_hi, 0x04);
331 rearm6 = _mm256_blend_epi32(rearm6,
332 _mm256_srli_si256(ol_flags, 4),
334 rearm7 = _mm256_blend_epi32(rearm7,
335 _mm256_srli_si256(ol_flags_hi, 4),
338 /* Store all mbuf fields for final four packets. */
339 _mm256_storeu_si256((void *)&rx_pkts[i + 4]->rearm_data,
341 _mm256_storeu_si256((void *)&rx_pkts[i + 5]->rearm_data,
343 _mm256_storeu_si256((void *)&rx_pkts[i + 6]->rearm_data,
345 _mm256_storeu_si256((void *)&rx_pkts[i + 7]->rearm_data,
348 nb_rx_pkts += num_valid;
349 if (num_valid < BNXT_RX_DESCS_PER_LOOP_VEC256)
354 rxr->rx_raw_prod = RING_ADV(rxr->rx_raw_prod, nb_rx_pkts);
356 rxq->rxrearm_nb += nb_rx_pkts;
357 cpr->cp_raw_cons += 2 * nb_rx_pkts;
365 bnxt_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
370 while (nb_pkts > RTE_BNXT_MAX_RX_BURST) {
373 burst = recv_burst_vec_avx2(rx_queue, rx_pkts + cnt,
374 RTE_BNXT_MAX_RX_BURST);
379 if (burst < RTE_BNXT_MAX_RX_BURST)
382 return cnt + recv_burst_vec_avx2(rx_queue, rx_pkts + cnt, nb_pkts);
386 bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
388 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
389 uint32_t raw_cons = cpr->cp_raw_cons;
391 uint32_t nb_tx_pkts = 0;
392 struct tx_cmpl *txcmp;
393 struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
394 struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
395 uint32_t ring_mask = cp_ring_struct->ring_mask;
398 cons = RING_CMPL(ring_mask, raw_cons);
399 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
401 if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1))
404 nb_tx_pkts += txcmp->opaque;
405 raw_cons = NEXT_RAW_CMP(raw_cons);
406 } while (nb_tx_pkts < ring_mask);
409 if (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE)
410 bnxt_tx_cmp_vec_fast(txq, nb_tx_pkts);
412 bnxt_tx_cmp_vec(txq, nb_tx_pkts);
413 cpr->cp_raw_cons = raw_cons;
419 bnxt_xmit_one(struct rte_mbuf *mbuf, struct tx_bd_long *txbd,
420 struct rte_mbuf **tx_buf)
422 uint64_t dsc_hi, dsc_lo;
427 dsc_hi = mbuf->buf_iova + mbuf->data_off;
428 dsc_lo = (mbuf->data_len << 16) |
429 bnxt_xmit_flags_len(mbuf->data_len, TX_BD_FLAGS_NOCMPL);
431 desc = _mm_set_epi64x(dsc_hi, dsc_lo);
432 _mm_store_si128((void *)txbd, desc);
436 bnxt_xmit_fixed_burst_vec(struct bnxt_tx_queue *txq, struct rte_mbuf **pkts,
439 struct bnxt_tx_ring_info *txr = txq->tx_ring;
440 uint16_t tx_prod, tx_raw_prod = txr->tx_raw_prod;
441 struct tx_bd_long *txbd;
442 struct rte_mbuf **tx_buf;
445 tx_prod = RING_IDX(txr->tx_ring_struct, tx_raw_prod);
446 txbd = &txr->tx_desc_ring[tx_prod];
447 tx_buf = &txr->tx_buf_ring[tx_prod];
449 /* Prefetch next transmit buffer descriptors. */
451 rte_prefetch0(txbd + 3);
453 nb_pkts = RTE_MIN(nb_pkts, bnxt_tx_avail(txq));
455 if (unlikely(nb_pkts == 0))
458 /* Handle TX burst request */
462 * If current descriptor is not on a 32-byte boundary, send one packet
463 * to align for 32-byte stores.
466 bnxt_xmit_one(pkts[0], txbd++, tx_buf++);
472 * Send four packets per loop, with a single store for each pair
475 while (to_send >= BNXT_TX_DESCS_PER_LOOP) {
476 uint64_t dsc0_hi, dsc0_lo, dsc1_hi, dsc1_lo;
477 uint64_t dsc2_hi, dsc2_lo, dsc3_hi, dsc3_lo;
478 __m256i dsc01, dsc23;
480 /* Prefetch next transmit buffer descriptors. */
481 rte_prefetch0(txbd + 4);
482 rte_prefetch0(txbd + 7);
484 /* Copy four mbuf pointers to tx buf ring. */
485 #ifdef RTE_ARCH_X86_64
486 __m256i tmp = _mm256_loadu_si256((void *)pkts);
487 _mm256_storeu_si256((void *)tx_buf, tmp);
489 __m128i tmp = _mm_loadu_si128((void *)pkts);
490 _mm_storeu_si128((void *)tx_buf, tmp);
493 dsc0_hi = tx_buf[0]->buf_iova + tx_buf[0]->data_off;
494 dsc0_lo = (tx_buf[0]->data_len << 16) |
495 bnxt_xmit_flags_len(tx_buf[0]->data_len,
498 dsc1_hi = tx_buf[1]->buf_iova + tx_buf[1]->data_off;
499 dsc1_lo = (tx_buf[1]->data_len << 16) |
500 bnxt_xmit_flags_len(tx_buf[1]->data_len,
503 dsc01 = _mm256_set_epi64x(dsc1_hi, dsc1_lo, dsc0_hi, dsc0_lo);
505 dsc2_hi = tx_buf[2]->buf_iova + tx_buf[2]->data_off;
506 dsc2_lo = (tx_buf[2]->data_len << 16) |
507 bnxt_xmit_flags_len(tx_buf[2]->data_len,
510 dsc3_hi = tx_buf[3]->buf_iova + tx_buf[3]->data_off;
511 dsc3_lo = (tx_buf[3]->data_len << 16) |
512 bnxt_xmit_flags_len(tx_buf[3]->data_len,
515 dsc23 = _mm256_set_epi64x(dsc3_hi, dsc3_lo, dsc2_hi, dsc2_lo);
517 _mm256_store_si256((void *)txbd, dsc01);
518 _mm256_store_si256((void *)(txbd + 2), dsc23);
520 to_send -= BNXT_TX_DESCS_PER_LOOP;
521 pkts += BNXT_TX_DESCS_PER_LOOP;
522 txbd += BNXT_TX_DESCS_PER_LOOP;
523 tx_buf += BNXT_TX_DESCS_PER_LOOP;
526 /* Send any remaining packets, writing each descriptor individually. */
528 bnxt_xmit_one(pkts[0], txbd++, tx_buf++);
533 /* Request a completion for the final packet of the burst. */
534 txbd[-1].opaque = nb_pkts;
535 txbd[-1].flags_type &= ~TX_BD_LONG_FLAGS_NO_CMPL;
537 tx_raw_prod += nb_pkts;
538 bnxt_db_write(&txr->tx_db, tx_raw_prod);
540 txr->tx_raw_prod = tx_raw_prod;
546 bnxt_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
550 struct bnxt_tx_queue *txq = tx_queue;
551 struct bnxt_tx_ring_info *txr = txq->tx_ring;
552 uint16_t ring_size = txr->tx_ring_struct->ring_size;
554 /* Tx queue was stopped; wait for it to be restarted */
555 if (unlikely(!txq->tx_started)) {
556 PMD_DRV_LOG(DEBUG, "Tx q stopped;return\n");
560 /* Handle TX completions */
561 if (bnxt_tx_bds_in_hw(txq) >= txq->tx_free_thresh)
562 bnxt_handle_tx_cp_vec(txq);
568 * Ensure that no more than RTE_BNXT_MAX_TX_BURST packets
569 * are transmitted before the next completion.
571 num = RTE_MIN(nb_pkts, RTE_BNXT_MAX_TX_BURST);
574 * Ensure that a ring wrap does not occur within a call to
575 * bnxt_xmit_fixed_burst_vec().
577 num = RTE_MIN(num, ring_size -
578 (txr->tx_raw_prod & (ring_size - 1)));
579 ret = bnxt_xmit_fixed_burst_vec(txq, &tx_pkts[nb_sent], num);