1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Broadcom All rights reserved. */
7 #include <rte_bitmap.h>
8 #include <rte_byteorder.h>
9 #include <rte_malloc.h>
10 #include <rte_memory.h>
15 #include "bnxt_ring.h"
16 #include "bnxt_rxtx_vec_common.h"
26 bnxt_rxq_rearm(struct bnxt_rx_queue *rxq, struct bnxt_rx_ring_info *rxr)
28 struct rx_prod_pkt_bd *rxbds = &rxr->rx_desc_ring[rxq->rxrearm_start];
29 struct rte_mbuf **rx_bufs = &rxr->rx_buf_ring[rxq->rxrearm_start];
30 struct rte_mbuf *mb0, *mb1;
33 const uint64x2_t hdr_room = {0, RTE_PKTMBUF_HEADROOM};
34 const uint64x2_t addrmask = {0, UINT64_MAX};
37 * Number of mbufs to allocate must be a multiple of two. The
38 * allocation must not go past the end of the ring.
40 nb = RTE_MIN(rxq->rxrearm_nb & ~0x1,
41 rxq->nb_rx_desc - rxq->rxrearm_start);
43 /* Allocate new mbufs into the software ring */
44 if (rte_mempool_get_bulk(rxq->mb_pool, (void *)rx_bufs, nb) < 0) {
45 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed += nb;
50 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
51 for (i = 0; i < nb; i += 2, rx_bufs += 2) {
52 uint64x2_t buf_addr0, buf_addr1;
53 uint64x2_t rxbd0, rxbd1;
58 /* Load address fields from both mbufs */
59 buf_addr0 = vld1q_u64((uint64_t *)&mb0->buf_addr);
60 buf_addr1 = vld1q_u64((uint64_t *)&mb1->buf_addr);
62 /* Load both rx descriptors (preserving some existing fields) */
63 rxbd0 = vld1q_u64((uint64_t *)(rxbds + 0));
64 rxbd1 = vld1q_u64((uint64_t *)(rxbds + 1));
66 /* Add default offset to buffer address. */
67 buf_addr0 = vaddq_u64(buf_addr0, hdr_room);
68 buf_addr1 = vaddq_u64(buf_addr1, hdr_room);
70 /* Clear all fields except address. */
71 buf_addr0 = vandq_u64(buf_addr0, addrmask);
72 buf_addr1 = vandq_u64(buf_addr1, addrmask);
74 /* Clear address field in descriptor. */
75 rxbd0 = vbicq_u64(rxbd0, addrmask);
76 rxbd1 = vbicq_u64(rxbd1, addrmask);
78 /* Set address field in descriptor. */
79 rxbd0 = vaddq_u64(rxbd0, buf_addr0);
80 rxbd1 = vaddq_u64(rxbd1, buf_addr1);
82 /* Store descriptors to memory. */
83 vst1q_u64((uint64_t *)(rxbds++), rxbd0);
84 vst1q_u64((uint64_t *)(rxbds++), rxbd1);
87 rxq->rxrearm_start += nb;
88 bnxt_db_write(&rxr->rx_db, rxq->rxrearm_start - 1);
89 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
90 rxq->rxrearm_start = 0;
92 rxq->rxrearm_nb -= nb;
96 bnxt_parse_pkt_type(struct rx_pkt_cmpl *rxcmp, struct rx_pkt_cmpl_hi *rxcmp1)
98 uint32_t l3, pkt_type = 0;
99 uint32_t t_ipcs = 0, ip6 = 0, vlan = 0;
102 vlan = !!(rxcmp1->flags2 &
103 rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN));
104 pkt_type |= vlan ? RTE_PTYPE_L2_ETHER_VLAN : RTE_PTYPE_L2_ETHER;
106 t_ipcs = !!(rxcmp1->flags2 &
107 rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC));
108 ip6 = !!(rxcmp1->flags2 &
109 rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_TYPE));
111 flags_type = rxcmp->flags_type &
112 rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS_ITYPE_MASK);
115 l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
116 else if (!t_ipcs && ip6)
117 l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
118 else if (t_ipcs && !ip6)
119 l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
121 l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
123 switch (flags_type) {
124 case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_ICMP):
126 pkt_type |= l3 | RTE_PTYPE_L4_ICMP;
128 pkt_type |= l3 | RTE_PTYPE_INNER_L4_ICMP;
131 case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_TCP):
133 pkt_type |= l3 | RTE_PTYPE_L4_TCP;
135 pkt_type |= l3 | RTE_PTYPE_INNER_L4_TCP;
138 case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_UDP):
140 pkt_type |= l3 | RTE_PTYPE_L4_UDP;
142 pkt_type |= l3 | RTE_PTYPE_INNER_L4_UDP;
145 case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_IP):
154 bnxt_parse_csum(struct rte_mbuf *mbuf, struct rx_pkt_cmpl_hi *rxcmp1)
158 flags = flags2_0xf(rxcmp1);
160 if (likely(IS_IP_NONTUNNEL_PKT(flags))) {
161 if (unlikely(RX_CMP_IP_CS_ERROR(rxcmp1)))
162 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
164 mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
165 } else if (IS_IP_TUNNEL_PKT(flags)) {
166 if (unlikely(RX_CMP_IP_OUTER_CS_ERROR(rxcmp1) ||
167 RX_CMP_IP_CS_ERROR(rxcmp1)))
168 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
170 mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
171 } else if (unlikely(RX_CMP_IP_CS_UNKNOWN(rxcmp1))) {
172 mbuf->ol_flags |= PKT_RX_IP_CKSUM_UNKNOWN;
176 if (likely(IS_L4_NONTUNNEL_PKT(flags))) {
177 if (unlikely(RX_CMP_L4_INNER_CS_ERR2(rxcmp1)))
178 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
180 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
181 } else if (IS_L4_TUNNEL_PKT(flags)) {
182 if (unlikely(RX_CMP_L4_INNER_CS_ERR2(rxcmp1)))
183 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
185 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
186 if (unlikely(RX_CMP_L4_OUTER_CS_ERR2(rxcmp1))) {
187 mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
188 } else if (unlikely(IS_L4_TUNNEL_PKT_ONLY_INNER_L4_CS
190 mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_UNKNOWN;
192 mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
194 } else if (unlikely(RX_CMP_L4_CS_UNKNOWN(rxcmp1))) {
195 mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
200 bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
203 struct bnxt_rx_queue *rxq = rx_queue;
204 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
205 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
206 uint32_t raw_cons = cpr->cp_raw_cons;
209 struct rx_pkt_cmpl *rxcmp;
210 const uint64x2_t mbuf_init = {rxq->mbuf_initializer, 0};
211 const uint8x16_t shuf_msk = {
212 0xFF, 0xFF, 0xFF, 0xFF, /* pkt_type (zeroes) */
213 2, 3, 0xFF, 0xFF, /* pkt_len */
215 0xFF, 0xFF, /* vlan_tci (zeroes) */
216 12, 13, 14, 15 /* rss hash */
220 /* If Rx Q was stopped return */
221 if (unlikely(!rxq->rx_started))
224 if (rxq->rxrearm_nb >= rxq->rx_free_thresh)
225 bnxt_rxq_rearm(rxq, rxr);
227 /* Return no more than RTE_BNXT_MAX_RX_BURST per call. */
228 nb_pkts = RTE_MIN(nb_pkts, RTE_BNXT_MAX_RX_BURST);
230 /* Make nb_pkts an integer multiple of RTE_BNXT_DESCS_PER_LOOP. */
231 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_BNXT_DESCS_PER_LOOP);
235 /* Handle RX burst request */
236 for (i = 0; i < nb_pkts; i++) {
237 struct rx_pkt_cmpl_hi *rxcmp1;
238 struct rte_mbuf *mbuf;
242 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
244 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
245 rxcmp1 = (struct rx_pkt_cmpl_hi *)&cpr->cp_desc_ring[cons + 1];
247 if (!CMP_VALID(rxcmp1, raw_cons + 1, cpr->cp_ring_struct))
251 cons = rxcmp->opaque;
253 mbuf = rxr->rx_buf_ring[cons];
255 rxr->rx_buf_ring[cons] = NULL;
257 /* Set constant fields from mbuf initializer. */
258 vst1q_u64((uint64_t *)&mbuf->rearm_data, mbuf_init);
260 /* Set mbuf pkt_len, data_len, and rss_hash fields. */
261 mm_rxcmp = vld1q_u64((uint64_t *)rxcmp);
262 pkt_mb = vqtbl1q_u8(vreinterpretq_u8_u64(mm_rxcmp), shuf_msk);
263 vst1q_u64((uint64_t *)&mbuf->rx_descriptor_fields1,
264 vreinterpretq_u64_u8(pkt_mb));
266 rte_compiler_barrier();
268 if (rxcmp->flags_type & RX_PKT_CMPL_FLAGS_RSS_VALID)
269 mbuf->ol_flags |= PKT_RX_RSS_HASH;
272 RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN) {
273 mbuf->vlan_tci = rxcmp1->metadata &
274 (RX_PKT_CMPL_METADATA_VID_MASK |
275 RX_PKT_CMPL_METADATA_DE |
276 RX_PKT_CMPL_METADATA_PRI_MASK);
278 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
281 bnxt_parse_csum(mbuf, rxcmp1);
282 mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);
284 rx_pkts[nb_rx_pkts++] = mbuf;
289 RING_ADV(rxr->rx_ring_struct, rxr->rx_prod, nb_rx_pkts);
291 rxq->rxrearm_nb += nb_rx_pkts;
292 cpr->cp_raw_cons = raw_cons;
294 !!(cpr->cp_raw_cons & cpr->cp_ring_struct->ring_size);
302 bnxt_tx_cmp_vec(struct bnxt_tx_queue *txq, int nr_pkts)
304 struct bnxt_tx_ring_info *txr = txq->tx_ring;
305 struct rte_mbuf **free = txq->free;
306 uint16_t cons = txr->tx_cons;
307 unsigned int blk = 0;
310 struct bnxt_sw_tx_bd *tx_buf;
311 struct rte_mbuf *mbuf;
313 tx_buf = &txr->tx_buf_ring[cons];
314 cons = RING_NEXT(txr->tx_ring_struct, cons);
315 mbuf = rte_pktmbuf_prefree_seg(tx_buf->mbuf);
316 if (unlikely(mbuf == NULL))
320 if (blk && mbuf->pool != free[0]->pool) {
321 rte_mempool_put_bulk(free[0]->pool, (void **)free, blk);
327 rte_mempool_put_bulk(free[0]->pool, (void **)free, blk);
333 bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
335 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
336 uint32_t raw_cons = cpr->cp_raw_cons;
338 uint32_t nb_tx_pkts = 0;
339 struct tx_cmpl *txcmp;
340 struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
341 struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
342 uint32_t ring_mask = cp_ring_struct->ring_mask;
345 cons = RING_CMPL(ring_mask, raw_cons);
346 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
348 if (!CMP_VALID(txcmp, raw_cons, cp_ring_struct))
351 if (likely(CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2))
352 nb_tx_pkts += txcmp->opaque;
355 "Unhandled CMP type %02x\n",
357 raw_cons = NEXT_RAW_CMP(raw_cons);
358 } while (nb_tx_pkts < ring_mask);
360 cpr->valid = !!(raw_cons & cp_ring_struct->ring_size);
362 bnxt_tx_cmp_vec(txq, nb_tx_pkts);
363 cpr->cp_raw_cons = raw_cons;
369 bnxt_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
372 struct bnxt_tx_queue *txq = tx_queue;
373 struct bnxt_tx_ring_info *txr = txq->tx_ring;
374 uint16_t prod = txr->tx_prod;
375 struct rte_mbuf *tx_mbuf;
376 struct tx_bd_long *txbd = NULL;
377 struct bnxt_sw_tx_bd *tx_buf;
380 nb_pkts = RTE_MIN(nb_pkts, bnxt_tx_avail(txq));
382 if (unlikely(nb_pkts == 0))
385 /* Handle TX burst request */
388 tx_mbuf = *tx_pkts++;
389 rte_prefetch0(tx_mbuf);
391 tx_buf = &txr->tx_buf_ring[prod];
392 tx_buf->mbuf = tx_mbuf;
395 txbd = &txr->tx_desc_ring[prod];
396 txbd->address = tx_mbuf->buf_iova + tx_mbuf->data_off;
397 txbd->len = tx_mbuf->data_len;
398 txbd->flags_type = bnxt_xmit_flags_len(tx_mbuf->data_len,
400 prod = RING_NEXT(txr->tx_ring_struct, prod);
404 /* Request a completion for last packet in burst */
406 txbd->opaque = nb_pkts;
407 txbd->flags_type &= ~TX_BD_LONG_FLAGS_NO_CMPL;
410 rte_compiler_barrier();
411 bnxt_db_write(&txr->tx_db, prod);
419 bnxt_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
423 struct bnxt_tx_queue *txq = tx_queue;
425 /* Tx queue was stopped; wait for it to be restarted */
426 if (unlikely(!txq->tx_started)) {
427 PMD_DRV_LOG(DEBUG, "Tx q stopped;return\n");
431 /* Handle TX completions */
432 if (bnxt_tx_bds_in_hw(txq) >= txq->tx_free_thresh)
433 bnxt_handle_tx_cp_vec(txq);
438 num = RTE_MIN(nb_pkts, RTE_BNXT_MAX_TX_BURST);
439 ret = bnxt_xmit_fixed_burst_vec(tx_queue,
452 bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq)
454 return bnxt_rxq_vec_setup_common(rxq);