1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Broadcom All rights reserved. */
7 #include <rte_bitmap.h>
8 #include <rte_byteorder.h>
9 #include <rte_malloc.h>
10 #include <rte_memory.h>
15 #include "bnxt_ring.h"
16 #include "bnxt_rxtx_vec_common.h"
25 #define GET_OL_FLAGS(rss_flags, ol_index, errors, pi, ol_flags) \
29 of = _mm_extract_epi32((rss_flags), (pi)) | \
30 bnxt_ol_flags_table[_mm_extract_epi32((ol_index), (pi))]; \
32 tmp = _mm_extract_epi32((errors), (pi)); \
34 of |= bnxt_ol_flags_err_table[tmp]; \
38 #define GET_DESC_FIELDS(rxcmp, rxcmp1, shuf_msk, ptype_idx, pi, ret) \
43 /* Set mbuf pkt_len, data_len, and rss_hash fields. */ \
44 r = _mm_shuffle_epi8((rxcmp), (shuf_msk)); \
46 /* Set packet type. */ \
47 ptype = bnxt_ptype_table[_mm_extract_epi32((ptype_idx), (pi))]; \
48 r = _mm_blend_epi16(r, _mm_set_epi32(0, 0, 0, ptype), 0x3); \
51 r = _mm_blend_epi16(r, _mm_slli_si128((rxcmp1), 6), 0x20); \
56 descs_to_mbufs(__m128i mm_rxcmp[4], __m128i mm_rxcmp1[4],
57 __m128i mbuf_init, struct rte_mbuf **mbuf)
59 const __m128i shuf_msk =
60 _mm_set_epi8(15, 14, 13, 12, /* rss */
61 0xFF, 0xFF, /* vlan_tci (zeroes) */
63 0xFF, 0xFF, 3, 2, /* pkt_len */
64 0xFF, 0xFF, 0xFF, 0xFF); /* pkt_type (zeroes) */
65 const __m128i flags_type_mask =
66 _mm_set_epi32(RX_PKT_CMPL_FLAGS_ITYPE_MASK,
67 RX_PKT_CMPL_FLAGS_ITYPE_MASK,
68 RX_PKT_CMPL_FLAGS_ITYPE_MASK,
69 RX_PKT_CMPL_FLAGS_ITYPE_MASK);
70 const __m128i flags2_mask1 =
71 _mm_set_epi32(RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN |
72 RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC,
73 RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN |
74 RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC,
75 RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN |
76 RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC,
77 RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN |
78 RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC);
79 const __m128i flags2_mask2 =
80 _mm_set_epi32(RX_PKT_CMPL_FLAGS2_IP_TYPE,
81 RX_PKT_CMPL_FLAGS2_IP_TYPE,
82 RX_PKT_CMPL_FLAGS2_IP_TYPE,
83 RX_PKT_CMPL_FLAGS2_IP_TYPE);
84 const __m128i rss_mask =
85 _mm_set_epi32(RX_PKT_CMPL_FLAGS_RSS_VALID,
86 RX_PKT_CMPL_FLAGS_RSS_VALID,
87 RX_PKT_CMPL_FLAGS_RSS_VALID,
88 RX_PKT_CMPL_FLAGS_RSS_VALID);
89 __m128i t0, t1, flags_type, flags2, index, errors, rss_flags;
93 /* Compute packet type table indexes for four packets */
94 t0 = _mm_unpacklo_epi32(mm_rxcmp[0], mm_rxcmp[1]);
95 t1 = _mm_unpacklo_epi32(mm_rxcmp[2], mm_rxcmp[3]);
96 flags_type = _mm_unpacklo_epi64(t0, t1);
98 _mm_srli_epi32(_mm_and_si128(flags_type, flags_type_mask), 9);
100 t0 = _mm_unpacklo_epi32(mm_rxcmp1[0], mm_rxcmp1[1]);
101 t1 = _mm_unpacklo_epi32(mm_rxcmp1[2], mm_rxcmp1[3]);
102 flags2 = _mm_unpacklo_epi64(t0, t1);
104 ptype_idx = _mm_or_si128(ptype_idx,
105 _mm_srli_epi32(_mm_and_si128(flags2, flags2_mask1), 2));
106 ptype_idx = _mm_or_si128(ptype_idx,
107 _mm_srli_epi32(_mm_and_si128(flags2, flags2_mask2), 7));
109 /* Extract RSS valid flags for four packets. */
110 rss_flags = _mm_srli_epi32(_mm_and_si128(flags_type, rss_mask), 9);
112 /* Extract errors_v2 fields for four packets. */
113 t0 = _mm_unpackhi_epi32(mm_rxcmp1[0], mm_rxcmp1[1]);
114 t1 = _mm_unpackhi_epi32(mm_rxcmp1[2], mm_rxcmp1[3]);
116 /* Compute ol_flags and checksum error indexes for four packets. */
117 flags2 = _mm_and_si128(flags2, _mm_set_epi32(0x1F, 0x1F, 0x1F, 0x1F));
119 errors = _mm_srli_epi32(_mm_unpacklo_epi64(t0, t1), 4);
120 errors = _mm_and_si128(errors, _mm_set_epi32(0xF, 0xF, 0xF, 0xF));
121 errors = _mm_and_si128(errors, flags2);
123 index = _mm_andnot_si128(errors, flags2);
125 /* Update mbuf rearm_data for four packets. */
126 GET_OL_FLAGS(rss_flags, index, errors, 0, ol_flags);
127 _mm_store_si128((void *)&mbuf[0]->rearm_data,
128 _mm_or_si128(mbuf_init, _mm_set_epi64x(ol_flags, 0)));
130 GET_OL_FLAGS(rss_flags, index, errors, 1, ol_flags);
131 _mm_store_si128((void *)&mbuf[1]->rearm_data,
132 _mm_or_si128(mbuf_init, _mm_set_epi64x(ol_flags, 0)));
134 GET_OL_FLAGS(rss_flags, index, errors, 2, ol_flags);
135 _mm_store_si128((void *)&mbuf[2]->rearm_data,
136 _mm_or_si128(mbuf_init, _mm_set_epi64x(ol_flags, 0)));
138 GET_OL_FLAGS(rss_flags, index, errors, 3, ol_flags);
139 _mm_store_si128((void *)&mbuf[3]->rearm_data,
140 _mm_or_si128(mbuf_init, _mm_set_epi64x(ol_flags, 0)));
142 /* Update mbuf rx_descriptor_fields1 for four packes. */
143 GET_DESC_FIELDS(mm_rxcmp[0], mm_rxcmp1[0], shuf_msk, ptype_idx, 0, t0);
144 _mm_store_si128((void *)&mbuf[0]->rx_descriptor_fields1, t0);
146 GET_DESC_FIELDS(mm_rxcmp[1], mm_rxcmp1[1], shuf_msk, ptype_idx, 1, t0);
147 _mm_store_si128((void *)&mbuf[1]->rx_descriptor_fields1, t0);
149 GET_DESC_FIELDS(mm_rxcmp[2], mm_rxcmp1[2], shuf_msk, ptype_idx, 2, t0);
150 _mm_store_si128((void *)&mbuf[2]->rx_descriptor_fields1, t0);
152 GET_DESC_FIELDS(mm_rxcmp[3], mm_rxcmp1[3], shuf_msk, ptype_idx, 3, t0);
153 _mm_store_si128((void *)&mbuf[3]->rx_descriptor_fields1, t0);
157 bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
160 struct bnxt_rx_queue *rxq = rx_queue;
161 const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
162 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
163 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
164 uint16_t cp_ring_size = cpr->cp_ring_struct->ring_size;
165 uint16_t rx_ring_size = rxr->rx_ring_struct->ring_size;
166 struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
167 uint64_t valid, desc_valid_mask = ~0UL;
168 const __m128i info3_v_mask = _mm_set_epi32(CMPL_BASE_V, CMPL_BASE_V,
169 CMPL_BASE_V, CMPL_BASE_V);
170 uint32_t raw_cons = cpr->cp_raw_cons;
171 uint32_t cons, mbcons;
173 const __m128i valid_target =
174 _mm_set_epi32(!!(raw_cons & cp_ring_size),
175 !!(raw_cons & cp_ring_size),
176 !!(raw_cons & cp_ring_size),
177 !!(raw_cons & cp_ring_size));
180 /* If Rx Q was stopped return */
181 if (unlikely(!rxq->rx_started))
184 if (rxq->rxrearm_nb >= rxq->rx_free_thresh)
185 bnxt_rxq_rearm(rxq, rxr);
187 /* Return no more than RTE_BNXT_MAX_RX_BURST per call. */
188 nb_pkts = RTE_MIN(nb_pkts, RTE_BNXT_MAX_RX_BURST);
190 cons = raw_cons & (cp_ring_size - 1);
191 mbcons = (raw_cons / 2) & (rx_ring_size - 1);
193 /* Prefetch first four descriptor pairs. */
194 rte_prefetch0(&cp_desc_ring[cons]);
195 rte_prefetch0(&cp_desc_ring[cons + 4]);
197 /* Ensure that we do not go past the ends of the rings. */
198 nb_pkts = RTE_MIN(nb_pkts, RTE_MIN(rx_ring_size - mbcons,
199 (cp_ring_size - cons) / 2));
201 * If we are at the end of the ring, ensure that descriptors after the
202 * last valid entry are not treated as valid. Otherwise, force the
203 * maximum number of packets to receive to be a multiple of the per-
206 if (nb_pkts < RTE_BNXT_DESCS_PER_LOOP)
207 desc_valid_mask >>= 16 * (RTE_BNXT_DESCS_PER_LOOP - nb_pkts);
209 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_BNXT_DESCS_PER_LOOP);
211 /* Handle RX burst request */
212 for (i = 0; i < nb_pkts; i += RTE_BNXT_DESCS_PER_LOOP,
213 cons += RTE_BNXT_DESCS_PER_LOOP * 2,
214 mbcons += RTE_BNXT_DESCS_PER_LOOP) {
215 __m128i rxcmp1[RTE_BNXT_DESCS_PER_LOOP];
216 __m128i rxcmp[RTE_BNXT_DESCS_PER_LOOP];
217 __m128i tmp0, tmp1, info3_v;
220 /* Copy four mbuf pointers to output array. */
221 tmp0 = _mm_loadu_si128((void *)&rxr->rx_buf_ring[mbcons]);
222 #ifdef RTE_ARCH_X86_64
223 tmp1 = _mm_loadu_si128((void *)&rxr->rx_buf_ring[mbcons + 2]);
225 _mm_storeu_si128((void *)&rx_pkts[i], tmp0);
226 #ifdef RTE_ARCH_X86_64
227 _mm_storeu_si128((void *)&rx_pkts[i + 2], tmp1);
230 /* Prefetch four descriptor pairs for next iteration. */
231 if (i + RTE_BNXT_DESCS_PER_LOOP < nb_pkts) {
232 rte_prefetch0(&cp_desc_ring[cons + 8]);
233 rte_prefetch0(&cp_desc_ring[cons + 12]);
237 * Load the four current descriptors into SSE registers in
238 * reverse order to ensure consistent state.
240 rxcmp1[3] = _mm_load_si128((void *)&cp_desc_ring[cons + 7]);
241 rte_compiler_barrier();
242 rxcmp[3] = _mm_load_si128((void *)&cp_desc_ring[cons + 6]);
244 rxcmp1[2] = _mm_load_si128((void *)&cp_desc_ring[cons + 5]);
245 rte_compiler_barrier();
246 rxcmp[2] = _mm_load_si128((void *)&cp_desc_ring[cons + 4]);
248 tmp1 = _mm_unpackhi_epi32(rxcmp1[2], rxcmp1[3]);
250 rxcmp1[1] = _mm_load_si128((void *)&cp_desc_ring[cons + 3]);
251 rte_compiler_barrier();
252 rxcmp[1] = _mm_load_si128((void *)&cp_desc_ring[cons + 2]);
254 rxcmp1[0] = _mm_load_si128((void *)&cp_desc_ring[cons + 1]);
255 rte_compiler_barrier();
256 rxcmp[0] = _mm_load_si128((void *)&cp_desc_ring[cons + 0]);
258 tmp0 = _mm_unpackhi_epi32(rxcmp1[0], rxcmp1[1]);
260 /* Isolate descriptor valid flags. */
261 info3_v = _mm_and_si128(_mm_unpacklo_epi64(tmp0, tmp1),
263 info3_v = _mm_xor_si128(info3_v, valid_target);
266 * Pack the 128-bit array of valid descriptor flags into 64
267 * bits and count the number of set bits in order to determine
268 * the number of valid descriptors.
270 valid = _mm_cvtsi128_si64(_mm_packs_epi32(info3_v, info3_v));
271 num_valid = __builtin_popcountll(valid & desc_valid_mask);
275 rxr->rx_buf_ring[mbcons + 3] = NULL;
278 rxr->rx_buf_ring[mbcons + 2] = NULL;
281 rxr->rx_buf_ring[mbcons + 1] = NULL;
284 rxr->rx_buf_ring[mbcons + 0] = NULL;
290 descs_to_mbufs(rxcmp, rxcmp1, mbuf_init, &rx_pkts[nb_rx_pkts]);
291 nb_rx_pkts += num_valid;
293 if (num_valid < RTE_BNXT_DESCS_PER_LOOP)
300 RING_ADV(rxr->rx_ring_struct, rxr->rx_prod, nb_rx_pkts);
302 rxq->rxrearm_nb += nb_rx_pkts;
303 cpr->cp_raw_cons += 2 * nb_rx_pkts;
305 !!(cpr->cp_raw_cons & cpr->cp_ring_struct->ring_size);
313 bnxt_tx_cmp_vec(struct bnxt_tx_queue *txq, int nr_pkts)
315 struct bnxt_tx_ring_info *txr = txq->tx_ring;
316 struct rte_mbuf **free = txq->free;
317 uint16_t cons = txr->tx_cons;
318 unsigned int blk = 0;
321 struct bnxt_sw_tx_bd *tx_buf;
322 struct rte_mbuf *mbuf;
324 tx_buf = &txr->tx_buf_ring[cons];
325 cons = RING_NEXT(txr->tx_ring_struct, cons);
326 mbuf = rte_pktmbuf_prefree_seg(tx_buf->mbuf);
327 if (unlikely(mbuf == NULL))
331 if (blk && mbuf->pool != free[0]->pool) {
332 rte_mempool_put_bulk(free[0]->pool, (void **)free, blk);
338 rte_mempool_put_bulk(free[0]->pool, (void **)free, blk);
344 bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
346 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
347 uint32_t raw_cons = cpr->cp_raw_cons;
349 uint32_t nb_tx_pkts = 0;
350 struct tx_cmpl *txcmp;
351 struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
352 struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
353 uint32_t ring_mask = cp_ring_struct->ring_mask;
356 cons = RING_CMPL(ring_mask, raw_cons);
357 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
359 if (!CMP_VALID(txcmp, raw_cons, cp_ring_struct))
362 if (likely(CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2))
363 nb_tx_pkts += txcmp->opaque;
366 "Unhandled CMP type %02x\n",
368 raw_cons = NEXT_RAW_CMP(raw_cons);
369 } while (nb_tx_pkts < ring_mask);
371 cpr->valid = !!(raw_cons & cp_ring_struct->ring_size);
373 bnxt_tx_cmp_vec(txq, nb_tx_pkts);
374 cpr->cp_raw_cons = raw_cons;
380 bnxt_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
383 struct bnxt_tx_queue *txq = tx_queue;
384 struct bnxt_tx_ring_info *txr = txq->tx_ring;
385 uint16_t prod = txr->tx_prod;
386 struct rte_mbuf *tx_mbuf;
387 struct tx_bd_long *txbd = NULL;
388 struct bnxt_sw_tx_bd *tx_buf;
391 nb_pkts = RTE_MIN(nb_pkts, bnxt_tx_avail(txq));
393 if (unlikely(nb_pkts == 0))
396 /* Handle TX burst request */
399 tx_mbuf = *tx_pkts++;
400 rte_prefetch0(tx_mbuf);
402 tx_buf = &txr->tx_buf_ring[prod];
403 tx_buf->mbuf = tx_mbuf;
406 txbd = &txr->tx_desc_ring[prod];
407 txbd->address = tx_mbuf->buf_iova + tx_mbuf->data_off;
408 txbd->len = tx_mbuf->data_len;
409 txbd->flags_type = bnxt_xmit_flags_len(tx_mbuf->data_len,
411 prod = RING_NEXT(txr->tx_ring_struct, prod);
415 /* Request a completion for last packet in burst */
417 txbd->opaque = nb_pkts;
418 txbd->flags_type &= ~TX_BD_LONG_FLAGS_NO_CMPL;
421 rte_compiler_barrier();
422 bnxt_db_write(&txr->tx_db, prod);
430 bnxt_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
434 struct bnxt_tx_queue *txq = tx_queue;
436 /* Tx queue was stopped; wait for it to be restarted */
437 if (unlikely(!txq->tx_started)) {
438 PMD_DRV_LOG(DEBUG, "Tx q stopped;return\n");
442 /* Handle TX completions */
443 if (bnxt_tx_bds_in_hw(txq) >= txq->tx_free_thresh)
444 bnxt_handle_tx_cp_vec(txq);
449 num = RTE_MIN(nb_pkts, RTE_BNXT_MAX_TX_BURST);
450 ret = bnxt_xmit_fixed_burst_vec(tx_queue,
463 bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq)
465 return bnxt_rxq_vec_setup_common(rxq);