1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Broadcom All rights reserved. */
7 #include <rte_bitmap.h>
8 #include <rte_byteorder.h>
9 #include <rte_malloc.h>
10 #include <rte_memory.h>
15 #include "bnxt_ring.h"
19 #include "bnxt_rxtx_vec_common.h"
25 #define GET_OL_FLAGS(rss_flags, ol_index, errors, pi, ol_flags) \
29 of = _mm_extract_epi32((rss_flags), (pi)) | \
30 rxr->ol_flags_table[_mm_extract_epi32((ol_index), (pi))]; \
32 tmp = _mm_extract_epi32((errors), (pi)); \
34 of |= rxr->ol_flags_err_table[tmp]; \
38 #define GET_DESC_FIELDS(rxcmp, rxcmp1, shuf_msk, ptype_idx, pi, ret) \
43 /* Set mbuf pkt_len, data_len, and rss_hash fields. */ \
44 r = _mm_shuffle_epi8((rxcmp), (shuf_msk)); \
46 /* Set packet type. */ \
47 ptype = bnxt_ptype_table[_mm_extract_epi32((ptype_idx), (pi))]; \
48 r = _mm_blend_epi16(r, _mm_set_epi32(0, 0, 0, ptype), 0x3); \
51 r = _mm_blend_epi16(r, _mm_slli_si128((rxcmp1), 6), 0x20); \
56 descs_to_mbufs(__m128i mm_rxcmp[4], __m128i mm_rxcmp1[4],
57 __m128i mbuf_init, struct rte_mbuf **mbuf,
58 struct bnxt_rx_ring_info *rxr)
60 const __m128i shuf_msk =
61 _mm_set_epi8(15, 14, 13, 12, /* rss */
62 0xFF, 0xFF, /* vlan_tci (zeroes) */
64 0xFF, 0xFF, 3, 2, /* pkt_len */
65 0xFF, 0xFF, 0xFF, 0xFF); /* pkt_type (zeroes) */
66 const __m128i flags_type_mask =
67 _mm_set1_epi32(RX_PKT_CMPL_FLAGS_ITYPE_MASK);
68 const __m128i flags2_mask1 =
69 _mm_set1_epi32(RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN |
70 RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC);
71 const __m128i flags2_mask2 =
72 _mm_set1_epi32(RX_PKT_CMPL_FLAGS2_IP_TYPE);
73 const __m128i rss_mask =
74 _mm_set1_epi32(RX_PKT_CMPL_FLAGS_RSS_VALID);
75 __m128i t0, t1, flags_type, flags2, index, errors, rss_flags;
79 /* Compute packet type table indexes for four packets */
80 t0 = _mm_unpacklo_epi32(mm_rxcmp[0], mm_rxcmp[1]);
81 t1 = _mm_unpacklo_epi32(mm_rxcmp[2], mm_rxcmp[3]);
82 flags_type = _mm_unpacklo_epi64(t0, t1);
84 _mm_srli_epi32(_mm_and_si128(flags_type, flags_type_mask), 9);
86 t0 = _mm_unpacklo_epi32(mm_rxcmp1[0], mm_rxcmp1[1]);
87 t1 = _mm_unpacklo_epi32(mm_rxcmp1[2], mm_rxcmp1[3]);
88 flags2 = _mm_unpacklo_epi64(t0, t1);
90 ptype_idx = _mm_or_si128(ptype_idx,
91 _mm_srli_epi32(_mm_and_si128(flags2, flags2_mask1), 2));
92 ptype_idx = _mm_or_si128(ptype_idx,
93 _mm_srli_epi32(_mm_and_si128(flags2, flags2_mask2), 7));
95 /* Extract RSS valid flags for four packets. */
96 rss_flags = _mm_srli_epi32(_mm_and_si128(flags_type, rss_mask), 9);
98 /* Extract errors_v2 fields for four packets. */
99 t0 = _mm_unpackhi_epi32(mm_rxcmp1[0], mm_rxcmp1[1]);
100 t1 = _mm_unpackhi_epi32(mm_rxcmp1[2], mm_rxcmp1[3]);
102 /* Compute ol_flags and checksum error indexes for four packets. */
103 flags2 = _mm_and_si128(flags2, _mm_set1_epi32(0x1F));
105 errors = _mm_srli_epi32(_mm_unpacklo_epi64(t0, t1), 4);
106 errors = _mm_and_si128(errors, _mm_set1_epi32(0xF));
107 errors = _mm_and_si128(errors, flags2);
109 index = _mm_andnot_si128(errors, flags2);
111 /* Update mbuf rearm_data for four packets. */
112 GET_OL_FLAGS(rss_flags, index, errors, 0, ol_flags);
113 _mm_store_si128((void *)&mbuf[0]->rearm_data,
114 _mm_or_si128(mbuf_init, _mm_set_epi64x(ol_flags, 0)));
116 GET_OL_FLAGS(rss_flags, index, errors, 1, ol_flags);
117 _mm_store_si128((void *)&mbuf[1]->rearm_data,
118 _mm_or_si128(mbuf_init, _mm_set_epi64x(ol_flags, 0)));
120 GET_OL_FLAGS(rss_flags, index, errors, 2, ol_flags);
121 _mm_store_si128((void *)&mbuf[2]->rearm_data,
122 _mm_or_si128(mbuf_init, _mm_set_epi64x(ol_flags, 0)));
124 GET_OL_FLAGS(rss_flags, index, errors, 3, ol_flags);
125 _mm_store_si128((void *)&mbuf[3]->rearm_data,
126 _mm_or_si128(mbuf_init, _mm_set_epi64x(ol_flags, 0)));
128 /* Update mbuf rx_descriptor_fields1 for four packes. */
129 GET_DESC_FIELDS(mm_rxcmp[0], mm_rxcmp1[0], shuf_msk, ptype_idx, 0, t0);
130 _mm_store_si128((void *)&mbuf[0]->rx_descriptor_fields1, t0);
132 GET_DESC_FIELDS(mm_rxcmp[1], mm_rxcmp1[1], shuf_msk, ptype_idx, 1, t0);
133 _mm_store_si128((void *)&mbuf[1]->rx_descriptor_fields1, t0);
135 GET_DESC_FIELDS(mm_rxcmp[2], mm_rxcmp1[2], shuf_msk, ptype_idx, 2, t0);
136 _mm_store_si128((void *)&mbuf[2]->rx_descriptor_fields1, t0);
138 GET_DESC_FIELDS(mm_rxcmp[3], mm_rxcmp1[3], shuf_msk, ptype_idx, 3, t0);
139 _mm_store_si128((void *)&mbuf[3]->rx_descriptor_fields1, t0);
143 bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
146 struct bnxt_rx_queue *rxq = rx_queue;
147 const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
148 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
149 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
150 uint16_t cp_ring_size = cpr->cp_ring_struct->ring_size;
151 uint16_t rx_ring_size = rxr->rx_ring_struct->ring_size;
152 struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
153 uint64_t valid, desc_valid_mask = ~0ULL;
154 const __m128i info3_v_mask = _mm_set1_epi32(CMPL_BASE_V);
155 uint32_t raw_cons = cpr->cp_raw_cons;
156 uint32_t cons, mbcons;
158 const __m128i valid_target =
159 _mm_set1_epi32(!!(raw_cons & cp_ring_size));
162 /* If Rx Q was stopped return */
163 if (unlikely(!rxq->rx_started))
166 if (rxq->rxrearm_nb >= rxq->rx_free_thresh)
167 bnxt_rxq_rearm(rxq, rxr);
169 /* Return no more than RTE_BNXT_MAX_RX_BURST per call. */
170 nb_pkts = RTE_MIN(nb_pkts, RTE_BNXT_MAX_RX_BURST);
172 cons = raw_cons & (cp_ring_size - 1);
173 mbcons = (raw_cons / 2) & (rx_ring_size - 1);
175 /* Prefetch first four descriptor pairs. */
176 rte_prefetch0(&cp_desc_ring[cons]);
177 rte_prefetch0(&cp_desc_ring[cons + 4]);
179 /* Ensure that we do not go past the ends of the rings. */
180 nb_pkts = RTE_MIN(nb_pkts, RTE_MIN(rx_ring_size - mbcons,
181 (cp_ring_size - cons) / 2));
183 * If we are at the end of the ring, ensure that descriptors after the
184 * last valid entry are not treated as valid. Otherwise, force the
185 * maximum number of packets to receive to be a multiple of the per-
188 if (nb_pkts < RTE_BNXT_DESCS_PER_LOOP)
189 desc_valid_mask >>= 16 * (RTE_BNXT_DESCS_PER_LOOP - nb_pkts);
191 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_BNXT_DESCS_PER_LOOP);
193 /* Handle RX burst request */
194 for (i = 0; i < nb_pkts; i += RTE_BNXT_DESCS_PER_LOOP,
195 cons += RTE_BNXT_DESCS_PER_LOOP * 2,
196 mbcons += RTE_BNXT_DESCS_PER_LOOP) {
197 __m128i rxcmp1[RTE_BNXT_DESCS_PER_LOOP];
198 __m128i rxcmp[RTE_BNXT_DESCS_PER_LOOP];
199 __m128i tmp0, tmp1, info3_v;
202 /* Copy four mbuf pointers to output array. */
203 tmp0 = _mm_loadu_si128((void *)&rxr->rx_buf_ring[mbcons]);
204 #ifdef RTE_ARCH_X86_64
205 tmp1 = _mm_loadu_si128((void *)&rxr->rx_buf_ring[mbcons + 2]);
207 _mm_storeu_si128((void *)&rx_pkts[i], tmp0);
208 #ifdef RTE_ARCH_X86_64
209 _mm_storeu_si128((void *)&rx_pkts[i + 2], tmp1);
212 /* Prefetch four descriptor pairs for next iteration. */
213 if (i + RTE_BNXT_DESCS_PER_LOOP < nb_pkts) {
214 rte_prefetch0(&cp_desc_ring[cons + 8]);
215 rte_prefetch0(&cp_desc_ring[cons + 12]);
219 * Load the four current descriptors into SSE registers in
220 * reverse order to ensure consistent state.
222 rxcmp1[3] = _mm_load_si128((void *)&cp_desc_ring[cons + 7]);
223 rte_compiler_barrier();
224 rxcmp[3] = _mm_load_si128((void *)&cp_desc_ring[cons + 6]);
226 rxcmp1[2] = _mm_load_si128((void *)&cp_desc_ring[cons + 5]);
227 rte_compiler_barrier();
228 rxcmp[2] = _mm_load_si128((void *)&cp_desc_ring[cons + 4]);
230 tmp1 = _mm_unpackhi_epi32(rxcmp1[2], rxcmp1[3]);
232 rxcmp1[1] = _mm_load_si128((void *)&cp_desc_ring[cons + 3]);
233 rte_compiler_barrier();
234 rxcmp[1] = _mm_load_si128((void *)&cp_desc_ring[cons + 2]);
236 rxcmp1[0] = _mm_load_si128((void *)&cp_desc_ring[cons + 1]);
237 rte_compiler_barrier();
238 rxcmp[0] = _mm_load_si128((void *)&cp_desc_ring[cons + 0]);
240 tmp0 = _mm_unpackhi_epi32(rxcmp1[0], rxcmp1[1]);
242 /* Isolate descriptor valid flags. */
243 info3_v = _mm_and_si128(_mm_unpacklo_epi64(tmp0, tmp1),
245 info3_v = _mm_xor_si128(info3_v, valid_target);
248 * Pack the 128-bit array of valid descriptor flags into 64
249 * bits and count the number of set bits in order to determine
250 * the number of valid descriptors.
252 valid = _mm_cvtsi128_si64(_mm_packs_epi32(info3_v, info3_v));
253 num_valid = __builtin_popcountll(valid & desc_valid_mask);
257 rxr->rx_buf_ring[mbcons + 3] = NULL;
260 rxr->rx_buf_ring[mbcons + 2] = NULL;
263 rxr->rx_buf_ring[mbcons + 1] = NULL;
266 rxr->rx_buf_ring[mbcons + 0] = NULL;
272 descs_to_mbufs(rxcmp, rxcmp1, mbuf_init, &rx_pkts[nb_rx_pkts],
274 nb_rx_pkts += num_valid;
276 if (num_valid < RTE_BNXT_DESCS_PER_LOOP)
282 rxr->rx_raw_prod = RING_ADV(rxr->rx_raw_prod, nb_rx_pkts);
284 rxq->rxrearm_nb += nb_rx_pkts;
285 cpr->cp_raw_cons += 2 * nb_rx_pkts;
287 !!(cpr->cp_raw_cons & cpr->cp_ring_struct->ring_size);
295 bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
297 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
298 uint32_t raw_cons = cpr->cp_raw_cons;
300 uint32_t nb_tx_pkts = 0;
301 struct tx_cmpl *txcmp;
302 struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
303 struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
304 uint32_t ring_mask = cp_ring_struct->ring_mask;
307 cons = RING_CMPL(ring_mask, raw_cons);
308 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
310 if (!CMP_VALID(txcmp, raw_cons, cp_ring_struct))
313 if (likely(CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2))
314 nb_tx_pkts += txcmp->opaque;
317 "Unhandled CMP type %02x\n",
319 raw_cons = NEXT_RAW_CMP(raw_cons);
320 } while (nb_tx_pkts < ring_mask);
322 cpr->valid = !!(raw_cons & cp_ring_struct->ring_size);
324 if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE)
325 bnxt_tx_cmp_vec_fast(txq, nb_tx_pkts);
327 bnxt_tx_cmp_vec(txq, nb_tx_pkts);
328 cpr->cp_raw_cons = raw_cons;
334 bnxt_xmit_one(struct rte_mbuf *mbuf, struct tx_bd_long *txbd,
335 struct bnxt_sw_tx_bd *tx_buf)
342 desc = _mm_set_epi64x(mbuf->buf_iova + mbuf->data_off,
343 bnxt_xmit_flags_len(mbuf->data_len,
344 TX_BD_FLAGS_NOCMPL));
345 desc = _mm_blend_epi16(desc, _mm_set_epi16(0, 0, 0, 0, 0, 0,
346 mbuf->data_len, 0), 0x02);
347 _mm_store_si128((void *)txbd, desc);
351 bnxt_xmit_fixed_burst_vec(struct bnxt_tx_queue *txq, struct rte_mbuf **tx_pkts,
354 struct bnxt_tx_ring_info *txr = txq->tx_ring;
355 uint16_t tx_prod, tx_raw_prod = txr->tx_raw_prod;
356 struct tx_bd_long *txbd;
357 struct bnxt_sw_tx_bd *tx_buf;
360 tx_prod = RING_IDX(txr->tx_ring_struct, tx_raw_prod);
361 txbd = &txr->tx_desc_ring[tx_prod];
362 tx_buf = &txr->tx_buf_ring[tx_prod];
364 /* Prefetch next transmit buffer descriptors. */
366 rte_prefetch0(txbd + 3);
368 nb_pkts = RTE_MIN(nb_pkts, bnxt_tx_avail(txq));
370 if (unlikely(nb_pkts == 0))
373 /* Handle TX burst request */
375 while (to_send >= RTE_BNXT_DESCS_PER_LOOP) {
376 /* Prefetch next transmit buffer descriptors. */
377 rte_prefetch0(txbd + 4);
378 rte_prefetch0(txbd + 7);
380 bnxt_xmit_one(tx_pkts[0], txbd++, tx_buf++);
381 bnxt_xmit_one(tx_pkts[1], txbd++, tx_buf++);
382 bnxt_xmit_one(tx_pkts[2], txbd++, tx_buf++);
383 bnxt_xmit_one(tx_pkts[3], txbd++, tx_buf++);
385 to_send -= RTE_BNXT_DESCS_PER_LOOP;
386 tx_pkts += RTE_BNXT_DESCS_PER_LOOP;
390 bnxt_xmit_one(tx_pkts[0], txbd++, tx_buf++);
395 /* Request a completion for the final packet of burst. */
396 rte_compiler_barrier();
397 txbd[-1].opaque = nb_pkts;
398 txbd[-1].flags_type &= ~TX_BD_LONG_FLAGS_NO_CMPL;
400 tx_raw_prod += nb_pkts;
401 bnxt_db_write(&txr->tx_db, tx_raw_prod);
403 txr->tx_raw_prod = tx_raw_prod;
409 bnxt_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
413 struct bnxt_tx_queue *txq = tx_queue;
414 struct bnxt_tx_ring_info *txr = txq->tx_ring;
415 uint16_t ring_size = txr->tx_ring_struct->ring_size;
417 /* Tx queue was stopped; wait for it to be restarted */
418 if (unlikely(!txq->tx_started)) {
419 PMD_DRV_LOG(DEBUG, "Tx q stopped;return\n");
423 /* Handle TX completions */
424 if (bnxt_tx_bds_in_hw(txq) >= txq->tx_free_thresh)
425 bnxt_handle_tx_cp_vec(txq);
431 * Ensure that no more than RTE_BNXT_MAX_TX_BURST packets
432 * are transmitted before the next completion.
434 num = RTE_MIN(nb_pkts, RTE_BNXT_MAX_TX_BURST);
437 * Ensure that a ring wrap does not occur within a call to
438 * bnxt_xmit_fixed_burst_vec().
440 num = RTE_MIN(num, ring_size -
441 (txr->tx_raw_prod & (ring_size - 1)));
442 ret = bnxt_xmit_fixed_burst_vec(txq, &tx_pkts[nb_sent], num);
453 bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq)
455 return bnxt_rxq_vec_setup_common(rxq);