1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright(c) 2019 Broadcom All rights reserved. */
7 #include <rte_bitmap.h>
8 #include <rte_byteorder.h>
9 #include <rte_malloc.h>
10 #include <rte_memory.h>
11 #if defined(RTE_ARCH_X86)
12 #include <tmmintrin.h>
14 #error "bnxt vector pmd: unsupported target."
19 #include "bnxt_ring.h"
22 #include "hsi_struct_def_dpdk.h"
23 #include "bnxt_rxtx_vec_common.h"
33 bnxt_rxq_rearm(struct bnxt_rx_queue *rxq, struct bnxt_rx_ring_info *rxr)
35 struct rx_prod_pkt_bd *rxbds = &rxr->rx_desc_ring[rxq->rxrearm_start];
36 struct rte_mbuf **rx_bufs = &rxr->rx_buf_ring[rxq->rxrearm_start];
37 struct rte_mbuf *mb0, *mb1;
40 const __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM, 0);
41 const __m128i addrmask = _mm_set_epi64x(UINT64_MAX, 0);
43 /* Pull RTE_BNXT_RXQ_REARM_THRESH more mbufs into the software ring */
44 if (rte_mempool_get_bulk(rxq->mb_pool,
46 RTE_BNXT_RXQ_REARM_THRESH) < 0) {
47 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
48 RTE_BNXT_RXQ_REARM_THRESH;
53 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
54 for (i = 0; i < RTE_BNXT_RXQ_REARM_THRESH; i += 2, rx_bufs += 2) {
55 __m128i buf_addr0, buf_addr1;
61 /* Load address fields from both mbufs */
62 buf_addr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
63 buf_addr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
65 /* Load both rx descriptors (preserving some existing fields) */
66 rxbd0 = _mm_loadu_si128((__m128i *)(rxbds + 0));
67 rxbd1 = _mm_loadu_si128((__m128i *)(rxbds + 1));
69 /* Add default offset to buffer address. */
70 buf_addr0 = _mm_add_epi64(buf_addr0, hdr_room);
71 buf_addr1 = _mm_add_epi64(buf_addr1, hdr_room);
73 /* Clear all fields except address. */
74 buf_addr0 = _mm_and_si128(buf_addr0, addrmask);
75 buf_addr1 = _mm_and_si128(buf_addr1, addrmask);
77 /* Clear address field in descriptor. */
78 rxbd0 = _mm_andnot_si128(addrmask, rxbd0);
79 rxbd1 = _mm_andnot_si128(addrmask, rxbd1);
81 /* Set address field in descriptor. */
82 rxbd0 = _mm_add_epi64(rxbd0, buf_addr0);
83 rxbd1 = _mm_add_epi64(rxbd1, buf_addr1);
85 /* Store descriptors to memory. */
86 _mm_store_si128((__m128i *)(rxbds++), rxbd0);
87 _mm_store_si128((__m128i *)(rxbds++), rxbd1);
90 rxq->rxrearm_start += RTE_BNXT_RXQ_REARM_THRESH;
91 bnxt_db_write(&rxr->rx_db, rxq->rxrearm_start - 1);
92 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
93 rxq->rxrearm_start = 0;
95 rxq->rxrearm_nb -= RTE_BNXT_RXQ_REARM_THRESH;
99 bnxt_parse_pkt_type(struct rx_pkt_cmpl *rxcmp, struct rx_pkt_cmpl_hi *rxcmp1)
101 uint32_t l3, pkt_type = 0;
102 uint32_t t_ipcs = 0, ip6 = 0, vlan = 0;
105 vlan = !!(rxcmp1->flags2 &
106 rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN));
107 pkt_type |= vlan ? RTE_PTYPE_L2_ETHER_VLAN : RTE_PTYPE_L2_ETHER;
109 t_ipcs = !!(rxcmp1->flags2 &
110 rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC));
111 ip6 = !!(rxcmp1->flags2 &
112 rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_TYPE));
114 flags_type = rxcmp->flags_type &
115 rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS_ITYPE_MASK);
118 l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
119 else if (!t_ipcs && ip6)
120 l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
121 else if (t_ipcs && !ip6)
122 l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
124 l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
126 switch (flags_type) {
127 case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_ICMP):
129 pkt_type |= l3 | RTE_PTYPE_L4_ICMP;
131 pkt_type |= l3 | RTE_PTYPE_INNER_L4_ICMP;
134 case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_TCP):
136 pkt_type |= l3 | RTE_PTYPE_L4_TCP;
138 pkt_type |= l3 | RTE_PTYPE_INNER_L4_TCP;
141 case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_UDP):
143 pkt_type |= l3 | RTE_PTYPE_L4_UDP;
145 pkt_type |= l3 | RTE_PTYPE_INNER_L4_UDP;
148 case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_IP):
157 bnxt_parse_csum(struct rte_mbuf *mbuf, struct rx_pkt_cmpl_hi *rxcmp1)
161 flags = flags2_0xf(rxcmp1);
163 if (likely(IS_IP_NONTUNNEL_PKT(flags))) {
164 if (unlikely(RX_CMP_IP_CS_ERROR(rxcmp1)))
165 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
167 mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
168 } else if (IS_IP_TUNNEL_PKT(flags)) {
169 if (unlikely(RX_CMP_IP_OUTER_CS_ERROR(rxcmp1) ||
170 RX_CMP_IP_CS_ERROR(rxcmp1)))
171 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
173 mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
174 } else if (unlikely(RX_CMP_IP_CS_UNKNOWN(rxcmp1))) {
175 mbuf->ol_flags |= PKT_RX_IP_CKSUM_UNKNOWN;
179 if (likely(IS_L4_NONTUNNEL_PKT(flags))) {
180 if (unlikely(RX_CMP_L4_INNER_CS_ERR2(rxcmp1)))
181 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
183 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
184 } else if (IS_L4_TUNNEL_PKT(flags)) {
185 if (unlikely(RX_CMP_L4_INNER_CS_ERR2(rxcmp1)))
186 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
188 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
189 if (unlikely(RX_CMP_L4_OUTER_CS_ERR2(rxcmp1))) {
190 mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
191 } else if (unlikely(IS_L4_TUNNEL_PKT_ONLY_INNER_L4_CS
193 mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_UNKNOWN;
195 mbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
197 } else if (unlikely(RX_CMP_L4_CS_UNKNOWN(rxcmp1))) {
198 mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
203 bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
206 struct bnxt_rx_queue *rxq = rx_queue;
207 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
208 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
209 uint32_t raw_cons = cpr->cp_raw_cons;
212 struct rx_pkt_cmpl *rxcmp;
213 const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
214 const __m128i shuf_msk =
215 _mm_set_epi8(15, 14, 13, 12, /* rss */
216 0xFF, 0xFF, /* vlan_tci (zeroes) */
218 0xFF, 0xFF, 3, 2, /* pkt_len */
219 0xFF, 0xFF, 0xFF, 0xFF); /* pkt_type (zeroes) */
222 /* If Rx Q was stopped return */
223 if (unlikely(!rxq->rx_started))
226 if (rxq->rxrearm_nb >= RTE_BNXT_RXQ_REARM_THRESH)
227 bnxt_rxq_rearm(rxq, rxr);
229 /* Return no more than RTE_BNXT_MAX_RX_BURST per call. */
230 nb_pkts = RTE_MIN(nb_pkts, RTE_BNXT_MAX_RX_BURST);
233 * Make nb_pkts an integer multiple of RTE_BNXT_DESCS_PER_LOOP.
234 * nb_pkts < RTE_BNXT_DESCS_PER_LOOP, just return no packet
236 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_BNXT_DESCS_PER_LOOP);
240 /* Handle RX burst request */
241 for (i = 0; i < nb_pkts; i++) {
242 struct rx_pkt_cmpl_hi *rxcmp1;
243 struct rte_mbuf *mbuf;
244 __m128i mm_rxcmp, pkt_mb;
246 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
248 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
249 rxcmp1 = (struct rx_pkt_cmpl_hi *)&cpr->cp_desc_ring[cons + 1];
251 if (!CMP_VALID(rxcmp1, raw_cons + 1, cpr->cp_ring_struct))
255 cons = rxcmp->opaque;
257 mbuf = rxr->rx_buf_ring[cons];
259 rxr->rx_buf_ring[cons] = NULL;
261 /* Set constant fields from mbuf initializer. */
262 _mm_store_si128((__m128i *)&mbuf->rearm_data, mbuf_init);
264 /* Set mbuf pkt_len, data_len, and rss_hash fields. */
265 mm_rxcmp = _mm_load_si128((__m128i *)rxcmp);
266 pkt_mb = _mm_shuffle_epi8(mm_rxcmp, shuf_msk);
267 _mm_storeu_si128((void *)&mbuf->rx_descriptor_fields1, pkt_mb);
269 rte_compiler_barrier();
271 if (rxcmp->flags_type & RX_PKT_CMPL_FLAGS_RSS_VALID)
272 mbuf->ol_flags |= PKT_RX_RSS_HASH;
275 RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN) {
276 mbuf->vlan_tci = rxcmp1->metadata &
277 (RX_PKT_CMPL_METADATA_VID_MASK |
278 RX_PKT_CMPL_METADATA_DE |
279 RX_PKT_CMPL_METADATA_PRI_MASK);
281 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
284 bnxt_parse_csum(mbuf, rxcmp1);
285 mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);
287 rx_pkts[nb_rx_pkts++] = mbuf;
292 RING_ADV(rxr->rx_ring_struct, rxr->rx_prod, nb_rx_pkts);
294 rxq->rxrearm_nb += nb_rx_pkts;
295 cpr->cp_raw_cons = raw_cons;
297 !!(cpr->cp_raw_cons & cpr->cp_ring_struct->ring_size);
305 bnxt_tx_cmp_vec(struct bnxt_tx_queue *txq, int nr_pkts)
307 struct bnxt_tx_ring_info *txr = txq->tx_ring;
308 struct rte_mbuf **free = txq->free;
309 uint16_t cons = txr->tx_cons;
310 unsigned int blk = 0;
313 struct bnxt_sw_tx_bd *tx_buf;
314 struct rte_mbuf *mbuf;
316 tx_buf = &txr->tx_buf_ring[cons];
317 cons = RING_NEXT(txr->tx_ring_struct, cons);
318 mbuf = rte_pktmbuf_prefree_seg(tx_buf->mbuf);
319 if (unlikely(mbuf == NULL))
323 if (blk && mbuf->pool != free[0]->pool) {
324 rte_mempool_put_bulk(free[0]->pool, (void **)free, blk);
330 rte_mempool_put_bulk(free[0]->pool, (void **)free, blk);
336 bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
338 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
339 uint32_t raw_cons = cpr->cp_raw_cons;
341 uint32_t nb_tx_pkts = 0;
342 struct tx_cmpl *txcmp;
343 struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
344 struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
345 uint32_t ring_mask = cp_ring_struct->ring_mask;
348 cons = RING_CMPL(ring_mask, raw_cons);
349 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
351 if (!CMP_VALID(txcmp, raw_cons, cp_ring_struct))
354 if (likely(CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2))
355 nb_tx_pkts += txcmp->opaque;
358 "Unhandled CMP type %02x\n",
360 raw_cons = NEXT_RAW_CMP(raw_cons);
361 } while (nb_tx_pkts < ring_mask);
363 cpr->valid = !!(raw_cons & cp_ring_struct->ring_size);
365 bnxt_tx_cmp_vec(txq, nb_tx_pkts);
366 cpr->cp_raw_cons = raw_cons;
372 bnxt_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
375 struct bnxt_tx_queue *txq = tx_queue;
376 struct bnxt_tx_ring_info *txr = txq->tx_ring;
377 uint16_t prod = txr->tx_prod;
378 struct rte_mbuf *tx_mbuf;
379 struct tx_bd_long *txbd = NULL;
380 struct bnxt_sw_tx_bd *tx_buf;
383 nb_pkts = RTE_MIN(nb_pkts, bnxt_tx_avail(txq));
385 if (unlikely(nb_pkts == 0))
388 /* Handle TX burst request */
391 tx_mbuf = *tx_pkts++;
392 rte_prefetch0(tx_mbuf);
394 tx_buf = &txr->tx_buf_ring[prod];
395 tx_buf->mbuf = tx_mbuf;
398 txbd = &txr->tx_desc_ring[prod];
399 txbd->address = tx_mbuf->buf_iova + tx_mbuf->data_off;
400 txbd->len = tx_mbuf->data_len;
401 txbd->flags_type = bnxt_xmit_flags_len(tx_mbuf->data_len,
403 prod = RING_NEXT(txr->tx_ring_struct, prod);
407 /* Request a completion for last packet in burst */
409 txbd->opaque = nb_pkts;
410 txbd->flags_type &= ~TX_BD_LONG_FLAGS_NO_CMPL;
413 rte_compiler_barrier();
414 bnxt_db_write(&txr->tx_db, prod);
422 bnxt_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
426 struct bnxt_tx_queue *txq = tx_queue;
428 /* Tx queue was stopped; wait for it to be restarted */
429 if (unlikely(!txq->tx_started)) {
430 PMD_DRV_LOG(DEBUG, "Tx q stopped;return\n");
434 /* Handle TX completions */
435 if (bnxt_tx_bds_in_hw(txq) >= txq->tx_free_thresh)
436 bnxt_handle_tx_cp_vec(txq);
441 num = RTE_MIN(nb_pkts, RTE_BNXT_MAX_TX_BURST);
442 ret = bnxt_xmit_fixed_burst_vec(tx_queue,
455 bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq)
457 return bnxt_rxq_vec_setup_common(rxq);