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34 #ifndef _HSI_STRUCT_DEF_EXTERNAL_H_
35 #define _HSI_STRUCT_DEF_EXTERNAL_H_
38 * per-context HW statistics -- chip view
41 struct ctx_hw_stats64 {
42 uint64_t rx_ucast_pkts;
43 uint64_t rx_mcast_pkts;
44 uint64_t rx_bcast_pkts;
45 uint64_t rx_drop_pkts;
46 uint64_t rx_discard_pkts;
47 uint64_t rx_ucast_bytes;
48 uint64_t rx_mcast_bytes;
49 uint64_t rx_bcast_bytes;
51 uint64_t tx_ucast_pkts;
52 uint64_t tx_mcast_pkts;
53 uint64_t tx_bcast_pkts;
54 uint64_t tx_drop_pkts;
55 uint64_t tx_discard_pkts;
56 uint64_t tx_ucast_bytes;
57 uint64_t tx_mcast_bytes;
58 uint64_t tx_bcast_bytes;
64 } __attribute__((packed));
66 /* HW Resource Manager Specification 1.5.1 */
67 #define HWRM_VERSION_MAJOR 1
68 #define HWRM_VERSION_MINOR 5
69 #define HWRM_VERSION_UPDATE 1
71 #define HWRM_VERSION_STR "1.5.1"
74 * Following is the signature for HWRM message field that indicates not
75 * applicable (All F's). Need to cast it the size of the field if needed.
77 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
78 #define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */
79 #define HWRM_MAX_RESP_LEN (176) /* hwrm_func_qstats */
80 #define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */
81 #define HW_HASH_KEY_SIZE 40
82 #define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */
87 #define HWRM_VER_GET (UINT32_C(0x0))
88 #define HWRM_FUNC_RESET (UINT32_C(0x11))
89 #define HWRM_FUNC_QCAPS (UINT32_C(0x15))
90 #define HWRM_FUNC_QCFG (UINT32_C(0x16))
91 #define HWRM_FUNC_DRV_UNRGTR (UINT32_C(0x1a))
92 #define HWRM_FUNC_DRV_RGTR (UINT32_C(0x1d))
93 #define HWRM_PORT_PHY_CFG (UINT32_C(0x20))
94 #define HWRM_PORT_PHY_QCFG (UINT32_C(0x27))
95 #define HWRM_QUEUE_QPORTCFG (UINT32_C(0x30))
96 #define HWRM_VNIC_ALLOC (UINT32_C(0x40))
97 #define HWRM_VNIC_FREE (UINT32_C(0x41))
98 #define HWRM_VNIC_CFG (UINT32_C(0x42))
99 #define HWRM_VNIC_RSS_CFG (UINT32_C(0x46))
100 #define HWRM_RING_ALLOC (UINT32_C(0x50))
101 #define HWRM_RING_FREE (UINT32_C(0x51))
102 #define HWRM_RING_GRP_ALLOC (UINT32_C(0x60))
103 #define HWRM_RING_GRP_FREE (UINT32_C(0x61))
104 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (UINT32_C(0x70))
105 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (UINT32_C(0x71))
106 #define HWRM_CFA_L2_FILTER_ALLOC (UINT32_C(0x90))
107 #define HWRM_CFA_L2_FILTER_FREE (UINT32_C(0x91))
108 #define HWRM_CFA_L2_FILTER_CFG (UINT32_C(0x92))
109 #define HWRM_CFA_L2_SET_RX_MASK (UINT32_C(0x93))
110 #define HWRM_STAT_CTX_ALLOC (UINT32_C(0xb0))
111 #define HWRM_STAT_CTX_FREE (UINT32_C(0xb1))
112 #define HWRM_STAT_CTX_CLR_STATS (UINT32_C(0xb3))
113 #define HWRM_EXEC_FWD_RESP (UINT32_C(0xd0))
116 #define HWRM_ERR_CODE_INVALID_PARAMS (UINT32_C(0x2))
117 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (UINT32_C(0x3))
119 /* Short TX BD (16 bytes) */
123 * All bits in this field must be valid on the first BD of a
124 * packet. Only the packet_end bit must be valid for the
125 * remaining BDs of a packet.
127 /* This value identifies the type of buffer descriptor. */
128 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
129 #define TX_BD_SHORT_TYPE_SFT 0
131 * Indicates that this BD is 16B long and is
132 * used for normal L2 packet transmission.
134 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
136 * If set to 1, the packet ends with the data in the buffer
137 * pointed to by this descriptor. This flag must be valid on
140 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
142 * If set to 1, the device will not generate a completion for
143 * this transmit packet unless there is an error in it's
144 * processing. If this bit is set to 0, then the packet will be
145 * completed normally. This bit must be valid only on the first
148 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
150 * This value indicates how many 16B BD locations are consumed
151 * in the ring by this packet. A value of 1 indicates that this
152 * BD is the only BD (and that the it is a short BD). A value of
153 * 3 indicates either 3 short BDs or 1 long BD and one short BD
154 * in the packet. A value of 0 indicates that there are 32 BD
155 * locations in the packet (the maximum). This field is valid
156 * only on the first BD of a packet.
158 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
159 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
161 * This value is a hint for the length of the entire packet. It
162 * is used by the chip to optimize internal processing. The
163 * packet will be dropped if the hint is too short. This field
164 * is valid only on the first BD of a packet.
166 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
167 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
168 /* indicates packet length < 512B */
169 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
170 /* indicates 512 <= packet length < 1KB */
171 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
172 /* indicates 1KB <= packet length < 2KB */
173 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
174 /* indicates packet length >= 2KB */
175 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
176 #define TX_BD_SHORT_FLAGS_LHINT_LAST TX_BD_SHORT_FLAGS_LHINT_GTE2K
178 * If set to 1, the device immediately updates the Send Consumer
179 * Index after the buffer associated with this descriptor has
180 * been transferred via DMA to NIC memory from host memory. An
181 * interrupt may or may not be generated according to the state
182 * of the interrupt avoidance mechanisms. If this bit is set to
183 * 0, then the Consumer Index is only updated as soon as one of
184 * the host interrupt coalescing conditions has been met. This
185 * bit must be valid on the first BD of a packet.
187 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
189 * All bits in this field must be valid on the first BD of a
190 * packet. Only the packet_end bit must be valid for the
191 * remaining BDs of a packet.
193 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
194 #define TX_BD_SHORT_FLAGS_SFT 6
197 * This is the length of the host physical buffer this BD
198 * describes in bytes. This field must be valid on all BDs of a
203 * The opaque data field is pass through to the completion and
204 * can be used for any data that the driver wants to associate
205 * with the transmit BD. This field must be valid on the first
210 * This is the host physical address for the portion of the
211 * packet described by this TX BD. This value must be valid on
212 * all BDs of a packet.
214 } __attribute__((packed));
216 /* Long TX BD (32 bytes split to 2 16-byte struct) */
220 * All bits in this field must be valid on the first BD of a
221 * packet. Only the packet_end bit must be valid for the
222 * remaining BDs of a packet.
224 /* This value identifies the type of buffer descriptor. */
225 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
226 #define TX_BD_LONG_TYPE_SFT 0
228 * Indicates that this BD is 32B long and is
229 * used for normal L2 packet transmission.
231 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
233 * If set to 1, the packet ends with the data in the buffer
234 * pointed to by this descriptor. This flag must be valid on
237 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
239 * If set to 1, the device will not generate a completion for
240 * this transmit packet unless there is an error in it's
241 * processing. If this bit is set to 0, then the packet will be
242 * completed normally. This bit must be valid only on the first
245 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
247 * This value indicates how many 16B BD locations are consumed
248 * in the ring by this packet. A value of 1 indicates that this
249 * BD is the only BD (and that the it is a short BD). A value of
250 * 3 indicates either 3 short BDs or 1 long BD and one short BD
251 * in the packet. A value of 0 indicates that there are 32 BD
252 * locations in the packet (the maximum). This field is valid
253 * only on the first BD of a packet.
255 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
256 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
258 * This value is a hint for the length of the entire packet. It
259 * is used by the chip to optimize internal processing. The
260 * packet will be dropped if the hint is too short. This field
261 * is valid only on the first BD of a packet.
263 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
264 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
265 /* indicates packet length < 512B */
266 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
267 /* indicates 512 <= packet length < 1KB */
268 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
269 /* indicates 1KB <= packet length < 2KB */
270 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
271 /* indicates packet length >= 2KB */
272 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
273 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
275 * If set to 1, the device immediately updates the Send Consumer
276 * Index after the buffer associated with this descriptor has
277 * been transferred via DMA to NIC memory from host memory. An
278 * interrupt may or may not be generated according to the state
279 * of the interrupt avoidance mechanisms. If this bit is set to
280 * 0, then the Consumer Index is only updated as soon as one of
281 * the host interrupt coalescing conditions has been met. This
282 * bit must be valid on the first BD of a packet.
284 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
286 * All bits in this field must be valid on the first BD of a
287 * packet. Only the packet_end bit must be valid for the
288 * remaining BDs of a packet.
290 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
291 #define TX_BD_LONG_FLAGS_SFT 6
294 * This is the length of the host physical buffer this BD
295 * describes in bytes. This field must be valid on all BDs of a
300 * The opaque data field is pass through to the completion and
301 * can be used for any data that the driver wants to associate
302 * with the transmit BD. This field must be valid on the first
307 * This is the host physical address for the portion of the
308 * packet described by this TX BD. This value must be valid on
309 * all BDs of a packet.
311 } __attribute__((packed));
313 /* last 16 bytes of Long TX BD */
314 struct tx_bd_long_hi {
317 * All bits in this field must be valid on the first BD of a
318 * packet. Their value on other BDs of the packet will be
322 * If set to 1, the controller replaces the TCP/UPD checksum
323 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
324 * checksum field of the encapsulated TCP/UDP packets with the
325 * hardware calculated TCP/UDP checksum for the packet
326 * associated with this descriptor. The flag is ignored if the
327 * LSO flag is set. This bit must be valid on the first BD of a
330 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
332 * If set to 1, the controller replaces the IP checksum of the
333 * normal packets, or the inner IP checksum of the encapsulated
334 * packets with the hardware calculated IP checksum for the
335 * packet associated with this descriptor. This bit must be
336 * valid on the first BD of a packet.
338 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
340 * If set to 1, the controller will not append an Ethernet CRC
341 * to the end of the frame. This bit must be valid on the first
342 * BD of a packet. Packet must be 64B or longer when this flag
343 * is set. It is not useful to use this bit with any form of TX
344 * offload such as CSO or LSO. The intent is that the packet
345 * from the host already has a valid Ethernet CRC on the packet.
347 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
349 * If set to 1, the device will record the time at which the
350 * packet was actually transmitted at the TX MAC. This bit must
351 * be valid on the first BD of a packet.
353 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
355 * If set to 1, The controller replaces the tunnel IP checksum
356 * field with hardware calculated IP checksum for the IP header
357 * of the packet associated with this descriptor. For outer UDP
358 * checksum, global outer UDP checksum TE_NIC register needs to
359 * be enabled. If the global outer UDP checksum TE_NIC register
360 * bit is set, outer UDP checksum will be calculated for the
361 * following cases: 1. Packets with tcp_udp_chksum flag set to
362 * offload checksum for inner packet AND the inner packet is
363 * TCP/UDP. If the inner packet is ICMP for example (non-
364 * TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
365 * checksum will not be calculated. 2. Packets with lso flag set
366 * which implies inner TCP checksum calculation as part of LSO
369 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
371 * If set to 1, the device will treat this packet with LSO(Large
372 * Send Offload) processing for both normal or encapsulated
373 * packets, which is a form of TCP segmentation. When this bit
374 * is 1, the hdr_size and mss fields must be valid. The driver
375 * doesn't need to set t_ip_chksum, ip_chksum, and
376 * tcp_udp_chksum flags since the controller will replace the
377 * appropriate checksum fields for segmented packets. When this
378 * bit is 1, the hdr_size and mss fields must be valid.
380 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
382 * If set to zero when LSO is '1', then the IPID will be treated
383 * as a 16b number and will be wrapped if it exceeds a value of
384 * 0xffff. If set to one when LSO is '1', then the IPID will be
385 * treated as a 15b number and will be wrapped if it exceeds a
388 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
390 * If set to zero when LSO is '1', then the IPID of the tunnel
391 * IP header will not be modified during LSO operations. If set
392 * to one when LSO is '1', then the IPID of the tunnel IP header
393 * will be incremented for each subsequent segment of an LSO
394 * operation. The flag is ignored if the LSO packet is a normal
395 * (non-tunneled) TCP packet.
397 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
399 * If set to '1', then the RoCE ICRC will be appended to the
400 * packet. Packet must be a valid RoCE format packet.
402 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
404 * If set to '1', then the FCoE CRC will be appended to the
405 * packet. Packet must be a valid FCoE format packet.
407 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
410 * When LSO is '1', this field must contain the offset of the
411 * TCP payload from the beginning of the packet in as 16b words.
412 * In case of encapsulated/tunneling packet, this field contains
413 * the offset of the inner TCP payload from beginning of the
414 * packet as 16-bit words. This value must be valid on the first
417 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
418 #define TX_BD_LONG_HDR_SIZE_SFT 0
421 * This is the MSS value that will be used to do the LSO
422 * processing. The value is the length in bytes of the TCP
423 * payload for each segment generated by the LSO operation. This
424 * value must be valid on the first BD of a packet.
426 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
427 #define TX_BD_LONG_MSS_SFT 0
431 * This value selects a CFA action to perform on the packet. Set
432 * this value to zero if no CFA action is desired. This value
433 * must be valid on the first BD of a packet.
437 * This value is action meta-data that defines CFA edit
438 * operations that are done in addition to any action editing.
440 /* When key=1, This is the VLAN tag VID value. */
441 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
442 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
443 /* When key=1, This is the VLAN tag DE value. */
444 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
445 /* When key=1, This is the VLAN tag PRI value. */
446 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
447 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
448 /* When key=1, This is the VLAN tag TPID select value. */
449 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
450 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
452 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
454 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
456 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
458 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
460 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
461 /* Value programmed in CFA VLANTPID register. */
462 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
463 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
464 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
465 /* When key=1, This is the VLAN tag TPID select value. */
466 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
467 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
469 * This field identifies the type of edit to be performed on the
470 * packet. This value must be valid on the first BD of a packet.
472 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
473 #define TX_BD_LONG_CFA_META_KEY_SFT 28
475 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
477 * - meta[17:16] - TPID select value (0 =
478 * 0x8100). - meta[15:12] - PRI/DE value. -
479 * meta[11:0] - VID value.
481 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
482 #define TX_BD_LONG_CFA_META_KEY_LAST TX_BD_LONG_CFA_META_KEY_VLAN_TAG
483 } __attribute__((packed));
485 /* RX Producer Packet BD (16 bytes) */
486 struct rx_prod_pkt_bd {
488 /* This value identifies the type of buffer descriptor. */
489 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
490 #define RX_PROD_PKT_BD_TYPE_SFT 0
492 * Indicates that this BD is 16B long and is an
493 * RX Producer (ie. empty) buffer descriptor.
495 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
497 * If set to 1, the packet will be placed at the address plus
498 * 2B. The 2 Bytes of padding will be written as zero.
501 * This is intended to be used when the host buffer is cache-
502 * line aligned to produce packets that are easy to parse in
503 * host memory while still allowing writes to be cache line
506 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
508 * If set to 1, the packet write will be padded out to the
509 * nearest cache-line with zero value padding.
512 * If receive buffers start/end on cache-line boundaries, this
513 * feature will ensure that all data writes on the PCI bus
514 * start/end on cache line boundaries.
516 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
518 * This value is the number of additional buffers in the ring
519 * that describe the buffer space to be consumed for the this
520 * packet. If the value is zero, then the packet must fit within
521 * the space described by this BD. If this value is 1 or more,
522 * it indicates how many additional "buffer" BDs are in the ring
523 * immediately following this BD to be used for the same network
524 * packet. Even if the packet to be placed does not need all the
525 * additional buffers, they will be consumed anyway.
527 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
528 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
529 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
530 #define RX_PROD_PKT_BD_FLAGS_SFT 6
533 * This is the length in Bytes of the host physical buffer where
534 * data for the packet may be placed in host memory.
537 * While this is a Byte resolution value, it is often
538 * advantageous to ensure that the buffers provided end on a
543 * The opaque data field is pass through to the completion and
544 * can be used for any data that the driver wants to associate
545 * with this receive buffer set.
549 * This is the host physical address where data for the packet
550 * may by placed in host memory.
553 * While this is a Byte resolution value, it is often
554 * advantageous to ensure that the buffers provide start on a
557 } __attribute__((packed));
559 /* Completion Ring Structures */
560 /* Note: This structure is used by the HWRM to communicate HWRM Error. */
561 /* Base Completion Record (16 bytes) */
566 * This field indicates the exact type of the completion. By
567 * convention, the LSB identifies the length of the record in
568 * 16B units. Even values indicate 16B records. Odd values
569 * indicate 32B records.
571 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
572 #define CMPL_BASE_TYPE_SFT 0
573 /* TX L2 completion: Completion of TX packet. Length = 16B */
574 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
576 * RX L2 completion: Completion of and L2 RX
577 * packet. Length = 32B
579 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
581 * RX Aggregation Buffer completion : Completion
582 * of an L2 aggregation buffer in support of
583 * TPA, HDS, or Jumbo packet completion. Length
586 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
588 * RX L2 TPA Start Completion: Completion at the
589 * beginning of a TPA operation. Length = 32B
591 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
593 * RX L2 TPA End Completion: Completion at the
594 * end of a TPA operation. Length = 32B
596 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
598 * Statistics Ejection Completion: Completion of
599 * statistics data ejection buffer. Length = 16B
601 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
602 /* HWRM Command Completion: Completion of an HWRM command. */
603 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
604 /* Forwarded HWRM Request */
605 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
606 /* Forwarded HWRM Response */
607 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
608 /* HWRM Asynchronous Event Information */
609 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
610 /* CQ Notification */
611 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
612 /* SRQ Threshold Event */
613 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
614 /* DBQ Threshold Event */
615 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
616 /* QP Async Notification */
617 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
618 /* Function Async Notification */
619 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
628 * This value is written by the NIC such that it will be
629 * different for each pass through the completion queue. The
630 * even passes will write 1. The odd passes will write 0.
632 #define CMPL_BASE_V UINT32_C(0x1)
634 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
635 #define CMPL_BASE_INFO3_SFT 1
638 } __attribute__((packed));
640 /* TX Completion Record (16 bytes) */
644 * This field indicates the exact type of the completion. By
645 * convention, the LSB identifies the length of the record in
646 * 16B units. Even values indicate 16B records. Odd values
647 * indicate 32B records.
649 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
650 #define TX_CMPL_TYPE_SFT 0
651 /* TX L2 completion: Completion of TX packet. Length = 16B */
652 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
654 * When this bit is '1', it indicates a packet that has an error
655 * of some type. Type of error is indicated in error_flags.
657 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
659 * When this bit is '1', it indicates that the packet completed
660 * was transmitted using the push acceleration data provided by
661 * the driver. When this bit is '0', it indicates that the
662 * packet had not push acceleration data written or was executed
663 * as a normal packet even though push data was provided.
665 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
666 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
667 #define TX_CMPL_FLAGS_SFT 6
669 /* unused1 is 16 b */
672 * This is a copy of the opaque field from the first TX BD of
673 * this transmitted packet.
677 * This value is written by the NIC such that it will be
678 * different for each pass through the completion queue. The
679 * even passes will write 1. The odd passes will write 0.
681 #define TX_CMPL_V UINT32_C(0x1)
683 * This error indicates that there was some sort of problem with
684 * the BDs for the packet.
686 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
687 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
689 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
690 /* Bad Format: BDs were not formatted correctly. */
691 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
692 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
693 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
695 * When this bit is '1', it indicates that the length of the
696 * packet was zero. No packet was transmitted.
698 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
700 * When this bit is '1', it indicates that the packet was longer
701 * than the programmed limit in TDI. No packet was transmitted.
703 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
705 * When this bit is '1', it indicates that one or more of the
706 * BDs associated with this packet generated a PCI error. This
707 * probably means the address was not valid.
709 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
711 * When this bit is '1', it indicates that the packet was longer
712 * than indicated by the hint. No packet was transmitted.
714 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
716 * When this bit is '1', it indicates that the packet was
717 * dropped due to Poison TLP error on one or more of the TLPs in
718 * the PXP completion.
720 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
721 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
722 #define TX_CMPL_ERRORS_SFT 1
724 /* unused2 is 16 b */
726 /* unused3 is 32 b */
727 } __attribute__((packed));
729 /* RX Packet Completion Record (32 bytes split to 2 16-byte struct) */
733 * This field indicates the exact type of the completion. By
734 * convention, the LSB identifies the length of the record in
735 * 16B units. Even values indicate 16B records. Odd values
736 * indicate 32B records.
738 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
739 #define RX_PKT_CMPL_TYPE_SFT 0
741 * RX L2 completion: Completion of and L2 RX
742 * packet. Length = 32B
744 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
746 * When this bit is '1', it indicates a packet that has an error
747 * of some type. Type of error is indicated in error_flags.
749 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
750 /* This field indicates how the packet was placed in the buffer. */
751 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
752 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
753 /* Normal: Packet was placed using normal algorithm. */
754 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
755 /* Jumbo: Packet was placed using jumbo algorithm. */
756 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
758 * Header/Data Separation: Packet was placed
759 * using Header/Data separation algorithm. The
760 * separation location is indicated by the itype
763 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
764 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
765 /* This bit is '1' if the RSS field in this completion is valid. */
766 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
769 * This value indicates what the inner packet determined for the
772 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
773 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
774 /* Not Known: Indicates that the packet type was not known. */
775 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 12)
777 * IP Packet: Indicates that the packet was an
778 * IP packet, but further classification was not
781 #define RX_PKT_CMPL_FLAGS_ITYPE_IP (UINT32_C(0x1) << 12)
783 * TCP Packet: Indicates that the packet was IP
784 * and TCP. This indicates that the
785 * payload_offset field is valid.
787 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
789 * UDP Packet: Indicates that the packet was IP
790 * and UDP. This indicates that the
791 * payload_offset field is valid.
793 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 12)
795 * FCoE Packet: Indicates that the packet was
796 * recognized as a FCoE. This also indicates
797 * that the payload_offset field is valid.
799 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 12)
801 * RoCE Packet: Indicates that the packet was
802 * recognized as a RoCE. This also indicates
803 * that the payload_offset field is valid.
805 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 12)
807 * ICMP Packet: Indicates that the packet was
808 * recognized as ICMP. This indicates that the
809 * payload_offset field is valid.
811 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 12)
813 * PtP packet wo/timestamp: Indicates that the
814 * packet was recognized as a PtP packet.
816 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 12)
818 * PtP packet w/timestamp: Indicates that the
819 * packet was recognized as a PtP packet and
820 * that a timestamp was taken for the packet.
822 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 12)
823 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
824 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
825 #define RX_PKT_CMPL_FLAGS_SFT 6
828 * This is the length of the data for the packet stored in the
829 * buffer(s) identified by the opaque value. This includes the
830 * packet BD and any associated buffer BDs. This does not
831 * include the the length of any data places in aggregation BDs.
835 * This is a copy of the opaque field from the RX BD this
836 * completion corresponds to.
841 * This value is written by the NIC such that it will be
842 * different for each pass through the completion queue. The
843 * even passes will write 1. The odd passes will write 0.
845 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
847 * This value is the number of aggregation buffers that follow
848 * this entry in the completion ring that are a part of this
849 * packet. If the value is zero, then the packet is completely
850 * contained in the buffer space provided for the packet in the
853 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
854 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
856 uint8_t rss_hash_type;
858 * This is the RSS hash type for the packet. The value is packed
859 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}
860 * . The value of tuple_extrac_op provides the information about
861 * what fields the hash was computed on. * 0: The RSS hash was
862 * computed over source IP address, destination IP address,
863 * source port, and destination port of inner IP and TCP or UDP
864 * headers. Note: For non-tunneled packets, the packet headers
865 * are considered inner packet headers for the RSS hash
866 * computation purpose. * 1: The RSS hash was computed over
867 * source IP address and destination IP address of inner IP
868 * header. Note: For non-tunneled packets, the packet headers
869 * are considered inner packet headers for the RSS hash
870 * computation purpose. * 2: The RSS hash was computed over
871 * source IP address, destination IP address, source port, and
872 * destination port of IP and TCP or UDP headers of outer tunnel
873 * headers. Note: For non-tunneled packets, this value is not
874 * applicable. * 3: The RSS hash was computed over source IP
875 * address and destination IP address of IP header of outer
876 * tunnel headers. Note: For non-tunneled packets, this value is
877 * not applicable. Note that 4-tuples values listed above are
878 * applicable for layer 4 protocols supported and enabled for
879 * RSS in the hardware, HWRM firmware, and drivers. For example,
880 * if RSS hash is supported and enabled for TCP traffic only,
881 * then the values of tuple_extract_op corresponding to 4-tuples
882 * are only valid for TCP traffic.
884 uint8_t payload_offset;
886 * This value indicates the offset in bytes from the beginning
887 * of the packet where the inner payload starts. This value is
888 * valid for TCP, UDP, FCoE, and RoCE packets. A value of zero
889 * indicates that header is 256B into the packet.
895 * This value is the RSS hash value calculated for the packet
896 * based on the mode bits and key value in the VNIC.
898 } __attribute__((packed));
900 /* last 16 bytes of RX Packet Completion Record */
901 struct rx_pkt_cmpl_hi {
904 * This indicates that the ip checksum was calculated for the
905 * inner packet and that the ip_cs_error field indicates if
906 * there was an error.
908 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
910 * This indicates that the TCP, UDP or ICMP checksum was
911 * calculated for the inner packet and that the l4_cs_error
912 * field indicates if there was an error.
914 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
916 * This indicates that the ip checksum was calculated for the
917 * tunnel header and that the t_ip_cs_error field indicates if
918 * there was an error.
920 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
922 * This indicates that the UDP checksum was calculated for the
923 * tunnel packet and that the t_l4_cs_error field indicates if
924 * there was an error.
926 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
927 /* This value indicates what format the metadata field is. */
928 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
929 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
930 /* No metadata informtaion. Value is zero. */
931 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
933 * The metadata field contains the VLAN tag and
934 * TPID value. - metadata[11:0] contains the
935 * vlan VID value. - metadata[12] contains the
936 * vlan DE value. - metadata[15:13] contains the
937 * vlan PRI value. - metadata[31:16] contains
938 * the vlan TPID value.
940 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
941 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
942 RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN
944 * This field indicates the IP type for the inner-most IP
945 * header. A value of '0' indicates IPv4. A value of '1'
946 * indicates IPv6. This value is only valid if itype indicates a
947 * packet with an IP header.
949 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
952 * This is data from the CFA block as indicated by the
955 /* When meta_format=1, this value is the VLAN VID. */
956 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
957 #define RX_PKT_CMPL_METADATA_VID_SFT 0
958 /* When meta_format=1, this value is the VLAN DE. */
959 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
960 /* When meta_format=1, this value is the VLAN PRI. */
961 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
962 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
963 /* When meta_format=1, this value is the VLAN TPID. */
964 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
965 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
968 * This value is written by the NIC such that it will be
969 * different for each pass through the completion queue. The
970 * even passes will write 1. The odd passes will write 0.
972 #define RX_PKT_CMPL_V2 UINT32_C(0x1)
974 * This error indicates that there was some sort of problem with
975 * the BDs for the packet that was found after part of the
976 * packet was already placed. The packet should be treated as
979 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
980 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
981 /* No buffer error */
982 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (UINT32_C(0x0) << 1)
984 * Did Not Fit: Packet did not fit into packet
985 * buffer provided. For regular placement, this
986 * means the packet did not fit in the buffer
987 * provided. For HDS and jumbo placement, this
988 * means that the packet could not be placed
989 * into 7 physical buffers or less.
991 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (UINT32_C(0x1) << 1)
993 * Not On Chip: All BDs needed for the packet
994 * were not on-chip when the packet arrived.
996 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (UINT32_C(0x2) << 1)
997 /* Bad Format: BDs were not formatted correctly. */
998 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (UINT32_C(0x3) << 1)
999 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
1000 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT
1001 /* This indicates that there was an error in the IP header checksum. */
1002 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR UINT32_C(0x10)
1004 * This indicates that there was an error in the TCP, UDP or
1007 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR UINT32_C(0x20)
1009 * This indicates that there was an error in the tunnel IP
1012 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR UINT32_C(0x40)
1014 * This indicates that there was an error in the tunnel UDP
1017 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR UINT32_C(0x80)
1019 * This indicates that there was a CRC error on either an FCoE
1020 * or RoCE packet. The itype indicates the packet type.
1022 #define RX_PKT_CMPL_ERRORS_CRC_ERROR UINT32_C(0x100)
1024 * This indicates that there was an error in the tunnel portion
1025 * of the packet when this field is non-zero.
1027 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00)
1028 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
1030 * No additional error occurred on the tunnel
1031 * portion of the packet of the packet does not
1034 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9)
1036 * Indicates that IP header version does not
1037 * match expectation from L2 Ethertype for IPv4
1038 * and IPv6 in the tunnel header.
1040 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9)
1042 * Indicates that header length is out of range
1043 * in the tunnel header. Valid for IPv4.
1045 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9)
1047 * Indicates that the physical packet is shorter
1048 * than that claimed by the PPPoE header length
1049 * for a tunnel PPPoE packet.
1051 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (UINT32_C(0x3) << 9)
1053 * Indicates that physical packet is shorter
1054 * than that claimed by the tunnel l3 header
1055 * length. Valid for IPv4, or IPv6 tunnel packet
1058 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x4) << 9)
1060 * Indicates that the physical packet is shorter
1061 * than that claimed by the tunnel UDP header
1062 * length for a tunnel UDP packet that is not
1065 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x5) << 9)
1067 * indicates that the IPv4 TTL or IPv6 hop limit
1068 * check have failed (e.g. TTL = 0) in the
1069 * tunnel header. Valid for IPv4, and IPv6.
1071 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x6) << 9)
1072 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
1073 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
1075 * This indicates that there was an error in the inner portion
1076 * of the packet when this field is non-zero.
1078 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000)
1079 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
1081 * No additional error occurred on the tunnel
1082 * portion of the packet of the packet does not
1085 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12)
1087 * Indicates that IP header version does not
1088 * match expectation from L2 Ethertype for IPv4
1089 * and IPv6 or that option other than VFT was
1090 * parsed on FCoE packet.
1092 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12)
1094 * indicates that header length is out of range.
1095 * Valid for IPv4 and RoCE
1097 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12)
1099 * indicates that the IPv4 TTL or IPv6 hop limit
1100 * check have failed (e.g. TTL = 0). Valid for
1103 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12)
1105 * Indicates that physical packet is shorter
1106 * than that claimed by the l3 header length.
1107 * Valid for IPv4, IPv6 packet or RoCE packets.
1109 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12)
1111 * Indicates that the physical packet is shorter
1112 * than that claimed by the UDP header length
1113 * for a UDP packet that is not fragmented.
1115 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12)
1117 * Indicates that TCP header length > IP
1118 * payload. Valid for TCP packets only.
1120 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12)
1121 /* Indicates that TCP header length < 5. Valid for TCP. */
1122 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
1123 (UINT32_C(0x7) << 12)
1125 * Indicates that TCP option headers result in a
1126 * TCP header size that does not match data
1127 * offset in TCP header. Valid for TCP.
1129 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
1130 (UINT32_C(0x8) << 12)
1131 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
1132 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
1133 #define RX_PKT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
1134 #define RX_PKT_CMPL_ERRORS_SFT 1
1137 * This field identifies the CFA action rule that was used for
1142 * This value holds the reordering sequence number for the
1143 * packet. If the reordering sequence is not valid, then this
1144 * value is zero. The reordering domain for the packet is in the
1145 * bottom 8 to 10b of the rss_hash value. The bottom 20b of this
1146 * value contain the ordering domain value for the packet.
1148 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
1149 #define RX_PKT_CMPL_REORDER_SFT 0
1150 } __attribute__((packed));
1152 /* HWRM Forwarded Request (16 bytes) */
1153 struct hwrm_fwd_req_cmpl {
1154 uint16_t req_len_type;
1155 /* Length of forwarded request in bytes. */
1157 * This field indicates the exact type of the completion. By
1158 * convention, the LSB identifies the length of the record in
1159 * 16B units. Even values indicate 16B records. Odd values
1160 * indicate 32B records.
1162 #define HWRM_FWD_INPUT_CMPL_TYPE_MASK UINT32_C(0x3f)
1163 #define HWRM_FWD_INPUT_CMPL_TYPE_SFT 0
1164 /* Forwarded HWRM Request */
1165 #define HWRM_FWD_INPUT_CMPL_TYPE_HWRM_FWD_INPUT UINT32_C(0x22)
1166 /* Length of forwarded request in bytes. */
1167 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
1168 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
1171 * Source ID of this request. Typically used in forwarding
1172 * requests and responses. 0x0 - 0xFFF8 - Used for function ids
1173 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF -
1177 /* unused1 is 32 b */
1178 uint32_t req_buf_addr_v[2];
1179 /* Address of forwarded request. */
1181 * This value is written by the NIC such that it will be
1182 * different for each pass through the completion queue. The
1183 * even passes will write 1. The odd passes will write 0.
1185 #define HWRM_FWD_INPUT_CMPL_V UINT32_C(0x1)
1186 /* Address of forwarded request. */
1187 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
1188 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
1189 } __attribute__((packed));
1191 /* HWRM Asynchronous Event Completion Record (16 bytes) */
1192 struct hwrm_async_event_cmpl {
1194 /* unused1 is 10 b */
1196 * This field indicates the exact type of the completion. By
1197 * convention, the LSB identifies the length of the record in
1198 * 16B units. Even values indicate 16B records. Odd values
1199 * indicate 32B records.
1201 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
1202 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
1203 /* HWRM Asynchronous Event Information */
1204 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
1205 /* unused1 is 10 b */
1207 /* Identifiers of events. */
1208 /* Link status changed */
1209 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE UINT32_C(0x0)
1210 /* Link MTU changed */
1211 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE UINT32_C(0x1)
1212 /* Link speed changed */
1213 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE UINT32_C(0x2)
1214 /* DCB Configuration changed */
1215 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE UINT32_C(0x3)
1216 /* Port connection not allowed */
1217 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED UINT32_C(0x4)
1218 /* Link speed configuration was not allowed */
1219 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED UINT32_C(0x5)
1220 /* Link speed configuration change */
1221 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE UINT32_C(0x6)
1222 /* Port PHY configuration change */
1223 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE UINT32_C(0x7)
1224 /* Function driver unloaded */
1225 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD UINT32_C(0x10)
1226 /* Function driver loaded */
1227 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD UINT32_C(0x11)
1228 /* Function FLR related processing has completed */
1229 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT UINT32_C(0x12)
1230 /* PF driver unloaded */
1231 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD UINT32_C(0x20)
1232 /* PF driver loaded */
1233 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD UINT32_C(0x21)
1234 /* VF Function Level Reset (FLR) */
1235 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR UINT32_C(0x30)
1236 /* VF MAC Address Change */
1237 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE UINT32_C(0x31)
1238 /* PF-VF communication channel status change. */
1239 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE UINT32_C(0x32)
1240 /* VF Configuration Change */
1241 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE UINT32_C(0x33)
1243 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR UINT32_C(0xff)
1244 uint32_t event_data2;
1245 /* Event specific data */
1249 * This value is written by the NIC such that it will be
1250 * different for each pass through the completion queue. The
1251 * even passes will write 1. The odd passes will write 0.
1253 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
1255 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
1256 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
1257 uint8_t timestamp_lo;
1258 /* 8-lsb timestamp from POR (100-msec resolution) */
1259 uint16_t timestamp_hi;
1260 /* 16-lsb timestamp from POR (100-msec resolution) */
1261 uint32_t event_data1;
1262 /* Event specific data */
1263 } __attribute__((packed));
1266 * Note: The Hardware Resource Manager (HWRM) manages various hardware resources
1267 * inside the chip. The HWRM is implemented in firmware, and runs on embedded
1268 * processors inside the chip. This firmware service is vital part of the chip.
1269 * The chip can not be used by a driver or HWRM client without the HWRM.
1272 /* Input (16 bytes) */
1276 * This value indicates what type of request this is. The format
1277 * for the rest of the command is determined by this field.
1281 * This value indicates the what completion ring the request
1282 * will be optionally completed on. If the value is -1, then no
1283 * CR completion will be generated. Any other value must be a
1284 * valid CR ring_id value for this function.
1287 /* This value indicates the command sequence number. */
1290 * Target ID of this command. 0x0 - 0xFFF8 - Used for function
1291 * ids 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF
1296 * This is the host address where the response will be written
1297 * when the request is complete. This area must be 16B aligned
1298 * and must be cleared to zero before the request is made.
1300 } __attribute__((packed));
1302 /* Output (8 bytes) */
1304 uint16_t error_code;
1306 * Pass/Fail or error type Note: receiver to verify the in
1307 * parameters, and fail the call with an error when appropriate
1310 /* This field returns the type of original request. */
1312 /* This field provides original sequence number of the command. */
1315 * This field is the length of the response in bytes. The last
1316 * byte of the response is a valid flag that will read as '1'
1317 * when the command has been completely written to memory.
1319 } __attribute__((packed));
1323 * Description: This function is called by a driver to determine the HWRM
1324 * interface version supported by the HWRM firmware, the version of HWRM
1325 * firmware implementation, the name of HWRM firmware, the versions of other
1326 * embedded firmwares, and the names of other embedded firmwares, etc. Any
1327 * interface or firmware version with major = 0, minor = 0, and update = 0 shall
1328 * be considered an invalid version.
1330 /* Input (24 bytes) */
1331 struct hwrm_ver_get_input {
1334 * This value indicates what type of request this is. The format
1335 * for the rest of the command is determined by this field.
1339 * This value indicates the what completion ring the request
1340 * will be optionally completed on. If the value is -1, then no
1341 * CR completion will be generated. Any other value must be a
1342 * valid CR ring_id value for this function.
1345 /* This value indicates the command sequence number. */
1348 * Target ID of this command. 0x0 - 0xFFF8 - Used for function
1349 * ids 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF
1354 * This is the host address where the response will be written
1355 * when the request is complete. This area must be 16B aligned
1356 * and must be cleared to zero before the request is made.
1358 uint8_t hwrm_intf_maj;
1360 * This field represents the major version of HWRM interface
1361 * specification supported by the driver HWRM implementation.
1362 * The interface major version is intended to change only when
1363 * non backward compatible changes are made to the HWRM
1364 * interface specification.
1366 uint8_t hwrm_intf_min;
1368 * This field represents the minor version of HWRM interface
1369 * specification supported by the driver HWRM implementation. A
1370 * change in interface minor version is used to reflect
1371 * significant backward compatible modification to HWRM
1372 * interface specification. This can be due to addition or
1373 * removal of functionality. HWRM interface specifications with
1374 * the same major version but different minor versions are
1377 uint8_t hwrm_intf_upd;
1379 * This field represents the update version of HWRM interface
1380 * specification supported by the driver HWRM implementation.
1381 * The interface update version is used to reflect minor changes
1382 * or bug fixes to a released HWRM interface specification.
1384 uint8_t unused_0[5];
1385 } __attribute__((packed));
1387 /* Output (128 bytes) */
1388 struct hwrm_ver_get_output {
1389 uint16_t error_code;
1391 * Pass/Fail or error type Note: receiver to verify the in
1392 * parameters, and fail the call with an error when appropriate
1395 /* This field returns the type of original request. */
1397 /* This field provides original sequence number of the command. */
1400 * This field is the length of the response in bytes. The last
1401 * byte of the response is a valid flag that will read as '1'
1402 * when the command has been completely written to memory.
1404 uint8_t hwrm_intf_maj;
1406 * This field represents the major version of HWRM interface
1407 * specification supported by the HWRM implementation. The
1408 * interface major version is intended to change only when non
1409 * backward compatible changes are made to the HWRM interface
1410 * specification. A HWRM implementation that is compliant with
1411 * this specification shall provide value of 1 in this field.
1413 uint8_t hwrm_intf_min;
1415 * This field represents the minor version of HWRM interface
1416 * specification supported by the HWRM implementation. A change
1417 * in interface minor version is used to reflect significant
1418 * backward compatible modification to HWRM interface
1419 * specification. This can be due to addition or removal of
1420 * functionality. HWRM interface specifications with the same
1421 * major version but different minor versions are compatible. A
1422 * HWRM implementation that is compliant with this specification
1423 * shall provide value of 2 in this field.
1425 uint8_t hwrm_intf_upd;
1427 * This field represents the update version of HWRM interface
1428 * specification supported by the HWRM implementation. The
1429 * interface update version is used to reflect minor changes or
1430 * bug fixes to a released HWRM interface specification. A HWRM
1431 * implementation that is compliant with this specification
1432 * shall provide value of 2 in this field.
1434 uint8_t hwrm_intf_rsvd;
1435 uint8_t hwrm_fw_maj;
1437 * This field represents the major version of HWRM firmware. A
1438 * change in firmware major version represents a major firmware
1441 uint8_t hwrm_fw_min;
1443 * This field represents the minor version of HWRM firmware. A
1444 * change in firmware minor version represents significant
1445 * firmware functionality changes.
1447 uint8_t hwrm_fw_bld;
1449 * This field represents the build version of HWRM firmware. A
1450 * change in firmware build version represents bug fixes to a
1451 * released firmware.
1453 uint8_t hwrm_fw_rsvd;
1455 * This field is a reserved field. This field can be used to
1456 * represent firmware branches or customer specific releases
1457 * tied to a specific (major,minor,update) version of the HWRM
1460 uint8_t mgmt_fw_maj;
1462 * This field represents the major version of mgmt firmware. A
1463 * change in major version represents a major release.
1465 uint8_t mgmt_fw_min;
1467 * This field represents the minor version of mgmt firmware. A
1468 * change in minor version represents significant functionality
1471 uint8_t mgmt_fw_bld;
1473 * This field represents the build version of mgmt firmware. A
1474 * change in update version represents bug fixes.
1476 uint8_t mgmt_fw_rsvd;
1478 * This field is a reserved field. This field can be used to
1479 * represent firmware branches or customer specific releases
1480 * tied to a specific (major,minor,update) version
1482 uint8_t netctrl_fw_maj;
1484 * This field represents the major version of network control
1485 * firmware. A change in major version represents a major
1488 uint8_t netctrl_fw_min;
1490 * This field represents the minor version of network control
1491 * firmware. A change in minor version represents significant
1492 * functionality changes.
1494 uint8_t netctrl_fw_bld;
1496 * This field represents the build version of network control
1497 * firmware. A change in update version represents bug fixes.
1499 uint8_t netctrl_fw_rsvd;
1501 * This field is a reserved field. This field can be used to
1502 * represent firmware branches or customer specific releases
1503 * tied to a specific (major,minor,update) version
1505 uint32_t dev_caps_cfg;
1507 * This field is used to indicate device's capabilities and
1511 * If set to 1, then secure firmware update behavior is
1512 * supported. If set to 0, then secure firmware update behavior
1515 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED UINT32_C(0x1)
1517 * If set to 1, then firmware based DCBX agent is supported. If
1518 * set to 0, then firmware based DCBX agent capability is not
1519 * supported on this device.
1521 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED UINT32_C(0x2)
1522 uint8_t roce_fw_maj;
1524 * This field represents the major version of RoCE firmware. A
1525 * change in major version represents a major release.
1527 uint8_t roce_fw_min;
1529 * This field represents the minor version of RoCE firmware. A
1530 * change in minor version represents significant functionality
1533 uint8_t roce_fw_bld;
1535 * This field represents the build version of RoCE firmware. A
1536 * change in update version represents bug fixes.
1538 uint8_t roce_fw_rsvd;
1540 * This field is a reserved field. This field can be used to
1541 * represent firmware branches or customer specific releases
1542 * tied to a specific (major,minor,update) version
1544 char hwrm_fw_name[16];
1546 * This field represents the name of HWRM FW (ASCII chars with
1549 char mgmt_fw_name[16];
1551 * This field represents the name of mgmt FW (ASCII chars with
1554 char netctrl_fw_name[16];
1556 * This field represents the name of network control firmware
1557 * (ASCII chars with NULL at the end).
1559 uint32_t reserved2[4];
1561 * This field is reserved for future use. The responder should
1562 * set it to 0. The requester should ignore this field.
1564 char roce_fw_name[16];
1566 * This field represents the name of RoCE FW (ASCII chars with
1570 /* This field returns the chip number. */
1572 /* This field returns the revision of chip. */
1574 /* This field returns the chip metal number. */
1575 uint8_t chip_bond_id;
1576 /* This field returns the bond id of the chip. */
1577 uint8_t chip_platform_type;
1579 * This value indicates the type of platform used for chip
1583 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
1584 /* FPGA platform of the chip. */
1585 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
1586 /* Palladium platform of the chip. */
1587 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
1588 uint16_t max_req_win_len;
1590 * This field returns the maximum value of request window that
1591 * is supported by the HWRM. The request window is mapped into
1592 * device address space using MMIO.
1594 uint16_t max_resp_len;
1595 /* This field returns the maximum value of response buffer in bytes. */
1596 uint16_t def_req_timeout;
1598 * This field returns the default request timeout value in
1606 * This field is used in Output records to indicate that the
1607 * output is completely written to RAM. This field should be
1608 * read as '1' to indicate that the output has been completely
1609 * written. When writing a command completion or response to an
1610 * internal processor, the order of writes has to be such that
1611 * this field is written last.
1613 } __attribute__((packed));
1615 /* hwrm_func_reset */
1617 * Description: This command resets a hardware function (PCIe function) and
1618 * frees any resources used by the function. This command shall be initiated by
1619 * the driver after an FLR has occurred to prepare the function for re-use. This
1620 * command may also be initiated by a driver prior to doing it's own
1621 * configuration. This command puts the function into the reset state. In the
1622 * reset state, global and port related features of the chip are not available.
1625 * Note: This command will reset a function that has already been disabled or
1626 * idled. The command returns all the resources owned by the function so a new
1627 * driver may allocate and configure resources normally.
1629 /* Input (24 bytes) */
1630 struct hwrm_func_reset_input {
1633 * This value indicates what type of request this is. The format
1634 * for the rest of the command is determined by this field.
1638 * This value indicates the what completion ring the request
1639 * will be optionally completed on. If the value is -1, then no
1640 * CR completion will be generated. Any other value must be a
1641 * valid CR ring_id value for this function.
1644 /* This value indicates the command sequence number. */
1647 * Target ID of this command. 0x0 - 0xFFF8 - Used for function
1648 * ids 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF
1653 * This is the host address where the response will be written
1654 * when the request is complete. This area must be 16B aligned
1655 * and must be cleared to zero before the request is made.
1658 /* This bit must be '1' for the vf_id_valid field to be configured. */
1659 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
1662 * The ID of the VF that this PF is trying to reset. Only the
1663 * parent PF shall be allowed to reset a child VF. A parent PF
1664 * driver shall use this field only when a specific child VF is
1665 * requested to be reset.
1667 uint8_t func_reset_level;
1668 /* This value indicates the level of a function reset. */
1670 * Reset the caller function and its children
1671 * VFs (if any). If no children functions exist,
1672 * then reset the caller function only.
1674 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL UINT32_C(0x0)
1675 /* Reset the caller function only */
1676 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME UINT32_C(0x1)
1678 * Reset all children VFs of the caller function
1679 * driver if the caller is a PF driver. It is an
1680 * error to specify this level by a VF driver.
1681 * It is an error to specify this level by a PF
1682 * driver with no children VFs.
1684 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN UINT32_C(0x2)
1686 * Reset a specific VF of the caller function
1687 * driver if the caller is the parent PF driver.
1688 * It is an error to specify this level by a VF
1689 * driver. It is an error to specify this level
1690 * by a PF driver that is not the parent of the
1691 * VF that is being requested to reset.
1693 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF UINT32_C(0x3)
1695 } __attribute__((packed));
1697 /* Output (16 bytes) */
1698 struct hwrm_func_reset_output {
1699 uint16_t error_code;
1701 * Pass/Fail or error type Note: receiver to verify the in
1702 * parameters, and fail the call with an error when appropriate
1705 /* This field returns the type of original request. */
1707 /* This field provides original sequence number of the command. */
1710 * This field is the length of the response in bytes. The last
1711 * byte of the response is a valid flag that will read as '1'
1712 * when the command has been completely written to memory.
1720 * This field is used in Output records to indicate that the
1721 * output is completely written to RAM. This field should be
1722 * read as '1' to indicate that the output has been completely
1723 * written. When writing a command completion or response to an
1724 * internal processor, the order of writes has to be such that
1725 * this field is written last.
1727 } __attribute__((packed));
1729 /* hwrm_func_qcaps */
1731 * Description: This command returns capabilities of a function. The input FID
1732 * value is used to indicate what function is being queried. This allows a
1733 * physical function driver to query virtual functions that are children of the
1734 * physical function. The output FID value is needed to configure Rings and
1735 * MSI-X vectors so their DMA operations appear correctly on the PCI bus.
1737 /* Input (24 bytes) */
1738 struct hwrm_func_qcaps_input {
1741 * This value indicates what type of request this is. The format
1742 * for the rest of the command is determined by this field.
1746 * This value indicates the what completion ring the request
1747 * will be optionally completed on. If the value is -1, then no
1748 * CR completion will be generated. Any other value must be a
1749 * valid CR ring_id value for this function.
1752 /* This value indicates the command sequence number. */
1755 * Target ID of this command. 0x0 - 0xFFF8 - Used for function
1756 * ids 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF
1761 * This is the host address where the response will be written
1762 * when the request is complete. This area must be 16B aligned
1763 * and must be cleared to zero before the request is made.
1767 * Function ID of the function that is being queried. 0xFF...
1768 * (All Fs) if the query is for the requesting function.
1770 uint16_t unused_0[3];
1771 } __attribute__((packed));
1773 /* Output (80 bytes) */
1774 struct hwrm_func_qcaps_output {
1775 uint16_t error_code;
1777 * Pass/Fail or error type Note: receiver to verify the in
1778 * parameters, and fail the call with an error when appropriate
1781 /* This field returns the type of original request. */
1783 /* This field provides original sequence number of the command. */
1786 * This field is the length of the response in bytes. The last
1787 * byte of the response is a valid flag that will read as '1'
1788 * when the command has been completely written to memory.
1792 * FID value. This value is used to identify operations on the
1793 * PCI bus as belonging to a particular PCI function.
1797 * Port ID of port that this function is associated with. Valid
1798 * only for the PF. 0xFF... (All Fs) if this function is not
1799 * associated with any port. 0xFF... (All Fs) if this function
1800 * is called from a VF.
1803 /* If 1, then Push mode is supported on this function. */
1804 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED UINT32_C(0x1)
1806 * If 1, then the global MSI-X auto-masking is enabled for the
1809 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING UINT32_C(0x2)
1811 * If 1, then the Precision Time Protocol (PTP) processing is
1812 * supported on this function. The HWRM should enable PTP on
1813 * only a single Physical Function (PF) per port.
1815 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED UINT32_C(0x4)
1817 * If 1, then RDMA over Converged Ethernet (RoCE) v1 is
1818 * supported on this function.
1820 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED UINT32_C(0x8)
1822 * If 1, then RDMA over Converged Ethernet (RoCE) v2 is
1823 * supported on this function.
1825 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED UINT32_C(0x10)
1827 * If 1, then control and configuration of WoL magic packet are
1828 * supported on this function.
1830 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED UINT32_C(0x20)
1832 * If 1, then control and configuration of bitmap pattern packet
1833 * are supported on this function.
1835 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED UINT32_C(0x40)
1837 * If set to 1, then the control and configuration of rate limit
1838 * of an allocated TX ring on the queried function is supported.
1840 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED UINT32_C(0x80)
1842 * If 1, then control and configuration of minimum and maximum
1843 * bandwidths are supported on the queried function.
1845 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED UINT32_C(0x100)
1847 * If the query is for a VF, then this flag shall be ignored. If
1848 * this query is for a PF and this flag is set to 1, then the PF
1849 * has the capability to set the rate limits on the TX rings of
1850 * its children VFs. If this query is for a PF and this flag is
1851 * set to 0, then the PF does not have the capability to set the
1852 * rate limits on the TX rings of its children VFs.
1854 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED UINT32_C(0x200)
1856 * If the query is for a VF, then this flag shall be ignored. If
1857 * this query is for a PF and this flag is set to 1, then the PF
1858 * has the capability to set the minimum and/or maximum
1859 * bandwidths for its children VFs. If this query is for a PF
1860 * and this flag is set to 0, then the PF does not have the
1861 * capability to set the minimum or maximum bandwidths for its
1864 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED UINT32_C(0x400)
1865 uint8_t mac_address[6];
1867 * This value is current MAC address configured for this
1868 * function. A value of 00-00-00-00-00-00 indicates no MAC
1869 * address is currently configured.
1871 uint16_t max_rsscos_ctx;
1873 * The maximum number of RSS/COS contexts that can be allocated
1876 uint16_t max_cmpl_rings;
1878 * The maximum number of completion rings that can be allocated
1881 uint16_t max_tx_rings;
1883 * The maximum number of transmit rings that can be allocated to
1886 uint16_t max_rx_rings;
1888 * The maximum number of receive rings that can be allocated to
1891 uint16_t max_l2_ctxs;
1893 * The maximum number of L2 contexts that can be allocated to
1898 * The maximum number of VNICs that can be allocated to the
1901 uint16_t first_vf_id;
1903 * The identifier for the first VF enabled on a PF. This is
1904 * valid only on the PF with SR-IOV enabled. 0xFF... (All Fs) if
1905 * this command is called on a PF with SR-IOV disabled or on a
1910 * The maximum number of VFs that can be allocated to the
1911 * function. This is valid only on the PF with SR-IOV enabled.
1912 * 0xFF... (All Fs) if this command is called on a PF with SR-
1913 * IOV disabled or on a VF.
1915 uint16_t max_stat_ctx;
1917 * The maximum number of statistic contexts that can be
1918 * allocated to the function.
1920 uint32_t max_encap_records;
1922 * The maximum number of Encapsulation records that can be
1923 * offloaded by this function.
1925 uint32_t max_decap_records;
1927 * The maximum number of decapsulation records that can be
1928 * offloaded by this function.
1930 uint32_t max_tx_em_flows;
1932 * The maximum number of Exact Match (EM) flows that can be
1933 * offloaded by this function on the TX side.
1935 uint32_t max_tx_wm_flows;
1937 * The maximum number of Wildcard Match (WM) flows that can be
1938 * offloaded by this function on the TX side.
1940 uint32_t max_rx_em_flows;
1942 * The maximum number of Exact Match (EM) flows that can be
1943 * offloaded by this function on the RX side.
1945 uint32_t max_rx_wm_flows;
1947 * The maximum number of Wildcard Match (WM) flows that can be
1948 * offloaded by this function on the RX side.
1950 uint32_t max_mcast_filters;
1952 * The maximum number of multicast filters that can be supported
1953 * by this function on the RX side.
1955 uint32_t max_flow_id;
1957 * The maximum value of flow_id that can be supported in
1958 * completion records.
1960 uint32_t max_hw_ring_grps;
1962 * The maximum number of HW ring groups that can be supported on
1965 uint16_t max_sp_tx_rings;
1967 * The maximum number of strict priority transmit rings that can
1968 * be allocated to the function. This number indicates the
1969 * maximum number of TX rings that can be assigned strict
1970 * priorities out of the maximum number of TX rings that can be
1971 * allocated (max_tx_rings) to the function.
1976 * This field is used in Output records to indicate that the
1977 * output is completely written to RAM. This field should be
1978 * read as '1' to indicate that the output has been completely
1979 * written. When writing a command completion or response to an
1980 * internal processor, the order of writes has to be such that
1981 * this field is written last.
1983 } __attribute__((packed));
1985 /* hwrm_cfa_l2_filter_alloc */
1987 * A filter is used to identify traffic that contains a matching set of
1988 * parameters like unicast or broadcast MAC address or a VLAN tag amongst
1989 * other things which then allows the ASIC to direct the incoming traffic
1990 * to an appropriate VNIC or Rx ring.
1993 /* Input (96 bytes) */
1994 struct hwrm_cfa_l2_filter_alloc_input {
1996 * This value indicates what type of request this is. The format for the
1997 * rest of the command is determined by this field.
2002 * This value indicates the what completion ring the request will be
2003 * optionally completed on. If the value is -1, then no CR completion
2004 * will be generated. Any other value must be a valid CR ring_id value
2005 * for this function.
2009 /* This value indicates the command sequence number. */
2013 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
2014 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
2019 * This is the host address where the response will be written when the
2020 * request is complete. This area must be 16B aligned and must be
2021 * cleared to zero before the request is made.
2026 * Enumeration denoting the RX, TX type of the resource. This
2027 * enumeration is used for resources that are similar for both TX and RX
2028 * paths of the chip.
2030 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
2033 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
2034 (UINT32_C(0x0) << 0)
2036 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
2037 (UINT32_C(0x1) << 0)
2038 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
2039 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
2041 * Setting of this flag indicates the applicability to the loopback
2044 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
2047 * Setting of this flag indicates drop action. If this flag is not set,
2048 * then it should be considered accept action.
2050 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
2053 * If this flag is set, all t_l2_* fields are invalid and they should
2054 * not be specified. If this flag is set, then l2_* fields refer to
2055 * fields of outermost L2 header.
2057 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
2061 /* This bit must be '1' for the l2_addr field to be configured. */
2062 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
2064 /* This bit must be '1' for the l2_addr_mask field to be configured. */
2065 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
2067 /* This bit must be '1' for the l2_ovlan field to be configured. */
2068 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
2070 /* This bit must be '1' for the l2_ovlan_mask field to be configured. */
2071 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
2073 /* This bit must be '1' for the l2_ivlan field to be configured. */
2074 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
2076 /* This bit must be '1' for the l2_ivlan_mask field to be configured. */
2077 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
2079 /* This bit must be '1' for the t_l2_addr field to be configured. */
2080 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
2083 * This bit must be '1' for the t_l2_addr_mask field to be configured.
2085 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
2087 /* This bit must be '1' for the t_l2_ovlan field to be configured. */
2088 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
2091 * This bit must be '1' for the t_l2_ovlan_mask field to be configured.
2093 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
2095 /* This bit must be '1' for the t_l2_ivlan field to be configured. */
2096 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
2099 * This bit must be '1' for the t_l2_ivlan_mask field to be configured.
2101 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
2103 /* This bit must be '1' for the src_type field to be configured. */
2104 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
2106 /* This bit must be '1' for the src_id field to be configured. */
2107 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
2109 /* This bit must be '1' for the tunnel_type field to be configured. */
2110 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
2112 /* This bit must be '1' for the dst_id field to be configured. */
2113 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
2116 * This bit must be '1' for the mirror_vnic_id field to be configured.
2118 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
2123 * This value sets the match value for the L2 MAC address. Destination
2124 * MAC address for RX path. Source MAC address for TX path.
2132 * This value sets the mask value for the L2 address. A value of 0 will
2133 * mask the corresponding bit from compare.
2135 uint8_t l2_addr_mask[6];
2137 /* This value sets VLAN ID value for outer VLAN. */
2141 * This value sets the mask value for the ovlan id. A value of 0 will
2142 * mask the corresponding bit from compare.
2144 uint16_t l2_ovlan_mask;
2146 /* This value sets VLAN ID value for inner VLAN. */
2150 * This value sets the mask value for the ivlan id. A value of 0 will
2151 * mask the corresponding bit from compare.
2153 uint16_t l2_ivlan_mask;
2159 * This value sets the match value for the tunnel L2 MAC address.
2160 * Destination MAC address for RX path. Source MAC address for TX path.
2162 uint8_t t_l2_addr[6];
2168 * This value sets the mask value for the tunnel L2 address. A value of
2169 * 0 will mask the corresponding bit from compare.
2171 uint8_t t_l2_addr_mask[6];
2173 /* This value sets VLAN ID value for tunnel outer VLAN. */
2174 uint16_t t_l2_ovlan;
2177 * This value sets the mask value for the tunnel ovlan id. A value of 0
2178 * will mask the corresponding bit from compare.
2180 uint16_t t_l2_ovlan_mask;
2182 /* This value sets VLAN ID value for tunnel inner VLAN. */
2183 uint16_t t_l2_ivlan;
2186 * This value sets the mask value for the tunnel ivlan id. A value of 0
2187 * will mask the corresponding bit from compare.
2189 uint16_t t_l2_ivlan_mask;
2191 /* This value identifies the type of source of the packet. */
2193 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT \
2194 (UINT32_C(0x0) << 0)
2195 /* Physical function */
2196 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF \
2197 (UINT32_C(0x1) << 0)
2198 /* Virtual function */
2199 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF \
2200 (UINT32_C(0x2) << 0)
2201 /* Virtual NIC of a function */
2202 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC \
2203 (UINT32_C(0x3) << 0)
2204 /* Embedded processor for CFA management */
2205 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG \
2206 (UINT32_C(0x4) << 0)
2207 /* Embedded processor for OOB management */
2208 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE \
2209 (UINT32_C(0x5) << 0)
2210 /* Embedded processor for RoCE */
2211 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO \
2212 (UINT32_C(0x6) << 0)
2213 /* Embedded processor for network proxy functions */
2214 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG \
2215 (UINT32_C(0x7) << 0)
2220 * This value is the id of the source. For a network port, it represents
2221 * port_id. For a physical function, it represents fid. For a virtual
2222 * function, it represents vf_id. For a vnic, it represents vnic_id. For
2223 * embedded processors, this id is not valid. Notes: 1. The function ID
2224 * is implied if it src_id is not provided for a src_type that is either
2230 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
2231 (UINT32_C(0x0) << 0)
2232 /* Virtual eXtensible Local Area Network (VXLAN) */
2233 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
2234 (UINT32_C(0x1) << 0)
2236 * Network Virtualization Generic Routing Encapsulation (NVGRE)
2238 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
2239 (UINT32_C(0x2) << 0)
2241 * Generic Routing Encapsulation (GRE) inside Ethernet payload
2243 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
2244 (UINT32_C(0x3) << 0)
2246 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
2247 (UINT32_C(0x4) << 0)
2248 /* Generic Network Virtualization Encapsulation (Geneve) */
2249 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
2250 (UINT32_C(0x5) << 0)
2251 /* Multi-Protocol Lable Switching (MPLS) */
2252 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
2253 (UINT32_C(0x6) << 0)
2254 /* Stateless Transport Tunnel (STT) */
2255 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
2256 (UINT32_C(0x7) << 0)
2258 * Generic Routing Encapsulation (GRE) inside IP datagram
2261 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
2262 (UINT32_C(0x8) << 0)
2263 /* Any tunneled traffic */
2264 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
2265 (UINT32_C(0xff) << 0)
2266 uint8_t tunnel_type;
2271 * If set, this value shall represent the Logical VNIC ID of the
2272 * destination VNIC for the RX path and network port id of the
2273 * destination port for the TX path.
2277 /* Logical VNIC ID of the VNIC where traffic is mirrored. */
2278 uint16_t mirror_vnic_id;
2281 * This hint is provided to help in placing the filter in the filter
2285 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
2286 (UINT32_C(0x0) << 0)
2287 /* Above the given filter */
2288 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
2289 (UINT32_C(0x1) << 0)
2290 /* Below the given filter */
2291 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
2292 (UINT32_C(0x2) << 0)
2293 /* As high as possible */
2294 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
2295 (UINT32_C(0x3) << 0)
2296 /* As low as possible */
2297 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
2298 (UINT32_C(0x4) << 0)
2305 * This is the ID of the filter that goes along with the pri_hint. This
2306 * field is valid only for the following values. 1 - Above the given
2307 * filter 2 - Below the given filter
2309 uint64_t l2_filter_id_hint;
2310 } __attribute__((packed));
2312 /* Output (24 bytes) */
2313 struct hwrm_cfa_l2_filter_alloc_output {
2315 * Pass/Fail or error type Note: receiver to verify the in parameters,
2316 * and fail the call with an error when appropriate
2318 uint16_t error_code;
2320 /* This field returns the type of original request. */
2323 /* This field provides original sequence number of the command. */
2327 * This field is the length of the response in bytes. The last byte of
2328 * the response is a valid flag that will read as '1' when the command
2329 * has been completely written to memory.
2334 * This value identifies a set of CFA data structures used for an L2
2337 uint64_t l2_filter_id;
2340 * This is the ID of the flow associated with this filter. This value
2341 * shall be used to match and associate the flow identifier returned in
2342 * completion records. A value of 0xFFFFFFFF shall indicate no flow id.
2351 * This field is used in Output records to indicate that the output is
2352 * completely written to RAM. This field should be read as '1' to
2353 * indicate that the output has been completely written. When writing a
2354 * command completion or response to an internal processor, the order of
2355 * writes has to be such that this field is written last.
2358 } __attribute__((packed));
2360 /* hwrm_cfa_l2_filter_free */
2362 * Description: Free a L2 filter. The HWRM shall free all associated filter
2363 * resources with the L2 filter.
2366 /* Input (24 bytes) */
2367 struct hwrm_cfa_l2_filter_free_input {
2369 * This value indicates what type of request this is. The format for the
2370 * rest of the command is determined by this field.
2375 * This value indicates the what completion ring the request will be
2376 * optionally completed on. If the value is -1, then no CR completion
2377 * will be generated. Any other value must be a valid CR ring_id value
2378 * for this function.
2382 /* This value indicates the command sequence number. */
2386 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
2387 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
2392 * This is the host address where the response will be written when the
2393 * request is complete. This area must be 16B aligned and must be
2394 * cleared to zero before the request is made.
2399 * This value identifies a set of CFA data structures used for an L2
2402 uint64_t l2_filter_id;
2403 } __attribute__((packed));
2405 /* Output (16 bytes) */
2406 struct hwrm_cfa_l2_filter_free_output {
2408 * Pass/Fail or error type Note: receiver to verify the in parameters,
2409 * and fail the call with an error when appropriate
2411 uint16_t error_code;
2413 /* This field returns the type of original request. */
2416 /* This field provides original sequence number of the command. */
2420 * This field is the length of the response in bytes. The last byte of
2421 * the response is a valid flag that will read as '1' when the command
2422 * has been completely written to memory.
2432 * This field is used in Output records to indicate that the output is
2433 * completely written to RAM. This field should be read as '1' to
2434 * indicate that the output has been completely written. When writing a
2435 * command completion or response to an internal processor, the order of
2436 * writes has to be such that this field is written last.
2439 } __attribute__((packed));
2441 /* hwrm_cfa_l2_set_rx_mask */
2442 /* Description: This command will set rx mask of the function. */
2444 /* Input (40 bytes) */
2445 struct hwrm_cfa_l2_set_rx_mask_input {
2447 * This value indicates what type of request this is. The format for the
2448 * rest of the command is determined by this field.
2453 * This value indicates the what completion ring the request will be
2454 * optionally completed on. If the value is -1, then no CR completion
2455 * will be generated. Any other value must be a valid CR ring_id value
2456 * for this function.
2460 /* This value indicates the command sequence number. */
2464 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
2465 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
2470 * This is the host address where the response will be written when the
2471 * request is complete. This area must be 16B aligned and must be
2472 * cleared to zero before the request is made.
2479 /* Reserved for future use. */
2480 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_RESERVED UINT32_C(0x1)
2482 * When this bit is '1', the function is requested to accept multi-cast
2483 * packets specified by the multicast addr table.
2485 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST UINT32_C(0x2)
2487 * When this bit is '1', the function is requested to accept all multi-
2490 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST UINT32_C(0x4)
2492 * When this bit is '1', the function is requested to accept broadcast
2495 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST UINT32_C(0x8)
2497 * When this bit is '1', the function is requested to be put in the
2498 * promiscuous mode. The HWRM should accept any function to set up
2499 * promiscuous mode. The HWRM shall follow the semantics below for the
2500 * promiscuous mode support. # When partitioning is not enabled on a
2501 * port (i.e. single PF on the port), then the PF shall be allowed to be
2502 * in the promiscuous mode. When the PF is in the promiscuous mode, then
2503 * it shall receive all host bound traffic on that port. # When
2504 * partitioning is enabled on a port (i.e. multiple PFs per port) and a
2505 * PF on that port is in the promiscuous mode, then the PF receives all
2506 * traffic within that partition as identified by a unique identifier
2507 * for the PF (e.g. S-Tag). If a unique outer VLAN for the PF is
2508 * specified, then the setting of promiscuous mode on that PF shall
2509 * result in the PF receiving all host bound traffic with matching outer
2510 * VLAN. # A VF shall can be set in the promiscuous mode. In the
2511 * promiscuous mode, the VF does not receive any traffic unless a unique
2512 * outer VLAN for the VF is specified. If a unique outer VLAN for the VF
2513 * is specified, then the setting of promiscuous mode on that VF shall
2514 * result in the VF receiving all host bound traffic with the matching
2515 * outer VLAN. # The HWRM shall allow the setting of promiscuous mode on
2516 * a function independently from the promiscuous mode settings on other
2519 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS UINT32_C(0x10)
2521 * If this flag is set, the corresponding RX filters shall be set up to
2522 * cover multicast/broadcast filters for the outermost Layer 2
2523 * destination MAC address field.
2525 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST UINT32_C(0x20)
2528 /* This is the address for mcast address tbl. */
2529 uint64_t mc_tbl_addr;
2532 * This value indicates how many entries in mc_tbl are valid. Each entry
2535 uint32_t num_mc_entries;
2538 } __attribute__((packed));
2540 /* Output (16 bytes) */
2541 struct hwrm_cfa_l2_set_rx_mask_output {
2543 * Pass/Fail or error type Note: receiver to verify the in parameters,
2544 * and fail the call with an error when appropriate
2546 uint16_t error_code;
2548 /* This field returns the type of original request. */
2551 /* This field provides original sequence number of the command. */
2555 * This field is the length of the response in bytes. The last byte of
2556 * the response is a valid flag that will read as '1' when the command
2557 * has been completely written to memory.
2567 * This field is used in Output records to indicate that the output is
2568 * completely written to RAM. This field should be read as '1' to
2569 * indicate that the output has been completely written. When writing a
2570 * command completion or response to an internal processor, the order of
2571 * writes has to be such that this field is written last.
2574 } __attribute__((packed));
2576 /* hwrm_exec_fwd_resp */
2578 * Description: This command is used to send an encapsulated request to the
2579 * HWRM. This command instructs the HWRM to execute the request and forward the
2580 * response of the encapsulated request to the location specified in the
2581 * original request that is encapsulated. The target id of this command shall be
2582 * set to 0xFFFF (HWRM). The response location in this command shall be used to
2583 * acknowledge the receipt of the encapsulated request and forwarding of the
2587 /* Input (128 bytes) */
2588 struct hwrm_exec_fwd_resp_input {
2590 * This value indicates what type of request this is. The format for the
2591 * rest of the command is determined by this field.
2596 * This value indicates the what completion ring the request will be
2597 * optionally completed on. If the value is -1, then no CR completion
2598 * will be generated. Any other value must be a valid CR ring_id value
2599 * for this function.
2603 /* This value indicates the command sequence number. */
2607 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
2608 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
2613 * This is the host address where the response will be written when the
2614 * request is complete. This area must be 16B aligned and must be
2615 * cleared to zero before the request is made.
2620 * This is an encapsulated request. This request should be executed by
2621 * the HWRM and the response should be provided in the response buffer
2622 * inside the encapsulated request.
2624 uint32_t encap_request[26];
2627 * This value indicates the target id of the response to the
2628 * encapsulated request. 0x0 - 0xFFF8 - Used for function ids 0xFFF8 -
2629 * 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
2631 uint16_t encap_resp_target_id;
2633 uint16_t unused_0[3];
2634 } __attribute__((packed));
2636 /* Output (16 bytes) */
2637 struct hwrm_exec_fwd_resp_output {
2639 * Pass/Fail or error type Note: receiver to verify the in parameters,
2640 * and fail the call with an error when appropriate
2642 uint16_t error_code;
2644 /* This field returns the type of original request. */
2647 /* This field provides original sequence number of the command. */
2651 * This field is the length of the response in bytes. The last byte of
2652 * the response is a valid flag that will read as '1' when the command
2653 * has been completely written to memory.
2663 * This field is used in Output records to indicate that the output is
2664 * completely written to RAM. This field should be read as '1' to
2665 * indicate that the output has been completely written. When writing a
2666 * command completion or response to an internal processor, the order of
2667 * writes has to be such that this field is written last.
2670 } __attribute__((packed));
2672 /* hwrm_port_phy_cfg */
2674 * Description: This command configures the PHY device for the port. It allows
2675 * setting of the most generic settings for the PHY. The HWRM shall complete
2676 * this command as soon as PHY settings are configured. They may not be applied
2677 * when the command response is provided. A VF driver shall not be allowed to
2678 * configure PHY using this command. In a network partition mode, a PF driver
2679 * shall not be allowed to configure PHY using this command.
2682 /* Input (56 bytes) */
2683 struct hwrm_port_phy_cfg_input {
2685 * This value indicates what type of request this is. The format for the
2686 * rest of the command is determined by this field.
2691 * This value indicates the what completion ring the request will be
2692 * optionally completed on. If the value is -1, then no CR completion
2693 * will be generated. Any other value must be a valid CR ring_id value
2694 * for this function.
2698 /* This value indicates the command sequence number. */
2702 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
2703 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
2708 * This is the host address where the response will be written when the
2709 * request is complete. This area must be 16B aligned and must be
2710 * cleared to zero before the request is made.
2715 * When this bit is set to '1', the PHY for the port shall be reset. #
2716 * If this bit is set to 1, then the HWRM shall reset the PHY after
2717 * applying PHY configuration changes specified in this command. # In
2718 * order to guarantee that PHY configuration changes specified in this
2719 * command take effect, the HWRM client should set this flag to 1. # If
2720 * this bit is not set to 1, then the HWRM may reset the PHY depending
2721 * on the current PHY configuration and settings specified in this
2724 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY UINT32_C(0x1)
2726 * When this bit is set to '1', the link shall be forced to be taken
2727 * down. # When this bit is set to '1", all other command input settings
2728 * related to the link speed shall be ignored. Once the link state is
2729 * forced down, it can be explicitly cleared from that state by setting
2730 * this flag to '0'. # If this flag is set to '0', then the link shall
2731 * be cleared from forced down state if the link is in forced down
2732 * state. There may be conditions (e.g. out-of-band or sideband
2733 * configuration changes for the link) outside the scope of the HWRM
2734 * implementation that may clear forced down link state.
2736 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN UINT32_C(0x2)
2738 * When this bit is set to '1', the link shall be forced to the
2739 * force_link_speed value. When this bit is set to '1', the HWRM client
2740 * should not enable any of the auto negotiation related fields
2741 * represented by auto_XXX fields in this command. When this bit is set
2742 * to '1' and the HWRM client has enabled a auto_XXX field in this
2743 * command, then the HWRM shall ignore the enabled auto_XXX field. When
2744 * this bit is set to zero, the link shall be allowed to autoneg.
2746 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE UINT32_C(0x4)
2748 * When this bit is set to '1', the auto-negotiation process shall be
2749 * restarted on the link.
2751 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG UINT32_C(0x8)
2753 * When this bit is set to '1', Energy Efficient Ethernet (EEE) is
2754 * requested to be enabled on this link. If EEE is not supported on this
2755 * port, then this flag shall be ignored by the HWRM.
2757 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE UINT32_C(0x10)
2759 * When this bit is set to '1', Energy Efficient Ethernet (EEE) is
2760 * requested to be disabled on this link. If EEE is not supported on
2761 * this port, then this flag shall be ignored by the HWRM.
2763 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE UINT32_C(0x20)
2765 * When this bit is set to '1' and EEE is enabled on this link, then TX
2766 * LPI is requested to be enabled on the link. If EEE is not supported
2767 * on this port, then this flag shall be ignored by the HWRM. If EEE is
2768 * disabled on this port, then this flag shall be ignored by the HWRM.
2770 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI UINT32_C(0x40)
2773 /* This bit must be '1' for the auto_mode field to be configured. */
2774 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE UINT32_C(0x1)
2775 /* This bit must be '1' for the auto_duplex field to be configured. */
2776 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX UINT32_C(0x2)
2777 /* This bit must be '1' for the auto_pause field to be configured. */
2778 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE UINT32_C(0x4)
2780 * This bit must be '1' for the auto_link_speed field to be configured.
2782 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED UINT32_C(0x8)
2784 * This bit must be '1' for the auto_link_speed_mask field to be
2787 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
2789 /* This bit must be '1' for the wirespeed field to be configured. */
2790 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED UINT32_C(0x20)
2791 /* This bit must be '1' for the lpbk field to be configured. */
2792 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK UINT32_C(0x40)
2793 /* This bit must be '1' for the preemphasis field to be configured. */
2794 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS UINT32_C(0x80)
2795 /* This bit must be '1' for the force_pause field to be configured. */
2796 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE UINT32_C(0x100)
2798 * This bit must be '1' for the eee_link_speed_mask field to be
2801 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
2803 /* This bit must be '1' for the tx_lpi_timer field to be configured. */
2804 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER UINT32_C(0x400)
2807 /* Port ID of port that is to be configured. */
2811 * This is the speed that will be used if the force bit is '1'. If
2812 * unsupported speed is selected, an error will be generated.
2814 /* 100Mb link speed */
2815 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB \
2816 (UINT32_C(0x1) << 0)
2817 /* 1Gb link speed */
2818 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB \
2819 (UINT32_C(0xa) << 0)
2820 /* 2Gb link speed */
2821 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB \
2822 (UINT32_C(0x14) << 0)
2823 /* 2.5Gb link speed */
2824 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB \
2825 (UINT32_C(0x19) << 0)
2826 /* 10Gb link speed */
2827 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB \
2828 (UINT32_C(0x64) << 0)
2829 /* 20Mb link speed */
2830 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB \
2831 (UINT32_C(0xc8) << 0)
2832 /* 25Gb link speed */
2833 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB \
2834 (UINT32_C(0xfa) << 0)
2835 /* 40Gb link speed */
2836 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB \
2837 (UINT32_C(0x190) << 0)
2838 /* 50Gb link speed */
2839 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB \
2840 (UINT32_C(0x1f4) << 0)
2841 /* 100Gb link speed */
2842 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB \
2843 (UINT32_C(0x3e8) << 0)
2844 /* 10Mb link speed */
2845 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB \
2846 (UINT32_C(0xffff) << 0)
2847 uint16_t force_link_speed;
2850 * This value is used to identify what autoneg mode is used when the
2851 * link speed is not being forced.
2854 * Disable autoneg or autoneg disabled. No speeds are selected.
2856 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE (UINT32_C(0x0) << 0)
2857 /* Select all possible speeds for autoneg mode. */
2858 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS \
2859 (UINT32_C(0x1) << 0)
2861 * Select only the auto_link_speed speed for autoneg mode. This
2862 * mode has been DEPRECATED. An HWRM client should not use this
2865 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED \
2866 (UINT32_C(0x2) << 0)
2868 * Select the auto_link_speed or any speed below that speed for
2869 * autoneg. This mode has been DEPRECATED. An HWRM client should
2870 * not use this mode.
2872 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW \
2873 (UINT32_C(0x3) << 0)
2875 * Select the speeds based on the corresponding link speed mask
2876 * value that is provided.
2878 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK \
2879 (UINT32_C(0x4) << 0)
2883 * This is the duplex setting that will be used if the autoneg_mode is
2884 * "one_speed" or "one_or_below".
2886 /* Half Duplex will be requested. */
2887 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF \
2888 (UINT32_C(0x0) << 0)
2889 /* Full duplex will be requested. */
2890 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL \
2891 (UINT32_C(0x1) << 0)
2892 /* Both Half and Full dupex will be requested. */
2893 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH \
2894 (UINT32_C(0x2) << 0)
2895 uint8_t auto_duplex;
2898 * This value is used to configure the pause that will be used for
2899 * autonegotiation. Add text on the usage of auto_pause and force_pause.
2902 * When this bit is '1', Generation of tx pause messages has been
2903 * requested. Disabled otherwise.
2905 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX UINT32_C(0x1)
2907 * When this bit is '1', Reception of rx pause messages has been
2908 * requested. Disabled otherwise.
2910 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX UINT32_C(0x2)
2912 * When set to 1, the advertisement of pause is enabled. # When the
2913 * auto_mode is not set to none and this flag is set to 1, then the
2914 * auto_pause bits on this port are being advertised and autoneg pause
2915 * results are being interpreted. # When the auto_mode is not set to
2916 * none and this flag is set to 0, the pause is forced as indicated in
2917 * force_pause, and also advertised as auto_pause bits, but the autoneg
2918 * results are not interpreted since the pause configuration is being
2919 * forced. # When the auto_mode is set to none and this flag is set to
2920 * 1, auto_pause bits should be ignored and should be set to 0.
2922 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE UINT32_C(0x4)
2928 * This is the speed that will be used if the autoneg_mode is
2929 * "one_speed" or "one_or_below". If an unsupported speed is selected,
2930 * an error will be generated.
2932 /* 100Mb link speed */
2933 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB \
2934 (UINT32_C(0x1) << 0)
2935 /* 1Gb link speed */
2936 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB \
2937 (UINT32_C(0xa) << 0)
2938 /* 2Gb link speed */
2939 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB \
2940 (UINT32_C(0x14) << 0)
2941 /* 2.5Gb link speed */
2942 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB \
2943 (UINT32_C(0x19) << 0)
2944 /* 10Gb link speed */
2945 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB \
2946 (UINT32_C(0x64) << 0)
2947 /* 20Mb link speed */
2948 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB \
2949 (UINT32_C(0xc8) << 0)
2950 /* 25Gb link speed */
2951 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB \
2952 (UINT32_C(0xfa) << 0)
2953 /* 40Gb link speed */
2954 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB \
2955 (UINT32_C(0x190) << 0)
2956 /* 50Gb link speed */
2957 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB \
2958 (UINT32_C(0x1f4) << 0)
2959 /* 100Gb link speed */
2960 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB \
2961 (UINT32_C(0x3e8) << 0)
2962 /* 10Mb link speed */
2963 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB \
2964 (UINT32_C(0xffff) << 0)
2965 uint16_t auto_link_speed;
2968 * This is a mask of link speeds that will be used if autoneg_mode is
2969 * "mask". If unsupported speed is enabled an error will be generated.
2971 /* 100Mb link speed (Half-duplex) */
2972 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
2974 /* 100Mb link speed (Full-duplex) */
2975 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
2977 /* 1Gb link speed (Half-duplex) */
2978 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
2980 /* 1Gb link speed (Full-duplex) */
2981 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
2983 /* 2Gb link speed */
2984 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
2986 /* 2.5Gb link speed */
2987 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
2989 /* 10Gb link speed */
2990 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
2992 /* 20Gb link speed */
2993 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
2995 /* 25Gb link speed */
2996 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
2998 /* 40Gb link speed */
2999 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
3001 /* 50Gb link speed */
3002 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
3004 /* 100Gb link speed */
3005 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
3007 /* 10Mb link speed (Half-duplex) */
3008 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
3010 /* 10Mb link speed (Full-duplex) */
3011 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
3013 uint16_t auto_link_speed_mask;
3015 /* This value controls the wirespeed feature. */
3016 /* Wirespeed feature is disabled. */
3017 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF (UINT32_C(0x0) << 0)
3018 /* Wirespeed feature is enabled. */
3019 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON (UINT32_C(0x1) << 0)
3022 /* This value controls the loopback setting for the PHY. */
3023 /* No loopback is selected. Normal operation. */
3024 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE (UINT32_C(0x0) << 0)
3026 * The HW will be configured with local loopback such that host
3027 * data is sent back to the host without modification.
3029 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL (UINT32_C(0x1) << 0)
3031 * The HW will be configured with remote loopback such that port
3032 * logic will send packets back out the transmitter that are
3035 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE (UINT32_C(0x2) << 0)
3039 * This value is used to configure the pause that will be used for force
3043 * When this bit is '1', Generation of tx pause messages is supported.
3044 * Disabled otherwise.
3046 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
3048 * When this bit is '1', Reception of rx pause messages is supported.
3049 * Disabled otherwise.
3051 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
3052 uint8_t force_pause;
3057 * This value controls the pre-emphasis to be used for the link. Driver
3058 * should not set this value (use enable.preemphasis = 0) unless driver
3059 * is sure of setting. Normally HWRM FW will determine proper pre-
3062 uint32_t preemphasis;
3065 * Setting for link speed mask that is used to advertise speeds during
3066 * autonegotiation when EEE is enabled. This field is valid only when
3067 * EEE is enabled. The speeds specified in this field shall be a subset
3068 * of speeds specified in auto_link_speed_mask. If EEE is enabled,then
3069 * at least one speed shall be provided in this mask.
3072 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 UINT32_C(0x1)
3073 /* 100Mb link speed (Full-duplex) */
3074 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB UINT32_C(0x2)
3076 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 UINT32_C(0x4)
3077 /* 1Gb link speed (Full-duplex) */
3078 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB UINT32_C(0x8)
3080 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
3083 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
3085 /* 10Gb link speed */
3086 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
3088 uint16_t eee_link_speed_mask;
3094 * Reuested setting of TX LPI timer in microseconds. This field is valid
3095 * only when EEE is enabled and TX LPI is enabled.
3097 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK \
3099 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
3100 uint32_t tx_lpi_timer;
3103 } __attribute__((packed));
3105 /* Output (16 bytes) */
3106 struct hwrm_port_phy_cfg_output {
3108 * Pass/Fail or error type Note: receiver to verify the in parameters,
3109 * and fail the call with an error when appropriate
3111 uint16_t error_code;
3113 /* This field returns the type of original request. */
3116 /* This field provides original sequence number of the command. */
3120 * This field is the length of the response in bytes. The last byte of
3121 * the response is a valid flag that will read as '1' when the command
3122 * has been completely written to memory.
3132 * This field is used in Output records to indicate that the output is
3133 * completely written to RAM. This field should be read as '1' to
3134 * indicate that the output has been completely written. When writing a
3135 * command completion or response to an internal processor, the order of
3136 * writes has to be such that this field is written last.
3139 } __attribute__((packed));
3141 /* hwrm_port_phy_qcfg */
3142 /* Description: This command queries the PHY configuration for the port. */
3143 /* Input (24 bytes) */
3145 struct hwrm_port_phy_qcfg_input {
3147 * This value indicates what type of request this is. The format for the
3148 * rest of the command is determined by this field.
3153 * This value indicates the what completion ring the request will be
3154 * optionally completed on. If the value is -1, then no CR completion
3155 * will be generated. Any other value must be a valid CR ring_id value
3156 * for this function.
3160 /* This value indicates the command sequence number. */
3164 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
3165 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
3170 * This is the host address where the response will be written when the
3171 * request is complete. This area must be 16B aligned and must be
3172 * cleared to zero before the request is made.
3176 /* Port ID of port that is to be queried. */
3179 uint16_t unused_0[3];
3180 } __attribute__((packed));
3182 /* Output (96 bytes) */
3183 struct hwrm_port_phy_qcfg_output {
3185 * Pass/Fail or error type Note: receiver to verify the in parameters,
3186 * and fail the call with an error when appropriate
3188 uint16_t error_code;
3190 /* This field returns the type of original request. */
3193 /* This field provides original sequence number of the command. */
3197 * This field is the length of the response in bytes. The last byte of
3198 * the response is a valid flag that will read as '1' when the command
3199 * has been completely written to memory.
3203 /* This value indicates the current link status. */
3204 /* There is no link or cable detected. */
3205 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK (UINT32_C(0x0) << 0)
3206 /* There is no link, but a cable has been detected. */
3207 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL (UINT32_C(0x1) << 0)
3208 /* There is a link. */
3209 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK (UINT32_C(0x2) << 0)
3214 /* This value indicates the current link speed of the connection. */
3215 /* 100Mb link speed */
3216 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB \
3217 (UINT32_C(0x1) << 0)
3218 /* 1Gb link speed */
3219 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB \
3220 (UINT32_C(0xa) << 0)
3221 /* 2Gb link speed */
3222 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB \
3223 (UINT32_C(0x14) << 0)
3224 /* 2.5Gb link speed */
3225 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB \
3226 (UINT32_C(0x19) << 0)
3227 /* 10Gb link speed */
3228 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB \
3229 (UINT32_C(0x64) << 0)
3230 /* 20Mb link speed */
3231 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB \
3232 (UINT32_C(0xc8) << 0)
3233 /* 25Gb link speed */
3234 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB \
3235 (UINT32_C(0xfa) << 0)
3236 /* 40Gb link speed */
3237 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB \
3238 (UINT32_C(0x190) << 0)
3239 /* 50Gb link speed */
3240 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB \
3241 (UINT32_C(0x1f4) << 0)
3242 /* 100Gb link speed */
3243 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB \
3244 (UINT32_C(0x3e8) << 0)
3245 /* 10Mb link speed */
3246 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB \
3247 (UINT32_C(0xffff) << 0)
3248 uint16_t link_speed;
3250 /* This value is indicates the duplex of the current connection. */
3251 /* Half Duplex connection. */
3252 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_HALF (UINT32_C(0x0) << 0)
3253 /* Full duplex connection. */
3254 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_FULL (UINT32_C(0x1) << 0)
3258 * This value is used to indicate the current pause configuration. When
3259 * autoneg is enabled, this value represents the autoneg results of
3260 * pause configuration.
3263 * When this bit is '1', Generation of tx pause messages is supported.
3264 * Disabled otherwise.
3266 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
3268 * When this bit is '1', Reception of rx pause messages is supported.
3269 * Disabled otherwise.
3271 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
3275 * The supported speeds for the port. This is a bit mask. For each speed
3276 * that is supported, the corrresponding bit will be set to '1'.
3278 /* 100Mb link speed (Half-duplex) */
3279 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
3281 /* 100Mb link speed (Full-duplex) */
3282 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
3284 /* 1Gb link speed (Half-duplex) */
3285 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
3287 /* 1Gb link speed (Full-duplex) */
3288 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
3290 /* 2Gb link speed */
3291 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
3293 /* 2.5Gb link speed */
3294 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
3296 /* 10Gb link speed */
3297 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
3299 /* 20Gb link speed */
3300 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
3302 /* 25Gb link speed */
3303 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
3305 /* 40Gb link speed */
3306 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
3308 /* 50Gb link speed */
3309 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
3311 /* 100Gb link speed */
3312 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
3314 /* 10Mb link speed (Half-duplex) */
3315 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
3317 /* 10Mb link speed (Full-duplex) */
3318 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
3320 uint16_t support_speeds;
3323 * Current setting of forced link speed. When the link speed is not
3324 * being forced, this value shall be set to 0.
3326 /* 100Mb link speed */
3327 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB \
3328 (UINT32_C(0x1) << 0)
3329 /* 1Gb link speed */
3330 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB \
3331 (UINT32_C(0xa) << 0)
3332 /* 2Gb link speed */
3333 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB \
3334 (UINT32_C(0x14) << 0)
3335 /* 2.5Gb link speed */
3336 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB \
3337 (UINT32_C(0x19) << 0)
3338 /* 10Gb link speed */
3339 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB \
3340 (UINT32_C(0x64) << 0)
3341 /* 20Mb link speed */
3342 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB \
3343 (UINT32_C(0xc8) << 0)
3344 /* 25Gb link speed */
3345 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB \
3346 (UINT32_C(0xfa) << 0)
3347 /* 40Gb link speed */
3348 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
3349 (UINT32_C(0x190) << 0)
3350 /* 50Gb link speed */
3351 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
3352 (UINT32_C(0x1f4) << 0)
3353 /* 100Gb link speed */
3354 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
3355 (UINT32_C(0x3e8) << 0)
3356 /* 10Mb link speed */
3357 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
3358 (UINT32_C(0xffff) << 0)
3359 uint16_t force_link_speed;
3361 /* Current setting of auto negotiation mode. */
3363 * Disable autoneg or autoneg disabled. No speeds are selected.
3365 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE \
3366 (UINT32_C(0x0) << 0)
3367 /* Select all possible speeds for autoneg mode. */
3368 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS \
3369 (UINT32_C(0x1) << 0)
3371 * Select only the auto_link_speed speed for autoneg mode. This
3372 * mode has been DEPRECATED. An HWRM client should not use this
3375 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED \
3376 (UINT32_C(0x2) << 0)
3378 * Select the auto_link_speed or any speed below that speed for
3379 * autoneg. This mode has been DEPRECATED. An HWRM client should
3380 * not use this mode.
3382 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW \
3383 (UINT32_C(0x3) << 0)
3385 * Select the speeds based on the corresponding link speed mask
3386 * value that is provided.
3388 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK \
3389 (UINT32_C(0x4) << 0)
3393 * Current setting of pause autonegotiation. Move autoneg_pause flag
3397 * When this bit is '1', Generation of tx pause messages has been
3398 * requested. Disabled otherwise.
3400 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX UINT32_C(0x1)
3402 * When this bit is '1', Reception of rx pause messages has been
3403 * requested. Disabled otherwise.
3405 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX UINT32_C(0x2)
3407 * When set to 1, the advertisement of pause is enabled. # When the
3408 * auto_mode is not set to none and this flag is set to 1, then the
3409 * auto_pause bits on this port are being advertised and autoneg pause
3410 * results are being interpreted. # When the auto_mode is not set to
3411 * none and this flag is set to 0, the pause is forced as indicated in
3412 * force_pause, and also advertised as auto_pause bits, but the autoneg
3413 * results are not interpreted since the pause configuration is being
3414 * forced. # When the auto_mode is set to none and this flag is set to
3415 * 1, auto_pause bits should be ignored and should be set to 0.
3417 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
3422 * Current setting for auto_link_speed. This field is only valid when
3423 * auto_mode is set to "one_speed" or "one_or_below".
3425 /* 100Mb link speed */
3426 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB \
3427 (UINT32_C(0x1) << 0)
3428 /* 1Gb link speed */
3429 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB \
3430 (UINT32_C(0xa) << 0)
3431 /* 2Gb link speed */
3432 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB \
3433 (UINT32_C(0x14) << 0)
3434 /* 2.5Gb link speed */
3435 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB \
3436 (UINT32_C(0x19) << 0)
3437 /* 10Gb link speed */
3438 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB \
3439 (UINT32_C(0x64) << 0)
3440 /* 20Mb link speed */
3441 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB \
3442 (UINT32_C(0xc8) << 0)
3443 /* 25Gb link speed */
3444 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB \
3445 (UINT32_C(0xfa) << 0)
3446 /* 40Gb link speed */
3447 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB \
3448 (UINT32_C(0x190) << 0)
3449 /* 50Gb link speed */
3450 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB \
3451 (UINT32_C(0x1f4) << 0)
3452 /* 100Gb link speed */
3453 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB \
3454 (UINT32_C(0x3e8) << 0)
3455 /* 10Mb link speed */
3456 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
3457 (UINT32_C(0xffff) << 0)
3458 uint16_t auto_link_speed;
3461 * Current setting for auto_link_speed_mask that is used to advertise
3462 * speeds during autonegotiation. This field is only valid when
3463 * auto_mode is set to "mask". The speeds specified in this field shall
3464 * be a subset of supported speeds on this port.
3466 /* 100Mb link speed (Half-duplex) */
3467 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
3469 /* 100Mb link speed (Full-duplex) */
3470 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
3472 /* 1Gb link speed (Half-duplex) */
3473 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
3475 /* 1Gb link speed (Full-duplex) */
3476 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
3478 /* 2Gb link speed */
3479 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
3481 /* 2.5Gb link speed */
3482 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
3484 /* 10Gb link speed */
3485 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
3487 /* 20Gb link speed */
3488 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
3490 /* 25Gb link speed */
3491 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
3493 /* 40Gb link speed */
3494 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
3496 /* 50Gb link speed */
3497 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
3499 /* 100Gb link speed */
3500 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
3502 /* 10Mb link speed (Half-duplex) */
3503 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
3505 /* 10Mb link speed (Full-duplex) */
3506 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
3508 uint16_t auto_link_speed_mask;
3510 /* Current setting for wirespeed. */
3511 /* Wirespeed feature is disabled. */
3512 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF (UINT32_C(0x0) << 0)
3513 /* Wirespeed feature is enabled. */
3514 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON (UINT32_C(0x1) << 0)
3517 /* Current setting for loopback. */
3518 /* No loopback is selected. Normal operation. */
3519 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE (UINT32_C(0x0) << 0)
3521 * The HW will be configured with local loopback such that host
3522 * data is sent back to the host without modification.
3524 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL (UINT32_C(0x1) << 0)
3526 * The HW will be configured with remote loopback such that port
3527 * logic will send packets back out the transmitter that are
3530 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE (UINT32_C(0x2) << 0)
3534 * Current setting of forced pause. When the pause configuration is not
3535 * being forced, then this value shall be set to 0.
3538 * When this bit is '1', Generation of tx pause messages is supported.
3539 * Disabled otherwise.
3541 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX \
3544 * When this bit is '1', Reception of rx pause messages is supported.
3545 * Disabled otherwise.
3547 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX \
3549 uint8_t force_pause;
3552 * This value indicates the current status of the optics module on this
3555 /* Module is inserted and accepted */
3556 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
3557 (UINT32_C(0x0) << 0)
3558 /* Module is rejected and transmit side Laser is disabled. */
3559 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
3560 (UINT32_C(0x1) << 0)
3561 /* Module mismatch warning. */
3562 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
3563 (UINT32_C(0x2) << 0)
3564 /* Module is rejected and powered down. */
3565 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
3566 (UINT32_C(0x3) << 0)
3567 /* Module is not inserted. */
3568 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
3569 (UINT32_C(0x4) << 0)
3570 /* Module status is not applicable. */
3571 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
3572 (UINT32_C(0xff) << 0)
3573 uint8_t module_status;
3575 /* Current setting for preemphasis. */
3576 uint32_t preemphasis;
3578 /* This field represents the major version of the PHY. */
3581 /* This field represents the minor version of the PHY. */
3584 /* This field represents the build version of the PHY. */
3587 /* This value represents a PHY type. */
3589 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
3590 (UINT32_C(0x0) << 0)
3592 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
3593 (UINT32_C(0x1) << 0)
3594 /* BASE-KR4 (Deprecated) */
3595 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
3596 (UINT32_C(0x2) << 0)
3598 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
3599 (UINT32_C(0x3) << 0)
3601 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
3602 (UINT32_C(0x4) << 0)
3603 /* BASE-KR2 (Deprecated) */
3604 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
3605 (UINT32_C(0x5) << 0)
3607 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
3608 (UINT32_C(0x6) << 0)
3610 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
3611 (UINT32_C(0x7) << 0)
3613 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
3614 (UINT32_C(0x8) << 0)
3615 /* EEE capable BASE-T */
3616 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
3617 (UINT32_C(0x9) << 0)
3618 /* SGMII connected external PHY */
3619 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
3620 (UINT32_C(0xa) << 0)
3623 /* This value represents a media type. */
3625 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN \
3626 (UINT32_C(0x0) << 0)
3628 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP (UINT32_C(0x1) << 0)
3629 /* Direct Attached Copper */
3630 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC \
3631 (UINT32_C(0x2) << 0)
3633 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE \
3634 (UINT32_C(0x3) << 0)
3637 /* This value represents a transceiver type. */
3638 /* PHY and MAC are in the same package */
3639 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
3640 (UINT32_C(0x1) << 0)
3641 /* PHY and MAC are in different packages */
3642 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
3643 (UINT32_C(0x2) << 0)
3644 uint8_t xcvr_pkg_type;
3647 * This field represents flags related to EEE configuration. These EEE
3648 * configuration flags are valid only when the auto_mode is not set to
3649 * none (in other words autonegotiation is enabled).
3651 /* This field represents PHY address. */
3652 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK UINT32_C(0x1f)
3653 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
3655 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
3656 * Speeds for autoneg with EEE mode enabled are based on
3657 * eee_link_speed_mask.
3659 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
3662 * This flag is valid only when eee_enabled is set to 1. # If
3663 * eee_enabled is set to 0, then EEE mode is disabled and this flag
3664 * shall be ignored. # If eee_enabled is set to 1 and this flag is set
3665 * to 1, then Energy Efficient Ethernet (EEE) mode is enabled and in
3666 * use. # If eee_enabled is set to 1 and this flag is set to 0, then
3667 * Energy Efficient Ethernet (EEE) mode is enabled but is currently not
3670 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
3673 * This flag is valid only when eee_enabled is set to 1. # If
3674 * eee_enabled is set to 0, then EEE mode is disabled and this flag
3675 * shall be ignored. # If eee_enabled is set to 1 and this flag is set
3676 * to 1, then Energy Efficient Ethernet (EEE) mode is enabled and TX LPI
3677 * is enabled. # If eee_enabled is set to 1 and this flag is set to 0,
3678 * then Energy Efficient Ethernet (EEE) mode is enabled but TX LPI is
3681 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
3684 * This field represents flags related to EEE configuration. These EEE
3685 * configuration flags are valid only when the auto_mode is not set to
3686 * none (in other words autonegotiation is enabled).
3688 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
3690 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
3691 uint8_t eee_config_phy_addr;
3693 /* Reserved field, set to 0 */
3695 * When set to 1, the parallel detection is used to determine the speed
3696 * of the link partner. Parallel detection is used when a
3697 * autonegotiation capable device is connected to a link parter that is
3698 * not capable of autonegotiation.
3700 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT \
3702 /* Reserved field, set to 0 */
3703 #define HWRM_PORT_PHY_QCFG_OUTPUT_RESERVED_MASK UINT32_C(0xfe)
3704 #define HWRM_PORT_PHY_QCFG_OUTPUT_RESERVED_SFT 1
3705 uint8_t parallel_detect;
3708 * The advertised speeds for the port by the link partner. Each
3709 * advertised speed will be set to '1'.
3711 /* 100Mb link speed (Half-duplex) */
3712 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
3714 /* 100Mb link speed (Full-duplex) */
3715 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
3717 /* 1Gb link speed (Half-duplex) */
3718 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
3720 /* 1Gb link speed (Full-duplex) */
3721 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
3723 /* 2Gb link speed */
3724 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
3726 /* 2.5Gb link speed */
3727 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
3729 /* 10Gb link speed */
3730 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
3732 /* 20Gb link speed */
3733 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
3735 /* 25Gb link speed */
3736 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
3738 /* 40Gb link speed */
3739 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
3741 /* 50Gb link speed */
3742 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
3744 /* 100Gb link speed */
3745 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
3747 /* 10Mb link speed (Half-duplex) */
3748 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
3750 /* 10Mb link speed (Full-duplex) */
3751 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
3753 uint16_t link_partner_adv_speeds;
3756 * The advertised autoneg for the port by the link partner. This field
3757 * is deprecated and should be set to 0.
3760 * Disable autoneg or autoneg disabled. No speeds are selected.
3762 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
3763 (UINT32_C(0x0) << 0)
3764 /* Select all possible speeds for autoneg mode. */
3765 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS\
3766 (UINT32_C(0x1) << 0)
3768 * Select only the auto_link_speed speed for autoneg mode. This
3769 * mode has been DEPRECATED. An HWRM client should not use this
3772 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
3773 (UINT32_C(0x2) << 0)
3775 * Select the auto_link_speed or any speed below that speed for
3776 * autoneg. This mode has been DEPRECATED. An HWRM client should
3777 * not use this mode.
3780 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
3781 (UINT32_C(0x3) << 0)
3783 * Select the speeds based on the corresponding link speed mask
3784 * value that is provided.
3786 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK\
3787 (UINT32_C(0x4) << 0)
3788 uint8_t link_partner_adv_auto_mode;
3790 /* The advertised pause settings on the port by the link partner. */
3792 * When this bit is '1', Generation of tx pause messages is supported.
3793 * Disabled otherwise.
3795 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
3798 * When this bit is '1', Reception of rx pause messages is supported.
3799 * Disabled otherwise.
3801 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
3803 uint8_t link_partner_adv_pause;
3806 * Current setting for link speed mask that is used to advertise speeds
3807 * during autonegotiation when EEE is enabled. This field is valid only
3808 * when eee_enabled flags is set to 1. The speeds specified in this
3809 * field shall be a subset of speeds specified in auto_link_speed_mask.
3812 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
3814 /* 100Mb link speed (Full-duplex) */
3815 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
3818 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
3820 /* 1Gb link speed (Full-duplex) */
3821 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
3824 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
3827 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
3829 /* 10Gb link speed */
3830 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
3832 uint16_t adv_eee_link_speed_mask;
3835 * Current setting for link speed mask that is advertised by the link
3836 * partner when EEE is enabled. This field is valid only when
3837 * eee_enabled flags is set to 1.
3841 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
3843 /* 100Mb link speed (Full-duplex) */
3845 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
3849 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
3851 /* 1Gb link speed (Full-duplex) */
3853 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
3857 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
3861 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
3863 /* 10Gb link speed */
3865 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
3867 uint16_t link_partner_adv_eee_link_speed_mask;
3869 /* This value represents transceiver identifier type. */
3871 * Current setting of TX LPI timer in microseconds. This field is valid
3872 * only when_eee_enabled flag is set to 1 and tx_lpi_enabled is set to
3875 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
3877 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
3878 /* This value represents transceiver identifier type. */
3879 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
3880 UINT32_C(0xff000000)
3881 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT \
3884 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
3885 (UINT32_C(0x0) << 24)
3886 /* SFP/SFP+/SFP28 */
3887 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
3888 (UINT32_C(0x3) << 24)
3890 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
3891 (UINT32_C(0xc) << 24)
3893 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
3894 (UINT32_C(0xd) << 24)
3896 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
3897 (UINT32_C(0x11) << 24)
3898 uint32_t xcvr_identifier_type_tx_lpi_timer;
3903 * Up to 16 bytes of null padded ASCII string representing PHY vendor.
3904 * If the string is set to null, then the vendor name is not available.
3906 char phy_vendor_name[16];
3909 * Up to 16 bytes of null padded ASCII string that identifies vendor
3910 * specific part number of the PHY. If the string is set to null, then
3911 * the vendor specific part number is not available.
3913 char phy_vendor_partnumber[16];
3921 * This field is used in Output records to indicate that the output is
3922 * completely written to RAM. This field should be read as '1' to
3923 * indicate that the output has been completely written. When writing a
3924 * command completion or response to an internal processor, the order of
3925 * writes has to be such that this field is written last.
3928 } __attribute__((packed));
3930 /* hwrm_queue_qportcfg */
3932 * Description: This function is called by a driver to query queue configuration
3933 * of a port. # The HWRM shall at least advertise one queue with lossy service
3934 * profile. # The driver shall use this command to query queue ids before
3935 * configuring or using any queues. # If a service profile is not set for a
3936 * queue, then the driver shall not use that queue without configuring a service
3937 * profile for it. # If the driver is not allowed to configure service profiles,
3938 * then the driver shall only use queues for which service profiles are pre-
3942 /* Input (24 bytes) */
3943 struct hwrm_queue_qportcfg_input {
3945 * This value indicates what type of request this is. The format for the
3946 * rest of the command is determined by this field.
3951 * This value indicates the what completion ring the request will be
3952 * optionally completed on. If the value is -1, then no CR completion
3953 * will be generated. Any other value must be a valid CR ring_id value
3954 * for this function.
3958 /* This value indicates the command sequence number. */
3962 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
3963 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
3968 * This is the host address where the response will be written when the
3969 * request is complete. This area must be 16B aligned and must be
3970 * cleared to zero before the request is made.
3975 * Enumeration denoting the RX, TX type of the resource. This
3976 * enumeration is used for resources that are similar for both TX and RX
3977 * paths of the chip.
3979 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH \
3982 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX \
3983 (UINT32_C(0x0) << 0)
3985 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX \
3986 (UINT32_C(0x1) << 0)
3987 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
3988 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
3992 * Port ID of port for which the queue configuration is being queried.
3993 * This field is only required when sent by IPC.
3998 } __attribute__((packed));
4000 /* hwrm_ring_alloc */
4002 * Description: This command allocates and does basic preparation for a ring.
4005 /* Input (80 bytes) */
4006 struct hwrm_ring_alloc_input {
4008 * This value indicates what type of request this is. The format for the
4009 * rest of the command is determined by this field.
4014 * This value indicates the what completion ring the request will be
4015 * optionally completed on. If the value is -1, then no CR completion
4016 * will be generated. Any other value must be a valid CR ring_id value
4017 * for this function.
4021 /* This value indicates the command sequence number. */
4025 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
4026 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
4031 * This is the host address where the response will be written when the
4032 * request is complete. This area must be 16B aligned and must be
4033 * cleared to zero before the request is made.
4037 /* This bit must be '1' for the Reserved1 field to be configured. */
4038 #define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED1 UINT32_C(0x1)
4039 /* This bit must be '1' for the Reserved2 field to be configured. */
4040 #define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED2 UINT32_C(0x2)
4041 /* This bit must be '1' for the Reserved3 field to be configured. */
4042 #define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED3 UINT32_C(0x4)
4044 * This bit must be '1' for the stat_ctx_id_valid field to be
4047 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID UINT32_C(0x8)
4048 /* This bit must be '1' for the Reserved4 field to be configured. */
4049 #define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED4 UINT32_C(0x10)
4050 /* This bit must be '1' for the max_bw_valid field to be configured. */
4051 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID UINT32_C(0x20)
4055 /* Completion Ring (CR) */
4056 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_CMPL (UINT32_C(0x0) << 0)
4058 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX (UINT32_C(0x1) << 0)
4060 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX (UINT32_C(0x2) << 0)
4066 /* This value is a pointer to the page table for the Ring. */
4067 uint64_t page_tbl_addr;
4069 /* First Byte Offset of the first entry in the first page. */
4073 * Actual page size in 2^page_size. The supported range is increments in
4074 * powers of 2 from 16 bytes to 1GB. - 4 = 16 B Page size is 16 B. - 12
4075 * = 4 KB Page size is 4 KB. - 13 = 8 KB Page size is 8 KB. - 16 = 64 KB
4076 * Page size is 64 KB. - 22 = 2 MB Page size is 2 MB. - 23 = 4 MB Page
4077 * size is 4 MB. - 31 = 1 GB Page size is 1 GB.
4082 * This value indicates the depth of page table. For this version of the
4083 * specification, value other than 0 or 1 shall be considered as an
4084 * invalid value. When the page_tbl_depth = 0, then it is treated as a
4085 * special case with the following. 1. FBO and page size fields are not
4086 * valid. 2. page_tbl_addr is the physical address of the first element
4089 uint8_t page_tbl_depth;
4095 * Number of 16B units in the ring. Minimum size for a ring is 16 16B
4101 * Logical ring number for the ring to be allocated. This value
4102 * determines the position in the doorbell area where the update to the
4103 * ring will be made. For completion rings, this value is also the MSI-X
4104 * vector number for the function the completion ring is associated
4107 uint16_t logical_id;
4110 * This field is used only when ring_type is a TX ring. This value
4111 * indicates what completion ring the TX ring is associated with.
4113 uint16_t cmpl_ring_id;
4116 * This field is used only when ring_type is a TX ring. This value
4117 * indicates what CoS queue the TX ring is associated with.
4124 /* This field is reserved for the future use. It shall be set to 0. */
4126 /* This field is reserved for the future use. It shall be set to 0. */
4131 /* This field is reserved for the future use. It shall be set to 0. */
4135 * This field is used only when ring_type is a TX ring. This input
4136 * indicates what statistics context this ring should be associated
4139 uint32_t stat_ctx_id;
4141 /* This field is reserved for the future use. It shall be set to 0. */
4145 * This field is used only when ring_type is a TX ring. Maximum BW
4146 * allocated to this TX ring in Mbps. The HWRM will translate this value
4147 * into byte counter and time interval used for this ring inside the
4153 * This field is used only when ring_type is a Completion ring. This
4154 * value indicates what interrupt mode should be used on this completion
4155 * ring. Note: In the legacy interrupt mode, no more than 16 completion
4156 * rings are allowed.
4159 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY (UINT32_C(0x0) << 0)
4161 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD (UINT32_C(0x1) << 0)
4163 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX (UINT32_C(0x2) << 0)
4164 /* No Interrupt - Polled mode */
4165 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL (UINT32_C(0x3) << 0)
4168 uint8_t unused_8[3];
4169 } __attribute__((packed));
4171 /* Output (16 bytes) */
4173 struct hwrm_ring_alloc_output {
4175 * Pass/Fail or error type Note: receiver to verify the in parameters,
4176 * and fail the call with an error when appropriate
4178 uint16_t error_code;
4180 /* This field returns the type of original request. */
4183 /* This field provides original sequence number of the command. */
4187 * This field is the length of the response in bytes. The last byte of
4188 * the response is a valid flag that will read as '1' when the command
4189 * has been completely written to memory.
4193 /* Physical number of ring allocated. */
4196 /* Logical number of ring allocated. */
4197 uint16_t logical_ring_id;
4204 * This field is used in Output records to indicate that the output is
4205 * completely written to RAM. This field should be read as '1' to
4206 * indicate that the output has been completely written. When writing a
4207 * command completion or response to an internal processor, the order of
4208 * writes has to be such that this field is written last.
4211 } __attribute__((packed));
4213 /* hwrm_ring_free */
4215 * Description: This command is used to free a ring and associated resources.
4217 /* Input (24 bytes) */
4219 struct hwrm_ring_free_input {
4221 * This value indicates what type of request this is. The format for the
4222 * rest of the command is determined by this field.
4227 * This value indicates the what completion ring the request will be
4228 * optionally completed on. If the value is -1, then no CR completion
4229 * will be generated. Any other value must be a valid CR ring_id value
4230 * for this function.
4234 /* This value indicates the command sequence number. */
4238 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
4239 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
4244 * This is the host address where the response will be written when the
4245 * request is complete. This area must be 16B aligned and must be
4246 * cleared to zero before the request is made.
4251 /* Completion Ring (CR) */
4252 #define HWRM_RING_FREE_INPUT_RING_TYPE_CMPL (UINT32_C(0x0) << 0)
4254 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX (UINT32_C(0x1) << 0)
4256 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX (UINT32_C(0x2) << 0)
4261 /* Physical number of ring allocated. */
4265 } __attribute__((packed));
4267 /* Output (16 bytes) */
4268 struct hwrm_ring_free_output {
4270 * Pass/Fail or error type Note: receiver to verify the in parameters,
4271 * and fail the call with an error when appropriate
4273 uint16_t error_code;
4275 /* This field returns the type of original request. */
4278 /* This field provides original sequence number of the command. */
4282 * This field is the length of the response in bytes. The last byte of
4283 * the response is a valid flag that will read as '1' when the command
4284 * has been completely written to memory.
4294 * This field is used in Output records to indicate that the output is
4295 * completely written to RAM. This field should be read as '1' to
4296 * indicate that the output has been completely written. When writing a
4297 * command completion or response to an internal processor, the order of
4298 * writes has to be such that this field is written last.
4301 } __attribute__((packed));
4303 /* hwrm_ring_grp_alloc */
4305 * Description: This API allocates and does basic preparation for a ring group.
4308 /* Input (24 bytes) */
4309 struct hwrm_ring_grp_alloc_input {
4311 * This value indicates what type of request this is. The format for the
4312 * rest of the command is determined by this field.
4317 * This value indicates the what completion ring the request will be
4318 * optionally completed on. If the value is -1, then no CR completion
4319 * will be generated. Any other value must be a valid CR ring_id value
4320 * for this function.
4324 /* This value indicates the command sequence number. */
4328 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
4329 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
4334 * This is the host address where the response will be written when the
4335 * request is complete. This area must be 16B aligned and must be
4336 * cleared to zero before the request is made.
4340 /* This value identifies the CR associated with the ring group. */
4343 /* This value identifies the main RR associated with the ring group. */
4347 * This value identifies the aggregation RR associated with the ring
4348 * group. If this value is 0xFF... (All Fs), then no Aggregation ring
4354 * This value identifies the statistics context associated with the ring
4358 } __attribute__((packed));
4360 /* Output (16 bytes) */
4361 struct hwrm_ring_grp_alloc_output {
4363 * Pass/Fail or error type Note: receiver to verify the in parameters,
4364 * and fail the call with an error when appropriate
4366 uint16_t error_code;
4368 /* This field returns the type of original request. */
4371 /* This field provides original sequence number of the command. */
4375 * This field is the length of the response in bytes. The last byte of
4376 * the response is a valid flag that will read as '1' when the command
4377 * has been completely written to memory.
4382 * This is the ring group ID value. Use this value to program the
4383 * default ring group for the VNIC or as table entries in an RSS/COS
4386 uint32_t ring_group_id;
4393 * This field is used in Output records to indicate that the output is
4394 * completely written to RAM. This field should be read as '1' to
4395 * indicate that the output has been completely written. When writing a
4396 * command completion or response to an internal processor, the order of
4397 * writes has to be such that this field is written last.
4400 } __attribute__((packed));
4402 /* hwrm_ring_grp_free */
4404 * Description: This API frees a ring group and associated resources. # If a
4405 * ring in the ring group is reset or free, then the associated rings in the
4406 * ring group shall also be reset/free using hwrm_ring_free. # A function driver
4407 * shall always use hwrm_ring_grp_free after freeing all rings in a group. # As
4408 * a part of executing this command, the HWRM shall reset all associated ring
4412 /* Input (24 bytes) */
4413 struct hwrm_ring_grp_free_input {
4415 * This value indicates what type of request this is. The format for the
4416 * rest of the command is determined by this field.
4421 * This value indicates the what completion ring the request will be
4422 * optionally completed on. If the value is -1, then no CR completion
4423 * will be generated. Any other value must be a valid CR ring_id value
4424 * for this function.
4428 /* This value indicates the command sequence number. */
4432 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
4433 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
4438 * This is the host address where the response will be written when the
4439 * request is complete. This area must be 16B aligned and must be
4440 * cleared to zero before the request is made.
4444 /* This is the ring group ID value. */
4445 uint32_t ring_group_id;
4448 } __attribute__((packed));
4450 /* Output (16 bytes) */
4451 struct hwrm_ring_grp_free_output {
4453 * Pass/Fail or error type Note: receiver to verify the in parameters,
4454 * and fail the call with an error when appropriate
4456 uint16_t error_code;
4458 /* This field returns the type of original request. */
4461 /* This field provides original sequence number of the command. */
4465 * This field is the length of the response in bytes. The last byte of
4466 * the response is a valid flag that will read as '1' when the command
4467 * has been completely written to memory.
4477 * This field is used in Output records to indicate that the output is
4478 * completely written to RAM. This field should be read as '1' to
4479 * indicate that the output has been completely written. When writing a
4480 * command completion or response to an internal processor, the order of
4481 * writes has to be such that this field is written last.
4484 } __attribute__((packed));
4486 /* hwrm_stat_ctx_alloc */
4488 * Description: This command allocates and does basic preparation for a stat
4492 /* Input (32 bytes) */
4493 struct hwrm_stat_ctx_alloc_input {
4495 * This value indicates what type of request this is. The format for the
4496 * rest of the command is determined by this field.
4501 * This value indicates the what completion ring the request will be
4502 * optionally completed on. If the value is -1, then no CR completion
4503 * will be generated. Any other value must be a valid CR ring_id value
4504 * for this function.
4508 /* This value indicates the command sequence number. */
4512 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
4513 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
4518 * This is the host address where the response will be written when the
4519 * request is complete. This area must be 16B aligned and must be
4520 * cleared to zero before the request is made.
4524 /* This is the address for statistic block. */
4525 uint64_t stats_dma_addr;
4528 * The statistic block update period in ms. e.g. 250ms, 500ms, 750ms,
4531 uint32_t update_period_ms;
4534 } __attribute__((packed));
4536 /* Output (16 bytes) */
4537 struct hwrm_stat_ctx_alloc_output {
4539 * Pass/Fail or error type Note: receiver to verify the in parameters,
4540 * and fail the call with an error when appropriate
4542 uint16_t error_code;
4544 /* This field returns the type of original request. */
4547 /* This field provides original sequence number of the command. */
4551 * This field is the length of the response in bytes. The last byte of
4552 * the response is a valid flag that will read as '1' when the command
4553 * has been completely written to memory.
4557 /* This is the statistics context ID value. */
4558 uint32_t stat_ctx_id;
4565 * This field is used in Output records to indicate that the output is
4566 * completely written to RAM. This field should be read as '1' to
4567 * indicate that the output has been completely written. When writing a
4568 * command completion or response to an internal processor, the order of
4569 * writes has to be such that this field is written last.
4572 } __attribute__((packed));
4574 /* hwrm_stat_ctx_clr_stats */
4575 /* Description: This command clears statistics of a context. */
4577 /* Input (24 bytes) */
4578 struct hwrm_stat_ctx_clr_stats_input {
4580 * This value indicates what type of request this is. The format for the
4581 * rest of the command is determined by this field.
4586 * This value indicates the what completion ring the request will be
4587 * optionally completed on. If the value is -1, then no CR completion
4588 * will be generated. Any other value must be a valid CR ring_id value
4589 * for this function.
4593 /* This value indicates the command sequence number. */
4597 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
4598 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
4603 * This is the host address where the response will be written when the
4604 * request is complete. This area must be 16B aligned and must be
4605 * cleared to zero before the request is made.
4609 /* ID of the statistics context that is being queried. */
4610 uint32_t stat_ctx_id;
4613 } __attribute__((packed));
4615 /* Output (16 bytes) */
4616 struct hwrm_stat_ctx_clr_stats_output {
4618 * Pass/Fail or error type Note: receiver to verify the in parameters,
4619 * and fail the call with an error when appropriate
4621 uint16_t error_code;
4623 /* This field returns the type of original request. */
4626 /* This field provides original sequence number of the command. */
4630 * This field is the length of the response in bytes. The last byte of
4631 * the response is a valid flag that will read as '1' when the command
4632 * has been completely written to memory.
4642 * This field is used in Output records to indicate that the output is
4643 * completely written to RAM. This field should be read as '1' to
4644 * indicate that the output has been completely written. When writing a
4645 * command completion or response to an internal processor, the order of
4646 * writes has to be such that this field is written last.
4649 } __attribute__((packed));
4651 /* hwrm_stat_ctx_free */
4652 /* Description: This command is used to free a stat context. */
4653 /* Input (24 bytes) */
4655 struct hwrm_stat_ctx_free_input {
4657 * This value indicates what type of request this is. The format for the
4658 * rest of the command is determined by this field.
4663 * This value indicates the what completion ring the request will be
4664 * optionally completed on. If the value is -1, then no CR completion
4665 * will be generated. Any other value must be a valid CR ring_id value
4666 * for this function.
4670 /* This value indicates the command sequence number. */
4674 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
4675 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
4680 * This is the host address where the response will be written when the
4681 * request is complete. This area must be 16B aligned and must be
4682 * cleared to zero before the request is made.
4686 /* ID of the statistics context that is being queried. */
4687 uint32_t stat_ctx_id;
4690 } __attribute__((packed));
4692 /* Output (16 bytes) */
4694 struct hwrm_stat_ctx_free_output {
4696 * Pass/Fail or error type Note: receiver to verify the in parameters,
4697 * and fail the call with an error when appropriate
4699 uint16_t error_code;
4701 /* This field returns the type of original request. */
4704 /* This field provides original sequence number of the command. */
4708 * This field is the length of the response in bytes. The last byte of
4709 * the response is a valid flag that will read as '1' when the command
4710 * has been completely written to memory.
4714 /* This is the statistics context ID value. */
4715 uint32_t stat_ctx_id;
4722 * This field is used in Output records to indicate that the output is
4723 * completely written to RAM. This field should be read as '1' to
4724 * indicate that the output has been completely written. When writing a
4725 * command completion or response to an internal processor, the order of
4726 * writes has to be such that this field is written last.
4729 } __attribute__((packed));
4731 /* hwrm_vnic_alloc */
4733 * Description: This VNIC is a resource in the RX side of the chip that is used
4734 * to represent a virtual host "interface". # At the time of VNIC allocation or
4735 * configuration, the function can specify whether it wants the requested VNIC
4736 * to be the default VNIC for the function or not. # If a function requests
4737 * allocation of a VNIC for the first time and a VNIC is successfully allocated
4738 * by the HWRM, then the HWRM shall make the allocated VNIC as the default VNIC
4739 * for that function. # The default VNIC shall be used for the default action
4740 * for a partition or function. # For each VNIC allocated on a function, a
4741 * mapping on the RX side to map the allocated VNIC to source virtual interface
4742 * shall be performed by the HWRM. This should be hidden to the function driver
4743 * requesting the VNIC allocation. This enables broadcast/multicast replication
4744 * with source knockout. # If multicast replication with source knockout is
4745 * enabled, then the internal VNIC to SVIF mapping data structures shall be
4746 * programmed at the time of VNIC allocation.
4749 /* Input (24 bytes) */
4750 struct hwrm_vnic_alloc_input {
4752 * This value indicates what type of request this is. The format for the
4753 * rest of the command is determined by this field.
4758 * This value indicates the what completion ring the request will be
4759 * optionally completed on. If the value is -1, then no CR completion
4760 * will be generated. Any other value must be a valid CR ring_id value
4761 * for this function.
4765 /* This value indicates the command sequence number. */
4769 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
4770 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
4775 * This is the host address where the response will be written when the
4776 * request is complete. This area must be 16B aligned and must be
4777 * cleared to zero before the request is made.
4782 * When this bit is '1', this VNIC is requested to be the default VNIC
4783 * for this function.
4785 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
4789 } __attribute__((packed));
4791 /* Output (16 bytes) */
4792 struct hwrm_vnic_alloc_output {
4794 * Pass/Fail or error type Note: receiver to verify the in parameters,
4795 * and fail the call with an error when appropriate
4797 uint16_t error_code;
4799 /* This field returns the type of original request. */
4802 /* This field provides original sequence number of the command. */
4806 * This field is the length of the response in bytes. The last byte of
4807 * the response is a valid flag that will read as '1' when the command
4808 * has been completely written to memory.
4812 /* Logical vnic ID */
4820 * This field is used in Output records to indicate that the output is
4821 * completely written to RAM. This field should be read as '1' to
4822 * indicate that the output has been completely written. When writing a
4823 * command completion or response to an internal processor, the order of
4824 * writes has to be such that this field is written last.
4827 } __attribute__((packed));
4830 /* Description: Configure the RX VNIC structure. */
4832 /* Input (40 bytes) */
4833 struct hwrm_vnic_cfg_input {
4835 * This value indicates what type of request this is. The format for the
4836 * rest of the command is determined by this field.
4841 * This value indicates the what completion ring the request will be
4842 * optionally completed on. If the value is -1, then no CR completion
4843 * will be generated. Any other value must be a valid CR ring_id value
4844 * for this function.
4848 /* This value indicates the command sequence number. */
4852 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
4853 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
4858 * This is the host address where the response will be written when the
4859 * request is complete. This area must be 16B aligned and must be
4860 * cleared to zero before the request is made.
4865 * When this bit is '1', the VNIC is requested to be the default VNIC
4868 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
4870 * When this bit is '1', the VNIC is being configured to strip VLAN in
4871 * the RX path. If set to '0', then VLAN stripping is disabled on this
4874 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE UINT32_C(0x2)
4876 * When this bit is '1', the VNIC is being configured to buffer receive
4877 * packets in the hardware until the host posts new receive buffers. If
4878 * set to '0', then bd_stall is being configured to be disabled on this
4881 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE UINT32_C(0x4)
4883 * When this bit is '1', the VNIC is being configured to receive both
4884 * RoCE and non-RoCE traffic. If set to '0', then this VNIC is not
4885 * configured to be operating in dual VNIC mode.
4887 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE UINT32_C(0x8)
4889 * When this flag is set to '1', the VNIC is requested to be configured
4890 * to receive only RoCE traffic. If this flag is set to '0', then this
4891 * flag shall be ignored by the HWRM. If roce_dual_vnic_mode flag is set
4892 * to '1', then the HWRM client shall not set this flag to '1'.
4894 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE UINT32_C(0x10)
4897 /* This bit must be '1' for the dflt_ring_grp field to be configured. */
4898 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP UINT32_C(0x1)
4899 /* This bit must be '1' for the rss_rule field to be configured. */
4900 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE UINT32_C(0x2)
4901 /* This bit must be '1' for the cos_rule field to be configured. */
4902 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE UINT32_C(0x4)
4903 /* This bit must be '1' for the lb_rule field to be configured. */
4904 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE UINT32_C(0x8)
4905 /* This bit must be '1' for the mru field to be configured. */
4906 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU UINT32_C(0x10)
4909 /* Logical vnic ID */
4913 * Default Completion ring for the VNIC. This ring will be chosen if
4914 * packet does not match any RSS rules and if there is no COS rule.
4916 uint16_t dflt_ring_grp;
4919 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if there is no
4925 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if there is no
4931 * RSS ID for load balancing rule/table structure. 0xFF... (All Fs) if
4932 * there is no LB rule.
4937 * The maximum receive unit of the vnic. Each vnic is associated with a
4938 * function. The vnic mru value overwrites the mru setting of the
4939 * associated function. The HWRM shall make sure that vnic mru does not
4940 * exceed the mru of the port the function is associated with.
4945 } __attribute__((packed));
4947 /* Output (16 bytes) */
4948 struct hwrm_vnic_cfg_output {
4950 * Pass/Fail or error type Note: receiver to verify the in parameters,
4951 * and fail the call with an error when appropriate
4953 uint16_t error_code;
4955 /* This field returns the type of original request. */
4958 /* This field provides original sequence number of the command. */
4962 * This field is the length of the response in bytes. The last byte of
4963 * the response is a valid flag that will read as '1' when the command
4964 * has been completely written to memory.
4974 * This field is used in Output records to indicate that the output is
4975 * completely written to RAM. This field should be read as '1' to
4976 * indicate that the output has been completely written. When writing a
4977 * command completion or response to an internal processor, the order of
4978 * writes has to be such that this field is written last.
4981 } __attribute__((packed));
4983 /* hwrm_vnic_free */
4985 * Description: Free a VNIC resource. Idle any resources associated with the
4986 * VNIC as well as the VNIC. Reset and release all resources associated with the
4990 /* Input (24 bytes) */
4991 struct hwrm_vnic_free_input {
4993 * This value indicates what type of request this is. The format for the
4994 * rest of the command is determined by this field.
4999 * This value indicates the what completion ring the request will be
5000 * optionally completed on. If the value is -1, then no CR completion
5001 * will be generated. Any other value must be a valid CR ring_id value
5002 * for this function.
5006 /* This value indicates the command sequence number. */
5010 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
5011 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
5016 * This is the host address where the response will be written when the
5017 * request is complete. This area must be 16B aligned and must be
5018 * cleared to zero before the request is made.
5022 /* Logical vnic ID */
5026 } __attribute__((packed));
5028 /* Output (16 bytes) */
5029 struct hwrm_vnic_free_output {
5031 * Pass/Fail or error type Note: receiver to verify the in parameters,
5032 * and fail the call with an error when appropriate
5034 uint16_t error_code;
5036 /* This field returns the type of original request. */
5039 /* This field provides original sequence number of the command. */
5043 * This field is the length of the response in bytes. The last byte of
5044 * the response is a valid flag that will read as '1' when the command
5045 * has been completely written to memory.
5055 * This field is used in Output records to indicate that the output is
5056 * completely written to RAM. This field should be read as '1' to
5057 * indicate that the output has been completely written. When writing a
5058 * command completion or response to an internal processor, the order of
5059 * writes has to be such that this field is written last.
5062 } __attribute__((packed));
5064 /* hwrm_vnic_rss_cfg */
5065 /* Description: This function is used to enable RSS configuration. */
5067 /* Input (48 bytes) */
5068 struct hwrm_vnic_rss_cfg_input {
5070 * This value indicates what type of request this is. The format for the
5071 * rest of the command is determined by this field.
5076 * This value indicates the what completion ring the request will be
5077 * optionally completed on. If the value is -1, then no CR completion
5078 * will be generated. Any other value must be a valid CR ring_id value
5079 * for this function.
5083 /* This value indicates the command sequence number. */
5087 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
5088 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
5093 * This is the host address where the response will be written when the
5094 * request is complete. This area must be 16B aligned and must be
5095 * cleared to zero before the request is made.
5100 * When this bit is '1', the RSS hash shall be computed over source and
5101 * destination IPv4 addresses of IPv4 packets.
5103 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
5105 * When this bit is '1', the RSS hash shall be computed over
5106 * source/destination IPv4 addresses and source/destination ports of
5109 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
5111 * When this bit is '1', the RSS hash shall be computed over
5112 * source/destination IPv4 addresses and source/destination ports of
5115 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
5117 * When this bit is '1', the RSS hash shall be computed over source and
5118 * destination IPv4 addresses of IPv6 packets.
5120 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
5122 * When this bit is '1', the RSS hash shall be computed over
5123 * source/destination IPv6 addresses and source/destination ports of
5126 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
5128 * When this bit is '1', the RSS hash shall be computed over
5129 * source/destination IPv6 addresses and source/destination ports of
5132 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
5137 /* This is the address for rss ring group table */
5138 uint64_t ring_grp_tbl_addr;
5140 /* This is the address for rss hash key table */
5141 uint64_t hash_key_tbl_addr;
5143 /* Index to the rss indirection table. */
5144 uint16_t rss_ctx_idx;
5146 uint16_t unused_1[3];
5147 } __attribute__((packed));
5149 /* Output (16 bytes) */
5150 struct hwrm_vnic_rss_cfg_output {
5152 * Pass/Fail or error type Note: receiver to verify the in parameters,
5153 * and fail the call with an error when appropriate
5155 uint16_t error_code;
5157 /* This field returns the type of original request. */
5160 /* This field provides original sequence number of the command. */
5164 * This field is the length of the response in bytes. The last byte of
5165 * the response is a valid flag that will read as '1' when the command
5166 * has been completely written to memory.
5176 * This field is used in Output records to indicate that the output is
5177 * completely written to RAM. This field should be read as '1' to
5178 * indicate that the output has been completely written. When writing a
5179 * command completion or response to an internal processor, the order of
5180 * writes has to be such that this field is written last.
5183 } __attribute__((packed));
5185 /* Input (16 bytes) */
5186 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
5188 * This value indicates what type of request this is. The format for the
5189 * rest of the command is determined by this field.
5194 * This value indicates the what completion ring the request will be
5195 * optionally completed on. If the value is -1, then no CR completion
5196 * will be generated. Any other value must be a valid CR ring_id value
5197 * for this function.
5201 /* This value indicates the command sequence number. */
5205 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
5206 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
5211 * This is the host address where the response will be written when the
5212 * request is complete. This area must be 16B aligned and must be
5213 * cleared to zero before the request is made.
5216 } __attribute__((packed));
5218 /* Output (16 bytes) */
5220 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
5222 * Pass/Fail or error type Note: receiver to verify the in parameters,
5223 * and fail the call with an error when appropriate
5225 uint16_t error_code;
5227 /* This field returns the type of original request. */
5230 /* This field provides original sequence number of the command. */
5234 * This field is the length of the response in bytes. The last byte of
5235 * the response is a valid flag that will read as '1' when the command
5236 * has been completely written to memory.
5240 /* rss_cos_lb_ctx_id is 16 b */
5241 uint16_t rss_cos_lb_ctx_id;
5250 * This field is used in Output records to indicate that the output is
5251 * completely written to RAM. This field should be read as '1' to
5252 * indicate that the output has been completely written. When writing a
5253 * command completion or response to an internal processor, the order of
5254 * writes has to be such that this field is written last.
5257 } __attribute__((packed));
5259 /* hwrm_vnic_rss_cos_lb_ctx_free */
5260 /* Description: This function can be used to free COS/Load Balance context. */
5261 /* Input (24 bytes) */
5263 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
5265 * This value indicates what type of request this is. The format for the
5266 * rest of the command is determined by this field.
5271 * This value indicates the what completion ring the request will be
5272 * optionally completed on. If the value is -1, then no CR completion
5273 * will be generated. Any other value must be a valid CR ring_id value
5274 * for this function.
5278 /* This value indicates the command sequence number. */
5282 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
5283 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
5288 * This is the host address where the response will be written when the
5289 * request is complete. This area must be 16B aligned and must be
5290 * cleared to zero before the request is made.
5294 /* rss_cos_lb_ctx_id is 16 b */
5295 uint16_t rss_cos_lb_ctx_id;
5297 uint16_t unused_0[3];
5298 } __attribute__((packed));
5300 /* Output (16 bytes) */
5301 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
5303 * Pass/Fail or error type Note: receiver to verify the in parameters,
5304 * and fail the call with an error when appropriate
5306 uint16_t error_code;
5308 /* This field returns the type of original request. */
5311 /* This field provides original sequence number of the command. */
5315 * This field is the length of the response in bytes. The last byte of
5316 * the response is a valid flag that will read as '1' when the command
5317 * has been completely written to memory.
5327 * This field is used in Output records to indicate that the output is
5328 * completely written to RAM. This field should be read as '1' to
5329 * indicate that the output has been completely written. When writing a
5330 * command completion or response to an internal processor, the order of
5331 * writes has to be such that this field is written last.
5334 } __attribute__((packed));
5336 /* Output (32 bytes) */
5337 struct hwrm_queue_qportcfg_output {
5339 * Pass/Fail or error type Note: receiver to verify the in parameters,
5340 * and fail the call with an error when appropriate
5342 uint16_t error_code;
5344 /* This field returns the type of original request. */
5347 /* This field provides original sequence number of the command. */
5351 * This field is the length of the response in bytes. The last byte of
5352 * the response is a valid flag that will read as '1' when the command
5353 * has been completely written to memory.
5357 /* The maximum number of queues that can be configured. */
5358 uint8_t max_configurable_queues;
5360 /* The maximum number of lossless queues that can be configured. */
5361 uint8_t max_configurable_lossless_queues;
5364 * 0 - Not allowed. Non-zero - Allowed. If this value is non-zero, then
5365 * the HWRM shall allow the host SW driver to configure queues using
5368 uint8_t queue_cfg_allowed;
5371 * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then
5372 * the HWRM shall allow the host SW driver to configure queue buffers
5373 * using hwrm_queue_buffers_cfg.
5375 uint8_t queue_buffers_cfg_allowed;
5378 * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then
5379 * the HWRM shall allow the host SW driver to configure PFC using
5380 * hwrm_queue_pfcenable_cfg.
5382 uint8_t queue_pfcenable_cfg_allowed;
5385 * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then
5386 * the HWRM shall allow the host SW driver to configure Priority to CoS
5387 * mapping using hwrm_queue_pri2cos_cfg.
5389 uint8_t queue_pri2cos_cfg_allowed;
5392 * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then
5393 * the HWRM shall allow the host SW driver to configure CoS Bandwidth
5394 * configuration using hwrm_queue_cos2bw_cfg.
5396 uint8_t queue_cos2bw_cfg_allowed;
5398 /* ID of CoS Queue 0. FF - Invalid id */
5401 /* This value is applicable to CoS queues only. */
5402 /* Lossy (best-effort) */
5403 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
5404 (UINT32_C(0x0) << 0)
5406 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
5407 (UINT32_C(0x1) << 0)
5409 * Set to 0xFF... (All Fs) if there is no service profile
5412 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
5413 (UINT32_C(0xff) << 0)
5414 uint8_t queue_id0_service_profile;
5416 /* ID of CoS Queue 1. FF - Invalid id */
5418 /* This value is applicable to CoS queues only. */
5419 /* Lossy (best-effort) */
5420 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
5421 (UINT32_C(0x0) << 0)
5423 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
5424 (UINT32_C(0x1) << 0)
5426 * Set to 0xFF... (All Fs) if there is no service profile
5429 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
5430 (UINT32_C(0xff) << 0)
5431 uint8_t queue_id1_service_profile;
5433 /* ID of CoS Queue 2. FF - Invalid id */
5435 /* This value is applicable to CoS queues only. */
5436 /* Lossy (best-effort) */
5437 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
5438 (UINT32_C(0x0) << 0)
5440 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
5441 (UINT32_C(0x1) << 0)
5443 * Set to 0xFF... (All Fs) if there is no service profile
5446 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
5447 (UINT32_C(0xff) << 0)
5448 uint8_t queue_id2_service_profile;
5450 /* ID of CoS Queue 3. FF - Invalid id */
5453 /* This value is applicable to CoS queues only. */
5454 /* Lossy (best-effort) */
5455 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
5456 (UINT32_C(0x0) << 0)
5458 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
5459 (UINT32_C(0x1) << 0)
5461 * Set to 0xFF... (All Fs) if there is no service profile
5464 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
5465 (UINT32_C(0xff) << 0)
5466 uint8_t queue_id3_service_profile;
5468 /* ID of CoS Queue 4. FF - Invalid id */
5470 /* This value is applicable to CoS queues only. */
5471 /* Lossy (best-effort) */
5472 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
5473 (UINT32_C(0x0) << 0)
5475 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
5476 (UINT32_C(0x1) << 0)
5478 * Set to 0xFF... (All Fs) if there is no service profile
5481 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
5482 (UINT32_C(0xff) << 0)
5483 uint8_t queue_id4_service_profile;
5485 /* ID of CoS Queue 5. FF - Invalid id */
5488 /* This value is applicable to CoS queues only. */
5489 /* Lossy (best-effort) */
5490 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
5491 (UINT32_C(0x0) << 0)
5493 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
5494 (UINT32_C(0x1) << 0)
5496 * Set to 0xFF... (All Fs) if there is no service profile
5499 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
5500 (UINT32_C(0xff) << 0)
5501 uint8_t queue_id5_service_profile;
5503 /* ID of CoS Queue 6. FF - Invalid id */
5504 uint8_t queue_id6_service_profile;
5505 /* This value is applicable to CoS queues only. */
5506 /* Lossy (best-effort) */
5507 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
5508 (UINT32_C(0x0) << 0)
5510 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
5511 (UINT32_C(0x1) << 0)
5513 * Set to 0xFF... (All Fs) if there is no service profile
5516 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
5517 (UINT32_C(0xff) << 0)
5520 /* ID of CoS Queue 7. FF - Invalid id */
5523 /* This value is applicable to CoS queues only. */
5524 /* Lossy (best-effort) */
5525 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
5526 (UINT32_C(0x0) << 0)
5528 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
5529 (UINT32_C(0x1) << 0)
5531 * Set to 0xFF... (All Fs) if there is no service profile
5534 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
5535 (UINT32_C(0xff) << 0)
5536 uint8_t queue_id7_service_profile;
5539 * This field is used in Output records to indicate that the output is
5540 * completely written to RAM. This field should be read as '1' to
5541 * indicate that the output has been completely written. When writing a
5542 * command completion or response to an internal processor, the order of
5543 * writes has to be such that this field is written last.
5546 } __attribute__((packed));
5548 /* hwrm_func_drv_rgtr */
5550 * Description: This command is used by the function driver to register its
5551 * information with the HWRM. A function driver shall implement this command. A
5552 * function driver shall use this command during the driver initialization right
5553 * after the HWRM version discovery and default ring resources allocation.
5556 /* Input (80 bytes) */
5557 struct hwrm_func_drv_rgtr_input {
5559 * This value indicates what type of request this is. The format for the
5560 * rest of the command is determined by this field.
5565 * This value indicates the what completion ring the request will be
5566 * optionally completed on. If the value is -1, then no CR completion
5567 * will be generated. Any other value must be a valid CR ring_id value
5568 * for this function.
5572 /* This value indicates the command sequence number. */
5576 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
5577 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
5582 * This is the host address where the response will be written when the
5583 * request is complete. This area must be 16B aligned and must be
5584 * cleared to zero before the request is made.
5589 * When this bit is '1', the function driver is requesting all requests
5590 * from its children VF drivers to be forwarded to itself. This flag can
5591 * only be set by the PF driver. If a VF driver sets this flag, it
5592 * should be ignored by the HWRM.
5594 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE UINT32_C(0x1)
5596 * When this bit is '1', the function is requesting none of the requests
5597 * from its children VF drivers to be forwarded to itself. This flag can
5598 * only be set by the PF driver. If a VF driver sets this flag, it
5599 * should be ignored by the HWRM.
5601 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE UINT32_C(0x2)
5604 /* This bit must be '1' for the os_type field to be configured. */
5605 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE UINT32_C(0x1)
5606 /* This bit must be '1' for the ver field to be configured. */
5607 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER UINT32_C(0x2)
5608 /* This bit must be '1' for the timestamp field to be configured. */
5609 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP UINT32_C(0x4)
5610 /* This bit must be '1' for the vf_req_fwd field to be configured. */
5611 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD UINT32_C(0x8)
5613 * This bit must be '1' for the async_event_fwd field to be configured.
5615 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
5619 /* This value indicates the type of OS. */
5621 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN \
5622 (UINT32_C(0x0) << 0)
5623 /* Other OS not listed below. */
5624 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER \
5625 (UINT32_C(0x1) << 0)
5627 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS \
5628 (UINT32_C(0xe) << 0)
5630 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS \
5631 (UINT32_C(0x12) << 0)
5633 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS \
5634 (UINT32_C(0x1d) << 0)
5636 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX \
5637 (UINT32_C(0x24) << 0)
5639 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD \
5640 (UINT32_C(0x2a) << 0)
5641 /* VMware ESXi OS. */
5642 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI \
5643 (UINT32_C(0x68) << 0)
5644 /* Microsoft Windows 8 64-bit OS. */
5645 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 \
5646 (UINT32_C(0x73) << 0)
5647 /* Microsoft Windows Server 2012 R2 OS. */
5648 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 \
5649 (UINT32_C(0x74) << 0)
5652 /* This is the major version of the driver. */
5655 /* This is the minor version of the driver. */
5658 /* This is the update version of the driver. */
5665 * This is a 32-bit timestamp provided by the driver for keep alive. The
5666 * timestamp is in multiples of 1ms.
5673 * This is a 256-bit bit mask provided by the PF driver for letting the
5674 * HWRM know what commands issued by the VF driver to the HWRM should be
5675 * forwarded to the PF driver. Nth bit refers to the Nth req_type.
5676 * Setting Nth bit to 1 indicates that requests from the VF driver with
5677 * req_type equal to N shall be forwarded to the parent PF driver. This
5678 * field is not valid for the VF driver.
5680 uint32_t vf_req_fwd[8];
5683 * This is a 256-bit bit mask provided by the function driver (PF or VF
5684 * driver) to indicate the list of asynchronous event completions to be
5685 * forwarded. Nth bit refers to the Nth event_id. Setting Nth bit to 1
5686 * by the function driver shall result in the HWRM forwarding
5687 * asynchronous event completion with event_id equal to N. If all bits
5688 * are set to 0 (value of 0), then the HWRM shall not forward any
5689 * asynchronous event completion to this function driver.
5691 uint32_t async_event_fwd[8];
5692 } __attribute__((packed));
5694 /* Output (16 bytes) */
5696 struct hwrm_func_drv_rgtr_output {
5698 * Pass/Fail or error type Note: receiver to verify the in parameters,
5699 * and fail the call with an error when appropriate
5701 uint16_t error_code;
5703 /* This field returns the type of original request. */
5706 /* This field provides original sequence number of the command. */
5710 * This field is the length of the response in bytes. The last byte of
5711 * the response is a valid flag that will read as '1' when the command
5712 * has been completely written to memory.
5722 * This field is used in Output records to indicate that the output is
5723 * completely written to RAM. This field should be read as '1' to
5724 * indicate that the output has been completely written. When writing a
5725 * command completion or response to an internal processor, the order of
5726 * writes has to be such that this field is written last.
5729 } __attribute__((packed));
5731 /* hwrm_func_drv_unrgtr */
5733 * Description: This command is used by the function driver to un register with
5734 * the HWRM. A function driver shall implement this command. A function driver
5735 * shall use this command during the driver unloading.
5737 /* Input (24 bytes) */
5739 struct hwrm_func_drv_unrgtr_input {
5741 * This value indicates what type of request this is. The format for the
5742 * rest of the command is determined by this field.
5747 * This value indicates the what completion ring the request will be
5748 * optionally completed on. If the value is -1, then no CR completion
5749 * will be generated. Any other value must be a valid CR ring_id value
5750 * for this function.
5754 /* This value indicates the command sequence number. */
5758 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
5759 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
5764 * This is the host address where the response will be written when the
5765 * request is complete. This area must be 16B aligned and must be
5766 * cleared to zero before the request is made.
5771 * When this bit is '1', the function driver is notifying the HWRM to
5772 * prepare for the shutdown.
5774 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
5779 } __attribute__((packed));
5781 /* Output (16 bytes) */
5782 struct hwrm_func_drv_unrgtr_output {
5784 * Pass/Fail or error type Note: receiver to verify the in parameters,
5785 * and fail the call with an error when appropriate
5787 uint16_t error_code;
5789 /* This field returns the type of original request. */
5792 /* This field provides original sequence number of the command. */
5796 * This field is the length of the response in bytes. The last byte of
5797 * the response is a valid flag that will read as '1' when the command
5798 * has been completely written to memory.
5808 * This field is used in Output records to indicate that the output is
5809 * completely written to RAM. This field should be read as '1' to
5810 * indicate that the output has been completely written. When writing a
5811 * command completion or response to an internal processor, the order of
5812 * writes has to be such that this field is written last.
5815 } __attribute__((packed));
5817 /* hwrm_func_qcfg */
5819 * Description: This command returns the current configuration of a function.
5820 * The input FID value is used to indicate what function is being queried. This
5821 * allows a physical function driver to query virtual functions that are
5822 * children of the physical function. The output FID value is needed to
5823 * configure Rings and MSI-X vectors so their DMA operations appear correctly on
5826 /* Input (24 bytes) */
5827 struct hwrm_func_qcfg_input {
5829 * This value indicates what type of request this is. The format for the
5830 * rest of the command is determined by this field.
5834 * This value indicates the what completion ring the request will be
5835 * optionally completed on. If the value is -1, then no CR completion
5836 * will be generated. Any other value must be a valid CR ring_id value
5837 * for this function.
5840 /* This value indicates the command sequence number. */
5843 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
5844 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
5848 * This is the host address where the response will be written when the
5849 * request is complete. This area must be 16B aligned and must be
5850 * cleared to zero before the request is made.
5854 * Function ID of the function that is being queried. 0xFF... (All Fs)
5855 * if the query is for the requesting function.
5859 uint16_t unused_0[3];
5860 } __attribute__((packed));
5862 /* Output (72 bytes) */
5863 struct hwrm_func_qcfg_output {
5865 * Pass/Fail or error type Note: receiver to verify the in parameters,
5866 * and fail the call with an error when appropriate
5868 uint16_t error_code;
5869 /* This field returns the type of original request. */
5871 /* This field provides original sequence number of the command. */
5874 * This field is the length of the response in bytes. The last byte of
5875 * the response is a valid flag that will read as '1' when the command
5876 * has been completely written to memory.
5880 * FID value. This value is used to identify operations on the PCI bus
5881 * as belonging to a particular PCI function.
5885 * Port ID of port that this function is associated with. 0xFF... (All
5886 * Fs) if this function is not associated with any port.
5890 * This value is the current VLAN setting for this function. The value
5891 * of 0 for this field indicates no priority tagging or VLAN is used.
5892 * This VLAN is in 802.1Q tag format.
5900 * This value is current MAC address configured for this function. A
5901 * value of 00-00-00-00-00-00 indicates no MAC address is currently
5904 uint8_t mac_address[6];
5907 * This value is current PCI ID of this function. If ARI is enabled,
5908 * then it is Bus Number (8b):Function Number(8b). Otherwise, it is Bus
5909 * Number (8b):Device Number (4b):Function Number(4b).
5912 /* The number of RSS/COS contexts currently allocated to the function. */
5913 uint16_t alloc_rsscos_ctx;
5915 * The number of completion rings currently allocated to the function.
5916 * This does not include the rings allocated to any children functions
5919 uint16_t alloc_cmpl_rings;
5921 * The number of transmit rings currently allocated to the function.
5922 * This does not include the rings allocated to any children functions
5925 uint16_t alloc_tx_rings;
5927 * The number of receive rings currently allocated to the function. This
5928 * does not include the rings allocated to any children functions if
5931 uint16_t alloc_rx_rings;
5932 /* The allocated number of L2 contexts to the function. */
5933 uint16_t alloc_l2_ctx;
5934 /* The allocated number of vnics to the function. */
5935 uint16_t alloc_vnics;
5937 * The maximum transmission unit of the function. For rings allocated on
5938 * this function, this default value is used if ring MTU is not
5943 * The maximum receive unit of the function. For vnics allocated on this
5944 * function, this default value is used if vnic MRU is not specified.
5947 /* The statistics context assigned to a function. */
5948 uint16_t stat_ctx_id;
5950 * The HWRM shall return Unknown value for this field when this command
5951 * is used to query VF's configuration.
5953 /* Single physical function */
5954 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF \
5955 (UINT32_C(0x0) << 0)
5956 /* Multiple physical functions */
5957 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS \
5958 (UINT32_C(0x1) << 0)
5959 /* Network Partitioning 1.0 */
5960 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 \
5961 (UINT32_C(0x2) << 0)
5962 /* Network Partitioning 1.5 */
5963 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 \
5964 (UINT32_C(0x3) << 0)
5965 /* Network Partitioning 2.0 */
5966 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 \
5967 (UINT32_C(0x4) << 0)
5969 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
5970 (UINT32_C(0xff) << 0)
5971 uint8_t port_partition_type;
5974 /* The default VNIC ID assigned to a function that is being queried. */
5975 uint16_t dflt_vnic_id;
5980 * Minimum BW allocated for this function in Mbps. The HWRM will
5981 * translate this value into byte counter and time interval used for the
5982 * scheduler inside the device. A value of 0 indicates the minimum
5983 * bandwidth is not configured.
5987 * Maximum BW allocated for this function in Mbps. The HWRM will
5988 * translate this value into byte counter and time interval used for the
5989 * scheduler inside the device. A value of 0 indicates that the maximum
5990 * bandwidth is not configured.
5994 * This value indicates the Edge virtual bridge mode for the domain that
5995 * this function belongs to.
5997 /* No Edge Virtual Bridging (EVB) */
5998 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB (UINT32_C(0x0) << 0)
5999 /* Virtual Ethernet Bridge (VEB) */
6000 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB (UINT32_C(0x1) << 0)
6001 /* Virtual Ethernet Port Aggregator (VEPA) */
6002 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA (UINT32_C(0x2) << 0)
6008 * The number of allocated multicast filters for this function on the RX
6011 uint32_t alloc_mcast_filters;
6012 /* The number of allocated HW ring groups for this function. */
6013 uint32_t alloc_hw_ring_grps;
6019 * This field is used in Output records to indicate that the output is
6020 * completely written to RAM. This field should be read as '1' to
6021 * indicate that the output has been completely written. When writing a
6022 * command completion or response to an internal processor, the order of
6023 * writes has to be such that this field is written last.
6026 } __attribute__((packed));